GENERAL DESCRIPTION z JEDEC standard 3.3V power supply. 2 x 524,288 words by 16 bits, fabricated with z MRS cycle with address key programs

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1 512K x 16Bit x 2Banks Synchronous DRAM M12L16161A FEATURES GENERAL DESCRIPTION z JEDEC standard 3.3V power supply The M12L16161A is 16,777,216 bits synchronous high data rate Dynamic RAM organized as z LVTTL compatible with multiplexed address z Dual banks operation 2 x 524,288 words by 16 bits, fabricated with z MRS cycle with address key programs high performance CMOS technology. Synchronous - CAS Latency (2 & 3 ) design allows precise cycle control with the - Burst Length (1, 2, 4, 8 & full page) use of system clock I/O transactions are possible z - Burst Type (Sequential & Interleave) on every clock cycle. Range of operating frequencies, programmable burst length and pro- All inputs are sampled at the positive going edge of the system clock grammable latencies allow the same device to be z Burst Read Single-bit Write operation useful for a variety of high bandwidth, high z M for masking performance memory system applications. z Auto & self refresh z 32ms refresh period (2K cycle) ORDERING INFORMATION Part NO. MAX Freq. Interface Package M12L16161A-4.3T 233MHz M12L16161A-5T 200MHz M12L16161A-5.5T 183MHz 50 LVTTL M12L16161A-6T 166MHz TSOP(II) M12L16161A-7T 143MHz M12L16161A-8T 125MHz PIN CONFIGURATION (TOP VIEW) VDD 0 1 VSSQ 2 3 VD 4 5 VSSQ 6 7 VD LM WE CAS RAS CS BA A10/AP A0 A1 A2 A3 VDD VSS VSSQ VD VSSQ 9 8 VD N.C/RFU UM CLK CKE N.C A9 A8 A7 A6 A5 A4 VSS 50PIN TSOP(II) (400mil x 825mil) (0.8 mm PIN PITCH) Elite Semiconductor Memory Technology Inc. P.1 Publication Date : Jan. 2000

2 FUNCTIONAL BLOCK DIAGRAM Bank Select Data Input Register I/O Control LWE LM CLK ADD Address Register Row Buffer Refresh Counter Row Decoder 512K x K x 16 Sense AMP Output Buffer i LCKE LRAS LCBR Col. Buffer Column Decoder Latency & Burst Length LRAS LCBR LWE LCAS Programming Register LWCBR LM Timing Register CLK CKE CS RAS CAS WE L(U)M PIN FUNCTION DESCRIPTION Pin Name Input Function CLK System Clock Active on the positive going edge to sample all inputs. CS Disables or enables device operation by masking or enabling all inputs except Chip Select CLK, CKE and L(U)M. CKE Clock Enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. A0 ~ A10/AP BA Address Bank Select Address Row / column addresses are multiplexed on the same pins. Row address : RA0 ~ RA10, column address : CA0 ~ CA7 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row Address Strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column Address Strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write Enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. L(U)M Data Input / Output Mask Makes data output Hi-Z, tshz after the clock and masks the output. Blocks data input when L(U)M active. 0 ~ 15 Data Input / Output Data inputs/outputs are multiplexed on the same pins. VDD/VSS Power Supply/Ground Power and ground for the input buffers and the core logic. Elite Semiconductor Memory Technology Inc. P.2 Publication Date : Jan. 2000

3 VD/VSSQ N.C/RFU Data Output Power/Ground No Connection/ Reserved for Future Use M12L16161A Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device. ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to VSS VIN,VOUT -1.0 ~ 4.6 V Voltage on VDD supply relative to VSS VDD,VD -1.0 ~ 4.6 V Storage temperature TSTG -55 ~ C Power dissipation PD 1 W Short circuit current IOS 50 MA Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA=0 to 70 C ) Parameter Symbol Min Typ Max Unit Note Supply voltage VDD,VD V Input logic high voltage VIH VDD+0.3 V 1 Input logic low voltage VIL V 2 Output logic high voltage VOH V IOH =-2mA Output logic low voltage VOL V IOL = 2mA Input leakage current IIL -5-5 ua 3 Output leakage current IOL -5-5 ua 4 Note : 1.VIH (max) = 4.6V AC for pulse width 10ns acceptable. 2.VIL (min) = -1.5V AC for pulse width 10ns acceptable. 3.Any input 0V VIN VDD+ 0.3V, all other pins are not under test = 0V. 4.Dout is disabled, 0V VOUT VDD. CAPACITANCE (VDD = 3.3V, TA = 25 C, f = 1MHz) Pin Symbol Min Max Unit CLOCK CCLK pf RAS, CAS, WE, CS, CKE, LM, UM CIN pf ADDRESS CADD pf 0 ~15 COUT pf Elite Semiconductor Memory Technology Inc. P.3 Publication Date : Jan. 2000

4 DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70 C VIH(min)/VIL(max)=2.0V/0.8V) Parameter Symbol Test Condition Operating Current (One Bank Active) ICC1 Burst Length = 1 trc trc (min), tcc tcc (min), IOL= 0mA CAS Version Latency Unit Note ma 1 Precharge Standby ICC2P CKE VIL(max), tcc =15ns 2 ma Current in power-down mode ICC2PS CKE VIL(max), CLK VIL(max), tcc = 2 Precharge Standby Current in non powerdown mode ICC2N ICC2NS CKE VIH(min), CS VIH(min), tcc =15ns Input signals are changed one time during 30ns CKE VIH(min), CLK VIL(max), tcc = Input signals are stable Active Standby Current ICC3P CKE VIL(max), tcc =15ns 10 in power-down mode ICC3PS CKE VIL(max), CLK VIL(max), tcc = ma 2 ma ma Active Standby Current in non power-down mode (One Bank Active) Operating Current (Burst Mode) ICC3N ICC3NS ICC4 CKE VIH(min), CS VIH(min), tcc=15ns Input signals are changed one time during 30ns CKE VIH (min), CLK VIL(max), tcc= Input signals are stable 40 ma 10 ma IOL= 0Ma, Page Burst ma 1 All Band Activated, tccd = tccd (min) Refresh Current ICC5 trc trc(min) ma 2 Self Refresh Current ICC6 CKE 0.2V 1 ma Note: 1.Measured with outputs open. Addresses are changed only one time during tcc(min). 2.Refresh period is 32ms. Addresses are changed only one time during tcc(min). Elite Semiconductor Memory Technology Inc. P.4 Publication Date : Jan. 2000

5 AC OPERATING TEST CONDITIONS (VDD=3.3V ± 0.3V,TA= 0 to 70 C ) Parameter Value Unit Input levels (Vih/Vil) 2.4 / 0.4 V Input timing measurement reference level 1.4 V Input rise and fall time tr / tf = 1 / 1 ns Output timing measurement reference level 1.4 V Output load condition See Fig.2 M12L16161A 3.3V Vtt =1.4V 1200 è Output VOH(DC) = 2.4V, IOH = -2mA VOL(DC) = 0.4V, IOL = 2mA Output Z0=50 è 50 è 870 è 30 pf 30 pf (Fig.1) DC Output Load circuit (Fig.2) AC Output Load Circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Symbol Version Unit Note Row active to row active delay trrd(min) ns 1 RAS to CAS delay trcd(min) ns 1 Row precharge time trp(min) ns 1 tras(min) ns 1 Row active time tras(max) 100 us Row cycle time trc(min) ns 1 Last data in to new col. Address delay tcdl(min) 1 CLK 2 Last data in to row precharge trdl(min) 1 CLK 2 Last data in to burst stop tbdl(min) 1 CLK 2 Col. Address to col. Address delay tccd(min) 1 CLK 3 Number of valid output data CAS latency=3 1 CAS latency=2 1 ea 4 Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 4. Minimum delay is required to complete write. 4. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks. Elite Semiconductor Memory Technology Inc. P.5 Publication Date : Jan. 2000

6 AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter Symbol Unit Note Min Max Min Max Min Max Min Max Min Max Min Max CLK cycle time CAS Latency = tcc CAS Latency = ns 1 CLK to valid CAS Latency = tsac output delay CAS Latency = ns 1 Output data hold time toh ns 2 CLK high pulse width tch ns 3 CLK low pulse width tcl ns 3 Input setup time tss ns 3 Input hold time tsh ns 3 CLK to output in Low-Z tslz ns 2 CLK to output CAS Latency = tshz in Hi-Z CAS latency = ns *All AC parameters are measured from half to half. Note: 1.Parameters depend on programmed CAS latency. 2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter. 3.Assumed input rise and fall time (tr & tf)=1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the parameter. Elite Semiconductor Memory Technology Inc. P.6 Publication Date : Jan. 2000

7 FREQUENCY vs. AC PARAMENTER RELATIONAHIP TABLE M12L16161A-4.3T Frequency CAS Latency (Unit: number of clock) trc tras trp trrd trcd tccd tcdl trdl 47.3ns 34.3ns 12.9ns 8.6ns 12.9ns 4.3ns 4.3ns 4.3ns 233MHz(4.3ns) MHz(5.0ns) MHz(5.5ns) MHz(6.0ns) MHz(7.0ns) M12L16161A-5T Frequency CAS Latency (Unit: number of clock) trc tras trp trrd trcd tccd tcdl trdl 55ns 40ns 15ns 10ns 15ns 5ns 5ns 5ns 200MHz(5.0ns) MHz(5.5ns) MHz(6.0ns) MHz(7.0ns) MHz(8.0ns) MHz(9.0ns) M12L16161A-5.5T (Unit: number of clock) CAS Latency trc tras trp trrd trcd tccd tcdl trdl Frequency 60ns 40ns 16ns 11ns 16ns 5.5ns 5.5ns 5.5ns 183MHz(5.5ns) MHz(6.0ns) MHz(7.0ns) MHz(8.0ns) MHz(9.0ns) M12L16161A-6T Frequency CAS Latency (Unit: number of clock) trc tras trp trrd trcd tccd tcdl trdl 60ns 42ns 18ns 12ns 16ns 6ns 6ns 6ns 166MHz(6.0ns) MHz(7.0ns) MHz(8.0ns) MHz(9.0ns) MHz(10.0ns) M12L16161A-7T Frequency CAS Latency (Unit: number of clock) trc tras trp trrd trcd tccd tcdl trdl 62ns 42ns 20ns 14ns 16ns 7ns 7ns 7ns 143MHz(7.0ns) MHz(8.0ns) MHz(9.0ns) MHz(10.0ns) MHz(12.0ns) M12L16161A-8T Frequency CAS Latency (Unit: number of clock) trc tras trp trrd trcd tccd tcdl trdl 68ns 48ns 20ns 16ns 20ns 8ns 8ns 8ns 125MHz(8.0ns) MHz(9.0ns) MHz(10.0ns) MHz(12.0ns) MHz(13.0ns) Elite Semiconductor Memory Technology Inc. P.7 Publication Date : Jan. 2000

8 Mode Register JEDEC Standard Test Set (refresh counter test) x x LTMODE WT BL Burst Read and Single Write (for Write Through Cache) Use in future x x x 1 1 v v v v v v v Vender Specific v =Valid LTMODE WT BL Mode Register Set x =Don t care Burst length Wrap type Bit2-0 WT=0 WT= R R 101 R R 110 R R 111 Full page R 0 Sequential 1 Interleave Mode Register Write Timing Latency mode Bits6-4 CAS Latency 000 R 001 R R 101 R 110 R 111 R Remark R : Reserved CLOCK CKE CS RAS CAS WE A0-A11 Mode Register Write Elite Semiconductor Memory Technology Inc. P.8 Publication Date : Jan. 2000

9 Burst Length and Sequence (Burst of Two) Starting Address (column address A0 binary) Sequential Addressing Sequence (decimal) 0 0,1 0,1 1 1,0 1,0 M12L16161A Interleave Addressing Sequence (decimal) (Burst of Four) Starting Address (column address A1-A0, binary) Sequential Addressing Sequence (decimal) 00 0,1,2,3 0,1,2,3 01 1,2,3,0 1,0,3,2 10 2,3,0,1 2,3,0,1 11 3,0,1,2 3,2,1,0 Interleave Addressing Sequence (decimal) (Burst of Eight) Starting Address (column address A2-A0, binary) Sequential Addressing Sequence (decimal) Interleave Addressing Sequence (decimal) 000 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6, ,2,3,4,5,6,7,0 1,0,3,2,5,4,7, ,3,4,5,6,7,0,1 2,3,0,1,6,7,4, ,4,5,6,7,0,1,2 3,2,1,0,7,6,5, ,5,6,7,0,1,2,3 4,5,6,7,0,1,2, ,6,7,0,1,2,3,4 5,4,7,6,1,0,3, ,7,0,1,2,3,4,5 6,7,4,5,2,3,0, ,0,1,2,3,4,5,6 7,6,5,4,3,2,1,0 Full page burst is an extension of the above tables of Sequential Addressing, with the length being 256 for 1Mx16 divice. POWER UP SEQUENCE 1.Apply power and start clock, attempt to maintain CKE= H, L(U)M = H and the other pin are NOP condition at the inputs. 2.Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 3.Issue precharge commands for all banks of the devices. 4.Issue 2 or more auto-refresh commands. 5.Issue mode register set command to initialize the mode register. Cf.)Sequence of 4 & 5 is regardless of the order. Elite Semiconductor Memory Technology Inc. P.9 Publication Date : Jan. 2000

10 SIMPLIFIED TRUTH TABLE COMMAND CKEn-1 CKEn CS RAS CAS WE M BA A10/AP A9~A0 Note Register Mode Register Set H X L L L L X OP CODE 1,2 Auto Refresh H 3 H L L L H X X Entry L 3 Refresh Self Refresh L H H H 3 Exit L H X X H X X X 3 Bank Active & Row Addr. H X L L H H X V Row Address Read & Auto Precharge Disable H X L H L H X V L Column 4 Column Address Auto Precharge Enable H Write & Column Auto Precharge Disable H X L H L L X V L Column 4 Address Auto Precharge Enable H Burst Stop H X L H H L X X 6 Precharge Bank Selection V L 4 H X L L H L X X Both Banks X H 4 H X X X Clock Suspend or Entry H L X L V V V Active Power Down Exit L H X X X X X X H X X X Entry H L X Precharge Power Down Mode L H H H H X X X Exit L H X L V V V X M H X V X 7 No Operation Command H H X X X X H L H H H X X (V= Valid, X= Don t Care, H= Logic High, L = Logic Low) Address (A0~A7) 4,5 Address (A0~A7) 4,5 Note:1 OP Code: Operation Code A0~ A10/AP, BA: Program keys.(@mrs) 2. MRS can be issued only at both banks precharge state. A new command can be issued after 2 clock cycle of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by Auto. Auto / self refresh can be issued only at both banks precharge state. 4. BA: Bank select address. If Low : at read, write, row active and precharge, bank A is selected. If High : at read, write, row active and precharge, bank B is selected. If A10/AP is High at row precharge, BA ignored and both banks are selected. 5.During burst read or write with auto precharge, new read/write command can not be issued. Another bank read /write command can be issued after the end of burst. New row active of the associated bank can be issued at trp after the end of burst. 6.Burst stop command is valid at every burst length. 7.M sampled at positive going edge of a CLK masks the data-in at the very CLK (Write M latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read M latency is 2) Elite Semiconductor Memory Technology Inc. P.10 Publication Date : Jan. 2000

11 Single Bit Read-Write-Read Cycle (Same Latency=3, Burst Length=1 C L O C K t C H t C L C K E t C C t R A S H IG H *Note1 t R C t S H C S t R C D t R P t S H t S S R A S t S S t S H t C C D C A S t S H t S S t S S A D D R R a C a C b C c R b t S S t S H B A *Note2 *Note2,3 *Note2,3 *Note2,3 *Note4 *Note2 B S B S B S B S B S B S A 1 0 / A P R a *Note 3 *Note 3 *Note 3 *Note4 R b t R A C t S A C t S H Q a Db Qc W E t S L Z t O H t S H t S S t S S M t S S t S H R o w A c t i v e R e a d W r i t e R e a d P r e c h a r g e R o w A c t i v e : D o n ' t C a r e Elite Semiconductor Memory Technology Inc. P.11 Publication Date : Jan. 2000

12 *Note: 1. All inputs expect CKE & M can be don t care when CS is high at the CLK high going edge. 2. Bank active & read/write are controlled by BA. BA Active & Read/Write 0 Bank A 1 Bank B 3.Enable and disable auto precharge function are controlled by A10/AP in read/write command. A10/AP BA Operation 0 Disable auto precharge, leave bank A active at end of burst. 0 1 Disable auto precharge, leave bank B active at end of burst. 0 Enable auto precharge, precharge bank A at end of burst. 1 1 Enable auto precharge, precharge bank B at end of burst. 4.A10/AP and BA control bank precharge when precharge command is asserted. A10/AP BA precharge 0 0 Bank A 0 1 Bank B 1 X Both Banks Elite Semiconductor Memory Technology Inc. P.12 Publication Date : Jan. 2000

13 Power Up Sequence C L O C K C K E H i g h l e v e l i s n e c e s s a r y CS t R P t R C t R C RAS CAS A D D R K e y R A a BA K e y A 1 0 / A P K e y R A a H i g h - Z WE M H i g h l e v e l i s n e c e s s a r y P r e c h a r g e A l l B a n k s A u t o R e f r e s h A u t o R e f r e s h M o d e R e g i s t e r S e t ( A - B a n k ) R o w A c t i v e : D o n ' t c a r e Elite Semiconductor Memory Technology Inc. P.13 Publication Date : Jan. 2000

14 Read & Write Cycle at Same Length = 4 CLOCK C K E HIGH t RC *Note1 CS t RCD RAS *Note2 CAS ADDR R a Ca 0 R b C b 0 BA A10/AP R a R b QC CL=2 trac *Note3 t OH Q a 0 Q a 1 Q a 2 Q a 3 D b 0 D b 1 D b 2 D b 3 t SAC t O H t S HZ *Note4 t R DL C L=3 t RAC *Note3 Q a 0 Q a 1 Q a 2 Q a 3 D b 0 D b 1 D b 2 D b 3 t SAC ts H Z *Note4 t R DL WE M R ead Precharge Write Prec ha rge : Don't care *Note: 1.Minimum row cycle times is required to complete internal DRAM operation. 2.Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clock. 3.Access time from Row active command. tcc*(trcd +CAS latency-1)+tsac 4.Ouput will be Hi-Z after the end of burst.(1,2,4,8 bit burst) Burst can t end in Full Page Mode. Elite Semiconductor Memory Technology Inc. P.14 Publication Date : Jan. 2000

15 Page Read & Write Cycle at Same Burst Length=4 CLOCK CKE HIGH CS t RCD RAS *Note2 CAS ADDR Ra Ca0 Cb0 Cc0 Cd0 BA A10/AP Ra t RDL CL=2 Qa0 Qa1 Qb0 Qb1 Qb2 Dc0 Dc1 Dd0 Dd1 CL=3 Qa0 Qa1 Qb1 Qb2 Dc0 Dc1 Dd0 Dd2 t CDL WE *Note3 M *Note1 Read Read Write Write Precharge : Don't care *Note :1.To write data before burst read ends, M should be asserted three cycle prior to write command to avoid bus contention. 2.Row precharge will interrupt writing. Last data input, trdl before Row precharge, will be written. 3.M should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. Elite Semiconductor Memory Technology Inc. P.15 Publication Date : Jan. 2000

16 Page Read Cycle at Different Burst Length=4 CLOCK CKE HIGH CS *Note1 RAS *Note2 CAS ADDR RAa CAa RBb CBb CAc CBd CAe BA A10/AP RAa RBb CL=2 QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 CL=3 QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 WE M Read Read (B-Bank) Read Read (B-Bank) Read Precharge (B-Bank) : Don't care *Note: 1. CS can be don t cared when RAS, CAS and WE are high at the clock high going dege. 2.To interrupt a burst read by row precharge, both the read and the precharge banks must be the same. Elite Semiconductor Memory Technology Inc. P.16 Publication Date : Jan. 2000

17 Page Write Cycle at Different Length = 4 CLOCK CKE HIGH CS RAS CAS *Note2 ADDR RAa CAa RBb CBb CAc CBd BA A10/AP RAa RBb DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 DBd1 tcdl trdl WE *Note1 M (B-Bank) Write Write (B-Bank) Write Write (B-Bank) Precharge (Both Banks) : Don't care *Note: 1.To interrupt burst write by Row precharge, M should be asserted to mask invalid input data. 2.To interrupt burst write by row precharge, both the write and the precharge banks must be the same. Elite Semiconductor Memory Technology Inc. P.17 Publication Date : Jan. 2000

18 Read & Write Cycle at Different Burst Length = 4 CLOCK CKE HIGH CS RAS CAS ADDR RAa CAa RBb CBb RAc CAc BA A10/AP RAa RBb RAc *Note1 tcdl CL=2 QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3 QAc0 QAc1 QAc2 CL=3 QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3 QAc0 QAc1 WE M Read Precharge Write (B-Bank) Read (B-Bank) : D o n ' t C a r e *Note: 1.tCDL should be met to complete write. Elite Semiconductor Memory Technology Inc. P.18 Publication Date : Jan. 2000

19 Read & Write Cycle with auto Burst Length =4 C L O C K C K E H IG H C S R A S C A S A D D R R a R b C a C b B A A 1 0 / A P R a R b C L = 2 Q a 0 Q a 1 Q a 2 Q a 3 D b 0 D b 1 D b 2 D b 3 C L = 3 Q a 0 Q a 1 Q a 2 Q a 3 D b 0 D b 1 D b 2 D b 3 W E M ( A - Bank ) Read with Auto Precharge ( A - Bank ) ( B - Bank ) CL= 2 Auto Precharge Start Point ( A - Bank) CL= 3 Auto Precharge Start Point ( A - Bank) W r i t e w i t h A u t o P r e c h a r g e ( B - B a n k ) A u t o P r e c h a r g e S t a r t P o i n t ( B - B a n k ) : D o n ' t C a r e *Note: 1.tCDL Should be controlled to meet minimum tras before internal precharge start (In the case of Burst Length=1 & 2 and BRSW mode) Elite Semiconductor Memory Technology Inc. P.19 Publication Date : Jan. 2000

20 Clock Suspension & M Operation Latency=2, Burst Length= C L O C K C K E C S R A S C A S A D D R R a C a C b C c B A A 1 0 / A P R a Q a 0 Q a 1 Q a 2 Q a 3 Q b 0 Q b 1 D c 0 Dc 2 t S H Z t S H Z W E * N o t e 1 M R o w A c t i v e R e a d C l o c k S u s p en s i o n R e a d W r i t e M W r i t e M R e a d D Q M W r i t e C l o c k S u s p en s i o n : D o n ' t C a r e *Note:1.M is needed to prevent bus contention. Elite Semiconductor Memory Technology Inc. P.20 Publication Date : Jan. 2000

21 Read Interrupted by Precharge Command & Read Burst Stop Length =Full page CLOCK CKE HIGH CS RAS CAS ADDR RAa CAa CAb BA A10/AP RAa CL=2 *Note2 1 1 Q A a 0 Q A a 1 Q A a 2 Q A a 3 Q A a 4 Q A b 0 Q A b 1 QA b 2 QA b 3 QA b 4 Q A b 5 CL=3 2 2 Q A a 0 Q A a 1 Q A a 2 Q A a 3 Q A a 4 Q A b 0 Q A b 1 QA b 2 Q A b 3 Q A b 4 Q A b 5 WE *Note1 M Read Burst Stop Read Precharge :Don't Care *Note: 1.Burst can t end in full page mode, so auto precharge can t issue. 2.About the valid s after burst stop, it is same as the case of RAS interrupt. Both cases are illustrated above timing diagram. See the label 1,2 on them. But at burst write, burst stop and RAS interrupt should be compared carefully. Refer the timing diagram of Full page write burst stop cycle. 3.Burst stop is valid at every burst length. Elite Semiconductor Memory Technology Inc. P.21 Publication Date : Jan. 2000

22 Write Interrupted by Precharge Command & Write Burst stop Burst Length =Full page CLOCK CKE HIGH CS RAS CAS ADDR RAa CAa CAb BA A10/AP RAa t BDL t RDL *Note2 DAa0 DAa1 DAa2 DAa3 DAa4 DAb0 DAb1 DAb2 DAb3 DAb4 DAb5 WE M Write Burst Stop Write Precharge :Don't Care *Note: 1. Burst can t end in full page mode, so auto precharge can t issue. 2.Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of trdl. M at write interrupted by precharge command is needed to prevent invalid write. Input data after Row precharge cycle will be masked internally. 3.Burst stop is valid at every burst length. Elite Semiconductor Memory Technology Inc. P.22 Publication Date : Jan. 2000

23 Burst Read Single bit Write Length=2 C L O C K C K E * N o t e 1 H IG H C S R A S C A S * N o t e 2 A D D R R A a C A a R B b C A b R A c C B c C A d B A A 1 0 / A P R A a R B b R A c C L = 2 D A a 0 QA b 0 Q A b 1 D B c 0 Q A d 0 QA d 1 C L = 3 D A a 0 Q A b 0 Q A b 1 D B c 0 QA d 0 Q A d 1 W E M R o w A c t i v e ( A - B a n k ) (B-Bank) R o w A c t i v e ( A - B a n k ) R e a d ( A - B a n k ) P r e c h a r g e ( A - B a n k ) W r i t e ( A - B a n k ) Read with Auto Precharge W r i t e w i t h A u t o P r e c h a r g e ( B - B a n k ) : D o n ' t C a r e *Note:1.BRSW modes is enabled by setting A9 High at MRS(Mode Register Set). At the BRSW Mode, the burst length at write is fixed to 1 regardless of programmed burst length. 2.When BRSW write command with auto precharge is executed, keep it in mind that tras should not be violated. Auto precharge is executed at the next cycle of burst-end, so in the case of BRSW write command, the precharge command will be issued after two clock cycles. Elite Semiconductor Memory Technology Inc. P.23 Publication Date : Jan. 2000

24 Active/Precharge Power Down Latency=2, Burst Length=4 M12L16161A C L O C K C K E t S S * N o t e 1 * N o t e 2 t S S t S S C S * N o t e 3 R A S C A S A D D R R a C a B A A 1 0 / A P R a t S H Z Q a 0 Q a 1 Q a 2 W E M P r e c h a r g e P o w e r - D o w n E n t r y Precharge Power-Down Exit Active Power-down Entry Read Active Power-down Exit P r e c h a r g e : D o n ' t c a r e *Note :1.Both banks should be in idle state prior to entering precharge power down mode. 2.CKE should be set high at least 1CLK+tss prior to Row active command. 3.Can not violate minimum refresh specification. (32ms) Elite Semiconductor Memory Technology Inc. P.24 Publication Date : Jan. 2000

25 t R C m i n * N o t e 6 M12L16161A Self Refresh Entry & Exit Cycle C L O C K * N o t e 2 * N o t e 4 C K E * N o t e 1 *Note3 t S S C S * N o t e 5 R A S * N o t e 7 CA S A D D R B A A 1 0 / A P Hi - Z Hi - Z W E M S e l f R e f r e s h E n t r y S e l f R e f r e s h E x i t A u t o R e f r e s h : D o n ' t c a r e *Note: TO ENTER SELF REFRESH MODE 1. CS, RAS & CAS with CKE should be low at the same clock cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don t care except for CKE. 3. The device remains in self refresh mode as long as CKE stays Low. cf.) Once the device enters self refresh mode, minimum tras is required before exit from self refresh. TO EXIT SELF REFRESH MODE 4. System clock restart and be stable before returning CKE high. 5. CS Starts from high. 6. Minimum trc is required after CKE going high to complete self refresh exit. 7.2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh. Elite Semiconductor Memory Technology Inc. P.25 Publication Date : Jan. 2000

26 Mode Register Set Cycle Auto Refresh Cycle C L O C K C K E H IG H H I G H C S * N o t e 2 t R F C R A S * N o t e 1 CA S A D D R * N o t e 3 Key R a H i - Z H i- Z W E D QM MR S N e w C o m m a n d A u t o R e f r e s h N e w C o m m a n d : D o n ' t C a r e *Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle. MODE REGISTER SET CYCLE *Note: 1. CS, RAS, CAS & WE activation at the same clock cycle with address key will set internal mode register. 2.Minimum 2 clock cycles should be met before new RAS activation. 3.Please refer to Mode Register Set table. Elite Semiconductor Memory Technology Inc. P.26 Publication Date : Jan. 2000

27 2.91 M12L16161A PACKAGE DIMENSIONS 50-LEAD TSOP(II) SDRAM(400mil) D H- A A2 DETAIL A O 2 (4X) O1.5 E1 E REF 0.21 REF R 1 B R 2 -C- A1 O 3 (4X) GAGE.25 O PLANE C- DETAIL A O 1 L B L 1 (ZD) WITH PLATING b BASE METAL c 1 c SECTION B-B -C- e b 0.10 C b 1 SEATING PLANE Symbol Dimension in mm Dimension in inch Min Nom Max Min Nom Max A A A b b c c D ZD REF REF E E L L REF REF 0.80 BSC BSC R R ð ð² ð³ ð Elite Semiconductor Memory Technology Inc. P.27 Publication Date : Jan. 2000