White Electronic Designs

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1 查询 WS1M32-25HSCA 供应商 White Electronic Designs 捷多邦, 专业 PCB 打样工厂,24 小时加急 出货 1Mx32 SRAM MODULE FEATURES Access Times of 17, 20, 25ns Packaging 4 lead, 2mm CQFP, (Package 511) 66 pin PGA Type, 1 35" sq, Hermetic Ceramic HIP (Package 402)* Organized as two banks of 512Kx32, User Configurable as 2Mx16 or 4Mx * Package to be developed Commercial, Industrial and Military Temperature Ranges TTL Compatible Inputs and Outputs 5 Volt Power Supply Low Power CMOS Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation Weight WS1M32-XH2X* - 13 grams (typical) WS1M32-XG3X - 20 grams (typical) PIN CONFIGURATION FOR WS1M32-XH2X* TOP VIEW I/O I/O9 I/O10 A13 A14 A15 WE2 OE2 I/O11 A10 A11 I/O15 I/O14 I/O13 I/O12 OE1 A1 I/O24 I/O25 I/O26 A6 A7 CS2 OE4 WE4 I/O27 A3 A4 I/O31 I/O30 I/O29 I/O2 A0 A1 PIN DESCRIPTION I/O0-31 Data Inputs/Outputs A0-1 Address Inputs WE1-4 Write Enables CS1-2 Chip Selects OE1-4 Output Enable Power Supply Ground Not Connected A16 A17 A12 WE1 I/O7 A A9 A5 WE3 A2 I/O23 BLOCK DIAGRAM I/O0 CS1 I/O6 I/O16 OE3 I/O22 OE1 WE1 OE2 WE2 OE3 WE3 OE4 WE4 I/O1 I/O5 I/O17 I/O21 CS1 A 0-1 I/O2 I/O3 I/O4 I/O1 I/O19 I/O K 2M x x 512K x 512K 2M x x 512K x 512K 2M x x 512K 2M x 512K x 512K x CS2 I/O0-7 I/O-15 I/O16-23 I/O24-31 NOTE: CS1& CS2 are used as bank select

2 PIN CONFIGURATION FOR WS1M32-XG3X TOP VIEW PIN DESCRIPTION I/O31 I/O30 I/O29 I/O2 I/O27 I/O26 I/O25 I/O24 I/O23 I/O22 I/O21 I/O20 I/O19 I/O1 I/O17 I/O16 I/O0-31 Data Inputs/Outputs A0-1 Address Inputs WE1-4 Write Enables A0 A1 A2 A3 A4 A5 A6 OE1 OE2 OE3 OE4 A7 A A9 A10 A11 A12 A WE4 WE3 WE2 WE1 A1 A17 A16 A15 A14 CS1 A 0-1 OE1 WE1 512K 2M x x 512K x BLOCK DIAGRAM OE2 WE2 CS1-2 OE K 2M x x 512K x OE3 WE3 Chip Selects Output Enables Power Supply Ground Not Connected 512K 2M x x 512K 2M x OE4 WE4 512K x 512K x I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CS1 CS2 I/O I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CS2 I/O0-7 I/O-15 I/O16-23 I/O24-31 NOTE: CS1& CS2 are used as bank select 1.146" The WEDC 4 lead G3 CQFP fills the same fit and function as the JEDEC 4 lead CQFJ or 4 PLCC But the G3 has the TCE and lead inspection advantage of the CQFP form

3 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min Max Unit Operating Temperature TA C Storage Temperature TSTG C Signal Voltage Relative to VG -0 5 Vcc V Junction Temperature T J 150 C Supply Voltage V RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Max Unit Supply Voltage V Input High Voltage VIH V Input Low Voltage VIL V Operating Temp (Mil) TA C Operating Temp (Ind ) TA C CAPACITAE (TA = +25 C) Parameter Symbol Conditions Max Unit OE1-4 capacitance COE VIN = 0 V, f = 1 0 MHz 30 pf WE1-4 capacitance CWE VIN = 0 V, f = 1 0 MHz 30 pf CS1-2 capacitance CCS VIN = 0 V, f = 1 0 MHz 30 pf Data I/O capacitance CI/O VI/O = 0 V, f = 1 0 MHz 30 pf Address input capacitance CAD VIN = 0 V, f = 1 0 MHz 75 pf This parameter is guaranteed by design but not tested TRUTH TABLE CS1 CS2 OE WE Mode Data I/O Power H H X X Standby High Z Standby L H L H Read Data Out Active L H H H Out Disable High Z Active L H X L Write Data In Active H L L H Read Data Out Active H L H H Out Disable High Z Active H L X L Write Data In Active L L X X Invalid State Invalid State Invalid State DC CHARACTERISTICS ( = 5 0V, = 0V, TA = -55 C to +125 C) Parameter Symbol Conditions Units Min Max Input Leakage Current ILI = 5 5, VIN = to 10 µa Output Leakage Current ILO CS = VIH, OE = VIH, VOUT = to 10 µa Operating Supply Current x 32 Mode ICC x 32 CS = VIL, OE = VIH, f = 5MHz, Vcc = ma Standby Current ISB CS = VIH, OE = VIH, f = 5MHz, Vcc = ma Output Low Voltage VOL IOL = ma, Vcc = V Output High Voltage VOH IOH = -4 0mA, Vcc = V NOTE: DC test conditions: VIH = -0 3V, VIL = 0 3V

4 AC CHARACTERISTICS (= 5 0V, = 0V, TA= -55 C to +125 C) Parameter Symbol Units Read Cycle Min Max Min Max Min Max Read Cycle Time trc ns Address Access Time taa ns Output Hold from Address Change toh ns Chip Select Access Time tacs ns Output Enable to Output Valid toe ns Chip Select to Output in Low Z tclz ns Output Enable to Output in Low Z tolz ns Chip Disable to Output in High Z tchz ns Output Disable to Output in High Z tohz ns 1 This parameter is guaranteed by design but not tested AC CHARACTERISTICS (= 5 0V, = 0V, TA= -55 C to +125 C) Parameter Symbol Units Write Cycle Min Max Min Max Min Max Write Cycle Time twc ns Chip Select to End of Write tcw ns Address Valid to End of Write taw ns Data Valid to End of Write tdw ns Write Pulse Width twp ns Address Setup Time tas ns Address Hold Time tah ns Output Active from End of Write tow ns Write Enable to Output in High Z twhz ns Data Hold Time tdh ns 1 This parameter is guaranteed by design but not tested AC TEST CIRCUIT AC TEST CONDITIONS Current Source D.U.T. C eff = 50 pf Current Source I OL I OH V Z 1.5V (Bipolar Supply) Parameter Typ Unit Input Pulse Levels VIL = 0, VIH = 3 0 V Input Rise and Fall 5 ns Input and Output Reference Level 1 5 V Output Timing Reference Level 1 5 V NOTES: VZ is programmable from -2V to +7V IOL & IOH programmable from 0 to 16mA Tester Impedance Z0 = 75W VZ is typically the midpoint of VOH and VOL IOL & IOH are adjusted to simulate a typical resistive load circuit ATE tester includes jig capacitance

5 TIMING WAVEFORM - READ CYCLE ADDRESS t RC t AA CS ADDRESS t RC t AA OE t ACS t CLZ t CHZ DATA I/O t OH PREVIOUS DATA VALID DATA VALID DATA I/O t OE t OLZ HIGH IMPEDAE DATA VALID t OHZ READ CYCLE 1 (CS = OE = V IL, WE = V IH ) READ CYCLE 2 (WE = V IH ) WRITE CYCLE - WE CONTROLLED t WC ADDRESS t AW t CW t AH CS t AS t WP WE t OW t WHZ t DW t DH DATA I/O DATA VALID WRITE CYCLE 1, WE CONTROLLED WRITE CYCLE - CS CONTROLLED ADDRESS t WC WS32K32-XHX t AW t AS tcw t AH CS t WP WE t DW t DH DATA I/O DATA VALID WRITE CYCLE 2, CS CONTROLLED

6 PACKAGE 402: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H2) 35.2 (1.35) ± 0.3 (0.015) SQ PIN 1 IDENTIFIER SQUARE PAD ON BOTTOM 25.4 (1.0) TYP 5.7 (0.223) MAX 3.1 (0.150) ± 0.1 (0.005) 1.27 (0.050) ± 0.1 (0.005) 0.76 (0.030) ± 0.1 (0.005) 2.54 (0.100) TYP (0.600) TYP 25.4 (1.0) TYP 1.27 (0.050) TYP DIA 0.46 (0.01) ± 0.05 (0.002) DIA ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN IHES

7 PACKAGE 511: 4 LEAD, CERAMIC QUAD FLAT PACK (G3) (1.190) ± 0.25 (0.010) SQ 27.1 (1.070) ± 0.25 (0.010) SQ 4.29 (0.169) ± 0.2 (0.011) 4.12 (0.162) ± 0.20 (0.00) Pin (0.010) ± 0.03 (0.002) R (0.005) MIN (1.146) ± 0.25 (0.010) 1 / (0.00) ± 0.06 (0.003) 1.02 (0.040) ± 0.12 (0.005) DETAIL A 1.27 (0.050) TYP 0.3 (0.015) ± 0.05 (0.002) (1.000) TYP 0.27 (0.011) ± 0.04 (0.001) SEE DETAIL "A" 1.146" The WEDC 4 lead G3 CQFP fills the same fit and function as the JEDEC 4 lead CQFJ or 4 PLCC But the G3 has the TCE and lead inspection advantage of the CQFP form ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN IHES

8 ORDERING INFORMATION W S 1M32 - XX X X X LEAD FINISH: Blank = Gold plated leads A = Solder dip leads DEVICE GRADE: M = Military Screened I = Industrial C = Commercial -55 C to +125 C -40 C to +5 C 0 C to +70 C PACKAGE TYPE: H2 = Ceramic Hex-In-line Package, HIP (Package 402)* G3 = 2 mm Ceramic Quad Flatpack, CQFP (Package 511) ACCESS TIME (ns) ORGANIZATION, two banks of 512Kx32 User configurable as 2Mx16 or 4Mx SRAM WHITE ELECTRONIC DESIGNS CORP * Package to be developed

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