Standard Products UT54ACS273/UT54ACTS273 Octal D-Flip-Flops with Clear. Datasheet December 16, 2011
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1 Standard Products UT54AS273/UT54ATS273 Octal -Flip-Flops with lear atasheet ecember 16, FEATUES ontains eight flip-flops with single-rail outputs Buffered clock and direct clear inputs Individual data input to each flip-flop Applications include: - Buffer/storage registers, shift registers, and pattern generators MOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 20-pin IP - 20-lead flatpack UT54AS273 - SM UT54ATS273 - SM ESIPTION The UT54AS273 and the UT54ATS273 are positive-edgetriggered -type flip-flops with a direct clear input. Information at the inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. When the clock input is at either the high or low level, the input signal has no effect at the output. The devices are characterized over full military temperature range of -55 to FUNTION TABLE PINOUTS L 1Q 1 2 2Q 3Q 3 4 4Q V SS LOGI SYMBOL L 1Q 1 2 2Q 3Q 3 4 4Q V SS 20-Pin IP Top View Lead Flatpack Top View V 8Q 8 7 7Q 6Q 6 5 5Q LK V 8Q 8 7 7Q 6Q 6 5 5Q LK INPUTS OUTPUTS L LK x Q x L X X L H H H L H L X H L No change (1) L (11) LK (3) 1 (4) 2 (7) 3 (8) 4 (13) 5 (14) 6 (17) 7 (18) (2) 1Q (5) 2Q (6) 3Q (9) 4Q (12) 5Q (15) 6Q (16) 7Q (19) 8Q 1 Note: 1. Logic symbol in accordance with ANSI/IEEE standard and IE Publication
2 2 LOGI IAGAM 1 (3) 1Q (2) 2 (4) 2Q (5) 3 (7) 3Q (6) 4 (8) 4Q (9) 5 (13) 5Q (12) 6 (14) 6Q (15) 7 (17) 7Q (16) 8 (18) 8Q (19) (11) (1) L LK
3 OPEATIONAL ENVIONMENT 1 PAAMETE LIMIT UNITS Total ose 1.0E6 rads(si) SEU Threshold 2 80 MeV-cm 2 /mg SEL Threshold 120 MeV-cm 2 /mg Neutron Fluence 1.0E14 n/cm 2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. evice storage elements are immune to SEU affects. ABSOLUTE MAXIMUM ATINGS SYMBOL PAAMETE LIMIT UNITS V Supply voltage -0.3 to 7.0 V V I/O Voltage any pin -.3 to V +.3 V T STG Storage Temperature range -65 to +150 T J Maximum junction temperature +175 T LS Lead temperature (soldering 5 seconds) +300 J Thermal resistance junction to case 20 /W I I input current 10 ma P Maximum power dissipation 1 W Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. EOMMENE OPEATING ONITIONS SYMBOL PAAMETE LIMIT UNITS V Supply voltage 4.5 to 5.5 V V IN Input voltage any pin 0 to V V T Temperature range -55 to
4 ELETIAL HAATEISTIS 7 (V = 5.0V 10%; V SS = 0V 6, -55 < T < +125 ); Unless otherwise noted, Tc is per the temperature range ordered. SYMBOL PAAMETE ONITION MIN MAX UNIT V IL Low-level input voltage 1 ATS AS V IH High-level input voltage 1 ATS AS 0.8 V.3V.5V V.7V I IN Input leakage current ATS/AS V IN = V or V SS -1 1 A V OL Low-level output voltage 3 ATS AS I OL = 8.0mA I OL = 100 A V V OH High-level output voltage 3 ATS AS I OH = -8.0mA I OH = -100 A.7V V V I OS Short-circuit output current 2,4 ATS/AS V O = V and V SS ma I OL Output current 10 (Sink) V IN = V or V SS V OL = 0.4V 8 ma I OH Output current 10 (Source) V IN = V or V SS V OH = V - 0.4V -8 ma P total Power dissipation 2, 8, 9 L = 50pF 1.9 mw/ MHz I Q Quiescent Supply urrent V = 5.5V 10 A I Q Quiescent Supply urrent elta ATS For input under test V IN = V - 2.1V 1.6 ma For all other inputs V IN = V or V SS V = 5.5V IN Input capacitance 5 = 0V 15 pf OUT Output capacitance 5 = 0V 15 pf 4
5 Notes: 1. Functional tests are conducted in accordance with MIL-ST-883 with the following input test conditions: V IH = V IH (min) + 20%, - 0%; V IL = V IL (max) + 0%, - 50%, as specified herein, for TTL, MOS, or Schmitt compatible inputs. evices may be tested using any input voltage within the above specified range, but are guaranteed to V IH (min) and V IL (max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PF-38535, for current density 5.0E5 amps/cm 2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. apacitance measured for initial qualification and when design changes may affect the value. apacitance is measured between the designated terminal and V SS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 5
6 A ELETIAL HAATEISTIS 2 (V = 5.0V 10%; V SS = 0V 6, -55 < T < +125 ); Unless otherwise noted, Tc is per the temperature range ordered. SYMBOL PAAMETE MINIMUM MAXIMUM UNIT t PLH LK to Q 4 17 ns t PHL LK to Q 4 19 ns t PHL L to Q 5 19 ns f MAX Maximum clock frequency 63 MHz t SU1 L inactive setup time before LK 5 ns t SU2 ata setup time before LK 5 ns t H ata hold time after LK 3 ns t W Minimum pulse width L low LK high LK low 8 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(si). 6
7 PAKAGING Side-Brazed Packages 7
8 FLATPAK PAKAGES 8
9 UT54AS273/UT54ATS273: SM 5962 * ***** ** * * * Lead Finish: (Notes 1 & 2) A = Solder = Gold X = Optional Package Type: X = 20-lead ceramic bottom-brazed dual-in-line Flatpack = 20-lead ceramic side-brazed dip lass esignator: Q = QML lass Q V = QML lass V evice Type: 01 rawing Number: = UT54AS = UT54ATS273 Total ose: (Notes 3 & 4) = 1E5 rads(si) F = 3E5 rads(si) G = 5E5 rads(si) H = 1E6 rads(si) Notes: 1. Lead finish (A,, or X) must be specified. 2. If an X is specified when ordering, part marking will match the lead finish and will be either A (solder) or (gold). 3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. For prototype inquiries, contact factory. 4. evice type 02 is only offered with a TI tolerance guarantee of 3E5 rads(si) or 1E6 rads(si) and is tested in accordance with MIL-ST-883 Test Method 1019 ondition A and section evice type 03 is only offered with a TI tolerance guarantee of 1E5 rads(si), 3E5 rads(si), and 5E5 rads(si), and is tested in accordance with MIL-ST-883 Test Method 1019 ondition A. 9
10 Aeroflex olorado Springs - atasheet efinition Advanced atasheet - Product In evelopment Preliminary atasheet - Shipping Prototype atasheet - Shipping QML & educed Hi-el OLOAO Toll Free: Fax: SE AN MI-ATLANTI Tel: Fax: INTENATIONAL Tel: Fax: WEST OAST Tel: Fax: NOTHEAST Tel: Fax: ENTAL Tel: Fax: info-ams@aeroflex.com Aeroflex UTM Microelectronic Systems Inc. (Aeroflex) reserves the right to make changes to any products and services herein at any time without notice. onsult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. Aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by Aeroflex; nor does the purchase, lease, or use of a product or service from Aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Aeroflex or of third parties. Our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused 10
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Quad D-Type Flip-Flop With Clear General Description The MM74HC175 high speed D-type flip-flop with complementary outputs utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity
74HC1G86; 74HCT1G86. 2-input EXCLUSIVE-OR gate. The standard output currents are half those of the 74HC/HCT86.
Rev. 04 20 July 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G86 and 74HCT1G86 are high-speed Si-gate CMOS devices. They provide a 2-input EXCLUSIVE-OR function.
74LV74 Dual D-type flip-flop with set and reset; positive-edge trigger
INTEGRATED IRUITS positive-edge trigger Supersedes data of 1996 Nov 07 I24 Data andbook 1998 Apr 20 FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for ow Voltage applications: 1.0 to 3.6V Accepts
CD4024BC 7-Stage Ripple Carry Binary Counter
CD4024BC 7-Stage Ripple Carry Binary Counter General Description The CD4024BC is a 7-stage ripple-carry binary counter. Buffered outputs are externally available from stages 1 through 7. The counter is
CD54/74HC393, CD54/74HCT393
CD54/74HC393, CD54/74HCT393 Data sheet acquired from Harris Semiconductor SCHS186A September 1997 - Revised May 2000 High Speed CMOS Logic Dual 4-Stage Binary Counter /Title CD74 C393 D74 CT39 ) Subect
CD4013BM CD4013BC Dual D Flip-Flop
CD4013BM CD4013BC Dual D Flip-Flop General Description The CD4013B dual D flip-flop is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement mode transistors
CD54/74HC164, CD54/74HCT164
Data sheet acquired from Harris Semiconductor SCHS155A October 1997 - Revised May 2000 CD54/74HC164, CD54/74HCT164 High Speed CMOS Logic 8-Bit Serial-In/Parallel-Out Shift Register Features Description
NTE74177 Integrated Circuit TTL 35Mhz Presettable Binary Counter/Latch
NTE74177 Integrated Circuit TTL 35Mhz Presettable Binary Counter/Latch Description: The NTE74177 is a high speed monolithic counter in a 14 Lead plastic DIP type package consisting of four DC coupled master
CD54/74AC153, CD54/74ACT153
CD4/74AC13, CD4/74ACT13 Data sheet acquired from Harris Semiconductor SCHS237A September 1998 - Revised May 2000 Dual 4-Input Multiplexer Features Description [ /Title (CD74 AC13, CD74 ACT1 3) /Subject
8-bit binary counter with output register; 3-state
Rev. 01 30 March 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low power Schottky TTL (LSTTL). It
Features. Y LS174 contains six flip-flops with single-rail outputs. Y LS175 contains four flip-flops with double-rail outputs
54LS174 DM54LS174 DM74LS174 54LS175 DM54LS175 DM74LS175 Hex Quad D Flip-Flops with Clear General Description These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop
74HC2G34; 74HCT2G34. The 74HC2G34; 74HCT2G34 is a high-speed Si-gate CMOS device. The 74HC2G34; 74HCT2G34 provides two buffers.
Rev. 01 6 October 2006 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The provides two buffers. Wide supply voltage range from 2.0
3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω termination resistors; 3-state
with 30 Ω termination resistors; 3-state Rev. 03 17 January 2005 Product data sheet 1. General description 2. Features The is a high performance BiCMOS product designed for V CC operation at 3.3 V. The
54AC 74AC11 Triple 3-Input AND Gate
54AC 74AC11 Triple 3-Input AND Gate General Description The AC11 contains three 3-input AND gates Logic Symbol IEEE IEC Features Pin Assignment for DIP Flatpak and SOIC Y ICC reduced by 50% Y Outputs source
CD74HC221, CD74HCT221
November 997 SEMIONDUTO D74H22, D74HT22 High Speed MOS Logic Dual Monostable Multivibrator with eset Features Description Overriding ESET Terminates Output Pulse Triggering from the Leading or Trailing
INTEGRATED CIRCUITS. 74LV259 8-bit addressable latch. Product specification Supersedes data of 1997 Jun 06 IC24 Data Handbook.
INTEGRATED CIRCUITS Supersedes data of 1997 Jun 06 IC24 Data Handbook 1998 May 20 FEATURES Optimized for low voltage applicatio: 1.0 to 3.6 V Accepts TTL input levels between = 2.7 V and = 3.6 V Typical
MM74HC175 Quad D-Type Flip-Flop With Clear
Quad D-Type Flip-Flop With Clear General Description The MM74HC175 high speed D-type flip-flop with complementary outputs utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity
74HC4040; 74HCT stage binary ripple counter. Each counter stage is a static toggle flip-flop.
Rev. 03 14 September 2005 Product data sheet 1. General description 2. Features 3. pplications 4. uick reference data he are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series.
74HC1GU04GV. 1. General description. 2. Features. 3. Ordering information. Marking. 5. Functional diagram. Inverter
Rev. 5 1 July 27 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. It provides an inverting single stage function. The standard output
74HC273; 74HCT273. Octal D-type flip-flop with reset; positive-edge trigger
Rev. 03 24 January 2006 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).
8-channel analog multiplexer/demultiplexer. For operation as a digital multiplexer/demultiplexer, V EE is connected to V SS (typically ground).
Rev. 04 12 January 2005 Product data sheet 1. General description 2. Features The is an with three address inputs (0 to 2), an active LOW enable input (E), eight independent inputs/outputs (Y0 to Y7) and
CD40174BC CD40175BC Hex D-Type Flip-Flop Quad D-Type Flip-Flop
Hex D-Type Flip-Flop Quad D-Type Flip-Flop General Description The CD40174BC consists of six positive-edge triggered D- type flip-flops; the true outputs from each flip-flop are externally available. The
CD74HC151, CD74HCT151
Data sheet acquired from Harris Semiconductor SCHS150 September 1997 CD74HC151, CD74HCT151 High Speed CMOS Logic 8-Input Multiplexer [ /Title (CD74H C151, CD74H CT151) /Subject High peed MOS ogic 8- nput
74ALVC bit dual supply translating transciever; 3-state. This device can be used as two 8-bit transceivers or one 16-bit transceiver.
16-bit dual supply translating transciever; 3-state Rev. 02 1 June 2004 Product data sheet 1. General description 2. Features The is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior
The 74LVC1G02 provides the single 2-input NOR function.
Rev. 07 18 July 2007 Product data sheet 1. General description 2. Features The provides the single 2-input NOR function. Input can be driven from either 3.3 V or 5 V devices. These features allow the use
CD74HC165, CD74HCT165
Data sheet acquired from Harris Semiconductor SCHS156 February 1998 CD74HC165, CD74HCT165 High Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register Features [ /Title (CD74H C165, CD74H CT165) /Subject
The 74LVC1G11 provides a single 3-input AND gate.
Rev. 0 September 200 Product data sheet 1. General description 2. Features The is a high-performance, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The input