Stellaris Family Development Board

Transcription

1 Stellaris Family evelopment oard USER S MNUL M-LMSFM-0 opyright 00 Luminary Micro, Inc.

2 Legal isclaimers and Trademark Information Legal isclaimers and Trademark Information INFORMTION IN THIS OUMENT IS PROVIE IN ONNETION WITH LUMINRY MIRO PROUTS. NO LIENSE, EXPRESS OR IMPLIE, Y ESTOPPEL OR OTHERWISE, TO NY INTELLETUL PROPERTY RIGHTS IS GRNTE Y THIS OUMENT. EXEPT S PROVIE IN LUMINRY MIRO S TERMS N ONITIONS OF SLE FOR SUH PROUTS, LUMINRY MIRO SSUMES NO LIILITY WHTSOEVER, N LUMINRY MIRO ISLIMS NY EXPRESS OR IMPLIE WRRNTY, RELTING TO SLE N/OR USE OF LUMINRY MIRO S PROUTS INLUING LIILITY OR WRRNTIES RELTING TO FITNESS FOR PRTIULR PURPOSE, MERHNTILITY, OR INFRINGEMENT OF NY PTENT, OPYRIGHT OR OTHER INTELLETUL PROPERTY RIGHT. LUMINRY MIRO S PROUTS RE NOT INTENE FOR USE IN MEIL, LIFE SVING, OR LIFE-SUSTINING PPLITIONS. Luminary Micro may make changes to specifications and product descriptions at any time, without notice. ontact your local Luminary Micro sales office or your distributor to obtain the latest specifications before placing your product order. esigners must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Luminary Micro reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. opyright 00 Luminary Micro, Inc. ll rights reserved. Stellaris and the Luminary Micro logo are trademarks of Luminary Micro, Inc. or its subsidiaries in the United States and other countries. RM and Thumb are registered trademarks, and ortex is a trademark of RM Limited. Other names and brands may be claimed as the property of others. Luminary Micro, Inc. 99 South apital of Texas Hwy, Suite -00 ustin, TX Main: Fax: July 0, 00

3 Stellaris Family evelopment oard User s Manual Revision History This table provides a summary of the document revisions. ate Revision escription March Initial release of doc to customers. May 00 0 Release of daughterboard and documentation. May 00 0 dded missing schematics to board manual PF. July 00 0 Switched Layout and Layout figures so most current board is first. dded QEI text to Headers paragraph in hapter. July 0, 00

4 July 0, 00

5 Stellaris Family evelopment oard User s Manual Table of ontents hapter : Stellaris Family evelopment oard... 9 Features... 9 lock iagram... 0 Functional escription... aughterboard... URT... Headers... Potentiometer... Photocell... User LEs... User Pushbutton... JTG ebug onnector... US ebug... I EEPROM Memory... SPI Flash Memory... uzzer... Real-Time lock... External Reset... Prototype rea... Peripheral evice ontroller (P)... Power Supply... Motherboard Layout... evelopment oard onfiguration... aughterboard Installation... URT... SPI Port (On-oard Peripherals)... I Port... uzzer... L Panel, IP Switch, LEs, and GPIOs... User Pushbutton... User LEs... Photocell... Potentiometer... JTG ebug onnector... US ebug....-khz lock Oscillator... Reset Switch... GPIO Headers... Power... Peripheral evice ontroller (P)... Stellaris Microcontroller to P Interface... P I/O... P Registers... July 0, 00

6 Table of ontents SPI Protocol... 9 hapter : aughterboard... Features... lock iagram... aughterboard Interface... aughterboard Layout... Shunt Jumper... evelopment oard Signal Usage... hapter : aughterboard... Features... lock iagram... aughterboard Interface... aughterboard Layout... Shunt Jumpers... 0 evelopment oard Signal Usage... ppendix : ontact Information... ppendix : Schematics... July 0, 00

7 Stellaris Family evelopment oard User s Manual List of Figures Figure -. Stellaris Family evelopment oard lock iagram... 0 Figure -. Stellaris Family Motherboard Layout... Figure -. P Timing iagrams... 0 Figure -. aughterboard lock iagram... Figure -. aughterboard Layout... Figure -. aughterboard lock iagram... Figure -. aughterboard Layout... 9 Figure -. aughterboard Layout... 0 July 0, 00

8 List of Tables List of Tables Table -. Possible oard Power Sources... Table -. Stellaris Microcontroller to P Interface... Table -. Peripheral to P Interface... Table -. P Registers... Table -. aughterboard Interface... Table -. Jumper Settings for aughterboard... Table -. evelopment oard Signals Used by aughterboard... Table -. aughterboard Interface... Table -. Jumper Settings for aughterboard... 0 Table -. evelopment oard Signals Used by aughterboard... July 0, 00

9 H P T E R Stellaris Family evelopment oard Features The Stellaris Family evelopment oard provides a platform for product development. Hardware and software engineers use this board for evaluation of Stellaris family microcontroller features and functionality, and for software development. The development board includes the Stellaris motherboard and a daughterboard with a Stellaris family microcontroller. The daughterboard is available for -pin SOI devices, and the daughterboard is available for -pin LQFP devices. These daughterboards are described in hapter, aughterboard on page and hapter, aughterboard on page. The Stellaris Family evelopment oard includes the following features. Note that not all features are implemented on all Stellaris microcontrollers. aughterboards enable support for multiple package/pin-out options Two URT transceivers and 9 male connectors ll I/O available on headers One potentiometer and one photocell for driving the nalog-to-igital onverter () and comparator inputs Eight user LEs and one pushbutton for use with the Stellaris GPIOs Standard RM 0-pin JTG debug connector US.0 full speed interface allows JTG/SW debug without in-circuit emulator (IE) -Kbit I EEPROM memory -Mbit SPI-based flash memory One buzzer for PWM use.-khz oscillator for real-time clock External reset switch and power-on reset supervisor -V and.-v LE power indicators User-prototype area Peripheral evice ontroller (P) PL for interface with the following: character by -line L display status LEs -position dual-inline package (IP) switch GPIOs July 0, 00 9

10 Stellaris Family evelopment oard lock iagram Figure -. Stellaris Family evelopment oard lock iagram Stellaris aughterboard onnectors RESET JTG URT0 Photocell URT [0///] Port Headers 0+/+/+ [///] P P P P PE I us EEPROM 0-/-/- Flash US Potentiometer. V Regulator Expansion Headers SPI us User LEs P User Pushbutton GPIOX GPIOY GPIOZ GPIOs IP Switch uzzer L Panel Motherboard LEs 0 July 0, 00

11 Stellaris Family evelopment oard User s Manual Functional escription aughterboard URT Headers Potentiometer Photocell User LEs The daughterboard contains the Stellaris microcontroller and connects to the motherboard with four -pin connectors. The Stellaris PLL clock is generated from a -MHz crystal provided on pin sockets for easy crystal changes. n optional SM connector can be used to drive an external clock source. Two URT transceivers and 9 connectors are provided to connect with the Stellaris microcontroller URT peripherals. The URT0 peripheral (TX, RX) is included in all Stellaris microcontrollers; URT is available in all -pin microcontrollers except the LMS0. On the LMS0, LMS0 and LMS0, URT is available for external use. ll Stellaris I/O signals are available on five -pin GPIO headers labeled Port through Port E to match the Stellaris microcontroller GPIO ports. For each port header, pin is bit 0 and pin is bit of the corresponding Stellaris GPIO. For example, Port pin is P0 and Port pin is P of the Stellaris microcontroller. Note that ports and E have only six I/O signals, with the remaining two header pins connected to ground. Jumper shunts are used to connect Stellaris signals to onboard devices to allow connect/disconnect. Stellaris signals can be rewired with the included flywires. There are also two 0-pin expansion headers (J9 and J). Header J9 is intended primarily as an interface for a motor driver board, and includes all the Stellaris PWM outputs, QEI inputs, analog comparator inputs, and three inputs. Header J has the remaining Stellaris signals, and includes URT, SSI, I, JTG, and timer P input signals. NOTE: PWM, QEI,, I, and analog comparators are available on select Stellaris microcontrollers. One potentiometer is included to drive selected nalog-to-igital onverter () inputs and/or analog comparator inputs. The voltage range is 0 to.0. Shunt headers are used for signal selection. NOTE: and analog comparators are available on select Stellaris microcontrollers. One photocell is included to drive selected inputs and/or analog comparator inputs. The voltage range is 0 to.0. Shunt headers are used for signal selection. NOTE: and analog comparators are available on select Stellaris microcontrollers. Eight user LEs (ULE0-ULE) are provided for general use. Headers are provided for connectivity. User Pushbutton One user pushbutton (SW) is provided for general use. header is provided for connectivity. July 0, 00

12 Stellaris Family evelopment oard JTG ebug onnector US ebug standard 0-pin connector for JTG debug is provided. This port is also used to access the Serial-Wire ebug (SW) interface of the Stellaris microcontroller. When using this connector, the US interface cannot be used for JTG/SW debug (US can still be used for providing board power). shunt jumper at location JP may be required when using this port. US.0 full-speed interface provides debug capability via JTG or SW without the need for an IE. Note that use of this interface requires installation of the corresponding US drivers. When using this interface, the 0-pin JTG connector cannot be used for JTG/SW debug. Ensure that no shunt jumper is present at location JP. I EEPROM Memory n -Kbit I memory is included for use with the Inter-Integrated ircuit (I ) bus interface. jumper block is provided for connecting this memory. NOTE: The I interface is available on select Stellaris microcontrollers. SPI Flash Memory uzzer -Mbit SPI flash memory is included for use with the Serial Port Interface (SPI) port. jumper block is provided for connecting this memory. buzzer is provided for use with one of the PWM outputs. Real-Time lock External Reset Prototype rea.-khz crystal oscillator generates a clock signal that can be used to drive the Stellaris realtime clock. Shunt jumpers on the daughterboard can be used to connect this clock source. The external reset is implemented with a reset switch SW connected to a reset supervisor circuit, and provides a system reset signal. prototype area is provided for implementing user circuits. To supply power, there are power and ground rows. The prototype area is indicated on the board with a Luminary Micro logo (see Figure - on page ). Peripheral evice ontroller (P) Peripheral evice ontroller (P) implemented with a PL is accessible via the SPI interface and provides access to several devices including a -character by -line L display, an -bit IP switch, general-purpose user LEs, and GPIOs. July 0, 00

13 Stellaris Family evelopment oard User s Manual Power Supply The Stellaris Family evelopment oard requires volts at 00 m for operation, and three options are provided for supply connection.. US connector can be used when connected to a high-power (00-m) US hub port.. -V jack can be used with an external power supply.. terminal block can be wired to a -V external bench supply. slide switch selects between US power and the other two options (see Figure - on page ). Table - on page describes how to select the power supply. Motherboard Layout The Stellaris family motherboard layout is shown in Figure -. The gray squares show the location of pin for all connectors and headers. (On the board silk-screen, white arrows indicate pin.) There are four ground test loops: TL-TL. TL is.0 V, and TL is. V. Figure -. Stellaris Family Motherboard Layout TL P JP JP JP JP9 P J9 J J V J9 J J JP0 S J JP JP JP Port Port Port GPIOZ JP.0V. V TL.V J J J JP JP PortPortE Spare GPIOX GPIOY J0 TL R JP0 J J JP JP JP JP LE JP0 WP SL S ULE JP JP Z JP SW JP9 JP JP JP JP SW SW TL R POT LE 0 JP ULE 0 R NOTE: The gray squares indicate the location of pin for all connectors and headers. July 0, 00

14 Stellaris Family evelopment oard evelopment oard onfiguration NOTE: In the descriptions that follow, reference designators are used to indicate locations on the board layout (as shown in Figure -). In addition, reference designators in parenthesis refer to parts in the schematics in ppendix, Schematics. aughterboard Installation URT The daughterboard connects to the motherboard header connectors J-J. With no power applied to the motherboard, place the daughterboard and align each connector of the motherboard with the corresponding daughterboard connector. Press the daughterboard down until the daughterboard is firmly seated, and visually inspect all four connectors to ensure proper connection before proceeding. To connect the URT0 transceiver, connect shunt jumpers on headers JP and JP. To connect URT, connect shunt jumpers on headers JP and JP9. SPI Port (On-oard Peripherals) I Port uzzer To connect the Serial Peripheral Interface port, which is used to communicate with the P and the on-board flash memory, connect shunt jumpers to pins - of headers JP, JP, JP, and JP. To write-protect the SPI flash memory, place a shunt jumper on JP0. NOTE: The Stellaris microcontroller s SSI port can be programmed for one of three serial modes: Freescale SPI, National Semiconductor MIROWIRE, or Texas Instruments synchronous serial. (The mode is set with the FRF bit in the SSI ontrol0 (SSIR0) register.) The Stellaris Family evelopment oard is designed for use with SPI mode although MIROWIRE and TI synchronous serial modes can be used when implementing user circuits in the prototype area. SPI mode must be set to use the board s L, IP switch, LEs, and GPIOX, GPIOY, and GPIOZ ports. To connect the I port for access to the on-board EEPROM, place shunt jumpers on JP and JP. To write-protect the EEPROM memory, place a shunt jumper on JP. ddress line for the EEPROM memory can be set to 0 by placing a shunt jumper on JP. Removing the jumper sets to. NOTE: The I interface is available on select Stellaris microcontrollers. To enable the buzzer Z, connect a shunt jumper to JP. To connect the buzzer power driver to the Stellaris microcontroller P0 port, place a shunt jumper on JP. To use a different port to drive the buzzer, remove the shunt at JP and connect a fly-wire from the desired port to JP-. L Panel, IP Switch, LEs, and GPIOs To use the L panel, IP switch, LEs LE0-LE (-), and the GPIOs, the SPI port must be connected as described above. The SPI port connects to the P to control these devices. The potentiometer R is used to adjust the contrast of the L panel. The L panel, IP switch, LEs, and GPIOs are controlled with the P registers (see Table - on page ). July 0, 00

15 Stellaris Family evelopment oard User s Manual User Pushbutton User LEs Photocell Potentiometer Pushbutton SW is available for general use. To connect this switch to P, place a shunt jumper on JP9. To use a different port, remove shunt at JP9 and connect a fly-wire from the desired port to JP9-. User LEs ULE0-ULE (9, 0,, -) are available for general use. Each user LE has an associated header for connection to a Stellaris GPIO, P GPIO, or external circuitry. To connect a user LE to its associated Stellaris GPIO, place a shunt jumper on the corresponding header (ULE0-ULE => P0-P, ULE-ULE => P0-P). To use a different port, remove the shunt jumper from the header and connect a fly-wire from the desired port to pin of the header. Photocell R can be used to provide an analog signal to drive the (analog-to-digital converter) and the analog comparator using headers JP (0,,,) => (PE,PE,P,P), and JP (0+,+,+) => (P,P,P). To connect the photocell to an channel, place a shunt jumper on the corresponding JP header. To connect the photocell to a comparator channel, place a shunt jumper on the corresponding JP header. NOTE: and analog comparators are available on select Stellaris microcontrollers. Potentiometer R can be used to provide an analog signal to drive the (analog-to-digital converter) and the analog comparator using headers JP (,,,) => (PE,PE,P,P), and JP (0-,-,-) => (P,P,P). To connect the potentiometer to an channel, place a shunt jumper on the corresponding JP header. To connect the potentiometer to a comparator channel, place a shunt jumper on the corresponding JP header. NOTE: and analog comparators are available on select Stellaris microcontrollers. JTG ebug onnector US ebug For JTG debug with an external IE, connect the IE to connector J with a standard 0-pin JTG debug cable. To link the motherboard reset to the JTG emulator reset, place a shunt jumper on JP0. epending on the IE, a shunt jumper at location JP may be required if a US driver conflict occurs. For debug with US, connect the US cable to the US device connector. Ensure that no shunt jumper is present at location JP. Note that a corresponding US driver must be installed on the host computer. The US driver selects the mode of operation by controlling the US_MO signal from the FTI part (US). If US_MO is, JTG mode is selected. If US_MO is 0, SW mode is selected. JTG/SW signals are driven to the Stellaris microcontroller when the US driver sets US_EN (US) to 0..-KHz lock Oscillator n on-board.-khz oscillator can be used to drive the Stellaris real-time clock. To enable this oscillator, remove the shunt jumper on JP. To disable the oscillator output, place a shunt jumper on JP. July 0, 00

16 Stellaris Family evelopment oard Reset Switch GPIO Headers Power Reset switch SW generates a 0-ms (minimum) system reset signal. Powering up the board also generates a 0-ms system reset signal. shunt jumper can be placed on JP0 to link the JTG emulator reset with the system reset. ll Stellaris GPIO ports are available on -pin headers labeled Port (J), Port (J), Port (J), Port (J0), and PortE (J). The 0-pin headers J9 and J include all the GPIOs and provide a convenient connection for expansion to another board. The -pin headers labeled GPIOX (J), GPIOY (J), and GPIOZ (J) provide a connection to the GPIOs implemented in the P. Three options are available for board power, and only one should be connected to the board. These are described in Table -. The two power indicators light once there is power to the board. Table -. Possible oard Power Sources Power Source US high-power hub (00 m) onfiguration Slide switch S towards the board edge. onnect a US cable from the US hub to the US- receptacle J. Slide switch S towards the board center to turn on power. -V (00-m) supply with.-mm plug Slide switch S towards the center of the board. onnect a -V supply with a.-mm plug to jack J9. Slide switch S towards the board edge to turn on power. -V (00-m) bench supply Slide switch S towards the center of the board. onnect a -V supply with two wires to terminal block J. onnect the -V wire to J- (V) and the ground wire to J- (). Slide switch S towards the board edge to turn on power. J V Peripheral evice ontroller (P) The P provides access to a common set of peripherals across all Stellaris microcontrollers, since they all include an SSI port. The Stellaris SSI port is used in SPI mode for communications with the P. The P operates at MHz. July 0, 00

17 Stellaris Family evelopment oard User s Manual Stellaris Microcontroller to P Interface The Stellaris microcontroller connects to the P with a SPI port using the signals shown in Table -. Table -. Stellaris Microcontroller to P Interface P I/O oard Signal irection escription SPI_LK Input SPI clock signal, MHz. SPI_SEL Input SPI select signal, set high to enable SPI transfers. Set to low for reset of the P (minimum 00 nanoseconds). Note that with SPI_SEL low the SPI flash at location U is selected. SPI_MOSI Input Master output, slave input data transfer signal. SPI_MISO Output Master input, slave output data transfer signal. The P connects to supported peripherals with the following signals: Table -. Peripheral to P Interface oard Signal irection escription L_RS Out L register select L_RW Out L read/write L_EN Out L chip enable L_LIGHT Out L backlight L[:0] InOut L data bus LE[:0] Out LE select outputs SW[:0] In IP switch inputs GPIOX_[:0] InOut GPIOX I/O ports GPIOY_[:0] InOut GPIOY I/O ports GPIOZ_[:0] InOut GPIOZ I/O ports July 0, 00

18 Stellaris Family evelopment oard P Registers P registers are bits, and there are three types: Read-Only (RO), Read/Write (R/W), and Read/Write delayed (RW). RW transaction requires an additional dummy transfer due to peripheral device latency. Table -. P Registers Register ddress Type escription VERSION 0x0 R0 The VERSION register contains the version of the P design programmed in the PL. SR 0x R/W The ommand/status (SR) register is used to set special configuration options and read device status. Unused bits are reserved and should be written to 0. The following bits are defined: it0 - LL: The L backlight bit controls the L panel backlight. Setting this bit to turns on the L backlight. Setting this bit to 0 turns off the L backlight. it - LSY: The L busy bit reflects the value of the L panel busy flag. When this bit is, the L panel is busy processing a command. When this bit is 0, a new command can be written to the L panel. IPSW 0x R0 The IP Switch (IPSW) register contains the value of the debug IP switch at location SW. it i corresponds to switch i+. switch in the OFF position is read as 0. switch in the ON position is read as. LE 0x R/W The LE Output (LE) register controls LE0-LE. it i controls LEi. Writing a bit to turns on the corresponding LE. Writing a bit to 0 turns off the corresponding LE. LSR 0x RW The L ommand/status (LSR) register is used to write configuration and control commands and to read status information from the L panel. For more information, refer to the FH0 L panel data sheet (available from LRM 0x RW The L RM (LRM) register is used to write and read the L display data RM (RM) and the character generator RM (GRM). For more information, refer to the FH0 L panel data sheet (available from GPXT 0x R/W The GPIOX ata (GPXT) register is used to access the generalpurpose I/O port GPIOX at location J. it i corresponds with the GPIOX_i port signal. Each bit can be configured for input or output in the GPXIR register. Writing a bit to sets the corresponding GPIOX port signal to if the port signal is configured as an output. Writing a bit to 0 sets the corresponding GPIOX port signal to 0 if the port signal is configured as an output. Reading a bit reads the value of the corresponding GPIOX port signal. If the GPIOX port is 0, the bit will read as 0. If the GPIOX port signal is, the bit will read as. Note that a read of the GPXT register always reads the GPIOX port signals, not the internal register. July 0, 00

19 Stellaris Family evelopment oard User s Manual Table -. P Registers Register ddress Type escription SPI Protocol GPXIR 0x9 R/W The GPIOX irection (GPXIR) register is used to select the data transfer direction for the GPXT register. it i corresponds to GPXT bit i. Writing a bit to sets the corresponding GPXT bit as an output port. Writing a bit to 0 sets the corresponding GPXT bit as an input port. GPYT 0x R/W The GPIOY ata (GPYT) register is used to access the generalpurpose I/O port GPIOY at location J. it i corresponds with the GPIOY_i port signal. Each bit can be configured for input or output in the GPYIR register. Writing a bit to sets the corresponding GPIOY port signal to if the port signal is configured as an output. Writing a bit to 0 sets the corresponding GPIOY port signal to 0 if the port signal is configured as an output. Reading a bit reads the value of the corresponding GPIOY port signal. If the GPIOY port is 0, the bit will read as 0. If the GPIOY port signal is, the bit will read as. Note that a read of the GPYT register always reads the GPIOY port signals, not the internal register. GPYIR 0x R/W The GPIOY irection (GPYIR) register is used to select the data transfer direction for the GPYT register. it i corresponds with GPYT bit i. Writing a bit to sets the corresponding GPYT bit as an output port. Writing a bit to 0 sets the corresponding GPYT bit as an input port. GPZT 0x R/W The GPIOZ ata (GPZT) register is used to access the generalpurpose I/O port GPIOZ at location J. it i corresponds with the GPIOZ_i port signal. Each bit can be configured for input or output in the GPZIR register. Writing a bit to sets the corresponding GPIOZ port signal to if the port signal is configured as an output. Writing a bit to 0 sets the corresponding GPIOZ port signal to 0 if the port signal is configured as an output. Reading a bit reads the value of the corresponding GPIOZ port signal. If the GPIOZ port is 0, the bit will read as 0. If the GPIOZ port signal is, the bit will read as. Note that a read of the GPZT register always reads the GPIOZ port signals, not the internal register. GPZIR 0x R/W The GPIOZ irection (GPZIR) register is used to select the data transfer direction for the GPZT register. it i corresponds with GPZT bit i. Writing a bit to sets the corresponding GPZT bit as an output port. Writing a bit to 0 sets the corresponding GPZT bit as an input port. The SPI slave interface is enabled when SPI_SEL goes High. ll SPI commands and data are received via the SPI_MOSI input signal, with data sampled on the rising edge of the SPI clock. ll SPI output data is transmitted on the SPI_MISO output signal, with data shifted out on the falling edge of the SPI clock. Set SPI_SEL Low for 00 nanoseconds to reset the P. July 0, 00 9

20 Stellaris Family evelopment oard Every transaction is composed of at least two -bit SPI transfers. The first byte contains a -bit address on the lower bits (bits :0) and a read/write (R/W) bit to indicate transfer direction on the most significant bit (bit ). The remaining bits (bits :) are reserved and must be 0. The next byte is driven by the Stellaris microcontroller for write transfers (R/W bit=0), and by the P for read transfers (R/W bit=). For read transfers to L registers, a dummy byte follows the first byte, with a valid data byte afterwards. Timing diagrams are shown in Figure -. Figure -. P Timing iagrams P Read Transfer SPI_SEL SPI_LK SPI_MOSI RW SPI_MISO 0 L Read Transfer SPI_SEL SPI_LK SPI_MOSI RW SPI_MISO 0 0 ummy yte P/L Write Transfer SPI_SEL SPI_LK SPI_MOSI RW SPI_MISO 0 July 0, 00

21 H P T E R aughterboard Features The daughterboard contains a -pin SOI Stellaris microcontroller and connects to the motherboard with four -pin connectors. NOTE: In the descriptions that follow, reference designators are used to indicate locations on the board layout (as shown in Figure - on page ). In addition, reference designators in parenthesis refer to parts in the schematics in ppendix, Schematics. esigned for -pin SOI Stellaris microcontroller -MHz crystal mounted on pin sockets for easy crystal changes SM connector for external clock Power and ground test loops Jumper-selectable.-KHz clock ll daughterboard connector signals accessible via headers on the daughterboard lock iagram Figure -. aughterboard lock iagram Stellaris onnectors JP aughterboard Interface The daughterboard connects to the motherboard with four connectors: J-J (see Figure - on page ). Table - on page lists the connections. July 0, 00

22 aughterboard Table -. aughterboard Interface Pin J J J J.V.V XP P0 LKK 9 P 0 P V RSTn P P P P/TO P P0/TK P 9 P/TMS P P0 0 P/TI P P P/TRST aughterboard Layout The daughterboard layout is shown in Figure - on page. single Stellaris microcontroller is soldered at location U. There are four ground test loops: TL, TL, TL, and TL. TL is connected to the LO pin and TL is connected to V. The gray squares show the location of pin for each connector. Note that TL and pin of J and J are. V. clock signal can be applied to SM connector J after removing crystal Y. July 0, 00

23 Stellaris Family evelopment oard User s Manual Figure -. aughterboard Layout.V J.V TL TL TL TL LO V U J U J J TL TL TL Y J.V JP NOTE: The gray squares indicate the location of pin. Shunt Jumper There is a single shunt jumper JP (see Figure -) used for selecting the connection of port (P) as shown in Table -. Table -. Shunt No shunt Shunt - Jumper Settings for aughterboard escription P is unconnected P is connected to.-khz clock Shunt - P is connected to daughterboard connector J- (XP) July 0, 00

24 aughterboard evelopment oard Signal Usage Table - shows the signal connectivity and usage between the daughterboard and the motherboard. For the jumpers column, the numbers in brackets show the jumper position. Table -. evelopment oard Signals Used by aughterboard Stellaris Signal aughterboard onnection Motherboard Jumpers Motherboard Signal escription P0 J-9 JP-[][] U0_RX Serial port 0 receive P J-0 JP-[][] U0_TX Serial port 0 transmit P J- JP-[][] SPI_LK Serial peripheral interface clock P J- JP-[][] SPI_SEL Serial peripheral interface select P J- JP-[][] SPI_MISO Serial peripheral interface master-in/slave-out P J- JP-[][] SPI_MOSI Serial peripheral interface master-out/slave-in P0 J- JP[][] PWM uzzer signal JP[][] ULE0 User LE P JP-[][] (J-) LKK.-KHz clock JP-[][] (J-) JP-[][] ULE User LE P J-9 P J-0 J-9 I_SL I clock signal to EEPROM JP[][] ULE User LE J-0 I_S I data signal to EEPROM JP[][] ULE User LE P J-0 JP-[][] 0- onnects to 0k potentiometer P J-9 JP-[][] - onnects to 0k potentiometer P J- JP-[][] 0+ onnects to photocell P J- J- TRST JTG signal, used by emulator P0 J- J-9 TK JTG signal, used by emulator P J-9 J- TMS JTG signal, used by emulator P J-0 J- TI JTG signal, used by emulator P J- J- TO JTG signal, used by emulator RST J- SYSRST_ onnects to reset supervisor OS0 J, onnects to pin socket and capacitor for crystal OS J, onnects to pin socket and capacitor for crystal V- (U) TL, J-, J-.V onnects to.-v plane July 0, 00

25 Stellaris Family evelopment oard User s Manual Table -. evelopment oard Signals Used by aughterboard Stellaris Signal aughterboard onnection Motherboard Jumpers Motherboard Signal escription J-, J- J-, J- LO onnects to ground plane onnects to. microfarad capacitor and to test loop July 0, 00

26 aughterboard July 0, 00

27 H P T E R aughterboard Features The daughterboard contains a -pin LQFP Stellaris microcontroller and connects to the motherboard with four -pin connectors. NOTE: In the descriptions that follow, reference designators are used to indicate locations on the board layout (as shown in Figure - on page 9 and Figure - on page 0). In addition, reference designators in parenthesis refer to parts in the schematics in ppendix, Schematics. esigned for -pin LQFP Stellaris microcontroller -MHz crystal mounted on pin sockets for easy crystal changes SM connector for external clock Power and ground test loops Jumper-selectable.-KHz clock ll daughterboard connector signals accessible via headers on the daughterboard lock iagram Figure -. aughterboard lock iagram Stellaris JP JP JP onnectors aughterboard Interface The daughterboard connects to the motherboard with four connectors: J-J (see Figure - on page ). Table - on page lists the connections. July 0, 00

28 aughterboard Table -. aughterboard Interface Pin J J J J.V.V PV P PE P PE XP P0 LKK XPE 9 P 0 P P V PE RSTn P P P PE P P/TO PE0 XP P P P P0/TK P P 9 P/TMS P P P0 0 P/TI P0 P P P/TRST P aughterboard Layout There are two different layouts of the daughterboard. Layout shown on Figure - on page 9 has the Stellaris microcontroller soldered at U on the center of the board. Layout shown on Figure - on page 0 has the Stellaris microcontroller soldered at location U on the left side of the board. oth layouts include four ground test loops: TL-TL in Layout and TL, TL, TL, and TL in Layout. TL in Layout and TL in Layout are connected to the LO pin. The gray squares show the location of pin for each connector. Note that TL in Layout and TL in Layout as well as pin of J and J are. V. clock signal can be applied to SM connector J after removing crystal Y. July 0, 00

29 Stellaris Family evelopment oard User s Manual Figure -. aughterboard Layout.V J.V TL JP JP TL LO TL JP J U TL J J Y.V TL TL J NOTE: The gray squares indicate the location of pin. July 0, 00 9

30 aughterboard Figure -. aughterboard Layout.V J.V TL TL TL TL LO V J U U U J J TL TL TL Y J.V JP JP JP NOTE: The gray squares indicate the location of pin. Shunt Jumpers There are three shunt jumpers for connection of a.-khz clock as shown in Table -. Table -. Jumper Settings for aughterboard Jumper Shunt escription JP No shunt P is unconnected Shunt - Shunt - P is connected to.-khz clock. P is connected to daughterboard connector J- (XP) JP No shunt P is unconnected Shunt - Shunt - P is connected to.-khz clock. P is connected to daughterboard connector J- (XP) JP No shunt PE is unconnected Shunt - Shunt - PE is connected to.-khz clock. PE is connected to daughterboard connector J- (XPE) 0 July 0, 00

31 Stellaris Family evelopment oard User s Manual evelopment oard Signal Usage Table - shows the signal connectivity and usage between the daughterboard and the motherboard. For the jumpers column, the numbers in brackets show the jumper position. Table -. evelopment oard Signals Used by aughterboard Stellaris Signal aughterboard onnection Motherboard Jumpers Motherboard Signal escription P0 J-9 JP-[][] U0_RX Serial port 0 receive P J-0 JP-[][] U0_TX Serial port 0 transmit P J- JP-[][] SPI_LK Serial peripheral interface clock P J- JP-[][] SPI_SEL Serial peripheral interface select P J- JP-[][] SPI_MISO Serial peripheral interface master-in/slave-out P J- JP-[][] SPI_MOSI Serial peripheral interface master-out/slave-in P0 J- JP-[][] PWM uzzer signal JP-[][] ULE0 User LE P JP-[][] (J-) LKK.-KHz clock JP-[][] (J-) JP-[][] ULE User LE P J-9 P J-0 JP-[][] I_SL I clock signal to EEPROM JP-[][] ULE User LE JP-[][] I_S I data signal to EEPROM JP-[][] ULE User LE P J-0 JP-[][] 0- onnects to 0k potentiometer P J-9 JP-[][] - onnects to 0k potentiometer P J- JP-[][] 0+ onnects to photocell P J- J- TRST JTG signal, used by emulator P0 J- J-9 TK JTG signal, used by emulator P J-9 J- TMS JTG signal, used by emulator P J-0 J- TI JTG signal, used by emulator P J- J- TO JTG signal, used by emulator P J- P Not used P J- JP-[][] + onnects to photocell P J- JP-[][] + onnects to photocell July 0, 00

32 aughterboard Table -. evelopment oard Signals Used by aughterboard Stellaris Signal aughterboard onnection Motherboard Jumpers Motherboard Signal escription P JP-[][] (J-) JP-[][] -.-KHz clock JP-[][] (J- ) JP-[][] - onnects to 0k potentiometer P0 J-0 JP-[][] ULE User LE P J-9 JP-[][] ULE User LE P J- P J- JP9-[][] U_RX Serial port receive JP9-[][] ULE User LE JP-[][] U_TX Serial port transmit JP0-[][] ULE User LE P J- JP-[][] onnects to 0k potentiometer P J-0 JP-[][] onnects to photocell P J- JP-[][] onnects to 0k potentiometer P J- JP-[][] onnects to photocell PE0 J- PE0 Not used PE J- PE Not used PE JP-[][] (J-) LKK.-KHz clock JP-[][] (J-) JP-[][] onnects to 0k potentiometer PE J- JP-[][] onnects to photocell PE J- JP-[][] onnects to 0k potentiometer PE J- JP-[][] 0 onnects to photocell RST J- SYSRST_ onnects to reset supervisor OS0 J, onnects to pin socket and capacitor for crystal OS J, onnects to pin socket and capacitor for crystal V- (U) TL (Layout ), TL (Layout ), J-, J-.V onnects to.-v plane J-,J- onnects to ground plane J-,J- LO onnects to. microfarad capacitor and to test loop July 0, 00

33 P P E N I X ontact Information ompany Information Luminary Micro, Inc. designs, markets, and sells RM ortex-m based microcontrollers for use in embedded applications within the industrial, commercial, and consumer markets. Luminary Micro is RM's lead partner in the implementation of the ortex-m core. Please contact us if you are interested in obtaining further information about our company or our products. Luminary Micro, Inc. 99 South apital of Texas Hwy, Suite -00 ustin, TX Main: Fax: sales@luminarymicro.com Support Information For support on Luminary Micro products, contact: support@luminarymicro.com , ext. July 0, 00

34 July 0, 00

35 P P E N I X Schematics Schematics for the development board follow: Stellaris Motherboard on page aughterboard on page aughterboard Layout (board revision R) on page aughterboard Layout (board revision R) on page July 0, 00

36 July 0, 00

37 Table of ontents Page escription Table of ontents / Revision ontrol lock iagram oard onnectors, GPIO, JTG URT, SPI, I P, L isplay Reset, Power US to Serial Wire ebug Luminary Micro, Inc. 99 S. apital of Texas Hwy ustin, TX This document contains information proprietary to Luminary Micro Inc. and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of Luminary Micro, Inc. opyright 00 Luminary Micro, Inc. ll rights reserved. esigner: rawing Title: rnaldo ruz rawn by: Page Title: rnaldo ruz Table of ontents Stellaris evelopment oard pproved: Size ocument Number Rev <pprover> 000 R ate: Thursday, May, 00 Sheet of

38 oard onnectors J, J, J, J SYSTEM Reset JTG US khz Oscillator Serial Wire ebug JUMPER LOK URT XVER PORT0 SM Photocell Potentiometer Jumper block [0///] 0+/+/+ Jumper block [///] 0-/-/- Port Headers P[:0] P[:0] P[:0] P[:0] PE[:0] JUMPER LOK I US JUMPER LOK JUMPER LOK URT XVER I EEPROM kbit PORT.V Regulator Expansion Headers SPI US FLSH Mbit JUMPER LOK User LES JUMPER LOK User Pushbutton P (Peripheral evice ontroller) GPIO Port Headers GPIOX[:0] GPIOY[:0] GPIOZ[:0] IP Switch [:0] JUMPER LOK uzzer L panel char x rows LES [:0] rawing Title: Stellaris evelopment oard Page Title: lock iagram Size ocument Number Rev 000 R ate: Thursday, May, 00 Sheet of

39 pg pg pg pg pg SYSRST_ GK GRQ SRST_ P RTK P0 P P P RSTn TO TK TMS TI TRST M_INEX M_H_ M_H_ P P P v oard onnectors J XHR 0909 P0 P P P P P P0 P P P P P P P P0 P P P P P P P U0_RX U0_TX SSI_LK SSI_FSS SSI_RX SSI_TX PWM PWM ISL IS TRST J XHR Port J XHR Port J XHR Port pg pg pg, pg, pg pg pg pg pg, pg, pg pg P P0 PE P P P P P P P P P0 P pg P P P P P P.v J J.v 9.v.v v uF 0uF 0uF TNT TNT TNT V V V XHR J XHR 0909 XHR.v.v F 00 MHz 0.uF 0.uF P0 P P0 PWM0 PWM PWM P PWM PE0 PWM PE PWM SYSRST_ P.v PE PE P PE P PE PE0 P P0 J X0 HR pg pg h h IX TK TMS TI TO h 0o/+ h P P P P P P P P P P P0 P P P P P P P PE0 PE PE PE PE PE PWM0 PWM U_RX U_TX P0 P Fault IX PWM PWM P P P P J0 XHR Port J XHR PortE JP x HR ken J SM NP U E/ OUT Vcc.KHz SM_k R. %.v 0.uF LKK.v R 0K % TILE_ pg P0 P P P P P P P P U0_RX U0_TX SSI_LK SSI_FSS SSI_RX SSI_TX ISL IS TRST J X0 HR TK P0 TMS P TI P TO P U_RX P U_TX P P PE P PE P PE P PE.v R PHOTOELL-P0 JP 0 PE PE P P PELL x HR.v R.K % JP x HR P P P pg SRST_ P P P P0 RTK P SRST_ GRQ GK TRST TI TMS TK TO R 0K % R 0K % R 0K % R 0K % R9 0K % R0 0K % R 0K % R 0K % JTG J X0 HR-SHR.v R % R 0K POT POT JP x HR JP x HR PE PE P P P P P rawing Title: Stellaris evelopment oard Page Title: oard onnectors, GPIO, JTG Size ocument Number Rev 000 R ate: Thursday, May, 00 Sheet of

40 pg pg P P0 JP U0_TX x HR JP U0_RX x HR U0_TX U0_RX U pg pg, P P JP U_TX x HR JP9 U_RX x HR R 0K % R 0K % U_TX U_RX.v R 0K % R 0K % 0.uF 0 0.uF V 0% V 0% TIN TIN ROUT 0 ROUT FOREON 0 FOREOFF MX TOUT TOUT RIN RIN 9 V+ 0.uF V 0% 9 V- 0.uF V 0% INVLI TP REY TP.v V 9 0.uF V 0% _TX0 _RX0 _TX _RX P 9_M SER0 P 9_M SER.v pg pg pg pg SPI_SEL SPI_MISO SPI_MOSI SPI_LK JP0 x HR SPIM_WP R 0K % Mbit U S V SO HOL WP SK SI TF0N.v 0.uF.v R 0K %.v JP x HR IM_ R 0K % U 0 V WP SL S T0 kbits.v 0.uF R9 0K %.v R 0 % JP IM_WP x HR.v pg, P I_S JP I_S x HR R0.0K % R.0K % pg, P I_SL JP x HR I_SL rawing Title: Stellaris evelopment oard Page Title: URT/SPI/I Size ocument Number Rev 000 R ate: Thursday, May, 00 Sheet of

41 .v R9 0K % pg P JP XHR SPI_LK PL_TK SPI_LK pg J0 x HR 0MHz_OE.v pg pg pg J x HR TEST R 0K % U OE P P P pg SYSRST_ pg TILE_ NP PL_JTG OUT J x HR PL_SLEEP.v J V 0.000MHZ.V R 0 % R 0K % XHR.v TEST LK_0M.v R 0K % JP XHR SPI_MOSI GPIOX GPIOY GPIOY_ 0 0.uF GPIOY_ PTF R 0 % GPIOY_ 9 SW GPIOY_ PT P SW GPIOY_ PT P 9 SW PT P 0 XHR R 0 % 0 0.uF JP XHR SPI_MISO JP XHR SPI_SEL SPRE pg XHR J J J XHR J PL_TO PL_TI PL_TMS PL_TK US_MO SPRE_ SPRE_ SPRE_ SPRE_ SPRE_ SPRE_ SPRE_ SPRE_0 GPIOX_0 GPIOX_ GPIOX_ GPIOX_ GPIOX_ GPIOX_ GPIOX_ GPIOX_ GPIOY_0 GPIOY_ GPIOY_.v PL_TI PL_TO PL_TMS XHR GPIOZ_ GPIOZ_ GPIOZ_ GPIOZ GPIOZ_ GPIOZ_ GPIOZ_ GPIOZ_ GPIOZ_0 R R 0K 0K % % R 0K % R.K % R0 0K % R 0K % PL PL PL PL PL PL PL PL TK TMS TI TO 0 _0 _0 9 _0 _ P 9 PL PL PL PL/GSRN PL PL/TSLL PL PL 9 PL 0 PL PL PL PL9 PL9 00 PT 99 PT 9 PT 9 PT 9 PTE 9 PTF 9 PT 9 PT 9 PT PT PT/LK0_0 PT/LK0_ PT PT PTE U0 SLEEPN SPI_MOSI pg SPI_MISO pg SPI_SEL PR PR PR PR PR 0 PR 9 PR PR PR PR PR PR PR PR 9 PR PR PR PR PR PR PR9 PR9 P 9 P 0 P P P/LK_ P P/LK_0 P 9 LMXO-T00 P P P P V V 90 VUX VIO_0 0 VIO_0 VIO_0 9 VIO_ 0 VIO_ VIO_.v pg L_RS L_RW L_En L_LIGHT L0 L L L L L L L LE0 LE LE LE LE LE LE LE 0.uF 0.uF 0 0.uF L0 L L L L L L L US_EN pg FT_I pg FT_O pg FT_S pg P pg TP TP0 0.uF 9 0.uF 0.uF R.0K % 0.uF 0.uF 9 0.uF P P pg pg Q MMT90 R 0K ONTRST SW0 SW SW SW SW SW0 SW SW SW SW SW SW SW NP NP v R 0. % R.K % R.K % NP L_ONTRST R 0K % R9 0K % R0 0K % R 0K % R 0K % R 0K % R 0K % R 0K % R 0 % R 0 % R 0 % R 0 % R9 0 % R0 0 % R 0 % v GREEN LE LE0 GREEN LE LE GREEN LE LE GREEN LE LE GREEN LE LE GREEN LE LE GREEN LE LE EUG SW ON uF GREEN LE LE SW IP- Rocker 9 0 J XHR.v U L isplay x rawing Title: Stellaris evelopment oard Page Title: P, L isplay Size ocument Number Rev 000 R ate: Thursday, May, 00 Sheet of

42 SW SYSRST 0.uF U MR V RESET MX.v R 0K % 0.uF SYSRST_ pg,.v R 0K % SW USER JP9 USER_P x HR P pg TL TL TL TL FI 0 Mil Pad 00 Mil Mask FI 0 Mil Pad 00 Mil Mask FI 0 Mil Pad 00 Mil Mask FI 0 Mil Pad 00 Mil Mask FI 0 Mil Pad 00 Mil Mask FI 0 Mil Pad 00 Mil Mask FI 0 Mil Pad 00 Mil Mask FI 0 Mil Pad 00 Mil Mask pg SRST_ JP0 LINK_SRST x HR Fiducials v JP x HR PWM_uzzer pg P0 JP PWM x HR R.K % R.0K % R9 % GREEN LE PWM_LE Z Q MMT90 R0. % + - UZZER EM-0S pg pg pg, pg, pg pg pg, pg P0 P P P P0 P P P JP ULE0 x HR JP ULE x HR JP ULE x HR JP ULE x HR JP ULE x HR JP ULE x HR JP9 ULE x HR JP0 ULE x HR R 0 % R 0 % R 0 % R 0 % R 0 % R 0 % R 0 % R9 0 % 9 GREEN LE ULE0 0 GREEN LE ULE GREEN LE ULE GREEN LE ULE GREEN LE ULE GREEN LE ULE GREEN LE ULE GREEN LE ULE Notes:. Power provided by external v supply or US port, as selected by switch S.. Use of US power requires a high power port (00m). US_v J9 RP-cd 0 N9 v S 0MSQE R0 % GREEN LE.0V + uf TNT V.0V TL 0.uF R 0K % U9 VIN EN T T MI09 VOUT J.V TL 0 pf R.K % R + K uf % TNT V.v R 0 % 9 GREEN LE.V J Term_lock_V_pos N9 rawing Title: Stellaris evelopment oard Page Title: Power, Reset Size ocument Number Rev 000 R ate: Thursday, May, 00 Sheet of

43 J US_ - V S S + G.v v F 00 MHz US_v R9 % R0 % 0.uF R.0K % U VOUT USM USP US0 US US US US US US US US0 US US US SI/WU TK/SK TI/O TO/I TMS/S TP TP TP TP TP TP R9 0K % R9 0K % R 0K % R 0 R9 0 R 0 P0 pg FT_O pg FT_I pg FT_S pg US_EN pg US_MO pg JP x HR US_OFF U K X V S SK N I O T9-0SI-. US_v R9 0K % R9 0K % R 0K % R.K % Y.000MHz pf 0V 0% pf 0V 0% R 0K % 9 EES EESK EET TEST XTIN XTOUT RESET# RSTOUT# FT US0 0 US 9 US US US US US US US0 0 US 9 US US SI/WU PWREN# SWO V V VIO VIO V R % 9 0.uF TP TP0 TP9 TP TP TP TP TP TP TP TP9 F 00 MHz 0.uF JP x HR US_MO NP.v 0.uF 0.uF R90.0K % NP v 0.uF R9.0K % NP P JP x HR US_EN NP pg rawing Title: Stellaris evelopment oard Page Title: US to Serial Wire ebug Size ocument Number Rev 000 R ate: Thursday, May, 00 Sheet of

44 Table of ontents Page escription Table of ontents / Revision ontrol LMSXX, Socket, onnectors Luminary Micro, Inc. 99 S. apital of Texas Hwy ustin, TX This document contains information proprietary to Luminary Micro Inc. and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of Luminary Micro, Inc. opyright 00 Luminary Micro, Inc. ll rights reserved. esigner: rawing Title: rnaldo ruz rawn by: Page Title: rnaldo ruz Table of ontents Stellaris aughterboard pproved: Size ocument Number Rev <pprover> 000 R ate: Saturday, March, 00 Sheet of

45 v RSTn P TO P0 P P P TK TMS TI TRST J x SKT P0 P P P P P P P0 P XP.v J J.v 9.v.v uF 0uF TNT TNT V V x SKT x SKT J x SKT TL TL TL TL P P P LKK JP XHR P_MUX.v R 0. Ohm 0.% V TL FI 0 Mil Pad 00 Mil Mask FI 0 Mil Pad 00 Mil Mask U FI 0 Mil Pad 00 Mil Mask FI 0 Mil Pad 00 Mil Mask 0.uF P P P P RSTn LO OS0 OS P0 P P P 9 0 P P P P P P P P P9 P0 P P P P SOP P P P P P P P P P0 P9 P P P P 0 9 P0 P P P P P P P0 P P 0.uF 0.uF Fiducials SOKET_SOP NP U P0 P P P P P P0/U0Rx P/U0Tx P/SSIlk P/SSIFss P/SSIRx P/SSITx P0/P0 9 P/KHz 0 P/ISL P/IS P/0- P/-/0o P/0+/P P/TRST P0 P P P P P P P J SM R. % pf 0V 0% J 9 Y.000MHz J 9 OS0 OS pf 0V 0% P0 P P P RSTn 9 0 P0/TK/SWLK P/TMS/SWIO P/TI P/TO/SWO OS0 OS RST LMSXX_SOP LO V V V.v TL 9 0.uF 0 0.uF.v 0.uF LO TL LO uf 0.uF V 0% rawing Title: Stellaris aughterboard Page Title: LMSXX, Socket, onnectors Size ocument Number Rev 000 R ate: Saturday, March, 00 Sheet of

46 Table of ontents Page escription Table of ontents / Revision ontrol LMSXXX, onnectors Luminary Micro, Inc. 99 S. apital of Texas Hwy ustin, TX This document contains information proprietary to Luminary Micro Inc. and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of Luminary Micro, Inc. opyright 00 Luminary Micro, Inc. ll rights reserved. esigner: rawing Title: rnaldo ruz rawn by: Page Title: rnaldo ruz Table of ontents Stellaris aughterboard pproved: Size ocument Number Rev <pprover> 000 R ate: Thursday, May, 00 Sheet of

47 RSTn RSTn P TO P P P P0 P P P TK TMS TI TRST v J x SKT XP P0 XPE P P P P P P P P P0 P.v J J.v 9.v.v v uF 0uF 0uF TNT TNT TNT V V V x SKT x SKT PE PE P PE P PE PE0 P P0 J x SKT P P P P P XP LKK JP XHR P P XP TL TL TL TL JP XHR P P XP JP XHR PE PE XPE P0 P P P P P P0 P P P P P P P U P0/U0Rx P/U0Tx P/SSIlk P/SSIFss P/SSIRx P/SSITx P0/TK/SWLK P/TMS/SWIO P/TI P/TO/SWO P/P/Ph P/+/o/0o/P P/+/o/P/Ph P/-/P P0/PWM/P0 9 P/PWM/P 0 P/ISL P/IS P/0- P/-/P P/0+ P/TRST P0/PWM0 P/PWM P/URx P/UTx P//P0 P//P P//Fault P//0o/IX P0 P P P P P P P P0 P P P P P P P FI 0 Mil Pad 00 Mil Mask FI 0 Mil Pad 00 Mil Mask FI FI 0 Mil Pad 0 Mil Pad 00 Mil Mask 00 Mil Mask Fiducials J SM R. % pf 0V 0% J 9 Y.000MHz J 9 pf 0V 0% PE0 PE PE PE PE PE RSTn OS0 OS 9 0 PE0/PWM PE/PWM PE//P PE//P PE//P PE/0/P OS0 OS RST LMSXXX_QFP LO V V V V.v 0. uf 9 0. uf 0 0. uf 0. uf.v TL + 0uF TNT V uf LO 0.uF V 0% LO TL 0.0 uf 0.0 uf 0.0 uf 0.0 uf + 0uF TNT V 0. uf NP 9 0. uf NP 0 0. uf NP 0. uf NP + 0uF TNT V NP + 0uF TNT V NP uf NP 0.uF V 0% NP 0.0 uf NP 0.0 uf NP 0.0 uf NP uf NP Located on bottom layer rawing Title: Stellaris aughterboard Page Title: LMSXXX, onnectors Size ocument Number Rev 000 R ate: Thursday, May, 00 Sheet of

48 Table of ontents Page escription Table of ontents / Revision ontrol LMSXXX, Socket, onnectors Luminary Micro, Inc. 99 S. apital of Texas Hwy ustin, TX This document contains information proprietary to Luminary Micro Inc. and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of Luminary Micro, Inc. opyright 00 Luminary Micro, Inc. ll rights reserved. esigner: rawing Title: rnaldo ruz rawn by: Page Title: rnaldo ruz Table of ontents Stellaris aughterboard pproved: Size ocument Number Rev <pprover> 000 R ate: Saturday, March, 00 Sheet of

49 RSTn RSTn P TO P P P P0 P P P TK TMS TI TRST v J x SKT XP P0 XPE P P P P P P P P P0 P.v J J.v 9.v.v v uF 0uF 0uF TNT TNT TNT V V V x SKT x SKT PE PE P PE P PE PE0 P P0 J x SKT P P P P P XP LKK JP XHR P P XP TL TL TL TL JP XHR P P XP JP XHR PE PE XPE FI 0 Mil Pad 00 Mil Mask FI 0 Mil Pad 00 Mil Mask V TL.v P P P P P P P P P0 P P P R 0. Ohm 0.% U 0 9 FI 0 Mil Pad 00 Mil Mask FI 0 Mil Pad 00 Mil Mask P P P P P P P P P0 P9 P P 0.uF PE PE PE PE RSTn LO OS0 OS P P 0.uF P P P P P P P P 9 P9 0 P0 P P SOKET_QFP NP P P P P P P P9 P0 P P P P 9 0 P P QFP P0 P P P P P P P P P P P P0 P9 P P P P uF PE PE0 P P P P0 P P P P0 0.uF P0 P P P P P P0 P P P P P P P U P0/U0Rx P/U0Tx P/SSIlk P/SSIFss P/SSIRx P/SSITx P0/TK/SWLK P/TMS/SWIO P/TI P/TO/SWO P/P/Ph P/+/o/0o/P P/+/o/P/Ph P/-/P P0/PWM/P0 9 P/PWM/P 0 P/ISL P/IS P/0- P/-/P P/0+ P/TRST P0/PWM0 P/PWM P/URx P/UTx P//P0 P//P P//Fault P//0o/IX P0 P P P P P P P P0 P P P P P P P Fiducials J SM R. % pf 0V 0% J 9 Y.000MHz J 9 pf 0V 0% PE0 PE PE PE PE PE RSTn OS0 OS 9 0 PE0/PWM PE/PWM PE//P PE//P PE//P PE/0/P OS0 OS RST LMSXXX_QFP LO V V V V.v TL 0.uF 9 0.uF.v 0 0.uF 0.uF LO uf LO TL 0.uF V 0% rawing Title: Stellaris aughterboard Page Title: LMSXXX, Socket, onnectors Size ocument Number Rev 000 R ate: Saturday, March, 00 Sheet of