FX18 DDR0/DDR1. PCIe/SD/SPI/CONFIG
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- Alan Montgomery
- 6 years ago
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1 ate: feb 0 Kiad... ev: V Size: Id: / Title: alatea ile: alatea.sch Sheet: / License: Y-S PowerSypply PowerSypply.sch X NK()/NK(X) 0/ PIe/S/SPI/ONI NK()/NK0(X)/TP P OUPLIN POW SUPPLY.sch 0_[0..] 0_[0..] 0_K 0_K_P 0_K_N 0_Q[0..] 0_LM 0_OT 0_ST_N 0_S_N 0_S_N 0_W_N 0_UM 0_LQS_P 0_LQS_N 0_UQS_P 0_UQS_N 0_ZQ _[0..] _[0..] _K _K_P _K_N _Q[0..] _LM _OT _ST_N _S_N _S_N _W_N _UM _LQS_P _LQS_N _UQS_P _UQS_N _ZQ PPower PPower.sch INIT_ TK TI P_PO_ P_TO HSWP P_TO P_TO TK TK TO TO Mxpansion Mxpansion.sch MTTXP MTTXN MTLKP MTLKN MTXP MTXN PIO_N_[..] PIO_P_[..] TK P_TO TO PIO_N_[..] PIO_P_[..] PIO_N_[..] PIO_P_[..] PIO_N_[..] PIO_P_[..] PIO_P_[..0] PIO_N_[..0] TI HSWP HSWP P P.sch P_M0_MP_MISO SPI MISO SPI_O_IN_MISO SPI_S_N SPI_LK SPI_MOSI_SI_N_MISO0 SPI MISO P_M INIT K _K_N _K_P _Q[0..] _LM _OT _ST_N _UM _S_N _S_N _W_N _UQS_N _UQS_P _LQS_N _LQS_P _[0..] _[0..] S_T0 S_T S_T S_T S_M S_LK USLK LK TTX TX PIO_P_[..] PIO_N_[..] PIO_N_[..] PIO_P_[..] TS P_ P_.sch 0_Q[0..] 0_[0..] 0_UQS_P 0_UQS_N 0_LQS_P 0_LQS_N 0_UM 0_LM 0_S_N 0_S_N 0_K_P 0_K_N 0_W_N 0_ST_N 0_[0..] 0_OT 0_K PI_TX0_P PI_TX0_N PI_X0_P PI_X0_N PI_LK_QO_P PI_LK_QO_N MTTXP MTTXN MTLKP MTLKN MTXP MTXN PIO_N_[..] PIO_P_[..] LK PI_PST_N HSWP PIO_N_[..] PIO_P_[..] PIO_N_[..0] PIO_P_[..0] LK_P LK_N LK_P LK_N TI TI TS TS PIe PIe.sch PI_PST_N PI_LK_QO_P PI_LK_QO_N PI_TXO_P PI_XO_P PI_XO_N PI_TX0_N SPI MISO SPI_O_IN_MISO SPI_S_N SPI_MOSI_SI_N_MISO0 SPI_LK SPI MISO P_M0_MP_MISO P_M P_PO_ S_T0 S_T S_LK S_M S_T S_T TI TO TK USLK LK LK TTX TX TS LK_N LK_P LK_P LK_N LK_N LK_P LK_P LK_N LK_N LK_P LK_P LK_N
2 ate: feb 0 Kiad... ev: V Size: Id: / Title: alatea ile: PowerSypply.sch Sheet: /PowerSypply/ License: Y-S V V SS P N P P SW 0 SW VST PWP U TPS L.UH.K.K.N 00K U 0K 0U 0U U V V SS P N P P SW 0 SW VST PWP U TPS L.UH.K.K 0.N 00K U 0K 0U 0U U V V SS P N P P SW 0 SW VST PWP U TPS L.UH 0.K.K.N 00K U 0K 0U 0U U.V TPV V N POO VST OVP 0 MO 0 TP V U TPS 00K U 00K 0K 0 00K.K K.U U 0 U V V L.UH 00K 0 N.K 0K 00U N VLOIN P SNS N POO 0 U TPS00 V VV 0K 0K 0.00U 0U 0U 0U 0U 0U 00K 0.U VV VV VV VV VV TPV VV VTT0 U U U V V V N VLOIN P SNS N POO 0 U TPS00 0K 0K 0.00U 0U 0 0U 0U 0 0U 0U 00K.U VV VV VTT VTT0 VTT P VI U LM0_N U U U 0U 0U 0U 0U 0 U U 00U 00U 0U 0U 0U 0U 0U 0U U 0U 0U 0U 0 0U? IOSH V V
3 0 0 ate: feb 0 Kiad... ev: V Size: Id: / Title: alatea ile:.sch Sheet: // License: Y-S Q Q Q Q Q Q VQ H N J OT K N L M N P T Q Q Q Q Q Q Q H J K S_N L 0 M N P ST_N T Q Q UM Q0 LQS LQS_N Q H S_N J S_N K W_N L M 0 N P T Q UQS_N UQS Q LM Q Q H K J K_N K 0/P L N M /_N N P /N T Q Q Q0 Q Q Q Q H J K ZQ L V M N P T Q Q Q Q Q Q H N J K K N L M N P T U MTJM VTT0 00 VV VV 00 K K K VV VTT0 0_0 0_ 0_ 0_ 0_ 0_ 0_ 0_ 0_ 0_ 0_0 0_ 0_ 0_ 0_ 0_[0..] 0_0 0_ 0_ 0_[0..] 0_K 0_K_P 0_K_N 0_Q0 0_Q 0_Q 0_Q 0_Q 0_Q 0_Q 0_Q 0_Q 0_Q 0_Q0 0_Q 0_Q 0_Q 0_Q 0_Q 0_Q[0..] 0_LM 0_OT 0_ST_N 0_S_N 0_S_N 0_W_N 0_UM 0_LQS_P 0_LQS_N 0_UQS_P 0_UQS_N VV VTT0 0_ZQ VTT VV VTT VV Q Q Q Q Q Q VQ H N J OT K N L M N P T Q Q Q Q Q Q Q H J K S_N L 0 M N P ST_N T Q Q UM Q0 LQS LQS_N Q H S_N J S_N K W_N L M 0 N P T Q UQS_N UQS Q LM Q Q H K J K_N K 0/P L N M /_N N P /N T Q Q Q0 Q Q Q Q H J K ZQ L V M N P T Q Q Q Q Q Q H N J K K N L M N P T U MTJM..... VTT 00 VV VV 00 K 0 K K _[0..] _[0..] _K _K_P _K_N _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q[0..] _LM _OT _ST_N _S_N _S_N _W_N _UM _LQS_P _LQS_N _UQS_P _UQS_N VTT _ZQ VTT _0 0 _ VTT VTT0 SN SN SN _0 SN WN WN 0 _0 0_ 0_0 0_ 0_ 0_ 0_ 0_ 0_ 0_0 0_ 0_ 0_ 0_ SN0 SN0 W0 SN0 SN0 W0 0_ 0_ 0_ 0_ 0_0
4 0 0 ate: feb 0 Kiad... ev: V Size: Id: / Title: alatea ile: PPower.sch Sheet: /PPower/ License: Y-S _ L W _0 J _ N _ U _ W _0 _ L _ V _ T _0 0 0 TK _ L W _ V POM T 0 *US P _ L *VTT T _ V _0 TO *VS U _ TI _ J _ N _ U MPS V _0 ON_ SUSPN U0 XSLX0T SUSPN HSWP ON PO SUSPN VS S.K S J N U V L VUX VUX V H U W J VUX L VUX N VUX H J K L M N P 0 J0 K0 L0 M0 N0 P0 VUX 0 V0 VUX J K L M N P VUX U J N U VUX J K L M N P VUX J K L M N P J K L M N P V VUX H J VUX K VUX M W N L W U0 XSLX0T VV VV VV 0 0 L ON K VV.K VV PO INIT_.K VV TK TI P_TO VV VV VV VV 0 VV P_PO_ VV.K HSWP VV VV VV.K.K VTT VTT VS VV VV
5 ate: feb 0 Kiad... ev: V Size: Id: / Title: alatea ile: Mxpansion.sch Sheet: /Mxpansion/ License: Y-S P HIOS_0PIN MTTXP MTTXN MTLKP MTLKN MTXP MTXN V VV TPV V PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_0 PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_0 PIO_N_ PIO_N_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_0 PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_0 PIO_P_ PIO_P_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_0 PIO_N_ PIO_N_ PIO_P_ PIO_P_ PIO_P_ PIO_P_0 PIO_P_ PIO_P_ PIO_N_[..] PIO_P_[..] PIO_N_[..] PIO_P_[..] PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_0 PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_0 PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_N_[..] PIO_P_[..] PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_0 PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_0 PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_0 PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_0 PIO_N_[..] PIO_P_[..] PIO_P_[..0] PIO_N_[..0] PIO_P_ P HIOS_0PIN MTTXP MTTXN MTLKP MTLKN MTXP MTXN V VV V TK P_TO TK TK VV V V TI O X TO OM X X_TO X_TO X_TO TO X_TO P_TO JT SLTION TI O X TO OM X X_TO PIO_N_ PIO_P_ P TI H P H P
6 0 0 ate: feb 0 Kiad... ev: V Size: Id: / Title: alatea ile: P.sch Sheet: /P/ License: Y-S IO_LP_INIT Y IO_LP Y IO_LN U *IO_L0P_ W *IO_L0N_ Y IO_LP T *IO_LP_ V IO_LP_ Y *IO_LN_ *IO_LP_ T *IO_LN_ U *IO_LN_ W IO_LN_W V_ Y *IO_LP_ *IO_L0P_ U *IO_L0N_ V IO_LP W IO_LP_ Y *IO_LP_ T0 *IO_LN_ U0 *IO_LP_ W0 *IO_LN_ Y0 IO_LP_LK_ Y0 *IO_LP_ *IO_LN_ T *IO_LP_ V *IO_LN_ W IO_LP_LK_ Y IO_LP_LK_ T IO_LN_LK_ U IO_L0P_ W IO_L0N_ Y IO_LP MISO_ IO_LN_V_ U *IO_LP_ V *IO_LN_ W IO_L0P_LK Y IO_LN_SO IO_LN MISO_ T IO_LP_ U *IO_L0P_ W *IO_L0N_ Y IO_LP_ IO_LN_ *IO_LP_ T *IO_LN_ U *IO_LN_V_ V *IO_LN_ W IO_LP_ Y IO_LN *IO_LP_ U *IO_LP_ Y IO_LP IO_LN IO_LP_MPLK_ V *IO_LP_ W IO_LP_ Y IO_LN_ IO_LN_MPMOSI_ W *IO_LN_ Y IO_LP_ IO_LN_ IO_LP_M_ Y IO_LN_ IO_LP_ 0 IO_LN_V_ 0 IO_LP_0_IN_MISO_MISO_ 0 IO_LN_MOSI_SI MISO0_ 0 IO_LN_LK_ IO_LN_M0_MPMISO_ IO_LP_LK IO_LN_LK0 IO_L0N_LK0_USLK_ IO_LP_ IO_LN_ IO_LN_ IO_LP_ IO_LN_ IO_LN_ IO_LP IO_LN IO_LN_0_ U0 XSLX0T IO_L0P_ 0 IO_LP M_ 0 IO_LN M_ 0 IO_LP M_ 0 IO_LN M_ H0 IO_LP_M_ J0 IO_LP MLK_ K0 IO_LP_LK_MQ_ L0 IO_L0P_LK_M_ M0 IO_LP MLQS_ N0 IO_LP_LK_MUM_ P0 IO_LP_W MQ0_ 0 IO_LN_ T0 IO_LP_MQ0_ U0 IO_LN USY_ V0 IO_LP_MQ_ W0 *IO_L0P_ *IO_LP_ IO_LP MK_ IO_LP M0_ H IO_LP_LK_IY_MSN_ K IO_LP MQ_ M IO_LP_S MQ_ P IO_LP_H_MQ_ T IO_L0P_MUQS_ V IO_LP_MQ_ Y *IO_L0N_ IO_L0N_ *IO_LN_V_ IO_LN M_ IO_LN M_ IO_LN_0_M_ IO_LN M_ H IO_LN_MOT_ J IO_LN_LK_MSN_ K IO_LN_LK_MQ_ L IO_LN MQ_ M IO_LN_0_MLQSN_ N IO_LN_O MQ_ P IO_LN_L_MQ_ IO_LN_MQ_ T IO_LN_MQ_ U IO_L0N_MUQSN_ V IO_LN_MQ_ W IO_LN_MQ_ Y *IO_LP_ L *IO_LN_ N *IO_L0P_ *IO_LP_ H IO_LP_ J *IO_LN_ K *IO_LP_ M IO_L0P_ N IO_L0N_ P *IO_L0N_ *IO_LN_ H IO_LN_ J IO_LP M0_ K IO_LN M_ L IO_LP_ M *IO_LP_ P *IO_LP_ *IO_LN_ T IO_LP IO_L0P MST_ H IO_LN M_ K IO_LN_ M *IO_LN_ P *IO_LN_ T IO_LN V_ IO_LP M_ IO_L0N_0_M_ H IO_LP M0_ J IO_LP MW_ K IO_LN MLKN_ L IO_L0N_LK0_M_ M IO_LN_LK_TY_MLM_ N IO_LP_ P IO_LN_V_ *IO_LP_ T IO_LP_ U IO_LP_WK_ V U0 XSLX0T P_M0_MP_MISO SPI MISO SPI_O_IN_MISO SPI_S_N SPI_LK SPI_MOSI_SI_N_MISO0 SPI MISO P_M INIT 0 _0 _0 _K _K_N _K_P _Q[0..] _LM _OT _ST_N _UM _S_N _S_N _W_N _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q UQS_N _UQS_P _LQS_N _LQS_P _[0..] _[0..] S_T0 S_T S_T S_T S_M S_LK PIO_N_ PIO_N_ PIO_N_0 PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_0 PIO_N_ PIO_N_ PIO_P_ PIO_P_ PIO_P_0 PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_N_ PIO_P_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_N_ PIO_N_ PIO_N_ PIO_P_ PIO_P_ PIO_P_ PIO_P_0 PIO_P_ PIO_P_[..] PIO_N_[..] PIO_N_[..] PIO_P_[..] VTT USLK LK 0 TTX TX XLK0 XLK XLK XLK0 U SM_ON U SM_ON SWITH SWITH SW SW_PUSH VTT VTT TS SM ONNTO
7 0 0 ate: feb 0 Kiad... ev: Size: Id: / Title: alatea ile: P_.sch Sheet: /P_/ License: Y-S IO_LN_V_ IO_LP_ IO_LN_ IO_LN_M_ IO_LN_M_ IO_LN_M_ IO_L0N_M_ H IO_LN_M_ J IO_LN_M_ K IO_LN_LK_MQ_ L IO_L0N_MQ_ M IO_LN_MLQSN_ N IO_LN_MQ_ P IO_LN_MQ_ IO_LN_MQ_ T IO_LN_MQ_ U IO_LN_MUQSN_ V IO_LN_MQ_ W IO_LN_MQ_ Y IO_LP_ IO_LP_MK_ IO_L0P_MW_ H IO_LP_M0_ K IO_L0P_MQ_ M IO_LP_MQ_ P IO_LP_MQ_ T IO_LP_MUQS_ V IO_LP_MQ_ Y IO_LP_MST_ IO_L0P_ IO_LP_M_ IO_LN_M_ H IO_LP_M0_ J IO_LN_MLKN_ K IO_LP_LK_MQ_ L IO_LP_LK_M_ M IO_LP_MLQS_ N IO_LP_LK_TY_MUM_ P IO_LP_MQ0_ *IO_LP_ T IO_LP_MQ0_ U *IO_LN_ V IO_LP_MQ_ W IO_LN_ Y IO_L0N_ *IO_LN_ *IO_LP_ H IO_LP_M0_ J IO_LP_MLK_ K IO_LN_LK0_M_ L IO_LN_LK_IY_MSN_ M IO_LN_LK_MLM_ N IO_LN_ P *IO_LN_ *IO_LN_ T *IO_LP_ U IO_LP_ W *IO_LP_ IO_LN_M_ H IO_LN_M_ K IO_LP_LK_MSN_ M IO_LP_ P *IO_LN_ T *IO_LP_ V *IO_LN_ *IO_L0P_ H IO_LP_M_ J IO_LP_M_ K IO_LN_MOT_ L IO_LP_M_ M *IO_LP_ N *IO_LP_ P *IO_LP_ T *IO_L0N_ *IO_LP_ J *IO_LP_ K IO_LP_ M *IO_LN_ N *IO_LN_ P IO_LP_ *IO_LN_ H *IO_LN_V_ K IO_LN_V_ M IO_LN_V_ P IO_L0N_ IO_L0P_ U0 XSLX0T 0_ 0_ 0_ 0_ST_N 0_ 0_K 0_ 0_ 0_ 0_0 0_ 0_W_N 0_ 0_ 0_ 0_0 0_ 0_0 0_K_N 0_K_P 0_OT 0_ 0_ 0_ 0_S_N 0_S_N 0_LM 0_UM 0_Q 0_Q 0_Q 0_Q 0_Q 0_Q 0_Q0 0_Q 0_Q 0_Q 0_Q0 0_Q 0_Q 0_Q 0_Q 0_LQS_N 0_LQS_P 0_UQS_P 0_UQS_N 0_Q[0..] 0_[0..] 0_UQS_P 0_UQS_N 0_LQS_P 0_LQS_N 0_UM 0_LM 0_S_N 0_S_N 0_K_P 0_K_N 0_W_N 0_ST_N 0_[0..] 0_Q 0_OT 0_K IO_LN_0 IO_LP_0 IO_LN_0 IO_LP_0 IO_LP_HSWPN_0 IO_LN_V_0 IO_LN_0 IO_LP_0 IO_LP_0 IO_LN_V_0 IO_LP_0 IO_LN_0 IO_LP_0 MTTXN0_0 MTTXP0_0 IO_LN_0 MTVTTTX_0 MTXN0_0 MTXP0_0 IO_LP_0 MTTXN_0 MTTXP_0 MTVTTX_0 MTVTTL_0 IO_LN_0 IO_LP_0 MTVP0_0 MTXN_0 MTXP_0 MT_0 IO_LN_0 IO_LP_LK_0 MTLK0P_0 0 MTLK0N_0 0 MTV_0 0 MTV_ 0 IO_LN_LK_0 0 IO_LP_0 H0 IO_LN_SP_0 0 IO_LP_SP_0 0 MTLKP_0 MTLKN_0 IO_LN_LK_0 IO_LN_0 H *MTLK0P_ *MTLK0N_ MTVP_0 *MTLKP_ *MTLKN_ IO_LP_LK_0 H *MTVP0_ *MTXN0_ *MTXP0_ *MTVP_ IO_LN_V_0 IO_LP_0 H *MTTXN0_ *MTTXP0_ MTVTTX_ IO_LP_LK_0 IO_LP_0 H MTVTTTX_ *MTXN_ *MTXP_ IO_LN_LK_0 IO_LN_0 *MTTXN_ *MTTXP_ IO_LP_LK_0 IO_LN_LK_0 IO_LP_0 IO_L0N_0 IO_L0P_0 IO_LP_SP_0 IO_LN_0 IO_LN_SP_0 IO_LP_SP_0 IO_LN_SP0_0 IO_LP_0 IO_LN_SP_0 IO_LP_SP_0 IO_LN_V_0 U0 XSLX0T PI_TX0_P PI_TX0_N PI_X0_P PI_X0_N PI_LK_QO_P PI_LK_QO_N shield U ST shield U ST MTTXP MTTXN MTLKP MTLKN MTXP MTXN PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_0 PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_0 PIO_N_ PIO_N_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_0 PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_0 PIO_P_ PIO_P_ PIO_N_[..] PIO_P_[..]. PIO_N_ PIO_N_ PIO_N_0 PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_ PIO_N_0 PIO_P_ PIO_P_ PIO_P_0 PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_ PIO_P_0 PIO_N_[..] PIO_P_[..] PIO_N_[..0] PIO_P_[..0] TPV VTT0 00 TPV TPV LK PI_PST_N 0 PIO_N_ PIO_P_ HSWP HSWP VTT0 VTT0 LK_P LK_N LK_P LK_N
8 ate: feb 0 Kiad... ev: V Size: Id: / Title: alatea ile: PIe.sch Sheet: /PIe/ License: Y-S PSNT# +V +V +V +V +V TK SMLK TI SMT TO +V +V TST# +V 0 V_UX 0 PST# WK# SV LK+ LK- PTP0 PTN0 PP0 PN0 PSNT# U XPI VV PI_PSNT_ PI_PSNT_ PI_PST_N PI_LK_QO_P PI_LK_QO_N PI_TXO_P PI_TX0_N PI_XO_P PI_XO_N #S 0(IO) #WP(IO) I(IO0) LK #HL/#ST(IO) V U WQVI 0 VV VV SPI MISO SPI_O_IN_MISO SPI_S_N SPI_MOSI_SI_N_MISO0 SPI_LK SPI MISO JP JUMP JP JUMP P_M0_MP_MISO P_M P_PO_ SPI_S_N SPI_MOSI_SI_N_MISO0 SPI_O_IN_MISO SPI_LK VV 0 00K 00K 00K 00K 00K S_T0 S_T S_LK S_M S_T S_T VV VV TI TO TK JT H / V U XO-H 0 K VV USLK P / V U XO-H K 0 VV LK 0 P / V U XO-H K 0 VV LK 0 P N S I V SK O SV SHIL SHIL 0 SHIL SHIL U MIO_S TX T TS VIO X I N S 0 V 0 TS US US US US0 US N US+ US- TST UT OSI OSO ST U0 TLNW Vbus - + I J US_MINI 0 VV TTX TX 0 P K VV IOSH V P VV 0 0K 0K VV 0K TS 0 / N _# V U XO-L VV K 0.0U 00 / N _# V U XO-L VV K 0.0U 00 LK_N LK_P LK_P LK_N 0 0MHz TP LOK 0MHz TP LOK 00MHz LOK 00MHz LOK 00MHz LOK SPI H QU SPI UT PIe MIO S
Power USB I/F. USB->Uart AX309. Power LED :25:33 I:\AX\AX309\2.0\1_POWER.SchDoc VBUS VBUS D- D+ Fuse VCC GND D3V3 U
X0.0 0-- :: I:\X\X0\.0\_POWER.Schoc ate: R K Power LE LE SW SW V P P P V V F Fuse U SRV0- VUS P M RX TX LE RX LE TX R K R K VUS - I J US->Uart US I/F E 00uF/V OUT IN = U -. V E 00uF/V OUT IN = U -. V E
DOCUMENT NUMBER PAGE SECRET
OUMENT NUMER PGE SERET / SERET OUMENT NUMER PGE / Spartan onfiguration SPI Flash Q S V W/VPP HOL VSS U MPVME R 0 R.K 0.U 9 IO_LP 0 IO_LN VREF_ G IO_L9P_ G IO_L9N_ F IO_L0P_ F IO_L0N_ IO_L9P_ IO_L9N_ 0
ADC IF1_P IF1_N INT_OSC_EN INT_OSC_EN ADC_PWDN ADC_PWDN INT_OSC_EN ADC_PWDN UC_CTRL[1-2] UC_DATA[0-7] FPGA_PROG[1-5] RF_POWER_DET
![ADC IF1_P IF1_N INT_OSC_EN INT_OSC_EN ADC_PWDN ADC_PWDN INT_OSC_EN ADC_PWDN UC_CTRL[1-2] UC_DATA[0-7] FPGA_PROG[1-5] RF_POWER_DET](/thumbs/93/112794925.jpg "ADC IF1_P IF1_N INT_OSC_EN INT_OSC_EN ADC_PWDN ADC_PWDN INT_OSC_EN ADC_PWDN UC_CTRL[1-2] UC_DATA[0-7] FPGA_PROG[1-5] RF_POWER_DET")
MIXER FPG RF RF_MP_OUT RF_MP_OUT RF_POWER_ET RF_MP_ MIXER LOP LON IF_P IF_N IF_P IF_N T_OS_EN _PWN IF_P IF_N T_OS_EN _PWN _LK _[0-] _OR _LK _[0-] _OR LK_REF _LK _[0-] _OR LK_REF RF_G_TRL RF_G_TRL RF_G_TRL
Mounted: No OSC5. positive frequency shift. C138 GND. 25MHz OSC1 C nF 50V X7R GND 50V X7R 0603 GND P3V3 P3V3 R78 R77. 10k. 10k 0.1W 0.
Start up clock. onnected directly to the FPG. nf nf V nf PLL_OUT V nf OS +Vs OUT V V OS MHz GN_TXO_V V V V MHz OUT V V OS MHz OS +Vs OUT V Stable clock for low drift and low jitter. onnected to the FPG
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