K2L SCHEMATICS MAJOR REVISION HISTORY : I2C ADDRESS TABLE : PCB LAYER STACK-UP DETAILS : PCB MECHANICAL DETAILS : NOTES, UNLESS OTHERWISE SPECIFIED :

Transcription

1 KL SHEMTIS MJOR REVISION HISTORY : I RESS TLE : P REV. SH. REV. ESRIPTION TE REF ES ESRIPTION IT RESS.0.0 Pre-Proto uild -ec eta uild 0-Sep-0 EEPROM I EEPROM MIT MHZ SO 0x0.0.0 Production uild -Nov-0 U0 I SP EEPROM KIT 00KHZ TSSOP 0x P MEHNIL ETILS : P LYER STK-UP ETILS :. P SIZE:." x." x 0.0". P MTERIL: T. MER OF LYERS:. IMPENE ONTROL: YES NOTES, UNLESS OTHERWISE SPEIFIE :. RESISTNE VLUES RE IN OHMS.. PITNE VLUES RE IN MIROFRS.. PRTS NOT INSTLLE RE INITE WITH ''.. SIGNL NET NMES WITH "#" SUFFIX, RE TIVE LOW SIGNLS. ISLIMER: THIS IRUIT ESIGN IS PROVIE S REFERENE ONLY, WITHOUT WRRNTY EXPRESSE OR IMPLIE. THE USER IS ENOURGE TO PERFORM LL UE ILIGENE WITH RESPET TO ESIGN N NLYSIS. FOR OMMITTE PERFORMNE N FUNTIONLITY OF THE EVIE, PLESE REFER TO THE EVIE T ML. opyright () 0 Texas Instruments Incorporated. ll rights reserved. KL EVM esigned for TI by einfochips OVER PGE ocument Number _00_0.0 ate: Monday, June, 0 of

2 SHEMTI PGE ONTENT : OVER PGE : TLE OF ONTENTS : LOK IGRM : PLEMENT : POWER ONSUMPTION : POWER SEQUENE : POWER ISTRIUTION : LOK ISTRIUTION : M LOK IGRM 0 : FM Interface to JES/RF devices- : FM Interface to JES/RF devices - : JES Serdes switch - : JES Serdes switch - : SGMII/PIe Serdes switch : FPG, SYSREF uffering, LEs : FPG, FPG pin conn, SPI Flash, LEs : FPG, KL SPI/TIM/URT, FPG test conn : KL LVS SigMux, lock Mux, KL Reset, KL ML Serdes JES/IL, : KL R 0 : R() : R(),.vaux ->.v R Vt, R SP EEPROM : KL GN N POWER : KL US, TPS US v isolation, US Type connector, magnetics, filter, SO URT./.v, US to dual URT : KL EMU, KL JTG, EMU MIPI 0, EMU etect, M/XS00 : USIM, SO URT.v switching,.v/.v GPIO INT, SO URT, GPS : Expansion onnector, I SO to Expander.v/.vux : KL EMIF, V and VSSMON, EMIFWIT bfr, NN Flash, I EEPROM : EMIF ddr/ntl uffer, Ext EMIF_OE, EMIF ata Transceiver : M Processor (LMS), switches, IPsw, URT Rx Mux, LEs 0 : L, L Power, M US for URT, pin URT for M, M : M connector : SO Temp, U00, PMus Pgm conn, VI Isolator for PMus : Ethernet PHY, Magnetics for channel/ Tx/Rx, : Ethernet PHY, Magnetics for channel/ Tx/Rx : M0 lk,./., Power Filter for lock, : M0 lk, 00 /., Power Filter for lock : XS00 / M0, flash, US connector for Emulator : XS00 / M0, boot mode, reset, XS00 power : XS00 / debug hdr, oscillators 0 : XS00 Power : XS00 Emulation PL : v input (fused), v to pv MP, KL VI, p to VPPp switch, vux to v, FM Power (fuse), : Top vatar, v to VV, v to.v,.v aux ->.v,.v aux ->.v : TPS00, v -> VV, v, v, v : KL VV, VV, bypass caps, KL v, KL v0 PLL, caps, filters : KL VLV, v filter, bypass caps, v ->.vaux : REVISION HISTORY TLE OF ONTENTS KL EVM ocument Number _00_0.0 esigned for TI by einfochips ate: Monday, June, 0 of

3 KL EVM LOK IGRM esigned for TI by einfochips ocument Number _00_0.0 ate: Monday, June, 0 of

4 PLEMENT KL EVM PLEMENT esigned for TI by einfochips ocument Number _00_0.0 ate: Monday, June, 0 of

5 POWER ONSUMPTION KL EVM POWER ONSUMPTION esigned for TI by einfochips ocument Number _00_0.0 ate: Monday, June, 0 of

6 KL EVM POWER SEQUENE esigned for TI by einfochips ocument Number _00_0.0 ate: Monday, June, 0 of

7 POWER ISTRIUTION KL EVM POWER ISTRIUTION esigned for TI by einfochips ocument Number _00_0.0 ate: Monday, June, 0 of

8 LOK ISTRIUTION KL EVM LOK ISTRIUTION esigned for TI by einfochips ocument Number _00_0.0 ate: Monday, June, 0 of

9 M LOK IGRM KE EVM M LOK IGRM esigned for TI by einfochips ocument Number _00_0.0 ate: Monday, June, 0 of

10 FM Interface to JES/RF devices - JES_TXP_FM_NET JES_TXN_FM_NET JES0_TXP_FM_NET JES0_TXN_FM_NET JES_TXP_FM_NET JES_TXN_FM_NET JES_TXP_FM_NET JES_TXN_FM_NET VIN_FM V_IN_FM JES0_RXN_FM JES0_RXP_FM JES_RXP_FM JES_RXN_FM JES_RXP_FM JES_RXN_FM JES_RXP_FM JES_RXN_FM GPIO FM_FPG_V GPIO FM_FPG_V GPIO FM_FPG_V GPIO_0_FM_FPG_V GPIO FM_FPG_V GPIO FM_FPG_V GPIO FM_FPG_V GPIO FM_FPG_V GPIO0 FM_FPG_V GPIO0 FM_FPG_V GPIO0 FM_FPG_V GPIO0 FM_FPG_V GPIO0 FM_FPG_V GPIO0 FM_FPG_V GPIO0 FM_FPG_V STTUS_0_FM_FPG_V STTUS FM_FPG_V RST#_FM_FPG_V USY#_FM_FPG_V SYS_LKP_FM SYS_LKN_FM SYSREF_N_FM SYSREF_P_FM SO_JES_SYNOUT0_P_FM SO_JES_SYNOUT0_N_FM SO_JES_SYNIN0_P_FM SO_JES_SYNIN0_N_FM SPI_S0_FM_FPG_V SPI_S_LMK_FM_FPG_V SPI_MISO_FM_FPG_V SPI_MOSI_FM_FPG_V SPI_LK_FM_FPG_V SPI_LK_LMK_FM_FPG_V SPI_MOSI_LMK_FM_FPG_V SPI_MISO/RST_LMK_FM_FPG_V GPIO0_0/GPTEST_FM_FPG_V GP_FM_FPG_V GP_FM_FPG_V GP_FM_FPG_V GP_FM_FPG_V GP_FM_FPG_V GP_FM_FPG_V GP_FM_FPG_V GP_FM_FPG_V JES0_TXP_FM JES0_TXN_FM JES_TXN_FM JES_TXP_FM IRQ_FM_FPG_V JES_TXN_FM JES_TXP_FM JES_TXN_FM JES_TXP_FM ate: ocument Number of esigned for TI by einfochips FM Interface to JES/RF devices- 0 Monday, June, 0 KL EVM _00_0.0 ate: ocument Number of esigned for TI by einfochips FM Interface to JES/RF devices- 0 Monday, June, 0 KL EVM _00_0.0 ate: ocument Number of esigned for TI by einfochips FM Interface to JES/RF devices- 0 Monday, June, 0 KL EVM _00_0.0 SEF S-0---K-TR N GN E H0_P_ E H0_N_ E GN E GN E H0_P E H0_N E GN E H0_P E H0_N E0 GN E H_P E H_N E GN E H_P E H_N E GN0 E H0_P E H0_N E GN E0 H0_P E H0_N E GN E H0_P E H0_N E GN E H0_P E H0_N E GN E H_P E0 H_N E GN E H_P E H_N E GN E H_P E H_N E GN E VJ E GN E0 PG_M F GN F GN0 F H00_P_ F H00_N_ F GN F H0_P F H0_N F GN F H0_P F0 H0_N F GN F H_P F H_N F GN F H_P F H_N F GN F H_P F H_N F0 GN F H0_P F H0_N F GN F H0_P F H0_N F GN F H0_P F H0_N F GN F0 H_P F H_N F GN00 F H_P F H_N F GN0 F H0_P F H0_N F GN0 F VJ F0 GN0 G LK0_M_P G LK0_M_N G GN0 G GN0 G L00_P_ G L00_N_ G GN0 G L0_P G L0_N G0 GN0 G L0_P G L0_N G GN0 G L_P G L_N G GN0 G L_P G L_N G GN0 G0 L0_P G L0_N G GN G L_P G L_N G GN G L_P G L_N G GN G L_P G0 L_N G GN G L_P G L_N G GN G L_P G L_N G GN G VJ G GN G0 VREF M H PRSNT_M_L H GN H LK0_M_P H LK0_M_N H GN H L0_P H L0_N H GN0 H L0_P H0 L0_N H GN H L0_P H L0_N H GN H L_P H L_N H GN H L_P H L_N H0 GN H L_P H L_N H GN H L_P H L_N H GN H L_P H L_N H GN H0 L_P H L_N H GN H L0_P H L0_N H GN H L_P H L_N H GN0 H VJ H0 TP0 0.uF_.V UF_V 0.uF_.V TP 0.uF_.V_0%_XR_00 SEF S-0---K-TR N GN J LK_M_P J LK_M_N J GN J GN J H0_P J H0_N J GN J H0_P J H0_N J0 GN J H_P J H_N J GN J H_P J H_N J GN J H_P J H_N J GN J0 H_P J H_N J GN J H0_P J H0_N J GN0 J H0_P J H0_N J GN J H_P J0 H_N J GN J H_P J H_N J GN J H_P J H_N J GN J VIO M J GN J0 VREF M K GN K GN K LK_M_P K LK_M_N K GN K H0_P K H0_N K GN K H0_P K0 H0_N K GN0 K H0_P K H0_N K GN K H_P_ K H_N_ K GN K H_P K H_N K0 GN K H_P K H_N K GN K H00_P_ K H00_N_ K GN K H0_P_ K H0_N_ K GN K0 H0_P K H0_N K GN K H_P K H_N K GN K H_P_ K H_N_ K GN K VIO M K0 SEF S-0---K-TR N GN P_M_P P_M_N GN GN P_M_P P_M_N GN GN P_M_P 0 P_M_N GN GN P_M_P P_M_N GN GN P_M_P P_M_N GN0 0 GN P_M_P P_M_N GN GN P_M_P P_M_N GN GN P_M_P 0 P_M_N GN GN P_M_P P_M_N GN GN P_M_P P_M_N GN0 0 RES GN GN P_M_P P_M_N GN GN P_M_P P_M_N GN 0 GN P_M_P P_M_N GN GN P_M_P P_M_N GN GN0 GTLK_M_P 0 GTLK_M_N GN GN P_M_P P_M_N GN GN P_M_P P_M_N GN 0 GN P_M_P P_M_N GN GN P_M_P P_M_N GN GN0 RES0 0 GN P0_M_P P0_M_N GN GN P0_M_P P0_M_N GN GN L0_P 0 L0_N GN GN L0_P L0_N GN GN L_P L_N GN0 0 GN L_P_ L_N_ GN GN L_P L_N GN GN SL 0 S GN GN G0 P0V GN P0V GN PV GN0 0 PG_M GN GN GTLK0_M_P GTLK0_M_N GN GN L0_P_ L0_N_ GN 0 L0_P L0_N GN L0_P L0_N GN L_P L_N GN L_P_ 0 L_N_ GN L_P L_N GN0 L_P L_N GN TK TI 0 TO PVUX TMS TRST_L G PV GN PV GN PV uF_.V 0.uF_.V_0%_XR_00 0.uF_.V 0.uF_.V_0%_XR_00 0.uF_.V_0%_XR_00

11 FM Interface to JES/RF devices - JES_TXP_FM_NET JES_TXN_FM_NET JES_TXP_FM_NET JES_TXN_FM_NET V_IN_FM VIN_FM STTUS_0_FM_FPG_V STTUS FM_FPG_V RST#_FM_FPG_V USY#_FM_FPG_V SYS_LKP_FM SYS_LKN_FM SYSREF_N_FM SYSREF_P_FM SO_JES_SYNOUT_P_FM SO_JES_SYNOUT_N_FM SO_JES_SYNIN_P_FM SO_JES_SYNIN_N_FM SPI_S_FM_FPG_V SPI_S_LMK_FM_FPG_V SPI_MISO_FM_FPG_V SPI_MOSI_FM_FPG_V SPI_LK_FM_FPG_V SPI_LK_LMK_FM_FPG_V SPI_MOSI_LMK_FM_FPG_V SPI_MISO/RST_LMK_FM_FPG_V JES_RXP_FM JES_RXN_FM JES_RXP_FM JES_RXN_FM GPIO FM_FPG_V GPIO FM_FPG_V GPIO FM_FPG_V GPIO_0_FM_FPG_V GPIO FM_FPG_V GPIO FM_FPG_V GPIO FM_FPG_V GPIO FM_FPG_V GPIO0 FM_FPG_V GPIO0 FM_FPG_V GPIO0 FM_FPG_V GPIO0 FM_FPG_V GPIO0 FM_FPG_V GPIO0 FM_FPG_V GPIO0 FM_FPG_V GPIO0_0/GPTEST_FM_FPG_V GP_FM_FPG_V GP_FM_FPG_V GP_FM_FPG_V GP_FM_FPG_V GP_FM_FPG_V GP_FM_FPG_V GP_FM_FPG_V GP_FM_FPG_V JES_TXN_FM JES_TXP_FM IRQ_FM_FPG_V JES_TXN_FM JES_TXP_FM ate: ocument Number of esigned for TI by einfochips FM Interface to JES/RF devices - Monday, June, 0 KL EVM _00_0.0 ate: ocument Number of esigned for TI by einfochips FM Interface to JES/RF devices - Monday, June, 0 KL EVM _00_0.0 ate: ocument Number of esigned for TI by einfochips FM Interface to JES/RF devices - Monday, June, 0 KL EVM _00_0.0 R0.E_0.W_%_00 R.E_% SEF S-0---K-TR N GN E H0_P_ E H0_N_ E GN E GN E H0_P E H0_N E GN E H0_P E H0_N E0 GN E H_P E H_N E GN E H_P E H_N E GN0 E H0_P E H0_N E GN E0 H0_P E H0_N E GN E H0_P E H0_N E GN E H0_P E H0_N E GN E H_P E0 H_N E GN E H_P E H_N E GN E H_P E H_N E GN E VJ E GN E0 PG_M F GN F GN0 F H00_P_ F H00_N_ F GN F H0_P F H0_N F GN F H0_P F0 H0_N F GN F H_P F H_N F GN F H_P F H_N F GN F H_P F H_N F0 GN F H0_P F H0_N F GN F H0_P F H0_N F GN F H0_P F H0_N F GN F0 H_P F H_N F GN00 F H_P F H_N F GN0 F H0_P F H0_N F GN0 F VJ F0 GN0 G LK0_M_P G LK0_M_N G GN0 G GN0 G L00_P_ G L00_N_ G GN0 G L0_P G L0_N G0 GN0 G L0_P G L0_N G GN0 G L_P G L_N G GN0 G L_P G L_N G GN0 G0 L0_P G L0_N G GN G L_P G L_N G GN G L_P G L_N G GN G L_P G0 L_N G GN G L_P G L_N G GN G L_P G L_N G GN G VJ G GN G0 VREF M H PRSNT_M_L H GN H LK0_M_P H LK0_M_N H GN H L0_P H L0_N H GN0 H L0_P H0 L0_N H GN H L0_P H L0_N H GN H L_P H L_N H GN H L_P H L_N H0 GN H L_P H L_N H GN H L_P H L_N H GN H L_P H L_N H GN H0 L_P H L_N H GN H L0_P H L0_N H GN H L_P H L_N H GN0 H VJ H0 SEF S-0---K-TR N GN J LK_M_P J LK_M_N J GN J GN J H0_P J H0_N J GN J H0_P J H0_N J0 GN J H_P J H_N J GN J H_P J H_N J GN J H_P J H_N J GN J0 H_P J H_N J GN J H0_P J H0_N J GN0 J H0_P J H0_N J GN J H_P J0 H_N J GN J H_P J H_N J GN J H_P J H_N J GN J VIO M J GN J0 VREF M K GN K GN K LK_M_P K LK_M_N K GN K H0_P K H0_N K GN K H0_P K0 H0_N K GN0 K H0_P K H0_N K GN K H_P_ K H_N_ K GN K H_P K H_N K0 GN K H_P K H_N K GN K H00_P_ K H00_N_ K GN K H0_P_ K H0_N_ K GN K0 H0_P K H0_N K GN K H_P K H_N K GN K H_P_ K H_N_ K GN K VIO M K0 UF_V R00.E_0.W_%_00 0.uF_.V R0.E_% R.E_% 0 0.uF_.V R.E_% R.E_% R.E_% SEF S-0---K-TR N GN P_M_P P_M_N GN GN P_M_P P_M_N GN GN P_M_P 0 P_M_N GN GN P_M_P P_M_N GN GN P_M_P P_M_N GN0 0 GN P_M_P P_M_N GN GN P_M_P P_M_N GN GN P_M_P 0 P_M_N GN GN P_M_P P_M_N GN GN P_M_P P_M_N GN0 0 RES GN GN P_M_P P_M_N GN GN P_M_P P_M_N GN 0 GN P_M_P P_M_N GN GN P_M_P P_M_N GN GN0 GTLK_M_P 0 GTLK_M_N GN GN P_M_P P_M_N GN GN P_M_P P_M_N GN 0 GN P_M_P P_M_N GN GN P_M_P P_M_N GN GN0 RES0 0 GN P0_M_P P0_M_N GN GN P0_M_P P0_M_N GN GN L0_P 0 L0_N GN GN L0_P L0_N GN GN L_P L_N GN0 0 GN L_P_ L_N_ GN GN L_P L_N GN GN SL 0 S GN GN G0 P0V GN P0V GN PV GN0 0 PG_M GN GN GTLK0_M_P GTLK0_M_N GN GN L0_P_ L0_N_ GN 0 L0_P L0_N GN L0_P L0_N GN L_P L_N GN L_P_ 0 L_N_ GN L_P L_N GN0 L_P L_N GN TK TI 0 TO PVUX TMS TRST_L G PV GN PV GN PV 0 TP TP 0.uF_.V_0%_XR_00 0.uF_.V_0%_XR_00

12 JES0_RXP_FM_NET JES0_RXN_FM_NET IF0_RXP_M_NET IF0_RXN_M_NET JES_RXP_FM_NET JES_RXN_FM_NET IF_RXP_M_NET IF_RXN_M_NET JES0/IF0_TXP_SO_NET JES0/IF0_TXN_SO_NET JES/IF_TXP_SO_NET JES/IF_TXN_SO_NET JES Serdes switch - VV_UX VV_UX R 0K_0.W_%_00 VV_UX R 0K_0.W_%_00 VV_UX R0 0K_0.W_%_00 VV_UX R0 0K_0.W_%_00 EQ SW EQ_0_SW EQ_0_SW EQ SW uf_v_0%_xr_00 0uF_.V U VIN Note: Place the capacitors close to V pins of the I. V V V V V 0 R 0K_0.W_%_00 R 0K_0.W_%_00 R 0K_0.W_%_00 0 R 0 0K_0.W_%_00 JES0_RXP_FM JES0_RXN_FM IF0_RXP_M IF0_RXN_M 0.uF_.V 0.uF_.V 0.uF_.V 0.uF_.V S_IN0+ S_IN0- S_IN0+ S_IN0- _OUT0+ _OUT0- JES0/IF0_RXP_SO JES0/IF0_RXN_SO 0 JES_RXP_FM 0 JES_RXN_FM IF_RXP_M IF_RXN_M 0.uF_.V 0.uF_.V 0.uF_.V 0 0.uF_.V 0 S_IN+ S_IN- S_IN+ S_IN- _OUT+ _OUT- JES/IF_RXP_SO JES/IF_RXN_SO VV_UX VV_UX R 0K_0.W_%_00 EQ_0_SW R 0K_0.W_%_00 R 0K_0.W_%_00 EQ SW R 0K_0.W_%_00 VV_UX JES0/IF0_TXP_SO 0.uF_.V JES0/IF0_TXN_SO 0.uF_.V coupling caps R 0K_0.W_%_00 VV_UX JES/IF_TXP_SO 0.uF_.V JES/IF_TXN_SO 0.uF_.V R 0K_0.W_%_00 R 0K_0.W_%_00 SERES_SW_SEL0_FPG_V_EXP SERES_SW_SEL_FPG_V_EXP R K_% 0 _IN0+ _IN0- _IN+ _IN- MOE SEL0 SEL/RE_EN V_SEL INPUT_EN S_OUT0+ S_OUT0- S_OUT0+ S_OUT0- S_OUT+ S_OUT- S_OUT+ 0 S_OUT- LL_ONE JES0_TXP_FM 0 JES0_TXN_FM 0 IF0_TXP_M IF0_TXN_M IF_TXP_M IF_TXN_M JES_TXP_FM 0 JES_TXN_FM 0 TP Note: Output is fully compatible with coupled ML inputs. FM / M end should support ML input. VV_UX R 0K_0.W_%_00 EQ SW_R VV_UX R 0K_0.W_%_00 EQ_0_SW_R VV_UX R K_% VV_UX R K_% EQ SW R EQ_0_SW R VV_UX,,,,0 M_I_S,,,,0 M_I_SL R R0 EQ SW_R EQ_0_SW_R 0 0 EQ_ EQ_0 EQ_S0/ EQ_S/ ENSM EM_S0/S EM_S/SL N N N N N N N N VV_UX R 0K_0.W_%_00 R0 0K_0.W_%_00 VV_UX R0 K_% R K_% R0 K_% R K_% R 0K_% R 0K_% VV_UX K_% K_% R R VV_UX K_% K_% R R RESET# EM_0/ EM_/0 GN S00M0SQE/NOP K_% K_% R R VV_UX K_% R K_% R I RESS FOR SERES SWITHES Reference esignator 0 Lamarr allname SIS_0_RXN0 Lamarr irection iff In TLE FOR SERES ONNETIONS Lamarr all J Lamarr SO Net name to switch JES0/IF0_RXN_SO Sw/SO Sw Out Switch Inputs JES0_RXN_FM or IF0_RXN_M Switch Outputs - FM Name JES0_RXN_FM FM Pin FM Name FM Pin Marconi Name TXN_S M Name IF0_RXN_M M Pin U U U0 0 0 SIS_0_RXP0 iff In J JES0/IF0_RXP_SO Sw Out JES0_RXP_FM or IF0_RXP_M - JES0_RXP_FM TXP_S IF0_RXP_M SIS_0_RXN iff In K0 JES/IF_RXN_SO Sw Out JES_RXN_FM or IF_RXN_M - JES_RXN_FM TXN_S IF_RXN_M SIS_0_RXP iff In K JES/IF_RXP_SO Sw Out JES_RXP_FM or IF_RXP_M - JES_RXP_FM TXP_S IF_RXP_M SIS_0_TXN0 iff Out H JES0/IF0_TXN_SO Sw In JES0_TXN_FM JES0_TXN_FM RXN_S IF0_TXN_M or IF0_TXN_M SIS_0_TXP0 iff Out H JES0/IF0_TXP_SO Sw In JES0_TXP_FM JES0_TXP_FM RXP_S or IF0_TXP_M SIS_0_TXN iff Out G JES/IF_TXN_SO Sw In JES_TXN_FM JES_TXN_FM RXN_S or IF_TXN_M SIS_0_TXP iff Out G JES/IF_TXP_SO Sw In JES_TXP_FM or IF_TXP_M IF0_TXP_M IF_TXN_M 0 JES_TXP_FM RXP_S IF_TXP_M KL EVM esigned for TI by einfochips JES Serdes switch - ocument Number _00_0.0 ate: Monday, June, 0 of

13 JES Serdes switch - uf_v_0%_xr_00 VV_UX 0 0uF_.V U VIN Note: Place the capacitors close to V pins of the I. V V V V V JES_RXP_FM JES_RXN_FM JES_RXP_FM JES_RXN_FM 0.uF_.V 0.uF_.V 0.uF_.V 0.uF_.V JES_RXP_FM_NET JES_RXN_FM_NET JES_RXP_FM_NET JES_RXN_FM_NET S_IN0+ S_IN0- S_IN0+ S_IN0- _OUT0+ _OUT0- JES_RXP_SO JES_RXN_SO VV_UX R K_% 0 0 VV_UX R 0K_0.W_%_00 JES_RXP_FM JES_RXN_FM JES_RXP_FM JES_RXN_FM JES_TXP_SO JES_TXN_SO R 0K_0.W_%_00 JES_TXP_SO JES_TXN_SO R0 0K_0.W_%_ coupling caps 0.uF_.V 0.uF_.V 0.uF_.V 0.uF_.V 0.uF_.V 0.uF_.V 0.uF_.V 0.uF_.V SERES_SW_SEL0_FPG_V_EXP SERES_SW_SEL_FPG_V_EXP JES_RXP_FM_NET JES_RXN_FM_NET JES_RXP_FM_NET JES_RXN_FM_NET JES_TXP_SO_NET JES_TXN_SO_NET JES_TXP_SO_NET JES_TXN_SO_NET 0 S_IN+ S_IN- S_IN+ S_IN- 0 _OUT+ _OUT- S_OUT0+ S_OUT0- S_OUT0+ S_OUT0- S_OUT+ S_OUT- S_OUT+ 0 S_OUT- LL_ONE _IN0+ _IN0- _IN+ _IN- MOE SEL0 SEL/RE_EN V_SEL INPUT_EN JES_RXP_SO JES_RXN_SO JES_TXP_FM 0 JES_TXN_FM 0 JES_TXP_FM JES_TXN_FM JES_TXP_FM JES_TXN_FM JES_TXP_FM 0 JES_TXN_FM 0 TP Note: Output is fully compatible with coupled ML inputs. FM / M end should support ML input. VV_UX VV_UX VV_UX R K_% R0 K_% VV_UX R0 K_% R K_% VV_UX R K_% R K_% VV_UX R 0K_% R 0K_% VV_UX R K_% R K_%,,,,0,,,,0 M_I_S M_I_SL VV_UX R K_% R K_% EQ SW EQ_0_SW R R R R EQ SW_R EQ_0_SW_R 0 0 EQ_ EQ_0 EQ_S0/ EQ_S/ ENSM EM_S0/S EM_S/SL RESET# EM_0/ EM_/0 GN N N N N N N N N S00M0SQE/NOP VV_UX K_% R0 K_% R0 VV_UX K_% R K_% R R 0K_0.W_%_00 EQ SW_R R 0K_0.W_%_00 R 0K_0.W_%_00 EQ_0_SW_R R 0K_0.W_%_00 Lamarr allname SIS RXN0 Lamarr irection iff In TLE FOR SERES ONNETIONS Lamarr all J Lamarr SO Net name to switch JES_RXN_SO Sw/SO Switch Inputs Sw Out JES_RXN_FM or JES_RXN_FM Switch Outputs - FM Name JES_RXN_FM FM Pin FM Name JES_RXN_FM FM Pin Marconi Name TXN_S SIS RXP0 iff In J JES_RXP_SO Sw Out JES_RXP_FM or JES_RXP_FM - JES_RXP_FM JES_RXP_FM TXP_S SIS RXN iff In K JES_RXN_SO Sw Out JES_RXN_FM or JES_RXN_FM - JES_RXN_FM JES_RXN_FM TXN_S SIS RXP iff In K JES_RXP_SO Sw Out JES_RXP_FM or JES_RXP_FM - JES_RXP_FM 0 JES_RXP_FM 0 TXP_S SIS TXN0 iff Out H JES_TXN_SO Sw In - JES_TXN_FM or JES_TXN_FM JES_TXN_FM RXN_S JES_TXN_FM SIS TXP0 iff Out H JES_TXP_SO Sw In - JES_TXP_FMor JES_TXP_FM JES_TXP_FM SIS TXN iff Out G JES_TXN_SO SIS TXP iff Out G JES_TXP_SO Sw In Sw In - - JES_TXN_FM or JES_TXN_FM JES_TXP_FMor JES_TXP_FM JES_TXN_FM JES_TXP_FM 0 JES_TXP_FM JES_TXN_FM JES_TXP_FM RXP_S RXN_S 0 RXP_S KL EVM esigned for TI by einfochips JES Serdes switch - ocument Number _00_0.0 ate: Monday, June, 0 of

14 SGMII/PIe Serdes switch VV_UX uf_v_0%_xr_00 0uF_.V Note: Place the capacitors close to V pins of the I. 0 U VIN V V V V V PIe0_RXP_M PIe0_RXN_M SGMII_RXP_M SGMII_RXN_M 0.uF_.V 0.uF_.V 0.uF_.V 0 0.uF_.V PIe0_RXP_M_NET PIe0_RXN_M_NET SGMII_RXP_M_NET SGMII_RXN_M_NET S_IN0+ S_IN0- S_IN0+ S_IN0- _OUT0+ _OUT0- PIe0/SGMII_RXP_SO PIe0/SGMII_RXN_SO PIe_RXP_M PIe_RXN_M SGMII_RXP_M SGMII_RXN_M 0.uF_.V 0.uF_.V 0.uF_.V 0.uF_.V PIe_RXP_M_NET 0 PIe_RXN_M_NET S_IN+ SGMII_RXP_M_NET S_IN- SGMII_RXN_M_NET S_IN+ S_IN- _OUT+ _OUT- PIe/SGMII_RXP_SO PIe/SGMII_RXN_SO coupling caps PIe0/SGMII_TXP_SO_NET PIe0/SGMII_TXP_SO 0.uF_.V 0 PIe0/SGMII_TXN_SO_NET PIe0/SGMII_TXN_SO 0.uF_.V VV_UX R VV_UX 0K_0.W_%_00 0.uF_.V PIe/SGMII_TXP_SO_NET PIe/SGMII_TXP_SO PIe/SGMII_TXN_SO_NET PIe/SGMII_TXN_SO 0.uF_.V R 0K_0.W_%_00 R 0K_0.W_%_00 SERES_SW_SEL0_FPG_V_EXP SERES_SW_SEL_FPG_V_EXP R K_% _IN0+ _IN0- _IN+ _IN- MOE SEL0 SEL/RE_EN V_SEL INPUT_EN S_OUT0+ S_OUT0- S_OUT0+ S_OUT0- S_OUT+ S_OUT- S_OUT+ 0 S_OUT- LL_ONE PIe0_TXP_M PIe0_TXN_M SGMII_TXP_M SGMII_TXN_M SGMII_TXP_M SGMII_TXN_M PIe_TXP_M PIe_TXN_M TP Note: Output is fully compatible with coupled ML inputs. FM / M end should support ML input. VV_UX R K_% VV_UX R K_% VV_UX,,,,0,,,,0 EQ SW EQ_0_SW M_I_S M_I_SL R R R R EQ SW_R EQ_0_SW_R 0 0 EQ_ EQ_0 EQ_S0/ EQ_S/ ENSM EM_S0/S EM_S/SL N N N N N N N N VV_UX R 0K_0.W_%_00 EQ SW_R VV_UX R0 0K_0.W_%_00 EQ_0_SW_R VV_UX R K_% R K_% R K_% R K_% R 0K_% R0 0K_% VV_UX R K_% R K_% VV_UX R K_% R K_% RESET# EM_0/ EM_/0 GN S00M0SQE/NOP VV_UX K_% R K_% R VV_UX K_% R K_% R0 R 0K_0.W_%_00 R 0K_0.W_%_00 TLE FOR SERES ONNETIONS Lamarr allname Lamarr irection Lamarr all Lamarr SO Net name to switch Sw/SO Switch Inputs Switch Outputs M PIe connm Pin M SGMII conn M Pin SIS RXN0 iff In J PIe0/SGMII_RXN_SO Sw Out PIe0_RXN_M or SGMII_RXN_M - PIe0_RXN_M SGMII_RXN_M SIS RXP0 iff In J PIe0/SGMII_RXP_SO Sw Out PIe0_RXP_M or - PIe0_RXP_M SGMII_RXP_M SGMII_RXP_M SIS RXN iff In K PIe/SGMII_RXN_SO Sw Out PIe_RXN_M or SGMII_RXN_M - PIe_RXN_M SGMII_RXN_M SIS RXP iff In K PIe/SGMII_RXP_SO Sw Out PIe_RXP_M or SGMII_RXP_M - PIe_RXP_M SGMII_RXP_M SIS TXN0 iff Out H0 PIe0/SGMII_TXN_SO Sw In - PIe0_TXN_M or PIe0_TXN_M SGMII_TXN_M SIS TXP0 iff Out H PIe0/SGMII_TXP_SO Sw In - PIe0_TXP_M or PIe0_TXP_M SGMII_TXP_M SIS TXN iff Out G SIS TXP iff Out G PIe/SGMII_TXN_SO PIe/SGMII_TXP_SO Sw In Sw In - - PIe_TXN_M or SGMII_TXN_M PIe_TXP_M or SGMII_TXP_M PIe_TXN_M PIe_TXP_M 0 SGMII_TXN_M SGMII_TXP_M SGMII_TXN_M SGMII_TXP_M 0 KL EVM esigned for TI by einfochips SGMII/PIe Serdes switch ocument Number _00_0.0 ate: Monday, June, 0 of

15 FPG, SYSREF uffering, LEs Note: Place these TPs nearer TP TP TP, SO_SPI_LK SYSREF_P/N output from FPG is LVS pair FPG_LK_P/N input to FPG is LVS pair FPG_LK_N FPG_LK_P SYSREF_IVLK_N SYSREF_IVLK input to FPG is LVS pair SYSREF_IVLK_P, SO_TSRXLKOUT0N, SO_TSRXLKOUT0P, SO_GPIO FPG_V_EXP SO_PLLLOK_FPG_V_EXP EXPON_PRESENT_FPG_V_EXP EXPON_OR-I0_FPG_V_EXP EXPON_OR-I_FPG_V_EXP EXPON_OR-I_FPG_V_EXP.V idirectional I/O 0_% R SO_FE_GPIO0 SO_FE_GPIO SO_FE_GPIO SO_FE_GPIO SO_FE_GPIO SO_FE_GPIO SO_FE_GPIO SO_FE_GPIO SO_FE_GPIO SO_FE_GPIO SO_FE_GPIO0 SO_FE_GPIO SO_FE_GPIO SO_FE_GPIO SO_FE_GPIO SO_FE_GPIO SO_FE_GPIO SO_FE_GPIO SO_VPP_EN_FPG_V_EXP R K_% TP FPG_LK_N FPG_GPIO V FPG_GPIO V FPG_GPIO V FPG_GPIO V E F E F E 0 0 E0 0 U ank0(.v) IO_L0N_0 IO_LN_0/VREF_0 IO_L0P_0 IO_LP_0 IO_L0N_0 IO_LN_0 IO_L0P_0/VREF_0 IO_LP_0 IO_L0N_0 IO_LN_0 IO_L0P_0 IO_LP_0 IO_L0N_0 IO_LN_0 IO_L0P_0/VREF_0 IO_LP_0 IO_L0N_0 IO_LN_0 IO_L0P_0 IO_LP_0 IO_L0N_0 IO_LN_0 IO_L0P_0 IO_LP_0 IO_L0N_0 IO_LN_0 IO_L0P_0 IO_LP_0 IO_L0N_0 IO_LN_0 IO_L0P_0 IO_LP_0 IO_L0N_0 IO_L0N_0 IO_L0P_0 IO_L0P_0 IO_L0N_0/VREF_0 IO_LN_0 IO_L0P_0 IO_LP_0 IO_LN_0 IO_LN_0/PU_ IO_LP_0 IO_LP_0/VREF_0 IO_LN_0 IP_0_ IO_LP_0 IP_0_ IO_LN_0 IP_0_ IO_LP_0 IP_0_ IO_LN_0 IP_0_ IO_LP_0 IP_0_ IO_LN_0/GLK IP_0_ IO_LP_0/GLK IP_0_ IO_LN_0/GLK IP_0_ IO_LP_0/GLK IP_0_0 IO_LN_0/GLK IP_0_ IO_LP_0/GLK IP_0_ IO_LN_0/GLK IP_0/VREF_0 IO_LP_0/GLK0 VO_0_ IO_LN_0 VO_0_ IO_LP_0 VO_0_ IO_L0N_0 VO_0_ IO_L0P_0 VO_0_ IO_LN_0 VO_0_ IO_LP_0 F E F E F E F E E F F G G G0 G G H H0 H H G 0 F0 SO_RESETSTTZ_FPG_V_EXP, SO_HOUT_FPG_V_EXP SO_OOTOMPLETE_FPG_V_EXP SO_ORESEL0_FPG_V_EXP SO_ORESEL_FPG_V_EXP SO_ORESEL_FPG_V_EXP SO_PORZ_FPG_V_EXP, SO_RESETZ_FPG_V_EXP, SO_RESETFULLZ_FPG_V_EXP, SO_LRESETZ_FPG_V_EXP SO_LRESETNMIENZ_FPG_V_EXP SO_ORELKSEL0_FPG_V_EXP SO_ORELKSEL_FPG_V_EXP SO_NMIZ_FPG_V_EXP NOR_WPz M_GPIOINT_FPG_V_EXP TIMI_MUX_OEZ_FPG_V_EXP EXT_SL_FPG_V_EXP EXT_S_FPG_V_EXP FPG_PU PLLLOK_LE_FPG_V_EXP EXT_SWITH_IN_V EXT_SWITH_IN_V R K_% TP M_TIMO0 EXP_TIMO0 EXT_TIMO EXP_TIMO V_V_FPG 0_% TP TP TP R0 TP Note: Place these TPs nearer GPIO TON_FPG_V GPIO TON_FPG_V GPIO TON_FPG_V SO_SPISS SO_SPISS SO_SPI_MISO, SO_SPI_MOSI SO_TSSYNEVT SO_TSOMPOUT SO_EXTFRMEEVENT EVM_TS_SYNEVT_FPG_V EVM_TS_OMPOUT_FPG_V EVM_TS_EXTFRMEEVT_FPG_V, TP SO_TIMO0_FPG_V SO_TIMO_FPG_V SO_TIMI0_FPG_V SO_TIMI_FPG_V TIMO0_EVM_FPG_V TIMO_EVM_FPG_V R0 K_% R K_% M_GPS_EN_FPG_V_EXP NN_WPZ_FPG_V_EXP EEPROM_WPZ_FPG_V_EXP M_GPIOINT_FPG_V_EXP R K_% TP V0 W0 U V R T T0 T U0 U P P R R R0 R P0 P N N N N M M L L M0 M L L L K J0 K0 J J K J H H G0 H0 H ank(.v) U IO_L0N_/L IO_LP_ IO_L0P_/H IO_LN_/ IO_L0N_/L0 IO_LP_/ IO_L0P_/L IO_L0N_/ IO_L0N_/ IO_L0P_/ IO_L0P_/0 IO_LN_ IO_L0N_ IO_LP_ IO_L0P_ IO_LN_ IO_L0N_ IO_LP_ IO_L0P_ IO_LN_ IO_L0N_ IO_LP_ IO_L0P_ IO_LN_/ IO_L0N_ IO_LP_/0 IO_L0P_ IO_LN_/ IO_L0N_ IO_LP_/ IO_L0P_ IO_LN_/ IO_L0N_/VREF_ IO_LP_/ IO_L0P_ IP_/VREF_ IO_LN_/ IP_L0N_/VREF_ IO_LP_/ IP_L0P_ IO_LN_/ IP_LN_/VREF_ IO_LP_/ IP_LP_ IO_LN_/ IP_LN_ IO_LP_/ IP_LP_/VREF_ IO_LN_/ IP_LN_ IO_LP_/ IP_LP_ IO_LN_/RHLK IP_LN_ IO_LP_/RHLK0 IP_LP_/VREF_ IO_LN_/TRY/RHLK IP_LN_ IO_LP_/RHLK IP_LP_ IO_L0N_/RHLK IP_LN_ IO_L0P_/RHLK IP_LP_/VREF_ IO_LN_/RHLK IP_LN_ IO_LP_/IRY/RHLK IP_LP_ IO_LN_/ IP_LN_ IO_LP_/0 IP_LP_/VREF_ IO_LN_ VO IO_LP_ VO IO_LN_/ VO IO_LP_/ VO IO_LN_/ VO IO_LP_/ IO_LN_ G F F0 F G E E0 F E 0 F G 0 0 N P P M M M M L L K K J J J J H H G G H K N T R SO_GPIO_0_FPG_V_EXP, SO_GPIO FPG_V_EXP, SO_GPIO FPG_V_EXP, SO_GPIO FPG_V_EXP, SO_GPIO FPG_V_EXP, SO_GPIO FPG_V_EXP, SO_GPIO FPG_V_EXP, SO_GPIO FPG_V_EXP,, SO_GPIO FPG_V_EXP,, SO_GPIO FPG_V_EXP, SO_GPIO_0_FPG_V_EXP, SO_GPIO FPG_V_EXP,, SO_GPIO FPG_V_EXP, SO_GPIO FPG_V_EXP, SO_GPIO FPG_V_EXP, SO_GPIO FPG_V_EXP, M_GPIOINT0_FPG_V_EXP K_% TP0 V_V_FPG Tristated ootpin GPIOs Place near FPG pins,, SO_I_SL SO_I_S FPG_LK_P R0 R0 R 0_%_00 % EXT_SL_FPG_V_EXP EXT_S_FPG_V_EXP XS00N-FGG00 0.uF_.V.V 0.uF_.V.V 0.uF_.V.V 0.uF_.V 0.V 0.uF_.V.V 0.uF_.V.V 0uF_.V 0uF_.V XS00N-FGG00 V_V_FPG R0 0K_% FPG_PU 0.uF_.V.V 0.uF_.V.V 0.uF_.V.V 0.uF_.V 0.V 0.uF_.V.V 0uF_.V 0uF_.V R0 VV_UX VV_UX SYSREF_IVLK_N SYSREF_IVLK_P PLLLOK_LE_FPG_V_EXP R 0_%_00 % R _0.W_%_00 Q0 MMT0LTG VV_UX R _0.W_%_00 G LE_GREEN_00 Note:LE olor is GREEN R _0.W_%_00 VV_UX LE_RE_00 R K_% R K_% R SYSREF_P_FPG SYSREF_N_FPG VV_UX K_% R0 K_% R 0K_% U V Y Z Y Z Y EN Z EN Y 0 EN Z EN GN SNLVS0PWR SYSREF_P_SO SYSREF_N_SO TP TP LVS E_0.W_%_00 _0.W_%_00 R R E_0.W_%_00 _0.W_%_00 R R E_0.W_%_00 _0.W_%_00 R0 R E_0.W_%_00 _0.W_%_00 R SYSREF_P_FM 0 SYSREF_N_FM 0 SYSREF_P_FM SYSREF_N_FM R LVPEL, SO_RESETSTTZ_FPG_V_EXP R _0.W_%_00 Q MMT0LTG <haracteristic> Note:LE olor is RE R K_% KL EVM esigned for TI by einfochips FPG, SYSREF uffering, LEs ocument Number _00_0.0 ate: Monday, June, 0 of

16 FPG, FPG pin conn, SPI Flash, LEs FPG_M0 V FPG_M U 0 GPIO0 FM_FPG_V Y FPG_M W 0 GPIO0 FM_FPG_V W 0 GPIO FM_FPG_V Y R 0 GPIO FM_FPG_V 0 GPIO FM_FPG_V T GPIO0 FM_FPG_V U GPIO0 FM_FPG_V V GPIO FM_FPG_V U GPIO FM_FPG_V T FPG_VS U GPIO FM_FPG_V R 0K_% T GPIO_0_TON_FPG_V Y GPIO TON_FPG_V Y R 0K_% FPG_VS0 W R 0K_% FPG_VS V GPIO TON_FPG_V Y SYSREFREQ_TON_FPG_V Y T_TIME_SYN_V_TIMINGON U LSYN_V_TIMINGON T EXT-PS#_FPG_V_EXP W LK_MUXTRL_FPG_V_EXP V V,, M_SPI0_MISO_FPG_V V T0,, M_SPI0_MOSI_FPG_V R K_% U0 TP0 SYSREF_N_FPG Y SYSREF_P_FPG W LK_MUXTRL0_FPG_V_EXP W0 V0 LK_MUXTRL_FPG_V_EXP,, M_SPI0_LK_FPG_V V SERES_SW_SEL0_FPG_V_EXP Y SERES_SW_SEL_FPG_V_EXP V SERES_SW_SEL0_FPG_V_EXP U R SERES_SW_SEL_FPG_V_EXP SERES_SW_SEL0_FPG_V_EXP T SERES_SW_SEL_FPG_V_EXP W M_GPIOINT_FPG_V_EXP Y PHY_INT#_FPG_V_EXP W PHY_INT#_FPG_V_EXP Y ank(.v) U IO_L0N_/M0 IO_LN_/OUT IO_L0P_/M IO_LP_/WKE IO_L0N_/SO_ IO_LN_ IO_L0P_/M IO_LP_ IO_L0N_ IO_LN_/ IO_L0P_ IO_LP_/INIT_ IO_L0N_ IO_LN_ IO_L0P_ IO_LP_ IO_L0N_ IO_LN_/ IO_L0P_ IO_LP_/ IO_L0N_ IO_LN_ IO_L0P_ IO_LP_ IO_L0N_/VS IO_LN_ IO_L0P_/RWR_ IO_LP_ IO_L0N_ IO_LN_ IO_L0P_ IO_LP_ IO_L0N_/VS0 IO_L0N_ IO_L0P_/VS IO_L0P_ IO_L0N_ IO_LN_ IO_L0P_ IO_LP_ IO_LN_ IO_LN_/LK IO_LP_ IO_LP_/0/IN/MISO IO_LN_/ IP IO_LP_/ IP IO_LN_ IP IO_LP_ IP IO_LN_/ IP IO_LP_/ IP IO_LN_/GLK IP_/VREF IO_LP_/GLK IP_/VREF IO_LN_/GLK IP_/VREF IO_LP_/GLK IP_/VREF IO_LN_/GLK IP_/VREF IO_LP_/GLK0 IP_/VREF IO_LN_/GLK VO IO_LP_/GLK VO IO_LN_ VO IO_LP_ VO IO_L0N_/MOSI/SI_ VO IO_L0P_ VO IO_LN_ IO_LP_ V U R T W Y T V V Y T U W Y U V Y Y U V Y W P P P R R0 T N N P P0 P R R U U W W W R R R R IRQ_FM_FPG_V connected to I/O pin from I only pin IRQ_FM_FPG_V FPG_RST# M_REF_SEL_FPG_V_EXP FPG_INIT# JTG_RST#_FPG_V EXP_GPIO_EN IRQ_FM_FPG_V connected to I/O pin from I only pin IRQ_FM_FPG_V _% ONE_FPG_V M_REFLK_P#_FPG_V_EXP M_REF_SEL_FPG_V_EXP M_REFLK_P#_FPG_V_EXP EXPON_MU_RESETSTTZ_FPG_V_EXP M_GPIOINT_FPG_V_EXP FPG_SPI_S# FPG_SPI_SI _% FPG_SPI_SK FPG_SPI_SO M_SPI0_S0#_FPG_V K_% K_% TP0 TP0 VV_UX 0 GPIO FM_FPG_V 0 GPIO FM_FPG_V 0 GPIO0 FM_FPG_V 0 GPIO0 FM_FPG_V 0 GPIO0 FM_FPG_V 0 GPIO0 FM_FPG_V 0 GPIO0 FM_FPG_V 0 GPIO FM_FPG_V 0 GPIO FM_FPG_V 0 GPIO_0_FM_FPG_V 0 GP_FM_FPG_V 0 GP_FM_FPG_V 0 GP_FM_FPG_V 0 GP_FM_FPG_V 0 GP_FM_FPG_V 0 GP_FM_FPG_V 0 GP_FM_FPG_V 0 GP_FM_FPG_V 0 GPIO0_0/GPTEST_FM_FPG_V 0 SPI_LK_LMK_FM_FPG_V 0 SPI_S_LMK_FM_FPG_V 0 SPI_MOSI_LMK_FM_FPG_V 0 SPI_MISO/RST_LMK_FM_FPG_V 0 SPI_LK_FM_FPG_V 0 SPI_S0_FM_FPG_V 0 SPI_MOSI_FM_FPG_V 0 SPI_MISO_FM_FPG_V GPIO FM_FPG_V GPIO FM_FPG_V GPIO0 FM_FPG_V GPIO0 FM_FPG_V GPIO0 FM_FPG_V GPIO0 FM_FPG_V GPIO0 FM_FPG_V GPIO FM_FPG_V GPIO FM_FPG_V GPIO_0_FM_FPG_V GP_FM_FPG_V GP_FM_FPG_V GP_FM_FPG_V GP_FM_FPG_V GP_FM_FPG_V E G F J J H H G F F E H G G F H J J J K J L K L K M L M M M M N N N N ank(.v) U IO_L0N_ IO_LN_ IO_L0P_ IO_LP_ IO_L0N_ IO_LN_ IO_L0P_ IO_LP_ IO_L0N_ IO_L0N_ IO_L0P_ IO_L0P_ IO_L0N_ IO_LN_ IO_L0P_ IO_LP_/VREF_ IO_L0N_ IO_LN_ IO_L0P_ IO_LP_ IO_L0N_ IO_LN_ IO_L0P_ IO_LP_ IO_L0N_ IO_LN_ IO_L0P_ IO_LP_ IO_L0N_ IO_LN_ IO_L0P_ IO_LP_ IO_L0N_ IO_LN_ IO_L0P_ IO_LP_ IO_LN_ IP_ IO_LP_ IP_L0N_/VREF_ IO_LN_/VREF_ IP_L0P_ IO_LP_ IP_LN_/VREF_ IO_LN_ IP_LP_ IO_LP_ IP_LN_ IO_LN_ IP_LP_ IO_LP_ IP_LN_ IO_LN_/LHLK IP_LP_ IO_LP_/LHLK0 IP_LN_ IO_LN_/IRY/LHLK IP_LP_ IO_LP_/LHLK IP_LN_ IO_L0N_/LHLK IP_LP_ IO_L0P_/LHLK IP_LN_ IO_LN_/LHLK IP_LP_ IO_LP_/TRY/LHLK IP_LN_ IO_LN_ IP_LP_ IO_LP_/VREF_ IP_LN_/VREF_ IO_LN_ IP_LP_ IO_LP_ VO IO_LN_ VO IO_LP_ VO IO_LN_ VO IO_LP_ VO R P P P R R T T R T U U T R V V W W H G G J J K K K K L L M M N M N P P P E H L N U GP_FM_FPG_V GP_FM_FPG_V GP_FM_FPG_V RST#_FM_FPG_V 0 RST#_FM_FPG_V SPI_MISO_FM_FPG_V SPI_MOSI_FM_FPG_V SPI_S_FM_FPG_V SPI_LK_FM_FPG_V SPI_MISO/RST_LMK_FM_FPG_V SPI_MOSI_LMK_FM_FPG_V SPI_S_LMK_FM_FPG_V SPI_LK_LMK_FM_FPG_V GPIO0_0/GPTEST_FM_FPG_V R0 K_% TP0 R0 K_% TP0 STTUS_0_FM_FPG_V 0 STTUS FM_FPG_V 0 USY#_FM_FPG_V 0 STTUS_0_FM_FPG_V STTUS FM_FPG_V USY#_FM_FPG_V V_V_FPG TP R 0_% TP TP Note: Place these TPs nearer XS00N-FGG00 M M M0 etails 0 onfigure from internal flash memory 0.uF_.V 0.V 0.uF_.V.V 0.uF_.V.V 0.uF_.V 0.uF_.V 0.uF_.V 0uF_.V 0uF_.V XS00N-FGG00.V.V.V.V.V.V.V.V 0.uF_.V 0.uF_.V 0.uF_.V 0.uF_.V 0.uF_.V 0uF_.V 0uF_.V VV_UX VV_UX VV_UX VV_UX.K_% VV Mb SPI NOR Flash R K_% FPG_INIT# R R0 _0.W_%_00 FPG_M0 R00 R _0.W_%_00 FPG_M R0 R _0.W_%_00 FPG_M R R R NOR_H# NOR_SSPS SO_SSP0_LK SO_SSP0_MOSI SO_SSP0_MISO R _%.K_% NOR_WPz NOR_WPz NOR V U/N HOL/Q U/N S U/N SK U/N Q0 U/N Q U/N 0 W/Vpp/Q U/N VSS U/N MONYX_NQESF0F <haracteristic> VV U V EXT_SWITH_IN_V EXT_SWITH_IN_V V_V_FPG R 0K_% R 0K_% N 0000 SO_EUG_LE R _0.W_%_00 SO_EUG_LE R0 _0.W_%_00 SO_EUG_LE R _0.W_%_00 SO_EUG_LE R _0.W_%_00 G_ G R R0 Q KP-0SG MMT0LTG <haracteristic> R SML-LX00US-TR <haracteristic> Q MMT0LTG Q MMT0LTG G_ G_ R R SML-LX00US-TR <haracteristic> Q MMT0LTG R0 _0.W_%_00 _0.W_%_00 VV_UX _0.W_%_00 VV_UX SO ebug LEs Note: OLOR LE RE LE GREEN LE LUE LE LUE VV_UX FPG_GPIO V Y OUT SO_EUG_LE FPG_GPIO V Y OUT SO_EUG_LE FPG_GPIO V Y OUT SO_EUG_LE FPG_GPIO V Y OUT SO_EUG_LE EUG_LE_UFF_OE OE# 0 OE# R.K_% OE# OE# GN SNLVPWR KL EVM esigned for TI by einfochips FPG, FPG pin conn, SPI Flash, LEs ocument Number _00_0.0 ate: Monday, June, 0 of

17 FPG, FPG JTG, FPG-Flash, FPG Programmer, KL SPI/TIM/URT, FPG test conn 0 E E F G G H H J J K K0 K K L L UE GN_ GN_ GN_ GN_ GN_ GN_ GN_ GN_ GN_ GN_0 GN_ GN_ GN_ GN_ GN_ GN_ GN_ GN_ GN_ GN_0 GN_ GN_ GN_ GN_ GN_ GN_ GN_ GN_ GN_ GN_0 GN_ GN_ GN_ GN_ GN_ GN_ GN_ GN_ GN_ GN_0 GN_ GN_ GN_ XS00N-FGG00 N GPIO_0_TON_FPG_V R00 GPIO TON_FPG_V GPIO TON_FPG_V R _% GPIO TON_FPG_V GPIO TON_FPG_V GPIO TON_FPG_V SYSREFREQ_TON_FPG_V R LSYN_V_TIMINGON T_TIME_SYN_V_TIMINGON R 0 L L0 M0 M N N N P P R R T U V V W W Y Y0 Y0 FTSH-0-0-F-V-K-P-TR <haracteristic> VV_UX 0 ONE_FPG_V PROG FPG_V JTG_TK_FPG_V JTG_TI_FPG_V JTG_TO_FPG_V JTG_TMS_FPG_V VV_UX N TSM-0-0-S-SV 0 V_V_FPG E_% R E_% R E_% R R 0uF_.V K_% 0uF_.V R R W F E E E H K L N0 T Y VV_UX JTG_TK_FPG_V JTG_TI_FPG_V JTG_TO_FPG_V JTG_TMS_FPG_V JTG_RST#_FPG_V UF SUSPEN VINT_ ONE VINT_ PROG_ VINT_ TK VINT_ TI VINT_ TO VINT_ TMS VINT_ VUX_VINT_ VUX_VINT_ VUX_ VUX_ VUX_ VUX_ VUX_ VUX_ XS00N-FGG00 R.K_% R.K_% R J0 J K K L0 L M M N0.K_% V_V_FPG R.K_% R ONE_FPG_V K_% G VV_UX R0 K_% R PROG FPG_V _0.W_%_00 Must be High uring onfiguration to allow configuration to start JTG_TK_FPG_V JTG_TI_FPG_V JTG_TO_FPG_V JTG_TMS_FPG_V JTG_RST#_FPG_V LE_IFF_GREEN_ VV_UX R0 R 0uF_.V.K_% 0uF_.V 00K_0.W_%_00 0uF_.V R.K_%.K_%.K_%.K_% VV.K_%.K_%.K_% So R R R R R00 R0 VV_UX.K_% VV_UX,,.K_% SO_SSP0_MISO OOT MOE pins SO_I0_SL SO_I_SL SO_I_SL SO_I0_S SO_I_S SO_I_S SO_SSP0_LK SO_URT0_RX_V SO_URT0_TX_V SO_URT_TS_V SO_URT_RTS_V URT_RX_M SO_URT_TX_V SO_SSP_MOSI SO_SSP_MISO R VV NOR_SSPS SO_SSP0_MOSI,, SO_SPI_MISO SO_TIMI0_FPG_V SO_TIMI_FPG_V SO_TIMO0_FPG_V SO_TIMO_FPG_V % % SO_SSP_LK SO_SSP_S0 R R0 R R SO_SPI_LK SO_SPISS0 SO_SPISS SO_SPISS SO_SPI_MOSI R R % R TP TP TP TP R.K_%.K_% % _% _% % % R E_% R0 E_% R E_% E_% R E_% R0 R % SO_SSPK_R SO_SSPMOSI_R _% SO_SIM_LK SO_SIM_IO SO_SIM_RST N L M M M M L L0 K K0 K M L N M M L M N L J J H J L K K K K J L J F F F U0O SL0 SL SL S0 S S SPI0LK SPI0SS0 SPI0SS SPI0SS SPI0SS SPI0SS SPI0SIMO SPI0SOMI SPILK SPISS0 SPISS SPISS SPISIMO SPISOMI TIMI0_VSIFSEL0 TIMI_VSIFSEL TIMO0_SIS_0_MUX TIMO_SIS_0_LKTL URT0TS_SPILK URT0RTS_SPISS0 URT0RX URT0TX URTTS_SPISOMI URTRTS_SPISIMO URTRX URTTX USIMLK USIMIO USIMRST,,, FPG_SPI_S# FPG_SPI_SO R SO_PORZ_FPG_V_EXP SO_RESETFULLZ_FPG_V_EXP SO_RESETZ_FPG_V_EXP.K_% R0.K_% R.K_% FPG_SPI_S# FPG_SPI_SO FPG_SPI_WP# SO_RESETZ_FPG_V_EXP SO_PORZ_FPG_V_EXP SO_RESETFULLZ_FPG_V_EXP SO_RESETZ_FPG_V_EXP U S SO WP GN T-SSHL-T R0 R R V HOL SK SI 0.0uF_V 000pF_0V.K_%.K_%.K_% FPG_SPI_H# R R FPG_SPI_SI.K_% SO_PORZ_FPG_V_EXP SO_RESETFULLZ_FPG_V_EXP FPG_SPI_SK 0.0uF_V 000pF_0V 0.0uF_V 000pF_0V R R0.K_%.K_% LMRR_PROESSOR_0 R00 R0 0K_% 0K_% PHYSYN RSYN SO_TSREFLKN SO_TSREFLKP R 0_%_00 %,, SO_EXTFRMEEVENT, PHYSYN, RSYN SO_TSOMPOUT TSPUSHEVt0_E TSPUSHEVt_E SO_TSREFLKN_NET SO_TSREFLKP_NET SO_TSRXLKOUT0N SO_TSRXLKOUT0P SO_TSSYNEVT E J H G F H K K J J G U0S EXTFRMEEVENT PHYSYN RSYN TSOMPOUT TSPUSHEVT0 TSPUSHEVT TSREFLKN TSREFLKP TSRXLKOUT0N TSRXLKOUT0P TSSYNEVT KL EVM esigned for TI by einfochips FPG, KL SPI/TIM/URT, FPG test conn ocument Number _00_0.0 LMRR_PROESSOR_0 ate: Monday, June, 0 of

18 , 0 0 KL LVS SigMux, lock Mux, KL Reset, KL ML Serdes JES/IL, KL FE GPIO, KL FE Syncs/SysRef, KL lkin SO_JES_SYNIN0_P_FM SO_JES_SYNIN0_N_FM RP_LK_P_M RP_LK_N_M LK_MUXTRL0_FPG_V_EXP Note: ifferential signals Routing SO_JES_SYNIN_P_FM SO_JES_SYNIN_N_FM LK_MUXTRL0_FPG_V_EXP RP_F_P_M RP_F_N_M R0 U PLK0 nplk0 PLK nplk LK_SEL U0 N PLK0 nplk0 PLK nplk LK_SEL N VV_UX V N RESERVE VV_UX V V N RESERVE V Q nq 0 EP GN GN GN GN ISS0KILF Q nq 0 EP GN GN GN GN ISS0KILF SO_JES_SYNIN0_P SO_JES_SYNIN0_N SO_JES_SYNIN_P SO_JES_SYNIN_N EXT_0MHZ_M.MHZ_LKP_M.MHZ_LKN_M LK_MUXTRL_FPG_V_EXP 0 Note: ifferential signals Routing/Needs plane shielding MHZ_LKP_M MHZ_LKN_M.MHZ_SLVELKP.MHZ_SLVELKN LK_MUXTRL_FPG_V_EXP R.K_0.W_%_00 % R.K_0.W_%_00 Note: ifferential signals Routing/Place shielding U U PLK0 nplk0 PLK nplk LK_SEL PLK0 nplk0 PLK nplk N LK_SEL N VV_UX V N RESERVE V VV_UX V N RESERVE V Q nq 0 EP GN GN GN GN ISS0KILF Q nq 0 EP GN GN GN GN ISS0KILF Input lock swing = V V =.V R=.K, R=.K VREF=V*((R/(R+R)) =.V*((.K/(.K+.K)) =.V*((.K/.K) =~.V M_PRI_REFP M_PRI_REFN M_PRI_REFP M_PRI_REFN N EXT_0MHZ <haracteristic> OXIEL_V MML00TG_0V_0. VV_UX R.K_0.W_%_00 JES0/IF0_RXN_SO JES/IF_RXN_SO JES0/IF0_RXP_SO JES/IF_RXP_SO R K % JES_RXN_SO JES_RXN_SO JES_RXP_SO JES_RXP_SO EXT_0MHZ 0.0uF_V EXT_0MHZ_M 0. R 00K_0.W_%_00 0MHz clock input circuit added for positive clamp R K_0.W_%_ JES0/IF0_TXN_SO JES/IF_TXN_SO JES0/IF0_TXP_SO JES/IF_TXP_SO Note: ifferential signals Routing 0.uF_.V 0.uF_.V 0.uF_.V 0.uF_.V 0.uF_.V 0.uF_.V 0.uF_.V 0.uF_.V JES_TXN_SO JES_TXN_SO JES_TXP_SO JES_TXP_SO 0 0 R K % JES0/IF0_RXN_SO_NET JES/IF_RXN_SO_NET JES0/IF0_RXP_SO_NET JES/IF_RXP_SO_NET JES_RXN_SO_NET JES_RXN_SO_NET JES_RXP_SO_NET JES_RXP_SO_NET SO_FE_GPIO0 SO_FE_GPIO SO_FE_GPIO0 SO_FE_GPIO SO_FE_GPIO SO_FE_GPIO SO_FE_GPIO SO_FE_GPIO SO_FE_GPIO SO_FE_GPIO SO_FE_GPIO SO_FE_GPIO SO_FE_GPIO SO_FE_GPIO SO_FE_GPIO SO_FE_GPIO SO_FE_GPIO SO_FE_GPIO SO_JES_SYNIN0_N SO_JES_SYNIN_N SO_JES_SYNIN0_P SO_JES_SYNIN_P SO_JES_SYNOUT0_N_FM SO_JES_SYNOUT_N_FM SO_JES_SYNOUT0_P_FM SO_JES_SYNOUT_P_FM SYSREF_N_SO SYSREF_P_SO E J K0 J K F0 H G H G E J K J K E H G H G H J G0 J K0 K F K G H G K H K J G K K G F G F0 J0 H J H F0 E0 U0Q SHRE_SERES_0_REFRES SHRE_SERES_0_RXN0 SHRE_SERES_0_RXN SHRE_SERES_0_RXP0 SHRE_SERES_0_RXP RSV0 SHRE_SERES_0_TXN0 SHRE_SERES_0_TXN SHRE_SERES_0_TXP0 SHRE_SERES_0_TXP SHRE_SERES REFRES SHRE_SERES RXN0 SHRE_SERES RXN SHRE_SERES RXP0 SHRE_SERES RXP RSV0 SHRE_SERES TXN0 SHRE_SERES TXN SHRE_SERES TXP0 SHRE_SERES TXP LMRR_PROESSOR_0 U0T FEIO0 FEIO FEIO0_GPIO FEIO_GPIO FEIO_GPIO FEIO_GPIO FEIO_GPIO0 FEIO_GPIO FEIO_GPIO FEIO_GPIO FEIO_GPIO FEIO_GPIO FEIO_GPIO0 FEIO_GPIO FEIO_GPIO FEIO_GPIO FEIO_GPIO FEIO_GPIO FESYNINN0_RPLKN FESYNINN_RPFN FESYNINP0_RPLKP FESYNINP_RPFP FESYNOUTN0 FESYNOUTN FESYNOUTP0 FESYNOUTP FESYSREFN FESYSREFP SO_OOTOMPLETE_FPG_V_EXP SO_ORELKSEL0_FPG_V_EXP SO_ORELKSEL_FPG_V_EXP SO_ORESEL0_FPG_V_EXP SO_ORESEL_FPG_V_EXP SO_ORESEL_FPG_V_EXP SO_HOUT_FPG_V_EXP SO_LRESETNMIENZ_FPG_V_EXP SO_LRESETZ_FPG_V_EXP SO_NMIZ_FPG_V_EXP, SO_PORZ_FPG_V_EXP, SO_RESETFULLZ_FPG_V_EXP SO_RESETSTTZ_FPG_V_EXP, SO_RESETZ_FPG_V_EXP U0J G E OOTOMPLETE F ORELKSEL0 E ORELKSEL G ORESEL0_OOTMOE H ORESEL_OOTMOE H ORESEL_OOTMOE F HOUT K LRESETNMIENZ J LRESETZ G NMIZ E PORZ E RESETFULLZ F RESETSTTZ RESETZ LMRR_PROESSOR_0 K_% UF_.MHZ_LKP 0_% UF_.MHZ_LKN VV_UX R K_% R K_% R K_% R0 R0 U V Y Z Y Z Y EN Z EN Y 0 EN Z EN GN SNLVS0PWR VV_UX SIS_0_LKP LT_ORE_LKN LT_ORE_LKP SIS_0_LKP TP SIS_0_LKN SIS_0_LKN SIS_0_LKP SIS LKP SIS LKN 0 SIS LKN SIS LKP R SGMII_LKN RSV_LKP RSV_LKN 0_% SGMII_LKP 0 PIELKN_M TP 0 PIELKP_M 0 R_LKN 0 R_LKP 0 SO_PLLLOK_FPG_V_EXP TP TP0 RPLLOSLKN TP RPLLOSLKP SYS_LKN SYS_LKP TP SYSLKOUT_SO US_LKN 0 R 0_%_00 SIS_0_LKN Note: ifferential signals Routing R 0_%_00 % SIS LKN SIS LKP LT_ORE_LKN_NET LT_ORE_LKP_NET SIS_0_LKN_NET SIS_0_LKP_NET SIS LKN_NET SIS LKP_NET SGMII_LKN_NET SGMII_LKP_NET PIELKN_M_NET PIELKP_M_NET R_LKN_NET R_LKP_NET SYS_LKN_NET SYS_LKP_NET US_LKN_NET US_LKP_NET LMRR_PROESSOR_0 R 0_%_00 % U0K H0 G0 LTORELKN F LTORELKP F SHRE_SERES_0_REFLKN F SHRE_SERES_0_REFLKP F SHRE_SERES REFLKN F SHRE_SERES REFLKP F SGMIILKN E SGMIILKP E0 PIELKN G0 PIELKP F0 RLKN H RLKP E RSV00_ E RSV00 G RSV00_ F SYSLKN F SYSLKP R SYSLKOUT P USLKM USLKP SO_SSP_S SO_SSP_S SO_SSP_S R E_% R E_% R E_% R K_% US_LKP % LMRR_PROESSOR_0 oot mode pins,,,,,,,,,,,,,,,,,,, SO_GPIO_0_FPG_V_EXP SO_GPIO FPG_V_EXP SO_GPIO FPG_V_EXP SO_GPIO FPG_V_EXP SO_GPIO FPG_V_EXP SO_GPIO FPG_V_EXP SO_GPIO FPG_V_EXP SO_GPIO FPG_V_EXP SO_GPIO FPG_V_EXP SO_GPIO FPG_V_EXP SO_GPIO_0_FPG_V_EXP SO_GPIO FPG_V_EXP SO_GPIO FPG_V_EXP SO_GPIO FPG_V_EXP SO_GPIO FPG_V_EXP SO_GPIO FPG_V_EXP R R R R R R R R R R0 R R R00 R R0 R _% _% _% _% _% _% _% _% _% _% _% _% _% _% _% _% U0M G F GPIO00_SPISS_LENIN F GPIO0_SPISS_OOTMOE00 G GPIO0_SPISS_OOTMOE0 F GPIO0_SPISS_OOTMOE0 G GPIO0_TIMI_OOTMOE0 H0 GPIO0_TIMI_OOTMOE0 J GPIO0_TIMI_OOTMOE0 H GPIO0_TIMI_OOTMOE0 H GPIO0_TIMI_OOTMOE0 J GPIO0_TIMI_OOTMOE0 H GPIO0_TIMO_OOTMOE0 G GPIO_TIMO_OOTMOE0 H GPIO_TIMO_OOTMOE J0 GPIO_TIMO_OOTMOE K GPIO_TIMO_MINPLL_O_SEL GPIO_TIMO_RM_ENIN LMRR_PROESSOR_0 GPIO_SIS MUX GPIO_EMU GPIO_EMU0 GPIO_EMU GPIO0_EMU GPIO_EMU GPIO_EMU GPIO_EMU GPIO_EMU GPIO_EMU GPIO_EMU GPIO_EMU GPIO_EMU0 GPIO_EMU GPIO0_EMU GPIO_EMU K W Y V W V V U V V U T U T U T R _% SO_GPIO FPG_V_EXP, SO_EMU_ SO_EMU_0 SO_EMU_ SO_EMU_ SO_EMU_ SO_EMU_ SO_EMU_ SO_EMU_ SO_EMU_ SO_EMU_ SO_EMU_ SO_EMU_0 SO_EMU_ SO_EMU_ SO_EMU_ oot mode pin esigned for TI by einfochips KL EVM KL LVS SigMux, lock Mux, KL Reset, KL ML Serdes JES/IL, ocument Number _00_0.0 ate: Monday, June, 0 of

19 KL R SO_R_KP_0 SO_R_KN_0 R R.E_0.0W_%_00.E_0.0W_%_00 V_R 0, SO_R_[0..] SO_R_0 SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_0 SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ 0, SO_R_ TP 0, SO_R 0 0, SO_R 0, SO_R 0, SO_R_S# 0, SO_R_S_0# 0, SO_R_S_# 0, SO_R_KE_0 0, SO_R_KE_ 0, SO_R_KN_0 R0 0, SO_R_KP_0 0_% TP0 TP 0, SO_R_OT_0 0, SO_R_OT_ 0, SO_R_RS# 0, SO_R_RESETN R _0.W_%_00 R0 _0.W_%_00 R _0.W_%_00 V0VREF 0, SO_R_WE# <haracteristic> U0P R00 R00 R0 R0 E R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R00 R0 R0 R0 R0 R R0 R R0 E R R0 E R R0 R R0 E RSV00 R0 F R0 R0 E R R0 R R RSZ R RE0Z R E REZ R F RKE0 R RKE R RLKOUTN0 R RLKOUTN R RLKOUTP0 R E RLKOUTP R0 F RSV0 R RSV0 R F ROT0 R ROT R E RRSZ R F RRESETZ R F RRZQ0 R F RRZQ R F RRZQ R RVREFSSTL R0 RWEZ R R R R R R R R R R0 R R R R R R R R R R0 R R R R R R R R R R0 R R R RQM0 RQM RQM RQM RQM RQM RQM RQM RQM RQS0N RQS0P RQSN RQSP RQSN RQSP RQSN RQSP RQSN RQSP RQSN RQSP RQSN RQSP RQSN RQSP RQSN RQSP LMRR_PROESSOR_0 F F0 F E0 E E E E E F F F E F E F0 0 E0 0 E E E E F F E E F E E E0 E F 0 0 E E F E SO_R_E0 SO_R_E[0..] SO_R_E SO_R_E SO_R_E SO_R_E SO_R_E SO_R_E SO_R_E SO_R_Q0 SO_R_Q[0..] 0 SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q[..] 0 SO_R_Q SO_R_Q0 SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q[..] 0 SO_R_Q SO_R_Q SO_R_Q SO_R_Q0 SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q[..] 0 SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q0 SO_R_Q SO_R_Q SO_R_Q[..] 0 SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q0 SO_R_Q[0..] 0 SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q[..] SO_R_Q SO_R_Q0 SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q[..] SO_R_Q SO_R_Q SO_R_Q SO_R_Q0 SO_R_Q SO_R_Q SO_R_Q SO_R_M_0 0 SO_R_M_ 0 SO_R_M_ 0 SO_R_M_ 0 SO_R_M_ 0 SO_R_M_ 0 SO_R_M_ SO_R_M_ SO_R_M_ SO_R_QSN_0 0 SO_R_QSP_0 0 SO_R_QSN_ 0 SO_R_QSP_ 0 SO_R_QSN_ 0 SO_R_QSP_ 0 SO_R_QSN_ 0 SO_R_QSP_ 0 SO_R_QSN_ 0 SO_R_QSP_ 0 SO_R_QSN_ 0 SO_R_QSP_ 0 SO_R_QSN_ SO_R_QSP_ SO_R_QSN_ SO_R_QSP_ SO_R_QSN_ SO_R_QSP_ SO_R_0 SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_0 SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ R R R0 R R R R R R0 R R0 R0 R R R0 R.E_0.0W_%_00.E_0.0W_%_00.E_0.0W_%_00.E_0.0W_%_00.E_0.0W_%_00.E_0.0W_%_00.E_0.0W_%_00.E_0.0W_%_00.E_0.0W_%_00.E_0.0W_%_00.E_0.0W_%_00.E_0.0W_%_00.E_0.0W_%_00.E_0.0W_%_00.E_0.0W_%_00.E_0.0W_%_00 VTT_R Place these resistors at the end of the trace. 0 0 KL R 0.0uF_V 0.0uF_V 0.0uF_V SO_R 0 SO_R SO_R SO_R_OT_0 SO_R_WE# SO_R_RS# SO_R_S# SO_R_KE_0 SO_R_KE_ SO_R_S_0# SO_R_S_# SO_R_OT_ KL EVM R R R0 R R R R R R R R R Place these resistors at the end of the trace..e_0.0w_%_00.e_0.0w_%_00.e_0.0w_%_00.e_0.0w_%_00.e_0.0w_%_00.e_0.0w_%_00.e_0.0w_%_00.e_0.0w_%_00.e_0.0w_%_00.e_0.0w_%_00.e_0.0w_%_00.e_0.0w_%_00 VTT_R esigned for TI by einfochips ocument Number _00_ uF_V 0.0uF_V 0.0uF_V ate: Monday, June, 0 of

20 ,0,,0,,0,,0,,0,,0,,0,,0,,0,,0,,0,,0, SO_R_[0..] SO_R 0 SO_R SO_R SO_R_WE# SO_R_S# SO_R_RS# SO_R_S_0# SO_R_QSP_0 SO_R_QSN_0 SO_R_QSP_ SO_R_QSN_ SO_R_M_0 SO_R_M_ SO_R_KP_0 SO_R_KN_0 SO_R_KE_0 SO_R_OT_0 SO_R_0 SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_0 SO_R_ SO_R_ SO_R_ SO_R_ N P P N P P R R T R L R N T T M N M L K J L F G E J K K K R() 0 0/P /# 0 WE# S# RS# S# LQS LQS# UQS UQS# LM UM K K# KE OT U V. V. V. V. V. V. V. V. V. VQ. VQ. VQ. VQ. VQ. VQ. VQ. VQ. VQ. VREF VREFQ Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q R N K G K R N F H E H M H E F F F H H G H SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q0 SO_R_Q SO_R_Q SO_R_Q0 SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q V0VREF Trace need 0 mil. <haracteristic> SO_R_Q[0..] V_R SO_R_Q[..] uf_0v,0, SO_R_[0..],0,,0,,0,,0,,0,,0,,0,,0,,0,,0,,0, SO_R 0 SO_R SO_R SO_R_WE# SO_R_S# SO_R_RS# SO_R_S_0# SO_R_QSP_ SO_R_QSN_ SO_R_QSP_ SO_R_QSN_ SO_R_M_ SO_R_M_ SO_R_KP_0 SO_R_KN_0 SO_R_KE_0 SO_R_OT_0 SO_R_0 SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_0 SO_R_ SO_R_ SO_R_ SO_R_ N P P N P P R R T R L R N T T M N M L K J L F G E J K K K U 0 0/P /# 0 WE# S# RS# S# LQS LQS# UQS UQS# LM UM K K# KE OT V. V. V. V. V. V. V. V. V. VQ. VQ. VQ. VQ. VQ. VQ. VQ. VQ. VQ. VREF VREFQ Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q R N K G K R N F H E H M H E F F F H H G H V_R Trace need 0 mil. <haracteristic> <haracteristic> <haracteristic> <haracteristic> <haracteristic>.v V0VREF 0 <haracteristic> SO_R_Q SO_R_Q[..] SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q[0..] SO_R_Q SO_R_Q SO_R_Q SO_R_Q0 SO_R_Q SO_R_Q SO_R_Q uf_0v,0, * R pin M is used for as per JE standard T T SO_R_RESETN RESET# VSS.,0, SO_R_RESETN P R0 _0.W_%_00 L VSS. R _0.W_%_00 ZQ VSS.0 M VSS. J J VSS. G,0, SO_R_OT_,0, SO_R_OT_ L N. VSS.,0, SO_R_S_# * R pin M is used for,0, SO_R_S_# M N. VSS. J,0, SO_R_ VSS.,0, SO_R_ J N. T,0, SO_R_KE_ VSS. as per JE standard,0, SO_R_KE_ L N. P R _0.W_%_00 N. VSS. M R _0.W_%_00 VSS. E VSS. VSSQ.0 VSSQ. G VSSQ. E VSSQ. E VSSQ. VSSQ. VSSQ. F VSSQ. G VSSQ. * ata bits can be swapped within the byte lane to ease routing. * ddress/ommand/ontrol/lock routing must be Fly-y in byte order 0,,, E,,,,. MTKMH-:E T L J L M J L T RESET# VSS. P VSS. ZQ VSS.0 M VSS. J VSS. G N. VSS. N. VSS. J N. VSS. T N. VSS. P N. VSS. M VSS. E VSS. VSSQ.0 VSSQ. G VSSQ. E VSSQ. E VSSQ. VSSQ. VSSQ. F VSSQ. G VSSQ. MTKMH-:E,0, SO_R_[0..],0,,0,,0,,0,,0,,0,,0,,0,,0,,0,,0, SO_R 0 SO_R SO_R SO_R_WE# SO_R_S# SO_R_RS# SO_R_S_0# SO_R_QSP_ SO_R_QSN_ SO_R_QSP_ SO_R_QSN_ SO_R_M_ SO_R_M_ SO_R_KP_0 SO_R_KN_0 SO_R_KE_0 SO_R_OT_0 SO_R_0 SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_0 SO_R_ SO_R_ SO_R_ SO_R_ N P P N P P R R T R L R N T T M N M L K J L F G E J K K K 0 0/P /# 0 WE# S# RS# S# LQS LQS# UQS UQS# LM UM K K# KE OT U V. V. V. V. V. V. V. V. V. VQ. VQ. VQ. VQ. VQ. VQ. VQ. VQ. VQ. VREF VREFQ Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q R N K G K R N F H E H M H E F F F H H G H Trace need 0 mil. V_R V0VREF <haracteristic> SO_R_Q0 SO_R_Q[..] SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q[..] SO_R_Q SO_R_Q0 SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q uf_0v,0, * R pin M is used for as per JE standard SO_R_RESETN,0,,0,,0,,0, R SO_R_OT_ SO_R_S_# SO_R_ SO_R_KE_ R _0.W_%_00 _0.W_%_00 T RESET# VSS. L VSS. ZQ VSS.0 VSS. J VSS. L N. VSS. M N. VSS. J N. VSS. L N. VSS. N. VSS. VSS. VSS. VSSQ.0 VSSQ. VSSQ. VSSQ. VSSQ. VSSQ. VSSQ. VSSQ. VSSQ. MTKMH-:E T P M J G J T P M E G E E F G KL EVM esigned for TI by einfochips R() ocument Number _00_0.0 ate: Monday, June, 0 0 of

21 R(),.vaux ->.v R Vt, R SP EEPROM,0,,0,,0,,0,,0, SO_R_M_ SO_R_M_ * R pin M is used for as per JE standard,0,,0,,0,,0,,0,,0,,0,,0, SO_R_[0..] SO_R 0 SO_R SO_R SO_R_WE# SO_R_S# SO_R_RS# SO_R_S_0# SO_R_QSP_ SO_R_QSN_ SO_R_QSP_ SO_R_QSN_ SO_R_KP_0 SO_R_KN_0 SO_R_KE_0 SO_R_OT_0 SO_R_RESETN,0,,0,,0,,0, R0 R-XXXX iscretesrm rray SO_R_0 SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_0 SO_R_ SO_R_ SO_R_ SO_R_ SO_R_OT_ SO_R_S_# SO_R_ SO_R_KE_ R _0.W_%_00 % _0.W_%_00 U N P 0 V. P V. N V. P V. P V. R V. R V. T V. R V. L VQ. R 0/P VQ. N VQ. T /# VQ. T VQ. VQ. M VQ. N 0 VQ. M VQ. L VREF K WE# VREFQ J S# L RS# Q0 S# Q F Q G LQS Q LQS# Q UQS Q UQS# Q E Q LM Q UM Q J Q0 K K Q K K# Q KE Q K Q OT Q T RESET# VSS. L VSS. ZQ VSS.0 VSS. J VSS. L N. VSS. M N. VSS. J N. VSS. L N. VSS. N. VSS. VSS. VSS. VSSQ.0 VSSQ. VSSQ. VSSQ. VSSQ. VSSQ. VSSQ. VSSQ. VSSQ. MTKMH-:E R N K G K R N F H E H M H E F F F H H G H T P M J G J T P M E G E E F G SO_R_Q SO_R_Q0 SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q0 SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q SO_R_Q V0VREF Trace need 0 mil. <haracteristic> SO_R_Q[..] SO_R_Q[..] V_R uf_0v.v,0, * R pin M is used for as per JE standard SO_R_M_,0,,0,,0,,0,,0,,0,,0,,0,,0,,0,,0,,0, SO_R_[0..] SO_R 0 SO_R SO_R SO_R_WE# SO_R_S# SO_R_RS# SO_R_S_0# SO_R_QSP_ SO_R_QSN_ V_R R R SO_R_KP_0 SO_R_KN_0 SO_R_KE_0 SO_R_OT_0 SO_R_RESETN,0,,0,,0,,0, R R SO_R_0 SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_ SO_R_0 SO_R_ SO_R_ SO_R_ SO_R_ SO_R_OT_ SO_R_S_# SO_R_ SO_R_KE_ R.K_%.K_%.K_% _0.W_%_00 _0.W_%_00 N P P N P P R R T R L R N T T M N M L K J L F G E J K K K T L J L M J L FOR E USE 0 0/P /# 0 WE# S# RS# S# LQS LQS# UQS UQS# LM UM K K# KE OT RESET# ZQ N. N. N. N. N. U V. V. V. V. V. V. V. V. V. VQ. VQ. VQ. VQ. VQ. VQ. VQ. VQ. VQ. VREF VREFQ Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q VSS. VSS. VSS.0 VSS. VSS. VSS. VSS. VSS. VSS. VSS. VSS. VSS. VSSQ.0 VSSQ. VSSQ. VSSQ. VSSQ. VSSQ. VSSQ. VSSQ. VSSQ. MTKMH-:E R N K G K R N F H E H M H E F F F H H G H T P M J G J T P M E G E E F G V0VREF SO_R_E SO_R_E SO_R_E SO_R_E SO_R_E SO_R_E0 SO_R_E SO_R_E E_ R.K_% R.K_% R.K_% R.K_% R.K_% R.K_% R.K_% R0.K_% V_R <haracteristic> <haracteristic> <haracteristic> <haracteristic> <haracteristic>.v 0 Trace needs 0 mil. <haracteristic> uf_0v 0 SO_R_E[0..] V0V SP EEPROM V_R R0 0uF_.V V0V_EN V0VREF R0 0K_% VV_UX.uF_V K_% K_% R.uF_0V 0.0uF_V 0 0 U TPS00RT VIN PGOO REFIN VO VLOIN PGN EN VOSNS REFOUT GN EP EP EP EP EP EP VV_UX R0 TP 0K_% V0V_PGOO 0uF_.V 0uF_.V 0uF_.V 0uF_.V T TP VTT_R VV R 0K_% R 0K_% VV R0 0K_% R 0K_% VV R 0K_% R 0K_% KL EVM ddress: 0x U0 E0 E E VSS V W SL S VV ME0-FWTP 0 R 0K_% SO_I_SL, SO_I_S, esigned for TI by einfochips R(),.vaux ->.v R Vt, R SP EEPROM ocument Number _00_0.0 ate: Monday, June, 0 of

22 U0 J0 0 VSS_ VSS_ J 0 VSS_ VSS_ J VSS_ VSS_ J VSS_ VSS_ J VSS_ VSS_ J VSS_ VSS_ K 0 VSS_ VSS_0 K VSS_ VSS_ K VSS_ VSS_ K VSS_0 VSS_ K VSS_ VSS_ K VSS_ VSS_ K VSS_ VSS_ K VSS_ VSS_ K VSS_ VSS_ K VSS_ VSS_ K VSS_ VSS_0 L0 VSS_ VSS_ L VSS_ VSS_ L VSS_0 VSS_ L VSS_ VSS_ L VSS_ VSS_ L VSS_ VSS_ L0 0 VSS_ VSS_ L VSS_ VSS_ L VSS_ VSS_ L VSS_ VSS_0 L VSS_ VSS_ M 0 VSS_ VSS_ M VSS_0 VSS_ M VSS_ VSS_ M VSS_ VSS_ M VSS_ VSS_ M VSS_ VSS_ M VSS_ VSS_ M VSS_ VSS_ M VSS_ VSS_0 N VSS_ VSS_ N0 VSS_ VSS_ N VSS_0 VSS_ N VSS_ VSS_ N VSS_ VSS_ N VSS_ VSS_ N0 VSS_ VSS_ N VSS_ VSS_ N E0 VSS_ VSS_ N E VSS_ VSS_0 N E VSS_ VSS_ N E VSS_ VSS_ N E VSS_0 VSS_ N E VSS_ VSS_ P E VSS_ VSS_ P E VSS_ VSS_ P F VSS_ VSS_ P F VSS_ VSS_ P F VSS_ VSS_ P F VSS_ VSS_0 P F VSS_ VSS_ P F VSS_ VSS_ P G VSS_0 VSS_ P G VSS_ VSS_ P G VSS_ VSS_ P G0 VSS_ VSS_ P G VSS_ VSS_ P G VSS_ VSS_ P G VSS_ VSS_ R0 G VSS_ VSS_00 R H0 VSS_ VSS_0 R H VSS_ VSS_0 R H VSS_0 VSS_0 R H VSS_ VSS_0 R0 H VSS_ VSS_0 R H VSS_ VSS_0 R J VSS_ VSS_0 R J VSS_ VSS_0 R J VSS_ VSS_0 R J0 VSS_ VSS_0 R J VSS_ VSS_ T J VSS_ VSS_ T J VSS_0 VSS_ T K VSS_ VSS_ T K VSS_ VSS_ T K VSS_ VSS_ T K VSS_ VSS_ T K VSS_ VSS_ T K VSS_ VSS_ T K VSS_ VSS_0 T K0 VSS_ VSS_ T VSS_ VSS_ U0 VSS_0 VSS_ U VSS_ VSS_ U VSS_ VSS_ U VSS_ VSS_ U VSS_ VSS_ U VSS_ VSS_ U0 VSS_ VSS_ U 0 VSS_ VSS_0 U VSS_ VSS_ U VSS_ VSS_ U VSS_00 VSS_ U VSS_0 VSS_ V F VSS_0 VSS_ V F VSS_0 VSS_ V G VSS_0 VSS_ V G0 VSS_0 VSS_ V G VSS_0 VSS_ V G VSS_0 VSS_0 V G VSS_0 VSS_ V G VSS_0 VSS_ V G0 VSS_0 VSS_ V G VSS_ VSS_ W0 G VSS_ VSS_ W G VSS_ VSS_ W G VSS_ VSS_ W G VSS_ VSS_ W G VSS_ VSS_ W0 H VSS_ VSS_0 W H VSS_ VSS_ W H VSS_ VSS_ W H VSS_0 VSS_ W H VSS_ VSS_ W H VSS_ VSS_ Y H VSS_ VSS_ Y H VSS_ VSS_ Y H VSS_ VSS_ Y H VSS_ VSS_ Y H VSS_ VSS_0 Y H VSS_ VSS_ Y J0 VSS_ VSS_ Y J VSS_0 VSS_ Y J VSS_ VSS_ Y J VSS_ VSS_ Y VSS_ VSS_ LMRR_PROESSOR_0 KL GN N POWER V T V T THESE PS RE E FOR PROVISION ONLY. VLUES N E HNGE SE ON PI NLYSIS RESULT 00 Place near to SO pins T 00 T Place near to SO pins THESE PS RE E TO SUPPORT PER PIN EP. SE ON PI NLYSIS RESULT, IT WILL E HNGE (# OF PITORS, VLUES, ET) V 0 T T T 00 T T T T NEWLY E EPS FOR PI (NOS E) T T 0 T T T T T 0 T 0 T T T 0 T T T T V 0 T T T T 00 0 T T T T 0 T T 0 T T 0 T T KL EVM T KL GN N POWER T esigned for TI by einfochips ocument Number _00_0.0 ate: Monday, June, 0 of

23 KL US, TPS US v isolation, US Type connector, magnetics, filter, SO URT./.v, US to dual URT VV V.K_% V uf_v R0 R0 VUS0 KL US U0U R US0N P USM US0P US0RVUS M USP K_% N USRVVUS 0_0.W_%_00 M USI0 T USRESREF US0_RXN R USRX0M US0_RXP M USRX0P US0_TXN L USTX0M US0_TXP N USTX0P R0 USVUS LMRR_PROESSOR_0 US0VUS V US_VUS_EN TPS US v isolation uf_v Note: For US Power Isolation VUS0 U VIN VOUT U R0 V V US0RVUS R GN SNLVG0VR ON GN TPSYZVR R0 M0-00-P-T00 US0P L US0N M0-00-P-T00 US0_RXN L US0_RXP M0-00-P-T00 US0_TXN L US0_TXP US0VUS V US SWITH U IN OUT GN EN FLT TPS0VR <haracteristic> 00uF 0V USN_R USP_R US_RXN_R US_RXP_R US_TXN_R US_TXP_R US Type connector US.0 TYPE-- ONN. J US.0 Type VUS - + GN Std_SSRX- Std_SSRX+ GN_RIN Std_SSTX- Std_SSTX+ H H PTH_ PTH_ E N E N E N E N E N E N US.0_H US_SHIEL 0 NG GN US_SHIEL SP0-0UTG U0 F 0_00MHz 00 US_SHIEL SO URT./.v VV VV_UX US to dual URT Vbus mode option enabled VV.K_% SO_URT0_RX_V SO_URT0_TX_V SO_URT_RTS_V SO_URT_TS_V R0 0 OE V GN V U 0 TI_TXS00EPWR SO_URT0_RX_V SO_URT0_TX_V SO_URT_RTS_V SO_URT_TS_V PTH PTH F J -0 US_VUS_R VUS - + I GN 0_00MHz_0._00 US_VUS F US_VUS 0_00MHz 00 VV_UX R R US_VIO 0 OHM IFF. IMPENE ONTROL US_VUS R0.K_% % U RST - + VUS.V REGIN uf_v V VIO US_VIO.V RTS_EI 0 TS_EI RX_EI TX_EI GPIO._EI / SR_EI GPIO.0_EI / TR_EI N / _EI / VPP SUSPEN / RI_EI 0 RX_SI TX_SI RTS_SI TS_SI GPIO._SI / SR_SI GPIO._SI / TR_SI GPIO.0_SI / _SI SUSPEN / RI_SI uf_v R V.uF_V VV_UX P0_SO_U0RX MU_P_U0TX,0 P0_MU_U0RX VV_UX R.K_% % SO_URT0_TX_V, SO_URX_V P0_SO_U0RX U Y GN V G / Y TI_SNLVGUR VV_UX PIN_URT0-ETET# SO_URT0_RX_V HSSIS_GN 0KV HSSIS_GN TPS0RYR US_VUS_R GN P P0-F0-GM esigned for TI by einfochips KL EVM KL US, TPS US v isolation, US Type connector, magnetics, filter, SO URT./.v, US to dual URT ocument Number _00_0.0 ate: Monday, June, 0 of