ADC IF1_P IF1_N INT_OSC_EN INT_OSC_EN ADC_PWDN ADC_PWDN INT_OSC_EN ADC_PWDN UC_CTRL[1-2] UC_DATA[0-7] FPGA_PROG[1-5] RF_POWER_DET

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Derick Rogers
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1 MIXER FPG RF RF_MP_OUT RF_MP_OUT RF_POWER_ET RF_MP_ MIXER LOP LON IF_P IF_N IF_P IF_N T_OS_EN _PWN IF_P IF_N T_OS_EN _PWN _LK _[0-] _OR _LK _[0-] _OR LK_REF _LK _[0-] _OR LK_REF RF_G_TRL RF_G_TRL RF_G_TRL RF_G_TRL _PWN RF MIRO SYNTHESIZER LOP LON RF_POWER_ET _PWN RF_POWER_ET T_OS_EN U_TRL[-] U_T[0-] FPG_PROG[-] T_OS_EN U_TRL[-] U_T[0-] FPG_PROG[-] U_TRL[-] U_T[0-] FPG_PROG[-] FPG LK_REF SYNTH_TRL[0-] SYNTH_ENLE LK_REF SYNTH_TRL[0-] SYNTH_ENLE RF_G_TRL RF_G_TRL LK_REF SYNTH_TRL[0-] SYNTH_ENLE FPG_HSWPEN HSWPEN T_OS_EN SYNTH_ENLE FPG0 HSWPEN T_OS_EN SYNTH_ENLE SYNTHESIZER POWER G_ PLL_STROE G_ PLL_STROE G_ PLL_STROE PGOO[-] PGOO[-] PGOO[-] M&_[-] M&_[-] M&_[-] POWER MIRO FPG0 TLE OF ONTENTS Z M... MIXER POWER... Flower Hill Way Gaithersburg, M 0 US FPG0... FPG... MIRO... RF... SYNTHESIZER... General Layout Notes: - use R00 for all 00 - use R00 for all 00 - Label all TPs' names on SST OM-0 / M Size ocument Number Rev Y00 ate: Monday, May, 0 Sheet of

2 _+.V _+.V 00pF;00 +.V _+.V _ TP should be labeled IF_P IF_N alun should be as close as possible to R 00R;00;% ommon mode voltage: V/ _+.V R K;00;% R K;00;% T X0LNL _ Test Point TP Vpp differential input span TP 0 R;00;% R R;00;% R R R-OPEN;00 -OPEN;00 0 R 0R;00;% R0 0K;00;% _+.V 0 0.V Range VREF 's complement + duty cycle stabilizer U V+ V- REFT REF SENSE MOE V V RV PZ-0 0-IT 0 MSPS R R N N 0R;00;% PWN N N N N 0_LS 0 0 _MS OR LK -OPEN; _PWN _[0-] ontingency: trade-off 0//-bit precision for sampling speed, _OR 00 MHz Internal Oscillator Reference Y R E/ OUT V 0nH;00 OSILLTOR _ Route _LK through the pin and then to FPG, don't split using a Y trace _LK T_OS_EN LK_+.V FR LMKGTN _ nalog signals igital signals Z Flower Hill Way Gaithersburg, M 0 US OM-0 / Size ocument Number Rev Y00 ate: Monday, May, 0 Sheet of

3 _+.V _+.V U _+.V _+.V T_OS_EN SYNTH_ENLE PLL_STROE M&_[-] HSWPEN Monitoring & ontrol _ PLL_STROE HSWPEN HSWPEN OUTPUT_0 OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ LK_OUT OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_0 OUTPUT_ T_OS_EN SYNTH_ENLE M&_ {RIGHT_RX} M&_ {RIGHT_TX} M&_ {OT_RX} M&_ {OT_TX} 0 F0 E 0 0 E F E E VO_0_0 VO_0_0 VO_0_0 VO_0_0 IO_LP_GLK_0 IO_LN_GLK_0 IO_LP_GLK_0 IO_LN_GLK_0 IO_LP_GLK_0 IO_LN_GLK_0 IO_LP_GLK_0 IO_LN_GLK_0 XSLX-SG Note: Other FPG banks can be found on their respective functions' primary schematic page VO 0 VO 0 VO 0 VO 0 IO_LP_HSWPEN_0 IO_LP IO_LN_VREF_0 IO_LN VREF_ IO_LP_0 IO_LP M0_ IO_LN_0 IO_LN M_ IO_LP_0 IO_LP M_ IO_LN_0 IO_LN_0_M_ IO_LP_0 IO_LP M0_ IO_LN_0 IO_LN M_ IO_LP_0 IO_LP M0_ FPG IO_LN_0 IO_LN M_ IO_LP_0 IO_LP MLK_ IO_LN_0 IO_LN MLKN_ IO_LP_0 IO_LP_M_ IO_LN_0 IO_LN_MOT_ IO_L0P_0 ank 0 & IO_LP MQ_ IO_L0N_0 IO_LN MQ_ IO_LP_0 IO_LP MLQS_ IO_LN_VREF_0 IO_LN_0_MLQSN_ IO_LP_SP_0 IO_LP_FS MQ_ IO_LN_SP_0 IO_LN_FOE MQ_ IO_LP_SP_0 IO_LP_FWE MQ0_ IO_LN_SP_0 IO_LN_L_MQ_ IO_LP_SP_0 IO_LP_WKE_ IO_LN_SP_0 IO_LN_OUT_USY_ IO_LP_SP_0 IO_LN_SP0_0 LXN_IO_L0P MRESET_ LXN_IO_L0N_0_M_ LXN_IO_LP_0 LXN_IO_LP MKE_ LXN_IO_LN_0 LXN_IO_LN M_ LXN_IO_LP_0 LXN_IO_LP M_ LXN_IO_LN_0 LXN_IO_LN M_ LXN_IO_LP_0 LXN_IO_LP MWE_ LXN_IO_LN_VREF_0 LXN_IO_LN M_ IO_L0P_GLK_M_ IO_L0N_GLK0_M_ IO_LP_GLK_IRY_MRSN_ IO_LN_GLK_MSN_ IO_LP_GLK_MUM_ IO_LN_GLK_TRY_MLM_ IO_LP_GLK_MQ_ IO_LN_GLK_MQ_ ottom onnector J _ PLL_STROE M&_ {OT_TX} M&_ {OT_RX} 0 _ TMMH-0-0-L- same location as 00: J H J M J J E E K0 K F F K K L L M M N N P P G G F F H0 H H G K L G G H H J J OUTPUT_ OUTPUT_0 OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ PLL_STROE T_OS_EN SYNTH_ENLE G_ EXT LK OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_0 R filtering required when G_ is a PWM signal G_ Place R filter close to 0-pin connector Sensitive Input lock Trace EXT LK _ -OPEN;00 Place clock capacitors close to the FPG Z & K Flower Hill Way Gaithersburg, M 0 US 0 Pin OUTPUT LK_OUT OUTPUT_0 OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_0 OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_0 OUTPUT_ R 00K;00;% EXT LK OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ M&_{RIGHT_TX} M&_{RIGHT_RX} OUTPUT_ OUTPUT_ OUTPUT_0 _ OM-0 / FPG NKS 0/ & ONNETOR Size ocument Number Rev Y00 ate: Monday, May, 0 Sheet of J TMMH-0-0-L--R

4 G H M M L P P N N M M L L K K K J F F E E E J H G G H H F F E E J J H H K J G G E0 E U Note: Other FPG banks can be found on their respective functions' primary schematic page VO 0 VO 0 VO 0 VO 0 VO 0 VO 0 VO 0 VO 0 IO_LP_ PROGRM IO_LN_VREF_ IO_LP_LK_ IO_LP_ IO_LN_MOSI_SI MISO0_ IO_LN_ IO_LN_RWR VREF_ IO_LP_MQ0_ ONE_ IO_LN_MQ_ IO_LP_IT IO_LP_MQ_ SUSPEN IO_LN_MQ_ MPS IO_LP_MLQS_ IO_LN_MLQSN_ IO_LP_0 MISO_MISO_ IO_L0P_MQ_ IO_LP MISO_ IO_L0N_MQ_ IO_LN MISO_ IO_LP_M_ IO_LP IO_LN_MOT_ IO_LN IO_LP_MLK_ IO_LP IO_LN_MLKN_ IO_LN IO_LP_M_ IO_LP IO_LN_M_ IO_LP_MKE_ IO_LN_M0_MPMISO_ IO_LN_M_ IO_LP_M_ FPG IO_LP_MRESET_ IO_LN_M_ IO_LP_ IO_LP_MPLK_ IO_LN_VREF_ IO_LN_MPMOSI_ ank & IO_LP LXN_IO_LP_M0_ IO_LN LXN_IO_LN_M_ IO_LP_ LXN_IO_LP_M0_ IO_LN_VREF_ LXN_IO_LN_M_ IO_LP_ LXN_IO_LP_M_ IO_LN_ LXN_IO_LN_M_ IO_LP LXN_IO_L0P_MWE_ IO_LN LXN_IO_L0N_M_ IO_LN_0_ LXN_IO_LP_M0_ IO_LN_SO LXN_IO_LN_M_ LXN_IO_LP_ IO_LP_GLK_MQ_ LXN_IO_LN_ IO_LN_GLK_MQ_ LXN_IO_LP_ IO_LP_GLK_TRY_MUM_ LXN_IO_LN_ IO_LN_GLK_MLM_ IO_LP_GLK_MRSN_ IO_LP_GLK_ IO_LN_GLK_IRY_MSN_ IO_LN_GLK_ IO_LP_GLK_M_ IO_L0P_GLK IO_LN_GLK0_M_ IO_L0N_GLK0_USERLK_ IO_LP_GLK TK JTG inputs IO_LN_GLK0 TI internally IO_LP_GLK_ TO pulled-up, see IO_LN_GLK_ TMS ug0 h. M P P P _+.V R {PROG} FPG_PROG N {LE_LK} U_TRL R {SI} FPG_PROG R {RE_RWR} U_TRL R {ONE} FPG_PROG TP P {IT} FPG_PROG ONE L {SUSPEN} FPG_PROG L0 _+.V U_T[0-] P M N P R L L N R N0 P R L M0 P R N R M N R0 R M N L M N R M N K L P R U_T0 U_T U_T U_T U_T U_T U_T U_T +.V 0 µ Interface Slave SelectMP Programming onfiguration _0 PWN _OR _LK LK_REF _+.V FPG ONFIGURTION 0 _+.V R.K;00;% FPG_PROG {PROG} _+.V R R-OPEN;00 U_TRL {LE_LK} _ R0 R-OPEN;00 _+.V R 0R;00 FPG_PROG {ONE} _+.V R.K;00;% FPG_PROG {IT} [0-] K & Z - Route U_TRL as 0ohm trace - place termination R-OPENs closest to FPG Flower Hill Way Gaithersburg, M 0 US FPG Programming FPG_PROG {PROG} FPG_PROG {ONE} FPG_PROG {IT} FPG_PROG {SUSPEN} FPG_PROG {SI} U_TRL {LE_LK} U_TRL {RE_RWR} LK_REF LK_REF: 0 MHz Sampling clock (from synthesizer's oscillator) _LK _LK: 00 MHz Input sampling clock (from internal oscillator) or T MHz from FPG PLL _PWN _OR LK_REF _LK _PWN _OR FPG_PROG[-] U_TRL[-] XSLX-SG R 0R;00;% JTG isabled _ Sensitive Input lock Trace U_TRL {LE_LK} -OPEN;00 Place clock capacitors close to the FPG _ OM-0 / FPG NKS / Size ocument Number Rev Y00 ate: Monday, May, 0 Sheet of

5 U_TRL[-] U_T[0-] FPG_PROG[-] M&_[-] Shared µ Interface U_TRL {LE_LK} U_TRL {RE_RWR} U_T0 U_T U_T U_T U_T U_T U_T U_T FPG Programming FPG_PROG {PROG} FPG_PROG {ONE} FPG_PROG {IT} FPG_PROG {SUSPEN} FPG_PROG {SI} Monitoring & ontrol M&_ {RIGHT_RX} M&_ {RIGHT_TX} M&_ {OT_RX} M&_ {OT_TX} _+.V 0nF;00 0 0nF;00 _ SYNTH_ENLE _PWN PLL_STROE FPG_HSWPEN RF_POWER_ET RF_G_TRL U _+.V R R V_ V_ V_ V_ 0R;00;% 0R;00;% VT VREG_ VREG_ FPG_PROG {PROG} FPG_PROG {SUSPEN} P0[0]/R/TX/S M&_ {LEFT_TX} P0[]/T/RX/SL M&_ {LEFT_RX} 0 P0[]/TX0/0[] FPG_PROG {ONE} P0[]/RX0/0[] FPG_PROG {IT} P0[]/ISRX_S/SSEL/MT[0] P0[]/ISTX_LK/SK/MT[] P0[]/ISTX_WS/MISO/MT[] M&_ {OT_TX} P0[]/ISTX_S/MOSI/MT[] M&_ {OT_RX} 0 P0[0]/TX/S/MT[0] M&_ {TOP_TX} P0[]/RX/SL/MT[] M&_ {TOP_RX} P0[]/TX/SK0/SK P0[]/RX/SSEL0/SSEL P0[]/TS/MISO0/MISO P0[]//MOSI0/MOSI P0[]/RTS/T P0[]/0[]/ISRX _S/TX P0[]/0[]/OUT/RX V 0 VREFP VREFN _ 0 _ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS P[0]/VUS/0[] P0[0]/US_- P0[]/US_+ P[0]/PWM[]/TX P[]/PWM[]/RX P[]/PWM[]/TS/TRET[] P[]/PWM[]//TRET[] P[]/PWM[]/SR/TRET[] P[]/PWM[]/TR/TRET[0] P[]/PP[0]/RI/TRELK P[]/R/RTS P[]/T/TX P[]/US_ONNET/RX P[0]/ET0/NMI 0 0 Z match + & - to 0 ohm diff U_T0 U_T U_T U_T U_T U_T U_T U_T U_TRL {LE_LK} U_TRL {RE_RWR} R FPG_PROG {SI} 0K;00;% US_ONNET US_+.0V U_US_M U_US_P _+.V R.K;00 G R0 R FR LMKGTN Q S +.V FN0P R.K;00 R;00;% R;00;% Place.uF close to US connector J _ VUS - + I SHIEL SHIEL SHIEL SHIEL US_MI REEPTLE US connector should be in the same location as the OM0 US PGOO[-] Power Good Indicators PGOO {_+.V} PGOO {MP_+V} PGOO {_+.V} PGOO {LK_+.V} PGOO {SYNTH_+.V} SYNTH_TRL[0-] T_OS_EN RF_G_TRL G_ PGOO {_+.V} PGOO {MP_+V} PGOO {_+.V} PGOO {LK_+.V} PGOO {SYNTH_+.V} SYNTH_TRL0 SYNTH_TRL SYNTH_TRL SYNTH_TRL US_ONNET MOE_PWMOUTu {LK} {T} {LE} {L} P[0] P[] P[] P[] P[] 0 P[0] P[] P[] P[]/US_UP_LE/PWM[]/P[0] P[]/M0/US_PPWR/P[] P[0]/MI0/PWM[]/SK0 P[]/MO0/US_PWR/MT[0] 0 P[]/MI/PWM[]/MISO0 P[]/MI/PWM[]/MOSI0 P[]/MO/MT[] P[]/MO/PWM[]/P0[0] P[]/MO/PP[0]/MT0[0] P[]/MO/PP[]/MT0[] P[]/SK/0[] LPF uF;.V;T; Place 00uF near micro pin on bot layer _ RM ortex-m µ P[]/RX_MLK/MT[0]/TX P[]/TX_MLK/MT[]/RX TRST TI TMS/SWIO TK/SWLK TO/SWO RESET RSTOUT XTL 0 XTL RTX RTX M&_ M&_ {RIGHT_TX} {RIGHT_RX} RM_JTG_TRST RM_JTG_TI RM_JTG_TMS RM_JTG_TK RM_JTG_TO 00pF;00 00pF;00 R 0K;00;% 00 _ Y not populated TR-.KHZ _+.V _ LK_REF -OPEN;00 -OPEN;00 dd pin labels on SST: _, _+.V, MOE Provision for RS- not populated 0 M&_ {TOP_TX} M&_ {TOP_RX} +.V U _+.V RS- TXVR SP0E-L V +.V _ + - T TOUT ROUT R 0 VLI EN V+ FOREON V- FOREOFF _ RS- Header J TSW-0-0-F-S dd pin labels on SST:, RX, TX 0 _+.V Microcontroller Programming Interface J M&_ {LEFT_RX} M&_ {LEFT_TX} R _ R 0K;00;% JTG {E_} U_RESET {RST} EGE RM_JTG_TO FPG_PROG {SI} 0 RM_JTG_RTK _+.V R0 0K;00;% RM_JTG_TRST ONNETOR 0 RM_JTG_TK _+.V R 0K;00;% RM_JTG_TI RM_JTG_TMS _+.V ME-0-0-S--R-SL R R R R R R RM_JTG_TRST ontingency: use as mode input or pwm output MOE_PWMOUTu 0R;00;% LPF placement should be near micro K R R-OPEN;00 0K;00;% _ Flower Hill Way R-OPEN;00 _+.V Gaithersburg, M 0 0K;00;% _ US 0K;00;% _+.V 0K;00;% _+.V JP - Mode Select Jumper MOE_PWMOUT _ OM-0 / MIRO _+.V _ Size ocument Number Rev Y00 JP TSW-0-0-F-S -OPEN;00 ate: Monday, May, 0 Sheet of

6 MIXER_+.V MIXER_+.V VSET R R-OPEN;00 Fixed bias setting, +V Mixer supply current 0 m MIXER_+.V 00pF;00 MIXER_+.V 00pF;00 _+.V FR LMKGTN 0m 0pF;00 0pF;00 R 0R;00;% optional automatic input IP control J ETO EXTERNL LO SM ONNETOR SGLE ENE SM_EGE_FEMLE R0 R-OPEN;00 0 Ohm differential trace LOP LON 0 00pF;00 R 0R;00;% R 0R;00;% MOVE RES FOR TERNL / EXTERNL LO 00pF;00 scale down to.v max R 0K;00;% R R-OPEN;00 R R-OPEN;00 R K;00;% Zero Ohm resistors share pads at junctions RF power detection, -dm to 0 dm. RF_MP_ RF_POWER_ET Nominal level: +0dm 0 dm T 00 Ohm differential traces for LO and RF Inputs. MHz -. GHz XNL T XNL VSET ETO 0nF;00 0nF;00 0nF;00 0nF;00 0 U ENL VSET ETO RFIP RF LOIP LO L0PZ-R VPLO VPLO MIXER_+.V VPT 0-000MHZ IRET ONVERSION MIXER MIXER_+.V VPRF IFOP 0 IFON N MIXER_+.V MIXER_+.V 0nH;00;00m;SRF0MHz;.R L 0nH;00;00m;SRF0MHz;.R L 0nF;00 0nF;00 R R-OPEN;00 pf;00 L 0nH;00 R R-OPEN;00 pf;00 pf;00 R R-OPEN;00 0pF;00 pf;00 andpass filter enter: MHz andwidth: 0 MHz (two-sided) L uh;00;srfmhz.pf;00 L 0nH;00 L0 uh;00;srfmhz R R-OPEN;00.pF;00 L 0nH;00 R.pF;00 R-OPEN;00 L 0nH;00 IF_P IF_N Z Flower Hill Way Gaithersburg, M 0 US OM-0 / MIXER Size ocument Number Rev Y00 Monday, May, 0 ate: Sheet of

7 +V Supply Green Terminal lock OPERTIONL RNGE:. -.V J TT+ TT- _ FR LMKGTN Reverse Voltage Protection Q S G FN0P TVS SMJ.0-E Over Voltage Protection (.V) Q & Q must be placed and routed Q for a high current throughput. FMMTT R R;00;% ZXV R 0K;00;% N R K;00;% Q FMMTT Place Vin caps as close as possible to Vin and P pins 0 0nF;00 _ 0 0 R.K;00;% NPMNTWG / converter: max peak output current MHz switching U VP V OMP NPMNTWG NP / onverter P LX F VREF=0.V L.uH;. R.K;00;% R 0K;00;% Ityp = ~. Vout =.V 0 00uF;.V;T; 0 _+.V FR LMKGTN TTN_+.V _ PGOO _ PGOO PGOO _ PGOO _ {_+.V} {MP_+V} {_+.V} _ {LK_+.V} U LO OUT dj 00mOUT SHN# FULT# SET LPIMM-J NOP _ R U 0R;00;% LO OUT dj 00mOUT SHN# 0 FULT# LPIMM-J NOP _ TVS component placed near Over Voltage Protection circuit _ away from terminal block _ 0 U0 LO OUT dj 00mOUT SHN# FULT# SET LPIMM-J NOP SET U LO OUT dj 00mOUT SHN# FULT# SET LPIMM-J NOP 0 _ Imax = 0m Vout =.V 0 R0 K;00;% R 00K;00;% Imax = m Vout =.00V R0 0K;00;% R 00K;00;% Imax = m Vout =.V R 0K;00;% R 00K;00;% 00uF;.V;T; Imax = 0m Vout =.V R0 K;00;% R00 00K;00;% 0 First RF stages PGOO RF amps, mixer, gain control +.V LMKGTN FR _+.V 0m LMKGTN FR _+.V _ MP_+V _+.V LK_+.V _ PGOO[-] m Vin _ {SYNTH_+.V} H Power Good Indicators PGOO {_+.V} PGOO {MP_+V} PGOO {_+.V} PGOO {LK_+.V} PGOO {SYNTH_+.V} P Mounting Holes H H _ 0.nF;00 U LO OUT dj 00mOUT SHN# FULT# LPIMM-J NOP SET H _ Imax = 0m Vout =.V R K;00;% R0 00K;00;% _ R 0R;00;% Power Requirements (*T) OMP V m RF MP +.0 RF MP +. FPG +. 00* MIRO +. 0* +. 0 FPG _ Place 0 Ohm resistors near LRs SYNTH_+.V FR LMKGTN SYNTH_+.V 0 K Flower Hill Way Gaithersburg, M 0 US _ FPG Power _+.V _+.V _+.V _ OM-0 / POWER _+.V return path ate: Monday, May, 0 Sheet of Size ocument Number Rev Y00 R 0R;00;% U F G VT0 G VT0 H VT0 H VT0 J0 VT0 J VT0 K VT0 VT0 E VUX0 F VUX0 G0 VUX0 J VUX0 K VUX0 L VUX0 M VUX0 VUX0 FPG Supply XSLX-SG E 0 F 0 F 0 F 0 G G H J J K K K L N 0 N P0 P R R

8 RF_G_TRL Optional R LPF R RF_G_TRL 0R;00;% -OPEN;00 0 -OPEN;.V;T; Place near FR LMKGTN FR LMKGTN MP_+V MP_+V _+.V _+.V FR LMKGTN L0 FR0 L 0nH;00;00m;SRF0MHz;.R LMKGTN FR 0nH;00;00m;SRF0MHz;.R FR LMKGTN LMKGTN 0nF;00 00pF;00 L 00pF;00 L nh;00;00m;srf.ghz 0nF;00 nh;00;00m;srf.ghz 00pF;00 0nF;00 L 0nH;00;00m;SRF0MHz;.R L 0nF;00 0nH;00;00m;SRF0MHz;.R L 0nH;00;00m;SRF0MHz;.R 00pF;00 00pF;00 L 0nH;00;00m;SRF0MHz;.R R 00pF;00 0 RF PUT L 0R;00;% L U nh;00;00m;srf.ghz nh;00;00m;srf.ghz L R SM_P_0_MLE U nh;00;00m;srf.ghz 0R;00;% L 0nF;00 U nh;00;00m;srf.ghz V 0nF;00 0nF;00 U RF_ PUT V 0nF;00 0 MHz - GHz OUT PUT V 0nF;00 0nF;00 +0 dm max OUT PUT V 0nF;00 R OUT PUT RF_MP_OUT 0R;00 R OUT - 0R;00 R R J HSMP- - 0R;00 0R;00 - HSMP- - R R same location as 00: J G =.d.k;00;% G =.d G =.d Pdb = +.dm 0nF;00.K;00;% 0nF;00 Pdb = +.dm Pd= +.dm 0 R0 R.K;00;% G =.d 0nF;00.K;00;% 0nF;00 Pd= +.dm L 0nH;00;00m;SRF0MHz;.R L 0nH;00;00m;SRF0MHz;.R 00pF;00 0nF;00 0 TTN_+.V 00pF;00 0nF;00 0 TTN_+.V G = - to -d G = - to -d st SHIEL = d G MX st SHIEL = d G MX Z Flower Hill Way Gaithersburg, M 0 US OM-0 / RF Size ocument Number Rev Y00 Monday, May, 0 ate: Sheet of

9 EXTERNL FREQUENY REFERENE J SM_EGE_FEMLE _ LK_+.V _ R 0R;00;% SM edge location should be the same with OM0 SM location 0/0 MHz frequency reference. 0.Vpp min,.vpp max 0 _ V Y NSZ0PX LK_+.V V LK_+.V _ U N U N LK_+.V SYNTH_TRL[0-] LK_+.V R.K;00;% _ R 0K;00;%.V Zener: Prevent over/under-voltage damage to NSZ0 at analog inputs. -OPEN;00 SYNTH_TRL0 {LK} R SYNTH_TRL {T} R SYNTH_TRL {LE} R SYNTH_TRL {L} R SYNTH_PLL_LOK {MUXOUT} R 0R;00;% 0R;00;% 0R;00;% 0R;00;% 0R;00;% 0 _ Route the sensitive 0MHz_REF & 0MHz_REF_ traces away from noise sources TZM 0pF;00 SYNTH_+.V U V_VO V_VO LK T LE L MUXOUT SYNTH_+.V V 0 VP SYNTH_+.V 0pF;00 _ FR LMKGTN SYNTH_+.V V SV E 0pF;00 R0 P _VO _VO _VO ExP 0R;00;% _ S RF_OUT+ RF_OUT- RF_OUT- RF_OUT+ SYNTH_+.V R R-OPEN;00 0 SYNTH_+.V R SYNTH_+.V 0pF;00 R-OPEN;00 _ SYNTH_+.V L nh;00;00m;srf.ghz 0nH;00;00m;SRF0MHz;.R m 0pF;00 L SYNTH_+.V L nh;00;00m;srf.ghz 0nF;00 0nH;00;00m;SRF0MHz;.R m 0pF;00 L 0nF;00 RF_OUT/LO traces are 00 Ohm diff. impedance matched LOP LON R R;00;% Y NSZ0PX R M;00;% 0MHz_REF _ 0nF;00 -OPEN;00 SYNTH_ENLE 0MHz_REF_ R.K;00;% SYNTH_ENLE REF_ RSET PRF Frequency Synthesizer VTUNE POUT SW VREF TEMP 0 VOM Fast Lock Mode R 0R;00;%.nF;00 R 0R;00;% nf;00 0pF;00 Y 0MHz S0 F0PZ R R;00;% _ pf;00 _ rystal uses "laydown" footprint No traces under component pf;00 LK_+.V _ U0 N V NSZ0PX Y LK_+.V _ R R;00;% TP SYNTH_PLL_LOK {MUXOUT} _ PLL LOK testpoint dd SHIEL P for SHIEL FENE LK_REF TP LK REF testpoint TP_SMLL TP_SMLL R Label Testpoints 0R;00;% 0pF;00 0pF;00 0pF;00 R 0R;00;% K & Z Flower Hill Way Gaithersburg, M 0 US OM-0 / SYNTHESIZER Size ocument Number Rev Y00 ate: Monday, May, 0 Sheet of

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DOCUMENT NUMBER PAGE SECRET OUMENT NUMER PGE SERET / SERET OUMENT NUMER PGE / Spartan onfiguration SPI Flash Q S V W/VPP HOL VSS U MPVME R 0 R.K 0.U 9 IO_LP 0 IO_LN VREF_ G IO_L9P_ G IO_L9N_ F IO_L0P_ F IO_L0N_ IO_L9P_ IO_L9N_ 0