Mounted: No OSC5. positive frequency shift. C138 GND. 25MHz OSC1 C nF 50V X7R GND 50V X7R 0603 GND P3V3 P3V3 R78 R77. 10k. 10k 0.1W 0.

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1 Start up clock. onnected directly to the FPG. nf nf V nf PLL_OUT V nf OS +Vs OUT V V OS MHz GN_TXO_V V V V MHz OUT V V OS MHz OS +Vs OUT V Stable clock for low drift and low jitter. onnected to the FPG through an. It is also routed to the GTPs and FM. MHz OUT V Programmable clock _LN LIPPTXO_OUT_TO_FPG_P V nf V ontrol voltage is +. V to +.V. ± ppm min _LN OS pull range. Positive slope. Positive voltage for positive frequency shift. +Vs OUT V nf MHz OS LIPPTXO_OUT_TO_ V OUT PLL_OUT V V V pf.v ±ppm Surface Mount TXO Voltage ontrolled Oscillator (FPT- Serie) GN Local us lock L_RF_LK_M R R R LIPPTXO_OUT_TO_FPG_N R PLL_SLK PLL_SY_N PLL_IN PLL_SO PLL_LR_N PLL_L_N _LN SLK SY IN SO LR L V I VRFIN VRFOUT POR RUZ- Quad, -it with.v ppm/ On-hip Reference nf _LN V ouput range: V to.v PLL_OUT PLL_OUT GN_TXO_V _LN R V Tying POR to PLL_ powers up the to midscale (.V). Tied to it powers up to V. Mount only one of the R resistor. nf O_SIX SIX_S SIX_SL V O S SL V OS -MHz LK+ LK- SIX_LK_P SIX_LK_N -MHz.V ±ppm L ny-rate I Programmable XO Oscillator Si Serie Project/quipment ocument - PIe FM arrier locks uropean Organization for Nuclear Research H- Genève - Switzerland esigner P. lvarez / M. attin rawn by P. lvarez / M. attin heck.by egelec N. Lopez Last Mod. Modifiedy File clocks.schoc Print ate // :: --V- // // // Sheet of Size Rev *

2 S_RM_SWP_OVR S_F S_F S_SO S_SIO S_SLK S_IO_RST S_S_N S_OSK S_RTL S_RHOL S_ROVR S_PROFIL S_PROFIL S_PROFIL S_IO_UPT S_ S_ S_ S_ S_ S_ S_ S_ S_ S_ S_ S_ S_ S_ S_ S_ S_TXNL S_PLK V_ V_PV RM_SWP_OVR F F SO SIO SLK I/O_RST S OSK S_MSTR_RST RTL MSTR_RST RHOL ROVR PLL_LOOP_FILTR S_PLL_LOK PLL_LOK PROFIL PROFIL S_SY_IN_P PROFIL SY_IN+ S_SY_IN_N SY_IN- S_SY_OUT_P I/O_UPT SY_OUT+ S_SY_OUT_N SY_OUT- S_SY_SMP_RR SY_SMP_RR S_SY_LK SY_LK S_POWR_WN XT_PWR_WN TxNL PLK V_I/O (.V) V_I/O (.V) V (.V) V_I/O (.V) V (.V) V_I/O (.V) V (.V) V_I/O (.V) V (.V) V_I/O (.V) V (.V) V_I/O (.V) V (.V) V (.V) V (.V) V (.V) P() I SVZ _RST IOUT IOUT RFLK_OUT RF_LK RF_LK XTL_SL V (.V) V (.V) V (.V) V (.V) V (.V) V (.V) GSPS, -it,. V MOS irect igital Synthesizer PV S_OUT_N S_OUT_P S_RF_LK_P S_RF_LK_N R R V_PV R V R nf nf nf V PV L R@MHz uf PV uf L R@MHz uf uf S_RF_LK_P S_RF_LK_N V V V V V V V V R R R V_PV V S_RF_LK_P _S_RF_LK_N LVPL to LVPL termination taken from: -oupling etween ifferential LVPL, L, HSTL, and M. pplication Report S March. TexasInstruments. Figure Project/quipment ocument -O PIe FM arrier S uropean Organization for Nuclear Research H- Genève - Switzerland esigner P. lvarez / M. attin rawn by P. lvarez / M. attin heck.by egelec N. Lopez Last Mod. - File dds.schoc Print ate // :: --V- // // // Sheet of Size Rev -

3 High Pin ount Rows L High speed lines R R R LK_M_P LK_M_N PV_FM R R MV R k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k N: the L pairs must have a differential impedence of ohm (+/-%) and be routed with no skew between the P and the N lines. The skew between the various L pairs should be kept as low as possible (<ps). PV JJ L High speed lines R R R LK_M_P LK_M_N MV R R R j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j JI R R MV R R PV VJ f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f Low Pin ount Rows JF _PIe R R R VJ R e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e J M_IR GTLK_M_P GTLK_M_N b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b J P_M_P P_M_N P_M_P P_M_N P_M_P P_M_N P_M_P P_M_N P_M_P P_M_N P_M_P P_M_N P_M_P P_M_N P_M_P P_M_N a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a J L High speed lines VRF M PRSNT_M_L LK_M_P LK_M_N L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N VJ R h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h JH L High speed lines LK_M_P LK_M_N L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g g JG L High speed lines PG_M GTLK_M_P GTLK_M_N L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N L High speed lines P_M_P P_M_N P_M_P P_M_N TK_TO_FM L_P TI_TO_FM FM_SL L_N _PIe TO_FROM_FM FM_S _UX_FM h L_P g TMS_TO_FM d c h L_N g TRST_TO_FM d G c h g G d c h L_P g d c h L_N g d c PV_FM h g d c _PIe PV_FM h VJ g d c VJ _PIe h g d c _PIe V V uf uf R d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d J L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c J M M M Project/quipment ocument -O FM_SL FM_S R k M M M PIe FM arrier R FM onnector uropean Organization for Nuclear Research H- Genève - SwitzerL_Pd onnect only one of the three I master at a time. e careful, GN_S and GN_SL already have k ohm pull-up. k R R R R R R R R GN_SL GN_S GN_SL_GPIO GN_S_GPIO esigner P. lvarez / M. attin rawn by P. lvarez / M. attin heck.by egelec N. Lopez Last Mod. - File fmc_connector.schoc Print ate // :: --V- FPG_SL FPG_S FTG FTG FTG FTG FTG FTG // // // Sheet of Size Rev -

4 locking: GTPs and (as GTPs and ) form a UL GTP block that can share MGTs reference clocks. GTP NNOT SHR a reference clock with GTP. For more details see Xilinx user guide Spartan- FPG GTP Transceivers (ug.pdf). hapter : Shared Transceiver Features. Notice that using a GLK as a reference clock is allowed for testing but not recommended for operation. P_M_P P_M_N P_M_P P_M_N GTLK_M_P GTLK_M_N P_M_P P_M_N P_M_P P_M_N IH XSLXT-FGG MGTTXP_ MGTTXN_ MGTRXP_ MGTRXN_ MGTRFLKN_ MGTRFLKP_ MGTTXP_ MGTTXN_ MGTRXP_ MGTRXN_ MGTRFLKP_ MGTRFLKN_ FPG_PLL_RF_LK P FPG_PLL_RF_LK N FPG_PLL_RF_LK P FPG_PLL_RF_LK N SFPTX P SFPTX N SFPRX P SFPRX N _FPG_PLL_RF_LK P _FPG_PLL_RF_LK N P_M_P P_M_N P_M_P P_M_N _FPG_PLL_RF_LK P _FPG_PLL_RF_LK N IJ XSLXT-FGG MGTTXP_ F MGTTXN_ MGTRXP_ MGTRXN_ MGTRFLKP_ MGTRFLKN_ F F MGTTXP_ MGTTXN_ MGTRXP_ MGTRXN_ MGTRFLKP_ MGTRFLKN_ MGT_V_ MGTVPLL_ MGTVPLL_ MGTV_ MGTVTTTX_ MGTVTTRX_ MGT_V_ F MGTVPLL_ MGTVPLL_ MGTV_ MGTVTTTX_ MGTVTTRX_ FPG_PLL_RF_LK P FPG_PLL_RF_LK N P_M_P P_M_N P_M_P P_M_N GTLK_M_P GTLK_M_N P_M_P P_M_N P_M_P P_M_N _FPG_PLL_RF_LK P _FPG_PLL_RF_LK N alibration resistor traces must be equal in length and geometry. See Spartan- FPG GTP Transceivers (dvance Spec) UG. R MGT_V_ IG XSLXT-FGG MGTTXP_ MGTTXN_ MGTRXP_ MGTRXN_ MGTRFLKP_ MGTRFLKN_ MGTTXP_ MGTTXN_ MGTRXP_ MGTRXN_ MGTRFLKP_ MGTRFLKN_ MGTRRF_ MGTVTTRL_ MGTVPLL_ MGTVPLL_ MGTV_ MGTVTTTX_ MGTVTTRX_ FPG_PLL_RF_LK P FPG_PLL_RF_LK N FPG_PLL_RF_LK P FPG_PLL_RF_LK N ST_TX_P ST_TX_N ST_RX_P ST_RX_N _FPG_PLL_RF_LK P _FPG_PLL_RF_LK N ST_TX_P ST_TX_N ST_RX_P ST_RX_N _FPG_PLL_RF_LK P _FPG_PLL_RF_LK N alibration resistor traces must be equal in length and geometry. See Spartan- FPG GTP Transceivers (dvance Spec) UG. R MGT_V_ F F F F II XSLXT-FGG MGTTXP_ MGTTXN_ MGTRXP_ MGTRXN_ MGTRFLKP_ MGTRFLKN_ MGTTXP_ MGTTXN_ MGTRXP_ MGTRXN_ MGTRFLKP_ MGTRFLKN_ MGTRRF_ MGTVTTRL_ MGTVPLL_ MGTVPLL_ MGTV_ MGTVTTTX_ MGTVTTRX_ PV L R@MHz MGT_V_ uf PV L R@MHz MGT_V_ uf Power: GTPs power plane, and signal plane should be separated by a ground plane from any signal passing close. The capicitor bank recomended for decoupling is described in: Xilinx user guide Spartan- FPG GTP Transceivers (ug.pdf). hapter oard esign Guidelines. heck Table -: Recommended Minimum ecoupling for Spartan- FPG GTP_UL Tiles and Figure -: Stackup for GTP Power and Signal Layers. Project/quipment ocument -O PIe FM arrier GTPs uropean Organization for Nuclear Research H- Genève - Switzerland esigner P. lvarez / M. attin rawn by P. lvarez / M. attin heck.by egelec N. Lopez Last Mod. - File fpga_gtp.schoc Print ate // :: --V- // // // Sheet of Size Rev -

5 VO_ = VJ I XSLXT-FGG NK IO_LP_HSWPN_ IO_LN_VRF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_GLK_ IO_LN_GLK_ IO_LP_GLK_ IO_LN_GLK_ IO_LP_GLK_ IO_LN_GLK_ IO_LP_GLK_ IO_LN_GLK_ IO_LP_ IO_LN_VRF_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_ IO_LP_ IO_LN_VRF_ IO_LP_SP_ IO_LN_SP_ IO_LP_SP_ IO_LN_SP_ IO_LP_SP_ IO_LN_SP_ IO_LP_SP_ IO_LN_SP_ H G H G F F G F H G F H G F G F F J G H G K J J H F K H J H J J F G F F G F F H G H H G F VRF M L_P L_N L_P L_N L_P L_N L_P L_N VRF M L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N VRF M L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N L_P L_N VRF M L_P L_N L_P L_N L_P L_N L_P L_N VJ R k R R k R SPRI_XI_SWP Mount only one of the four options for HSWP. ) pull-up to VJ_FPG ) pull-up to ) pull-down to ) from GN (trough a R resistor) Test to find out the best option. Project/quipment ocument -O PIe FM arrier FPG FM IO ank uropean Organization for Nuclear Research H- Genève - Switzerland esigner P. lvarez / M. attin rawn by P. lvarez / M. attin // heck.by egelec N. Lopez / Last Mod. - // File fpga_io_bank fmc.schoc Sheet of Print ate // :: Size Rev - --V-

6 uropean Organization for Nuclear Research H- Genève - Switzerland FPG IO anks - * // :: fpga_io_bank_-.schoc Size File Rev Sheet of PIe FM arrier Project/quipment --V- P. lvarez / M. attin esigner P. lvarez / M. attin rawn by egelec N. Lopez heck.by // // -O Modifiedy Last Mod. ocument Print ate // PLL_S_N PLL_SY_N ROUT_THROUGH_LK_P ROUT_THROUGH_LK_N USR_RF P USR_RF N USR_RF_ LIPPTXO_OUT_TO_FPG_N S_ S_SO S_SY_LK MPS Y IO_LN_ IO_LN F ON_ F IO_LN_GLK_ F IO_LN_VRF_ IO_LN_ IO_LP IN_MISO_MISO_ IO_LP_ U IO_LP_ PROGRM F IO_LP_ Y IO_LP_ IO_LN_GLK_USRLK_ IO_LN_VRF_ IO_LP_ Y IO_LP_ IO_LN_ Y IO_LP_ W IO_LN_ IO_LP_ IO_LN_ V IO_LP_ Y IO_LP_ IO_LN W IO_LP W IO_LP_M_ IO_LN MISO_ W IO_LP MISO_ V IO_LP_ IO_LP_ W IO_LN_MOSI_SI MISO_ F IO_LN_MPMOSI_ IO_LP_MPLK_ Y IO_LN_M_MPMISO_ F IO_LP_LK_ IO_LP_GLK_ IO_LN_ IO_LN_ V IO_LP_ U IO_LN_ V IO_LN_ IO_LN_GLK_ F IO_LP_GLK IO_LN_ W IO_LP IO_LP_ V IO_LN_VRF_ Y IO_LN_VRF_ IO_LN_ IO_LN_ IO_LN_ IO_LP_ Y IO_LP_GLK_ IO_LN_GLK F IO_LP_GLK IO_LN_SO F IO_LP_INIT IO_LN NK IO_LP_ IO_LN_ IO_LP_ V IO_LP_ W IO_LN_RWR VRF_ IO_LP_ IO_LP IO_LN_ F IO_LN W IO_LP W IO_LP_ IO_LP_ IO_LN_ F IO_LP_ IO_LN_ W IO_LN F IO_LP IO_LN_ V IO_LP_ V IO_LN_VRF_ IO_LP_ Y IO_LN_ IO_LN_ Y IO_LP_ W SPRTN-, FPG, User I/Os, GTPs, -all G, ommercial Grade, Pb-Free I XSLXT-FGG PLLXT_SIO USRIO_P USRIO_N SPI_ SPI_Q SPI_LK FPG_INIT FPG_PROGRM FPG_ON OUT_V_MON IN_V_MON PL_LK_P PL_LK_N L_WR_RY NK IO_LP_ IO_LN_ U IO_LP_MUQS_ IO_LN_MLQSN_ V IO_LP_M_ R IO_LN_M_ R IO_LP_ M IO_LN_VRF_ IO_LP_ IO_LN_ IO_LP_ Y IO_LN_ Y IO_LP_ IO_LN_ IO_LP_ V IO_LN_ V IO_LP_ U IO_LP_ V IO_LN_VRF_ W IO_LP_ U IO_LN_ U IO_LP_ U IO_LN_VRF_ T IO_LP_MQ_ IO_LN_MQ_ IO_LP_MQ_ IO_LN_MQ_ IO_LN_MUQSN_ IO_LP_MQ_ IO_LN_MQ_ IO_LP_MQ_ IO_LN_MQ_ IO_LP_MQ_ Y IO_LN_MQ_ Y IO_LP_MQ_ W IO_LN_MQ_ W IO_LP_MLQS_ V IO_LP_MQ_ U IO_LN_MQ_ U IO_LP_GLK_MQ_ T IO_LN_GLK_MQ_ T IO_LP_GLK_TRY_MUM_ V IO_LN_GLK_MLM_ W IO_LP_GLK_MRSN_ R IO_LN_GLK_IRY_MSN_ R IO_LP_GLK_M_ R IO_LN_GLK_M_ R IO_LN_MOT_ T IO_LP_MLK_ U IO_LN_MLKN_ T IO_LP_M_ R IO_LN_M_ T IO_LP_M_ P IO_LN_M_ P IO_LP_M_ N IO_LN_M_ P IO_LP_MW_ P IO_LP_M_ N IO_LN_M_ N IO_LP_M_ R IO_LN_M_ R IO_LP_MK_ R IO_LN_M_ P IO_LP_MRST_ N IO_LN_M_ N IO_LP_M_ P IO_LN_M_ N IO_LN_VRF_ M I XSLXT-FGG SFP_MO_F SFP_RT_SLT M M QR_Q_N QR_Q_P VRF_QRII VRF_QRII VRF_QRII VRF_QRII FPG_S S_OUT_P S_OUT_N PLL_LR_N_PV THRMO_I _S_OUT_P _S_OUT_N SIX_S SIX_SL_PV R R PLL_OUT_TO_FPG_GLK_P PLL_OUT_TO_FPG_GLK_N PLLXT_RFMON SIO_V_MON PG_M QR_K_P QR_K_N NK IO_LP_ M IO_LN_MQ_ J IO_LP_MUM_ J IO_LN_M_ L IO_LP_MK_ K IO_LP_M_ K IO_LN_M_ K IO_LP_ H IO_LN_VRF_ H IO_LN_VRF_ N IO_LP_MQ_ N IO_LN_MQ_ N IO_LP_MQ_ M IO_LN_MQ_ M IO_LP_MUQS_ L IO_LN_MUQSN_ L IO_LP_MQ_ K IO_LN_MQ_ K IO_LP_MQ_ J IO_LP_MQ_ H IO_LN_MQ_ H IO_LP_MQ_ G IO_LN_MQ_ G IO_LP_MLQS_ F IO_LN_MLQSN_ F IO_LP_MQ_ IO_LN_MQ_ IO_LP_MQ_ IO_LN_MQ_ IO_LN_MLM_ J IO_LP_MRSN_ L IO_LN_MSN_ L IO_LP_M_ L IO_LN_M_ L IO_LP_M_ M IO_LN_MOT_ M IO_LP_MLK_ K IO_LN_MLKN_ J IO_LP_M_ L IO_LP_M_ IO_LN_M_ IO_LP_M_ L IO_LN_M_ K IO_LP_MW_ G IO_LN_M_ G IO_LP_M_ J IO_LN_M_ J IO_LP_M_ IO_LN_M_ IO_LN_M_ K IO_LP_MRST_ IO_LN_M_ I XSLXT-FGG VRF_QRII VRF_QRII PRSNT_M_L IO_LP_ N IO_LN M_ N IO_LP_M_ T IO_LN MQ_ T IO_LP_MUQS_ IO_LN_ IO_LN_VRF_ N IO_LP M_ L IO_LN M_ L IO_LP MRST_ N IO_LN M_ N IO_LP MK_ N IO_LN M_ N IO_LP M_ P IO_LN M_ P IO_LP M_ N IO_LP MW_ R IO_LN M_ R IO_LP M_ P IO_LN M_ P IO_LP M_ R IO_LN M_ R IO_LP M_ P IO_LN M_ P IO_LP MLK_ R IO_LN MLKN_ R IO_LN_MOT_ T IO_LP_GLK_M_ U IO_LN_GLK_M_ U IO_LP_GLK_IRY_MRSN_ R IO_LN_GLK_MSN_ R IO_LP_GLK_MUM_ V IO_LN_GLK_TRY_MLM_ W IO_LP_GLK_MQ_ U IO_LN_GLK_MQ_ U IO_LP MQ_ T IO_LP MLQS_ V IO_LN MLQSN_ V IO_LP_FS MQ_ W IO_LN_FO MQ_ W IO_LP_FW MQ_ IO_LN_L_MQ_ IO_LP_H_MQ_ IO_LN_MQ_ IO_LP_MQ_ IO_LN_MQ_ IO_LN_MUQSN_ IO_LP_MQ_ Y IO_LN_MQ_ Y IO_LP_MQ_ IO_LN_MQ_ IO_LP_ U IO_LN_VRF_ U IO_LP_ T IO_LN_ T IO_LP_ IO_LP_ U IO_LN_ U IO_LP_ V IO_LN_VRF_ V IO_LP_WK_ IO_LN_OUT_USY_ NK I XSLXT-FGG PLLXT_SLK_PV PLLXT_S_N_PV PLL_SLK_PV S_S_N_PV S_TXNL_PV S_SY_OUT_P S_SY_OUT_N SLK_V_MON_PV SVR_V_MON_PV QR_ QR_ QR_ QR_ P_WR_RY PLLXT_OUT_TO_FPG_P PLLXT_OUT_TO_FPG_N _S_OUT_P _S_OUT_N USRLK_IN_TO_FPG_N USRLK_IN_TO_FPG_P PLLXT_SO_PV PLL_SO_PV PLLXT_STTUS_PV PLLXT_PLL_LOK_PV PLL_PLL_LOK_PV PLL_STTUS_PV TO_FROM_FM_PV VRF_QRII VRF_QRII VRF_QRII TI_TO_FM_PV TK_TO_FM_PV TMS_TO_FM_PV S_MSTR_RST_PV S_SLK_PV PLL_IN_PV PLL_SLK_PV PLL_SO_PV PLL_SY_N_PV PLL_L_N_PV _VJ_POWR_GOO S G T SH S G T SH L_TOP L_OT R R Green OT L Red TOP L_ILIGHT_-F L VO_ =.V VO_ =.V VO_ =.V VO_ =.V M_IR O_SIX SIX_LK_P SIX_LK_N LLK_N LLK_P PL_T PL_T PL_T PL_T PL_T PL_T PL_T PL_T PL_T PL_T PL_VLI PL_T PL_T PL_T PL_T LP_T PL_T PL_FRM PL_T TX_RROR LP_T LP_T PLL_RFMON_PV PLL_P_N_PV LP_T LP_FRM LP_T LP_ LP_T GN_FPG_RST LP_VLI LP_T LP_T LP_T S_PLL_LOK_PV LP_T LP_T LP_T V_RY P_R RY LP_T LP_T P_R RY LP_T LP_T LP_RY P_WR_RQ P_WR_RQ V_RY L_WR_RY RX_RROR PL_RY QR_Q QR_Q QR_Q QR_Q QR_Q QR_Q QR_Q QR_Q QR_Q QR_Q QR_Q QR_Q QR_Q QR_Q QR_Q QR_Q QR_Q QR_Q QR_ QR_ QR_ QR_ QR_OFF_N QR_ QR_WS_N QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_WPS_N QR_ QR_ QR_ QR_RPS_N QR_ QR_WS_N QR_ QR_ QR_ P_WR_RY TO_FROM_FM_PV QR_ S_ S_PLK S_ S_ S_ GN_GPIO FPG_SL S_F S_ S_ PLLXT_SY_N NL_VJ S_RHOL S_IO_UPT S_ROVR S_SIO S_OSK S_ S_ S_ S_ S_ S_SY_SMP_RR S_V_MON S_PROFIL S_F S_ S_RM_SWP_OVR SPI_S GN_GPIO SFP_MO_F S_ S_ S_ S_SY_IN_N S_SY_IN_P S_PROFIL S_IO_RST S_RTL S_PROFIL SFP_LOS SFP_MO_F PLL_SIO QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ LP_LK_P LP_LK_N LK_M_P LK_M_N USRIO_N USRIO_P LK_M_N LK_M_P LIPPTXO_OUT_TO_FPG_P Place Ohm resistor close to IO. It should be treated as differential line. Impedance respect to should be Ohm. Ohm differential termination on FPG IO. LIPPTXO_OUT_TO_FPG_P carries a clipped sinewave. LIPPTXO_OUT_TO_FPG_N is the midpoint at.v. The corresponding FPG IO can be configured as an L input for optimal performance.

7 R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_K_P R_K_N R_K R_RST_N R_RS_N R_S_N R_W_N R_OT R_ R_ R_ PV V R Termination resistors must be placed close to MTJMH. R R R R R R R R R R R R R R R R R R R R.W R k R k R k VTT_R Meg x x anks R SRM, +.V Supply I N Q P F Q P F Q N F Q P H Q P H Q R G Q R H Q T Q R Q L /P Q R Q N / Q T Q R Q J K Q K K K K T RST UM J RS LM K S UQS R_S_N L F S LQS L W UQS R_ZQ L G ZQ LQS K OT J M J N L M L M VRF_R H T VRFQ M VRF PV PV V V VQ V VQ G V VQ K V VQ K V VQ N V VQ N F V VQ R H V VQ R H V VQ R G J J M M P P T T Q Q Q Q Q Q Q Q Q MTJMH- F G G R R R R R R R R R R R R R R R R R R R R R VTT_R R VTT_R Termination resistors must be placed close to FPG. R_ VTT_R R R_Q R_Q R_Q R_Q R_Q R_Q R_Q R_Q R_Q R_Q R_Q R_Q R_Q R_Q R_Q R_Q R_UM R_LM R_UQS_P R_LQS_P R_UQS_N R_LQS_N R_ is wired for compatibility with higher memory capacity. V PV uf R R Project/quipment ocument -O nf V VO_ =.V IF XSLXT-FGG NK VLOIN RFIN N P PIe FM arrier I PGOO VO VOSNS RFOUT P TPSRT IO_LP IO_LN VRF_ IO_LP_M_ IO_LN_M_ IO_LP_MRST_ IO_LN_M_ IO_LP_MK_ IO_LN_M_ IO_LP_M_ IO_LN_M_ IO_LP_M_ IO_LN_M_ IO_LP_MW_ IO_LN_M_ IO_LP_M_ IO_LN_M_ IO_LP_M_ IO_LN_M_ IO_LP_M_ IO_LN_M_ IO_LP_MLK_ IO_LN_MLKN_ IO_LP_M_ IO_LN_MOT_ IO_LP_M_ IO_LN_M_ IO_LP_MRSN_ IO_LN_MSN_ IO_LP_MUM_ IO_LN_MLM_ IO_LP_MQ_ IO_LN_MQ_ IO_LP_MQ_ IO_LN_MQ_ IO_LP_MLQS_ IO_LN_MLQSN_ IO_LP_MQ_ IO_LN_MQ_ IO_LP_MQ_ IO_LN_MQ_ IO_LP_MQ_ IO_LN_MQ_ IO_LP_MQ_ IO_LN_MQ_ IO_LP_MUQS_ IO_LN_MUQSN_ IO_LP_MQ_ IO_LN_MQ_ IO_LP_MQ_ IO_LN_MQ_ IO_LP_ IO_LN_VRF_ IO_LP_ IO_LN_ R + IO ank uropean Organization for Nuclear Research H- Genève - Switzerland VTT_R_GOO.V VRF_R.V V R R.W H G R_ R_ K R_RST_N K R_ R_K R_ H R_ H R_ F R_ G R_ J R_W_N J R_ R_ R_ L R_ K R_ R_ R_ R_K_P R_K_N K R_ K R_OT M R_ M R_ F R_RS_N G R_S_N J J R_UM R_LM R_Q R_Q R_Q R_Q F R_LQS_P F R_LQS_N H R_Q H R_Q G R_Q G R_Q K R_Q K R_Q J R_Q J R_Q M R_UQS_P M R_UQS_N L R_Q L R_Q N R_Q N R_Q M M L L_OT L L_TOP esigner P. lvarez / M. attin rawn by P. lvarez / M. attin // heck.by egelec N. Lopez // Last Mod. - // File fpga_io_bank ddr.schoc Sheet of Print ate // :: Size Rev - --V- uf VTT_R VRF_R VRF_R R.W uf

8 uropean Organization for Nuclear Research H- Genève - Switzerland FPG - // :: fpga_power.schoc Size File Rev Sheet of PIe FM arrier Project/quipment --V- P. lvarez / M. attin esigner P. lvarez / M. attin rawn by egelec N. Lopez heck.by // // Power -O - Last Mod. ocument Print ate // VO_ VO_ VO_ VO_ W VO_ G VO_ J VO_ K VO_ M VO_ M VO_ VO_ VO_ VO_ F VO_ F VO_ G VO_ H VO_ H VO_ J VO_ VO_ P VO_ P VO_ T VO_ W VO_ W VO_ Y VO_ VO_ VO_ VO_ VO_ VO_ W VO_ W VO_ Y VO_ Y VO_ VO_ P VO_ P VO_ T VO_ T VO_ W VO_ Y VO_ VO_ F VO_ H VO_ J VO_ K VO_ M VO_ M VO_ VO_ H IM XSLXT-FGG VUX VUX K VUX U VINT M VINT P VINT T VINT U VUX VUX VUX VUX VUX VUX VUX VUX G VUX J VUX J VUX K VUX L VUX L VUX L VUX M VUX N VUX R VUX U VUX U VUX U VUX V VUX V VUX W VINT K VINT K VINT L VINT L VINT L VINT M VINT M VINT M VINT M VINT M VINT N VINT N VINT N VINT N VINT P VINT P VINT P VINT R VINT R VINT R VINT R VINT R VINT R VINT R VINT T VINT T VINT T VINT U IN XSLXT-FGG PV VJ PV PV PV PV uf uf V uf PV uf uf uf V uf PV PV uf uf V uf VUX decoupling capacitors VINT decoupling capacitors K P T Y F F F F F F F F G H H J J K K L L L L M M N N P P P P P T T T T T T U U V V V Y Y Y Y IO XSLXT-FGG

9 J Mount the R resistor to bypass the SNST chip. ONN_TMS R FPG_TMS ONN_TK R FPG_TK ONN_TO R FPG_TO ONN_TI R FPG_TI MOLX_-.mm (.") Pitch Milli-Grid Header, Right ngle, Shrouded, enter Polarization Slot, Locking Window, ircuits R R SW SW_OMRON_S--H M R R M R ON = select JTG connector OFF = select GN GPIOs SLJTGIN R SNST configuration: - Stitcher mode - Select FPG only at power-up - Full transparent mode R ONN_TO ONN_TK ONN_TMS ONN_TI Place R resistor to disable full transparent mode (enable normal mode). FPG configuration modes: ) Master SPI The FPG take its configuration from the SPI flash memory. M=high, M=low ) Slave serial The FPG is configured via the GN by the driver at startup. M=high, M=high SLJTGIN G H K J J J H G K K F F F G H G J F K J F H H K K G H I O TI Y Y TMS TO TK TK TRST TMS TO TRST TRIST Y S Y S S S S TI S TO S TK S TMS TRST MSK Y Y TI TRIST TRIST TI RST TO TK LSPSL TMS LSPSL TRST LSPSL TRIST LSPSL LSPSL TI LSPSL TO LSPSL TK TMS MPSL/ TRST S/S TRIST TRNS TI TLR_TRST TO TLR_TRST TK TMS V TRST V V TI V TO V TK V TMS V TRST V V TI V TO TK TMS TRST SNSTSM/NOP F K F G J J H J H K K F H G F G H G F G J J K R R GN_GPIO_TI GN_GPIO_TMS GN_GPIO_TK GN_GPIO_TO FPG_TO FPG_TI FPG_TK FPG_TMS QR_TO QR_TI QR_TK QR_TMS GN_TO GN_TI GN_TK GN_TMS Remove the R resistor when bypassing the SNST. FPG_TI FPG_TO FPG_TK FPG_TMS G F Y IK XSLXT-FGG TI TO TK TMS SUSPN IL XSLXT-FGG W VFS V RFUS V VTT SPRI_xx are serial configuration signals from the GN. SPRI_TOUT R k R SPI_Q MP-VMFG I SPI_ Q SPI_LK SPI_S S V W/Vpp SPRI_LK R HOL MP-VMFG Mbit (Multilevel), Low-Voltage, Serial Flash Memory With -MHz SPI us Interface SPI_LK trace impedance must be ohm. R R R R k SPRI_STTUS R SPRI_ONFIG R SPRI_ON R R k R k FPG_INIT FPG_PROGRM FPG_ON nf V Project/quipment ocument -O PIe FM arrier JTG hain + FPG Flash uropean Organization for Nuclear Research H- Genève - Switzerland esigner P. lvarez / M. attin rawn by P. lvarez / M. attin heck.by egelec N. Lopez Last Mod. - File jtga_chain.schoc Print ate // :: --V- // // // Sheet of Size Rev -

10 uropean Organization for Nuclear Research H- Genève - Switzerland Level dapter V-V * // :: level_adapter_v_v.schoc Size File Rev Sheet of PIe FM arrier Project/quipment --V- P. lvarez / M. attin esigner P. lvarez / M. attin rawn by egelec N. Lopez heck.by // // -O Modifiedy Last Mod. ocument Print ate // PLLXT_SO PLL_SO PLLXT_STTUS PLLXT_PLL_LOK PLL_PLL_LOK PLL_STTUS TI_TO_FM TK_TO_FM TO_FROM_FM TMS_TO_FM V IR O V V I SNLVTPW V IR O V V I SNLVTPW TI_TO_FM_PV TK_TO_FM_PV TMS_TO_FM_PV PV PLLXT_SO_PV PLL_SO_PV PLLXT_STTUS_PV PLLXT_PLL_LOK_PV PLL_PLL_LOK_PV PLL_STTUS_PV TO_FROM_FM_PV PV V IR O V V -it ual-supply us Transceiver With onfigurable Voltage Translation and -State Outputs I SNLVTPW PV PLLXT_S_N_PV PLLXT_S_N S_PLL_LOK S_PLL_LOK_PV PLL_IN PLL_SLK PLL_LR_N PLL_SO PLL_SY_N PLL_L_N PV V IR O V V I SNLVTPW PLL_IN_PV PLL_SLK_PV PLL_LR_N_PV PLL_SO_PV PLL_SY_N_PV PLL_L_N_PV PLL_RFMON_PV PLL_RFMON SIX_SL_PV PV PV PV PV R R S_MSTR_RST_PV S_MSTR_RST S_SLK S_SLK_PV PLLXT_SLK_PV PLL_SLK_PV S_S_N_PV S_TXNL_PV PV V IR O V V I SNLVTPW PV R S_TXNL S_S_N PLLXT_SLK PLL_SLK SLK_V_MON_PV SLK_V_MON SLKR_V_MON SLKIO_V_MON SIX_SL SVR_V_MON_PV SVR_V_MON PLL_P_N_PV PLL_P_N PLLXT_P_N PLL_RF_SL S_POWR_WN MV_NL SFP_TX_ISL P_VR_ P_VR_ P_VR_ MV_NL GP GP GP GP V S SK SI SO RST INT INT GP GP GP GP GP GP GP GP GP GP GP GP P -bit I/O Port xpander With Serial Interface I MPS-/ML P_VR_ P_VR_ OUT_V_MON IN_V_MON SLKIO_V_MON SIO_V_MON TRST_TO_FM PLL_RST_N PLLXT_RST_N R MV_NL R R R R R R R P_VR_ P_VR_ P_VR_ P_VR_ P_VR_ R R R R R R R R R R R R SFP_TX_FULT

11 VTT_QRII PR_PV_PIe PR PIe PRST_N _PLKIN_P _PLKIN_N _PT_P _PT_N _PT_P _PT_N _PT_P _PT_N _PT_P _PT_N GN_S GN_SL SPRI_LK SPRI_TOUT SPRI_ONFIG SPRI_ON SPRI_XI_SWP SPRI_STTUS _GN R k R onnect ununsed GPIO to vias, in case we need to hack the P. GN_GPIO GN_GPIO R GN_SL_GPIO GN_S_GPIO GN_GPIO_TI GN_GPIO_TO GN_GPIO_TMS GN_GPIO_TK a a a a a a a a a a a RFLK+ RFLK- PRp PRn RSV PRp PRn PRp PRn PRp PRn RSV a a a a a a a a a a a a a a a a a a a a a k II GN GPIO GPIO GPIO GPIO F GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO PRSNT# +V +V TK TI TO TMS +.V +.V PRST# R IG GN SPRI_LK SPRI_TOUT SPRI_ONFIG SPRI_ON SPRI_XI_SWP SPRI_STTUS R J PI xpress x _GN +V +V +V SMLK SMT +.V TRST#.Vaux WK# RSV PTp PTn PRSNT# PTp PTn PTp PTn PTp PTn RSV PRSNT# b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b I S SL WP P V F-I/M PR_PV_PIe PR PIe IJ GN G G G G G G G G PR_P PR_N R PR_P PR_N PR_P PR_N PR_P PR_N Mount the R jumper for lane option. PLL_TST_OUT GN_TI GN_TMS GN_TK GN_TO _GN R R R R R R R _PT_N _PT_P _PT_N _PT_P _PT_N _PT_P _PT_N _PT_P _PLKIN_N _PLKIN_P F F R ccording to PIe specifications, coupling capacitors must be comprise between nf and nf. I GN TI TMS TK TRST TO SN_N TST_N Mount only one resistor at a time. For PROM boot up option, the pull-up must be mounted. LLK_MO LLK_MO LLK_MO LLK_MO V PT_N PT_P PLKIN_N PLKIN_P _GN R R PT_N PT_P PT_N PT_P PT_N PT_P LLK_P LLK_N PT_N PT_P PT_N PT_N PT_P PT_N PT_P PT_P PR_P PR_N PR_P PR_N PR_N PR_P PR_N PR_P PLKIN_N PLKIN_P GN_SL GN_S R R.W L_RF_LK_M M N F L P H J T G K R H G PR swapped to match pair length PT swapped to match pair length k PRST_N R GN_FPG_RST R k I GN PTn PTn PTn PTn PTp PTp PTp PTp PRn PRn PRn PRn PRp PRp PRp PRp LLK_MO LLK_MO LLK_MO LLK_MO PLKINn PLKINp IH GN SLK ST PROM_N T_LLK_P T_LLK_N IF GN RSTIN RSTOUT P RSTOUT k P R K L M M I GN LLK LLKn L_RF_LK_MI L_RF_LK_MO LLK_MO LLK_MO LLK_MO LLK_MO R VTT_QRII Termination resistors must be placed close to FPG. V PL_T PL_T PL_T PL_T PL_T PL_T PL_T PL_T PL_T PL_T PL_T PL_T PL_T PL_T PL_T PL_T PL_FRM PL_VLI PL_LK_P PL_LK_N P_WR_RQ P_WR_RQ P_WR_RY P_WR_RY V_RY V_RY PL_RY RX_RROR R R R R R R R R R R R R R R R R R R R R R R R R LP_T LP_T LP_T LP_T LP_T LP_T LP_T LP_T LP_T LP_T LP_T LP_T LP_T LP_T LP_T LP_T LP_FRM LP_VLI LP_ LP_LK_P LP_LK_N L_WR_RY L_WR_RY P_R RY P_R RY LP_RY TX_RROR VTT_QRII Termination resistors must be placed close to FPG. Project/quipment ocument -O VTT_QRII Termination resistors must be placed close to GN. R R R R R R PIe FM arrier R R PIe onnector + GN uropean Organization for Nuclear Research H- Genève - Switzerland.W I GN R P R PL_T R PL_T R R R PL_T R PL_T R R R PL_T R PL_T R R R PL_T R PL_T R T R PL_T T PL_T R T R PL_T T PL_T R T R PL_T T PL_T R T R PL_T T PL_T R R R PL_FRM P PL_VLI T_PL_LK_P P PL_LKp T_PL_LK_N R PL_LKn R R R R P N N N R P P P N R R R R R R R R R R R R R R R R R R R R R R R R R R Serial termination resistors must be placed close to GN. R R R R VTT_QRII P_WR_RQ P_WR_RQ P_WR_RY P_WR_RY V_RY V_RY PL_RY RX_RROR I GN LP_T LP_T LP_T F LP_T J LP_T K LP_T L LP_T N LP_T LP_T LP_T LP_T F LP_T J LP_T L LP_T M LP_T N LP_T H LP_FRM H LP_VLI G LP_ G LP_LKp G LP_LKn K L_WR_RY J L_WR_RY M P_R RY L P_R RY R F LP_RY R N TX_RROR.W Serial termination resistors must be placed close to GN. esigner P. lvarez / M. attin rawn by P. lvarez / M. attin heck.by egelec N. Lopez Last Mod. Modifiedy File pcie.schoc Print ate // :: --V- // // // Sheet of Size Rev *

12 PV uf uf PV PV R uf V uf uf uf R V V V L R@MHz V V V PV VTT_PIe V R.W V uf V uf V V VTT_PIe VRF_QRII PV PV T R N N M L K J G F N T M F R K F K T T P P P N N M M M L L L L K J H H G F F F M M L L J J H H F F x Lane PI xpress to Local ridge PLL_ PLL_V VTT_ VTT_ VRF VW VW VP VP V V V V V V V V V V V V V V V V V V V V V V V V V V V V VO VO VO VO VO VO VO VO VO VO VO VO PI_V PI_V _PI _PI _PI _PI _PI _PI _PI _PI _PI _PI _PI _PI _PI _PI _PI _PI V_PI V_PI V_PI V_PI V_PI V_PI VUX GN IK T R R P N M M M L L L K K K K K K K J J J J J J H H H H H H G G G G G G G J H T T P N M L K J H G F R P N G PI_V PV V GN and QRII share the same VTT supply!!! We keep two different drivers just in case one is not able to supply enough current, but normally only one should be mounted. R R k uf PV PV L R@MHz V R R PI_V nf V uf V I PGOO VLOIN VO RFIN VOSNS N P RFOUT P TPSRT PV L R@MHz V VTT_QRII.V VRF_QRII.V uf uf V PV R V VRF_QRII V V Project/quipment ocument -O PIe FM arrier GN Power uropean Organization for Nuclear Research H- Genève - Switzerland esigner P. lvarez / M. attin rawn by P. lvarez / M. attin heck.by egelec N. Lopez Last Mod. Modifiedy File pcie_power.schoc Print ate // :: --V- // // // Sheet of Size Rev *

13 Place Ohm bias resistors close to PLL_P pf pf R ROUT_THROUGH_LK_P ROUT_THROUGH_LK_N R PLL_YPSS R PLL_LF pf V NP.k R R k PLL_PLL_LOK PLL_STTUS PLL_RFMON PLL_RF_SL PLL_LF PLL_P PLL_YPSS USR_RF_ LIPPTXO_OUT_TO ROUT_THROUGH_LK_P.W _ROUT_THROUGH_LK_N PLL_P_N PLL_SY_N PLL_RST_N V _LN PLL_SLK PLL_SIO PLL_SO PLL_S_N I L STTUS RFMON RF_SL PRST RST LF P YPSS RFIN(RF) RFIN(RF) LK LK P SY RST SLK SIO SO S P() OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT(OUT) OUT(OUT) OUT(OUT) OUT(OUT) OUT(OUT) OUT(OUT) OUT(OUT) OUT(OUT) VP _LVPL _LVPL _LVPL -PZ.W _LN _LN R R R R _S_RF_LK_P _S_RF_LK_N PLL_OUT_TO_FPG_GLK_P PLL_OUT_TO_FPG_GLK_N FPG_PLL_RF_LK P FPG_PLL_RF_LK N LK_M_P LK_M_N FPG_PLL_RF_LK P FPG_PLL_RF_LK N FPG_PLL_RF_LK P FPG_PLL_RF_LK N -Output lock Generator with Integrated. GHz VO _LN V Project/quipment ocument -O PIe FM arrier PLL MHz uropean Organization for Nuclear Research H- Genève - Switzerland esigner P. lvarez / M. attin rawn by P. lvarez / M. attin heck.by egelec N. Lopez Last Mod. Modifiedy File pll_.schoc Print ate // :: --V- // // // Sheet of Size Rev *

14 pf pf USR_RF P USR_RF N USRLK_IN_TO P USRLK_IN_TO N R PLLXT_P R PLLXT_YPSS R R pf V NP.W.W PLLXT_LF V V R.k R k _USR_RF P _USR_RF N PLLXT_PLL_LOK PLLXT_STTUS PLLXT_RFMON PLLXT_PRST PLLXT_RST PLLXT_LF PLLXT_P PLLXT_YPSS _USRLK_IN_TO P _USRLK_IN_TO N PLLXT_P_N PLLXT_SY_N PLLXT_RST_N PLLXT_SLK PLLXT_SIO PLLXT_SO PLLXT_S_N _LN L STTUS RFMON RF_SL PRST RST LF P YPSS RFIN(RF) RFIN(RF) LK LK P SY RST SLK SIO SO S P() I OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT(OUT) OUT(OUT) OUT(OUT) OUT(OUT) OUT(OUT) OUT(OUT) OUT(OUT) OUT(OUT) VP _LVPL _LVPL _LVPL -PZ -Output lock Generator with Integrated. GHz VO.W R PLLXT_OUT_TO_FPG_P PLLXT_OUT_TO_FPG_N LK_M_P LK_M_N USRLK_OUT_P USRLK_OUT_N _LN _LN R R R FPG_PLL_RF_LK P FPG_PLL_RF_LK N FPG_PLL_RF_LK P FPG_PLL_RF_LK N _LN V Project/quipment ocument -O PIe FM arrier xternal PLL uropean Organization for Nuclear Research H- Genève - Switzerland esigner P. lvarez / M. attin rawn by P. lvarez / M. attin heck.by egelec N. Lopez Last Mod. Modifiedy File pll_ext.schoc Print ate // :: --V- // // // Sheet of Size Rev *

15 PV V PV V I IN PG IN IN IN OUT N OUT IS OUT SS OUT F P TPSRGWT R R R R k uf _LN uf PV_PIe R R k PV_PIe_SNS _PIe R R _FM_SNS VJ R R VJ_SNS Internal.V Vref. nalog input range : to Vref PV VJ_SNS UR_SNS_VJ UR_SNS_PV _FM_SNS UR_SNS FM PV_PIe_SNS UR_SNS_PV_PIe I IN SLK IN OUT IN IN IN S IN IN IN IN RF V SLK_V_MON OUT_V_MON IN_V_MON S_V_MON V R. V to. V, Micro Power, -hannel, ksps, -it _LN _PIe PV PV_FM PV nf V PV V I IN PG IN IN IN OUT N OUT IS OUT SS OUT F P TPSRGWT R R k R R uf PV uf PR PIe R R I IN+ OUT IN- PR OUT UF IN V+ INI uf uf _PIe UR_SNS FM V nf R V PV V I IN PG IN IN IN OUT N OUT IS OUT SS OUT F P TPSRGWT R R R R PV uf uf PV_PIe L PV_PIe_FILTR.uH PV_PIe F.-V PV_FM L.uH + uf Project/quipment ocument -O PIe FM arrier Linear Power Supplies uropean Organization for Nuclear Research H- Genève - Switzerland esigner P. lvarez / M. attin rawn by P. lvarez / M. attin // heck.by egelec N. Lopez // Last Mod. - // File power_supply_linear.schoc Print ate // :: Sheet of Size Rev - --V-

16 PV_PIe_FILTR + uf MV_LMT_NL For details on Vin vs Iout refer to page, of fa.pdf The configuration is copied from page of the same document. H J J J K K K L L L L H L F F IS RUN/SS SHR SY I UX PGOO J RT LTMV#PF G J K G L K K J J H G G G G G F F F F F R k R R k R PR_MV R PV_PIe_FILTR uf MV_LMT_NL + H J J J K K K L L L L H L F F I IS UX RUN/SS SHR SY PGOO J RT LTMV#PF G J K G L K K J J H G G G G G F F F F F R k R k R PR_MV k PV_PIe_FILTR + uf MV_LMT_NL H J J J K K K L L L L H L F F I IS UX RUN/SS SHR SY PGOO J RT LTMV#PF G J K G L K K J J H G G G G G F F F F F R k R k R PR_MV R k MV MV MV.V-V To.V-V, Iout Step own umodule onverter uf V uf V + uf PV_PIe_FILTR PV_PIe_FILTR PV_PIe_FILTR The minimum The minimum The minimum I I I current to switch current to switch current to switch o not mount if solid state o not mount if solid state o not mount if solid state ON is m. ON is m. ON is m. relay is mounted. relay is mounted. relay is mounted. MV_LMT_NL MV_LMT_NL MV_LMT_NL T T T SH SH SSR-- SSR-- SSR-- MV_NL G y default, the MV_NL G y default, the MV_NL G y default, the S regulator is disabled. S regulator is disabled. S regulator is disabled. SH SH SH MV MV MV Form, Solid State Relay (Photo MOSFT), V/./ Ohm R R TURNOFF IRUIT R R R R TURNOFF IRUIT R R R R TURNOFF IRUIT R R Project/quipment ocument -O PIe FM arrier Negative Power Supplies uropean Organization for Nuclear Research H- Genève - Switzerland esigner P. lvarez / M. attin rawn by P. lvarez / M. attin // heck.by egelec N. Lopez // Last Mod. - // File power_supply_negative.schoc Print ate // :: Sheet of Size Rev - --V-

17 The two ceramic capacitors are added to provide enough current to the ltm (up to each). PV_PIe_FILTR J J J + J J J K K K K K K K K L L L L L L L L L L M M M PV_PIe_FILTR M M k M M M M M M PV_PIe_FILTR M J J uf PV_PIe R PV_PV_POWR_GOO H PR_PV_PIe R R R R R_R W_PPM FRQ_MO SW_PV SW_PV H J F J H H H H J J RUN RUN PGOO MO/PLLIN FRQ/PLLFLTR INTV XTV SW SW S S S S I LTMV#PF VF TK OMP OMP TK VF K K L L K K F F F F F F F F F F F G G G G G G G G G G G G H H H H H H V pf.v-.v To.V-V, Iout ual - umodule Regulator PR OUT UF IN V+ INI UR_SNS_PV_PIe V nf pf PV R R k uf uf R uf uf PV V uf R uf uf R R nf uf R R PV Ohm Ohm PV K K pf on examples, but changed to pf to use same ca as in PLL filter PR OUT UF IN V+ PV_PIe_FILTR INI + uf PV R V UR_SNS_PV VJ enable can be fixed by mounting R and unmounting R. J J J J J J K K K K K K K K L L L L L L L L L L M PV_PIe_FILTR M M k M M M M M M M M M J R NL_VJ J _VJ_POWR_GOO H R R R FRQ_MO R PV SW_ SW_VJ H J F J H H If XTV is connected to an external +V, the internal V linear regulator is switched off IN gain is V/V, the output will give mv/. and replaced by XTV. _PIe OS R FRQ_MO k V+ OUT FRQ_MO OUT V R k ST MO R LTHS-#TRPF khz to MHz Resistor Set SOT- Oscillator with Spread Spectrum Modulation Fout = MHz*/Rset = khz Spread spectrum frequency modulation turned OFF if the resistor between OUT and MO is mounted. The resistor between MO and ground should be mounted if spread spectrum is desired. FRQ_MO and FRQ_MO are in quadrature ( and ). H H J J RUN RUN PGOO MO/PLLIN FRQ/PLLFLTR INTV XTV SW SW S S S S I LTMV#PF VF TK OMP OMP TK VF K K L F F F F F F F F F F F G G G G G G G G G G G G H H H H H H Project/quipment ocument -O pf V L K K VJ_FK pf R k uf PIe FM arrier VJ + FM + PV + PV uropean Organization for Nuclear Research H- Genève - Switzerland SVR_V_MON SLKR_V_MON IN_V_MON uf uf uf VJ uf S N.. SLK(I) N.. IN(U/) N.. SPI/U N...N.. V I L W MXU+, -it, Nonvolatile Linear-Taper igital Potentiometer uf uf R R uf V uf nf R k R k I IN+ OUT IN- I IN+ OUT IN- I IN+ OUT IN- PR OUT UF IN V+ R R R INI R k esigner P. lvarez / M. attin rawn by P. lvarez / M. attin // heck.by egelec N. Lopez // Last Mod. Modifiedy // File power_supply_switching.schoc Print ate // :: Sheet of Size Rev * --V- VJ_FK R k PV_PIe_FILTR PV VJ PV V nf R UR_SNS_VJ k pull down resistor is to be mounted in case a non adjastable V is needed. In this case, k and k must be unmounted. VJ

18 R QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ R R amping resistor placed insided the FPG. R and \ tied high to enable single clock mode. K clock is used for both input and ouput. Termination resistors must be placed close to YKV-ZX. R R R R R R PV R R R R R R R R QR_OFF_N QR_WS_N QR_WS_N QR_WPS_N QR_RPS_N QR_K_P QR_K_N QR_Q_N QR_Q_P QR_TO.W QR_TK QR_TMS QR_TI R VTT_QRII R R R I YKV-ZX P Q N Q L Q K Q G Q F Q Q Q N Q N Q N Q P Q P F Q P J Q P K Q R L Q R M Q R P Q R R R H OFF N WS M WS L WPS J RPS G F K K P R Q Q H G ZQ J R K TO R M TK R N TMS R P TI R R R Termination resistors must be placed close to FPG. R R R R R R R R R R R R VTT_QRII R R R QR_Q QR_Q QR_Q QR_Q QR_Q QR_Q QR_Q QR_Q QR_Q QR_Q QR_Q QR_Q QR_Q QR_Q QR_Q QR_Q QR_Q QR_Q R Termination resistors must be placed close to YKV-ZX. R R R R R R R R R R R R R R VTT_QRII R R R QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ QR_ PV I YKV-ZX F V /M F V /M G V G V H V H V J V J V K V PV K V VQ VQ F VQ F VQ G F VQ G F VQ H F VQ H G VQ H G VQ H G VQ J J VQ J J VQ K J VQ K K VQ L K VQ L K VQ L L L M M M N N N P P F P G H J VRF_QRII K L H VRF L H VRF L M N M N M M M VTT_QRII uf PV R R nf V I VLOIN RFIN N P PGOO VO VOSNS RFOUT P TPSRT.V Sink/Source R Termination Regulator R.V.V GN and QRII share the same VTT supply!!! We keep two different drivers just in case one is not able to supply enough current, but normally only one should be mounted. VTTQRII_GOO uf VTT_QRII uf uf uf PV PV VRF_QRII VTT_QRII Project/quipment ocument -O PIe FM arrier QR II uropean Organization for Nuclear Research H- Genève - Switzerland esigner P. lvarez / M. attin rawn by P. lvarez / M. attin heck.by egelec N. Lopez Last Mod. Modifiedy File qdr.schoc Print ate // :: --V- // // // Sheet of Size Rev *

19 ST_TX_P ST_TX_N ST_TX_P ST_TX_N ST_RX_P ST_RX_N ST_RX_P ST_RX_N USRLK_OUT_P USRLK_OUT_N USRLK_IN_P USRLK_IN_N _ST_TX_P _ST_TX_N _ST_TX_P _ST_TX_N _ST_RX_P _ST_RX_N _ST_RX_P _ST_RX_N _USRLK_OUT_P _USRLK_OUT_N _USRLK_IN_P _USRLK_IN_N USRIO_P USRIO_N _USRLK_OUT_N _USRLK_OUT_P _ST_TX_P _ST_TX_N _ST_RX_N _ST_RX_P J SHIL ST J SHIL ST USRIO_P USRIO_N _USRLK_IN_N _USRLK_IN_P _ST_TX_P _ST_TX_N _ST_RX_N _ST_RX_P J SHIL ST J SHIL ST THRMO_I R k I V Q SU+ Programmable Resolution -Wire igital Thermometer (- to + ) nf V USRLK_IN_N USRLK_IN_P I N N N N Y Z Y Z Y Z Y Z V SNLPW USRLK_IN_TO_FPG_N USRLK_IN_TO_FPG_P USRLK_IN_TO N USRLK_IN_TO P nf V V Project/quipment ocument -O PIe FM arrier Rear onnectors uropean Organization for Nuclear Research H- Genève - Switzerland esigner P. lvarez / M. attin rawn by P. lvarez / M. attin heck.by egelec N. Lopez Last Mod. Modifiedy File rear_connectors.schoc Print ate // :: --V- // // // Sheet of Size Rev *

20 V L R@MHz L R@MHz SFP_VT SFP_VR V SFP_VR SFP_VT dd age Top Here agetop (x: TYO_-) VR R+ VR R- VR VR VR T+ J T- VT TX_FULT TX_ISL VT MO_F VT MO_F VT MO_F RT_SLT LOS ageot G G G G G G G G dd age ottom Here G G (x: TYO_-) G SFP SFPRX P SFPRX N SFPTX P SFPTX N R R R R R SFP_TX_FULT SFP_TX_ISL SFP_MO_F SFP_MO_F SFP_MO_F SFP_RT_SLT SFP_LOS Project/quipment ocument -O PIe FM arrier SFP uropean Organization for Nuclear Research H- Genève - Switzerland esigner P. lvarez / M. attin rawn by P. lvarez / M. attin heck.by egelec N. Lopez Last Mod. Modifiedy File sfp.schoc Print ate // :: --V- // // // Sheet of Size Rev *