Inverted Input A to make routing easier fix in FPGA U2 ADS62P4X LVDS ADC

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Imogene Fletcher
6 years ago
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1 0 0 opyright 0 ttus Research. nverted nput to make routing easier fix in U SX VS V _0 0 p V_TX: R0 R R R S_ S_ S_ S_ V_TX: U TR T/ RST S 0 S S S R R S R0 S 0 % V_ 0 _ V V_ 0 _ in 00 R in _0 0 0 _0 0 0 n p n p n p n p n _0 p _0 n _TX: p n _0 0 p _0 0 _0 n TX_ TX_ TX_ TX_ TX_ TX0_ TX0_ TX0_ TX0_ TX0_ TX0_ TX0_ TX0_ TX0_ TX0_ TX00_ _ _ U UT_ UT_ UT_ UT_ TX_ TX_ TX_ TX_ TX_ TX0_ TX0_ TX0_ TX0_ TX0_ TX0_ TX0_ TX0_ TX0_ TX0_ TX00_ U _/S UT /RT UT _ UT_ UT p n p n p n p n _0 0 p _0 0 n p 0 n out _clkout_p out _clkout_n U VR_ SX TR S_ S V S_ ST RST V_TX: V_TX: S_ S TR R WR V V 0 V V V V V V V _ V V V V 0 V 0 U TR TR R0 0 R0 0 V_RX: _TX: V_RX: V_RX: 0 U R R R R R RV RV RV RV V V V SX VS WR USR lus s TT $ate$ : codecs.sch RVS: $Rev$ RW Y: $uthor$ 0 0

2 0 V_: These are really VccUX U 0 xx 0 X T V_: n/c XS00 T U S S S S R Vref/Vref 0 T 0/S R R/TS TS 0 V_: T : /T R T 0 T one/t R X T V_: T 0 TS in/t 0 T R0 0 R0 0 R0 0 opyright 0 ttus Research. Vref/Vref R T_ S ctually Vcco V_: / T/ V_: 0. R0 R This is really Vcco0. _V_: This is really VccUX V_: R_ ctually VccUX V_: R0 R0 V_: slot=. VccUX Voltage =.V U_ U_ R_ R V0 R0 XS00 /W 0/U_ R_ SUS U _0_/0 _0_/ _0_/S 0_/ /VS /RWR /VS0 /VS / / / / _0_/S/S /UT / /T / / / lternate lash rogramming able Y Y 0 0 Y 00 flash_cs 00 flash_mosi T_ flash_clk R R0 R R R R lternate lash footprint V_: V_: flash_wp Rflash_mosi V_: flash_wp flash_mosi flash_clk flash_clk R/TS /T one/t S S in/t / T/ U S S 0 V_: U W/Vpp V_: W/Vpp V 0 V flash_cs flash_clk flash_miso flash_mosi XX V S S S XX S S flash_cs flash_cs flash_miso V_: flash_cs flash_miso R0 0 R 0 /0//S flash_miso USR lus onfiguration TT $ate$ : config.sch RVS: RW Y: $Revision$ $uthor$ 0

3 V_TX: V_TX: _TX: S_TX_ V_TX: V_TX: _TX: _TX: _TX: V_TX: opyright 0 ttus Research. V_TX: 0 0 S_TX TX R S_TX_ S_TX_ 0 V_TX: orner freq 0z, d/octave U V_TX: Ref 0 R in R0 00 SY S _TX: x 0 0 R : 00 Vdd clock_tx_p clock_tx_n V_TX: U _TX: 0 UT UT 0 n n. U V_TX: 0 S_TX_ S S_TX_ in _TX TX 0u p lace at U S_TX_ out X S Vin 0u S_TX TX: ddress S Vin0 U0 _TX: V_TX: Vdd Vdd S UT _TX S_TX_ S 0 UT _TX Vref S_TX_ S_TX_ S_TX_ S S S_TX_ S Vref _TX R S_TX_ S Vref 0 _TX: _TX: _TX: _TX: _TX: _TX: UT_ UT_ UT_ UT_ V_TX: V_TX: io_tx_00 io_tx_0 io_tx_0 io_tx_0 io_tx_0 io_tx_0 io_tx_0 io_tx_0 io_tx_0 io_tx_0 io_tx_0 io_tx_ io_tx_ io_tx_ io_tx_ io_tx_ V_ V_ VR_ V_ V_ V_RX: V_RX: io_rx_00 io_rx_0 io_rx_0 io_rx_0 io_rx_0 io_rx_0 io_rx_0 io_rx_0 io_rx_0 io_rx_0 io_rx_0 io_rx_ io_rx_ io_rx_ io_rx_ io_rx RX: _RX: _RX: _RX: _RX: V_RX: Vref V_RX: _RX: _RX: _RX: S_RX_ S_RX_ S_RX_ S_RX_ S S 0 V_RX: V_RX: V_RX: V_RX: V_RX: U _RX: Vdd S_RX_ S Vin0 S_RX_ out Vin X S _RX ddress S_RX_ S in S_RX RX U V_RX: 0u orner freq 0z, d/octave : 00 R R U0 _RX: clock_rx_p Vdd S UT _RX n n. clock_rx_n S 0 UT V_RX: S_RX RX p V_RX: U S_RX_ S _RX R Vref _RX: S_RX_ S Vref UT UT lace at U Vdd 0 0 S SY in x R Ref _RX: 0u 0 V_RX: _RX: USR lus aughterboad nterface S_RX_ S_RX_ S_RX_ V_RX: 0 _RX: 0 _RX R $ate$ TT $Revision$ : dboard.sch RVS: _RX: $uthor$ RW Y: _RX: _RX 0

4 0 0 V_: 0 0 R0 0u 0 V_:, 0 T0 R. V_: R. VTX U V_: 0 Vcc UT 0z /TU R. R 0 V_: V_: R 0 R 0 R 0 R. clk_exp_in_p clk_exp_in_n R 00 U SY 0 V_: R + VT 0 + VT + VT + VT 0 0 V S0 S UT_ UT_ 0 R 00 R 00 clkref_p clkref_n R clk_sel0 clk_sel 00 0 U R_ R _ 00 0 R0 00 R0 00 R0 V_: VTX 0u R 00 0u under U next to pin of U Vcc U UT /TU.u R0 0 R0 0.u kz W, deg hase margin with z compare freq and m current u V_RX: _RX: utputs to: Test xpansion VS TX board VS RX board VS SRS VS U 0 UT UT0_ UT0_ UT_ UT_ UT_ UT_ UT_ testclk_p testclk_n opyright 0 ttus Research R 00 R 00 R 00 R 00 R0 00 R V_: T U UT Vin Vout 0p u u V_: 0 V_: 0 or irefly S U 0 UT UT_ UT_ UT_ UT_ UT_ SRS clk is generated from clock_tx_p clock_tx_n clk_exp_out_p V_: R R 00 _U R 00 _STTUS S_ S_ S_ U 0 TR UT STTUS S S 0 S 0 0 R. 0 0p R0. R V_: U SUT Vcc Y S_ 0 R. 0p R. R V_: U SUT Vcc Y S_ UT_ UT_ UT_ clk_exp_out_n clock_rx_p clock_rx_n V_:. R R S_ S 0 R0 V_: 00 0 V_: R0. % U RST RST R0. % Vcp VS 0 VS VS VS VS VS VS VS VS VS _ 0 VS VS VS 0 VS VS 0 VS VS VS VS VS VS 0 WR. R V_: R USR lus locks TT $ate$ : clock.sch RVS: $Rev$ RW Y: $uthor$ 0

5 0 opyright 0 ttus Research. _V_SR_: _V_SR: 00 R0 00 R0 ser_tx_clk ser_tklsb ser_tkmsb ser_t00 ser_t0 ser_t0 ser_t0 ser_t0 ser_t0 ser_t0 ser_t0 ser_t0 ser_t0 ser_t0 ser_t ser_t ser_t ser_t ser_t TXX TX TX_ TS/TX_R 0 TS/TX_ TX0 TX TX TX TX TX TX TX 0 TX TX TX0 TX TX TX TX TX U UTTX UTTX 0. R. R 0.0u 0 ser_out_n ser_out_p 0 0.0u ser_rx_en ser_rklsb ser_rkmsb ser_r00 ser_r0 ser_r0 ser_r0 ser_r0 ser_r0 ser_r0 ser_r0 ser_r0 ser_r0 ser_r0 ser_r ser_r ser_r ser_r ser_r U TXX RX R RS/RX_R/RS_SS 0 RS/RX_V/S RX0 0 RX RX RX RX RX RX RX 0 RX RX RX0 RX RX RX RX RX RX RX. R0. R0 0.0u 0 ser_in_n ser_in_p 0 0.0u ser_rx_clk RX_ 0.0u _V_SR_: 0 _V_SR: R 0 R 00 R 0 _V_: ser_in_p ser_in_n 0 SS SS X RX0_ RX0_ TX0_ TX0_ ser_out_p ser_out_n SS SS X S 0 0 _V_SR_: ser_enable ser_loopen ser_prbsen 00 R 0.0u RS Rref V V V V V V V TXX WR 0.0u 0.0u 0.0u 0.0u 0.0u _V_: R 0 exp_user_in_p exp_user_in_n clk_exp_in_p clk_exp_in_n 0 0 RX_ RX_ RX_ RX_ TX_ TX_ TX_ TX_ 0 exp_user_out_p exp_user_out_n clk_exp_out_p clk_exp_out_n R 00 R 00 VS VS TST _ U R 00 exp_time_in_p exp_time_in_n RX_ RX_ TX_ TX_ exp_time_out_p exp_time_out_n R 00 VS R 0 USR lus xpansion TT $ate$ 0 : expansion.sch RVS: $Revision$ RW Y: $uthor$

6 0 0.0u 0.0u 0 0.0u 0.0u R R 0 0 opyright 0 ttus Research. SSS_: T0 U R0. % R % U T0 RST RS TR0_ TR0_ TR_ TR_ TR_ TR_ TR_ TR V_T: 0. R0. R0. R0. R0. R0. R R R0 0 0 XT _ 0 _ S/ S/ T T T T S S SSS_: _V_T: 0 0u VTX X Vcc UT /TU Y_ 0 R R _V_T: R _Z _RS _RX RX_R _RX_V _RX0 _RX _RX _RX _RX _RX _RX _RX R0 R R R R R R R0 R R R R R RS RX_ 0 RX_R RX_V RX0 RX RX RX RX RX 0 RX RX TX_ TX_R TX_ TX0 TX TX TX TX TX TX TX TX_ 0 R R R R R R0 R R R R R R _TX TX_R _TX TX0 _TX _TX _TX _TX _TX _TX _TX _TX_ u R XR.V _V_T: T_ T_ R0 R R0 R (Yellow ath) (Yellow node) (rn ath/rg n) (rn n/rg ath) _V_T: T0 U S0 _V_T_: u R XR.V.u V_T_: _V_T: V_T: 0 00u.V 0 T U T0 WR V_R TR_V TR_V0 V_ V_ V_ V_ V_ V_ V_V V_V _V_T: V_T: _V_T: _V_T: R R R 0 R R 0 R T_ R S S 0 Y Y Y Y/00 Y0/_TXRX SYS /SR /SR S_000/000 0 US/_ u R XR.V.u.u u R XR.V.u V_V V_V V_V V_V V_V V_V V_V 0 0 _V_T_: U T0 T TRST T_SR T TS_SR T _V_T: R R Y_Tn U T0 T TRRUT Y_ Y_RST _T_ U T0 _/XT_ XT_ RST SYS_ V_V 0 V_V V_T_: V_V _ V_V USR lus thernet TT $ate$ : ethernet.sch RVS: $Revision$ RW Y: $uthor$

7 0 opyright 0 ttus Research. U Y R R_00 a (bit) R_0 a (bit) R_0 a (bit) R_0 R_0 a (bit) R_ R_0 a (bit) R_ R_0 R_0 R_0 a a a R_ R_ R_ X xtra ower Supply ins for T Version? R_0 a R_ R_0 R_0 R_ b b b R_ R_ R V_R: U Y WR V R_ b R_0 V 0 R_ b R_0 0 V R_ R_ R_ R_ b b b 0 b 0 R_0 R_0 R_0 R_0 U Y TR ZZ R_ZZ V V V 0 V 0 R_ c R_0 V 0 R_ c R_0 V R_0 R_ c c 00 R_0 R_0 V V R_ c 0 R_00 V 0 R_ c R_ c R_ c R_ c R_ d R_ d R_ d R_0 d R_ d _V_R: R_ d R_ d R_ d R_ 0 d W V/ Wa Wb Wc Wd R_n R_n _V_R: R_ R_Wn R_n R_n R_Wn R_Wn R_Wn R_Wn TT USR lus R $ate$ : ram.sch RVS: $Rev$ 0 RW Y: $uthor$

8 XS _0_0 0 _0_0 _0_0 _0_0 _0_0 _0_0 _0_0 _0_0 _0_0 _0_0 _0_0 _0_0 _0_0 _0_0 _0_ _0_ _0_0 _0_ _0_0 _0_ _0_0/VR_0 0/VR_0 _0_0/VR_0 0/VR_0 0/VR_0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0/VR_0 _0/VR_0 _0/VR_0 _0/VR_0 U opyright 0 ttus Research. ank 0,.V R Removed Vcco0 due to bug in gnetlist _V_: V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 XS00 T U 0/ 0/ 0/ 0/ 0/ 0/ 0/ 0/0 USR lus ank 0 TT $ate$ : fpga bank0.sch RVS: $Rev$ RW Y: $uthor$ 0 0 R_ R_ R_0 R_ R_ R_ R_ R_ R_ R_ R_ R_ R_0 R_ R_ R_ R_ R_ R_0 R_ R_ R_ R_ R_ R_ R_ R_ R_ R_0 R_0 R_0 R_0 R_0 R_0 R_0 R_0 R_0 R_0 R_00 R_n R_ R_Wn R_n R_n R_Wn R_Wn R_Wn R_Wn R_n R_ZZ R_00 R_0 R_0 R_0 R_0 R_0 R_0 R_0 R_0 R_0 R_0 R_ R_ R_ R_ R_ R_ R_ 0

9 Removed Vcco because of gnetlist bug U U Y U V R R _V_: V_ W _0_/VR /VR /VR /VR /VR /VR /VR /VR /VR /VR 0 0_ T V_ T V_ V_ V_ V_ V_ V_ V_ V 0 0 / /0 / / / 0 / 0 XS00 Y _0_/ Y0 _0_/ _0_/0 _0_/ _0_/ _0_/0 W _0_ W0 _ _ V _0_ V _0 0 0_ U0 _0_ V _0 U U Y Y T0 U Y Y T T V W V V U V R0 R U R / R / T / T / R / R / R / R / / /0 / / / / 0 / 0 / / / _ XS00 R U 0 _0_/R _0_/R0 /TRY/R /R /R /RY/R TT : fpga bank.sch RVS: $Rev$ 0 RW Y: $uthor$ 0 0 opyright 0 ttus Research. ank,.v o VS ut thernet SRS xpansion VS in _V_:. R _RST S 0 _TX_R _TX TX0 _TX _TX _TX _TX _TX _TX _TX T TX_ ser_rx_en ser_rklsb ser_rkmsb ser_r00 ser_r0 ser_r0 ser_r0 ser_r0 ser_r0 ser_r0 ser_r0 ser_r0 ser_r0 ser_r0 ser_r ser_r ser_r ser_r ser_r ser_tklsb ser_tkmsb ser_t00 ser_t0 ser_t0 ser_t0 ser_t0 ser_t0 ser_t0 ser_t0 ser_t0 ser_t0 ser_t0 ser_t ser_t ser_t ser_t ser_t ser_enable ser_loopen ser_prbsen exp_user_in_n exp_user_in_p exp_time_in_n exp_time_in_p Y_RST Y_Tn RS _RX_R _RX_V _RX0 _RX _RX _RX _RX _RX _RX _RX _RX TX T_ USR lus ank $ate$ 0 0 R ser_tx_clk /R 0 /R ser_rx_clk

10 0 0 0 TR debug_clk0 0 debug_clk debug_ debug_ [] [] debug_0 [] [] 0 debug_ [] ank,.v S onfig lock nterface ebug T s RS debug_ [] debug_ debug_ [] [] debug_ debug_ [] [] debug_ debug_0 [] [] debug_ 0 debug_0 0 [] V_: 0 [] debug_ X o we need RTS, TS, TR, SR,, R? Y _/VR /VR /VR /VR /VR /VR /VR /VR /VR_ W V_ V_ W V_ U V_ V_ V_ V_ V_ V_ V 0_ 0 0 U V Y V W 0_ 0 0 U V V W 0 XS00 _ Y _0_ W _ _ W0 _0_ V0 _ Y0 U V W V W _0_ V _0 debug_0 [0] opyright 0 ttus Research. V_: 0 u R XR 0V [0] debug_ V_: debug_0 0[] [] debug_ R 0 debug_0 0[] [] debug_ dsr debug_0 0[] [] debug_ R R 0 ri cts rts txd rxd debug_0 0 0[] [] debug_0 XS00 T U debug_0 0[] [] debug_ dtr R R 00 R R 00 TX_ V_: RX_ footprint=s device=x U X V+ + Y / / RX debug_0 0[] [] debug_ 0 Vcc nc / / / gnd TX debug_0 0[] [] debug_ V + debug_00 Y /0 / / TT : fpga bank.sch RVS: $Rev$ RW Y: $uthor$ 0[0] [0] debug_ TX Tx n Tx ut TX_ 0 R0 R 0 R R 0 RX Rx ut Rx n RX_ TX_ TX 0 Tx n Tx ut TX_ RX_ RX Rx n Rx ut RX_ S_ S_ S_ RX RX RX Removed Vcco because of gnetlist bug V_: 0 TX TX TX S S clk_sel clk_sel0 _U _STTUS S_ S_ S_ debug_00 debug_0 debug_0 debug_0 debug_0 debug_0 debug_0 debug_0 debug_0 debug_0 debug_0 debug_ debug_ debug_ debug_ debug_ S_TX_ S_TX_ S_TX_ S_TX_ S_TX_ S_TX_ S_TX_ S_TX_ S_TX_ S_ S_ S_ debug_clk0 debug_ debug_0 debug_ debug_ debug_ debug_ debug_ debug_ debug_ debug_ debug_ debug_0 debug_ debug_ debug_ debug_ debug_clk. R0 S {S,S,S}_{TX_,TX_,TX_,} all moved from bank ( total lines) S. R0 V_: slot= R V_: slot= R V_: slot= R V_: slot= R V_: exp_time_out_n slot= exp_time_out_p exp_user_out_n R USR lus ank $ate$ 0 0 exp_user_out_p V_:

11 U V_: _ _0 0 R R R T T R _0_ R _0 U T R U U R R V V T T0 V U U T W W Y Y U U Y Y V V 0 0_ V U W W /VR /VR /VR /VR /VR /VR 0_/VR 0 0_/VR 0 /VR R R0 Y V U W W V_ W V_ T V_ T V_ V_ V_ V_ V_ V_ V_ XS00 U / /0 /RY/ / / / 0 / /TRY/ TT : fpga bank.sch RVS: $Rev$ RW Y: $uthor$ XS opyright 0 ttus Research. X heck all S connections ank,.v / S, S USR lus ank $ate$ 0 0 S_ S_ S_ S_RX_ S_RX_ S_RX_ S_RX_ S_RX_ S_RX_ S_RX_ S_RX_ S_RX_ io_tx_00 io_tx_0 io_tx_0 io_tx_0 io_tx_0 io_tx_0 io_tx_0 io_tx_0 io_tx_0 io_tx_0 io_tx_0 io_tx_ io_tx_ io_tx_ io_tx_ io_tx_ TX_ TX_ TX_ TX_ TX_ TX0_ TX0_ TX0_ TX0_ TX0_ TX0_ TX0_ TX0_ TX0_ TX0_ TX00_ TX_ TX_ TX_ TX_ TX_ TX0_ TX0_ TX0_ TX0_ TX0_ TX0_ TX0_ TX0_ TX0_ TX0_ TX00 0 n _0 p n p n p n p n p _0 n _0 p n p _0 n _0 p n p io_rx_0 io_rx_0 io_rx_0 io_rx_0 io_rx_0 io_rx_0 io_rx_0 io_rx_0 io_rx_ io_rx_ io_rx_ io_rx_ io_rx_ 0 io_rx_00 io_rx_0 io_rx_0 S_ Removed Vcco because of gnetlist bug S_TX_ S_TX_ S_RX_ S_RX n p _0 n _0 p n p n p n p _clkout_n _clkout_p _ {S,S,S}_{TX_,TX_,TX_,} all moved to bank ( total lines)

12 0 0 Vunreg: 0 0 u R XR 0V u R XR 0V TS0 W U V T V UV WR S RT VS R u R0 0 _V: 00 u _V: 0 _V: 0 _V: 0 V: 0 Vunreg:.u R XR V 0 u V: V: 0 u V_: 0 u V: u V_TX: u V: 0 u V_RX: u opyright 0 ttus Research. R0 SY R0 0 R u SY 0 00p 0 00p _ 0 VSS R0 0 u R0 0 R0 0 00p R0. 0 0u u R XR.V Vunprot: Si 0V reverse and +0V overvoltage protection V trips at.0v with ~00mV hysteresis Si R 0 0 ZV W R 0 R 0 Vunreg: 00 00u 0V ront anel ower 0 0 S XXX u Vunprot: 0 S XXX T ower 0 0.u Vunreg: u R XR 0V u R XR 0V SY R0 0 R 0 R TS0 W U V T V UV WR S RT VS SY 0 VSS _ R. u u R _V: 0 u u R XR.V 0u ower Supplies 0 ZV V aughterboard ower (<), V for clock reg.v 0 (<00m), lock (m).v (00m), (<00m).V ll (<), UX.V thernet ore (00m), SRS (<0m), R (<00m).V ore (<).0V thernet ore R 00 R 0 0 Vunreg: 0 00m ower R0.u R XR V 0 0.0u p R 0 _V: 0 V_TX: _V: 0 V_RX: _V: _V_: _V: 0 _V_T: X ore ecoupling on. at _V: Vunreg: 0p R. R R. 00p 0 0 0p p _TX: 0 u p p _RX: 00 u 0p 0p u 0p 0p u u R XR 0V u R XR 0V TS0 W U V T V UV WR S RT VS R. u R _V: 0 u _V: 0 0p 0 0p V_RX: u _V: 0p 0 0p V_TX: u _V: 0 0p 0p _V_SR: u _V: 0 0 0p p _V_R: 0 u _V: 0 0.u.u.u.u.u.u.u.u.u.u.u.u R 0 R0 0 SY R SY _ 0 VSS u 0u u R XR.V _V: 0 V_: V_: 0.0u 00p 00p R R 0 R 00p 0p 0p u 0 0.u.u.u.u.u.u.u.u.u.u.u.u R. _V: V_: U Y VT Y VT Y VT Y VT Y VT W VT U VT T VT T VT T VT R VT R VT R VT VT VT VT VT VT VT VT VT VT VT VT VT VT VT VT VT VT VT 0 VT VT VT VT VT W VUX V VUX U VUX T VUX VUX 0 VUX VUX VUX VUX VUX VUX VUX VUX 0 VUX VUX VUX VUX VUX VUX VUX VUX VUX VUX VUX XS00 WR R R R T T T T T T T U0 U U U V W W W W W USR lus ower $ate$ : power.sch RVS: $Revision$ RW Y: $uthor$ 0 0 TT

U100. cgen_by BYPASS. cgen_cp CLK_FPGA_P (OUT0A) OUT0 CLK_FPGA_N (OUT0B) OUT0 (OUT1A) OUT1 (OUT1B) OUT1 (OUT2A) OUT2 U10 DS90LT012AH (OUT2B) OUT2

U100. cgen_by BYPASS. cgen_cp CLK_FPGA_P (OUT0A) OUT0 CLK_FPGA_N (OUT0B) OUT0 (OUT1A) OUT1 (OUT1B) OUT1 (OUT2A) OUT2 U10 DS90LT012AH (OUT2B) OUT2 9 0 TX nternal Reference loop filter for internal V vco_cp R.0 vco_vtune loop filter for VX vcxo_cp R0 0 vcxo_vtune V_TX: 0 0u VTX Vcc X UT /TU V_TX: R 0 0n p cgen_int_ref p vcxo_clk R 0 refer Ref ode