[1,2,3,4,6] VBAT. Headset Battery [1] BAT-M VBAT_M [1,6] BAT_ON 10K R2002 [1] BAT_DET CS_N(VBAT-) VBAT- [1,6] J2003 BAT-4PIN-BM22-4P [1] VBAT_M

Transcription

1 R00 R000 J00 MI-OS-T J000 MI-OS-T V T V T 0.u.V 0 J u.V R-00 MIIS0 MIIS0 [,,] [,] [,,,] [,] V0 V00 V0 p 00 00p 00 p 00 V0 VUS VIO T_HG_STT GPIO_HG_N 00 p 0 p 00 p 0 p 00p 0 00p 0 R0 R0 00K 0 LM0SN 0 LM0SN 00 LM0SN 00 LM0SN 00 LM0SN 00 LM0SN 0K 0 u u/v [,,,,] [,,].u 0 S SL VT VUS GPIO_HRG_SL VT_M [] R_P R_N 0 R00 R0 0 00n R0 MI+ VT- MI-.u/V MI+ 0K 0K/ U00 bq [] [,,,,] TST RGN P P VT_M VT SYS T ILIM TS TS 0 0 VUS < V,0=.u (0V) VUS > V,0=u (0V) R0 R00 R0 R0 0.u/0V R,R close each other R0 0K 0K ISNS I=0/R TSNS 0 n/v VT_M L00.uH > [] [,] RR_L 0 0u u lose to ore oard VT pin [,,,,] GPIO_UIO_P_N VT n n VT T-M S_N(VT-) R0.K R0.K [,,,,] J00 T-P-M-P R0 0.u R00 00K 00 0p V00 SHN N P U00 W.u 00 V0.u 00 0K R00 PV VOP VON VT_M T_ON 0 0 VT- VT_M T_ON T_T RMI- MI- [] [,] [,] [] [,] [] [,] n 0 n 0 J00 VIR u 00 MOTO+ MOTO- RMI+ [,] [] M_NT_P M_RX_N_P J00 VI-00 RR_L T_R_H RR_R M_NT_H R0 R0 p 0 00p 0 p 0.K 0.u 00.K 00.K 00.K 00 R00 R00 00.K [] T_T UTX0 URX0 [,] US_M [,] US_P.KJ0GZL J00 TP00 TP00 TP00 TP TP TP UIO harger V OTG Pin for OTG current: High--00m; Low--00m Sub MI Headset attery Main MI Receiver V00 V00 lose to Rec VUS VUS PMI /PG STT S SL T OTG/IUS / PSL SYS T Speaker Gain = 0K/(.K+Rin) 0=/(.*(.K+Rin)*in).K,n ---0=Hz; Gain=. V V P G N P G W G N N 00.u V0 V0 Motor VIR_PMU:.V 0 V00 V00 V00 V00 RWN Y.K is value for ead, not for Resistor MP Test Points urope:r00,00 SMT;R00,00 merican:r00,00 ;R00,00 SMT PROJT SHT of or Phone ONNTIL TITL UIO HK Y SIZ VR <T HR> <V.00>

2 [,,,,] GPIO_N_N [,,,,] VT R0 GPIO_M_ VT VRT RP RN RP RN RP0 RN0 RP RN RP RN R00 00K R0 00K u.u J00 T0P--R u.u u u 0n 00n 00n u U0 0 VT N V_P V V V 0 V V_IO TP MS_N_VP MS_N_PIO [,] VSIM VSIM_N SIM_N_P NT_N TX_N TX_P RX_P NT_P TP U00 LO-S0- N U00 LO-NX-L V N P VOUT OUT P/ 0 0n 0n GPIO_M_PN M amera sensor will pull this P to, (M is ) GPIO_M_RST S0 SL0 00 VM_PMU VM PMU VMIO VM 00.u MMLK u VMIO VM_PMU VM VM PMU [,] VM VM PMU [,] [,] [,] [,] u TP TST_MO/GPIO/OS_N/JTG_TO URT_TX/I_T/SPI_S URT_RX/I_K/SPI_K SPI_MISO/GPIO/JTG_TMS/G_TX SPI_MOSI/GPIO/JTG_TK/G_RX [,] S0 [,] SL0 [,] GPIO_SU_PN [,] GPIO_SU_RST VM VM VM PMU [,] VMIO 00 IRQ/GPIO T/GPIO/JTG_TI GPIO0/JTG_TRST MT0 GPIO0_M_M_V GPIO_SU_M_V VM 0 u R0 / R0 0K/ 0 u TP TP R00 00K J00 TP-0 R00 00K 0 0 u N_M 00 u 00 S SL VIO u GPIO_N_RST GPIO_M [,] [,] [,,] [,,] U00 LO-NX-L [,,,,] GPIO_N_IRQ V N R0 R0 R0 R R R V N P GPIO_N_T N_M VOUT U00 LO-NX-L P VOUT [,] RN_ RP_ RN0_ RP0_ RN_ RP_ MT MT MVSY MHSY MT MT MMLK 00.u HOT 00.u [,] X0 M-W-- MHZ HOT VM_PMU VM J00 ON_V_0 H_ VM R0 R0 RX_P TX_P TX_N 00n R [,] XTL_ XTL_ R.R.R.R R.R R XTL_ XTL_ [,] GPIO_SU_RST MPLK VMIO 0 p p/0v R0 K 00n 00n HOT 0p VM R 0 00n 00 TP_00 R0 L0 p/0v 0nH U00 00K HOT 00n X00 M-W-- M /0V p/0v IP IP 0p TVP_TQP PLL_ PLL_V XTL/OS XTL RST R0 u /0V 0 0 p 0 /0V p/0v 0p 0 0K R u 00 TP_00 u R0 p/0v L0 0nH p/0v R R R VSY/PLI I/GLO S SL V YOUT0 YOUT RN_ RP_ RN_ RP_ 0 00n 0 0 R 00n R R R R MT MT MT MT MT MT VMIO VM GPIO_SU_PN[,] MVSY MHSY MHSY MVSY I/GLO S0 SL0 VM MT0 MT MT MT MT MT0 [,] [,] [,] VSIM [,] VSIM VSIM_N SIM_SRST SIM_SLK [,] VSIM SIM_N_P SIM_SIO SIM_SLK SIM_SRST SIM_SIO MS_T MS_T MS_M VMH MS_LK MS_T0 MS_T.u 0 u R00 R00 R00 R00 u J00 0 R0 00K SIM G G GPIO0_LSH_N V VPP LK RST IO G G P P P P P P P P P V V RST RST LK LK RSRV RSRV VPP I/0 RSRV J00 TR-0-00 T /T M V TT LK VSS T0 T 0 TJTL J00 MIRO-SIM-PUSH-P G G 0 Q00 G G 0.u R0 R LSH+ LSH- LSH- LSH+ VT [,,,,] N [,,,,] VIO M V T-ard SIM SIM /00 are close to each other OM for eature. R0=R00=0K if IO/IO need support Pt. R0=R00= if IO/IO no need to support Pt MIPI Lane SYSRST_ (N_RST).Input pin.internal pull high.low active.n_os_n is output pin, and high active..need to connect to host SRLKNI and SRLKNI pin need to be default low. Only can use HW I. I is not allowed. R0 : XTL MO R0 0K : o-lock.n_irq is output pin, and high active..n_irq is also strap pin and host I/ connected with IRQ need to be default low. N_T.Input pin.internal pull low.high active,,,,0,,,, need to use % accuracy and 0V tolerance capacitor, PS: 00 cap can't tolerance 0V omponents in this region 支持.0 的 SR0 rate mode ut for N app. equivalent capacitance of MS_N_PIO and MS_N_VP should <=0.p. use % accuracy Pin:High implies I address is h SIM R T R The equivalent capacitance of MS S protection device must be <=0p. V Lash L [,] GPIO_M VM:.V.V [,,,,] VT.u.u 0 NT_P 0 V_S RX_P TX_P MT0 QN x IO_S R0 0K/ V_PMU 0 TX_N V_SIM 0 0n RX_N IO/GPIO R NT_N V_PMU 0K/ 0.V.V VM PMU:.V VM_IO_PMU:.V VM_PMU:.V LK_ V_SIM 0n SYSRST_ IO M_ [,,,,] VT [,,,,] VT VM [,] VMIO TP TP0 NT_P H_V SLK 0 H_ IO_V RM YOUT/ISL RP YOUT PN YOUT TRQ/GPL/VLK YOUT NT_N VIS/LK_ YOUT HSY YOUT V_ 和 SU_M 只能二选一 ONNTIL RWN Y HK Y 00 V00 V00 V0 V0 V0 0 V0 V0 V0 V00 V0 V0 V00 V0 PROJT SIZ V00 SHT V00 of TITL TV VR <T HR> <V.00>

3 [,] [,,] [,,] URX UTX GPIO_N_T GPIO SL S [,,] [,,,,] [] [] R00 R0 R0 R0 SI_T LM_RST TP TN TP TN TP TN TP0 TN0 TP TN L00 L00 L00 L00 L00 L00 L00 L00 L00 L00 J00 ZIP J00 ZIP [,,,,] VIO 0 00n [,,] VIO 0 00n [,,,] VT 0 0u ISP_PWM VIH =.V R0 00K L0 V N U0 UP 0uH LX OVP 00 n R0 u/0v 0 R0 L+ VIO VIO L+ L- UX L- [] [] S SL VGP_TP T_TP GPIO0_TP_RST TP TP TP TP0 TP 0 u J00 ZIP-- MIPI_L J00 compatible design for RG L MIPI_L_light 00 b=0.v TP ONNTIL RWN Y V00 V00 V00 V00 PROJT SHT of TV HK Y SIZ VR V00 TITL <T HR> <V.00>

4 <V.00> PROJT RWN Y TITL <T HR> of VR SIZ HK Y SHT TV URT Key Pin US M-Sensor MM:R=R=R=R=R0=R== K:R=R=R=R0=R=;R= YS:R=R=R=;R=R0=R= MM 00n 00n 00n 00n 00n 0 J0 URT-0M u 0 0n R0 00K N P/ OUT U0 LO-S0-0.u J00 IT-0-0H. J0 IT-0-0H. V00 V0 J0 IT-0-0H. V V J0 IT-0-0H. V0 V0 R0 0K Q00 TJTL R 0K Q00 TJTL R 00K/ R0 R0 + V V- TOUT R ROUT 0 T T ROUT R TOUT V U0 SP R0 K/ R 00K Q00 TJTL R 0K V00 S-TVS-HG V0 V0 V0 J00 US-U-0-S0--US R0 R0 RY/TST/T S/ SL/SK S/SI V/V RSV SO/VPP VSS/VS TST TRG VI/V 0/ //TST RST//RSTN P U0 KM/MM/YS R / R / R / R / u /.u.u R0 / R / R0 (.K) J0 IT-0-0H. V0 V J0 IT-0-0H. V V J0 IT-0-0H. V V J0 IT-0-0H. V V [,] [,] KPOL0 [] UTX_V [] URX_V [] UTX_ [] URX_ [] V_.V [] UTX_ GPIO_SP_N [,,,] VT [,] [,] KPOL [] UTX_V UTX [,,,,] VIO [] V_.V [] V_.V [] V_.V PWRKY SYSRST [] URX_V URX [] URX_ US_I [,] US_P [,] US_M [,] VUS [,,] SL [,,] S [,] VIO [,,,,] VIO [,,,,] VIO [,,,,] VIO GPIO [,] GPIO_N_RST [,] [,] KPOL [,] KPROW [,] KPOL0 [,] KPROW [,] KPOL [,] KPROW [,] KPOL ONNTIL

5 ON ON J00 P_00 00 L00 M_NT_P 00 L00 [] L00 00 NT_R_RX NT_R_PRX ON ON 00 L00 00 NT_GPS NT_WII/T TV SM_Main NT_MIMO M P NT UL-R-SMT00 U00 UL-R-SMT00 U00 WII/T NT UL-R-SMT00 GPS NT U00 UL-R-SMT00 U00 ONNTIL RWN Y PROJT HK Y SIZ VR SHT of TITL <T HR> <V.00>

6 [] [] RN_ RP_ RP RP0 RN0 RN MS_T0 MS_T MS_T MS_T MS_M MS_LK VMH SIM_SIO SIM_SRST SIM_SLK VSIM RN_ RP_ RN_ RP_ RN0_ RP0_ RN_ RP_ SIM_SRST VSIM VMIO [] ISNS [] TSNS [,] VIO [] VGP_TP VRT [] VIR [] PWRKY [] MI+ [] MI- [] SL [] [] [] [] [] [] [] NT_GPS [] NT_WII/T [] S MIIS0 M_NT_H [] RMI+ MI+ [] M_RX_N_P [] RR_R [] RR_L R_P R_N GPIO_UIO_P_N T_R_H J00 MOUL_M0 0+P GPIO/PI_0 GPIO_SU_M_V/PI_ URX/GPIO/PI_HSY URX/GPIO/PI_K0 UTX/GPIO0_LSH_N/PI_0 UTX/GPIO/PI_VSY SL S NT_R_RX SL S UTX0 URX0 UTX URX ISP_PWM/GPIO KPOL0 KPOL KPOL/GPIO IS_T_/GPIO_HG_N SPI_K/GPIO_HG_STT SPI_MO/GPIO_HRG_SL SPI_MI/GPIO_SP_N /SPI_S/GPIO//KROW NT_R_PRX US_I GPIO_M MPLK MMLK SL0 S0 GPIO_M_RST GPIO_M_PN GPIO_SU_RST GPIO_SU_PN US_I US_M VUS [] RMI- MI- VT VT- UX TP0 TN0 TP TN TP TN TP TN US_P T_ON TP TN [,,,] [] [] [] [] [] [] [] [] [] [] [] [] GPIO0_M_M_V GPIO_N_T GPIO_M_ GPIO_N_N GPIO_N_RST GPIO_N_IRQ GPIO GPIO_SU_M_V URX GPIO GPIO0_LSH_N UTX SL S NT_R_RX SL S UTX0 URX0 UTX URX ISP_PWM KPOL0 KPOL KPOL GPIO_HG_N T_HG_STT GPIO_HRG_SL GPIO_SP_N KPROW NT_R_PRX T_TP GPIO0_TP_RST SI_T LM_RST [,] [] [,] [,] [] [,] [] [] [] [,] [] [] [] [] [,,] [,,] [] [,] [,] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [,,,,] VIO R00 R00.K.K SL S [,] [,] RP RN RN RP RN RP SIM_SIO SIM_SLK [,,,,] VIO [] SYSRST 0 NT_GPS RN RP RN RP RN0 RP0 RN RP 0 RN RP RP_ RN_ RP0_ RN0_ RP_ RN_ RP_ RN_ RP_ RN_ GPIO_M MPLK MMLK SL0 S0 GPIO_M_RST/PI_0 GPIO_M_PN/PI_ GPIO_SU_RST/PI_ GPIO_SU_PN/PI_ GPIO0_M_M_V/PI_ GPIO_N_T/PI_ GPIO_M_/PI_ GPIO_N_N/PI_ GPIO_N_RST/PI_ GPIO_N_IRQ/PI_ NT_WII/T MS_T0 MS_T MS_T MS_T MS_M MS_LK VMH SIM_SIO SIM_SRST SIM_SLK VSIM SIM_SIO SIM_SRST SIM_SLK VSIM VMIO ISNS TSNS VIO VIO VGP_TP VRT SYSRST VIR PWRKY MI+ MI- SL S MIIS0 MI- MI+ M_RX_N_P M_NT_H R_MI+ R_MI- R_R_R R_R_L R_P R_N GPIO/UIO_P_N T/GPIO/R_H TN TP TN TP TN TP TN TP TN0 TP0 LM_RST SI_T UX VT- VT- VT+ VT+ T_ON VUS GPIO0/RST_TP US_M US_P T_TP 0 ONNTIL RWN Y HK Y PROJT SIZ SHT of TITL TV VR <T HR> <V.00>