Revision History. EFM32PG12 Pearl Gecko STK. Description. Board Function Page. EFM32PG12 Pearl Gecko Starter Kit. Title Page 1.

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1 EFMPG Pearl Gecko STK oard Function Page Title Page User Interface Rev. 00 History escription Initial release EFM Signal ssignments 0 hanged to rev of EFM EFM Power EFM I/O STK oard ontroller dvanced Energy Monitor ebug Interface oard ontroller 9 Power & Misc 0 P P0 / EFMPG STK esigned: pproved: HEL OM oc No: <age ode> esign reated ate: Wednesday, ecember 0, 00 EFMPG Pearl Gecko Starter Kit Title Page ocument number R0 reated ate Saturday, March, Modified ate Tuesday, January 0, 0 of 0

2 LESENSE L-Sensor _L_EXITE LES_L_SENSE R9 0 GN 99 00N R9 R9 K 9 0P R9 L00 90UH User LEs R0 K UIF_LE0 R0 K UIF_LE LE0 YELLOW GN GN LE00 YELLOW EXP Header EXP_HEER[..] VMU P00 EXP_HEER P9 P EXP_HEER EXP_HEER P9 P EXP_HEER EXP_HEER P P EXP_HEER EXP_HEER9 P 9 0 P9 EXP_HEER0 EXP_HEER P P0 EXP_HEER EXP_HEER P P EXP_HEER EXP_HEER P P0 EXP_HEER _I_SL 9 0 _I_S V V HEER_X0_.MM_HOR_SM GN User Pushbuttons _UIF_UTTON0 _UIF_UTTON UIF_UTTON0 UIF_UTTON VMU R0 M 00 N GN GN R0 M 0 N SW00 SW0 R00 0 R0 0 GN GN UIF_TOUH[..0] Touch Pads UIF_TOUH0 UIF_TOUH UIF_TOUH UIF_TOUH T TOUH SLIER EXP-Header Functionality GN P9.. P9 P US_TX #0 I_S# 9 P US_RX #0 I_SL# P US_LK #0 P US_S #9 P I0_SL# 9 Reserved for EXP oard Identification Reserved for EXP oard Identification VMU P P P 0 P9 P0 P P0 V 0 V US_TX # US_RX # US_LK # US_S # LEU0_TX # LEU0_RX # I0_S# Memory L-TFT isplay & Multiplexer VMU V Relative Humidity & Temperature Sensor _ISP_PWR_EN R0 00K GN R GN R09 M U0 N N NO NO IN IN TS9 OM OM _ISP_VILLE VISP R0 M xmm M xmm SENSOR_I_SL SENSOR_I_S SENSOR_ENLE VMU R9 U0 OM 9 OM 0 OM OM IN IN IN IN TS NO NO NO NO V_SENSOR R K R K U0 SL S GN Si0-0 V N N V_SENSOR 0 00N _ISP_SLK _ISP_MOSI _ISP_S _ISP_OM EFM_ISP_SLK EFM_ISP_MOSI EFM_ISP_S EFM_ISP_OM EFM_ISP_ENLE EFM_ISP_ENLE 0 ISP_TRL VISP EFM GN R0 0M U00 N N 9 N N NO NO NO NO IN- IN- VMU TS9 _ISP_PWR_EN OM OM OM OM _ISP_VILLE The EFM always controls ownership of the display using the EFM_ISP_ENLE signal. 0 TP0 TP TP TP GN R0 0M NM GN 0 00N ISP_SLK ISP_MOSI ISP_S ISP_OM GN 0 00N GN GN P0 0 9 SLK SI SS EXTOMIN ISP V V EXTMOE VSS VSS XFL-0-_MEML U00 GN TS9 0 GN ISP 0 00N GN LS0H0 U0 0 GN 00N TS9 GN EFMPG STK esigned: HEL OM oc No: GN R 0M pproved: esign reated ate: Wednesday, ecember 0, 00 Isolation GN GN U0 0 GN 00N TS GN GN EFMPG Pearl Gecko Starter Kit User Interfaces ocument number R0 reated ate Friday, October, 0 0 Modified ate Friday, ecember, 0 of 0

3 P onnections MU_P[9..0] P onnections MU_P[..] P onnections MU_P[..0] MU_P0 MU_P MU_P MU_P MU_P MU_P MU_P MU_P MU_P MU_P9 MU_P MU_P0 MU_P MU_P MU_P0 MU_P MU_P MU_P MU_P MU_P MU_P9 MU_P0 MU_P US0_TX#0 US0_RX#0 US0_TS#0 US0_RTS#0 LES_H US_TX# US_RX# US_LK# US_S# US_TX# US_LK# PNT0_S0IN# I0_S# I0_SL# LFXTL_P LFXTL_N EFM_ISP_MOSI EFM_ISP_SLK VOM_TX VOM_RX VOM_TS VOM_RTS LES_L_SENSE VOM_ENLE EXP_HEER EXP_HEER EXP_HEER EXP_HEER0 MU_P US_TX#0 EXP_HEER MU_P US_RX#0 EXP_HEER9 US_LK#0 EXP_HEER SENSOR_ENLE UIF_TOUH0 UIF_TOUH UIF_TOUH UIF_TOUH EXP_HEER EXP_HEER EXP_HEER SENSOR_I_SL SENSOR_I_S EXP_HEER[..] EXP_HEER[..] UIF_TOUH[..0] EXP_HEER[..] reakout onnections MU_P[9..0] MU_P[..] MU_PF[..0] MU_P0 MU_P MU_P MU_P MU_P MU_P MU_P9 MU_P0 MU_P MU_P MU_P V MU_PF MU_PF MU_PF MU_PF MU_PF MU_PF9 MU_PF0 MU_PF MU_PF MU_PF MU_PF MU_PF V VMU GN V J0 NM J VMU GN V MU_P MU_P MU_P MU_P MU_P MU_P MU_P MU_P MU_P MU_PK0 MU_PK MU_PK V OEN MUG_RESET MU_PF0 MU_PF MU_PF MU_PF MU_PI0 MU_PI MU_PI MU_PI MU_PJ MU_PJ V MU_P[..0] MU_P[..] MU_PK[..0] V GN MU_PF[..0] PF PF PF PF MU_PI[..0] PF PF9 PF0 MU_PJ[..] PF PF PF PF PF GN V reakout header labels: VMU VMU GN GN P0 P P P P P P P P P P P P9 P P0 P P P P PK0 P PK N PK GN GN V V V GN EN RST PF0 PF PF PF PI0 PI PI PI PJ PJ GN V GN NM GN P onnections MU_P[..] MU_P MU_P9 MU_P0 MU_P US_S#9 PNT0_SIN# EXP_HEER EXP_HEER EXP_HEER EXP_HEER EXP_HEER[..] MU_P MU_P MU_P MU_P 0_OUTLT#0 LETIM0_OUT# US_S#9 _L_EXITE EFM_ISP_OM EFM_ISP_S EFM_ISP_ENLE PF onnections MU_PF[..0] MU_PF0 MU_PF MU_PF MU_PF MU_PF MU_PF MU_PF MU_PF G_SWLK#0 G_SWIOTMS#0 G_SWO#0 / G_TO#0 G_TI#0 MUG_TK_SWLK MUG_TMS_SWIO MUG_TO_SWO MUG_TI UIF_LE0 UIF_LE UIF_UTTON0 UIF_UTTON MU_PF MU_PF9 MU_PF0 MU_PF MU_PF MUG_TRE0 MUG_TRE MUG_TRE MUG_TRE MUG_TRELK MUG_TRE[..0] esigned: pproved: HEL OM oc No: <age ode> esign reated ate: Wednesday, ecember 0, 00 EFMPG Pearl Gecko Starter Kit EFM Signal ssignments ocument number R0 0 reated ate Modified ate Friday, October, 0 Thursday, ecember, 0 of 0

4 Power Select Switch: EM/T EFM Power and ecoupling TP09 EM_VMU_OUT TP MUG_RESET P00 OIN_ELL + ST NM Labels: T GN SW0 PT_SW_SM Q0 NTS0 R9 K TP VMU TP0 0 00N GN GN RESET Pushbutton R9 0 VMU SW0 PTS0 OEN GN U U 0N 0N 0 00N 0N 0N M L0 U EFMPG00F0 Reset RESETn OEN I/O Supply 0 F IOV0 F IOV M IOV IOV / regulator input VREGV / regulator output VREGSW L U 0 U 0 0 U 0U GN GN VMU SWITH POS EM T GN GN MOE ESRIPTION GN EM Enabled, VMU sourced from external.v LO powered by US V supply EM isabled, VMU sourced from coin-cell battery or external power supply VMU GN L00 F0W GN R00 R GN GN GN GN 0 0 0U GN GN 0N GN 0N J J M N N N N N N N nalog supply V0 V V Unused pins N N N N N N N N igital supply V 0 Regulator decoupling EOUPLE 9 GN 0 00N GN 09 U GN U EFMPG00F0 E E E E E9 F F F F F9 G G G G G9 Ground VREGVSS0 VREGVSS VREGVSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS9 VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS9 VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS9 VSS0 VSS VSS VSS H H H H H9 J J J J J9 K L M M M M M M N GN GN EFMPG Pearl Gecko Starter Kit esigned: pproved: HEL OM oc No: <age ode> esign reated ate: Wednesday, ecember 0, 00 EFM Power ocument number R0 reated ate Friday, October, 0 0 Modified ate Tuesday, January 0, 0 of 0

5 EFM PG MU MU_P[9..0] MU_P[..] MU_P[..0] MU_P0 MU_P MU_P MU_P MU_P MU_P MU_P MU_P MU_P MU_P9 MU_P MU_P MU_P MU_P9 MU_P0 MU_P MU_P MU_P MU_P MU_P MU_P0 MU_P MU_P MU_P MU_P MU_P MU_P MU_P MU_P MU_P9 MU_P0 MU_P HFXTL_P HFXTL_N U EFMPG00F0 M L P0 L P K P K P J P J P J P H P H P P9 I/O F E P E P P P9 P0 P P P 0 P / LFXTL_N P / LFXTL_P P0 P P P P 9 P P P P P9 P0 P L K HFXO HFXTL_P HFXTL_N MU_P[..] MU_PF[..0] MU_PI[..0] MU_PJ[..] MU_PK[..0] MU_P MU_P9 MU_P0 MU_P MU_P MU_P MU_P MU_P MU_PF0 MU_PF MU_PF MU_PF MU_PF MU_PF MU_PF MU_PF MU_PF MU_PF9 MU_PF0 MU_PF MU_PF MU_PF MU_PF MU_PF MU_PI0 MU_PI MU_PI MU_PI MU_PJ MU_PJ MU_PK0 MU_PK MU_PK U EFMPG00F0 I/O N9 M9 P N0 P9 M0 P0 N P M P N P N P P PF0 PF PF G PF G PF H PF H PF PF PF PF9 PF0 PF PF PF E PF PF G G PI0 G PI F PI PI PJ PJ E E PK0 F PK PK High Frequency lock Low Frequency lock HFXTL_P LFXTL_P X 0.0MHz HFXTL_N X LFXTL_N EFMPG Pearl Gecko Starter Kit GN.kHz esigned: pproved: HEL OM oc No: <age ode> esign reated ate: Wednesday, ecember 0, 00 EFM I/O ocument number R0 reated ate Monday, November, 0 0 Modified ate Tuesday, January 0, 0 of 0

6 oard ontroller Functional lock H VOM_TX VOM_RX VOM_TS VOM_RTS VOM_RX VOM_TX VOM_#RTS VOM_#TS VOM EM EM_VMU_OUT EM_VMU_OUT VOM_ENLE _UIF_UTTON0 _UIF_UTTON VOM_ENLE User Interface to UIF_P0 UIF_P EUG MUG_TMS_SWIO_ MUG_TK_SWLK_K MUG_TI_PS MUG_RESET_KPS MUG_TO_SWO MUG_TRE[..0] MUG_TRELK MUG_TMS_SWIO MUG_TK_SWLK MUG_TI MUG_RESET MUG_TO_SWO MUG_TRE[..0] MUG_TRELK EXP oard Identification Output OUT _I_SL _I_S EXP_I_SL EXP_I_S IS TRLMU_SPI_#S TRLMU_SPI_MOSI TRLMU_SPI_SK TRLMU_IS_MK MU STK Platform oard ontroller GPIO _IO[..0] _IO[..0] _IO0 _IO _IO _ISP_MOSI _ISP_SLK _ISP_S _IO _ISP_VILLE _IO9 _IO0 _ISP_PWR_EN _ISP_OM EFMPG Pearl Gecko Starter Kit esigned: pproved: HEL OM oc No: <age ode> esign reated ate: Wednesday, ecember 0, 00 STK oard ontroller ocument number R0 reated ate Friday, October, 0 0 Modified ate Thursday, ecember, 0 of 0

7 MU power regulator EM_VMU_ENLE V 0 00N GN GN 0 0U R00 0K GN U0 IN OUT OUT SET SHN FULT 9 GN GN_HET LP9IL-J 0 N GN GN TP00 R0 0K VMU_R R0 VMU_S TP0 R 00 R0 Sense Resistor 0K 0U L0 GN GN F0W 0 00N 0 leeder Resistor GN U0 R0 0K 00N GN TS 0 00N U00 E n.c. Z Y NXVG U00 V GN NXVG EM_TRL[..0] EM_VMU_OUT TP0 U0 OM 9 OM 0 OM OM EM_TRL0 EM_TRL IN EM_TRL IN EM_TRL IN IN TS NO NO NO NO EM alibration TP R0 K TP R0 K TP R0 K TP GN R0 M EM_TRL 0x 0x 0x 0x 0x alibration urrent.0 u 00 u 0 u 0 u.0 m GN GN GN GN V L00 F0W R VS GN 0U 0 00N GN R09 K 00N MU current sense VMU_R GN U0 -INS -INF VREG V- 9 V- V- (HET) LT0 IN+ OUT R K VMU_S GN R0 K GN 9 0N NM R00 K R00 K GN GN 00 N 00 N GN R R00 K + - U000 R009 K U P 00 R00 R R00 R GN GN TP N TP0 00N EM_SENSE_URRENT_RNGE EM_SENSE_URRENT_RNGE MU Voltage Sense VMU_UF R K TP0 R9 00K N EM_SENSE_VOLTGE GN GN GN U000 V- GN 0 00N R 0U R L00 F0W V GN R00 K 0P /H MU STK Platform esigned: pproved: OM oc No: <age ode> esign reated ate: Monday, May, 0 EFMPG Pearl Gecko Starter Kit dvanced Energy Monitor ocument number R0 reated ate Tuesday, May, 0 0 Modified ate Thursday, ecember, 0 of 0

8 V R00 00K GN TPJ P MUG_TRELK MUG_TRE[..0] MUG_RESET_KPS MUG_TMS_SWIO_ MUG_TK_SWLK_K MUG_TO_SWO MUG_TI_PS H_VTRGET H_TMS_SWIO_ H_TK_SWLK_K H_TO_SWO H_TI H_#RESET 0 PESV0FUF GN MUG_TRELK MUG_TRE0 MUG_TRE MUG_TRE MUG_TRE R 0M H_VTRGET 00 VES0-HNH R 0 TPJ TPJ TPJ TPJ0 TPJ U0 OM 9 OM 0 OM OM IN IN IN IN TPJ TS NO NO NO NO 9 GN EUG_EXT_LE_TTH H_VTRGET R M R 00K H_VTRGET VMU_UF Q00 MNL0WK LV0 Z 9 Z 0 Z Z LV0 Z 9 Z 0 Z Z LV0 Z 9 Z 0 Z Z U00 Y Y Y Y E E E E U0 Y Y Y Y E E E E U0 Y Y Y Y E E E E VTRGET VTRGET TMS_SWIO TK_SWLK TO_SWO TI #RESET EUG_HEER_EN MU_SW_EN R0 K VTRGET V R0 R R0 K V R0 K VTRGET RP00 R RP0 R R09 00K NM LVG U0 R0 0 GN U0 LVG LVG U0 LVG U09 GN LVG U0 GN U0 0 9 LVG U09 LVT 9 0 OE IR GN EUG_H_SW_ENLE EUG_MU_SW_ENLE EUG_MU_ISOLTE_#EN EUG_TMS_SWIO_#OE EUG_TMS_SWIO_OUT EUG_TK_SWLK_OUT EUG_TK_SWLK_#OE EUG_TI_OUT EUG_TI_#OE EUG_TMS_SWIO_IN EUG_TK_SWLK_IN EUG_TO_SWO_IN EUG_TI_IN EUG_#RESET_IN EUG_RESET_OUT EUG_RESET_#OE GN Power & ecoupling L0 VTRGET VTRGET 0 00N V U0 TS Mode EUG_MU_SW_ENLE EUG_H_SW_ENLE EUG_UF_#OE ISOLTE_#EN H_VTRGET VTRGET ebug Out External voltage External voltage MU ebug 0 0 isconnected VMU ebug In VMU VMU ebug Off GN U0 GN LVT 00 00N V V P V GN 0 GN GN 00N GN V L00 F0W GN 0 GN U00 V U0 GN V LVG 00N GN LV0 GN GN N GN GN 0 U09 GN U0 V V LVG 00N GN LV0 GN GN F0W GN N U0 V 9 GN 00N LV0 GN 0 00N V GN U0 V GN LVG GN /H MU STK Platform esigned: pproved: OM oc No: <age ode> esign reated ate: Monday, May, 0 VTRGET ocument number R0 reated ate Monday, May, 0 R90 00K R9 00K GN EUG_EXT_V_TRGET EFMPG Pearl Gecko Starter Kit ebug Interface 90 0N 0 Modified ate Thursday, ecember, 0 of 0

9 Indicators: Status V ebug out J-Link V V R90 K R99 K R900 K R90 K0 MU R G LE90 LE_G_R LE900 YELLOW LE90 LUE EUG_RESET_OUT EUG_TI_OUT EUG_TMS_SWIO_OUT EUG_TK_SWLK_OUT EUG_TI_IN EUG_TMS_SWIO_IN EUG_TK_SWLK_IN EUG_#RESET_IN EUG_TO_SWO_IN EUG_RESET_OUT EUG_TI_OUT EUG_TMS_SWIO_OUT EUG_TK_SWLK_OUT EUG_TI_IN EUG_TMS_SWIO_IN EUG_TK_SWLK_IN EUG_#RESET_IN EUG_TO_SWO_IN LE_STTUS_R LE_STTUS_G LE_EUG_OUT LE_JLINK LE_STTUS_R LE_STTUS_G LE_EUG_OUT LE_JLINK EUG_EXT_V_TRGET EUG_EXT_LE_TTH EUG_EXT_V_TRGET EUG_EXT_LE_TTH UIF_P UIF_P0 UIF_P UIF_P0 EUG_TI_#OE EUG_TK_SWLK_#OE EUG_TMS_SWIO_#OE EUG_MU_ISOLTE_#EN EUG_RESET_#OE EUG_TI_#OE EUG_TK_SWLK_#OE EUG_TMS_SWIO_#OE EUG_MU_ISOLTE_#EN EUG_RESET_#OE J-Link US Port P0 WR_OM_US_MINI_ 9 TPJ Place these TPs close to US header EUG_MU_SW_ENLE EUG_H_SW_ENLE EM_VMU_ENLE EM_SENSE_VOLTGE EM_SENSE_URRENT_RNGE EM_SENSE_URRENT_RNGE EM_TRL[..0] EUG_MU_SW_ENLE EUG_H_SW_ENLE EM_VMU_ENLE EM_SENSE_VOLTGE EM_SENSE_URRENT_RNGE EM_SENSE_URRENT_RNGE EM_TRL[..0] EXP_I_S EXP_I_SL OUT REF_OR_I_S REF_OR_I_SL EXP_I_S EXP_I_SL OUT GN GN GN TPJ L00 FH V _URT_RX _URT_TX _URT_#RTS _URT_#TS _URT_RX _URT_TX _URT_#RTS _URT_#TS TRLMU_SPI_#S TRLMU_SPI_MOSI TRLMU_SPI_SK TRLMU_IS_MK TRLMU_SPI_#S TRLMU_SPI_MOSI TRLMU_SPI_SK TRLMU_IS_MK TPJ TPJ 00 IP0Z TPH999 USP USM OOTLOER_HLT ootloader Halt pin USP USM OOTLOER_HLT ontrol MU _EXT_HEER_ENLE _IO[..0] _EXT_HEER_ENLE _IO[..0] GN /H MU STK Platform EFMPG Pearl Gecko Starter Kit esigned: pproved: OM oc No: <age ode> esign reated ate: Monday, May, 0 oard ontroller ocument number R0 reated ate Wednesday, May, 0 0 Modified ate Thursday, ecember, 0 9 of 0

10 V V Regulator Virtual OM Port Interface VOM_RX VOM_TX VOM_#RTS VOM_#TS VOM_ENLE R0 0M Isolation Level Shift U0 TS GN U LVG OM NO 9 OM NO 0 OM NO OM NO V IN IN IN GN R IN K GN R K U0 LVG TPJ0 U0 LVG TPJ0 _URT_RX _URT_TX _URT_#RTS V GN 00 00N GN 0 0U R00 0K GN VMU Voltage Mirror U00 IN LP9IL-J OUT OUT SET SHN FULT 9 GN GN_HET 0 N GN GN R0 0K R0 0K TPJ00 GN 0 0U V M GN M M GN REF_VOM_RX REF_VOM_TX REF_VOM_#RTS REF_VOM_#TS 9 0 LV0 Z Z Z Z U0 Y Y Y Y E E E E V GN R 0K U LVG _EXT_HEER_ENLE _URT_#TS VMU Isolation Q0 MNL0 R K 00N GN Voltage uffering U0 + - MP00T R 0K R9 R K V Q0 L0 F0W WTG 0U VMU_UF R R 0 0U U0 V GN MP00T GN GN GN V U0 V 00N GN LV0 GN EXTERNL OR GN U0 0 00N GN TS GN GN GN U GN V LVG VMU_UF GN 00N GN onnector for external reference designs boards U0 GN V LVG VMU_UF GN 0 00N Power Supply for nalog Switches The US VUS voltage is used to bias these transistors, turning the P-hannel MOSFETs (Q00) off, and the N-hannel MOSFETs (Q0) on. J-Link US able onnected isconnected PMOS State Off ON NMOS State ON OFF.V VMU VMU_SENSE VMU Isolated V 09 U GN U0 IN OUT EN GN TLV0 0 U GN GN VMU R VMU_EXT REF_OR_I_SL REF_OR_I_S V V VMU_EXT P REF_VOM_RX REF_VOM_TX REF_VOM_#RTS REF_VOM_#TS V R R GN R 0K GN 0 N VMU Q00 SS Q00 SS TPJ0 Q0 MNL0 VMU V R NM R GN HEER_X0_.MM_SM /H MU STK Platform NM EFMPG Pearl Gecko Starter Kit 0 VES0-HNH GN 9 esigned: pproved: OM oc No: <age ode> esign reated ate: Monday, May, 0 Power & Misc ocument number R0 reated ate Monday, May, 0 0 Modified ate Thursday, ecember, 0 0 of 0

11 EUG_RESET_OUT EUG_TI_OUT EUG_TMS_SWIO_OUT EUG_TK_SWLK_OUT OUT EUG_TI_IN EUG_TMS_SWIO_IN EUG_TK_SWLK_IN EUG_#RESET_IN EUG_TO_SWO_IN EUG_EXT_V_TRGET EUG_EXT_LE_TTH USM USP R90 R EUG_MU_SW_ENLE R90 R 900 GN GN EUG_TI_#OE EUG_TK_SWLK_#OE EUG_TMS_SWIO_#OE EUG_MU_ISOLTE_#EN EUG_RESET_#OE EEPROM_WP TRLMU_I_SL TRLMU_I_S TRLMU_SPI_#S TRLMU_SPI_SK TRLMU_SPI_MISO TRLMU_SPI_MOSI EM_SENSE_VOLTGE EM_SENSE_URRENT_RNGE EM_SENSE_URRENT_RNGE TPJ90 TPJ9 TPJ9 TPJ9 TPJ9 TPJ9 P V 90 P V_SENSE V_SENSE V_SENSE R90 K TRL_MU_#TRST TRL_MU_TI TRL_MU_TMS_SWIO TRL_MU_TK_SWLK TRL_MU_TO_SW TEST_MOE US_R0 TRL_MU_TX TRL_MU_RX OOTLOER_HLT US_R US_R TPJ90 TPJ909 TPJ900 TPJ90 TPJ90 TPJ90 TPJ9 U900 ontrol MU G H P0 / WKUP / USRT_TS / _IN0 / TIM_H_ETR / TIM_H / TIM_ETR J P / USRT_RTS / _IN / TIM_H / TIM_H K P / USRT_TX / _IN / TIM_H / TIM_H P / USRT_RX / _IN / TIM_H / TIM_H PORT G H P / SPI_NSS / _OUT / USRT_K / _IN J P / SPI_SK / _OUT / _IN K P / SPI_MISO / TIM_KIN / _IN / TIM_H [TIM_KIN] 9 P / SPI_MOSI / TIM_HN / _IN / TIM_H [TIM_HN] 9 P / USRT_K / TIM_H / MO 0 P9 / USRT_TX / TIM_H 0 P0 / USRT_RX / TIM_H 0 P / USRT_TS / NRX / TIM_H / USM 0 P / USRT_RTS / NTX / TIM_ETR / USP 9 P / JTMS-SWIO P / JTK-SWLK P / JTI J K P0 / _IN / TIM_H / TIM_HN G P / _IN9 / TIM_H / TIM_HN P / OOT P / JTO / TRESWO / SPI_SK / IS_K [TIM_H/ SPI_SK] P / JNTRST / SPI_MISO [TIM_H/ SPI_MISO] P / I_SMI / SPI_MOSI / IS_S [TIM_H/ SPI_MOSI] P / I_SL / TIM_H [USRT_TX] P / I_S / FSM_NV / TIM_H [USRT_RX] P / TIM_H / SIO_ [I_SL/ NRX] J P9 / TIM_H / SIO_ [I_S/ NTX ] K P0 / I_SL / USRT_TX [TIM_H] K P / I_S / USRT_RX [TIM_H] J P / SPI_NSS / IS_WS / I_SMI / USRT_K / TIM_KIN H P / SPI_SK / IS_K / USRT_TS / TIM_HN G P / SPI_MISO / TIM_HN / USRT_RTS P / SPI_MOSI / IS_S / TIM_HN F F P0 / _IN0 E P / _IN F P / _IN G P / _IN H P / _IN F0 P / _IN E0 P / IS_MK / TIM_H / SIO_ [TIM_H] F9 P / IS_MK / TIM_H / SIO_ [TIM_H] E9 P / TIM_H / SIO_0 [TIM_H] 9 P9 / TIM_H / SIO_ [TIM_H] P0 / URT_TX / SIO_ [USRT_TX] P / URT_RX / SIO_ [USRT_RX] P / URT_TX / SIO_K [USRT_K] P / TMPER-RT P / OS_IN P / OS_OUT PORT PORT _IO[..0] EUG_H_SW_ENLE EM_VMU_ENLE EM_TRL[..0] _IO _IO LE_JLINK LE_EUG_OUT _URT_#TS _URT_#RTS _URT_TX _IO _URT_RX _IO0 _IO _IO _IO _UIF_P_ON _EXT_HEER_ENLE _IO0 _IO _IO _IO9 _IO _I_EXP_EN GN _UIF_P0 _UIF_P LK_SEL OR_REV0 OR_REV _I_EXP_EN EM_TRL0 EM_TRL EM_TRL EM_TRL E K9 J9 H9 G9 K0 J0 H0 G0 E H J K G H J K G H U900 P0 / OS_IN / FSM_ [NRX] P / OS_OUT / FSM_ [NTX] P / TIM_ETR / URT_RX / SIO_M P / FSM_LK [USRT_TS] P / FSM_NOE [USRT_RTS] P / FSM_NWE [USRT_TX] P / FSM_NWIT [USRT_RX] P / FSM_NE / FSM_NE [USRT_K] P / FSM_ [USRT_TX] P9 / FSM_ [USRT_RX] P0 / FSM_ [USRT_K] P / FSM_ [USRT_TS] P / FSM_ [USRT_RTS/ TIM_H] P / FSM_ [TIM_H] P / FSM_0 [TIM_H] P / FSM_ [TIM_H] PE0 / TIM_ETR / FSM_NL0 PE / FSM_NL PE / TREK / FSM_ PE / TRE0 / FSM_9 PE / TRE / FSM_0 PE / TRE / FSM_ PE / TRE / FSM_ PE / FSM_ [TIM_ETR] PE / FSM_ [TIM_HN] PE9 / FSM_ [TIM_H] PE0 / FSM_ [TIM_HN] PE / FSM_ [TIM_H] PE / FSM_9 [TIM_HN] PE / FSM_0 [TIM_H] PE / FSM_ [TIM_H] PE / FSM_ [TIM_KIN] Production test: 0MHz reference clock input TPJ9 ontrol MU TPJ9 GN V OOTLOER_HLT OR_REV R9 K NM LE_STTUS_R LE_STTUS_G OR_REV0 R9 K NM ontrol MU Power & ypass 90 P X P GN R9 MHz GN U900 V TP90 OS_IN OS_OUT VT 90 00N TPJ9 V R9 K0 LE90 RE L900 F0W V GN R9 0K 9 00N R90 R 90 0U GN 90 0N TRLMU_EUG_#RESET 909 0N _VREF 9 00N GN GN K G V VSS J H VREF+ VREF- F E R9 N OOT0 NRST V_ V_ V_ V_ V_ VSS_ VSS_ VSS_ VSS_ VSS_ ontrol MU F F F F 90 00N E E E E GN N 00N 9 00N 9 00N V 9 0U GN /H/MU ontrol MU esigned: pproved: OM oc No: <age ode> esign reated ate: Monday, May, 0 EFMPG Pearl Gecko Starter Kit ontrol MU ocument number R0 reated ate Wednesday, February, 0 0 Modified ate Wednesday, October, 0 of 0

12 V V TRLMU EEPROM reference voltage TPJ90 _VREF 9 0U V R 0 0 LM00IM-.0 TRLMU_I_S TRLMU_I_SL _UIF_P0 _UIF_P _I_EXP_EN _UIF_P_ON V R0 K R 00K V R0 K R 00K GN U0 S SL 0 U0 OM 9 OM 0 OM OM IN IN IN IN WP 0 V NO NO NO NO R09 0K EEPROM_WP TPJ0 TPJ TPJ TPJ EXP_I_S EXP_I_SL UIF_P0 UIF_P GN GN R 00K R0 00K TS GN GN V GN U0 V VSS N GN U0 0 GN 0N TS GN GN POWER SENSE TRLMU SERIL FLSH V R0 00K V_SENSE R 00K TP9 V_SENSE TRLMU_SPI_MISO TRLMU_SPI_MOSI TRLMU_SPI_#S TRLMU_SPI_SK U90 Q S HOL W MPX V V R0 00K R0 00K GN 0 00N V_SENSE R 00K GN 00N U90 V VSS MPX V 90 0N R0 00K GN 0 00N GN /H/MU ontrol MU EFMPG Pearl Gecko Starter Kit esigned: pproved: OM oc No: <age ode> esign reated ate: Monday, May, 0 oard ontroller Misc ocument number R0 reated ate Wednesday, February, 0 0 Modified ate Friday, October, 0 of 0

EFM32 Tiny Starter Kit. EFM32 Tiny Starter Kit. Revision History. Page. Board Function. Rev. Description. Title Page 1 A00.

EFM32 Tiny Starter Kit. EFM32 Tiny Starter Kit. Revision History. Page. Board Function. Rev. Description. Title Page 1 A00. oard Function Page Title Page User Interface Rev. 00 History escription Initial Release Signal ssignments EFM I/O 0 Swapped L-com pins dded Resistor R0 EFM Power 0 hanged R, R to lower values L Power +