EFM32 Tiny Starter Kit. EFM32 Tiny Starter Kit. Revision History. Page. Board Function. Rev. Description. Title Page 1 A00.
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1 oard Function Page Title Page User Interface Rev. 00 History escription Initial Release Signal ssignments EFM I/O 0 Swapped L-com pins dded Resistor R0 EFM Power 0 hanged R, R to lower values L Power + Misc 0 attery polarity protection dded frequency reference testpoint EM 0 hanged L part number ebug Interface ontrol MU P P0 esigned: pproved: G OM oc No: <age ode> esign reated ate: Wednesday, ecember 0, 00 Title Page ocument number 0 R0 reated ate Modified ate Saturday, March, 00 Monday, October 0, 0 of
![reakout onnections Test Specific onnections User pushbuttons MU_P[..] VMU MU_P[..] MU_P MU_P MU_P MU_P MU_P TP0 TP TP TP TP MU_P[.](/docs-images/88/117488404/images/2-0.jpg ".0] No onnect MU_P MU_P MU_P MU_P TP TP TP TP UIF_P0 UIF_P R 0 R SW0 SW R0 R GN MU_P[..] MU_P MU_P TP TP TP TP TP TP TP Touch slider GN GN Photo Transistor GN MU_P[..] MU_P MU_P X.")
2 reakout onnections Test Specific onnections User pushbuttons MU_P[..] VMU MU_P[..] MU_P MU_P MU_P MU_P MU_P TP0 TP TP TP TP MU_P[..0] No onnect MU_P MU_P MU_P MU_P TP TP TP TP UIF_P0 UIF_P R 0 R SW0 SW R0 R GN MU_P[..] MU_P MU_P TP TP TP TP TP TP TP Touch slider GN GN Photo Transistor GN MU_P[..] MU_P MU_P X.MM TP TP TP TP TP TP TP UIF_SLIER[..0] T TOUH SLIER Q0 TEMT00FX0 LES_LIGHT_EXITE LES_LIGHT_SENSE MU_P MU_P MU_P J0 TP UIF_SLIER0 UIF_SLIER UIF_SLIER UIF_SLIER R K GN MU_P[..0] MU_P0 MU_P MU_P MU_P MU_P MU_P MU_P MU_P MU_P TP TP TP TP TP TP TP TP TP Power VMU V V GN TP TP TP TP TP TP TP TP TP TP TP TP EXP port MU_P[..] MU_P[..] MU_P[..] MU_P MU_P MU_P MU_P MU_P MU_P MU_P MU_P GN VMU V P0 0 V HEER_X_.MM_HOR_SM MU_P0 MU_P MU_P MU_P MU_P[..0] OPMP EXP_HEER_P EXP_HEER_P EXP_HEER_P MU_P[..0] EXP ommunication SPI I URT LEURT MOSI-P0 MISO-P LK-P S-P S-P SL-P TX-P0 RX-P TX-P RX-P LESENSE L-Sensor User LE UIF_LE0 R K _L_EXITE R R LE0 YELLOW LES_L_SENSE GN 0N R K 0P R L0 0UH esigned: pproved: G OM oc No: <age ode> esign reated ate: Wednesday, ecember 0, 00 GN User Interfaces ocument number 0 R0 reated ate Modified ate Saturday, March, 00 Monday, October 0, 0 of
3 P onnections P onnections OPMP onnection Footprint MU_P[..0] L_P[..0] MU_P[..] L_P[..] MU_P[..] MU_P0 MU_P MU_P MU_P MU_P MU_P MU_P MU_P MU_P MU_P MU_P L_P0 L_P L_P L_P L_P L_P L_P L_P L_P L_P L_P L_P[..] MU_P[..] MU_P MU_P MU_P MU_P MU_P MU_P MU_P MU_P MU_P MU_P L_P L_P L_P L_P LFXTL_P LFXTL_N UIF_P _L_EXITE HFXTL_P HFXTL_N R0 K GN R EXP_HEER_P OPMP_NEG 0 0N R K OPMP_OUT R OPMP_POS EXP_HEER_P EXP_HEER_P EFM Opamp P onnections P onnections R K MU_P[..] MU_P MU_P MU_P MU_P UIF_SLIER0 UIF_SLIER UIF_SLIER[..0] LES_LIGHT_SENSE LES_L_SENSE MU_P[..0] MU_P MU_P MU_P MU_P MU_P OPMP_NEG OPMP_POS OPMP_OUT UIF_LE0 EFM TX EFM RX GN R K MU_P[..] UIF_SLIER[..0] LES_LIGHT_EXITE MU_P MU_P UIF_SLIER UIF_SLIER MU_P UIF_P0 MU_P EFM EN MU_P MUG_TO_SWO PE onnections PF onnections MU_PE[..] L_PE[..] MU_PF[..0] MU_PF0 MU_PF MUG_TK_SWLK MUG_TMS_SWIO MU_PE MU_PE MU_PE MU_PE MU_PE MU_PE MU_PE MU_PE MU_PE MU_PE MU_PE MU_PE L_PE L_PE L_PE L_PE L_PE L_PE L_PE L_PE L_PE L_PE L_PE L_PE MU_PF MU_PF MU_PF MU_PF L_PF L_PF L_PF L_PF L_PF[..] esigned: pproved: G OM oc No: <age ode> esign reated ate: Wednesday, ecember 0, 00 Signal ssignments ocument number 0 R0 reated ate Modified ate Friday, January, 0 Monday, October 0, 0 of
4 MU_P[..0] MU_P[..] MU_P[..] MU_P[..] MU_P[..] MU_P[..] MU_P0 MU_P MU_P MU_P MU_P MU_P MU_P MU_P MU_P MU_P MU_P U0 P0, L_SEG, TIM0_0 #0//, I0_S #0, LEU0_RX #, PRS_H0 #0, GPIO_EMWU0 P, L_SEG, TIM0_ #0/, I0_SL #0, MU_LK #0, PRS_H #0 P, L_SEG, TIM0_ #0/, MU_LK0 #0 P, L_SEG, LES_LTEX #0 P, L_SEG, LES_LTEX #0 P, L_SEG, LES_LTEX #0 P, L_SEG, GPIO_EMWU P, L_P_P P, L_P_N P, L_EXT P, L_SEG MU_P MU_P MU_P MU_P MU_P MU_P MU_P MU_P MU_P MU_P P, L_SEG0, L_OM P, L_SEG, L_OM P, L_SEG, L_OM P, L_SEG, L_OM P, LFXTL_P, TIM_0 #, US0_TX #, US_LK #0 P, LFXTL_N, TIM_ #, US0_RX #, US_S #0 P, 0_OUT0 #0, OPMP_OUT0 #0, TIM_ #, LETIM0_OUT0 # P, 0_OUT #0, OPMP_OUT #0, LETIM0_OUT # P, HFXTL_P, LEU0_TX #, US0_LK #/ P, HFXTL_N, LEU0_RX #, US0_S #/ MU_P MU_P MU_P MU_P MU_P MU_P MU_P MU_P P, 0_P0 #0, OPMP_P0 #0, MP0_H #0, LETIM0_OUT0 #, LES_H #0 P, 0_N0 #0, OPMP_N0 #0, MP0_H #0, LETIM0_OUT #, LES_H #0 P, MP0_H #0, I0_S #, LES_H #0 P, MP0_H #0, I0_SL #, LES_H #0 P, 0_OUTLT #0, OPMP_OUTLT #0, MP_H #0, MU_LK0 #, LES_H #0 P, 0_OUTLT #, OPMP_OUTLT #, MP_H #0, TIM_0 #0, TIM_ #, PNT0_S0IN #0, LES_H #0 P, 0_OUTLT #, OPMP_OUTLT #, MP_H #0, TIM_ #0, PNT0_SIN #0, US0_S #, LES_H #0 P, 0_OUTLT #, OPMP_OUTLT #, MP_H #0, TIM_ #0, US0_LK #, LES_H #0, G_SWO # EFMTG0F MU_P[..0] MU_PE[..] MU_PF[..0] MU_P0 MU_P MU_P MU_P MU_P MU_P MU_P MU_P MU_P U0 P0, 0_H0 #0, 0_OUT0LT #, OPMP_OUT0LT #, 0_OUT #, OPMP_OUT #, US_TX # 0 P, 0_H #0, 0_OUTLT #, OPMP_OUTLT #, TIM0_0 #, US_RX # P, 0_H #0, TIM0_ #, US_LK # P, 0_H #0, 0_N #0, OPMP_N #0, TIM0_ #, US_S # P, 0_H #0, 0_P #0, OPMP_P #0, LEU0_TX #0 P, 0_H #0, 0_OUT #0, OPMP_OUT #0, LEU0_RX #0 P, 0_H #0, 0_P #0, OPMP_P #0, TIM_0 #, LETIM0_OUT0 #0, PNT0_S0IN #, US_RX #, I0_S #, LES_LTEX0 #0, MP0_O # P, 0_H #0, 0_N #0, OPMP_N #0, TIM_ #, LETIM0_OUT #0, PNT0_SIN #, US_TX #, I0_SL #, MU_LK0 #, LES_LTEX #0, MP_O # P, MU_LK # MU_PE MU_PE MU_PE MU_PE MU_PE MU_PE MU_PE MU_PE MU_PE MU_PE MU_PE MU_PE 0 PE, L_OM0, US0_S # PE, L_OM, US0_LK # PE, L_OM, US0_RX # PE, L_OM, US0_TX # PE, L_SEG, PRS_H # PE, L_SEG PE, L_SEG, TIM_0 #, US0_TX #0 PE, L_SEG, TIM_ #, US0_RX #0, LES_LTEX #0 PE, L_SEG, TIM_ #, US0_RX #, US0_LK #0, I0_S #, MU_LK #, LES_LTEX #0 PE, L_SEG, US0_TX #, US0_S #0, I0_SL #, LES_LTEX #0, MP0_O #0, GPIO_EMWU PE, L_SEG, LEU0_TX # PE, L_SEG, LEU0_RX # MU_PF0 MU_PF MU_PF MU_PF MU_PF MU_PF 0 PF0, TIM0_0 #, LETIM0_OUT0 #, US_LK #, LEU0_TX #, I0_S #, G_SWLK #0/ PF, TIM0_ #, LETIM0_OUT #, US_S #, LEU0_RX #, I0_SL #, G_SWIO #0/, GPIO_EMWU PF, L_SEG0, TIM0_ #, LEU0_TX #, MP_O #0, G_SWO #0, GPIO_EMWU PF, L_SEG, PRS_H0 # PF, L_SEG, PRS_H # PF, L_SEG, PRS_H # EFMTG0F esigned: pproved: G OM oc No: <age ode> esign reated ate: Wednesday, ecember 0, 00 EFM I/O ocument number R0 reated ate Tuesday, January, 0 0 Modified ate Monday, October 0, 0 of
5 TP00 MUG_#RESET U0 0 RESET EOUPLE 0 00 VMU TP0 U VMU R0 SW00 L00 LMS R00 R VU V_0 V_ V_REG IOV_0 IOV_ IOV_ GN VU GN 0 0N 0 U N N VSS_P EFMTG0F 0N 0N 0N 0N U GN GN GN High Frequency lock Low Frequency lock HFXTL_N LFXTL_N HFXTL_P LFXTL_P X00 X0 P.0MHz P P.kHz P GN GN GN GN esigned: pproved: G OM oc No: <age ode> esign reated ate: Wednesday, ecember 0, 00 EFM Power ocument number R0 reated ate Tuesday, January, 0 0 Modified ate Monday, October 0, 0 of
![L signal connections L oost L_PF[..] L_PE[..] L_P[.](/docs-images/88/117488404/images/6-0.jpg ".] L_P[.")
![.0] L_PF L_PF L_PF L_PF L_PE L_PE L_PE L_PE L_PE L_PE L_PE L_PE L_P L_P0 L_SEG0 L_SEG L_SEG L_SEG L_SEG L_SEG L_SEG L_SEG L_SEG L_SEG L_SEG L_SEG L_SEG L_SEG L _EM_EM_EM _EM0_EM_NT M E_G_F M E_G_F](/docs-images/88/117488404/images/6-1.jpg "M_ 0_E_G_F EFM_P0_P_GEK MINUS_E_G_F _Q_H P_J_K T E_G_F OM0 OM OM OM OM OM OM OM N_P_J_K 0 _Q_H_ 0_E_G_F OL M_ N_P_J_K _Q_H_ L0--0 L_OM L_OM L_OM L_OM L_OM L_OM L_OM L_OM0 L_SEG L_SEG L_SEG L_SEG")
6 L signal connections L oost L_PF[..] L_PE[..] L_P[..] L_P[..0] L_PF L_PF L_PF L_PF L_PE L_PE L_PE L_PE L_PE L_PE L_PE L_PE L_P L_P0 L_SEG0 L_SEG L_SEG L_SEG L_SEG L_SEG L_SEG L_SEG L_SEG L_SEG L_SEG L_SEG L_SEG L_SEG L _EM_EM_EM _EM0_EM_NT M E_G_F M E_G_F M_ 0_E_G_F EFM_P0_P_GEK MINUS_E_G_F _Q_H P_J_K T E_G_F OM0 OM OM OM OM OM OM OM N_P_J_K 0 _Q_H_ 0_E_G_F OL M_ N_P_J_K _Q_H_ L0--0 L_OM L_OM L_OM L_OM L_OM L_OM L_OM L_OM0 L_SEG L_SEG L_SEG L_SEG L_SEG L_SEG L_P L_P L_P L_P L_PE L_PE L_PE L_PE L_P L_P L_P L_P L_P L_P L_P[..] L_PE[..] L_P[..0] L_P[..] L_P L_P L_P GN 00 N 0 U Segment names Segment placement esigned: pproved: G OM oc No: <age ode> esign reated ate: Wednesday, ecember 0, 00 L ocument number R0 reated ate Tuesday, January, 0 0 Modified ate Monday, October 0, 0 of
7 V Regulator Power input V TP00 V US_MINI_ P0 TP0 Place these TPs close to US header N U GN GN R00 K GN U00 IN SHN LPIL-J OUT OUT SET FULT GN GN_HET 0 N R0 K R0 K V GN GN GN GN GN TP0 L00 LMP00S USP V R0 0K V_SENSE V R0 0K V_SENSE USM R0 0K 0 0N R0 0K 0 0N 00 TP0 TP0 IP0Z GN GN GN VMU switch VMU_SWITHE VMU_SWITHE User input to control mcu V V TRLMU EEPROM EFM RX EFM TX R K V VMU U0 OM OM OM OM IN IN IN IN TS NO NO NO NO R0 K R U0 LVG _TX GN _RX TRLMU_MURST_ON TRLMU_UIF_P0_ON TRLMU_UIF_P_ON MUG_#RESET UIF_P0 UIF_P R R R0 R R U OM OM OM OM IN IN IN IN TS NO NO NO NO TRLMU_MURST TRLMU_UIF_P0 TRLMU_UIF_P TRLMU_I_S TRLMU_I_SL R0 K R0 K GN U0 S SL 0 WP 0 V R0 K EEPROM_WP EFM EN GN VMU V R K R M U 0 0N U0 0 V 0N M M M GN GN GN TS VSS 0 GN U0 LVG V L0 R LMS U0 V 0 GN 0N LVG GN V VMU U0 GN TS GN 0 0N GN esigned: pproved: G OM oc No: <age ode> esign reated ate: Wednesday, ecember 0, 00 GN GN Power + Misc ocument number 0 R0 reated ate Modified ate Saturday, March, 00 Monday, October 0, 0 of
8 + V TP N U GN GN R00 K GN U0 IN SHN LPIL-J OUT OUT SET FULT GN GN_HET 0 N GN GN R0 K R0 K VMU_R TP00 R0 R VMU_S TP0 00 U GN EM_VMU_ENLE GN 0 0N GN R0 M leeder Resistor U00 OM IN N NO TS 0m calibration switch GN V GN 0 0N TP0 TP0 SW00 PT_SW_SM TP GN R0 ST00 R0 Q0 NTS R K TP0 VMU 0 0N GN TP0 P00 OIN_ELL GN TP TP TP TP EM_H_TO_SWO EM_TRL0 EM_TRL EM_TRL EM_TRL U0 OM OM OM OM IN IN IN IN TS NO NO NO NO R0 K R0 K R0 K R0 GN MU power regulators EM_TRL[..0] GN 0 VMU_R VMU_S VMU_R VMU_S 0 V L00 LMS R R VS GN U R0 K 0N GN MU power current sense U0 -INS -INF VREG V- V- V- (HET) LT IN+ OUT R K GN R R R K R K GN GN R K + - U0 TLV R TP0 EM_SENSE_URRENT_RNGE VS 0N GN R R U0 -INS -INF VREG V- V- V- (HET) LT IN+ OUT R0 K GN R R K R K GN GN R K + - TLV U0 R TP0 EM_SENSE_URRENT_RNGE VMU_G power VMU_SWITHE K R 0N GN VMU voltage sense VMU_SWITHE R + - U0 - + U0 MP00T R MP00T R R K R 0K GN R K TP0 V R0 R Q0 VMU_G VMU_SWITHE 0 WTG R0 GN R GN L0 EM_SENSE_VOLTGE LMS U V L0 LMS R U R0 GN U GN U0 V GN MP00T U0 V GN MP00T referance voltage TP _VREF GN U V GN R K 0 LM00IM-.0 V L0 LMS esigned: pproved: G OM oc No: <age ode> esign reated ate: Wednesday, ecember 0, 00 R R GN U dvanced Energy Monitor ocument number R0 reated ate 0N Wednesday, ugust, 00 U0 GN TLV V Modified ate V U0 TS GN GN 0 0 0N of Monday, October 0, 0
9 R00 K V TP0 EUG_EXT_LE_TTH TP0 TP00 TP TP0 TP0 TP0 TP0 TP0 VTRGET GN EM_H_TO_SWO HEER_X_.MM_SM_SHROU P00 H_VTRGET H_#TRST H_TI H_TMS_SWIO H_TK_SWLK H_RTK H_TO_SWO H_#RESET 0 R0 0K GNGN R0 0K TP TP TP TP TP TP0 TP0 VES0-HNH 00 GN GN R0 0K LV0 Z Z Z Z LV0 Z Z Z Z U00 Y Y Y Y E E E E U0 Y Y Y Y E E E E EUG_HEER_EN R0 K V VTRGET SW_#TRST SW_TI SW_TMS_SWIO SW_TK_SWLK V R0 K LVG SW_TO_SWO U0 GN R R0 RP00 R RP0 R R0 R GN U OE OE IR IR LVT GN GN V EUG_#TRST_OUT EUG_TI_OUT EUG_TK_SWLK_OUT EUG_#TRST_IN EUG_TI_IN EUG_TMS_SWIO_IN EUG_TK_SWLK_IN EUG_TO_SWO_IN EUG_#RESET_IN EUG_UF_#OE MUG_TMS_SWIO MUG_TK_SWLK MUG_TO_SWO MUG_#RESET GN R M EUG U0 OM OM OM OM IN IN IN IN TS NO NO NO NO R VMU_G LV0 Z Z Z Z U0 Y Y Y Y E E E E GN VTRGET MU_SW_EN R0 K LVG U0 GN SW_#RESET VTRGET R0 0K R EUG_TMS_SWIO_#OE EUG_TMS_SWIO_OUT EUG_H_SW_ENLE EUG_MU_SW_ENLE MU_EUG_ISOLTE_#EN EUG_#RESET GN U0 LVG U0 LVG GN Power & ecoupling VTRGET 0 0N V U0 V V V V GN GN GN GN GN 0 GN GN 0N GN LVT GN VTRGET R GN L0 LMS U0 GN V LVG 0 0N V L00 LMS 0 0N GN U00 V Mode EUG_MU_SW_ENLE EUG_H_SW_ENLE EUG_UF_#OE H_VTRGET VTRGET ebug Out 0 0 External voltage External voltage MU ebug 0 0 isconnected VMU ebug In VMU VMU 0 VMU U0 TS U0 V GN V_F GN U0 V 0N GN 0N GN GN 0 LV0 LV0 00 0N 0 LV0 GN 0N 0N GN V MP00T esigned: G V U0 GN U0 LVG OM oc No: <age ode> esign reated ate: GN pproved: Wednesday, ecember 0, 00 VTRGET R ebug Interface ocument number R0 reated ate U0 - + Saturday, March, 00 MP00T R0 R Modified ate GN 0 N EUG_EXT_V_TRGET 0 of Monday, October 0, 0
10 USM USP R0 R R0 R TRLMU_I_SL TRLMU_I_S TRLMU_SPI_#S TRLMU_SPI_SK TRLMU_SPI_MISO TRLMU_SPI_MOSI 00 P GN EUG_#TRST_OUT EUG_TI_OUT EUG_TMS_SWIO_OUT EUG_TK_SWLK_OUT EUG_#TRST_IN EUG_TI_IN EUG_TMS_SWIO_IN EUG_TK_SWLK_IN EUG_#RESET_IN EUG_TO_SWO_IN R0 K GN 0 P EUG_UF_#OE EUG_TMS_SWIO_#OE MU_EUG_ISOLTE_#EN EUG_#RESET EEPROM_WP GN EUG_EXT_V_TRGET EUG_EXT_LE_TTH EM_VMU_ENLE EM_SENSE_VOLTGE EM_SENSE_URRENT_RNGE EM_SENSE_URRENT_RNGE V_SENSE V_SENSE 0 EUG_H_SW_ENLE EUG_MU_SW_ENLE V P00 TRL_MU_#TRST TRL_MU_TI TRL_MU_TMS_SWIO TRL_MU_TK_SWLK TRL_MU_TO_SW TRLMU_EUG_#RESET TP00 TP0 TP0 TP ootloader Halt TP TP0 TP0 LE0 YELLOW V U00 PORT PORT ontrol MU #TRST_OUT G TI_OUT H P0 / WKUP / USRT_TS / _IN0 / TIM_H_ETR / TIM_H / TIM_ETR TMS_OUT J P / USRT_RTS / _IN / TIM_H / TIM_H TK_OUT K P / USRT_TX / _IN / TIM_H / TIM_H PORT #TRST_IN G P / USRT_RX / _IN / TIM_H / TIM_H TI_IN H P / SPI_NSS / _OUT / USRT_K / _IN TMS_IN J P / SPI_SK / _OUT / _IN TK_IN K P / SPI_MISO / TIM_KIN / _IN / TIM_H [TIM_KIN] #RESET_IN P / SPI_MOSI / TIM_H / _IN / TIM_H [TIM_H] P / USRT_K / TIM_H / MO TO_SWO_IN P / USRT_TX / TIM_H P / USRT_RX / TIM_H P / USRT_TS / NRX / TIM_H / USM P / USRT_RTS / NTX / TIM_ETR / USP P / JTMS-SWIO P / JTK-SWLK P / JTI TP TP J K P0 / _IN / TIM_H / TIM_HN G P / _IN / TIM_H / TIM_HN P / OOT P / JTO / TRESWO / SPI_SK / IS_K [TIM_H / SPI_SK] P / JNTRST / SPI_MISO [TIM_H / SPI_MISO] P / I_SMI / SPI_MOSI / IS_S [TIM_H / SPI_MOSI] P / I_SL / TIM_H [USRT_TX] P / I_S / FSM_NV / TIM_H [USRT_RX] P / TIM_H / SIO_ [I_SL / NRX] J P / TIM_H / SIO_ [I_S / NTX ] K P / I_SL / USRT_TX [TIM_H] K P / I_S / USRT_RX [TIM_H] J P / SPI_NSS / IS_WS / I_SMI / USRT_K / TIM_KIN H P / SPI_SK / IS_K / USRT_TS / TIM_H G P / SPI_MISO / TIM_HN / USRT_RTS P / SPI_MOSI / IS_S / TIM_HN F F P0 / _IN E P / _IN F P / _IN G P / _IN H P / _IN F P / _IN E P / IS_MK / TIM_H / SIO_ [TIM_H] F P / IS_MK / TIM_H / SIO_ [TIM_H] E P / TIM_H / SIO_0 [TIM_H] P / TIM_H / SIO_ [TIM_H] P / URT_TX / SIO_ [USRT_TX] P / URT_RX / SIO_ [USRT_RX] P / URT_TX / SIO_K [USRT_K] P / TMPER-RT P / OS_IN P / OS_OUT R0 K GN _TX _RX TRLMU_MURST_ON TRLMU_UIF_P0 TRLMU_UIF_P TRLMU_UIF_P_ON TRLMU_UIF_P0_ON TRLMU_MURST P_REV0 P_REV ebug out LE V LK_SEL OR_REV0 OR_REV TP GN EM_TRL0 EM_TRL EM_TRL EM_TRL R00 K LE00 YELLOW U00 J-Link LE R0 K LE0 LUE EM_TRL[..0] V E P0 / OS_IN / FSM_ [NRX] P / OS_OUT / FSM_ [NTX] P / TIM_ETR / URT_RX / SIO_M P / FSM_LK [USRT_TS] P / FSM_NOE [USRT_RTS] P / FSM_NWE [USRT_TX] P / FSM_NWIT [USRT_RX] K P / FSM_NE / FSM_NE [USRT_K] J P / FSM_ [USRT_TX] H P / FSM_ [USRT_RX] G P / FSM_ [USRT_K] K P / FSM_ [USRT_TS] J P / FSM_ [USRT_RTS / TIM_H] H P / FSM_ [TIM_H] G P / FSM_0 [TIM_H] P / FSM_ [TIM_H] PE0 / TIM_ETR / FSM_NL0 PE / FSM_NL PE / TREK / FSM_ PE / TRE0 / FSM_ PE / TRE / FSM_0 E PE / TRE / FSM_ H PE / TRE / FSM_ J PE / FSM_ [TIM_ETR] K PE / FSM_ [TIM_H] G PE / FSM_ [TIM_H] H PE / FSM_ [TIM_HN] J PE / FSM_ [TIM_H] K PE / FSM_ [TIM_HN] G PE / FSM_ [TIM_H] H PE / FSM_ [TIM_H] PE / FSM_ [TIM_KIN] OR_REV[..0] ontrol MU ontrol MU Power & ypass TRLMU_EUG_#RESET R K V GN R 0N V V R K L00 LMS LE0 RE TP0 R R 0 U GN TP0 0 P GN 0 N 0 N X00 R Hz R 0 P _VREF 0N GN GN GN R0 E U00 OS_IN OS_OUT K G V VSS J H VREF+ VREF- F R N OOT0 NRST VT V_ V_ V_ V_ V_ VSS_ VSS_ VSS_ VSS_ VSS_ ontrol MU F F F F 0N E E E E GN 0 0N 0N 0N 0N 0N V U GN OR_REV[..0] esigned: G OM oc No: <age ode> esign reated ate: pproved: Wednesday, ecember 0, 00 OR_REV0 OR_REV V R K V ocument number R0 reated ate R K TRLMU_SPI_MISO TRLMU_SPI_MOSI TRLMU_SPI_#S TRLMU_SPI_SK ontrol MU Saturday, March, 00 Modified ate U0 MPX V GN 0 of Monday, October 0, 0 S U0 VSS MPX Q HOL W V V 0 N
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EFM US Type- 0 W harger History oard Function Title Page EFM & User Interface oard Power Page Rev. escription 00 Prototype version. 0 Initial release version. VUS Voltage Regulator ebug MU ebug Misc. P
Feature rich starter kit for evaluation, prototyping and application development for the EFM32 Gecko MCU family with the ARM Cortex-M3 CPU core.
USER MANUAL Starter Kit EFMG8XXSTK Feature rich starter kit for evaluation, prototyping and application development for the EFM Gecko MU family with the ARM ortexm PU core. Main features; Advanced Energy
Revision History. EFR32 Mighty Gecko Dual PHY Radio Board. 2.4 GHz 13dBm / MHz 14 dbm, DCDC to PAVDD. Board Function Page. Rev.
EFR Mighty Gecko ual PHY Radio oard. GHz dm / 868-9 MHz dm, to PV oard Function Page Title Page History Rev. escription. GHz RF, ntenna & Power 00 Prototype version. SubGHz RF, ntenna & Power EFR, PRO
Headers for all pins sorted by pin no. (unpopulated) TSX-1001 Cortex-M0. Oscillator 44MHz
V V Way type onnector US Type onnector x.v.v Regulators Headers for all pins sorted by pin no. (unpopulated) Prototyping area with power and GNs (unpopulated) RS Transceiver US to Serial onverter Expansion
S08P-LITE. 1 Title Page 2 Block Diagram 3 MCU & Arduino Headers 4 OSBDM & Power Supply 5 On-board Peripherials S08P-LITE. 23-Jun-17. V3.
Title Page lock iagram MU & rduino Headers OSM & Power Supply On-board Peripherials Revisions Rev escription ate -Jun- V.0 -Feb- pproved Microcontroller Product Group 0 William annon rive West ustin, T
POSWD0SWO POKBD0ROW0A GND POSDIO0D3 POLCD0NOE
L_LIGHT = P = TIM_H L_SX = P = FSM_NE L_TINS = P = FSM_0 LE_RE = P = TIM_H LE_GREEN = P = TIM_H LE_LUE = P0 = TIM_H POK0ROW0 K_ROW_ PIU0 POK0ROW0PIU0 K_ROW_ PIU0 POK0ROW0E K_ROW_E PIU0 POK0ROW0F K_ROW_F
Revisions. TWR-LCD-RGB Drawn by: Initial Release 15-JUL-11
Table of ontents Notes lock iagram isplay and Tower onnectors MU & apacitive Touch kt Rev X X escription Revisions Initial Release ate -JUL- pproved hanged Power L colours-jul- Removed J and J dded J &
KEIm Baseboard. PAGE DESCRIPTION 1 Block Diagram, History 2 SoM Connector. 3 LCD Connector. 4 Ethernet. 5 UART 6 Analog 7 Peripheral 8 Power
KEIm aseboard REV TE PGES ESRIPTION.0.0 Oct//0 ll INITIL REVISION RELESE..0 Feb//0 ll MP REVISION RELESE PGE ESRIPTION lock iagram, History SoM onnector L onnector Ethernet URT nalog Peripheral Power KONO
Intel Edison. 7V to 15V Brick Power Supply. 4.4V power supply and battery recharger UART 1 USB 0TG. EDISON BREAKOUT BOARD Title Title page
Intel Edison reakout Sept/0 V to V rick Power Supply V power supply and battery recharger SPI GPIO Intel Edison PWM I S URT 0 0" header US 0TG URT Level Shifter URT US FTI P P lient US Micro Type- lient
Block Diagram. Level Translators USB ICSP. Ethernet PoE. Atmega 32U4. 16MHz. User button Reset 32U4. Headers. Reset. Wi-Fi Module. Leds.
lock iagram Ethernet PoE Level Translators SPI HNSHKE URT tmega U US ISP MHz User button Leds Wi-Fi Module U GPIO Headers micros US US Host MHz lock iagram Size ocument Number Rev Yun ate: Thursday, January,
Revisions. 2 Notes. 4 FXLC95000CL / MCU Circuit 5 Power and Battery Charger Circuit. KITFXLC95000EVM Drawn by:
Table of ontents Notes lock iagram FXL000L / MU ircuit Power and attery harger ircuit Rev escription Revisions Original Release Remove signal line U- pin and add additional signal line between J-pin0 and
OTG_FS_VBUS OTG_FS_N OTG_FS_P OTG_FS_ID OTG_FS_OC OTG_FS_PWR OTG_FS_VBUS OTG_FS_N OTG_FS_P OTG_FS_ID OTG_FS_OC OTG_FS_PWR OLLO_SLEEP OLLO_SLEEP
MU ROOTIS / ORO MU_NRESET R_[0..] R_[0..] R_ R_ R_ R_ R_ R_0 R_0 R_ R_ R_ R_ R_ R_ OTG_S_VUS OTG_S_N OTG_S_P OTG_S_I OTG_S_O OTG_S_PWR OTG_S_I OTG_S_N OTG_S_P OTG_S_O OTG_S_VUS UT_USER UT_USER SW_USER
2 Notes 3 MC9S08LG32CLK 4 Touch Sensors 1 5 Touch Sensors 2 6 Power 7 OSBDM 8 USB COM
Table of ontents Notes MS0LGLK Touch Sensors Touch Sensors Power OSM US OM L Revisions Rev escription X First raft X Replaced, M RN with sigle resistors Updated Power section Swapped LE_ER, with ER, to
FRDM-KL27Z. 1 Title 2 Block Diagram 3 KL27Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Rev Description Date Approved
Table of ontents Title lock iagram KLZ MU OpenS INTERFE I/O Headers and Power Supply Revisions Rev escription ate pproved X Initial draft July, Release July, J, J, J, J, J, J, J, J, J, T, TP and TP Populate
01 TITLE PAGE 02 MCU 03 DEBUG INTERFACE 05 POWER BRIDGE 06 MOSFET DRIVERS / VI SENSING XSKEAZ128REFDES
Table of ontents 0 TITLE PGE 0 MU 0 EUG INTERFE 0 SUPPLY 0 POWER RIGE 0 MOSFET RIVERS / VI SENSING utomotive Product Group 0 William annon rive West ustin, T 9 esigner:. ZUZEK rawn by:. ZUZEK pproved:
HF SuperPacker Pro 100W Amp Version 3
HF SuperPacker Pro 00W mp Version Revised 0 0 V Stamps KOOR This is the third generation HF SuperPacker Pro 00W Version home construction project offered by HF Projects. This is a group construction project
L13X DAUGHTER CARDS TABLE OF CONTENTS REV SL NO. TABLE OF CONTENTS VERSION VERSION HISTORY BLOCK DIAGRAM 4 UART-0 INTERFACE
LX UGHTER RS TLE OF ONTENTS SL NO. ONTENTS PGE NO REV TLE OF ONTENTS VERSION HISTORY VERSION.0.. LOK IGRM URT-0 INTERFE N US INTERFE URT INTERFE PROFI US & SOFT IR INTERFE SOFT URTS REV NO. NTURE OF HNGE
X-USBPD-C-SHIELD. 2 Block Diagram 3 Type-C Connector 4 USB3/USB2 5 PTN5110 PD TCPC 6 Shield Headers 7 PD Source and Sink LS 8 3V3, 5V0, 1V8 Supplies
Table of ontents lock iagram Type- onnector US/US PTN0 P TP Shield Headers P Source and Sink LS V, V0, V Supplies Rev escription ate pproved Prototype Release -Mar- K ring up to NL and make updates requested
RSC CHIP VDD P05 P03 P01 P04 VDD GND PWM0 AVDD VDD AVDD P0-2 P0-5 P0-1 P0-6 P0-4 P0.3 GND P00. Y1 3.58MHz P00 P01 AGND P01 P00 P02 P02 P07 P0-0 P0-7
Place as close to pins of U as possible. RS HIP 0-00 RS-x emo/evaluation oard: RS-000 Thursday, ecember, 00 Size ocument Number Rev ate: Sheet of P XI P0 P0 P0 P0 P00 PN P0 P0 P0 P0 P0 P0 P0 P0 P XO -XM
Revisions. TRK-KEA128 Drawn by: Nov Original Release A. INZUNZA
Table of ontents Title Page Notes Rev X escription Original Release Revisions ate Nov--0 pproved Production Release ec--0 Production Release Feb--0 Microcontroller Solutions Group 0 William annon rive
Built on Dec /1/2018 Rev00. Project:STM32L4 Quadcopter Description: Quadcopter Control Board ...
Project:STML Quadcopter escription: Quadcopter ontrol oard //0 Rev uilt on ec-0 Page Index Page Index Page Index Page Index OVER PGE ONNETIONS: TTERY & ES ONNETIONS: LOW VOLTGE POWER: TTERY POWER: US POWER:
Design Overview. Page 2 Power,Flash,SDcard User switch,reset switch. Page 3 Ethernet. Page 4 Audio. Page 5 USB. Page 6 JTAG,BOOTSW,LED,Header
esign Overview Page Power,Flash,Scard User switch,reset switch. Page Ethernet Page udio Page US Page JTG,OOTSW,LE,Header isclaimer: Schematic's are for reference only. provides no warranty for the use
Changed in Rev.3. Title. Revision: Size: A4 Number:
ontent:. R Memory. Nand Flash, I, SPI Memory, S card. Ethernet M. Ethernet Phy 0. Ethernet Phy. RS-, ebug RS-, User leds, Relay leds. N0, N, External RT. US, US power switch. L onnector, Expansion onnector,
DP CoiNel Technology Solutions LLP GND GND GND GND. ETH_RST is connected to P1.28 GND GND GND GND GND GND GND GND GND ED 1. Vcc O 3 GND IOGND 35
V K R L FR nf nf Vcc E O MHZ_LK ENET_REF_LK ENET_MIO ENET_M MHZ_LK.K R Y OS_MHz LE_LK LE_SPEE LE_T nf is connected to P. ENET_TX ENET_TX ENET_RS ENET_RX ENET_RX ENET_REF_LK ENET_M ENET_MIO nf ENET_TX ENET_TX
Project: Date. Version. Items V1.01 C C. SIM Technology TITLE DRAWN BY PORJECT. SIM800C+SIM28M_VTS Reference CONTENT VER CHECKED BY SIZE V1.
Project: ate Version Items V.0 RWN Y PORJET SIM800+SIM8M_VTS Reference ONTENT HEKE Y V.0 SHEET of 7 POWER POWER -0V F0 0 L0 VIN LO X0 SM0 SWRH07 uh T-PIN-X TVS0 Z0 + 0 VT U0 VZ=V,Pd=W SM7 00uF V GN VOUT
VCC 21 VCC 52 AVCC PF0(ADC0) 60 PF1(ADC1) 59 PF2(ADC2) 58 PF3(ADC3) 57 PF4(ADC4/TCK) 56 PF5(ADC5/TMS) 55 PF6(ADC6/TDO) 54 PF7(ADC7/TDI) SCL TXD
POWER ELETRONIS **- Switching Power Regulation** V and.v outputs are isolated from High Voltage, but not each other Isolated Power Supply power.sch FTI US URT FTI US URT ftdi_uart.sch SLOOP_TRL HRG_TRL
05 - Adaptacion Puerto Serie RXD_UC R35 0 DTR_UC R36 0 RI_UC Adaptacion Puerto Serie Señalizacion GSM R37 0 INFO_NETLIGHT R38 0
0 - limentacion 0 - onector Externo 0 - daptacion Puerto Serie 0 - Modem SIM00 TT_VOLTGE VN_ TX TX_U RX_GSM RX_GSM HRGE_STTUS P. RX RX_U TX_GSM TX_GSM ST_ ST_ P. P. P. P. R 0 R 0 TR_U RI_U TR_GSM TR_GSM
CD-DET TP5_CS- LCDPWR RFPWR CHPD5 GP05 GP25 RST5 L13 D12 D11 D10 LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS- LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS-
SPST SW L 0uH.uF TP HEER NO STUFF TP 0 HEER NO STUFF TP TP pf Y.uF.uF 0 HEER NO STUFF 0 HEER NO STUFF MHz, 0ppm pf.uf (OUT) (IN) R 0K /W % 0uF OUT OUT OUT OUT KLT L 0 L_MISO L_MOSI L_SK S_S- L_S- L_- L_
AS1117M3 or LM1117MPX-ADJ ADJ. C20 0.1uF + C56. + C57 10uF. 10 uf R K 1% R18 GND 10.0K 1%
K POWER SW JP EXTERNL POWER FUSE 0. uf VT 0 uf R SM or LMMPX-J VIN VOUT U 0.0K % J R.K % 0uF REG_V 0 0.uF REG_V J PV PV_US_TGT V_M0X POWER_SELET R0 0Ohm V to V ENTER POSITIVE.
MSP430F16x Processor
MSP0x Processor V_. V_ V_. U Vcc Vcc R 0K SW, ETHER_T_00, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_T_0 P.0/TLK P./T0 P./T P./T P./SMLK P./T0 P./T P./T /RST/NMI 0.u P UTTON_
3 Different test points used in design: TPx - Test point pad. TPHx - Through Hole Pad Large (for standard 0.1" header). Also used on IO Matrix (IOMx)
NXP VKIT-SZV Table of ontents 0 LOK IGRM N NOTS 0 I/O Headers 0 Power/MU 0 Peripherals 0 US/OSM Revisions Rev escription esigner ate X Initial raft 00 Release 0/0/ X hanged MU to SZV 0// U T I O N : This
C uF T16 VDD T15 TMS TMS MCU_PORT_VDD T14 TDO TDO T13 JCOMP JCOMP PF3 T12 PF3 T11 VDDE3 5.0V PF4 T10 PF4 PJ5 PJ5 PF6 PF6 PF9 PF9 5.0V 5.
Size FSM No. WG No. Rev of 9 Galen Street Floor M 0 US MP0EMO Schematic -- MU and Symbol V V P P P P P 9 P0 0 P P P P0 VE V REFYP V P PK P P P 9 P 0 P0 P P P V P P P P9 P P P0 P P 9 P 0 P P P9 P P P P
Renesas Starter Kit for RL78/G13 CPU Board Schematics
Renesas Starter Kit for RL/G PU oard Schematics REV REF TE RWN Y 0.0 raft.0.0 TES.00 Release.0.0 YOI.0 Release 0.0.0 YOI PGE ESRIPTION INEX RL/G Microcontroller Switches, LEs, RESET, PSU E, Serial Port
FREEDOM KE02Z. 1 Title 2 Block Diagram 3 KE02Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Initial Draft 02/01/13
Table of ontents Title lock iagram KEZ MU OpenS INTERFE I/O Headers and Power Supply Rev X escription Initial raft Revisions. Remove Motor ontrol onnector J. Remap J, J, J, J pinout. dd one series resister
ZCRMZN00100KITG. Crimzon Development Board Kit. Product User Guide. Introduction. Kit Contents. Applying Power to Development Board
ZRMZN0000KITG rimzon evelopment oard Kit PUG000-0 Product User Guide Introduction Zilog s ZRMZN0000KITG rimzon evelopment oard Kit is designed for use as a target with the rimzon In-ircuit Emulator (ZRMZNIE0ZEMG).
0603/15p/10v L R/100MHz. 100nF/50V. 100nF/16V. 100nF/50V C105 C106 C108 C107 GND GND GND GND
+V +V 00nF/0V 00nF/0V 00nF/0V 00R/00MHz.µF/0V 00nF/V 00nF/V 0K K n.b. 0k 0k 00/p/0v 00/p/0v MHZ-.X. 00nF/V 0R 0R µ/v MK0XVLK MK0XVLK 00nF/0V 00nF/0V µ/v 00R/00MHz 0R 0 0 0 L0 0 0 R0 R0 R0 R0 L0 L0 Y0 0
CP2102 TESTAMATIC SYSTEMS POWER 5V TO 3.3V SECTION PINOUT CHECK DECOUPLING CAPACITORS. Btype USB connector TSPL_PPS_1 2.2
VUS R V_IN V TO.V SETION.V SI_RX SI_TX 0E R PINOUT HEK MINISM00F- Resettable Fuse F 00m WHITE 00nF U GN EN IN IN TPS PG nc OUT OUT 0k R 0.V 00nF Power_Good MIRO US IS INITE S ON TX RX 0.uF VUS TR RI GN
B0549-SCH-01 RD VEGA STDP4028 (DVI to DPTx) Reference Design PCB# Revision History
0-SH-0 R-0 VEG STP0 (VI to PTx) Reference esign P# 00- Revision History SHEMTI SHEET ate uthor Version omments 0. ontents, Revision History Sept., 00 Tony W. Rev. Initial schematic. 0. Overview Oct., 00
Quickfilter Development Board, QF4A512 - DK
Quickfilter evelopment oard, QF - K nalog Inputs - U +.V +.V J N hannel J N hannel J N hannel J N hannel U +.V +.V U +.V U +.V Prototyping rea J J Optional +V External Power x Header 0." US onnector U
CAN 1 CAN 2. CoiNel Technology Solutions LLP GND GND GND GND GND GND J1 JUMPER J2 JUMPER. 100nF. 100nF R2 120 R1 120 VDD 3 CAN1_H CAN2_H
V N N V N_TX N_TX U TX V 00nF N_H R 0 J JUMPER N_H N_TX N_TX U TX V 00nF N_H R 0 J JUMPER N_H N_RX N_RX V NP R RX Vref VSS N_L Rs 0K MP R N_H N_L N_L J ON N_RX N_RX V NP R RX Vref VSS N_L Rs 0K MP R N_H
For max 243 R2OUT is low when R2IN is disconnected enabling the MAX 489 (RS-485) This will not work if MAX232 is used!
JP RS_SELET V For max ROUT is low when RIN is disconnected enabling the MX (RS-) This will not work if MX is used! V On Front Panel -F (To Pg.) RS- RE_ RE_ RV_Y RV_Z 0.uF V U MXUK STR U- H G U MX 0 Y Z
General Description. Features. Kit Contents. MAX32660 EV System Photo
lick here for production status of specific part numbers. MX0 Evaluation System Evaluates: MX0 General escription The MX0 evaluation system offers a compact development platform that provides access to
nrf52840-mdk V1.0 An Open-Source, Micro Development Kit for IoT Applications using the nrf52840 SoC Revision History Function Description Page Rev.
nrf0-mk V.0 n Open-Source, Micro evelopment Kit for IoT pplications using the nrf0 So Revision History Function escription Page Rev. escription Title Sheet V.0 The First Release Power Supply US.0 Hub PLink
PS2_B_CLOCK PS2_B_DATA PS2_A_CLOCK PS2_A_DATA UART_C_RXD UART_B_RXD UART_A_RXD UART_C_TXD UART_B_TXD UART_A_CTS UART_A_TXD UART_A_RTS GPIO[0:31]
![PS2_B_CLOCK PS2_B_DATA PS2_A_CLOCK PS2_A_DATA UART_C_RXD UART_B_RXD UART_A_RXD UART_C_TXD UART_B_TXD UART_A_CTS UART_A_TXD UART_A_RTS GPIO[0:31]](/thumbs/87/96361917.jpg "PS2_B_CLOCK PS2_B_DATA PS2_A_CLOCK PS2_A_DATA UART_C_RXD UART_B_RXD UART_A_RXD UART_C_TXD UART_B_TXD UART_A_CTS UART_A_TXD UART_A_RTS GPIO[0:31]")
V. V. V. V. PI_RX URT LK URT TX PI_RX _TS_EXPHR _RX_EXPHR _RX_EXPHR Uarts URT TS URT RTS URT TX URT RX PS LOK PS T PS LOK PS T URT TX URT RX URT TX URT RX V. V. Ethernet ETH RX[0:] ETH RXV ETH RXER ETH
VCC 52 VCC 21 AVCC PF0(ADC0) 60 PF1(ADC1) 59 PF2(ADC2) 58 PF3(ADC3) 57 PF4(ADC4/TCK) 56 PF5(ADC5/TMS) 55 PF6(ADC6/TDO) 54 PF7(ADC7/TDI) SCL TXD
POWER ELETRONIS **- Switching Power Regulation** V and.v outputs are isolated from High Voltage, but not each other Isolated Power Supply power.sch FTI US URT FTI US URT ftdi_uart.sch Safety Loop Wiring
Audio Mod RF-04-N-10 PC13 BAS85 56 PG1 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PG0 57 PG2 87 PG3 88 PG4 89 PG5 90 PG6 91 PG7 92 PG8
LC0,uF,uF R R 0uF 0uF uf R uf uf uh FOX_.000 uh 0uF 0uF R k DFU mode k 0uF KRMR SSSM TCM0 P0DT0G S PN0-S STMFX_ZIT C C0 C C C C C C C R R C C C C R C0 C C C L R0 IC L C C RD C0 C0 R0 P R C C0 C C C C TP
J1B B1 B3 B5 B7 B9 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B35 B37 B39 B41 B43 B45 B47 B49 B51 B53 B55 B57 VCC VCC USB_DET
GP0 GP0 GP0 P0 GP0 GP GP GP GP GP GP GP P GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP00 UINO ONE PIN EFINE GP0 GP GP GP GP GP GP GP GP0 GP GP
All use SMD component if possible
R0 0K MF SW0 NEXT R0 0R LE0 STNY & POWER ON GN R0 SW0 PREV R 0 MF R 0 MF R 0K MF R0 K MF SW0 FF GN SNP OFF OR GN Q0 S Q0 S LE R k R k 00n R 0K MF M0 R0 K MF SW0 FR +V() Q0 R 0K MF GN R0 0 R 0 GN VF_on_off
Audio Mod RF-04-N-10 PC13 BAS85 56 PG1 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PG0 57 PG2 87 PG3 88 PG4 89 PG5 90 PG6 91 PG7 92 PG8
LC0,uF,uF R R 0uF 0uF uf R uf uf uh FOX_.000 uh 0uF 0uF R k DFU mode k 0uF KRMR SSSM TCM0 P0DT0G S PN0-S STMFX_ZIT C C0 C C C C C C C R R C C C C R C0 C C C L R0 IC L C C RD C0 C0 R0 P R C C0 C C C C TP
LED POWER STAGE1 NOT_EN LED+ PWM LED- 12V. LED Power Stage LED POWER STAGE2 NOT_EN LED+ PWM LED- 12V. LED Power Stage LED POWER STAGE3 NOT_EN LED+ PWM
MU LE POWER STGE MU MX LI LI_TX LI_RX THERMISTOR- MX_RX MX_TX MX_E MX_/RE EN_ EN_ EN_ EN _ V LE Power Stage LE POWER STGE LE+ LE- LE+ LE- R R 0 J 0 Way 0 LI_TX LI_RX MX_RX MX_TX MX_E MX_/RE V LE Power
Host MSP430. dacqs_host_board 12/7/2016 9:26 PM. U1 Value +3V3 AVCC_HOST UART_1_TX UART_1_RX MSP_SCLK UART_2_TX UART_2_RX CUTDOWN_EN MSP_SS
+V Host MSP +V R MSP_SS MSP_MOSI MSP_MISO V_HOST MOTOR_T_VSNS_ OMMS_MOSI OMMS_MISO OMMS_SLK OMMS_SS URT TX URT RX V V V V P._T._M_RTLK VRF-_VRF- P._T._TLK_OUT VRF+_VRF+ P._T._TLK_OUT P._T._UST P._T._UST
REVISION HISTORY DESCRIPTION INITIAL SCHEMATIC AIY REMOVED ANALOG SWITCHES CHANGED FEEDBACK
REVISION HISTORY Notes - Unless otherwise noted. Resistances values in Ohms. apacitance values in micrarads (uf). ll 0.uF and 0.0uF capactors are decoupling and should be placed near the I they are shown
CLKOUT CLKOUT VCC CLKOUT RESOUT OSCOUT ALE TEST AD0 66 AD2 INT0 INT0 AD INT1 AD INT2/INTA0 AD5 AD7 AD7 INT AD8 AD8 AD10
I U N R 00K RSIN* RST S N.0u Y LK TP RP K L TP USY INT0 INT RISMINT P.0 P. P. P. P. P. P. RY OL RX0 TX0 T P.0 P. P. P. S* S* S* S* RROR* SLK U LKIN LKOUT LKOUT LKIN LKOUT OSOUT 0 OSOUT L L RSIN* L 0 0
Revisions. TWR-MEM Drawn by: Convert into FSL template 9/8/09
Table of ontents Notes F & PL MRM, S & SFLSH OPTIONL PORT Rev X0 escription onvert into FSL template Revisions X ll parts FL //0 X Replaced U with the correct part //0 X X Replaced some components with
Note: Please refer to AX110xx Network SoC Application Design Note for more detailed information.
PGE PGE X00 & X00 hip H/W onfiguration Pins MHz rystal RJ- onnector o H ebugger onnector I onfiguration EEPROM (T0) Power and y-pass apacitors Serial us Schematic: I : I EEPROM SPI : T EEPROM (optional)
Realtek Semiconductor Corp. Title RTL8213(M)_FHG_V1.0
Fiber LE RJ M RYSTL EEPROM SRM & FLSH POWER PWRJK Jumper for GPIOs URT Realtek Semiconductor orp. RTL(M)_FHG_V.0 Size ocument Number Rev lock diagram.0 ate: Tuesday, November, 00 Sheet of ,, /ISGPIOSTP
Generated by Foxit PDF Creator Foxit Software For evaluation only.
I_ST I_SLK K_% R K_% R L_0 L_ L_ L_ KEY TON_STHL /F NN_ NN_ P M VS OUTL P OUTR VR MIIN VREF V HOSI LOSI R X pf LOSO.KHZ M_% pf HOSO X pf MHz HOSI 0 pf POWER Generated by Foxit PF reator Foxit Software
NOTE: please place R8 close to J1
Sheets, & /M_RESET PST T T0 +.V_MU R 0K /M_RESET PST T T0 +.V_MU 0.uF NOTE: please place J close to the edge of the P so that the debug cable is clear of the P when attached to the board J 0 0 M Header
DISPLAY 1 DISPLAY 2 a. a b. a f. a f. b g. c d. c d. 16 x 2 HD44780 BASED ALPHANUMERIC DISPLAY LCD 16 X 2
SEGMENT LE ISPLY R MUX MUX MUX MUX R nf SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ U R xt P P P P P P P P MX MX ss SL S P P P P P P P P nf S SEG_SL SEG_S SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_I_SL_
AS1117M3 or LM1117MPX-ADJ REG_VDD ADJ. C20 0.1uF U6. + C57 10uF R K 1% GND 3.92K 1%
K POWER SW JP EXTERNL POWER FUSE 0. uf VT + 0 uf SM or LMMPX-J REG_V VIN VOUT + 0uF 0 0.uF U R 0.0K % J R.K % REG_V J PV PV_US_TGT V_M0X POWER_SELET R0 0Ohm V to V ENTER POSITIVE.
#1 10P/DIL NORTH #3 #3 #3 #3 #3 #3 #3 #3 R198 RES0603 RES0603 DNP DNP DNP RES0603 RES0603 RES SDI_N 3-SDO_N 3-ALERT_N 3-CS_N 3-SCLK_N 3-CONV_N
P REVISION REOR J SP88 0 - RE N_JK P 90-00_-POS TP # - Remove these components to stack north # - Populate these components to stack north Use k Resistors or adjust as needed Header - Molex 90-0 PITORS,
XO2 DPHY RX Resistor Networks
PHY_0_P_RX PHY_0_N_RX [] [] R R LP_0_P_RX HS_0_P_RX HS_0_N_RX LP_0_N_RX PHY_LK0_P_RX PHY_LK0_N_RX PHY_LK_P_RX PHY_LK_N_RX [] [] [] [] R R6 R8 R0 LP_LK0_P_RX HS_LK0_P_RX HS_LK0_N_RX LP_LK0_N_RX LP_LK_P_RX
THAT Corporation. QSC Digital Cinema Monitor DCM-2/DCM-3 Monitor Board
anyone without the written permission of THT orporation. escription ate 00 Released // 0 Per EO # /0/ pproved ataports,,, -00.SH VMON & IMON Input Select of -00.SH UNLESS OTHERWISE NOTE: ataports E,F,G,H
5V_EXT J3-1 J3-1 5CSX_4A_IO39 5CSX_4A_IO37 5CSX_4A_IO40 UART0_CTS 5CSX_4A_IO32 UART0_RTS 5CSX_4A_IO29. 5CSX_IOp0 5CSX_IOn0. 5CSX_IOp1 5CSX_IOn1
JTG hain US to URT L RJ Socket PHY Micro S ard Socket HPS IO 空置 00-00 Soaseoard.(Final) PHY connect_.v V_EXT JTG_FPG_TO S_LK connect_.v SX IO N_RX connect_.v URT_TS URT_RTS RT_T S_ S_M S_T S_T S_T S_T0
MT9V128(SOC356) 63IBGA HB DEMO3 Card
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R SPIF output Power LO R SPIF input x Flash POR PWM LE x R* Lightning() P x pin Type connector US pin For Lightning & P T QFN RE PLY H Sel T PLY x PM Ext. MU H Sel T RE x S NE OP R* Size ocument
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igital Meter R0.K V 0 0.UF U0 R 0 V R0 K 0 0.uF 0.V R9 R K K V V V 0 09 0 N0 0UF/V Low 0UF/V 00UF/V R R 00K 00K 0 pf Left N0 0 N N 0 VR0 0K 0 0.uF R 0M 0 0.uF k U0 9 0 V0 0.uF N0 V PI 0 09 R R 0 SPL GREEN
DAC PLAY0 PLAY0 CT7601 DAC REC ADC REC RCA * 2. Power LDO RCA. RCA * 2 SPDIF output x2 RCA RCA RCA. Ext. MCU POR. PWM LED x 2. SPDIF input x 1.
R * SPIF output x Power LO R * R R SPIF input x POR Flash PWM LE x PM00 Lightning() P 0x0 0pin Type connector US 0pin For Lightning & P T0 RE PLY0 PLY H Sel Stereo T0 PLY0 T0 0x PLY 0x PM00 R Ext. MU H
LED_POWER_STAGE1 PWM GND ADJ LED- -12V R2 RA. LED Power Stage LED_POWER_STAGE2 PWM GND ADJ LED- -12V R4 RB. LED Power Stage LED_POWER_STAGE3
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Am186CC and Am186CH POTS Line Card
RVISION HISTORY RV. T INITILS.0 // JSK m and mh POTS Line ard Reference esign NOT: The purpose of this design is to illustrate how to connect some of the M digital blocks together. It is not intended to
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Reference Schematic for LAN9252-SPI/SQI+GPIO16 Mode
Reference Schematic for LN-SPI/SQI+GPIO Mode onfigurations SPI/SQI+GPIO Mode EEPROM - F (High) Port mode Port0 & Port = opper Page No. Schematic Page Title Power Supply LN(Part) LN(Part), Strap & EEPROM
Revisions. Prototype Release J.H. 21 May 12
Table of ontents Notes lock iagram MP MU in SKT MP MU Power, RST, LIN, N JTG & NEXUS M onnections M onnections Rev X escription Prototype Release Revisions Update from VT - hange shunt on J to pins - -
Power. I/O Extensions. CPU Extensions. JADE-D Subsystem
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P300. Technical Manual
+ I/Os, solenoid drivers Technical Manual icasso venue, avis, C, US Tel: -- Fax: -- Email: sales@tern.com http://www.tern.com COYRIHT, i-engine, -Engine, R-Engine and CTF are trademarks of TERN, Inc. mes
NXP Automotive S12ZVMBEVB C U S T O M E R E V B
NXP utomotive SZVMEV U S T O M E R E V Table of ontents 0 PWR SUPPLY / LIN INTERFE 0 ZZVM MU 0 MOTOR ONTROL 0 NLOG SENSE 0 USER PERIPHERLS 0 OSM Revisions Rev escription X Initial raft 00 Release Prototype
Desired Part Placement. Max current set to 3A (motor Drive is 2.5A) SCI-DRV8814-MVK Mike Claassen B1 Dawn Ritz 40V. VDC_In GND. Board Test Points TP1
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Block Diagram SGTL5000 PG. 3. Power PG. 8. Communication PG.6. I2S Signals PG.7. Analog Inputs PG.4. Analog Outputs PG.5.
lock iagram I R Select I/SPI Mode Select MLK Source ommunication PG. US to I/SPI IS Signals PG. nalog Inputs PG. IS Interface Line-In / Microphone nalog Outputs PG. Headphone SGTL PG. igital Header P PSI
ISA INTERFACE & POWER SELECTION Size Document Number Rev Custom. XR82C684 EVAL BOARD 1.2 Date: Monday, August 13, 2007 DO NOT INSTALL CON_AT62B
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FUNCTION. Write/Read RAM: Access to PRAM, CRAM, OFFRAM and Registers Digital Audio Interface - Test pin header. Regulator 1.2V.
[K-] K- K Evaluation oard Rev.0 GENERL ESRIPTION The K- is an evaluation kit for the K; a digital signal processor (SP) with channels digital data interface. It realizes an easy evaluation of the audio
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Reference Schematic for LAN9252-HBI-Multiplexed Mode
Reference Schematic for LN-HI-Multiplexed Mode onfigurations HI Multiplexed mode EEPROM - F (High) Port mode Port0 & Port = opper Page No. Schematic Page Title Power Supply LN(Part) LN(Part), Strap & EEPROM
XR21B1422/1424 POWER & USB 1.0 Date: Thursday, February 13, 2014
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THE UNIVERSITY OF NEWCASTLE University Drive Callaghan NSW 2308 Australia
MicroL MicroLon.Sch Timers_nalog Timers_nalog.Sch IO ufferingsch IO uffering.sch Power Supply Power Supply.Sch Mitsubishi ackplane oard ate: THE UNIVERSITY OF NEWSTLE University rive allaghan NSW 0 ustralia
8V Title SCHEMATIC, 8V89317EVB REV A. Date: Friday, June 14, Power Supply. XTAL Interface. 12.8MHz TCXO/OCXO LED Status IN1 OUT1
isclaimer: IT is providing this schematic for reference purposes only. lthough the schematic was taken from a known working design, it is being provided "as is" without any express or implied warranty
Dev Board for CC IMX28. Mechanicals Board Size should be 7 X 8 inches Group similar connections together (ENET, USB, UART, etc) H5 ANT1
0 S oard Size should be X inches roup similar connections together (NT, US, URT, etc) S URT T OUT NT Power Supplies TM US0 (OT) umpers and switches need to be organized in functional groups and labeled
AKD4554-E Evaluation board Rev.0 for AK4554
SHI KSI [K4554] K4554- valuation boar Rev.0 for K4554 GNRL SRIPTION K4554- is an evaluation boar for the portable igital auio 6bit / an / converter, K4554. The K4554- can evaluate / converter an / converter
Calypso Customer EVB 324 BGA Daughter Card (X-MPC574XG-324DS)
alypso ustomer EV G aughter ard (X-MPXG-S) Table Of ontents: Power - alypso power pins footprint Power - alypso ecoupling apacitors GPIO - alypso GPIO pins of GPIO - alypso GPIO pins of locks us Termination
XIO2213ZAY REFERENCE DESIGN
XIOZY REFERENE ESIGN XIOZY Reference Size ocument Number Rev ate: Wednesday, September, 00 Sheet of TP+ TP- TP+ TP- TPIS TP+ TP- TP+ TP- TPIS TP0+ TP0- TP0+ TP0- TPIS0 REFLK+ REFLK- V_ V_ V_ORE PLLV_ORE