UART Switches. DIO Switches. SPI Switches TEST POINTS 2 x 0.1 Inch Header UART SPI. Other DIO. XLR radio. (1W linearity requires 4W DC)

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1 0.-. Vdc POWR IN Terminal lock. - 0 Vdc POWR IN Phoenix US V ine (mini-) Switch iode iode US (mini-) power supply XR only. power supply S PROM (config TI) RSSI ( White roup) TX / RX / SSOIT (Yellow White lue group) MSUR URRNT POTNTI Mz PROM SPI US URT URT Switches s/ indicators ON_nSP (lue ) V ine (Red ) TI ommunication nable ( Yellow roup) NOTS (block diagram only) SPI = MOSI, MISO, S, SS, TTN URT = TX, RX, TS, RTS,, TR (pin sleep) PWR US to serial (TI T) IO IO Switches oopback (White ) SPI SPI Switches TST POINTS x 0. Inch eader SPI Other IO XR radio URT OMMISSION UTTON (XR_IO0/ 0/ ommtn) (W linearity requires W ) R connector MMX RST ONTRO RST UTTON serial wire debug (not T) NINR: atwyler PRT NO. 0 ohm trace O c igi International Inc. 0 ll rights reserved O NOT S RWIN RP-SM R onnect (antenna) SM R onnect (from radio) cable MMX to SM RV O PPROVS: SIN: RWN: : SRIPTION O N T: // TIT Y PPR T XR evelopment oard -U lock iagram 00-0 ST RV. of

2 0 Mechanicals STNI N_R P SM-00T N N N N TIS ONNTOR OR R ROM XR MOU (SM M) NO TRM RI ON NY YR VIS IN XPOS MT MUITP VIS TROU ROUN YRS (US VY "STIT") M P P TIS TR IS 0 OMs N_R P ONRVSM00 N N N N TIS ONNTOR OR R TO NTNN (target RP-SM M) M M M Mounting holes / inner grounded N_R RV O SRIPTION O N Y PPR T TIT PPROVS: T: O c igi International Inc. 0 ll rights reserved O NOT S RWIN SIN: RWN: : NINR: // atwyler PRT NO. XR evelopment oard -U Mechanicals 00-0 RV. ST of

3 0. V - 0 V Input Phoenix connector P P-0 VIN TP0 TP0 TP 0 SM0 TP TP u u/ 00u/00V SOTS -.0mm X.mm &.0mm X mm 0WQ0N-P POWR IN 0 00u/00V 0u/V 0n u u U is good for.v to V, is limited by cap voltage. voltage rating needs to be 0V. R. U TU N RT N/UV VIN VIN N P SYN/ MO TR/SS INTV N N N ST SW SW SW SW IS u 00n.u/. R M R 0 u V u 0mV drop across this Inductor at amps. 0mW, 0. OMs Spec is 0. OMs which would be 00mV and 00mW causing 0 degree rise.mp = 0mV rop if 0.0 OMs.mp = mv rop if 0.0 OMs u u 0 Ohm/ 0 u 0u u V_ V_ Pin and will be a maximum of.v MR00T V MR00T u US_V 0 Ohm/ 0u 0. expected 00 to 0m U0 STR VIN VOUT VOUT N u 0u R.V_TI u R0 u 0u.V RV O SRIPTION O N Y PPR T TIT PPROVS: T: O c igi International Inc. 0 ll rights reserved O NOT S RWIN SIN: RWN: : NINR: // atwyler PRT NO. XR evelopment oard -U Power Supplies./v 00-0 RV. ST of

4 0 TI IP TI_V VP VPY.V_TI 0 U- T VIO VIO VIO VIO VOR VOR VOR VP VPY N N N N N N N N N 0 00n TI_V 00n 0 00n.V_TI 0 Ohm/0. VP 00n.V.V V N Switches U- TVQ 00n V N U- TVQ 00n V N U- TVQ.V Switches TVQ.u 00n 0 VRIN VROUT.u 0 Ohm/0. 00n VPY 00n NN V N U- 00PW Inverter 00n.V V N UP0W U- 00n V N U0- TVQ 00n V N U- 0.u 00n TVQ - Place aps close to U. U. U. U.0 U. U. U. U.0 U. U. 00n.V_TI 00n 00n.V_TI 00n 00n 00n 00n 0 V N V N U- 00PW U- 00PW 00n 00n V U- N TVQ V U- N U. 00n V N U- T-I/SN PROM V comparator needs v for possible v on output line 0 00n V N U- MVIPWR O c igi International Inc. 0 ll rights reserved O NOT S RWIN RV O PPROVS: SIN: RWN: : NINR: SRIPTION O N T: // atwyler TIT PRT NO. Y PPR T XR evelopment oard -U Power TI, SW, omp 00-0 ST RV. of

5 0 US PORT US Mini US_V_POWR_IN 00 Ohm,. US_V US lines 0, and for port,, and are initially default output igh. see Note US_- US_ 0n V00P US000P R 0 US000P.V_TI U- T-I/SN N S S OR R. R 0 R 0 US_V R 0 R R R R U- T M P R RST S T TST OSI OSO US0 US US US US US US US US0 US US US US US US US 0 NOT US-R_ST TI_S/IO TI_SMOSI/IO TI_SMISO/IO TI_SS/IO TI_SMT_/IO TI_SMT_/IO TI_S TI_MOSI TI_MISO TI_SS TI_SMT_/IO TI_SMT_IO TI_SMT_IO see Note SPI INS connected to reserved pins lso connected with URT RST O I R. p Y Mz N N p US0 US US US US US US US US0 US US US US US US US 0 R R R R R TI_TX//IO TI_RX/IO TI_RTS/IO TI_TS/IO TI_TR/SP_RQ/IO TI_SR/ TI_STTN TI_0/IO0/OMM TI_S_ON_R TI_S_ON_WRIT TI_ON/SP/IO TI_RST TI_SSO/IO TI_RSSI_PWM/IO0 TI_PWM/IO US URT INS Module nabled if low. nables Module if low..v_ti PWRN SUSPN 0 R 0 U- UP0W R 0 U- UP0W TI_RST TI_RST_Openollector RV O SRIPTION O N Y PPR T TIT PPROVS: T: O c igi International Inc. 0 ll rights reserved O NOT S RWIN SIN: RWN: : NINR: // atwyler PRT NO. XR evelopment oard -U TI hip/us 00-0 RV. ST of

6 0 SW T00Q RST UTTON P can allow for in circuit current measurements if R and R are removed. owever voltage droop may cause undesired operation when sudden current spikes occur during transmit. _RST TSW-0-0--S P SW T00Q OMMISSIONIN UTTON _OMM V_ R R SW Switch/0--V XR_V Sensing Power Supply R XR_V nable V SNS V OR N OR N SNS M M R.V SMZV-- R 0 R0 0 R 0 R 0 N_URT_to_TI N_SPI_to_TI N_PIO_to_TI SW S00S.V Switch Position igh ow TI_S_ON_WRIT X X XR_Shutdown igh ow Module.V_OUT nabled Yes No Middle ow igh Yes N_URT_oopback/cho igh ow No -S--0 SW.V R0 R R XR_SUTOWN_TI_TO_SWIT This pin can be up to V supply maximum XR_SUTOWN RV O SRIPTION O N Y PPR T TIT PPROVS: T: O c igi International Inc. 0 ll rights reserved O NOT S RWIN SIN: RWN: : NINR: // atwyler PRT NO. XR evelopment oard -U uttons/switches/eaders 00-0 RV. ST of

7 0 XR_IO0/PWM RSSI/0.V R. R R RSSI s VR_.V VR_.0V VR_.V R 0 u VR_.V VR_.0V VR_.V U- MVIPWR - - U- MVIPWR - U- MVIPWR S S S WIT WIT WIT... R R0 R 0 00n.V Illuminates when V reaches Module XR_V nable.v Q SS S R R S Illuminates when URT and/or SPI and/or PIO switches connections are enabled to Module ON/SP XR_IO/ON_SP R..V S U Q- TU-- R 0 R S SM-X00YW.V URT_to_US_nable OUT, IN, N SSO S.V SPI_nable R S SM-X00YW ST XR_IO/OUT Pre-biased transistors are biased with 0k resistor XR_IO/IN/ONI Q- TU u Q- TU R 00 u R 00.V S Q- TU Q- TU S XR_IO/SSO.V R. R S S S U SM-X00YW WIT R. S Q- TU-- O c igi International Inc. 0 ll rights reserved O NOT S RWIN PIO_nable OOP N oopback needs URT_enabled to operate oopback for US side is independant of URT_to_US_nable N_URT_oopback/cho URT_to_US_nable R. R0 WIT S S SM-X00YW RV O PPROVS: SIN: RWN: : NINR: SRIPTION O N T: // atwyler TIT PRT NO. Y PPR T XR evelopment oard -U s 00-0 ST RV. of

8 0 TI (US) URT to XR RIO isable URT ontrol isable URT if unit.v_in is shutdown See note TI_TX//IO XR_IN_SW URT_to_US_nable O R U- TVQ XR_IO/IN/ONI N_URT_to_TI 0 U- 00PW URT_to_US_nable TI_RX/IO R U- TVQ XR_.V_IN_RY XR_OUT_SW O R U- TVQ XR_IO/OUT URT oopback nables cho This can be used for loopback. oopback circuit is always connected to US URT oopback circuit is disconnected from Module if N_URT_to_TI is low. TI_RTS/IO 0 O XR_IO/RTS TI_TX//IO U- 00PW U- 00PW R0 R XR_IN_SW TI_TS/IO U- TVQ O R XR_IO/TS 00PW U- 0 00PW U- N_URT_oopback/cho TI_TR/SP_RQ/IO U- TVQ O R XR_IO/TR/SP_RQ N_URT_oopback/cho TI_RX/IO R R 00PW U- U- 00PW 0 U- 00PW 00PW U- XR_OUT_SW U- TVQ TI_SR/ O XR_IO//PWM/TR RV O SRIPTION O N Y PPR T TIT PPROVS: T: O c igi International Inc. 0 ll rights reserved O NOT S RWIN SIN: RWN: : NINR: // atwyler PRT NO. XR evelopment oard -U Isolation Switches URT 00-0 RV. ST of

9 0 TI SPI TI_S/IO SPI_nable to XR RIO SPI U- TVQ O XR_IO/SPI_/x isable SPI/PIO ontrol isable SPI/PIO if unit.v_in is shutdown See Note N_SPI_to_TI XR_.V_IN_RY U- 00PW SPI_nable U- TVQ TI_SMOSI/IO O XR_IO/SPI_SI/x U- TVQ PIO_nable 0 O U- TVQ TI_SMISO/IO 0 O XR_IO/SPI_SO/x R _OMM TI_SS/IO U- TVQ O XR_IO/SPI_SS/x TI_0/IO0/OMM PIO_nable U- TVQ O XR_IO0/0/ommtn TI U- TVQ U- TVQ /IO to TI_STTN O XR_IO/SPI_TTN TI_SMT_/IO O XR_IO/ XR RIO U- TVQ TI_SMT_/IO 0 O XR_IO/ TP NO MOR TN 0 m from.v_out/in on XR module XR_.V_IN_RY TI_RST_Openollector Switch used as inverter for.v_in use to control Reset to US disconnect.v U- TVQ O R 0 XR_.V_IN U- TVQ O 00n R 0 R0 XR_.V_IN XR_RST _RST TI_SMT_/IO O c igi International Inc. 0 ll rights reserved O NOT S RWIN RV O PPROVS: SIN: RWN: : NINR: U- TVQ O SRIPTION O N T: // atwyler TIT PRT NO. XR_IO/ Y PPR T XR evelopment oard -U Isolation Switches SPI, PIO 00-0 ST RV. of

10 0 TI_SMT_IO PIO_nable U- TVQ O XR_IO.V isable PIO ontrol isable PIO if unit.v_in is shutdown See note N_PIO_to_TI U- 00PW PIO_nable TI_SMT_IO U- TVQ O uplicated with URT XR_IO//PWM/TR XR_.V_IN S O0 Q S O0 Q XR_.V_IN_RY U- TVQ 00 R 00 R TI_ON/SP/IO 0 O XR_IO/ON_SP U0- TVQ U- TVQ TI_S PIO_nable O reserved U TI_SSO/IO O XR_IO/SSO U0- TVQ TI_RSSI_PWM/IO0 0 U- TVQ O XR_IO0/PWM RSSI/0 TI_MOSI O reserved W TI_PWM/IO U- TVQ O XR_IO/PWM/ TI_MISO 0 U0- TVQ O reserved V.V Used s Inverter - V tolerant input R This pin can be up to V if switch is in middle position U0- TVQ TI_S_ON_WRIT VR_.0V U- MVIPWR 0 -. and XR_Shutdown is connected to V through eader P XR_SUTOWN_TI_TO_SWIT TI_SS O reserved_0_w TI_S_ON_R U- 00PW This pin can be up to V XR_SUTOWN RV O SRIPTION O N Y PPR T TIT PPROVS: T: O c igi International Inc. 0 ll rights reserved O NOT S RWIN SIN: RWN: : NINR: // atwyler PRT NO. XR evelopment oard -U Isolation Switches PIO 00-0 RV. ST 0 of

11 0 XR_V XR_.V_UST reserved U reserved W reserved V reserved_0_w 0u/0V XR_IO/SPI_TTN XR_IO/SPI_SS/x XR_IO/SPI_SI/x XR_IO/SPI_SO/x XR_IO/SPI_/x XR_IO/TS XR_IO/RTS XR_IO/OUT XR_IO/IN/ONI 0 u XR_V XR_.V_OUT.M R 0u 00n y. p.p XR_V (Pin# 0) maps to XR_onnector pin xcept for reserved pins on,,, and P TSW u XR_.V_IN XR_RST XR_IO0/0/ommtn XR_IO/ XR_IO/ XR_IO/ XR_IO XR_IO/SSO XR_IO/TR/SP_RQ XR_IO/ON_SP XR_VR XR_IO0/PWM RSSI/0 XR_IO/PWM/ XR_IO//PWM/TR XR_SUTOWN XR_V 0u 00n y. p.p.v UST leave open NO TRM RI ON NY YR VIS IN XPOS MT MUITP VIS TROU ROUN YRS (US VY N "STIT") reserved_ reserved_ reserved U reserved W XR_V XR_.V_OUT XR_.V_UST T/SW TO/SWO XR_TI TMS/SWIO XR_IO/SPI_TTN XR_IO/SPI_SS/x XR_IO/SPI_SI/x XR_IO/SPI_SO/x XR_IO/SPI_/x XR_IO/TS XR_IO/RTS XR_IO/OUT XR_IO/IN/ONI reserved_0 reserved_ holes for standoffs ayout for PIe mini card XR Radio dge onnector S0-SN R reserved_ reserved_ XR_V reserved V reserved_0_w Note XR_.V_IN XR_.V_OUT XR_RST XR_IO0/0/ommtn XR_IO/ XR_IO/ XR_IO/ XR_IO XR_IO/SSO XR_IO/TR/SP_RQ XR_IO/ON_SP XR_VR XR_IO0/PWM RSSI/0 XR_IO/PWM/ XR_IO//PWM/TR XR_TR_ XR_SUTOWN XR_V reserved_ reserved_ XR_V.p u 0u 00n p y. RV O SRIPTION O N Y PPR T TIT PPROVS: T: O c igi International Inc. 0 ll rights reserved O NOT S RWIN SIN: RWN: : NINR: // atwyler PRT NO. XR evelopment oard -U XR Module onnector 00-0 RV. ST of

12 0 TST POINTS V TP reserved_ reserved_ TP TP US_V_POWR_IN TP reserved_ TP.V TP reserved_ TP XR_V TP TP.V_TI TI_V TP0 TP S TP TP TP S TP0 TP 00-0 S The T/SW pins are referenced to. V from the XR. This must be here for proper T/SW operation. XR_.V_IN XR_T_V Y remove N P TS-0-0--V- 0 0 TMS/SWIO T/SW TO/SWO XR_TI XR_RST XR_TR_ reserved_0 reserved_ reserved_ reserved_ RV O SRIPTION O N Y PPR T TIT PPROVS: T: O c igi International Inc. 0 ll rights reserved O NOT S RWIN SIN: RWN: : NINR: // atwyler PRT NO. XR evelopment oard -U Test Points 00-0 RV. ST of

13 0 Notes. The T chip has separate I/O ports. ach of these ports can be set to different modes at any time. Only one mode can be set on a port at a time. ll of the ports can be set to serial, asynchronous bit-bang, or synchronous bit-bang. Only ports and can be set to MPSS mode, which includes SPI, I, and T modes. The default state for all of the ports will be URT for first time plug in. This cannot be changed until after programming PROM.. The T chip supports two modes for the SPI clock. The first mode supports speeds from z to Mz and follows the equation below ( is the clock divisor and must be an integer: f = Mz / ( * ( )) The other mode can handle speeds between 0 z and 0 Mz and follows the equation below: f = 0 Mz / ( * ( )) The MOSI and MISO lines are synchronous with the SPI clock. ll of the other PIO pins are not.. Since the TI chip is powered by.v. The XR.V_IN must be limited between to.v when connections are enabled. To test the XR at a lower voltage, all TI connections must be disabled, with XR_nShutdown low. n external supply can be inserted to.v_in as long as it complies with Manual requirements and signal integrity is observed.. If.V_IN is low all IO pins must be tri-state or low. Pullups are not allowed in this state.. Signal integrity should always be observed on all pins. ONY V pins and XR_SUTOWN can receive volages higher than.v_in. ll digital lines are based off of.v_in.. V supply is still needed for XR module to receive or transmit regardless of what voltage is on.v_in RV O SRIPTION O N Y PPR T TIT PPROVS: T: O c igi International Inc. 0 ll rights reserved O NOT S RWIN SIN: RWN: : NINR: // atwyler PRT NO. XR evelopment oard -U Notes 00-0 RV. ST of

14 P R0 SW R R R S P P 0 0 R R0 U R R U0 U U U U R0 U U R Q R R R R R R0 R R 0 R R R R R 0 R R P R S R S R S R0 S R R Q SW R R 0 U U0 R R 0 R0 Q SW R R U R R R 0 0 R R U P U R R R R R R Q Q R S R U Y R 0 TP R SW ON R R R R Q U U R R SW 0 R R R R R 0 R R0 R R S S S S 0 S S P Note: ll testpoints on bottom side - no solder allowed on pads. RV O SRIPTION O N Y PPR T PPROVS: T: TIT SIN: RWN: XR V TOP SSMY : NINR: PRT NO. RV. co igi International Inc. ll rights reserved 00-0 O NOT S RWIN ST of

15 TP TP TP TP TP TP TP TP0 TP TP TP TP TP0 TP TP0 TP TP TP0 TP TP RV O SRIPTION O N Y PPR T PPROVS: T: TIT SIN: W 0// XR V RWN: OTTOM SSMY : NINR: co igi International Inc. ll rights reserved PRT NO O NOT S RWIN ST of RV.