# Exploring Autonomous Memory Circuit Operation

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1 Exploring Autonomous Memory Circuit Operation October 21, 2014

2 Autonomous Au-to-no-mous: Merriam-Webster Dictionary (on-line) a. Existing independently of the whole. b. Reacting independently of the whole. An autonomous non-volatile memory operates by itself or is part of a larger system but still operates independently from that system.

3 Summary The purpose of this presentation is to reduce the mysteries of how autonomous memory works. This presentation is a visual summary of the design principles for autonomous memory described in Radiant s applications note Design for Integrated Circuits. Please read that application note of an in-depth discussion of autonomous memory and its applications. It may be found on Radiant s web site.

4 Contents The response of a ferroelectric capacitor as a component in an electrical circuit will be explored: a) Simple Resistor-Capacitor circuit. b) The more complex Resistor-Capacitor-Transistor circuit. c) The non-latching memory circuit and its internal node voltages. d) The latching autonomous memory.

5 Introduction The autonomous ferroelectric memory embeds ferroelectric capacitors into a Resistor-Capacitor-Transistor circuit. To understand the internal operation of the autonomous memory, we must first learn how a ferroelectric capacitor interacts with a series resistor. We must go from: V out

6 Summary The autonomous ferroelectric memory embeds ferroelectric capacitors into a Resistor-Capacitor-Transistor circuit. To understand the internal operation of the autonomous memory, we must learn how a ferroelectric capacitor interacts with a series resistor. We must go from: to: V out V out

7 Test Methodology The circuit below was used to capture the output voltages from the RC, RC FE, and RC FE X circuits on the measured data plots in this presentation.. DRIVE + - OSC The high input impedance of the op amp prevents the measurement circuit from interfering with the operation of the RC circuit. RETURN (Virtual Ground)

8 R C V o u t Classic RC C = 100pF R = 15M Measured Vout t RC ( 1 e ) V pwr V out T i m e ( m s )

9 Volts Classic RC C = 100pF R = 15M Numerical solution Vout RC = 1.5ms t RC ( 1 e ) pF Seconds

10 Volts Classic RC C = 100pF & 1nF R = 15M Numerical Solution Vout t RC ( 1 e ) nF 100pF Seconds

11 P o l a r i z a t i o n ( µ C /c m 2 ) Ferroelectric Capacitor What is the capacitance of a ferroelectric capacitor? Vo ltag e

12 C a p a c i t a n c e (µ F ) Ferroelectric Capacitor Take the mathematical derivative: C P V Area Q V Hy steresis Data V oltag e Instantaneous capacitance increases dramatically during switching.

13 C a p a c i t a n c e ( µ F ) Ferroelectric Capacitor Model For a simple model, create a 2-level capacitor to represent the ferroelectric capacitor when it switches. Hysteresis Data Cap 2 Cap 1 Voltage Use only Cap 1 for all voltages when the capacitor does not switch.

14 Volts RC FE C FE = Use higher capacitance from 2.2 volts to 2.9 volts R = 15M Numerical Solution Vout t RCFE ( 1 e ) 10 9 Non-switching C FE Model Switching C FE Model 2 1 1nF 100pF Seconds

15 R C V o u t A Real RC FE C = 400 µm Å-thick 20/80 PZT R = 15M Measured T i m e ( m s ) R C A B M o h m 9 V R C A B M o h m 9 V Defined as the Shelf Voltage.

16 nc Switching vs Non-Switching The two loops below are the half loops that created the two traces on the previous slide. The colors match. Half Lo o p UP: Po lar izatio n (µc/c m 2) Half Lo o p DOWN: Po lar izat io n (µc/c m2) Vo lts

17 Add a Transistor A transistor added to the RC FE circuits provides negative feedback to Vout. Conductive Load C FE V out C FE V out T1 T1 D T1 M The transistors are arranged so that all current through the ferroelectric capacitors passes into the transistor control inputs but the current through the conductive load splits between the ferroelectric capacitor and the transistor. These circuits form the most basic autonomous memories!

18 What does the Transistor Do? Both circuits with and without a transistor have exactly the same shape to their response. The transistor in the circuit on the right makes its circuit response slower than the response of the RC FE circuit without the transistor on the left. V out C FE V out T1 This characteristic is true for whatever technology is used for T1 as long as the conductivity of T1 is controlled by the current on its input.

19 What does the Transistor Do? First apply equal V pwr to both circuits. Stop time so V out is the same for both circuits. Then: 1) Current through the Resistor of both circuits will be the same. a) I = (-Vout)/R 2) All of the current in the RC FE circuit goes into the capacitor. 3) Most of the current in the transistor circuit goes through the transistor. Much less goes through the capacitor. R V out V pwr = V pwr V out = V out C FE R T1 V out The ferroelectric capacitor in the transistor circuit will charge more slowly!

20 The Math Vout (1 e t ( 1 gain) RCFE ) The expression for V out is simple! The expression for C FE is very complex and can only be exactly solved numerically. The simplest approach is to 1. Measure the half-hysteresis of the target C FE. 2. Do the mathematical derivative as shown earlier. 3. Import the derivative into SPICE as a piece-wise linear capacitor.

21 R C X V o u t RC FE vs RC FE X C = 400 µm Å-thick 20/80 PZT R = 15M β = 2 Measured Blue dashed = RC FE. Vout (1 e t ( 1 gain) RCFE Red solid = RC FE with transistor. ) R C A B M o h m 9 V R C A B M o h m 9 V R C X A B M o h m 9 V R C X A B M o h m 9 V (1+β) = 3 V threshold for the transistor causes this gap T i m e ( m s )

22 Dynamic Circuit Operation In the next section, we will examine the dynamics of autonomous memory operation and how the circuit interfaces to logic. We will start with a non-latching Autonomous Event Detector having a non-inverting buffer on its output and then move to the latching Autonomous Latch.

23 Event Detector Logic Buffer Event R Sense C FE R in T1 T2 R out Logic Out The Autonomous Event Detector connects the ferroelectric capacitor in the simple autonomous memory circuit to an outside event sensor that generates power when the event occurs. The energy from the event switches the ferroelectric capacitor DOWN. The Logic Buffer outputs ground except when a voltage has developed across R sense.

24 Basic Operation A voltage generated by Event turns on the input diode, turns on T1, and switches C FE DOWN through T1. Event C FE R in R Sense A T1 T2 R out Logic Buffer Logic Out Applying reads the capacitor state by causing the voltage at A to rise to. The Logic Out buffer will see the Shelf Voltage if it occurs.

25 Signal Interpretation After every time is applied, the ferroelectric capacitor is left in the UP direction. Every read is a Reset. The ferroelectric capacitor can only be set DOWN by an Event. Every time the circuit is powered up, a read takes place: If the shelf voltage occurs, the ferroelectric capacitor was DOWN before was applied. An event occurred since the last read operation. If the shelf voltage does not occur, then the ferroelectric capacitor was UP before was applied. An event did not occur since the last read operation.

26 Buffer Operation T2 of the output buffer turns on if the voltage on its gate at A falls below by a magnitude greater than its V threshold. If T2 is ON, Logic Out is connected to. R Sense Logic Buffer If T2 is OFF, Logic Out is pulled to ground by R out Event C FE A T1 T2 Logic Out Clearly, Logic Out will go HIGH if an Event occurs because the shelf voltage is generated. R in R out But, Logic Out may or may not go High if no Event occurred.

27 Steep If steps immediately to the power voltage faster than the rise time at A for a non-switching situation, T2 will turn on until A approaches within VThreshold of. See the area in the plot denoted by the blue arrows. RC AD103A 1Mohm 3V RC AD103A 1Mohm 3V 3.0 Logic Buffer 2.5 RC Vout RSense 1.0 CFE 0.5 A T Time (ms) T1 Event Rin Logic Out Logic Out µp Digital Input Rout

28 RC Vout Steep The switching trajectory causes Logic Out to go HIGH for much longer than the non-switching trajectory. The microprocessor monitoring Logic Out should capture its value at a time when Logic Out would be ground for a non-switching situation. RC AD103A 1Mohm 3V RC AD103A 1Mohm 3V Logic Buffer C FE R Sense A µp T Time (ms) Event T1 Logic Out Digital Input Logic Out R in R out Read Here!

29 RC Vout Ramped If the Logic Buffer drives the clocked input of a latch, Logic Out cannot not go high during the read if the event did not occur or the latch will latch false. In that case, ramp slower than the non-switching rise but faster than the Shelf Voltage! RC AD103A 1Mohm 3V RC AD103A 1Mohm 3V 3.0 Logic Buffer 2.5 R Sense C FE A T2 Latch Event T1 Logic Out 0.0 R in R out Logic Out Time (ms) Logic Out will only go high for the Shelf Voltage.

30 Vpower Executes the Read The application of power to the top of the basic autonomous memory circuit always executes a read operation. In some cases, power can rise much faster than either of the RC time constants of the circuit without causing an error. In other cases, the power must rise more slowly in order to accurately execute a read operation when the circuit output drives a clocked input. In no case can power rise as slow or more slowly than the length-in-time of the shelf voltage!

31 Self-Latching Logic Buffer R Sense C FE T2 Logic Out Event T1 R in R out Instead of putting out a logic state that affects a follow-on latch, the Logic Out signal can be fed back to T1 to latch the autonomous circuit!

32 Self-Latching Logic Buffer If Logic Out is LOW: C FE R Sense A T2 Logic Out T1 will remain OFF, A will got to, T2 will be OFF, and Logic Out is held LOW. Event R in T1 Both states are stable conditions that will remain unchanged as long as is applied. R out If Logic Out is HIGH: T1 will be forced ON, A will be pulled to ground T2 will be ON, and Logic Out is held HIGH.

33 Self-Latching Event Detector C FE R Sense A T2 Logic Buffer Logic Out for this latching Event Detector must be a ramp because Logic Out will latch LOW anytime A falls away from. Event R in T1 R out If C FE is UP, the latch will always power up with Logic Out LOW unless an Event occurred while the circuit was powered OFF. If an Event did occur while was OFF, then C FE will be DOWN when is applied, the Shelf Voltage will occur, T2 will turn on and Logic Out will go HIGH. Once an Event has occurred, the latch will always power up with Logic Out HIGH unless an external signal (not shown) resets the latch LOW.

34 Autonomous Latch Input Input Enable T2 C FE R in R Sense A T1 Output The Logic Buffer can be moved to the other side of the ferroelectric capacitor, the Event input replaced with an Input switch, and an Input Enable control added to create an autonomous ferroelectric non-volatile latch that can be used in any digital circuit to provide local, autonomous nonvolatile memory. When is applied, the internal signals in the autonomous latch will rise exactly the same as with the latching and non-latching Event Detectors we studied earlier in this document until the transistors decide to latch. The amplification by the transistors is so high they will overwhelm the read signals once the latching threshold is reached.

35 Autonomous Latch R Sense Input T2 C FE A T1 Output Input Enable R in The autonomous latch can be set to either the HIGH or LOW output state by putting a voltage into the Input with the input switch closed in order to force T1 to the desired state of ON or OFF. Once set, the latch will remain in that state until changed or power is removed.

36 Automatic Rewrite R Sense Input T2 C FE A T1 HIGH T1 and T2 are OFF! Input Enable R in C FE is held UP by the latch! Once the latch has been forced into the desired state, C FE will automatically be rewritten into the proper direction UP or DOWN so that when is removed and reapplied later, the latch will come up into its last assigned state!

37 Automatic Rewrite R Sense Input T2 C FE A T1 LOW T1 and T2 are ON! Input Enable R in C FE is held DOWN by the latch! Once the latch has been forced into the desired state, C FE will automatically be rewritten into the proper direction UP or DOWN so that when is removed and reapplied later, the latch will come up into its last assigned state!

38 Latch Summary The latching autonomous memory circuit: a) Will read the memory state of its ferroelectric capacitor when the circuit powers up and restore the original latch output state. b) Will automatically re-write the original ferroelectric capacitor memory state. c) Will allow its state to be set by an external input and will force the ferroelectric capacitor to memorize the new state. d) Will retain the memorized state without power.

39 Flexibility Certain components were used in certain positions in the exampled circuits of this presentation. These example circuits are not the only possible configurations. There are hundreds of other possibilities, for instance replacing R sense with a C sense or replacing the FET transistors with bipolar transistors, thin film transistors, or even relays!

40 Closing In this document, we explored a) The response of a ferroelectric capacitor in series with a resistor: it develops a shelf when it switches! b) Adding a transistor to an RC FE circuit to slow down both the non-switching and the switching waveforms. c) The voltage waveform generated at every node in a non-latching Event Detector as power rises on the circuit. The voltage signal at each node depends upon the memory state of the ferroelectric capacitor! d) How to convert a non-latching autonomous memory circuit to a self-restoring autonomous latch!

### An Autonomous Nonvolatile Memory Latch

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