TWR-MPC8309 Schematic

Transcription

1 TWR-MP0 Schematic SHEMTI PGE ESRIPTION: 0: over 0: Reset, lock and Switch 0: R and NOR Flash Memory 0: el, Latch, uffer and Logics 0: isplay, S ard and N 0: Ethernet Interface and lock 0: Ethernet PHYs and RJ 0: US Interface and US PHY 0: RS, RS and RS MUX 0: PI Interface and Mini PI onnector : Primary and Secondary Elevators : oldfire MU, IEEE, JTG and I evice : udio OE : MP ecoupling : Power Supplies MJOR REVISION HISTORY: P REV. SM REV. ESRIPTION TE 0 Initial Version //0 Production Version //0 Modify udio 0//0 P MEHNIL ETILS: : P SIZE: 0mm x 0mm : P MTERIL: FR : NUMER OF LYERS: 0 : IMPEENE ONTROL: YES NOTES, UNLESS OTHERWISE SPEIFIE:. RESISTNE TOLERENE IS % IF NOT SPEIFIE. PRTS NOT INSTLLE RE INITE WITH 'NP'.. SIGNL NET NMES WITH "#" SUFFIX, RE TIVE LOW SIGNLS.. PKGE SIZE FOR ESRETES IS "00" IF NOT SPEIFIE VOLTGE RIL NOTTION PWR RIL ESRIPTION +V.0V Input voltage from sources +V_ELEV.0V Input/output voltage to/from tower system +.V.V MP & Other I/O Voltage +.V_ELEV.V Output to Tower system +.V.V MP & R I/O voltage +.0V.0V MP ore Voltage I RESS ETILS. udio OE, SGTL000 = 0x0. igital ccelerometer, MM = 0x. MPR on isplay Module = 0x (R pin = V) OMPONENT MOUNT / UNMOUNT NOTTIONS: NOTTION (IN "MOUNTING" PROPERTY FIEL) MOUNTING INSTRUTIONS LNK OMPONENT TO E POPULTE NP NOT POPULTE over page Size ocument Number Rev TWR-MP0 Thursday, November, 0 ate: Sheet of

2 MP RESET, LOK & Switch +.V F LMSGTN MP_JTG_TK MP_JTG_TI MP_JTG_TO MP_JTG_TMS MP_JTG_TRST# 00nF R OS.K TRI_STTE V _ OUT.MHZ R +.V R R SYSLK R P P U SYS_LK_IN SYS_XTL_IN SYS_XTL_OUT TK TI TO TMS TRST_ E MP_JTG_TK MP_JTG_TI MP_JTG_TO MP_JTG_TMS MP_JTG_TRST# R.K R0.K R.K R.K R.K +.V IEEE lock Generation +.V.K R K-NP FG_LKIN_IV V U RT_PIT_LOK FG_LKIN_IV_ TEST_MOE THERM0 E THERM0 F LMPSN nF-NP 00nF-NP OS V_VXO MP_QE_LK_IN MP_QE_LK_IN R QE_LK_IN QUIESE_ QUIESE#, F_VOOX V_TRL V INH# N TP OUT R R MP_TMR_LK,,, MP_HRESET#, MP_POR# W W HRESET_ PORESET_ VTEUMJNF-0M MP0 +.V F LMSGTN 00nF R.K OS TRI_STTE V _ OUT +.V F LMPSN R R 00nF U NNRG -SOI V OE ILK Q Q Q Q R R0 R R R R R R MP_QE_LK_IN F_LK_IN SYS_MLK US_LKIN Reset onfiguration Words Source +.V 00nF 00nF S SW P S SW P R.K O_OOT_ONFIG0 O_OOT_ONFIG O_OOT_ONFIG O_OOT_ONFIG MP_POR# MP oot MUX +.V +.V +.V SWP MP_IRQ# R R R R.K.K-NP.K.K +.V U V MR# RESET# MITUY MHZ R.K,, O_OOT O_OOT_ONFIG0 MP_HL_TX_OOT_FG0 O_OOT_ONFIG MP_HL_RTS#_OOT_FG R.K +.V When IN=0, =S oot from on board NOR flash When IN=, =S oot from S card U +.V 00nF MP_HRESET# O_RV_NOR_LS# O_OOT I S V, MP_L_S0# I0 Y NOR_FLSH_S#, U IN S S S S TSV0PW LVG V EN S S S 0 S 0nF O_OOT_ONFIG MP_HL_RTS#_OOT_FG, O_OOT_ONFIG MP_HL_TX_OOT_FG, FG_RESET ESRIPTION SOURE[0:] 0000 RW from el NOR (efault ) 000 RW from el NN (small page -bit) 000 Reserved 00 Reserved 000 RW from I 00 RW from el NN (large page -bit) 00 Reserved 0 Reserved 000 RW hard-coded, boot from el 00 RW hard-coded, boot from el 00 RW hard-coded, boot from el 0 RW from el NOR 00 RW hard-coded, boot from el 0 RW hard-coded, boot from esh (O_OOT default) 0 RW hard-coded, boot from esh RW hard-coded, boot from SPI R R0 R R.K-NP.K.K-NP.K-NP When S=0, S0# = ON OR FLSH S When S= S0# = OFF OR S Reset, lock and Switch Size ocument Number Rev TWR-MP0 Wednesday, October, 0 ate: Sheet of

3 R Memory NOR FLSH MP_R_VREF MP_R_QS0 MP_R_QS MP_R_QS MP_R_QS MP_R_M0 MP_R_M MP_R_M MP_R_M MP_R_KE MP_R_0 MP_R_0 MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_0 MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_0 MP_R_ MP_R_VREF MP_R_ MP_R_ MP_R_ MP_R_ MP_R_0 MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_0 MP_R_ MP_R_K MP_R_K# MP_R_K MP_R_K# MP_R_S0# MP_R_OT0 MP_R_S# MP_R_RS# MP_R_WE# MP_R_S0# MP_R_KE MP_R_0 MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_0 MP_R_ MP_R_ MP_R_M0 MP_R_ MP_R_ MP_R_0 MP_R_ MP_R_ MP_R_S# MP_R_RS# MP_R_OT0 MP_R_ MP_R_WE# MP_R_ MP_R_0 MP_R_ MP_R_QS0 MP_R_ MP_R_0 MP_R_ MP_R_ MP_R_ MP_R_WE# MP_R_VREF MP_R_S# MP_R_RS# MP_R_ MP_R_ MP_R_ MP_R_ MP_R_S0# MP_R_KE MP_R_OT0 MP_R_0 MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_0 MP_R_ MP_R_M MP_R_QS MP_R_ MP_R_ MP_R_0 MP_R_ MP_R_QS MP_R_M MP_R_QS MP_R_M MP_R_M MP_R_QS MP_R_E MP_R_E MP_R_E MP_R_E MP_R_E MP_R_E0 MP_R_E MP_R_E MP_R_K MP_R_K# MP_R_K MP_R_K# MP_L_RE/OE# MP_L_WE0# MP_L_ MP_L_ MP_L_ MP_L_ MP_L_ MP_L_ MP_L_ MP_L_ MP_L_ MP_L_0 MP_L_ MP_L_ MP_L_ MP_L_ MP_L_ MP_L_ MP_L_ MP_L_0 MP_L_ MP_L_ MP_L_ MP_L_ MP_L_ MP_L_ MP_L_L0 MP_L_L MP_L_L MP_L_L MP_L_L MP_L_L MP_L_L MP_L_L0 MP_L_L MP_L_L MP_L_L MP_L_L MP_L_L MP_L_L MP_L_L MP_L_L MP_R_ MP_R_ MP_R_ MP_R_ MP_R_0 MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_0 MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_0 MP_R_ MP_R_ MP_R_ MP_R_ MP_R_ MP_R_K MP_R_K# MP_R_K MP_R_K# +.V +.V +.V +.V +.V +.V +.V +.V +.V MP_POR#, MP_L_[:0],, MP_L_[:0],, MP_L_RE/OE#, MP_L_WE0#,, NOR_FLSH_S#, MP_L_L[0:] Size ocument Number Rev ate: Sheet of TWR-MP0 R and NOR Flash Memory Wednesday, October, 0 Size ocument Number Rev ate: Sheet of TWR-MP0 R and NOR Flash Memory Wednesday, October, 0 Size ocument Number Rev ate: Sheet of TWR-MP0 R and NOR Flash Memory Wednesday, October, 0 R.K uf 00 R.K U HPSFFR-S FG Q E Q H J Q Q Q F Q H VL J N Q Q Q Q F Q G Q H Q Q0 Q0 E Q H L J M N P Q Q Q Q F Q0 G Q H 0 M N P Q Q Q F Q H OT K P 0 M N P R M N P UQS LQS F RS# K S# L UQS# / NU LQS / NU E S# L K J K# K KE K WE# K 0 L L N R RFU R L RFU R N N E UM LM F VREF J VQ VQ E VQ G VQ VQ VQ G VQ G VQ VQ VQ0 G V M V J V V E V R 00nF uf 00 00nF 00nF 00nF 00nF 00nF 0 00nF 00nF R0.K R nF uf 00 0uF 00 00nF 00nF 00nF 00nF 00nF R 0 00nF R K 00nF U HPSFFR-S FG Q E Q H J Q Q Q F Q H VL J N Q Q Q Q F Q G Q H Q Q0 Q0 E Q H L J M N P Q Q Q Q F Q0 G Q H 0 M N P Q Q Q F Q H OT K P 0 M N P R M N P UQS LQS F RS# K S# L UQS# / NU LQS / NU E S# L K J K# K KE K WE# K 0 L L N R RFU R L RFU R N N E UM LM F VREF J VQ VQ E VQ G VQ VQ VQ G VQ G VQ VQ VQ0 G V M V J V V E V R 00nF U MXGLE 0 0 WE RESET RY/Y 0 0 VPP/WP# 0 E OE Q0 Q Q Q Q Q0 0 Q Q V Q Q Q Q Q Q Q 0 Q/- YTE VIO N N N 0 N N 00nF 00nF 00nF 00nF 00nF 00nF MP0 U MEM_MQ0 U MEM_MQ MEM_MQ W MEM_MQ R MEM_MQ W MEM_MQ U MEM_MQ U MEM_MQ T MEM_MQ H MEM_MQ H MEM_MQ0 G MEM_MQ F MEM_MQ G MEM_MQ F MEM_MQ F MEM_MQ E MEM_MQ V MEM_MQ Y MEM_MQ Y MEM_MQ U MEM_MQ0 V MEM_MQ R MEM_MQ U MEM_MQ T MEM_MQ J MEM_MQ G MEM_MQ G MEM_MQ F MEM_MQ E MEM_MQ MEM_MQ0 MEM_MQ MEM_ME0 Y MEM_ME MEM_ME Y MEM_ME MEM_ME MEM_ME MEM_ME Y MEM_ME MEM_MM0 W MEM_MM E MEM_MM V MEM_MM MEM_MM W MEM_MQS0 T MEM_MQS H MEM_MQS P MEM_MQS E MEM_M QS V MEM_M0 K MEM_M K MEM_M N MEM_M0 L MEM_M L MEM_M L MEM_M L MEM_M M MEM_M M MEM_M M MEM_M N MEM_M N MEM_M N MEM_M0 L MEM_M P MEM_M N MEM_M P MEM_MWE_ J MEM_MRS_ K MEM_MS_ J MEM_MS_0 J MEM_MS_ K MEM_MKE P MEM_MK0 R MEM_MK R MEM_MK_0 T MEM_MK_ P MEM_MOT0 H MEM_MOT H MEM_MVREF M 00nF R K uf 00 00nF

4 ,, MP_L_[:0] MP_L_ MP_L_ MP_L_ MP_L_ MP_L_0 MP_L_ MP_L_ MP_L_ MP_L_ MP_L_,, MP_O_SPI_MOSI,, MP_O_SPI_MISO,, MP_O_SPI_LK MP_SPI_SEL MP_SPI_SEL_OOT# MP_I_S MP_I_SL,,, MP_I_S,,, MP_I_SL, MP_LK0 R R lose to TX side U MP0 0 L L L E L L0 L 0 L L L L E SPIMOSI E SPIMISO SPILK SPISEL SPISEL_OOT_ 0 0 II_S II_SL 0 II_S /KSTOP_OUT_/ II_SL/KSTOP_IN_/ E LLK0 MP el L0 L L L L E0 L L L 0 L L L0 L E L L L 0 L LS_0 LS_ LS_ LS_ LGPL0/LFLE LGPL/LFLE LGPL/LOE_/LFRE_ LGPL/LFWP_ LGPL/LGT_/LUPW E LGPL LWE_0/LFWE_0/LS_0 LWE_/LS_ LTL LLE URT_SIN URT_SOUT Y URT_SIN/URT_TS_/ W0 URT_SOUT/URT_RTS_/ MP_L_L0 MP_L_L MP_L_L MP_L_L MP_L_L MP_L_L MP_L_L MP_L_L MP_L_L MP_L_L MP_L_L0 MP_L_L MP_L_L MP_L_L MP_L_L MP_L_L MP_L_S0# MP_L_S# MP_L_S# MP_L_S# MP_L_LE MP_L_LE MP_L_RE/OE# MP_L_WP# MP_L_R# MP_L_GPL MP_L_WE0# MP_L_WE# MP_LTL MP_LLE +.V R R R R MP_L_L[0:] MP_L_S0#, MP_L_S# MP_L_S# MP_L_S# MP_L_LE MP_L_LE MP_L_RE/OE#, MP_L_WP# MP_L_R# MP_L_GPL MP_L_WE0#,, MP_L_WE# MP_LTL MP_LLE MP_URT_RX MP_URT_TX MP_URT_TS# MP_URT_RTS# MP_L_L0 MP_L_L MP_L_L MP_L_L MP_L_L MP_L_L MP_L_L MP_L_L MP_LLE MP_L_L MP_L_L MP_L_L0 MP_L_L MP_L_L MP_L_L MP_L_L MP_L_L MP_LLE Latches +.V U MP_L_0 Q MP_L_ Q MP_L_ Q MP_L_ Q MP_L_ Q MP_L_ Q MP_L_ E Q E MP_L_ Q OE V LE V E N N N N LVHZRR +.V U E E MP_L_ F Q F MP_L_ F Q F MP_L_0 G Q G MP_L_ G Q G MP_L_ H Q H MP_L_ H Q H MP_L_ J Q J MP_L_ Q J G J OE V G LE V F E F J J H N N H N N LVHZRR MP_L_[:0],, MP_L_L0 MP_L_L MP_L_L MP_L_L MP_L_L MP_L_L MP_L_L MP_L_L T_US_OE# MP_LTL MP_L_[:0],, MP_L_L MP_L_L MP_L_L0 MP_L_L MP_L_L MP_L_L MP_L_L MP_L_L T_US_OE# MP_LTL uffers +.V MP_L_[:0], U MP_L_0 MP_L_ MP_L_ MP_L_ MP_L_ MP_L_ MP_L_ E E MP_L_ +.V OE V IR V 0 E 0uF00 00nF 00nF 00nF 00nF N N N N LVHZRR +.V MP_L_[:0], U E E MP_L_ F F MP_L_ F F MP_L_0 G G MP_L_ G G MP_L_ H H MP_L_ H H MP_L_ J J MP_L_ J G J OE V G +.V IR V F E F H J 0 J N N H N N 0uF00 00nF 00nF 00nF 00nF LVHZRR +.V, I ddress. SGTL000 = 0x0. MM = 0x. MPR on isplay Module = 0x (R pin = V) NOR_FLSH_S# MP_L_S# MP_IRQ# MP_IRQ0# MP_IRQ# MP_IRQ# R R R R U0 I0 I MVHG00FTG U MLVX0TG V O +.V T_US_OE# U MLVX0TG U MLVX0TG U MLVX0TG U MLVX0TG 00nF 0 MP Interrupt U MLVX0TG 00nF U 00nF U MLVX0TG U MLVX0TG U MLVX0TG 0 IRQ_0_MP_IN_ IRQ_/MP_OUT_/ IRQ_/KSTOP_IN_/ IRQ_/KSTOP_OUT_/INT_/ 00nF +.V R R0 R R R R R R R R R R0 R R R.K.K.K.K.K.K.K.K.K.K.K.K.K.K.K U MLVX0TG U MLVX0TG 0 E E.K.K.K.K MP_L_L[0:] +.V MP_L_L[0:] MP_IRQ0# U MP_IRQ# MP_IRQ# MP_L_L E E MP_SPI_SEL0 MP_IRQ# MP_L_L F Q F MP_SPI_SEL MP_L_L0 F Q F MP_SPI_SEL MP_L_L G Q G MP_L_L G Q G ISPLY_TRL +.V MP_L_L H Q H ISPLY_RESET MP_L_L H Q H MP F_IRQ MP_SPI_SEL R0.K MP_L_L J Q J MP_RST_TWR# MP_O_SPI_LK R.K Q MP_O_SPI_MISO R.K J G MP_O_SPI_MOSI R.K WRITE J OE V G MP_L_WE0# R.K LE V MP_L_WE# R.K F E MP_L_RE/OE# R.K F MP_L_WP# R.K MP_L_R# R.K J J MP_L_S0# R0.K H N N H MP_L_S# R.K N N MP_L_S# R.K LVHZRR MP_L_S# R.K MP_I_S R.K MP_I_SL R.K MP_I_S R.K MP_I_SL R.K +.V MP_SPI_SEL_OOT# R.K MP_L_L[0:] U MP_L_L0 LE0 MP_L_L Q LE MP_L_L Q LE MP_L_L Q LE/RS SEL MP_L_L Q LE MP_L_L Q LE MP_L_L Q LE MP_L_L E Q E LE/RS SEL Q +.V OE V LE V E U MP_L_S# 0nF I0 V FE_INT# N N,, MP_L_WE0# I MP_L_S# WRITE N N FE_INT# O LVHZRR, MP_L_RE/OE# FE_INT# MVHG0FTG MPR MP_IRQ# MMQ MP_IRQ# LE0 R F MP_IRQ# 0 LE R SWP MP_IRQ# SPI Routing ecode LE R ELEV_PI_INT# LE/RS SEL R +.V +.V LE R MP_PI_INT# 0, R LE R LE R O MP_I_IRQ#.K U 00nF O MP_SPI0_IRQ# LE/RS SEL R MP_SPI_SEL0 0 O MP_SPI_IRQ# MP_SPI_SEL V MP F_SP0_SS MP_SPI_SEL O0# MP O_SPI_SEL0 O# E# MP O_SPI_SEL R.K O# E# MP O_SPI_SEL O# O MP_SPI_IRQ# E MP ISPLY_SPI_SEL O# 0 O# O# O MP_F_SPI_IRQ# O# MLXTG US_INT# R.K R.K R0.K R.K R.K R.K U MP_L_L E E O MP_SPI0_IRQ# MP_L_L F F O MP_SPI_IRQ# MP_L_L0 F F O MP_SPI_IRQ# MP_L_L G G F MP_IRQ# MP_L_L G G MPR MP_IRQ# MP_L_L H H MMQ MP_IRQ# MP_L_L H H O MP_F_SPI_IRQ# MP_L_L J J O MP_I_IRQ# RE J G J OE V G +.V IR V F E F H J J N N H 00nF 00nF 00nF 00nF N N LVHZRR MP_L_L[0:] +.V U MP_L_L0 URT_SEL0 MP_L_L URT_SEL MP_L_L OSEL MP_L_L RS_EN MP_L_L RS_EN MP_L_L SW0 MP_L_L SW MP_L_L E E O_OOT +.V OE V IR V E 0 U 0nF I0 V N N N N I RE LVHZRR O +.V MVHGFTG 0 00nF 00nF 00nF 00nF LE_GREEN +.V LE_GREEN LE_GREEN LE_GREEN LE_RE LE_RE S URT_SEL0 LE_RE URT_SEL SWa SWb OSEL SWa SWb LE_RE SWa RS_EN SWb SWa RS_EN SWb SW0 SWa SWb SW SWa SWb 0 O_OOT SWa SWb SWa SWb.K R0.K R.K R.K R.K R.K R.K R.K R SM_IP_SWx MLVX0TG el, Latch, uffer and Logics Size ocument Number Rev TWR-MP0 Wednesday, October, 0 ate: Sheet of

5 isplay, S ard and N Signals +.V +.V 0nF 0nF U MP0 R0 R0 R0 R0 R R R +.V E GPIO_0/S_LK/MSRI0 (R I) E GPIO_/S_M/MSRI (R I) GPIO_/S_/MSRI (R I) E GPIO_/S_WP/MSRI (R I) GPIO_/S_T0/MSRI (R I) GPIO_/S_T/MVL (R I) GPIO_/S_T/QE_EXT_REQ_ GPIO_/S_T/QE_EXT_REQ_ GPIO_/RXN/LSRI0/LS_ GPIO_/TXN/LSRI/LS_ GPIO_0/RXN/LSRI/LS_ E GPIO_/TXN/LSRI/LS_ GPIO_/RXN/LSRI/LLK GPIO_/TXN/LVL/ GPIO_/RXN/ GPIO_/TXN MP_SLK MP_SM MP_S# MP_SWP MP_S_T0 MP_S_T MP_S_T MP_S_T R R R S_LK R00 R S_M R0 R S_# R0 R S_WP R0 R S_T0 R0 R S_T R0 R S_T R0 R S_T MP_N_RX MP_N_TX MP_N_RX MP_N_TX MP_N_RX, MP_N_TX MP_N_RX MP_N_TX S_WP S_# S_T S_T0 S_LK S_M S_T S_T 0K 0K-NP 0K 0K 0K 00K 00K 0 J WP n T T0 LK V M /T T S R SOKET P P P P R 00K R -NP R -NP isplay onnector, MP_L_[:0] +V +.V J0 +.V MP_L_ MP_L_ MP_L_ MP_L_ MP_L_ MP_L_0 MP_L_ MP_L_ MP_L_ MP_L_ MP_L_ MP_L_ MP_L_ MP_L_ MP_L_ MP_L_0 +.0V +.V0 0 WR# OE# Parallel_S# R 0 RESET# TRL S SL 0 +.V IRQ# 0 SPI_MOSI SPI_LK SPI_MISO SPI_S MP_L_WE0#,, MP_L_S# MP_L_,, ISPLY_RESET ISPLY_TRL MP_I_S,,, MP_I_SL,,, MPR MP_IRQ# MP_O_SPI_MOSI,, MP_O_SPI_LK,, MP_O_SPI_MISO,, MP ISPLY_SPI_SEL F_, F_, F_, F_0,,,, MP_HRESET# MP_RST_TWR# U I0 V I O MVHG0FTG R.K 0nF TWR_RESET# Header x0 I ddress = 0x ssume MPR on isplay Module with R pin = V isplay, S card & N Size ocument Number Rev TWR-MP0 Wednesday, October, 0 ate: Sheet of

6 UG MP0 MP FE,FE & FE MP_FE_TX MP_FE_TX MP_FE_TX MP_FE_TX MP_FE_TX MP_FE_TX MP_FE_TX0 MP_FE_TX0 MP_FE_TXER MP_FE_TXER MP_FE_TXEN\TMR_GLK MP_FE_TXLK\TMR_LK MP_FE_RX MP_FE_RX MP_FE_RX MP_FE_RX MP_FE_RX MP_FE_RX MP_FE_RX0 MP_FE_RX0 MP_FE_RXER MP_FE_RXER MP_FE_RXV MP_FE_RXV MP_FE_RXLK MP_FE_RXLK MP_FE_RS MP_FE_RS MP_FE_OL MP_FE_OL R R R R R R R R R R R R R R Y W W FE_TX/TSE_TMR_LRM/GPIO_/ FE_TX/TSE_TMR_LRM/GPIO_/ FE_TX/TSE_TMR_PP/GPIO_/ FE_TX0/TSE_TMR_PP/GPIO_0/ FE_TX_ER/TSE_TMR_PP/GPIO_/ FE_TX_EN/TSE_TMR_GLK/GPIO_/ FE_TX_LK/TSE_TMR_LK/GPIO_/ FE_RX/TSE_TMR_TRIG/GPIO_/ FE_RX/TSE_TMR_TRIG/GPIO_/ FE_RX/FE_TMR_RX_ESF/GPIO_/ FE_RX0/FE_TMR_TX_ESF/GPIO_/ FE_RX_ER/FE_TMR_RX_ESF/GPIO_/ FE_RX_V/FE_TMR_TX_ESF/GPIO_/ FE_RX_LK/GPIO_0/ FE_RS/GPIO_/ FE_OL/GPIO_/ Y FE_OL/GTM_TIN/GPIO_/ FE_RS/GTM_TGTE_/GPIO_ W FE_RX_LK/GPIO_/ FE_RX_V/GTM_TIN/GPIO_/PLLZ_ORE_LKIN FE_RX_ER/GTM_TGTE_/GPIO_0/JTG _ISE FE_RX/GPIO_/TPR_SYS_[] FE_RX/GTM_TGTE_/GPIO_/TPR_S YS_[0] FE_RX/GTM_TIN/GPIO_/JTG_ISR_ TO_EN Y FE_RX0/GPIO_/JTG_PRPGPS 0 W FE_TX_LK/GTM_TIN/GPIO_/TPR_SYS_ [] FE_TX_EN/GTM_TGTE_/GPIO_/TPR_ SYS_[] 0 FE_TX_ER/GTM_TOUT_/GPIO_/TPR_S YS_[] R R R MP_FE_OL MP_FE_RS MP_FE_RXLK MP_FE_RXV MP_FE_RXER MP_FE_RX MP_FE_RX MP_FE_RX MP_FE_RX0 R MP_FE_TXLK R MP_FE_TXEN R MP_FE_TXER MP_FE_OL MP_FE_RS MP_FE_RXLK MP_FE_RXV MP_FE_RXER MP_FE_RX MP_FE_RX MP_FE_RX MP_FE_RX0 MP_FE_TXLK MP_FE_TXEN MP_FE_TXER MP_FE_TX MP_FE_TX MP_FE_TX MP_FE_TX0 MP_FE_TXER MP_FE_TXEN MP_FE_TXLK MP_FE_RX MP_FE_RX MP_FE_RX MP_FE_RX0 MP_FE_RXER MP_FE_RXV MP_FE_RXLK MP_FE_RS MP_FE_OL MP_FE_TX MP_FE_TX MP_FE_TX MP_FE_TX0 MP_FE_TXER MP_FE_TXEN MP_FE_TXLK MP_FE_RX MP_FE_RX MP_FE_RX MP_FE_RX0 MP_FE_RXER MP_FE_RXV MP_FE_RXLK MP_FE_RS MP_FE_OL R R0 R R R R R R R R R R R R Y W Y W Y FE_TX/GPIO_/ FE_TX/GTM_TOUT_/GPIO_/ FE_TX/GTM_TOUT_/GPIO_/ FE_TX0/GTM_TOUT_/GPIO_/P_XL MG_R_LOK FE_TX_ER/GTM_TOUT_/GPIO_/ FE_TX_EN/GTM_TGTE_/GPIO_/LO K_XL_LOK_OUT FE_TX_LK/GTM_TIN/GPIO_/ FE_RX/GPIO_0/TPR_SYS_K FE_RX/GTM_TGTE_/GPIO_/TPR_SYS_SYN FE_RX/GTM_TIN/GPIO_/TPR_SYS_ [] FE_RX0/GPIO_/TPR_SYS_[] FE_RX_ER/GTM_TGTE_/GPIO_/TPR_ SYS_[] FE_RX_V/GTM_TIN/GPIO_/TPR_SYS_ [] FE_RX_LK/GPIO_/TPR_SYS_[] FE_RS/GTM_TGTE_/GPIO_/TPR_SY S_[0] FE_OL/GTM_TIN/GPIO_/TPR_SYS_ [] FE_TX0/GTM_TOUT_/GPIO_/TPR_SY S_[] FE_TX/GTM_TOUT_/GPIO_/TPR_SY S_[] FE_TX/GTM_TOUT_/GPIO_0/TPR_SY S_[] FE_TX/GPIO_/TPR_SYS_[] FE_M W FE_MIO W R R R R R R R MP_FE_TX0 R MP_FE_TX R MP_FE_TX R MP_FE_TX R MP_FE_M R MP_FE_MIO MP_FE_TX0 MP_FE_TX MP_FE_TX MP_FE_TX +.V R0.K R.K MP_FE_MIO, MP_FE_M, MP_FE_RXER MP_FE_RXER R R K-NP K-NP MP_FE_TXLK\TMR_LK R R -NP MP_FE_TXLK MP_TMR_LK TP MP_FE_TXEN\TMR_GLK R MP_FE_TXEN R -NP MP_TMR_GLK, +.V F LMSGTN 00nF R OS.K TRI_STTE V _ OUT R0 +.V F LMPSN R R 00nF U NNRG -SOI V OE ILK Q Q Q Q R R R R R R R R FE_PHY_LK_MHz FE_PHY_LK_MHz FE_PHY_LK_MHz MHZ, MP_N_RX, MP_LK0 R R -NP -NP Ethernet Interface and lock Size ocument Number Rev TWR-MP0 Wednesday, October, 0 ate: Sheet of

7 0/00 ETHERNET PHY 0/00 RJ with Magnetics +.V PHY RESS[:0]=>0X0000 PHY OOT STRPS +.V +.V_V +.V uf 00nF 00 F LMPSN 00nF uf 00 +.V 0 0nF 0 0nF R.R R.R R.R R.R ETH_TXP 0 00nF ETH_TXN ETH_RXP 0 00nF ETH_RXN ETH_TXP ETH_T ETH_TXN ETH_RXP ETH_T ETH_RXN PHY 0 PHY PHY R.K R R.K-NP.K-NP PHY_0 PHY_ PHY_ R R R K-NP K K 00nF ETH_RXN ETH_RXP ETH_TXN ETH_TXP 0uF 00 FE_PHY_LK_MHz, MP_FE_MIO, MP_FE_M MP_FE_RX R R MP_FE_RX R0 R MP_FE_RX R R MP_FE_RX0 R R 00pF.K % 00 PHY_0 PHY_ PHY_ PHY_UP R REXT 0 P U KSZ0NL Rev PHY_FG PHY_ISO PHY_FG0 PHY_FG PHY_LE0 PHY_LE R R MP_FE_RXV R R MP_FE_RXLK R R MP_FE_RXER FE_INT# R R MP_FE_TXLK MP_FE_TXEN MP_FE_TX0 MP_FE_TX MP_FE_TX MP_FE_TX R R MP_FE_OL R R MP_FE_RS PHY_LE0 PHY_LE MP_HRESET#,,, ETH_TXP ETH_TXN ETH_T ETH_T ETH_RXP ETH_RXN +.V F LMPSN VIO_V VPLL_V RXV/RSV/ONFIG V_V RX RX- RXER/RX_ER/ISO 0 RX+ INTRP TX- TX TX+ TXEN/TX_EN XO TXO/TX[0] XI/REFLK TX/TX[] REXT TX MIO TX M OL/ONFIG0 RX/PHY0 RS/ONFIG RX/PHY LE0/NWYEN 0 RX/RX[]/PHY LE/SPEE RX0/RX[0]/UPLEX RST# J 0/00M JK T+ G T- T _ T_ G R+ R- 0 Y Y G G ONFIG[0:]=>000 MII NWYEN=>uto Nego Enable(default) SPEE=>00Mbps(default) UPLEX=>FULL UPLEX ISO => PHY not in Isolate mode (efault) NWYEN PHY_FG0 PHY_FG PHY_FG PHY_LE0 R R R K K K R.K +.V PHY_LE R0 PHY_LE0 R0 LE0 = LINK/T LE = SPEE nf KV SPEE UPLEX ISO PHY_LE PHY_UP PHY_ISO R0.K R R K K LE Mode F LE # [00] [0] LMPGSN LE0 LINK/T LINK LE SPEE SPEE Note: Software: onfigure LE mode for [00] setting 0/00 ETHERNET PHY 0/00 RJ with Magnetics PHY RESS[:0]=>0X V PHY OOT STRPS 00nF ETH_RXN ETH_RXP ETH_TXN ETH_TXP +.V_V 0uF 00 +.V FE_PHY_LK_MHz, MP_FE_MIO, MP_FE_M MP_FE_RX R00 R PHY_0 MP_FE_RX R R PHY_ MP_FE_RX R R PHY_ MP_FE_RX0 R R PHY_UP uf 00nF 00 0 F LMPSN P 00nF uf 00 +.V PHY_FG PHY_ISO PHY_FG0 PHY_FG PHY_LE0 PHY_LE R R R R R0 R0 R0 R0 R0 R0 R R 0 MP_FE_RXV MP_FE_RXLK MP_FE_RXER FE_INT# MP_FE_TXLK MP_FE_TXEN MP_FE_TX0 MP_FE_TX MP_FE_TX MP_FE_TX MP_FE_OL MP_FE_RS MP_HRESET#,,, 0nF 0nF R.R R.R R.R R.R ETH_TXP ETH_TXN ETH_RXP 00nF ETH_RXN LE # 00nF +.V LE Mode [00] ETH_T ETH_T PHY_LE PHY_LE0 +.V F LMPSN LE0 = LINK/T LE = SPEE [0] R0 R0 VIO_V VPLL_V RXV/RSV/ONFIG V_V RX RX- RXER/RX_ER/ISO 0 RX+ INTRP TX- TX TX+ TXEN/TX_EN XO TXO/TX[0] XI/REFLK TX/TX[] REXT TX MIO TX M OL/ONFIG0 RX/PHY0 RS/ONFIG RX/PHY LE0/NWYEN 0 RX/RX[]/PHY LE/SPEE RX0/RX[0]/UPLEX RST# J 0/00M JK T+ G T- T _ T_ G R+ R- Y Y 0 G G nf KV F LMPGSN PHY 0 PHY PHY ONFIG[0:]=>000 MII NWYEN=>uto Nego Enable(default) SPEE=>00Mbps(default) UPLEX=>FULL UPLEX ISO => PHY not in Isolate mode (efault) NWYEN R0.K-NP R.K R PHY_FG0 PHY_FG PHY_FG PHY_LE0.K-NP R R0 R PHY_0 PHY_ PHY_ K K K R.K R0 K R K-NP R K +.V 00pF.K % R0 REXT U KSZ0NL Rev LE0 LE LINK/T SPEE LINK SPEE SPEE UPLEX ISO PHY_LE PHY_UP PHY_ISO R.K R R K K Note: Software: onfigure LE mode for [00] setting ETH PHYs & RJ Size ocument Number Rev TWR-MP0 Wednesday, October, 0 ate: Sheet of

8 US Interface +.V R R R R UE MP0 USR_PWRFULT/E_PIO_/ USR_LK/URT_SIN/URT_TS_/ USR_IR/URM_TRIG/ USR_NXT/URT_SIN/U REQ_ USR_STP/U_URM/QE_EXT_REQ_ W.K.K.K.K US_PWRFULT US_LKOUT MP_US_IR MP_US_NXT MP_US_STP R K US_PWRFULT US_LKOUT MP_US_IR MP_US_NXT MP_US_STP USR_TXRX0/GPIO_/QE_TR_O Y W USR_TXRX/GPIO_/QE_TR_I USR_TXRX/GPIO_/QE_RG_ USR_TXRX/GPIO_/QE_RG_ USR_TXRX/GPIO_/QE_RG_ Y USR_TXRX/GPIO_/QE_RG_ USR_TXRX/GPIO_/QE_RG_ USR_TXRX/GPIO_/QE_RG_ USR_PTL0/URT_SOUT/U_URM/L_P OR_FG_OOT_E W USR_PTL/URT_SOUT/URT_RTS_/ L_POR_OOT_ERR W R K MP_US_PTL0 MP_US_PTL MP_US_0 MP_US_0 MP_US_ MP_US_ MP_US_ MP_US_ MP_US_ MP_US_ MP_US_ MP_US_ MP_US_ MP_US_ MP_US_ MP_US_ MP_US_ MP_US_ MP_US_PTL0 MP_US_PTL +.V +V US_PEN R 00K-NP U IN OUT IN OUT TL FLG GTE MI0-YM US_VUS R 00nF 00nF 0uF 0uF LE_RE R.K +.V US_INT# TP U I0 I V O +.V 00nF TP US_PWRFULT MVHG00FTG +.V +.V MP_US_PTL TP U I0 V I O MVHG00FTG 00nF +.V R LE_GREEN MP_US_PTL0 TP U I0 V I O MVHG00FTG 00nF +.V R LE_GREEN US PHY +.V uf 00nF 00nF 00nF 00nF 00nF U REG_EN V_. V_. 0 V_. V_. RST R US_INT# MP_US_0 MP_US_ MP_US_ MP_US_ MP_US_ MP_US_ MP_US_ MP_US_ MP_US_IR MP_US_STP MP_US_NXT US_LKOUT US_INT# MP_US_0 MP_US_ MP_US_ MP_US_ MP_US_ MP_US_ MP_US_ MP_US_ uf R US_PEN R 00nF 00nF 00nF 0 VUS_T T0 T T 0 T T T T T IR STP NXT LKOUT PEN V. M P I VUS XI V. V_. XO RIS P US00 US_N US_P US_I F US_VUS LMPGSN US_LKIN R K % +V 0 00nF 00nF uf R00M_0 J US MINI SKT Mini US F LMPGSN F LMPGSN U SP00 US Interface and US PHY Size ocument Number Rev TWR-MP0 Wednesday, October, 0 ate: Sheet of

9 UH MP0 MP - HL HL_TXLK/GPIO_0/QE_RG_/TM_TK 0 HL_TX/GPIO_/TM_T/FG_RESET_S OURE[0] W HL /GPIO_/TM_TFS/ HL_RXLK/GPIO_/TM_RK/ HL_RX/GPIO_/TM_R/ V HL_TS_/GPIO_/TM_RFS/ HL_RTS_/GPIO_/TM_STROE_/FG _RESET_SOURE[] HL_TXLK/GPIO_/QE_RG_/TM_TK Y0 W0 HL_TX/GPIO_/TM_T/FG_RESET_ SOURE[] V0 HL /GPIO_0/TM_TFS/ HL_RXLK/GPIO_/TM_RK/QE_RG_ Y W HL_RX/GPIO_/TM_R/ Y HL_TS_/GPIO_/TM_RFS/ U0 HL_RTS_/GPIO_/TM_STROE_/F G_RESET_SOURE[] MP_HL_TK MP_HL_TX_OOT_FG0 MP_HL_# MP_HL_RK MP_HL_RX MP_HL_TS# MP_HL_RTS#_OOT_FG MP_HL_TK MP_HL_TX_OOT_FG MP_HL_# MP_HL_RK MP_HL_RX MP_HL_TS# MP_HL_RTS#_OOT_FG MP_HL_TK MP_HL_TX_OOT_FG0, MP_HL_# MP_HL_RK MP_HL_RX MP_HL_TS# MP_HL_RTS#_OOT_FG, MP_HL_TK MP_HL_TX_OOT_FG, MP_HL_# MP_HL_RK MP_HL_RX MP_HL_TS# MP_HL_RTS#_OOT_FG, PHY_URT_TX PHY_URT_RTS# PHY_URT_RX PHY_URT_TS# 00nF R.K URT nF URT-V+ URT-V- 0 00nF URT-- URT-+ URT-- R.K RS_TX RS_RTS RS PHY 0 U T-IN T-IN R-OUT R-OUT T-OUT T-OUT MXUE J V+ V- R-IN R-IN V 00nF RS_TX RS_RTS RS_RX RS_TS +.V +.V +V R -NP R RS_RX RS_TS 0 00nF URT_SEL0 F_URT_TX F_URT_TX TEP_URT_TX PHY_URT_RX MP_URT_RX URT_SEL0 TEP_URT_TS#, F_URT_RTS# TEP_URT_TS# PHY_URT_TS# MP_URT_TS# Quad : mux EN# IN IN to S =S 0 0 =S 0 0 =S 0 =S X X OFF R EN# N S S S S EN# N S S S S U0 TS0PW U V+ EN# IN S S S 0 S V+ EN# IN S S S 0 S +.V 0 00nF +.V 00nF URT_SEL F_URT_RX F_URT_RX TEP_URT_RX PHY_URT_TX MP_URT_TX URT_SEL TEP_URT_RTS# F_URT_TS# TEP_URT_RTS# PHY_URT_RTS# MP_URT_RTS# R Header x.mm.k TS0PW U & U - RS VISO +.V VISO +.V R 0 MP_HL_TK, MP_HL_TX_OOT_FG0 MP_HL_# MP_HL_RX MP_HL_TS#, MP_HL_RTS#_OOT_FG LE/RS SEL, RS RTS#.K R U0 I0 V I O MVHG0FTG 0nF RS TR 00 U0 RS TX, K RS U I0 V 00nF U RS RX RS RE# OE V RS TS Emitter I US_RTS RS RTS#, RS RX node O I O RS TR athode MVHG00FTG R0 MVHGFTG ollector PS0- RS RX RS RX RS RE# 0 RS E, RS TX RS TX +.V U +.V I0 V +.V +.V RS RTS# U I O I0 V R 00nF MVHG00FTG I RS E 00nF O U 0K RS RE# OE V MVHG0FTG +.V I RS U +.V O RS_EN I0 V MVHGFTG 0 0 I RS RE# O 00nF 00nF 00nF R K R K 0 00nF 00nF 0nF 0uF00 U 0 V VISO_IN RX RE# E Z TX V Y 0 VISO_OUT ME 00nF 00nF 0nF 0uF00 US+ US- US+ J R Header x.mm VISO US_RTS US- MVHG00FTG +.V VISO MP_HL_TK, MP_HL_TX_OOT_FG MP_HL_# MP_HL_RX MP_HL_TS#, MP_HL_RTS#_OOT_FG LE/RS SEL, RS RTS#.K R U I0 V I O MVHG0FTG 0 RS TR RS TX, U0 00nF RS RE# RS OE V RS RX RS TS RS RX I RS RTS#, O RS TR MVHGFTG +.V +.V R 00nF U 00nF 0K RS RE# OE V I O RS MVHGFTG U Emitter node athode R ollector PS0-0 RS RTS# RS_EN U I0 I R K +.V V O MVHG00FTG 0 0nF U I0 V I US_RTS O MVHG00FTG RS RX RS RX RS RE# RS E, RS TX RS TX +.V U I0 V I RS E O +.V MVHG0FTG U +.V I0 V I RS RE# O 00nF 00nF 00nF MVHG00FTG +.V 0 00nF 00nF 0nF 0uF00 R U 0 K V VISO_IN RX RE# E Z TX V Y R0 0 VISO_OUT K ME VISO 00nF 00nF 0nF 0uF00 VISO US+ US- J0 US+ US_RTS US- R Header x.mm RS, RS and RS MUX Size ocument Number Rev TWR-MP0 Wednesday, October, 0 ate: Sheet of

10 , MP_PI_INT# MP_PI_RST_OUT# MP_PI_E0# MP_PI_E# MP_PI_E# MP_PI_E# MP_PI_PR MP_PI_FRME# MP_PI_TRY# MP_PI_IRY# MP_PI_STOP# MP_PI_EVSEL# MP_PI_ISEL# MP_PI_SERR# MP_PI_PERR# MP_PI_REQ0# MP_PI_REQ# MP_PI_REQ# MP_PI_GNT0# MP_PI_GNT# MP_PI_GNT# MP_PI_MEN MP_PI_INT# MP_PI_RST_OUT# MP_PI_E0# MP_PI_E# MP_PI_E# MP_PI_E# MP_PI_PR MP_PI_FRME# MP_PI_TRY# MP_PI_IRY# MP_PI_STOP# MP_PI_EVSEL# MP_PI_ISEL# MP_PI_SERR# MP_PI_PERR# MP_PI_REQ0# MP_PI_REQ# MP_PI_REQ# MP_PI_GNT0# MP_PI_GNT# MP_PI_GNT# MP_PI_MEN F L0 L L L M M0 M M N N N N P0 P P T T U U V UF MP0 PI_INT_ PI_RESET_OUT_ PI E_0 / OOT_ROM_RT[] PI E_ / OOT_ROM_RT[] PI E_ / OOT_ROM_RT[] PI E_ / SYSTEM_PLL_OUT/OOT_ROM_RT[] PI_PR/QE_PLL_OUT/OOT_ROM_RT[] PI_FRME_ / OOT_ROM_RT[] PI_TRY_ / OOT_ROM_RT[] PI_IRY_ / OOT_ROM_RT[] PI_STOP_ / OOT_ROM_RT[] PI_EVSEL_ / OOT_ROM_RT[0] PI_ISEL / OOT_ROM_RT[] PI_SERR_ / OOT_ROM_MO_EN PI_PERR_ / OOT_ROM_RW PI_REQ_0 / OOT_ROM_XFR_WIT PI_REQ_/PI_HS_ES/OOT_ROM_XFR_E RR PI_REQ_ PI_GNT_0 PI_GNT_/PI_HS_LE/ PI_GNT_0 PI_GNT_/PI_HS_ENUM/ MEN MP PI Interface PI_0/OOT_ROM_R[] PI_/OOT_ROM_R[] E0 PI_/OOT_ROM_R[] G PI_/OOT_ROM_R[] PI_/OOT_ROM_R[] H PI_/OOT_ROM_R[] PI_/E_PIO_0/OOT_ROM_R[] F0 PI_OOT_ROM_R[] E PI_/TPR_SYS_[0]/OOT_ROM_R[ 0] H0 PI_/TPR_SYS_[]/OOT_ROM_R[ ] PI_0/TPR_SYS_[]/OOT_ROM_R [] PI_/TPR_SYS_[]/OOT_ROM_RT [0] J PI_/TPR_SYS_[]/OOT_ROM_RT [] F PI_/TPR_SYS_[]/OOT_ROM_RT [] G PI_/TPR_SYS_[]/OOT_ROM_RT [] E PI_/TPR_SYS_[]/OOT_ROM_RT _[] E PI_/TPR_SYS_[]/OOT_ROM_RT [] J0 PI_/TPR_SYS_[]/OOT_ROM_RT [] F PI_/TPR_SYS_[0]/OOT_ROM_R T[] G PI_/TPR_SYS_[]/OOT_ROM_R T[] K PI_0/TPR_SYS_[]/OOT_ROM_R T[] H PI_/TPR_SYS_[]/OOT_ROM_R T[0] L PI_/TPR_SYS_[]/OOT_ROM_R T[] G PI_/TPR_SYS_[]/OOT_ROM_R T[] H PI_/TPR_SYS_SYN/OOT_ROM_RT [] J PI_/TPR_SYS_K/OOT_ROM_RT [] H PI_/U_URM/OOT_ROM_RT[] J PI_OOT_ROM_RT[] K PI_/U_URM/OOT_ROM_RT[] K PI_OOT_ROM_RT[] K PI_0OOT_ROM_RT[] K PI_OOT_ROM_RT[0] T PI_LK0 U PI_LK R PI_LK MP_PI_0 MP_PI_ MP_PI_ MP_PI_ MP_PI_ MP_PI_ MP_PI_ MP_PI_ MP_PI_ MP_PI_ MP_PI_0 MP_PI_ MP_PI_ MP_PI_ MP_PI_ MP_PI_ MP_PI_ MP_PI_ MP_PI_ MP_PI_ MP_PI_0 MP_PI_ MP_PI_ MP_PI_ MP_PI_ MP_PI_ MP_PI_ MP_PI_ MP_PI_ MP_PI_ MP_PI_0 MP_PI_ R R R R R0 R MP_PI_LK0 MP_PI_LK MP_PI_LK MP_PI_[:0] MP_PI_LK0 MP_PI_LK MP_PI_LK MP_PI_INT# MP_PI_RST_OUT# MP_PI_E0# MP_PI_E# MP_PI_E# MP_PI_E# MP_PI_PR MP_PI_FRME# MP_PI_TRY# MP_PI_IRY# MP_PI_STOP# MP_PI_EVSEL# MP_PI_SERR# MP_PI_PERR# MP_PI_REQ0# MP_PI_REQ# MP_PI_REQ# MP_PI_GNT0# MP_PI_GNT# MP_PI_GNT# MP_PI_MEN MP_PI_ISEL# R.K R.K R.K R.K R0.K R.K R.K R.K R.K R.K R.K R.K R.K R.K R0.K R.K R.K R.K R.K R.K R.K R.K +.V MP_PI_SYN_IN R -NP PI_SYN_IN T R0 PI_SYN_IN PI_SYN_OUT R R PI_SYN_OUT +V +.V Mini PI Type onnector +V ISEL <= INT <=MP0_IRQ INT<=N INT<=N INT<=N PILK0 PIGNT/PIREQ J TIP KEY RING KEY MP_PI_LK0 MP_PI_REQ0# MP_PI_[:0] +.V.K R MP_PI_PME# MP_PI_LKRUN#.K R MP_PI_ MP_PI_ MP_PI_ MP_PI_ MP_PI_E# MP_PI_ MP_PI_ MP_PI_ MP_PI_ MP_PI_E# MP_PI_IRY# MP_PI_LKRUN# MP_PI_SERR# MP_PI_PERR# MP_PI_E# MP_PI_ MP_PI_ MP_PI_0 MP_PI_ MP_PI_ MP_PI_ MP_PI_ MP_PI_ PMJ- PMJ- PMJ- PMJ- LE_GRNP LE_GRNN HS INT#.V_ RESERVE LK _ REQ#.V_ [] [] _ [] [] RESERVE_ /E[]# [] _ [] [] _ [] /E[]# IRY#.V_ LKRUN# SERR# _ PERR# /E[]# [] _ [] [0] _ [] [].V_ [] RESERVE_ [] V_ [] _0 _SYN _ST_IN _IT_LK _OE_I# MO_UIO_MON UIO_ SYS_UIO_OUT SYS_UIO_OUT UIO RESERVE_ VV RM PMJ- PMJ- PMJ- 0 PMJ- LES_YELP LE_YELN RESERVE_ V_ 0 INT# RESERVE_ R.VUX_ RST#.V_ 0 GNT# _ PME# RESERVE_ [0] 0.V_0 [] [] [] ISEL 0 _0 [] [0] PR [] 0 [] _ FRME# TRY# STOP# 0.V_0 EVSEL# _ [] [] 0 [] _ [] /E[0]#.V_ 0 [] [] [] [0] RESERVE_WIP_ 00 RESERVE_WIP_00 0 _0 MEN 0 _ST_OUT 0 0 _OE_I0# 0 _RESET# RESERVE SYS_UIO_IN SYS_UIO_IN 0 UIO 0 MPIT#.VUX_ RM MP_PI_INT#, -NP MP_PI_RST_OUT# MP_PI_GNT0# MP_PI_PME# MP_PI_0 MP_PI_ MP_PI_ MP_PI_ R R MP_PI_ MP_PI_ MP_PI_0 MP_PI_PR MP_PI_ MP_PI_ MP_PI_FRME# MP_PI_TRY# MP_PI_STOP# MP_PI_EVSEL# MP_PI_ MP_PI_ MP_PI_ MP_PI_ MP_PI_E0# MP_PI_ MP_PI_ MP_PI_ MP_PI_0 MP_PI_MEN TO E PLE NER MINI PI ONNETOR +.V +V 0 00nF 00nF 00nF 00nF 00nF 00nF 00nF 00nF uf uf 00nF V 00nF V uf V - PI Interface and Mini PI onnector Size ocument Number Rev TWR-MP0 Wednesday, October, 0 ate: Sheet of 0

11 Primary Elevator +.V_ELEV +V_ELEV +V_ELEV +.V_ELEV ELE_PS_SENSE S_LK S_T MP_HL_# S_M S_T0 R R R R R 0 J V.V_ ELE_PS_SENSE SPI_LK SPI_S SPI_S0 SPI_MOSI SPI_MISO V.V_.V _ SL0 S0 GPIO/OPEN GPIO/OPEN GPIO/OPEN 0 R R R R MP_I_SL MP_I_S S_T S_WP resistor on HL signals should be placed close to MP R -NP MP_HL_TS# R TEP_URT_TS# MP_FE_OL R MP_FE_RXER R0 MP_FE_TXLK R0 MP_FE_TXEN R0 resistor on HL signals MP_FE_TXER R0 should be placed close to MP MP_FE_TX R MP_FE_TX R MP_FE_TX R TEP_URT_RTS# R MP_FE_TX0 R, MP_HL_RTS#_OOT_FG R -NP R S_T F O_SPI_SS R R -NP MP_QE_LK_IN R00 FE_PHY_LK_MHz R0 -NP, MP_LK0, F_, F_, F_, F_0 MP_LTL R0 F_M_T_IR F_M_T_IR MP_N_RX F_M_PWM_ F_M_PWM_ F_M_T_IR0 F_M_T_IR MP_N_RX MP_N_TX MP O_SPI_SEL R0,, MP_O_SPI_MISO,, MP_O_SPI_MOSI MP O_SPI_SEL0 R0 MP_SPI_SEL_OOT# R0 -NP MP O_SPI_SEL,, MP_O_SPI_LK R,,, MP_I_SL R,,, MP_I_S F_M_INT TEP_URT_TX R -NP TEP_URT_RX R -NP O MP_SPI0_IRQ# O MP_SPI_IRQ# O MP_SPI_IRQ# O MP_F_SPI_IRQ# O MP_I_IRQ# F_M_INT0 F_M_INT F_M_INT R MP_L_S# MP_L_LE R -NP, MP_L_S0#,, MP_L_[:0] MP_L_0 MP_L_ MP_L_ MP_L_ MP_L_,, MP_L_WE0#, MP_L_[:0], MP_L_RE/OE# MP_L_0 MP_L_ MP_L_ MP_L_ MP_L_ MP_L_ MP_L_ MP_L_ ETH_OL ETH_RS ETH_RXER ETH_M ETH_TXLK/ETH_REF_LK ETH_MIO ETH_TXEN ETH_RXLK ETH_TXER ETH_RXV/ETH_RS_V ETH_TX ETH_RX ETH_TX ETH_RX ETH_TX ETH_RX ETH_TX0 ETH_RX0 GPIO/OPEN SSI_MLK GPIO/OPEN SSI_LK GPIO/OPEN SSI_FS LKIN0 SSI_RX LKOUT SSI_TX N N N N N N N N0 0 TMR TMR TMR TMR0 GPIO/OPEN GPIO/OPEN.V_.V_ PWM PWM PWM PWM PWM PWM PWM PWM0 NRX RX0 NTX TX0 N RX SPI0_MISO TX SPI0_MOSI GPIO0 SPI0_S0 GPIO0 SPI0_S GPIO0 SPI0_LK GPIO0 SL GPIO0 S GPIO0 GPIO/OPEN GPIO0 US_P_POWN TMS/KPT_ US_M_POWN US_M IRQ_H US_P IRQ_G US_I IRQ_F US_VUS IRQ_E TMR IRQ_ TMR IRQ_ TMR IRQ_ TMR IRQ_ RSTIN_ F_LE/F_S_ RSTOUT_ F_S0_ LKOUT0 0 F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 F_R/W_ F_ F_OE_ F_ F_ F_ F_ F_ F_ F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 F_0.V_.V_ EGE PI EXPRESS R R R R R R R0 R R R R R0 R0 R R R R R R R R R R0 R0 R0 R0 R R R MP_FE_RS MP_FE_M, MP_FE_MIO, MP_FE_RXLK MP_FE_RXV MP_FE_RX MP_FE_RX MP_FE_RX MP_FE_RX0 MP_HL_RK resistor on HL signals MP_HL_TK should be placed close to MP MP_HL_# MP_HL_RX MP_HL_TX_OOT_FG, F_URT_RTS#, F O_SPI_SPSK F O_SPI_MISO F O_SPI_MOSI F_VOOX, F_M_PWM_ F_M_PWM_0 MP_N_TX F_M_PWM_ F_M_PWM_ F_M_PWM_ F_M_PWM_0 TEP_URT_TS# TEP_URT_RTS# R TEP_URT_TX R -NP MP_HL_TX_OOT_FG0, R -NP MP_HL_RX R TEP_URT_RX MP_L_R# MP_HL_TS# MP_HL_RTS#_OOT_FG, resistor on HL signals THERM0 should be placed close to MP MP_N_TX MP_N_RX MP_HL_TK ELE_PS_SENSE MP_HL_RK -NP MP_N_TX -NP MP_N_RX, -NP MP_L_WE# -NP MP_L_WE0#,, F_M_PWM_0 F_M_PWM_ F_M_PWM_ F_M_PWM_ MP_HRESET#,,, TWR_RESET# -NP MP_PI_SYN_IN 0 MP_L_[:0],, MP_L_ MP_L_ MP_L_ MP_L_ 0 MP_PI_LK R MP_L_ 0 MP_PI_LK R MP_L_ MP_L_ MP_L_ MP_L_ 0 MP_PI_LK0 R0 MP_L_0 MP_L_ 0 MP_PI_E# R MP_L_ 0 MP_PI_E# R MP_L_ 0 MP_PI_TRY# MP_L_ 0 MP_PI_IRY# R MP_L_ 0 MP_PI_STOP# R 0 MP_PI_EVSEL# R 0 MP_PI_ISEL# R0 0 MP_PI_SERR# R 0 MP_PI_PERR# R 0 MP_PI_MEN R 0 MP_PI_[:0] MP_PI_0 MP_PI_ MP_PI_ MP_PI_ MP_PI_ R MP_PI_ R MP_PI_ MP_PI_ MP_PI_ 0 MP_PI_GNT0# R 0 MP_PI_GNT# R 0 MP_PI_GNT0# R -NP 0 MP_PI_GNT# R 0 MP_PI_GNT0# R -NP MP_PI_ MP_PI_,, MP_L_[:0] MP_L_ R0 MP_L_ R MP_L_ R MP_L_ R MP_L_ R MP_L_0 R 0 MP_PI_[:0] MP_PI_ MP_PI_ MP_PI_ MP_PI_ MP_PI_0 MP_PI_ MP_PI_0 MP_PI_ MP_PI_ Secondary Elevator +.V_ELEV +.V_ELEV +V_ELEV +V_ELEV J V_ V _.V_.V_ ELE_PS_SENSE.V _ SPI_LK SL0 SPI_S S0 0 SPI_S0 GPIO/OPEN SPI_MOSI US_SOTP 0 SPI_MISO US_LK ETH_OL GPIO ETH_RXER ETH_M ETH_TXLK/ETH_REF_LK ETH_MIO ETH_TXEN ETH_RXLK ETH_TXER ETH_RXV/ETH_RS_V GPIO0 GPIO0 GPIO0 GPIO0 0 ETH_TX ETH_RX 0 ETH_TX0 ETH_RX0 US_NEXT US_T0 US_IR US_T US_T US_T US_T US_T US_T US_T -NP -NP L_HSYN/L N L_VSYN/L N0 0 N N 0 N N -NP R -NP L_LK/L MP_PI_SYN_IN 0 GPIO0 TMR TMR R TMR0 MP_PI_E0# 0 TMR GPIO/OPEN MP_PI_E# 0 GPIO/OPEN R.V_.V_ R -NP PWM MP_PI_INT#,0 PWM R MP_PI_RST_OUT# 0 PWM PWM0 R PWM MP_PI_PR 0 0 PWM 0 R0 PWM MP_PI_FRME# 0 PWM NRX RX NTX TX GPIO0 RTS L_OE/L TS L_0/L0 RX L_/L TX L_/L RST L_/L MP_PI_[:0] 0 ST 0 0 MP_PI_ GPIO0 L_/L MP_PI_ GPIO0 L_/L MP_PI_ L_/L L_/L MP_PI_ L_/L L_/L MP_PI_ L_/L L_/L MP_PI_ IRQ_H L_/L MP_PI_0 IRQ_G L_0/L0 MP_PI_ IRQ_F L_/L R IRQ_E MP_PI_REQ0# 0 TMR R IRQ_ MP_PI_REQ# 0 0 TMR 0 R -NP IRQ_ MP_PI_REQ0# 0 TMR R0 IRQ_ MP_PI_REQ# 0 TMR MP_PI_ R -NP IRQ_ MP_PI_REQ0# 0 L_/L MP_PI_ L_/L L_/L MP_PI_ L_/L L_/L 0 R F_0/L O_OOT_ONFIG0 F_E/L R F_/L O_OOT_ONFIG F_E/L R F_/L O_OOT_ONFIG F_E/L0 R F_/L O_OOT_ONFIG 0 F_E0/L 0 R0 -NP F_/L MP_L_LE F_TSIZE0/L R -NP F_/L MP_L_LE F_TSIZE/L R -NP F_/L MP_L_WP# F_TS/L R -NP F_/L MP_L_GPL F_TST/L F_/L0 F_T/L R F_/L O_RV_NOR_LS# F_S/L F_0/L F_S/L R F_/L MP_L_S0#, F_S/L R -NP L_0/L0 MP_L_S0#, F_S/L0 0 L_/L GPIO/L 0 MP_PI_ L_/L L_/L.V_.V_ EGE PI EXPRESS Primary and Secondary Elevator Size ocument Number Rev TWR-MP0 Wednesday, October, 0 ate: Sheet of

12 +.V F LMSGTN 00nF 00nF 00nF 0 00nF 00nF.uF oldfire MU F_LE F LMSGTN V F LMSGTN VREFH R 00nF F LMSGTN 0nF 00nF F LMSGTN 0nF VREFL 00nF TP +V LE_RE F_LK_IN, MP_TMR_GLK R R F_M_T_IR0 F_M_T_IR F_M_INT F_M_PWM_0 F_M_PWM_ F_M_PWM_ F_M_PWM_ F_URT_TX F_URT_RX F_URT_TS#, F_0, F_, F_, F_ F O_SPI_SPSK F O_SPI_MISO F O_SPI_MOSI, F_URT_RTS# F_M_INT F_M_INT F MP_IRQ# MP F_IRQ MP F_SP0_SS,, MP_O_SPI_MISO STOUT SYN MU_RESET# F_KG OSEL F_M_INT0 -NP F_M_T_IR OSEL U V V V V VREFH VREFL VREF_OUT 0_SE/PT/SI_TS/I_SL/FTM_H/SPI_MISO/SI0_TX_FS/EZP_I VREGIN 0 0_SE/PT/SI_RTS/I_S/FTM_H/SPI_MOSI/LKOUT/SI0_TX/EZP_O VOUT TP US_- 0_SE/TSI0_H0/PT/LPT_LT/FTM_FLT/F_/F_ US0_M US_+ 0_SE/TSI0_H/PT/RGPIO0/FTM0_H0 US0_P 00nF.uF 0_SE0/TSI0_H/PT/RGPIO/FTM0_H/F_/F_0 0_SE/TSI0_H/PT/RGPIO/F_ 0_OUT F_VOOX, 0_SE/TSI0_H/PT/RGPIO/F_ 0_SE/TSI0_H/PT/SI0_TX/F_ PT0/I_SL/FTM_H0/F_/SI0_RX_FS F_M_PWM_0 0_SE/TSI0_H/PT/SI0_RX/RGPIO/F_ PT/I_S/FTM_H/F_/SI0_RX F_M_PWM_ 0_SE/TSI0_H/PT/SI0_TS/I_SL/RGPIO/F_ PT/SI_TX/FTM_H/SPI_SS F_M_PWM_ 0_SE/TSI0_H/PTE/SPI0_MOSI/I_S/F_OE PT/SI_RX/FTM_H/SPI_SLK/SI0_TX_LK/EZP_LK 0 F_M_PWM_ 0_SE/TSI0_H/PT/SPI0_MISO/F_S0 PT/SI0_TS/RGPIO/SPI0_SLK/LKOUT/SI0_MLK/ SI0_LKIN F_LE F_M_PWM_ V_V0_USEXT 0_SE/TSI0_H/PT/SPI0_MOSI/F_S/F_LE PT/SI0_RX/RGPIO/SPI0_MISO/P0_EXTRG 0_SE/TSI0_H/PTE/SI0_RTS/LPT_LT/SPI_SS/F_ PT/SI0_TX/RGPIO/SPI0_MOSI/MT_IRO MP_O_SPI_MOSI,, 0_SE0/PTE/SI0_TS/I_SL/SPI_SLK/F_ PT/SI0_TX/I0_SL/RGPIO/SPI_MOSI/F_ F_M_PWM_ F_M_PWM_ J PTE/SI0_RX/I_S/SPI_MISO/F_ PT/SI0_RX/I0_S/RGPIO/SPI_MISO/F_ 0_SE/PTE/SI0_TX/P0_EXTRG/SPI_MOSI/F_RW/F_ PT0/SI0_TS/I_S/RGPIO/SPI_SLK/F_/SI0_MLK/ SI0_LKIN F_M_T_IR F O_SPI_SS S S TSI0_H/PTE0/SI0_RTS/I_S/F_ PT/SI0_RTS/I_SL/RGPIO/SPI_SS/F_/SI0_RX_LK TSI0_H/PTE/SPI0_SS/FTM_FLT0/F_ PTF/SPI0_SLK/MP0_OUT/F_ MP_O_SPI_LK,, ITLK S S TSI0_H0/PT/SPI0_SLK/I0_S/FTM_FLT/LPT_LT/LKOUT PTF/SI_TS/SPI_SLK/F_/F_/SI0_TX_LK TSI0_H/PTE/I_SL/F_0 PTF/SI_RX/SPI_MISO/F_/F_RW/SI0_RX STIN F_M_PWM_0 US_MINI_ IRQ/PT0/EZP_MS/I0_SL/EZP_S PTF/SI_TX/SPI_MOSI/F_/F_/SI0_RX_FS 0 U F_URTSEL F0 MP0_IN0/PTF0/SPI0_SS/F_ PTF/SI0_RTS/SPI0_SS/F_0/F_0/SI0_RX_LK SP00 MP0_IN/PTF/SPI0_MISO/F_ LMSGTN MP0_IN/PTF/SPI0_MOSI/F_/SI0_TX MP0_IN/PT/SI_RTS/SPI_SS/RGPIO/F_/SI0_TX_FS +V RESET/PT/(Non_UST_VPP)/RGPIO/VPP R00M_0 KG/MS/PT XTL/PT EXTL/PT EXTL/PT/I_S/TMR_LKIN XTL/PT0/I_SL/TMR_LKIN0/RGPIO0 00nF TP VUS - + I G PFJU-P F_M_INT0 F_M_INT F_M_INT F_M_INT +.V R R0 R0 R0.K.K.K.K +.V U F_LE JTG_TRST# F O_SPI_SS MP_JTG_TMS F O_SPI_SPSK MP_JTG_TK F O_SPI_MOSI MP_JTG_TI MP_JTG_TO F O_SPI_MISO OSEL OE V 0 IR 0 MLXTG 00nF F_KG +.V R.K ebugger ccess: Pins: Pin - KG Pin - Pin - RESET# Pin - V J R Header x.mm +.V F_RESET# R.K U I0 I +.V 00nF V O R.K MU_RESET# MP JTG,,,, MP_POR# MP_HRESET# R R -NP MVHG0FTG +.V R R R R +.V R R R +.V I evice +.V MP_JTG_TO MP_JTG_TI MP_JTG_TK MP_JTG_TMS.K.K.K.K MP_JTG_TO MP_JTG_TI MP_JTG_TK MP_JTG_TMS MP_HRESET# HKSTP_OUT# K.K.K J TSM-0-0-S-V-P SMT 00MIL TO KEY TI TRST# QREQ# V_SENSE HKSTP_IN# TK HKSTP_IN# 0 TMS N SRESET# N HRESET# KEY HKSTP_OUT# JTG_TRST# 00nF U I0 V I MP_JTG_TRST# O MVHG0FTG MP_POR#, MP_JTG_TRST#,,,,,, MP_I_SL MP_I_S I ddress (S0=0) = 0x TP0 R.K U SL S S0 YP 00nF 0 VIO V 00nF INT INT N N N N N MMQ_P_ 0UF TP MMQ MP_IRQ#,,, MP_I_S,,, MP_I_SL R R0 -NP -NP HKSTP_OUT# HKSTP_IN# oldfire MU, IEEE, JTG and I evice Size ocument Number Rev TWR-MP0 Wednesday, October, 0 ate: Sheet of

13 udio OE I ddress = 0x0 MP_I_SL,,, MP_I_S,,, STOUT STIN ITLK SYN PIN and OIN SWP.mm udio Jack J SJ--SMT HP_R HP_V HP_L +.V 0 00nF U HP_R HP_V V HP_L N TRL_R0_S TRL_MOE V 0 TRL_LK N TRL_T IS_IN IS_OUT N VG LINEOUT_R LINEOUT_L LINEIN_R LINEIN_L MI MI_IS IS_SLK IS_LRLK N SYS_MLK VIO 0 N PFILT N _P +.V R R -NP SYS_MLK MP_TMR_GLK, SGTL000_QFN 0 00nF MI_IS.K R 00nF uf MI.mm udio Jack J TP LINE_OUT_R uf uf LINE_IN_L TP TP LINE_OUT_L uf 0 uf LINE_IN_R TP SJ--SMT udio OE Size ocument Number Rev TWR-MP0 Wednesday, October, 0 ate: Sheet of

14 MP ecoupling +.0V R UI MP0 N J.uF +.0V +.0V R 0 0nF 0nF 0nF 0nF 00nF 00nF 00nF 00nF uf uf uf uf uf uf V.uF.uF H H V P V +.0V T V L V 0nF 0nF 0nF 0nF T V V M V H V V N V R N V V L V 0 R V T V.uF.uF 00nF 00nF 00nF 00nF H0 V +.V H V K V T V 0 T V H V uf uf F0 uf uf H V V J V 0 V T V P T V 0nF 0nF 0nF 0nF 0nF H 0nF 0nF 0nF 0nF 0nF 0nF 0nF H V F H V uf F uf K V 00 V 00 T V 0 V M V V P V 00nF 00nF 00nF 00nF 00nF 00nF N 00nF 00nF 00nF 00nF J V G T0 V F R V V F 0 V F V uf uf uf G GV U uf uf uf uf H GV M 0 J GV F 0nF 0nF 0nF K GV F 0nF 0nF 0nF L GV F N GV F 000uF 000uF 000uF P GV V 000uF R GV V T GV T 00nF 00nF 00nF 00nF U GV L 00nF V GV F V GV F GV V V0 R 00nF 0uF 0uF J F K J M N R L J V P0 M M0 L Y0 K L F Y Y P R F N0 M K G0 R L N M 0 L Y N P T J R M J V N0 R K0 Y L0 W K N R0 K T0 M R M M K J N J0 R J P J K0 P G Y K R N M L P P.uF MP ecoupling Size ocument Number Rev TWR-MP0 Wednesday, October, 0 ate: Sheet of

15 Power Supplies External Power Input +V J V_JK MMZVL PJ-00H Tower Power Input +V_ELEV 00nF V R00M_0 F LMSGTN +V +V R 0K POWER SUPPLY.V ORE SUPPLY +V PG IN IN S 0 U 00nF MP0Q P SW SW 0 EN/SYN F uf V Low ESR 00nF V +.V L. uh. R 00nF 00K % + 0uF +V +.V R R LE_YELLOW LE_YELLOW R00M_0 R0 K % + 00UF V + 00UF V + 00UF V + 00UF POWER SUPPLY When ELE_PS_SENSE = 0, rive on board +.V to +.V_ELEV and +V to +V_ELEV When ELE_PS_SENSE =, isconnect +.V_ELEV from on board +.V and +V_ELEV from +V +V R 0K.V R- SUPPLY PG U0 MP0Q P IN IN S 00nF SW SW +V 00nF V L. uh. uf V Low ESR +.V + R 00nF 0uF +V U IN OUT IN OUT TL FLG GTE MRM0 +V_ELEV ENLE_IOV 0 EN/SYN F 00K % R 0K % MI0-YM ELE_PS_SENSE K R +V R.K Q MMT0LTG +.V U IN OUT IN OUT TL FLG GTE MI0-YM 0 MRM0 +.V_ELEV POWER SUPPLY.0V ORE SUPPLY R ENLE_IOV PG IN 0K IN S U 00nF MP0Q P SW SW +V R0 0 EN/SYN F +V 0 uf V Low ESR 00nF V +.0V L. uh. R 00nF 00K % + 0uF 0K Power-up Sequence R.M % Voltage.V.V 0%.0V Time Power Supplies Size ocument Number Rev TWR-MP0 Wednesday, October, 0 ate: Sheet of