TABLE OF CONTENTS AND REV HISTORY

Transcription

1 TLE OF ONTENTS N REV HISTORY PGE# TITLE PGE# TITLE PGE# TITLE 0 OVER_PGE Power Supply 0 lock iagram OSM IRUITS 0 MP - Power and ecaps UIO N S 0 MP - onfiguration 0 Reset onfiguration Jumpers 0 MP - LP and NF Interface 0 MP - R- Interface 0 MP - Miscelaneous Interfaces 0 MP - IU HMI Interface 0 MP - US / FE Interface MP - Ethernet R- Memories and Termnations Tower Expansion Main Elevator Tower Expansion Secondary Elevator OVER_PGE Size ocument Number Rev v. TWR-MP Wednesday, February, 00 ate: Sheet of

2 LOK IGRM Tower Expansion (Primary Elevator) FE RMII/US SH NN Flash (Gbyte or Gbyte) R SRM M byte X NF_LE NF_LE NF_RE# NF_WE# NF_WP# EM_[0:] EM_[0:] MQ[:0] MQS0 MM0 IIS it Nano Switch RII ONTROLLER N T US ULPI Jumper Selector US0 US PHY Freescale MP 00MHz.ORE US TYPE Mini- N XI URT PS PS S ard slot crystal.khz reset config Jumpers RX_OSM TX_OSM SPI X HEER X JTG HEER JTG OSM JTG US Type- power supply PSU V.V IN power supply HMI onnector HMI udio /Video Sil0 IU LE.V MEM.V ORE KEY Earphone onnector MI udio decoder WM OIN ELL 0.V VREF 0.V VREF I/ I/ SMS LN0 0/00T PHY RJ 0/00T crystal M N igital accel TJ00T PIN onnecter FE RMII/MII Tower Expansion (Secondary Elevator) LOK IGRM Size ocument Number Rev v. TWR-MP Wednesday, February, 00 ate: Sheet of

3 V_V V_V VV_IO VV_MEM VV_MEM VV_MEM VV_IO VV_IO V_V Size ocument Number Rev ate: Sheet of TWR-MP v. Thursday, February, 00 Size ocument Number Rev ate: Sheet of TWR-MP v. Thursday, February, 00 Size ocument Number Rev ate: Sheet of TWR-MP v. Thursday, February, 00 MP POWER N EPS MP POWER N EPS 0UF 0UF TP mil TP TP mil TP V_IO MP U- V_IO MP U- V_IO V_IO V_IO V_IO V_IO V_IO V_IO V_IO F V_IO H V_IO0 M V_IO R V_IO V V_IO W V_IO W V_IO V_IO V_IO V_IO V_IO V_IO0 V MP U- V MP U- V J0 V J V J V J V K V L V L V M V M V0 N V P0 V P V P V P 0 0 J HR_X J HR_X V_IO_MEM MP U- V_IO_MEM MP U- V_IO_MEM V_IO_MEM V_IO_MEM V_IO_MEM V_IO_MEM G V_IO_MEM H V_IO_MEM P V_IO_MEM R V_IO_MEM T V_IO_MEM0 V V_IO_MEM W V_IO_MEM Y V_IO_MEM UF 0UF 0UF 0UF TP mil TP TP mil TP 0UF 0UF VSS MP U- VSS MP U- VSS VSS VSS VSS VSS VSS VSS VSS F VSS F VSS0 J VSS J VSS K VSS K VSS K0 VSS K VSS K VSS K VSS K VSS L VSS0 L0 VSS L VSS L VSS L VSS L VSS M0 VSS M VSS M VSS M VSS N VSS0 N0 VSS N VSS N VSS N VSS N VSS P VSS P VSS P VSS P VSS U VSS0 U VSS W VSS W0 VSS W VSS W VSS Y VSS VSS VSS VSS J0 HR_X J0 HR_X TP mil TP TP mil TP 0UF 0UF 0 0 J HR_X J HR_X 0 0UF 0 0UF 0 0

4 MP - ONFIGURTION V_V JTG Header,,0,,, HRESET# TP TP mil PORESET# V_V TP TP mil R HRESET# SRESET# PORESET# 0K TP TP TP mil TP mil TP TP mil R 0K R 0K V_V G U- ONFIGURTION HRESET_ SRESET_ PORESET_ V_FUSER V_FUSEWR TRST_ TO TI TK TMS JTG_TRST# JTG_TO JTG_TI JTG_TK JTG_TMS JTG_TMS JTG_TK JTG_TI JTG_TO TP TP mil JTG_TO JTG_TI TP TP mil JTG_TK JTG_TMS SRESET# HRESET# JTG_HKSTOP_OUT JTG_HKSTOP_OUT V_V R 0K R 0K J 0 V_V OP_TRST# R 0UF 0 PF 0 V_PLL TEST R TP 0K JTG_TRST# TP TP mil HR_X V_V V_V R VSS_PLL V_SPLL TMPS_NVIZ SPLL_NVIZ TP TP V_V R 0K V_V 0UF 0 0 PF 0 V_OS_TMPS VSS_OS_TMPS_SPLL HI_MOE_ 0 0 PF 0UF R JTG_TRST# TTG VT RV-0 uf/v V R RV-0 T 0 PF R N RT_XTLI RT_XTLO MP SYS_XTLI SYS_XTLO 0 SYS_XTLI SYS_XTLO PWR_HI R.K U V_V V Vt =.V V_V + R 0M MR# RESET RESET# PORESET# R.K vdc Lithium F0 LMSGTN 0.0uF V R.K X V 0PF Y MHz 0PF SW SW_STMXX GN MXSEXK+T PORESET# TRI_STTE _GN OUT.k MP ONFIGURTION Size ocument Number Rev v. TWR-MP Wednesday, February, 00 ate: Sheet of

5 RESET ONFIGURTION JUMPERS RST FUNTION LP PIN ESRIPTION RST_ONF_LO LP_[:0] efault 0 Selects boot device 00 LP boot 0 NN (NF) boot 0 Factory Test mode, use TPR port at LP Factory Test mode, use TPR port at IU RST_ONF_MS RST_ONF_LP_W LP_[] efault LP_[:] efault 00 oot mode select: Selects e00 boot vector and configures default value for LP S0 or NF base address. LP ata Port Size 00 bit 0 Reserved 0 bit bit S_MXS0_SM 0 R R R R0 0K 0K 0K 0K RST_ONF_ROMLO0 RST_ONF_MS RST_ONF_LP_W0 RST_ONF_LP_W LP_0 LP_ LP_ LP_ LP_[:0],, RST_ONF_OREPLL LP_[:] ore PLL Multiply factor.0 : efault 00 See clock module for programming options R R 0K 0K RST_ONF_LPW RST_ONF_LPMX LP_ LP_ RST_ONF_SYSPLL LP_[:] System PLL Multiply factor : efault 00 See clock module for programming options RST_ONF_SYSIV RST_ONF_SYSOSEN LP_[:] efault 000 LP_[] efault System PLL divider ratio See clock module for programming options Oscillator ypass Mode 0 System Oscillator bypass mode System Oscillator mode SW V_V V_V R R R0 R R R R R R R R0 R 0K RST_ONF_OREPLL 0K RST_ONF_SYSPLL0 0K RST_ONF_SYSPLL 0K RST_ONF_SYSOSEN 0K RESERVE - ONNET TO 0K NP RST_ONF_SYSPLL 0K NP 0K NP 0K NP 0K NP 0K NP 0K LP_ LP_ LP_0 LP_ LP_ LP_ RST_ONF_LONGF RST_ONF_LPW RST_ONF_LP_TS LP_[] efault LP_[] LP_[] Reserved (must be tied to logic high) RST_ONF_PLLLOK LP_[] Use PLL lock signal use counter efault 0 0 use PLL lock signal RST_ONF_LPMX LP_[] LP Mux mode configuration 0 Non-multiplexed mode efault 0 Multiplexed mode efault efault 0 LP Word/yte address ddress is interpreted as byte address 0 ddress is interpreted as word address Use LP_TS, LP_TSIZE[:0] if boot from LP use LP_TS, LP_TSIZE[:0] if boot from LP 0 set LP_TS, LP_TSIZE[:0] is set to one if boot from LP V_V R R R R R R R0 R R R R R R R R R R R 0K NP 0K NP 0K NP 0K NP 0K NP 0K NP 0K NP 0K NP 0K NP 0K RST_ONF_SYSIV 0K RST_ONF_OREPLL 0K RST_ONF_OREPLL 0K RST_ONF_LP_TS 0K RST_ONF_ROMLO 0K RST_ONF_SYSPLL 0K RST_ONF_SYSIV0 0K RST_ONF_SYSIV 0K RST_ONF_PLLLOK LP_ LP_ LP_ LP_ LP_ LP_ LP_ LP_ LP_ Parameter MS=0(oot low) MS=(oot high) e00 oot Vector 0 X X FFF0000 Parameter MS=0(oot low) MS=(oot high) LP SOOT Start 0 X X FFF00000 LP SOOT End 0 X 000FFFF 0 X FFFFFFFF NF ase ddress 0 X X FFF00000 RESET ONFIG JUMPERS Size ocument Number Rev v. TWR-MP Wednesday, February, 00 ate: Sheet of

6 MP - LP N NF 0.0uF/nc V LP_0 LP_ LP_ LP_ LP_[:0],, LP_LK LP_LK R R LP_LK_R R LP_LK/TP/GPIO0 U- LPM / NF LP_ LP_ LP_ LP_ LP_R/W# LP_OE# LP_S0# LP_K#, LP_LE# LP_X0 LP_X0 LP_X0 LP_R/W# LP_OE# LP_S0# LP_K# NF_E LP_LE# LP_X00 LP_X0 LP_X0 LP_X0 NF_E# NF_R/# R R R R R TP0 R0 R R R R R R R R R R TP mil R R R R R R N N M P K N L L P N LP_00/NF_00/RST_ONF_LO0 LP_RW/PS_/GPIO0 LP_0/NF_0/RST_ONF_LO LP_OE_/PS_/GPIO0 LP_0/NF_0/RST_ONF_MS LP_0/NF_0/RST_ONF_LPW0 LP_S0_/GPIO0 LP_0/NF_0/RST_ONF_LPW LP_K_/LP_URST_/NF_E_/LP_S_/GPIO0 LP_0/NF_0/RST_ONF_OREPLL LP_0/NF_0/RST_ONF_OREPLL LP_0/NF_0/RST_ONF_OREPLL LP_0/NF_0/PS_/RST_ONF_SPMF0/GPIO E LP_0/NF_0/PS_/RST_ONF_SPMF/GPIO LP_0/NF_0/PS_0/RST_ONF_SPMF/GPIO LP_/NF_/PS_/RST_ONF_SPMF/GPIO LP_X00/LP_LE LP_/NF_/PS_/RST_ONF_PREIV0/GPIO E LP_X0/LP_TSIZ0/LP_S_ LP_/NF_/PS_/RST_ONF_PREIV/GPIO E LP_X0/LP_TSIZ/NF_E_/LP_S_ LP_/NF_/PS_/RST_ONF_PREIV/GPIO H LP_X0/LP_TS/NF_E_/LP_S_ LP_/NF_/PS_0/RST_ONF_SYSOSEN/GPIO E LP_/LP_0/NF_WE/RST_ONF_LONGF F LP_/LP_0/NF_RE/RST_ONF_PLLLOK G LP_/LP_0/NF_LE/RST_ONF_LPMX G LP_/LP_0/NF_LE/RST_ONF_LPW J LP_0/LP_0/TPR_K/GPIO0 H LP_/LP_0/TPR_SYN/GPIO F LP_/LP_0/TPR_[]/RST_ONF_LP_TS/GPIO K LP_/LP_0/TPR_[]/GPIO J LP_/LP_0/TPR_[]/GPIO K LP_/LP_0/TPR_[]/GPIO G LP_/LP_/TPR_[]/GPIO J NF_E0_/GPIO LP_/LP_/TPR_[]/GPIO M NF_R/GPIO0 LP_/LP_/TPR_[]/GPIO H LP_/LP_/TPR_[0]/GPIO L LP_0/LP_/N_LK/GPIO0 M LP_/LP_/PS_MLK_IN/GPIO0 J LP_0/NF_0 LP_/NF_ LP_/NF_ LP_/NF_ LP_/NF_ LP_/NF_ LP_/NF_ LP_/NF_ LP_/NF_ LP_/NF_ LP_0/NF_0 LP_/NF_ LP_/NF_ LP_/NF_ LP_/NF_ LP_/NF_ LP_/NF_WE LP_/NF_RE LP_/NF_LE LP_/NF_LE LP 0 LP LP LP LP LP LP LP LP LP LP 0 LP LP_ LP_ LP_0 LP_ LP_ LP_ LP_ LP_ LP_ LP_ LP_ LP_ LP_0 LP_ LP_ LP_ MP LP_ LP_ LP_ LP_ LP_ LP_ LP_0 LP_ V_V 0uF V 0.uF V 0.0uF V R.K R.K U0 V_V NF_R/# R.K LP_0/NF_0 LP_/NF_ LP_/NF_ LP_/NF_ LP_/NF_ LP_/NF_ LP_/NF_ LP_/NF_ 0 0 I/O0 I/O I/O I/O I/O I/O I/O Gb X NN I/O FLSH R/# R/# Gb X NN N N N N N0 N N N N N N N V V VSS VSS LE LE E# E# 0 RE# WE# WP# N N N N N N N N N 0 N0 N N N N N LP_/NF_LE LP_/NF_LE NF_E# NF_E LP_/NF_RE LP_/NF_WE R R.K nm HRESET#,,0,,, MTFG0MW OR MTFG0FWP MP LP N NF Size ocument Number Rev v. TWR-MP Monday, March 0, 00 ate: Sheet of

7 MP - R- MEMORY INTERFE R_Q[:0] R_QS0 R_QS R_QS R_QS R_QM0 R_QM R_QM R_QM R_QS0 R_QS R_QS R_QS R_QM0 R_QM R_QM R_QM R_Q0 R_Q R_Q R_Q R_Q R_Q R_Q R_Q R_Q R_Q R_Q0 R_Q R_Q R_Q R_Q R_Q R_Q R_Q R_Q R_Q R_Q0 R_Q R_Q R_Q R_Q R_Q R_Q R_Q R_Q R_Q R_Q0 R_Q U- SRM MQ00 Y MQ0 MQ0 MQ0 MQ0 Y0 MQ0 W0 MQ0 U MQ0 MQ0 Y MQ0 V0 MQ0 W MQ W MQ T0 MQ V MQ U MQ R0 MQ/GPT0 T MQ/GPT P0 MQ/GPT T MQ/GPT N0 MQ0/GPT P MQ/GPT N MQ/GPT M0 MQ/GPT M MQ/GPIO M MQ/GPIO L0 MQ/GPIO L MQ/GPIO K0 MQ/GPIO J MQ/GPIO J MQ0/GPIO J0 MQ/GPIO 0 MQS0 U0 MQS P MQS/GPIO L MQS/GPIO Y MM0 V MM R MM/GPIO K MM/GPIO0 MP M00 M0 M0 M0 M0 M0 M0 M0 M0 M0 M0 M M M M M/MS M0 M M MKE MK MK_ MS0_ MWE_ MS_ MRS_ MVTT MVTT MVTT MVTT0 MVREF MOT G0 R_0 F R_ F R_ E R_ E R_ F0 R_ R_ E0 R_ R_ R_ E R_0 R_ 0 R_ 0 0 H R_0 H0 R_ G R_ R_KE H R_K G R_K# R_S# R_WE# 0 R_S# R_RS# VTT_R K M R W N J R_OT R_[:0] R_0 R_ R_ R_KE R_K R_K# R_S# R_WE# R_S# R_RS# VREF_R R_OT VTT_R 0 Note: Place the Voltage evider and the decap near the Pin. Provide Groundgaurd to the Vref Line MP R INTERFE Size ocument Number Rev v. TWR-MP Wednesday, February, 00 ate: Sheet of

8 MP - EL INTERFE V_V V_V0 U-0 PS PS_0/SH_LK/GPT/N_TX PS_/N_LK/GPT/IRQ0 PS_/TP/GPT/IRQ PS_/KSTP_IN/NF_R/GPIO PS_/KSTP_OUT/NF_E_/GPIO0 MP R R R0 R0 JTG_HKSTOP_OUT TS RTS RX_OSM TX_OSM N_TX N_RX U S TX RX VIO V NH NL GN NH NL R0 J R 0K R 0K R.K TJ0T/ J R ON HR_X.NF U- GPIO GPIO00 GPIO0 GPIO0 GPIO0 R R R R R 0 NP NP NP NP NP _INT GPIO_ELEV0 INTR#_HMI S_WP_ET, S_R_ET, MP R R R0 V_V R.K.K.K.K SW_STMXX SW V_V V_V 0 U N RESERVE V N VSS V, I_S S/SI/SO VSS, I_SL SL/SP INT/ EL_INTERRUPT EL_INTERRUPT MM0F V_V V_V U- I / N / J0 I_SL/PS_/N_RX/GPIO I_S/PS_/N_TX/GPIO0 I_SL/PS_/US_LK/GPIO V I_S/PS_/US_STOP/GPIO U URT_TX URT_RX I_SL I_S R0.K R0.K R0.K R0.K URT_TX URT_RX I_SL I_S R0 N_RX R0 N_TX/PS_0/I_SL/GPIO R R N_RX N_TX N_RX R N_TX/PS_/I_S/GPIO R R R N_RX N_TX J0_RX/NF_R/I_S J0_TX/NF_E_/I_SL I_S I_SL I_S, I_SL, MP U- PS0 PS_MLK_IN/GPIO PS0_0/SH_M/GPT0/GPIO PS0_/SH_0/GPT/GPIO PS0_/SH IRQ/GPT/GPIO PS0_/SH_/GPT/GPIO PS0_/SH /GPT/N_TX R0 MP R Note: R R R PS0 port need to be configured to IS Master mode R R R R R R R EL_INTERRUPT NP GPIO_ELEV GPIO_ELEV NP PS0_0 NP PS0_ NP PS0_ NP PS0_ NP PS0_ LK ITLK R PS0_[:0], R LK SYN R R _STOUT R _STIN RST_RESET 0.0uF/nc V MP RS N EL Size ocument Number Rev v. TWR-MP Monday, March 0, 00 ate: Sheet of

9 MP - IU N HMI INTERFE U- IU MP N_RX/LK/IU_L00/GPIO N_TX/LK/IU_L0/GPIO IU_L0/PS_/US_T/LP_X0 IU_L0/PS_0/US_T/LP_X0 IU_L0/PS_/US_T/LP_X0 IU_L0/PS_/US_T/GPIO IU_L0/PS_/US_STOP/GPIO IU_L0/PS_/US_LK/GPIO N_RX/PS_0/IU_L0/GPIO N_TX/PS_/IU_L0/GPIO IU_L0/PS_/US_NEXT/GPIO IU_L/PS_/US_IR/GPIO0 IU_L/PS_/US_T0/GPT IU_L/PS_0/US_T/GPT IU_L/PS_/US_T/GPT0 IU_L/PS_/US_T/GPT LK0/I_SL/IU_L/GPIO LK/I_S/IU_L/GPIO IU_L/PS_/US_T/GPT IU_L/PS_/US_T/GPT IU_L0/PS_0/US_T/GPT IU_L/PS_/US_T/GPT IU_L/PS_/US_IR/GPIO IU_L/PS_/US_NEXT/GPIO IU_LK/PS_0/US_T0/LP_X0 IU_HSYN/PS_/US_T/LP_X0 IU_VSYN/PS_/US_T/GPIO IU_E/PS_/US_T/LP_X0 Y0 0 Y 0 Y W Y W Y Y W Y W Y TP TP TP mil TP mil IU_L0 IU_L IU_L IU_L IU_L IU_L IU_L IU_L IU_L IU_L IU_L0 IU_L IU_L IU_L IU_L IU_L IU_L IU_L IU_L IU_L IU_L0 IU_L IU_L IU_L TP TP mil R R R R R0 TP TP mil R R R IU_LK IU_HSYN IU_VSYN IU_E /nc IU_L[:0] IU_LK IU_HSYN IU_VSYN IU_E 0 /nc /nc /nc,,0,,, HRESET# HRESET# R 0 IU_L IU_L IU_L IU_L0 IU_L IU_L IU_L IU_L IU_L IU_L IU_L IU_L IU_L IU_L0 IU_L IU_L IU_L IU_L IU_L IU_L IU_L IU_L IU_L IU_L0 U0 RESET# EXT_SWG SL S HP INT E 0 E SL S RSVL I IO_SEL VQ 0 SWG TX_SL TX_S HPIN R INTR#_HMI E_ R R I K R.k,% V_V0 0 0 P LYOUT: 00ohm differential impedance for TMS traces F L0 SLV SV R0.K R K INTR#_HMI R.K P LYOUT: Place ES device close to connector R K IOV 0 0 I_SL, I_S, U Rlamp0P LINE N N LINE GN GN0 LINE N N LINE LINE N N LINE GN GN0 LINE N N LINE U Rlamp0P RV Varistor RV Varistor RV TX+ TX_SL TX_S _V HPIN Varistor TX+ TX- TX0+ TX0- TX+ TX- TX- E_ TX- TX0+ TX+ TX- TX0- TX+ TX- TX+ TX+ TX- TX+ TX- TX0+ TX0- TX+ TX- N SHELL 0 + SHELL Shield - + Shield Shield 0-0 K+ K Shield K- E Remote N LK T GN +V HPSHELL SHELL HMI ON-SMT P LYOUT: Layout footprint to support connector from JE & Molex R.K R.K R.K IU_VSYN IU_HSYN IU_E VSYN HSYN E IU_LK IK,,,, PS0_ PS0_0 PS0_ PS0_ SPIF_UNUSE PS0_ MLK PS0_0 ITLK PS0_ SYN IS_UNUSE_ IS_UNUSE_ IS_UNUSE_ PS0_ IS_T 0 SPIF MLK SK WS S S S S0 V_ V_ 0 V V V V V R.K R.K R.K R.K IS_UNUSE_ IS_UNUSE_ IS_UNUSE_ SPIF_UNUSE V_ V_ V_ V_ GN V_ IOGN V_ GN P IOV_ IOV_ IOV_ SiI0 TQFP-00 V IOV IOV + S 0uF/0v 0 V_V IOV F LM00SNJ + S 0uF/0v F LM00SNJ V V V_V U VINVOUT V F LM00SNJ 0.uF EN GN N + S 0uF/0v EMP-VF0GRR MP - IU,HMI INTERFE Size ocument Number Rev v. TWR-MP Monday, March 0, 00 ate: Sheet of

10 MP - US N FE INTERFE RYSTL V_V V_V V_V R 0M U- US US_T0/PS_0/FE_RX_/RMII_RX/TPR_[0] Y US_T/PS_/FE_TX_/RMII_TX/TPR_[] W US_T/PS_/FE_M/RMII_M/TPR_[] US_T/PS_/FE_RX_ER/RMII_RX_ER/TPR_[] US_T/PS_/FE_MIO/RMII_MIO/TPR_[] US_T/PS_0/FE_RX_0/RMII_RX0/TPR_[] Y US_T/PS_/FE_TX_0/RMII_TX0/TPR_[] Y US_T/PS_/FE_TX_LK/RMII_REF_LK/TPR_[] US_LK/PS_/FE_RX_V/RMII_RS_V/TRP_K Y US_STOP/PS_/FE_RX_LK/TPR_SYN W US_NEXT/FE_TX_EN/RMII_TX_EN/GPIO0 US_IR/FE_OL/GPIO0 W MP US_T0/FE_RX_ US_T/FE_TX_ US_T/FE_M US_T/FE_RX_ER US_T/FE_MIO US_T/FE_RX_0 US_T/FE_TX_0 US_T/FE_TX_LK US_LK/FE_RX_V US_STOP/FE_RX_LK US_NEXT/FE_TX_EN US_IR/FE_OL US_LK US_NEXT US_T0 US_T US_T US_T US_T US_T US_T US_T US_IR US_STOP R 0k _NP U LKOUT NXT T0 T T T T T 0 T T IR STP VIO VV 0 VV US0 REFLK XO RIS T V I VUS 0 M P 0PF R0 ST_US I US VUS US n US p Y MHz.0K,% R 0PF K.uF V V_V V_V 0.uF V R00 0K 00 R00 K OTG 0K evice/host 0.uF V US_device_p,,,,, HRESET# R RESET# REFSEL0 REFSEL I, US0, US Transceiv.QFN- N REFSEL SPK_L SPK_R PEN FLG V_V R0 TP TP mil TP TP mil V_V0 V_V IN N0- H OM=NO L OM=N R R R NP R NP V R0 0uF 0 V Host/OTG 0.uF NP evice U R EN# _00 R0 FLG# OUT NP R0 _NP EN# OUT FLG# REFLK REFSEL[:0] + 0 Source 0 00UF/.v M I M M 0K R K R 0K R R K NP R KNM IN GN US_device_p M FOR SEON ETHERNET J HR_X US_T0/FE_RX_ US_T/FE_TX_ US_T/FE_M US_T/FE_RX_ER US_T/FE_MIO US_T/FE_RX_0 R.K R R R R R R 0.uF V R R R R R R 0 0 U V GN EN IN IN N.. OM OM OM OM OM OM N N N N N N NO NO NO NO NO NO FE_RX_b FE_TX_b FE_Mb FE_RX_ERb FE_MIOb FE_RX_0b US_T0 US_T US_T US_T US_T US_T FE_RX_b FE_TX_b FE_Mb FE_RX_ERb FE_MIOb FE_RX_0b V_V to u pin /0/ 0.0uF 0uF 0.uF 0.uF V V V V 0.M 0 M 00.M 00 M V_V 0.0uF V 0.0uF US_device_p US n US p R SW0--00 L.k_NP ST_US I S S VUS - + I G OWN US_MINI_ TSEPWR U0 S S F US_T/FE_TX_0 US_T/FE_TX_LK US_LK/FE_RX_V US_STOP/FE_RX_LK US_NEXT/FE_TX_EN US_IR/FE_OL R R R R R0 R R R R R R R 0.0uF/nc V V N GN N 0 EN N IN N IN N N.. N OM NO OM NO OM NO OM NO 0 OM NO OM NO TSEPWR 0.0uF/nc V FE_TX_0b FE_TX_LKb FE_RX_Vb FE_RX_LKb FE_TX_ENb FE_OLb US_T US_T US_LK US_STOP US_NEXT US_IR FE_TX_0b FE_TX_LKb FE_RX_Vb FE_RX_LKb FE_TX_ENb FE_OLb V_V R.K R.K LMSGTN FE_Mb FE_MIOb MP US/FE Size ocument Number Rev ustom v. TWR-MP Monday, March 0, 00 ate: Sheet of 0

11 MP - MIS. INTERFES, PS_[:0] PS_ PS_ PS_ PS_0 SPIO_MiS0 SPIO_MOSI SPIO_S SPIO_LK 0.0uF/nc V PS PS_0 R0 R SPI R0 NP R0 NP MII R0 R U- FE FE_TX_LK/RMII_REF_LK/PS0_0/GPIO0 W FE_TX_0/RMII_TX0/NF_R/GPIO W FE_TX_/RMII_TX/PS_/US_T/GPIO W FE_TX_/PS_0/US_T0/GPIO FE_TX_/PS_/US_T/GPIO Y FE_TX_LK FE_TX_0 FE_TX_ FE_TX_ FE_TX_ R R R R0 R R R R R R FE_TX_LKb FE_TXb_0 FE_TXb_ PS_0 PS_ SPIO_LK SPIO_S FE_TX_LKb FE_TXb_[:0] V_V LMSGTN F V PS_ PS_ PS_ R R R R R R R NP R0 NP R NP R NP R NP R NP R R R0 R R R FE_TX_EN/RMII_TX_EN/PS0_/GPIO0 Y FE_TX_ER/PS_0/US_T/GPIO W FE_M/RMII_M/PS_/US_IR/GPIO V FE_MIO/RMII_MIO/US_LK/GPIO V FE_OL/PS0_/GPIO0 U FE_RS/PS_/US_T/GPIO U FE_RX_V/RMII_RS_V/PS0_/NF_R/GPIO0 FE_RX_ER/RMII_RX_ER/PS_/US_NEXT/GPIO0 Y FE_RX_0/RMII_RX0/US_STOP/GPIO FE_RX_/RMII_RX/PS_/US_T/GPIO FE_RX_/PS_/US_T/GPIO Y FE_RX_/PS_/US_T/GPIO FE_RX_LK/PS0_/NF_R/GPIO0 MP FE_RX_LK FE_TX_EN FE_TX_ER FE_M FE_MIO FE_OL FE_RS FE_RX_V FE_RX_ER FE_RX_0 FE_RX_ FE_RX_ FE_RX_ R FE_RX_V R R R R R R R0 R R R R R R R MII/RMII R R R R R R R R R R R R FE_RX_LKb 0.0uF/nc V FE_TX_ENb FE_TX_ERb FE_Mb FE_MIOb FE_OLb FE_RSb FE_RX_Vb FE_RX_ERb FE_RXb_0 FE_RXb_ PS_ PS_ FE_MIO FE_M FE_RX_ FE_RX_ FE_RX_ FE_RX_0 FE_RX_V FE_RX_LK FE_RX_ER R0 R0 R R0 R0 R0 R0 R R FE_TX_LK R FE_TX_EN R0 FE_TX_0 R0 FE_TX_ R0 FE_TX_ R0 FE_TX_ R FE_OL R00 FE_RS R0 R0 ROL/RS_V/MOE R FE_TX_ENb FE_TX_ERb FE_Mb FE_MIOb FE_OLb FE_RSb FE_RX_Vb FE_RX_ERb FE_RXb_[:0] SPIO_MOSI SPIO_MiS0 FE_RX_LKb R R NP NP R R NP NP R NP R R R NP NP _NP NP R R R.K RX/PHY RX/RMIISEL RX/MOE RX0/MOE0 RXV RXLK/PHY RXER/RX/PHY0 TXLK TXEN TX0 TX TX TX OL/RS_V/MOE RS 0.uF V 0% 0 0 VIO 0.uF V 0% VIO R0 ZERO /0W 0.uF V 0% MIO M RX/PHY RX/RMIISEL RX/MOE RX0/MOE0 RXV RXLK/PHY RXER/RX/PHY0 TXLK TXEN TX0 TX TX TX OL/RS_V/MOE RS XTL XTL/LKIN V V 0.uF V 0% U LN0 nint/txer/tx RIS VR VR nrst VSS/FLG.uF.V 0% TXP TXN RXP RXN 0 LE/REGOFF LE/nINTSEL R R /W % R R /W % LE/REGOFF LE/nINTSEL 0pF V 0% R R /0W R R /0W ETH_MI_TPTXp ETH_MI_TPTXn ETH_MI_TPRXp ETH_MI_TPRXn 0pF 0pF V V 0pF 0% V 0% 0% V R NM RX_T TX_T 0.uF V 00PF V LE/nINTSEL ETH_MI_TPRXp ETH_MI_TPRXn ETH_MI_TPTXp ETH_MI_TPTXn N L- L- TX- R+ T TX+ T R- RJ- PT-0L L+ L+ SHIEL 0 LE = LINK/T LE = SPEE R0 R 0 ES 00 LMSGTN F V LE/REGOFF V_V F 000pF,KV LMSGTN 0.0uF V R X.K TRI_STTE V _GN OUT R R Note: apacitors through are optional for EMI purposes and are not populated on the LN0 evaluation board. These capacitors are required for operation in an EMI constrained environment. 0MHZ FE_TX_LK R R GPIO_ELEV0I R R,,,0,, HRESET# _NP R.K /0W % 0.uF/NP V Resistor R R R onfiguration Resistor Settings POPULTE EMPTY PHY[0] = PHY[0] = 0 PHY[] = PHY[] = 0 PHY[] = PHY[] = 0 VR R R R R R RMII mode selected MII mode selected Internal.V reg. disabled Internal.V reg enabled MOE[0] = 0 MOE[0] = MOE[] = 0 MOE[] = MOE[] = 0 MOE[] = Note: & decoupling capacitors for VR added as rework. These capacitors should be placed as close to LN0 as possible. 0.uF V 0.uF V R INTERRUPT FUNTION ISLE ON nint/txer/tx SIGNL INTERRUPT FUNTION ENLE ON nint/txer/tx SIGNL Pull-up onfiguration Jumpers Pull-down onfiguration Resistors VIO V Note: To be connected to V on future P revisions. RX0/MOE0 RX/MOE OL/RS_V/MOE R 0K /0W % R R R N_0.0K N_0.0K 0K /0W /0W /0W % % % NP NP R N_0.0K /0W % LE/REGOFF NP RX/RMIISEL LE/nINTSEL NP NP NP NP R R R R N_0.0K N_0.0K N_0.0K N_0.0K /0W /0W /0W /0W % % % % RX/PHY RXER/RX/PHY0 RXLK/PHY [:0] dress set :0 MOE[:0] = MP - MIS. INTERFES Size ocument Number Rev v. TWR-MP Thursday, February, 00 ate: Sheet of

12 R_Q R_Q R_WE# R_S# R_RS# R_0 R_ R_ R_ R_ R_ R_ R_ R_ R_ R_0 R_ R_ R_Q0 R_Q R_Q R_Q R_Q R_0 R_S# R_Q R_Q R_ R_Q R_0 R_S# R_Q R_ R_Q R_Q0 R_Q0 R_Q R_ R_ R_QS0 R_ R_ R_KE R_Q R_ R_QS R_ R_OT R_ R_ R_Q R_ R_Q R_QS R_0 R_ R_Q R_ R_0 R_ R_ R_QS R_Q R_Q R_K R_Q R_K# R_Q R_Q R_QM0 R_KE R_OT R_Q0 R_QM R_Q R_Q R_K R_K# R_Q R_K R_K# R_Q R_Q R_WE# R_Q R_S# R_RS# R_Q R_QM R_QM R_RS# R_S# R_ R_0 R_ R_S# R_KE R_WE# R_OT V_V V_V V_V V_V VREF_R VREF_R V_V V_V V_V R_S# R_KE R_OT R_0 R_Q[:0] R_QS0 R_QS R_K R_QM0 R_WE# R_QM R_S# R_RS# R_K# R_QS R_QS R_ R_ R_[:0] R_QM R_QM R_OT Size ocument Number Rev ate: Sheet of TWR-MP v. Wednesday, February, 00 Size ocument Number Rev ate: Sheet of TWR-MP v. Wednesday, February, 00 Size ocument Number Rev ate: Sheet of TWR-MP v. Wednesday, February, 00 R- MEMORIES N TERMINTIONS Note: Place the R LK Termination resistor close the hips R MEMORIES_TERMINTIONS 0 0 R 0K R 0K R 0K R 0K R NP R NP R 0K R 0K 0 0 R MEMORY MTHMHR-:G U R MEMORY MTHMHR-:G U Q F Q H Q Q G VREF J KE K 0 L 0/P M N P R UM Q LM F Q H M N P UQS Q0 LQS F Q H M N P UQS Q LQS E Q0 G K K 0 M N P L Q F Q H OT K Q Q Q Q N R N R N R N E N L S L WE K S L RS K K J V V E V R V M V J VQ VQ G VQ VQ G VQ VQ G VQ VQ VQ E VQ0 G VL J VSSQ VSSQ F VSSQ H VSSQ VSSQ E VSSQ VSSQ VSSQ F VSSQ0 H VSS N VSS VSS E VSS J VSS P VSSQ VSSL J R0 0K R0 0K 0 0 uf uf 0 0 R0 0K R0 0K 0 0 R 0 R R 0K R 0K R 0K R 0K uf uf R 0K R 0K 0 0 R MEMORY MTHMHR-:G U R MEMORY MTHMHR-:G U Q F Q H Q Q G VREF J KE K 0 L 0/P M N P R UM Q LM F Q H M N P UQS Q0 LQS F Q H M N P UQS Q LQS E Q0 G K K 0 M N P L Q F Q H OT K Q Q Q Q N R N R N R N E N L S L WE K S L RS K K J V V E V R V M V J VQ VQ G VQ VQ G VQ VQ G VQ VQ VQ E VQ0 G VL J VSSQ VSSQ F VSSQ H VSSQ VSSQ E VSSQ VSSQ VSSQ F VSSQ0 H VSS N VSS VSS E VSS J VSS P VSSQ VSSL J R 0K R 0K

13 MIN ELEVTOR V_V_ELEV V_V_ELEV V_V0_ELEV V_V0_ELEV SH_LK SH SH_M/SPI_LK SH_0/SPI_S# ELE_PS_SENSE SH_LK SH SH_M/SPI_LK SH_0/SPI_S# ELE_PS_SENSE 0 J V_ GN_.V_ ELE_PS_SENSE GN_ GN_ SPI_LK SPI_S SPI_S0 SPI_MOSI SPI_MISO V_ GN_.V_.V_ GN_ GN_ SL0 S0 GPIO/OPEN GPIO/OPEN GPIO/OPEN 0 I_SL I_S SH_/MISO S_WP_ET I_SL, I_S, SH_/MISO S_WP_ET, 0 FE_OLb FE_OLb 0 FE_RX_ERb FE_RX_ERb FE_TX_LKb R 0 FE_TX_LKb 0 FE_TX_ENb FE_TX_ENb 0 FE_TX_b FE_TX_b FE_TX_0b 0 FE_TX_0b SH IRQ/SPI_MOSI SH IRQ/SPI_MOSI FE_TX_LKb R J HRX N_RX N_RX, PS_[:0] N_TX N_TX PS_ SPIO_MiS0 PS_ SPIO_MOSI PS_ SPIO_S PS_0 SPIO_LK I_SL I_SL I_S I_S S_R_ET, S_R_ET GPIO_ELEV0 GPIO_ELEV LP_LE#, LP_LE# LP_S0#,, LP_[:0] LP_S0# LP_ LP_ LP_ LP_ LP_ LP_R/W# LP_R/W# LP_OE# LP_OE# LP_ LP_ LP_ LP_ LP_ LP_ LP_ LP_ ETH_OL ETH_RS ETH_RXER ETH_M ETH_TXLK/ETH_REF_LK ETH_MIO ETH_TXEN ETH_RXLK ETH_TXER ETH_RXV/ETH_RS_V ETH_TX ETH_RX ETH_TX ETH_RX ETH_TX ETH_RX ETH_TX0 ETH_RX0 GPIO/OPEN SSI_MLK GPIO/OPEN SSI_LK GPIO/OPEN SSI_FS LKIN0 SSI_RX LKOUT SSI_TX GN_ GN_ N N N N N N N N0 GN_ GN_ 0 TMR TMR TMR TMR0 GPIO/OPEN GPIO/OPEN.V_.V_ PWM PWM PWM PWM PWM PWM PWM PWM0 NRX RX0 NTX TX0 N RX SPI0_MISO TX SPI0_MOSI GPIO0 SPI0_S0 GPIO0 SPI0_S GPIO0 SPI0_LK GPIO0 GN_ GN_ SL GPIO0 S GPIO0 GPIO/OPEN GPIO0 US_P_POWN TMS/KPT_ US_M_POWN US_M IRQ_H US_P IRQ_G US_I IRQ_F US_VUS IRQ_E TMR IRQ_ TMR IRQ_ TMR IRQ_ TMR IRQ_ RSTIN_ F_LE/F_S_ RSTOUT_ F_S0_ LKOUT0 GN_ GN_0 F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 F_R/W_ F_ F_OE_ F_ F_ F_ F_ F_ F_ F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 F_0 GN_ GN_.V_.V_ FE_Mb FE_MIOb FE_RX_LKb FE_RX_Vb FE_RX_b FE_RX_0b PS0_ PS0_0 PS0_ PS0_ PS0_ URT_RX URT_TX HRESET# LP_LK LP_ LP_ LP_0 LP_ LP_ LP_ LP_ LP_ LP_ LP_ LP_ LP_ LP_0 LP_ LP_ URT_RX URT_TX FE_Mb 0 FE_MIOb 0 FE_RX_LKb 0 FE_RX_Vb 0 FE_RX_b 0 FE_RX_0b 0 PS0_[:0], HRESET#,,,0,, LP_LK EGE PI EXPRESS TOWER EXP - MIN ELEVTOR Size ocument Number Rev v. TWR-MP Friday, February, 00 ate: Sheet of

14 LP_K# IU_VSYN IU_LK IU_L IU_L IU_E LP_ LP_ LP_0 LP_ LP_LE# LP_X0 LP_X0 LP_X0 IU_L0 IU_L IU_L IU_L IU_L IU_HSYN IU_L IU_L IU_L IU_L LP_X0 IU_L IU_L FE_RXb_ LP_K# IU_L0 FE_RXb_0 IU_L IU_L IU_L IU_L IU_L IU_L0 IU_L LP_X0 IU_L LP_X0 IU_L LP_X0 LP_X0 IU_L LP_X0 LP_[:0] LP_K# LP_ LP_ LP_ LP_ LP_ LP_ LP_0 LP_ LP_ LP_ LP_ LP_ LP_0 LP_ LP_ LP_ LP_ LP_ LP_ LP_ LP_0 LP_ LP_ LP_ LP_ LP_ LP_0 LP_ FE_Mb FE_TXb_ FE_RXb_ FE_MIOb FE_RX_ERb FE_RX_LKb FE_TX_LKb FE_RX_Vb FE_TX_ENb FE_RXb_0 FE_OLb FE_TX_ERb FE_RSb FE_TXb_0 FE_TXb_ FE_TXb_0 ELE_PS_SENSE V_V0_ELEV V_V_ELEV V_V0_ELEV V_V_ELEV IU_HSYN IU_VSYN IU_LK IU_E LP_X0 LP_X0 LP_X0 LP_LE#, IU_L[:0] LP_[:0],, LP_K# FE_Mb FE_MIOb FE_RX_ERb FE_RXb_[:0] FE_RX_LKb FE_TX_LKb FE_RX_Vb FE_TXb_[:0] FE_TX_ENb FE_OLb FE_TX_ERb FE_RSb ELE_PS_SENSE Size ocument Number Rev ate: Sheet of TWR-MP v. Wednesday, February, 00 Size ocument Number Rev ate: Sheet of TWR-MP v. Wednesday, February, 00 Size ocument Number Rev ate: Sheet of TWR-MP v. Wednesday, February, 00 SEONRY ELEVTOR LP_X00 LP_S# LP_S# LP_S# LP_S# LP_URST# LP_TSIZ0 LP_TSIZ LP_TS TOWER EXP - SEON ELEVTOR EGE PI EXPRESS J EGE PI EXPRESS J V_ GN_.V_ ELE_PS_SENSE GN_ GN_ SPI_LK SPI_S SPI_S0 SPI_MOSI 0 SPI_MISO ETH_OL ETH_RXER ETH_TXLK/ETH_REF_LK ETH_TXEN ETH_TXER GPIO0 GPIO0 ETH_TX ETH_TX0 0 US_NEXT US_IR US_T US_T US_T GN_ L_HSYN/L L_VSYN/L N N 0 GN_ L_LK/L TMR TMR0 GPIO/OPEN.V_ PWM PWM PWM PWM 0 NRX NTX GPIO0 L_OE/L L_0/L0 L_/L L_/L L_/L GN_ GPIO0 0 GPIO0 L_/L L_/L L_/L IRQ_H IRQ_G IRQ_F IRQ_E IRQ_ IRQ_ 0 IRQ_ IRQ_ L_/L L_/L GN_ F_0/L F_/L F_/L F_/L F_/L 0 F_/L F_/L F_/L F_/L0 F_/L F_0/L F_/L L_0/L0 L_/L L_/L 0 GN_.V_ V_ GN_.V_.V_ GN_ GN_ SL0 S0 GPIO/OPEN US_SOTP 0 US_LK GPIO ETH_M ETH_MIO ETH_RXLK ETH_RXV/ETH_RS_V GPIO0 GPIO0 ETH_RX ETH_RX0 0 US_T0 US_T US_T US_T US_T GN_ N N0 N N 0 GN_ GPIO0 TMR TMR GPIO/OPEN.V_ PWM PWM0 PWM PWM 0 RX TX RTS TS RX TX RST ST GN_ L_/L 0 L_/L L_/L L_/L L_/L L_/L L_0/L0 L_/L TMR TMR TMR 0 TMR L_/L L_/L L_/L GN_0 F_E/L F_E/L F_E/L0 F_E0/L F_TSIZE0/L 0 F_TSIZE/L F_TS/L F_TST/L F_T/L F_S/L F_S/L F_S/L F_S/L0 GPIO/L L_/L 0 GN_.V_

15 POWER SUPPLY J0 PJ-00H MMZVL External Power Input R00M_0 L LMSGTN V_V0 POWER POWER SUPPLY V_V0_ELEV R00M_0 + 00UF V_V0 + 00UF V_V R V_V0 PW_V Notes: 0K.prevent the external current lash power Is Protection the PU and R operating voltage. Ensure Powerup Sequence 0 PG P GN GN.V ORE SUPPLY EN/SYN U MP0Q IN IN S 0.uF SW SW F L. uh. R 0.K/% R K/% V_V0 0uF.V 0.uF TP + 0uF/.V TP L LMSGTN NP Q FN0P R 0K V_V0_ELEV R k V_V L LMSGTN POWER SUPPLY V_V R 00K R 00K TL_V L0 LMSGTN NP VV_IO FN0P Q V_V R PW_V 0K PW_V 0.V R- SUPPLY PG U MP0Q P GN GN EN/SYN IN IN S 0.uF SW SW F L. uh. R.K/% V_V 0uF.V TP0 0.uF V_V + 0uF/.V TP L 0 OHM NP Q FN0P VV_MEM PWR_HI R 0K Q 0 R K/% POWER SUPPLY V_V R 0K.V ORE SUPPLY PG U MP0Q IN IN S V_V 0 0uF.V PW_V 0 P GN GN EN/SYN 0.uF SW SW F L. uh. R.K/% 0.uF L V_V TP + LMSGTN 0uF TP R- TERMINTION REG 0 SS R K/% VREF_R V0V PWR_HI V_V V_V V_V U VQ R0 00K S# VREF VIN VSENSE R 0.uF uf.v uf.v VTT_R PWR_HI Voltage Powerup Sequence PVIN VTT.V 0 0.uF uf 0V 0.uF GN E_P GFUF uf.v uf.v 0.uF.V.V Note Route VSENSE line as a trace and connect it to the VTT power plane near the R- memories. Provide Ground Gaurd to the Vsense line Time POWER SUPPLY Size ocument Number Rev v. TWR-MP Wednesday, February, 00 ate: Sheet of

16 TX_RX_EN_ V_V TX_RX_EN_ V_V V_V R0 OSM IRUITS, PS_[:0] PS_ PS_ PS_ PS_0 SPIO_MiS0 SPIO_MOSI SPIO_S SPIO_LK R R R R SPI_SO SPI_SI SPI_SSN SPI_LK T_TX OUT_EN_ U V TX_OSM GN LV U TX_OSM T_RTS OUT_EN_ TRESET_OUT V GN U LV U JTG_TRST# TS JTG_TRST# 0K 0 U LV U PS PS_0 PS_ PS_ PS_ SPI R0 R R0 NP R R R NP R R R0 NP R R R NP MII R0 NP R0 R R NP R R R NP R0 R R NP R R RK_TMS JTG_TMS JTG_TMS LV LV OUT_EN_ LV OUT 0 U JTG_TI JTG_TI F V_V0 LMSGTN SPI_EN OUT_EN_ LV U SPI_SI TP OUT_EN R 0K TX_RX_EN R 0K U U V_V V SLK_OUT TLK_EN SNLV0PWE SNLV0PWE U GN SNLV0PWE R.K OUT_EN_ TX_RX_EN_ U 0 JTG_TK JTG_TK T_TX LV T_RX TLK_EN IN OUT V_V0 SLK_OUT V_V F OUT_EN R0 LMSGTN R X 0.0uF V.K TRI_STTE V _GN 0UF 0UF PTE0/Tx PTE/Rx 0 PTE/TPMH0 PTE/TPMH PTE/MISO PTE/MOSI PTE/SPSK PTE/SS PTF0/TPMH PTF/TPMH PTF/TPMH0 PTF/TPMH PTG0/KIP0 PTG/KIP PTG/KIP PTG/KIP PTG/XTL PTG/EXTL 0 VUS USN USP V VSSOS V/VREFH VSS VSS/VREFL R 0K OSSEL SPI_EN OUT T_TS T_RTS TX_RX_EN MHZ US_- R R US_-_R US_+ R R US_+_R U PT0/MISO/P0 PT/MOSI/P PT/SPSK/P PT/SS/P PT/KIP/P PT/KIP/P PT0/SL 0 PT/S PT PT/Tx PT PT/Rx PT0/P/MP+ PT/P/MP- 0 PT/KIP/MPO IRQ/TPMLK RESET KG/MS MS0JM0L SPI_SO TP SPI_LK TP SPI_SSN TP RK_TMS VTRG_IN TRESET_OUT PT0 PT JM0_IRQ_ JM0_RESET_ JM_KG V_V V_V0 R 0K LE_YELLOW 0 R 0K R.0K V_V0 R 0K R 0K R 0K R NP HT GREEN LE V_V OUT_EN_ R.0K U V IN GN HT HRESET#,,,0,, TX_RX_EN_ JTG_TO JTG_TO U V_V SNLV0PWE UE 0 000PF T_RX U 0 R 0K RX_OSM RX_OSM SNLV0PWE HT UF SNLV0PWE V_V0_USEXT V_V J OSSEL JM0_IRQ_ JM_KG U TX_RX_EN_ U SP00 J US_MINI_ R00M_0 S S V_V0 - VUS + I G S S F LMSGTN HR_X S0JM0 Function Select: - shorted - OSM - open - Serial to US bridge - shorted - S0JM0 bootloader mode - open - normal mode S0JM0 ebugger ccess S0JM0 ebugger ccess: Pins: Pin - GN Pin - V Pin - KG T_TS HT RTS RTS OSM IRUITS Size ocument Number Rev v. TWR-MP Friday, February, 00 ate: Sheet of

17 N S HPOUTR 0uF R_HPOUTR LM00SNJ F OUTR J HPOUTL 0uF R_HPOUTL LM00SNJ F F OUTL PHONE_GN LM00SNJ K-.- J VV_U V_ MIP 00PF F LM00SNJ 00PF F0 LM00SNJ R K MI_GN VFLH ON/OFF MIP R.K 0.uF _MIIS U MIIS MIP MIN V V V HPV TPV SPKV VREF MONO_OUTP MONO_OUTN _VREF _P ONNET MI_L 0 MIP MIN SPK_OUTLN SPK_OUTLP OUTL_P TP LINEINL LINEINR SPK_OUTRP SPK_OUTRN OUTR_P TP 0 PHONE PEEP HPOUTL HPOUTR HPOUTL HPOUTR TP LK ITLK _STIN _STOUT LK SYN RST_RESET _OMP_REF 0 ITLK STIN STOUT SYN RESET X+/R WIPER/UX Y+/TR MLK EXTLK GPIO/PENOWN GPIO//MSK GPIO/SPIF_OUT _XOUT _MSK _SPIFOUT TP mil R TP 0K _XIN Y.MHZ 0pF V 0pF V 0 0.0uF V 0.0uF V 0.0uF V 0.0uF V X-/TL Y-/L EXP_P GN GN GN GN HPGN TPGN SPKGN 0 GPIO/IRQ GPIO WMLGEFL_V _INT _INT 0.uF V_V F R 00K _MON _OMP_REF LMSGTN 0.uF V + 0uF V_V F _VREF _P uf 0.uF 0.0uF 0V V V POWER FILTERING VV_U F 0.uF V 0.0uF V _MIIS 0.uF V V_ U- SH MP SH_LK/NF_E_/FE_TX_/GPIO SH_M/PS_0/FE_TX_/GPIO SH_0/PS_/FE_RX_/GPIO SH IRQ/PS_/FE_RX_/LP_S_ SH_/PS_/FE_RS/LP_S_ SH /PS_/FE_TX_ER/LP_S_ T T T T R R SH_LK SH_M/SPI_LK SH_0/SPI_S# SH IRQ/SPI_MOSI SH_/MISO SH, S_R_ET SH_LK, S_WP_ET SH_M/SPI_LK SH_0/SPI_S# SH IRQ/SPI_MOSI SH_/MISO SH S_WP_ET S_R_ET SH IRQ/SPI_MOSI SH_0/SPI_S# SH_LK SH_M/SPI_LK SH R R R R R 0K 0K 0K 0K 0K S R SOKET ON 0 WP n P T T0 P VSS LK P V VSS P M /T LMSGTN + uf GN 0pF 0.0uF LMSGTN 0 0uF 0.uF <Volts> 0.uF V 0.0uF V 0.uF V 0.0uF V Layout Note: onnect the GN and GN underneath OE (U) with multiple Vias. SH_/MISO T S/MM R OSM IRUITS Size ocument Number Rev v. TWR-MP Wednesday, February, 00 ate: Sheet of