TWR-VF65GS10 VYBRID TOWER SYSTEM MODULE

Transcription

1 Table of ontents REVISION ISTORY NOTES & REV MOIFITIONS LOK IGRM VYRI MIS PIN POWER ISTRIUTION SERIL INTERFE PERIPERLS ELEVTOR ONNETORS TWRPI & POT & & SS R & NN FLS US Revisions Rev escription ate pproved X Initial ec nthony. Release Mar Release May Release June E Release ug F Release Oct G Release ec G Release July G Update July G Release July G Update Nov Release nthony. nthony. nthony. nthony. nthony. nthony. Naoum G. Naoum G. Naoum G. Naoum G. G Update Nov Jiri K. G Update Nov Jiri K. G Update ec Guillermo Ron Jan Guillermo Ron TWR-VFGS VYRI TOWER SYSTEM MOULE esigner:,, & rawn by: Jun Q. Microcontroller Product Group William annon rive West ustin, TX - This document contains information proprietary to Freescale and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of Freescale. IP lassification: FP: _ PUI: _ rawing Title: TWR-VFGS Table of ontents & Revisions pproved: Size ocument Number Rev Naoum G. & Jiri K. S- PF: SPF- ate: Thursday, January, Sheet of

2 Global Power & Ground Nets Main Revision Modifications: NET VOLTGE ESRIPTION Pxx_ELEV xx Input/output power from/to Elevators. PV_US V Input power. Filtered from US connector. Input to US power switch.. mil headers replaced with smaller mm ones.. V and.v power partition changed. PV_SW V Output of US power switch, enabled by input of US power supply.. Quad SPI and US data switches deleted (bypassed). PV V Source from either PV_ELEV, or US_VUS, or US_VUS, or external source.. Vybrid ballast transistor powered from.v, not.v. PV.V Output of high-power Switch-Mode regulator...v generated by Swith-Mode, not Linear regulator. V_V_K.V Output of low-power Linear regulator, power supply for K (Kinetis).. Optional "Virtual VFxx" configuration created. V_V_MU.V MU digital power. omes from PV.. Optional VSE[:] and LVS connections provided. V_V.V R.V pre-drive supply.. Vybrid US ports made compliant with US spec. V_V.V R.V main IO supply.. Vybrid Power-On-Reset active timeout made longer to guarantee proper S card initialization. V_V.V MU core power. Output of regulator based on on-chip controller and external ballast transistor. V Main Ground. Initial current comsumption of OpenS US port lowered to make compliant with US spec (by splitting _ net).. Removing U and powering K (Kinetis) by its internal regualtor output.v (which is regulated from elevator PV or US switch PV_SW).. Optional Ethernet MII interface added (NP-ed -Ohm resistors).. R: external termination deleted, Vref circuit simplified.. Series -Ohm resistors added into I, I, and I lines to Elevator for flexibility.. Filtering (series ferrite beads) added into x_fe and x_ power rails for better performance.. New button SW added to test low power use cases.. Unless Otherwise Specified: ll resistors are in ohms ll capacitors are in uf ll voltages are ll polarized capacitors are aluminum electrolytic.. Interrupted lines coded with the same letter or letter combinations are electrically connected.. evice type number is for reference only. The number varies with the manufacturer.. Special signal usage: _ enotes - ctive-low Signal <> or [] enotes - Vectored Signals. Interpret diagram in accordance with merican National Standards Institute specifications, current revision, with the exception of logic block symbology.. Specific P LYOUT notes are detailed in ITLIS.. Special component funtion notes are detailed in Narrow rial.. Jumper setting notes are detailed in ourier New.. Version modifications are detailed in rial. IP lassification: FP: PUI: rawing Title: TWR-VFGS -Notes & Rev Modifications Size ocument Number Rev S- PF: SPF- ate: Thursday, January, Sheet of

3 lock iagram IP lassification: FP: PUI: rawing Title: TWR-VFGS lock iagram Size ocument Number Rev S- PF: SPF- ate: Thursday, January, Sheet of

4 ,,, PT[..],,, PT[..] TP KO* PT TP KO* PT,,,, PT[..] PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT RMII_LKIN S_ JTLK JTI JTO JTMS TREK TRE[] TRE[] TRE[] TRE[] TRE[]* SI_RX_LK/TRE[]* SI_RX_T/TRE[]* SI_RX_SYN/TRE[]* S_LK/TRE[]* S_M/TRE[]* S_T/TRE[]* S_T/TRE[]* S_T/TRE[]*/ENET TMR* S_T/TRE[]*/ENET TMR* TRE[]*/ENET TMR* TRE[]*/ENET TMR* FTM FTM/RON** FTM/RON** FTM SI_TX SI_RX SI_TX/FTM SI_RX/FTM FTM FTM ENET_TS_LKIN/KO* KO* TRETL I_SL I_S N_RX*/I_SL* N_TX*/I_S* SPI_PS/EXT_UIO_MLK SPI_PS SPI_SIN SPI_SOUT SPI_SK SI_TX_LK/RON** NF_WE_b/RON** NF_E_b/RON** SI_TX_T/RON** NF_RE_b/RON** SI_TX_SYN/RON** RMII_M RMII_MIO RMII_RS_V RMII_RX[] RMII_RX[] RMII_RXER RMII_TX[] RMII_TX[] RMII_TXEN RMII_M/ESI_SKT RMII_MIO/ESI_FST RMII_RS_V/ESI_SO RMII_RX[]/ESI_SO RMII_RX[] RMII_RXER RMII_TX[]/ESI_SI RMII_TX[]/ESI_SI RMII_TXEN NF_R_b/RON** NF_LE/RON** NF_LE/RON** RON** SE/RON** SE/RON** EXTL_MIN XTL_MIN EXTL_RT XTL_RT N V K K K L L Y Y V U E R R R R P P P P T T V W Y Y W J J E E U L L M M L M N N N T U P P P R P R R E E T W Y W Y W U PT/RMII_LKOUT/RMII_LKIN PT PT/JTLK/SWLK PT/JTI/RMII_LKOUT/RMII_LKIN/WOG PT/JTO/EXT_UIO_MLK/ENET_TS_LKIN PT/JTMS/SWIO PT/TREK/EXT_UIO_MLK PT/TRE/US_VUS_EN/SE/SI_TX_LK PT/TRE/US_VUS_O/SE/US_SOF_PULSE PT/TRE/SE/FTM_Q_P/SI_TX_T PT/TRE/SE/FTM_Q_P/SI_TX_SYN PT/TRE/SI_TX PT/TRE/SI_RX_LK/SI_RX PT/TRE/SI_RX_T PT/TRE/SI_RX_SYN PT/TRE/US_VUS_EN/S_LK/WOG PT/TRE/US_VUS_O/S_M PT/TRE/SI_TX_LK/S_T PT/TRE/SI_RX_LK/S_T PT/TRE/SI_RX_T/ENET TMR/SI_TX/S_T PT/TRE/SI_TX_T/ENET TMR/SI_RX/S_T PT/TRE/SI_RX_SYN/ENET TMR/SI_RTS/SI_TX PT/TRE/SI_TX_SYN/ENET TMR/SI_TS/SI_RX PT/FTM/SE/TRETL/SI_RX_LK PT/FTM/SE/RON/SI_RX_T PT/FTM/SE/RON/SI_RX_SYN PT/FTM/SE/EXTRIG PT/FTM/SI_TX/SE PT/FTM/SI_RX/SE PT/FTM/SI_RTS/SI_TX PT/FTM/SI_TS/SI_RX PT/FTM/FTM_Q_P PT/FTM/FTM_Q_P PT/SI_TX/KO /ENET_TS_LKIN PT/SI_RX/KO PT/SI_RTS/SPI_PS PT/SI_TS/SPI_PS/TRETL PT/N_RX/I_SL PT/N_TX/I_S PT/N_RX/I_SL PT/N_TX/I_S PT/SPI_PS/EXT_UIO_MLK PT/SPI_PS PT/SPI_SIN PT/SPI_SOUT PT/SPI_SK PT/SI_TX_LK/SI_TX/RON PT/SI_RX_LK/SI_RX/RON/NF_WE PT/SI_RX_T/SI_RTS/RON/NF_E PT/SI_TX_T/SI_TS/RON/NF_E PT/SI_RX_SYN/RON/NF_RE PT/SI_TX_SYN/RON PT/RMII_M/FTM/SPI_PS/ESI_SKT/RON PT/RMII_MIO/FTM/SPI_PS/ESI_FST/RON PT/RMII_RS_V/SI_TX/ESI_SO/RON PT/RMII_RX/SI_RX/ESI_SO PT/RMII_RX/SI_RTS/SPI_PS/ESI_SO PT/RMII_RXER/SI_TS/SPI_PS/ESI_SO PT/RMII_TX/SPI_SIN/ESI_SI PT/RMII_TX/SPI_SOUT/ESI_SI PT/RMII_TXEN/SPI_SK PT/RMII_M/ESI_SKT PT/RMII_MIO/ESI_FST PT/RMII_RS_V/ESI_SO PT/RMII_RX/ESI_SO/SI_TX_LK PT/RMII_RX/ESI_SO/SI_RX_LK PT/RMII_RXER/ESI_SO/SI_TX/SI_RX_T/SE PT/RMII_TX/ESI_SI/SI_RX/SI_TX_T/SE PT/RMII_TX/ESI_SI/SI_RTS/SI_RX_SYN/SE PT/RMII_TXEN/SI_TS/SI_TX_SYN/US_SOF_PULSE/SE PT/SI_TX_LK/SPI_PS/RON/NF_R PT/SI_RX_LK/SPI_PS/RON/NF_LE PT/SI_RX_T/SPI_PS/RON/NF_LE PT/SI_TX_T/SPI_PS/RON PT/SI_RX_SYN/SPI_PS/RON/SE PT/SI_TX_SYN/RON/SE EXTL XTL EXTL XTL PT/QSPI SK/SI_TX/SPIF_EXTLK PT/QSPI S/SI_RX/SPIF_IN PT/QSPI T/SI_RTS/SPI_PS/SPIF_OUT PT/QSPI T/SI_TS/SPI_PS/SPIF_PLOK PT/QSPI T/SPI_PS/SPIF_SRLK PT/QSPI T/SPI_PS PT/QSPI QS/SPI_SIN PT/QSPI SK/SPI_SOUT PT/QSPI S/SPI_SK PT/QSPI T/SPI_PS/SI_TX_SYN PT/QSPI T/SPI_PS PT/QSPI T/SPI_SIN PT/QSPI T/SPI_SOUT PT/QSPI QS/SPI_SK PT/NF_IO/ESI_KT PT/NF_IO/ESI_KR PT/NF_IO/ESI_FSR/FTM_Q_P PT/NF_IO/ESI_SKR/FTM_Q_P PT/NF_IO/ENET TMR/S_T/SI_TS PT/NF_IO/ENET TMR/S_T/SI_RTS PT/NF_IO/FTM/ENET TMR/S_T/SI_RX PT/NF_IO/FTM/ENET TMR/S_T/SI_TX PT/NF_IO/FTM PT/NF_IO/FTM PT/NF_IO/FTM/S_WP PT/NF_IO/FTM/SPI_SK PT/NF_IO/FTM/SPI_SOUT PT/NF_IO/FTM/SPI_SIN PT/NF_IO/FTM/SPI_PS PT/NF_IO/FTM/SPI_PS PTE/U_SYN/U_TON/OOTMO PTE/U_VSYN/U_TON/OOTMO PTE/U_PLK PTE/U_TG/U_TON/SE PTE/U_E/U_TON PTE/U_R PTE/U_R PTE/U_R/RON PTE/U_R/RON PTE/U_R/RON PTE/U_R/RON PTE/U_R/RON PTE/U_R/SPI_PS/RON/LPT_LT PTE/U_G PTE/U_G PTE/U_G/RON PTE/U_G/RON PTE/U_G/RON PTE/U_G/RON PTE/U_G/RON PTE/U_G/RON/EWM_in PTE/U_ PTE/U_ PTE/U_/RON PTE/U_/RON PTE/U_/RON PTE/U_/RON PTE/U_/RON PTE/U_/RON/EWM_out US_VUS_ETET US_M US_P US_ US_VUS_ETET US_M US_P US_ SE SE SE SE VSE VSE VSE VSE Y Y V Y W W V V U U U T T T E E F F F F G G G G J N N N Y N T W M M M M L L Y W L L K K K V W J K Y T T V U V W Y Y W W Y Y U W V QSPI SK QSPI S_ QSPI T[] QSPI T[] QSPI T[] QSPI T[] QSPIO QS QSPI SK QSPI S_ QSPI T[] QSPI T[] QSPI T[] QSPI T[] QSPIO QS NF_IO[] NF_IO[] NF_IO[] NF_IO[] NF_IO[]/ENET TMR* NF_IO[]/ENET TMR* NF_IO[]/ENET TMR* NF_IO[]/ENET TMR* NF_IO[] NF_IO[] NF_IO[] NF_IO[] NF_IO[] NF_IO[] NF_IO[] NF_IO[] U_SYN/U_TON/OOTMO[]** U_VSYN/U_TON/OOTMO[]** U_PLK U_TG/U_TON U_E/U_TON U_R U_R U_R U_R U_R U_R U_R U_R U_G U_G U_G U_G U_G U_G U_G U_G U_ U_ U_ U_ U_ U_ U_ U_ VSE VSE VSE VSE SE SE SE SE R.K R.K R.K R.K PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PTE PTE PTE PTE PTE PTE PTE PTE PTE PTE PTE PTE PTE PTE PTE PTE PTE PTE PTE PTE PTE PTE PTE PTE PTE PTE PTE PTE PTE US_VUS,,, US_N US_P US_VUS, US_N US_P SE, SE, SE, SE, PT[..],,, PTE[..], J X MTMM---G-S- efault: - (loopback) TP TP R R.K R.K R.K R.K R.K R.K TMPER TMPER TMPER TMPER TMPER TMPER T U T U U U T EXT_TMPER EXT_TMPER EXT_TMPER/EXT_WM_TMPER_IN EXT_TMPER/EXT_WM_TMPER_OUT EXT_TMPER/EXT_WM_TMPER_IN EXT_TMPER/EXT_WM_TMPER_OUT Ext_POR O O LVSP LVSN U U W Y TPV TPV PF V _ O O PF V _ O O Place capacitors as close to MU as possible.,,, _ T /_OUT TEST T MVFNSMK (PVFNSMK) EXTL_RT PF V Y.Kz XTL_RT PF V Place.Kz clock curcuit adjacent to MU. XTL_MIN R.M R_ Y MZ PF V _ EXTL_MIN PF V _ Place MZ clock curcuit adjacent to MU. dded: - R...R, - TP, and TP, - TPVs. eleted: R, R. hanged: -,,,, and R footprint changed from to. - and changed from pf to pf. (for OM consolidation). - capacitors (close to MU) footprint from _ to _. IP lassification: FP: PUI: rawing Title: TWR-VFGS Vybrid Misc Pin Size ocument Number Rev S- PF: SPF- ate: Thursday, January, Sheet of

5 PV UF _ V_V TRL pin protection: prevents applying.v to Vybrid prior to.v to Q collector. R PV.K UF _ R.K.uF V.uF V // oin ell PV IEN_V IEN_V R R J X MTMM---G-S- T K- PV PV + efault: - (use PV).uF V.uF V - VOIN PV.V REGULTOR U ITM PV V EN max..v REGULTOR U ITM PV V EN P EP P EP max. efault: - (use PV_MU) PG LX F T--F R.K PG LX F VT PG_V UF _ UF _ L.u U_V_F L.u U_V_F V_V iode prevents Vybrid's reset when J opens. UF _ J X MTMM---G-S- UF _ UF _ NP R.uF V _ V_V_MU Place.uF close to each V pin, better to place one by one at the opposite P side under the G. V_V_MU V V Vybrid_VT IEN_V R.K % R.K % R.K % R.K % V_V TP POWER ON For application without.v rail, i.e. without R. e.g. VFxx: install diodes and move -Ohm resisitor from posistion to. R default: position. Place close to each SRM pin, better on opposite P side under the G. Place close to each V pin, better to place one by one at the opposite P side under the G. S V_V S_ S S_ S S_ R V_V_MU N NP N NP _V_ON YEL/GRN PV.uF V _ V_V R V_V V_V_MU TRL pin protection: prevents applying.v to Vybrid prior to providing.v for Q. NP MRLTG.uF V Q IRLML.uF V _ R.K Q PSSNT est performance when x_fe rails powered from dedicated linear voltage regulators. F OM efault: - (PV_ELEV) V_V_SRM UF _ TRL F OM J X MTMM---G-S- V_V_SRM V_V_SRM PV_ELEV.uF V _ V_V V_V_MU UF _ V_V_MU V_V_FE FVG ELE_PS_SENSE, E F K E E J E E T G J L K M P G N P G N P G J L N K M P N V K N V U K N T F W T V P.uF _ V T T R V_V_FEV V U F_V U SRM_VP_ SRM_VP_ SRM_VP_ SRM_VP_ SRM_VP_ SRM_VP_ SRM_VP_ SRM_VP_ SRM_VP_ SRM_VP_ SRM_VP_ EP_V_LO_OUT V V V V V V V V V V V V V V V V V V V V V V V EP_V_LO_OUT V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_LOIN VT VREG TRL V_FE VSS_FE V_FE VSS_FE V_FE_NGP MVFNSMK (PVFNSMK) Peripheral US PortVybrid_VUS_PERIPERL ost US Port dded: - series ferrite beads on x_fe and x_ rails (F, F, F, F). -.V / (U, R, R,,, R, L, R, R, S). - others (,,, J,, R,, Q, R). eleted: R termination U, R,..., U. NP-ed:,,,,, and. VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS_KEL US_VUS US_VUS US_P V_ VREF_ VREFL_ VSS_ V_V_MULO V_V_ VREF_V Vybrid_VUS_OST hanged: - J from x to x, - from uf to.uf (as per atasheet), - R from.k to.k, - R from K to.k, - Q from NJT to PSSNT, - ll uf are - ll mil headers to mm ones, - J from x to x, - capacitors (close to MU) footprint from _ to _, and change to be - capacitors (close to MU) footprint from _OV to _. and change to be.uf V E E E E E F G J J M M M R R U U V W V Y Y L P K M P G J L N J K L M P G J K L M N J K L M P G J K L M N K M P G J L N U W W Y V W V U UF _ efault: - -: Peripheral, Self-powered -: Peripheral, us-powered PV F OM F OM UF _ J X MTMM---G-S- NP UF _ V_V_MU efault: - est performance when x_ rails powered from dedicated linear voltage regulators. Most critical for VREF_; without power filtering, actual resolution might be degraded. From US Peripheral onnector US_VUS,,, From US ost onnector US_VUS, IP lassification: FP: PUI: rawing Title:.uF V _ J X MTMM---G-S- TWR-VFGS Power istribution Size ocument Number Rev S- PF: SPF- ate: Thursday, January, Sheet of

6 PV PV_SW V_V_K T--F uf V.uF V Serial interface reset when US port disconnected. UF _ PV_SW R.K R.K V_V_K RST_SI_ R NP TPV R K_VT K_US_N K_US_P R uf V U V V VSS VT VREGIN VOUT US_M US_P EXTL XTL VSS Serial Interface V_V_K J FTS---L-V JTG_TLK/SW_LK/EZP_LK/TSI_/PT/URT_TS/URT_OL/FTM_ JTG_TI/EZP_I/TSI_/PT/URT_RX/FTM_ JTG_TO/TRE_SWO/EZP_O/TSI_/PT/URT_TX/FTM_ JTG_TMS/SW_IO/TSI_/PT/URT_RTS/FTM_ NMI/EZP_S/TSI_/PT/FTM_/LLWU_P EXTL/PT/FTM_FLT/FTM_LKIN XTL/PT/FTM_FLT/FTM_LKIN/LPTMR_LT _SE/TSI_/PT/I_SL/FTM_/FTM_Q_P/LLWU_P _SE/TSI_/PT/I_S/FTM_/FTM_Q_P _SE/TSI_/PT/SPI_PS/URT_RTS/FTM_/IS_TX/LLWU_P _SE/MP_IN/TSI_/PT/SPI_PS/URT_TS/FTM_/IS_TX_FS MP_IN/PT/SPI_PS/URT_RX/FTM_/IS_TX_LK/LLWU_P PT/SPI_PS/URT_TX/FTM_/MP_OUT/LLWU_P PT/SPI_SK/LPTMR_LT/IS_RX/MP_OUT/LLWU_P MP_IN/PT/SPI_SOUT/P_EXTRG/IS_RX_LK/IS_MLK/LLWU_P MP_IN/PT/SPI_SIN/US_SOF_OUT/IS_RX_FS JTG_TMS_SI JTG_TLK_SI JTG_TO_SI JTG_TI_SI RST_SI_ JTG_TLK_SI JTG_TI_SI JTG_TO_SI JTG_TMS_SI SW_EN_SI_ R.M SW_SEL K_ R.K NP SI_SPI_S K_URT_RX K_URT_TX SI_SPI_SK SI_SPI_SOUT SI_SPI_SIN PV Mz_EXTL X.MZ Mz_XTL V_V_K R.K V_V_K R.K NP MNUL U SW P switch Q NTSNTG sc_ S S V_V_K R.K U MTG PV R NP S_ S_ SWLK SWIO.uF V PV PV R R Reset U MPT-I/TT V VSS RST {.V to.v Threshold} { to ms delay} {RST - Open rain with uilt-in K pull-up}.uf V NP R.K PT PT PV V_V_K R.K NP V R.K RSTR U MTG PT[..],,, ORNGE OpenS_URT_RX OpenS_URT_TX _,,, MTG EP V_V_K YEL U MTG PT/SPI_PS/URT_RTS/FTM_/EWM_IN/LLWU_P _SE/PT/SPI_PS/URT_TS/URT_OL/FTM_/EWM_OUT _SE/PT/SPI_PS/URT_RX/FTM_/FTM_FLT/LLWU_P PT/MT_IRO/URT_TX/FTM_/FTM_FLT R.K PV_US PKXVFM R.K R.K R US-SL SELL SELL SELL SELL OpenS ebug Interface Peripheral (OTG, Micro-) pf V VUS - + I J US_VUS US_N US_P U M P US I VUS RLMPP.TT F OM IN_ PV_US uf V TP NP, ELE_PS_SENSE R.K R.K Q NTSNTG sc_ From US Peripheral onnector,,, US_VUS.uF V U IN OUT TL OUT TL MIYM FLG FLG efault: - (OpenS) PV_SW J X MTMM---G-S- TZ SMJ. +V TP NP.uF V PV efault: - (PV_ELEV) J X MTMM---G-S- PV_ELEV dded:, Q, U,, TZ, R, TP, J, J, U (to improve S boot). eleted: U, U,,, U,. NP-ed: - R, - R (and changed from K to.k). - R, R, hanged: - R and R from to.k (to optimize brightness), - Ferrite beads from / to /, - Q from MMT to NTSNTG, - R from K to.k. IP lassification: FP: PUI: rawing Title: TWR-VFGS Serial Interface Size ocument Number Rev S- PF: SPF- ate: Thursday, January, Sheet of

7 JTG+TRE pin MITOR ETMv MIRO S INTERFE Place -pin connector in corner on top side, oriented so that ribbon cable comes out of tower board. PV.uF V PV,,,,,,, V_V_MU J VTREF V-Supply J X MTMM---G-S- efault: NP R_P PT[..] _ JTMS/SWIO JTLK/SWLK JTO/SWO JTI TREK TRE[] TRE[] TRE[] TRE[] PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT V_V_MU R.K R.K JTO RTK JTLK JTMS JTI njtrst TRE[] TRE[] TRE[] TRE[] TRE[] TRE[] TRE[] TRE[] J - TREK VTREF VSUPPLY TRE[] TRE[] TRE[] TRE[] TRE[] TRE[] TRE[] TRETL TRE[] V_V_MU PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT R.K R R R R R R R UF _ S_T S_T S_M S_LK S_T S_T S_SW PT.uF V S S_ J T /T M V LK VSS T T onn MicroS _SW _OMMON PT[..],,, VSS VSS VSS VSS PV R.K PT SW P switch PUS UTTONS,,,, _ PV R.K R.K R.K R.K R.K R.K R.K R.K R.K R.K R.K R.K R.K R.K R.K R.K RON RON RON RON RON RON RON RON RON RON RON OOTMO OOTMO RON RON RON G G U PV U O O O O LX O O O O PV V.uF V.uF V J R_X PV OOT ONFIG oot Options: default S ard (ON-, OFF-) Jumper: & & & & & QSPI: _ S ard: _ NN: _ URT/US: _ x x x Fuses: _ x x x U PV O O O O LX O O O O G G V.uF V, PTE[..] RON RON RON RON RON RON RON RON RON RON RON OOTMO[] OOTMO[] RON RON RON PTE PTE PTE PTE PTE PTE PTE PTE PT PT PT PTE PTE PTE PTE PTE PT PT PT PT PT PT PV PT[..],,, R LUE R.K SW P switch R.K SW P switch PT[..],,,, x LEs YEL R.K R YEL/GRN PV OR/RE R.K R.K R.K R.K R.K R.K R.K R.K R.K RON RON RON RON RON RON RON RON O O O O LX O O O O G G V RON RON RON RON RON RON RON RON PTE PTE PTE PTE PTE PTE PT PT dded: - RON and RON (PT and PT are removed), - SW, R - R and R (pull-up for SW and SW respectively) eleted: R. hanged: - R and R from K to.k to optimize brightness, - R from to.k to optimize brightness, - J from larger x with mm pitch to smaller x with mm pitch (US_SEL function deleted). IP lassification: FP: PUI: rawing Title: TWR-VFGS Peripherals Size ocument Number Rev S- PF: SPF- ate: Thursday, January, Sheet of

8 Optional MII interface: PT PT PT PT PT PT PT R R R R R R R NP NP NP NP NP NP NP MII_TXERR MII_TX MII_TX MII_OL MII_RS MII_RX MII_RX PT? MII_TXLK to J? (also used as RMII_LKIN) PT?MII_RXLK to J? (also used as I_RX_LK) PT?MII_TXERR to J? PT?MII_TX to J? PT?MII_TX to J? PT?MII_OL to J? PT?MII_RS to J? PT?MII_RX to J? PT?MII_RX to J? PTx signals also used by NN => no simultaneous use of NN and MII.,,, PT[..],,,, PT[..] PV_ELEV,,, PT[..] PV_ELEV Use (R) to switch between RMII LK and MII TXLK. R default: Position,,, PT[..] R MII_TXLK RMII_LKIN PT To use N, populate R and R. SW and SW push buttons (Sheet ) cannot be used in this case. PV_ELEV PV_ELEV J V_ V _.V_.V_,, ELE_PS_SENSE ELE_PS_SENSE_.V_,, ELE_PS_SENSE I_SL R PT PT R SPI_SK_ S_LK/SPI_LK I_SL I_S R PT S_/SPI_S I_S EGPIO R PT PT SPI_PS_ S_/SPI_S GPIO/URT_TS R EGPIO R PT PT R SPI_SOUT_ S_M/SPI_MOSI GPIO/S_ EGPIO R PT PT R SPI_SIN_ S_/SPI_MISO GPIO/S_WP_ET PT MII_OL MII_RS PT RMII_RXER ET_OL_ ET_RS RMII_M PT PT RMII_RXER MII_TXLK ET_RXER_ ET_M_ RMII_MIO PT PT RMII_TXEN ET_TXLK_ ET_MIO_ MII_RXLK PT RMII_TXEN MII_TXERR ET_TXEN_ ET_RXLK_ RMII_RS_V PT MII_TX ET_TXER ET_RXV_ MII_RX MII_TX ET_TX ET_RX MII_RX PT RMII_TX[] ET_TX ET_RX RMII_RX[] PT PT RMII_TX[] PT RMII_TX[] ET_TX_ ET_RX_ RMII_RX[] PT PT RMII_TX[] PT R EGPIO ET_TX_ ET_RX_ EXT_UIO_MLK PT EGPIO GPIO/URT_RTS IS_MLK R SI_TX_LK R PT R PT EGPIO GPIO/S_ IS_OUT_SK R SI_TX_SYN R PT LK_IN GPIO IS_OUT_WS SI_RX_T R LKIN IS_IN SI_TX_T R PT LKOUT IS_OUT R PTE U_SYN SE, N N PTE U_VSYN SE, PT R SE N N SE, PT R SE N N SE, N N O O PTE U_PLK PT R ENET TMR ENET TMRR PT PT R ENET TMR TMR TMR ENET TMRR PT TMR TMR EGPIO R PT PT R GPIO GPIO PT R NP FTM.V_.V_ FTM PT PT R NP FTM PWM PWM FTM PT PT R FTM PWM PWM FTM PT PT R FTM PWM PWM FTM PT PT R NP N_RX PWM PWM R NP SI_RX PT PT N_TX N_RX URT_RX R NP R NP SI_TX PT N_TX URT_TX L_ENLE PT SPI_SIN_ WIRE URT_RX ELEV_URT_RX R PTE U_E PT SPI_SOUT_ SPI_MISO/IO URT_TX ELEV_URT_TX R PTE U_ PT R SPI_PS_ SPI_MOSI/IO VSS PTE U_ SPI_S V N_RX R NP PT PTE U_ PT SPI_SK_ SPI_S N_RX R N_TX R NP PT PTE U_ SPI_LK N_TX F NP PT R I_SL PT R I_S I_SL GPIO OM PV_ELEV PT R EGPIO I_S GPIO F NP PTE U_G GPIO/SPI_OL/IO GPIO/SPI_WP/IO PTE U_G RSRV_ GPIO OM PTE U_G ELEV_US_N PT EIRQ RSRV_ US_M R PT EIRQ IRQ_ ELEV_US_P US_P R PT PT EIRQ IRQ_G US_I R PT PT R EIRQ IRQ_F SI_RX_LK US_VUS,,, US_VUS PT R EIRQ IRQ_E IS_IN_SK SI_RX_SYN PT PT R EIRQ IRQ_ IS_IN_WS R PT PT R EIRQ IRQ_ IS_IN PT R EIRQ IRQ_ IS_OUT IRQ,,, RSTIN PTE PTE U_R EI_LE/EI_S RSTOUT PTE U_R EI_S LKOUT EI_ EI_ R EI_ EI_ EI_ EI_ EI_ EI_ R PT EI_ EI_ EI_R/W EI_ EI_OE EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ MII_RXLK EI_ EI_ PTE U_R EI_ EI_ Use (R) to switch between PTE U_R EI_ EI_ PTE U_R EI_ SI RX LK and MII RXLK. EI _ R default: Position.V_.V_ PV_ELEV J V_ V _.V_.V_ ELE_PS_SENSE_.V _ SPI_LK I_SL SPI_S I_S SPI_S GPIO SPI_MOSI ULPI_STOP SPI_MISO ULPI_LK ET_OL_ GPIO ET_RXER_ ET_M_ ET_TXLK_ ET_MIO_ ET_TXEN_ ET_RXLK_ GPIO ET_RXV_ GPIO/S_ GPIO/S_ GPIO/S_ GPIO/S_ ET_TX_ ET_RX_ ET_TX_ ET_RX_ ULPI_NEXT/US_S_M ULPI_T/IS_MLK ULPI_IR/US_S_P ULPI_T/IS_OUT_SK UPLI_T/US_S_VUS ULPI_T/IS_OUT_WS ULPI_T/US_S_I ULPI_T/IS_IN ULPI_T ULPI_T/IS_OUT L_SYN/L_P N L_VSYN/L_P N N N N N L_LK/L_P GPIO/URT_ TMR TMR TMR TMR GPIO GPIO/URT_.V_.V_ PWM PWM PWM PWM PWM PWM PWM PWM N_RX URT_RX/TSI N_TX URT_TX/TSI L_ONTRST URT_RTS/TSI L_OE/L_P URT_TS/TSI L_/L_P URT_RX/TSI L_/L_P URT_TX/TSI L_/L_P URT_RTS/N_RX L_/L_P URT_TS/N_TX GPIO L_/L_P GPIO L_/L_P L_/L_P L_/L_P L_/L_P L_/L_P L_/L_P L_/L_P IRQ_P/SPI_S L_/L_P IRQ_O/SPI_S L_/L_P IRQ_N L_/L_P IRQ_M IS_IN_SK IRQ_L IS_IN_WS IRQ_K IS_IN IRQ_J IS_OUT IRQ_I L_/L_P L_/L_P/S_RX_+ L_/L_P/S_ L_/L_P/S_RX_- L_/L_P/S _ EI_/L_P/S_ EI_E /L_P/S_TX_+ EI_/L_P/S_ EI_E /L_P/S_TX_- EI_/L_P/S_RX_+ EI_E /L_P/S_ EI_/L_P/S_RX_- EI_E /L_P/S_ EI_/L_P/S_ EI_TSIZE/L_P/S_TX_+ EI_/L_P/S_ EI_TSIZE/L_P/S_TX_- EI_/L_P/S_RX_+ EI_TS/L_P/S_ EI_/L_P/S_RX_- EI_TST/L_P/S_ EI_/L_P/S_ EI_T/L_P/S_TX_+ EI_/L_P/S_ EI_S/L_P/S_TX_- EI_/L_P/S_RX_+ EI_S/L_P/S_ EI_/L_P/S_RX_- EI_S/L_P/S_ L_/L_P/S_ EI_S/L_P/S_TX_+ L_/L_P/S_REFLK+ GPIO/L_P/S_TX_- L_/L_P/S_REFLK- L_/L_P/S _.V_.V_ PV_ELEV I_SL I_S RMII_M RMII_MIO RMII_RS_V RMII_RX[] RMII_RX[] U_ U_ U_ U_ U_G U_G U_G U_G U_G U_R U_R U_R R R PTE PTE PTE PTE PTE PTE PTE PTE PTE PTE PTE PTE PT PT PT PT PT PT PT PTE[..], PI EXPRESS TOWER SYSTEM PRIMRY PI EXPRESS TOWER SYSTEM SEONRY dded: - Series -Ohm resistors into I, I, and I lines to Elevator for flexibility. - NP-ed series -Ohm resistors for optional MII interface (R-R). - R -pad, R, R, R, R, R. hanged: - R made -pad, - R, R, R, R, R, and R from R to R (to improve signal integrity on PT and PT lines bearing TRE signals). IP lassification: FP: PUI: rawing Title: TWR-VFGS Elevator onnector Size ocument Number Rev S- PF: SPF- ate: Thursday, January, Sheet of

9 , SE, SE,,,, PT[..] PV_ELEV PV PV PV PT SE, SE R.K PV.uF V TWRPI- TWRPI-I J ON_X F OM TWRPI- TWRPI- TWRPI-I PV R.K PT PT PT PT PT PT R.K I_SL SPI_SIN SPI_S TWRPI_GPIO/IRQ TWRPI_GPIO TWRPI_GPIO J I_S R.K SPI_SOUT SPI_SK TWRPI_GPIO TWRPI_GPIO PT PT PT PT,,, _ R ON_X R NP R PT, SE GENERL PURPOSE TWRPI,,, PT[..] PT POTENTIOMETER SE.uF V PV R K efault: J (- & -) and (- & -) Vybrid SI to OpenS (K) Vybrid SI to Elev URT (TWR-SER) lternative : J (- & -) and (- & -) Vybrid SI to Elev URT (TWR-SER) Vybrid SI to OpenS (K) lternative : J (-) and (-) Vybrid SI to Elev URT (populate R and R) Vybrid SI to Elev URT (TWR-SER) PT PT SI_TX OpenS_URT_RX SI_RX OpenS_URT_TX efault: - & - J R_X efault: - & - ELEV_URT_TX ELEV_URT_RX SI_TX SI_RX PT PT SERIL PORTS SELETION,,, PT[..] _VIO S S_ PV PV UF _.uf V.uF V R.K NP R.K PT PT.uF V _S _YP I_SL I_S U SL S S YP MMQ VIO V INT INT N N N N N MINT efault: - (use INT) J X MTMM---G-S- ELEROMETER PT dded: F, R, R (NP-ed), R. hanged: J (x) + J (x) replaced with J (x mm pitch) (OM consolidation) IP lassification: FP: PUI: rawing Title: TWR-VFGS TWRPI & POT & & SS Size ocument Number Rev S- PF: SPF- ate: Thursday, January, Sheet of

10 R MEMORIES N TERMINTIONS V_V S S_.uF V R % R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ N_R_ N_R_ N_R_ R_ R_ R_ R_S_b R_RS_b VREF_R R_WE_b R_ZQ_M R_KE R_LK R_LK_b R_S_b R_ G U R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_S R_RS R_VREF R_WE R_ZQ R_KE R_LK R_LK R_S R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_QM R_QM R_QS R_QS R_QS R_QS R_OT R_OT F G F J G J E G J G E E F R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_QM R_QM R_QS R_QS R_QS_b R_QS_b R_OT R_OT TPV Place R close to R chip. R R %.uf V R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_S_b R_RS_b R_S_b R_WE_b R_LK R_LK_b R_KE R_ R_ZQ_S R_OT VREF_R R_QM R_QM N P P N P P R R T R L R N M N M L J K L J K K T L K M E U /P / S RS S WE K K KE ZQ OT VREF VREFQ ML MU G K K N N R R V V V V V V V V V E F VQ VQ VQ VQ VQ VQ VQ VQ VQ G_R_SRM_MX G VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS E G J J M M P P T T V_R VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ E E F G G QU QU QU QU QU QU QU QU QL QL QL QL QL QL QL QL QSL QSL QSU QSU N_J N_J N_L N_L N_M N_T N_T E F F F G F G J J L L M T T KGG-F R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_QS R_QS_b R_QS R_QS_b R % R % R.K R.K.uF V NP V_R R_ R_KE V_R VREF_R.uF V.V Reference Only required if R Self-Refresh required when Vybrid in LPStop modes. "on't care" for other Vybrid's modes. MVFNSMK (PVFNSMK) V_R _.uf V _.uf V _,,,,,,, PT[..] PT[..] PT PT PT PT PT PT R.K PV S S_ R.K.uF V.uF V NF_E_b NF_RE_b NF_WE_b NF_LE NF_LE.uF V NF_WP_ NF_R_b NN FLS PV_NN.uF V U E RE WE LE LE WP R/ N N N N N N N N N N N V V V V VSS VSS VSS VSS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O N N N N N N,,, NF_[] NF_[] NF_[] NF_[] NF_[] NF_[] NF_[] NF_[] NF_[] NF_[] NF_[] NF_[] NF_[] NF_[] NF_[] NF_[] MTFGEWP:E PT[..] PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT PT QSPI T[] QSPI T[] QSPI T[] QSPI T[] QSPI S_ QSPI SK QSPI T[] QSPI T[] QSPI T[] QSPI T[] QSPI S_ QSPI SK QSPI NN FLS SI/IO SO/IO WP/IO OL/IO S SK U U V VSS EP SI/IO SO/IO WP/IO OL/IO S SK V VSS EP PV_QSPI SFLS SFLS S S_.uF V PV_QSPI.uF V PV dded: - TPVs on unused R lines, - New ".V Reference" circuit, - R and R (to support R Self-Refresh mode when Vybrid in LPStop modes). eleted: R termination. NP-ed: R. hanged: - from uf to uf (OM consolidation). IP lassification: FP: PUI: rawing Title: TWR-VFGS R & NN Flash Size ocument Number Rev S- PF: SPF- ate: Thursday, January, Sheet of

11 PV PV PV R.K R.K,,,, PT[..] PT,,, PT[..] PT PT R NP R.K R.K NP U EN FLG EN FLG IN OUT OUT MI-YM PV_UX NP UF _ TPV NP.uF V US_VUS,, Use (R + R) to switch between local and Elevator. R US-SL SELL SELL SELL SELL Peripheral (OTG, Micro-) pf V VUS - + I J MIRO_US_VUS F OM U M.uF V P US I RLMPP.TT VUS US_VUS,,, ON_US_N ON_US_P TPV US I R Resistors R and R default population position is Position. R To optimize signal integrity, place (R + R) and US N and P signals in same layer (-Ohm differential line). ELEV_US_N ELEV_US_P US_N US_P US-SL S J G + ost (Type ) US_TYPE FEMLE - V S F OM TP NP US ost +V US_VUS,, R pf V TYPE_US_VUS uf V uf V uf V U M P US I VUS RLMPP.TT US_N US_P dded: - TPVs, - US bypass for deleted U, - and (US spec), - R (NP-ed). - R (NP-ed). - R, R. eleted:,, U,. NP-ed:,. hanged: - from uf to.uf (US spec). IP lassification: FP: PUI: rawing Title: TWR-VFGS US Size ocument Number Rev S- PF: SPF- ate: Thursday, January, Sheet of