VER : 3A. Thermal Sensor & Fan P37 LVDS. E-switch PI2PCIE412-DZHE LVDS MXM III-NB8E (GT/SE/GLM) VRAM 256M VRAM 512M P18 HDMI HDMI P19 P17 SPDIF_MXM

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1 Module Y Mini PI (for ebug) P H / O (ST) P P X'TL.MHz LOK GENERTOR YLFXT RII SO-IMM RII SO-IMM P H (ST) P H / O (PT) P P in ard Reader ontroller R P,P in ard Reader connector P ST ST PT PI us MX(Maddog.) ual hannel R / MHz ual hannel R / MHz X'TL.KHz X'TL.KHz SPI ROM Merom ufpg FS P,P N restline GM ufg P,P,P,P,P,P,P S IHM-E P,P,P,P E WPLG uch Pad G P / Mhz MI X Lane LP K onn. P P P PI-E X Lane PI-E X Lane US. x zalia SPIF_MXM IR P VER : Thermal Sensor & Fan MXM III-NE (GT/SE/GLM) VRM M VRM M P zalia udio ontroller L P,P P LVS LVS HMI SPIF_MXM US US US US US US E-switch PIPIE-ZHE P HMI P US Port x Left Side US Port x Right Side P & IO board luetooth P P IO board EL P,P,P TT harger MX P LVS HMI Port IO board TT Selector MX.V/.V MX PIE- PIE- PIE- PIE- PIE- P P TFT L Panel P US US Express ard P MINI ard WLN P MINI ard Robson P VORE MX P /././. /./. V X'TL.MHz IEEE ontroller FW P X'TL MHz P M/M/G LN MM P,P IEEE Port System V/.V ISL P /TT onn. Transformer HPL-- IO board P IO board (udio-left Side; HMI-Right Side) IO board P RJ IO board US MINI ard Wireless-US P _: change P version from to E MX M P udio mplifier Phone Jack MX HP/MI/Line Out/SPIF P IO board Phone Jack HP/MI /Line Out IO board MI P QUNT OMPUTER lock iagram Speaker Size ocument Number Rev P MX ate: Friday, October, Sheet of

2 PU(HOST) () H_STPLK# () H_#[:] () H_ST# () H_REQ#[:] () H_#[:] () H_ST# () H_M# () H_FERR# () H_IGNNE# R _ () H_INTR () H_NMI () H_SMI# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_REQ# H_REQ# H_REQ# H_REQ# H_REQ# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_STPLK_R# U J []# L []# L []# K []# M []# N []# J []# N []# P []# P []# L []# P []# P []# R []# M ST[]# R GROUP R GROUP K REQ[]# H REQ[]# K REQ[]# J REQ[]# L REQ[]# Y []# U []# R []# W []# U []# Y []# U []# R []# T []# T []# W []# W []# Y []# U []# V []# W []# []# []# []# V ST[]# M# FERR# IGNNE# STPLK# LINT LINT SMI# M RSV[] N RSV[] T RSV[] V RSV[] RSV[] RSV[] RSV[] RSV[] RSV[] F RSV[] RESERVE XP/ITP SIGNLS ONTROL THERML PROHOT# THERM THERM IH H LK LK[] LK[] Merom all-out Rev a S# NR# PRI# EFER# RY# SY# R# IERR# INIT# LOK# RESET# RS[]# RS[]# RS[]# TRY# HIT# HITM# PM[]# PM[]# PM[]# PM[]# PRY# PREQ# TK TI TO TMS TRST# R# THERMTRIP# H E G H F E F H F F G G G E H_IERR# H_PURST_PU# XP_PM# XP_PM# XP_PM# XP_PM# XP_PM# XP_PM# XP_TK XP_TI XP_TO XP_TMS XP_TRST# XP_RESET# H_PROHOT_R# H_THERM H_THERM PM_THRMTRIP# R R _ R R LK_PU_LK () LK_PU_LK# ()./F_./F_ *.K N H_THERM () H_THERM () H_S# () H_NR# () H_PRI# () H_EFER# () H_RY# () H_SY# () H_REQ# ().V_VP H_INIT# () H_LOK# () H_RS# () H_RS# () H_RS# () H_TRY# () H_HIT# () H_HITM# () T T T T T T.V_VP SYS_RST# () H_PROHOT# H_THERM H_THERM lose to PU T R _ P/V for EMI request, close to PU H_PURST# () PROHOT# : efault is PU ohm, if no use. efault serial R is N, if it's used and connect to IMVP, PU ohm, serial R.K. *P/V_N PU/P (ITP).V_VP XP_TMS XP_TI TMS TRST# TK TO R /F_ R /F_ XP_PM# R *./F N XP_TO R *./F N XP_TK R /F_ XP_TRST# R /F_ ITP disable guidelines Signal Resistor Value onnect Resistor Placement TI ohm /- % VTT Within." of the ITP ohm /- % VTT ohm /- % ohm /- % Open VTT Within." of the ITP Within." of the ITP Within." of the ITP Within." of the ITP ITP_EN PU epop.v_run lose to K Pin Thermal Trip.V_VP R (,,) ELY_VR_PWRGOO *HH-PT_N *K N Q.V_VP FVN *U_N R Q./F_ MMT.V_VP () H_#[:] () H_STN# () H_STP# () H_INV# () H_#[:] <heck list & R> Layout note: Z= ohm H_GTLREF<." R () H_STN# K/F_ () H_STP# () H_INV# R K/F T T T T H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# U E []# F []# E []# G []# F []# G []# E []# E []# K []# G []# J []# J []# H []# F []# K []# H []# J STN[]# H STP[]# H INV[]# N []# K []# P []# R []# L []# M []# L []# M []# P []# P []# P []# T []# R []# L []# T []# N []# L STN[]# M STP[]# T GRP T GRP []# Y []# []# V []# V []# V []# T []# U []# U []# Y []# W []# Y []# W []# W []# []# []# STN[]# Y STP[]# INV[]# U T GRP []# E []# []# []# []# []# []# []# E []# F []# []# E []# []# []# []# F []# STN[]# E STP[]# F T GRP H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#[:] () H_STN# () H_STP# () H_INV# () H_#[:] () H_STN# () H_STP# () H_INV# () PM_THRMTRIP# SYS_SHN# (,) PM_THRMTRIP# (,) <R & esign guide> Layout Note: Thermal trip should connect to IH & GMH without T-ing (ZS default N) N INV[]# INV[]# <heck list & R> Layout note: L<." H_GTLREF OMP R./F R *K_N PU_TEST GTLREF OMP[] R OMP OMP/ Z=.ohm R./F R *K_N PU_TEST TEST MIS OMP[] U OMP OMP/ Z=. PU_TEST OMP[] R./F TEST OMP R./F PU_TEST TEST OMP[] Y F PU_TEST TEST QUNT F IH_PRSTP# (,,) PU_TEST TEST PRSTP# E FS LK SEL SEL SEL TEST PSLP# H_PSLP# () H_PWR# () <R & esign guide> OMPUTER PWR# (,) PU_MH_SEL SEL[] PWRGOO H_PWRG () Layout Note:onnect from S and PU Host(/) (,) PU_MH_SEL H_PUSLP# () daisy chain to PU ORE VR. Not SEL[] SLP# (,) PU_MH_SEL SEL[] PSI# E PSI# () use T connect.(s/vr/pu/n) Size ocument Number Rev Merom all-out Rev a MX ate: Friday, October, Sheet of

3 PU(Power) V_ORE ll use U V(-%,XS,)Pb-Free. V_ORE U/V U/V V_ORE V_ORE V_ORE V_ORE.V_VP U/V inside cavity, north side, secondary layer. U/V U/V U/V U/V inside cavity, south side, secondary layer. U/V U/V U/V inside cavity, north side, primary layer. U/V U/V inside cavity, south side, primary layer..u/v U/V U/V U/V U/V.U/V U/V U/V.U/V U/V Layout out: Place these inside socket cavity on North side secondary. U/V U/V U/V U/V U/V.U/V U/V U/V.U/V U/V U/V U/V U/V U/V U/V.U/V V_ORE V_ORE U V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] E <REV.NO../REF.NO.> V[] V[] E V[] V[] E Ivcc Max V[] V[] E V[] V[] E V[] V[] E Ivccp Max (VP supply before Vcc stable) V[] V[] E Max (VP supply after Vcc stable) V[] V[] E V[] V[] F Ivcca Max m V[] V[] F V[] V[] F V[] V[] F V[] V[] F V[] V[] F V[] V[] F E.V_VP V[] V[] F E V[] E V[] VP[] G E V[] VP[] V E V[] VP[] J E V[] VP[] K E V[] VP[] M E U/.V_ V[] VP[] J <heck list> E V[] VP[] K ESR=m ohm F V[] VP[] M F V[] VP[] N F V[] VP[] N F V[] VP[] R F V[] VP[] R F V[] VP[] T F V[] VP[] T F V[] VP[] V <R> F.V_RUN V[] VP[] W.U near to ball V[] V_PRO R V[] V[] V[] V[] V[] V[] VI[] H_VI () V_ORE.U/V_ U/V V[] VI[] F H_VI () V[] VI[] E H_VI () V[] VI[] F H_VI () en_:change from V[] VI[] E H_VI () HK to V[] VI[] F R H_VI () V[] VI[] E H_VI () HKMEE for derating. /F V[] V[] V[] VSENSE F VSENSE () V[] V[] V[] SENSE E SENSE () Merom all-out Rev a. R /F <emo board> Routing.ohm with mils spacing PU/P near to PU " U [] [] P [] [] P [] [] P [] [] R [] [] R [] [] R [] [] R F [] [] T [] [] T [] [] T [] [] T [] [] U [] [] U [] [] U [] [] U [] [] V [] [] V [] [] V [] [] V [] [] W [] [] W [] [] W [] [] W [] [] Y [] [] Y [] [] Y [] [] Y [] [] [] [] [] [] [] [] [] [] [] [] [] [] E [] [] E [] [] E [] [] E [] [] E [] [] E [] [] E [] [] E [] [] E [] [] F [] [] F [] [] F [] [] F [] [] F [] [] F [] [] F [] [] F [] [] F [] [] G [] [] G [] [] G [] [] G [] [] H [] [] H [] [] H [] [] H [] [] J [] [] J [] [] J [] [] J [] [] E K [] [] E K [] [] E K [] [] E K [] [] E L [] [] E L [] [] E L [] [] E L [] [] E M [] [] M [] [] F M [] [] F M [] [] F N [] [] F N [] [] F N [] [] F N [] [] F P [] [] [] F Merom all-out Rev a. QUNT OMPUTER PU Power(/) Size ocument Number Rev MX ate: Friday, October, Sheet of

4 N(HOST).V_VP.V_VP R /F R /F R./F R./F R./F.U/V H_SWING H_ROMP <check list> : mils(width:spacing) H_SOMP H_SOMP# <check list>.u close to () H_PURST# R _ () H_#[:].V_VP H_PURST_N# P/V for EMI request, close to N R K/F R () H_PUSLP# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_SWING H_ROMP H_SOMP H_SOMP# H_REF U E H_#_ G H_#_ G H_#_ M H_#_ H H_#_ H H_#_ G H_#_ F H_#_ N H_#_ H H_#_ M H_#_ N H_#_ N H_#_ H H_#_ P H_#_ K H_#_ M H_#_ W H_#_ Y H_#_ V H_#_ M H_#_ J H_#_ N H_#_ N H_#_ W H_#_ W H_#_ N H_#_ Y H_#_ Y H_#_ P H_#_ W H_#_ N H_#_ H_#_ E H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ Y H_#_ H_#_ E H_#_ H_#_ G H_#_ J H_#_ H H_#_ J H_#_ E H_#_ E H_#_ H H_#_ J H_#_ H H_#_ J H_#_ E H_#_ J H_#_ J H_#_ E H_#_ J H_#_ H H_#_ H H_#_ H_SWING H_ROMP W H_SOMP W H_SOMP# H_PURST_N# H_PURST# E H_PUSLP# H_VREF H_VREF HOST RESTLINE_GM FG QS H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_S# H_ST#_ H_ST#_ H_NR# H_PRI# H_REQ# H_EFER# H_SY# HPLL_LK HPLL_LK# H_PWR# H_RY# H_HIT# H_HITM# H_LOK# H_TRY# H_INV#_ H_INV#_ H_INV#_ H_INV#_ H_STN#_ H_STN#_ H_STN#_ H_STN#_ H_STP#_ H_STP#_ H_STP#_ H_STP#_ H_REQ#_ H_REQ#_ H_REQ#_ H_REQ#_ H_REQ#_ H_RS#_ H_RS#_ H_RS#_ J M F L G K L J K P R H L M N J E E N G H G E F M M H K E G K L E M K H L K J M E H E H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_INV# H_INV# H_INV# H_INV# H_STN# H_STN# H_STN# H_STN# H_STP# H_STP# H_STP# H_STP# H_REQ# H_REQ# H_REQ# H_REQ# H_REQ# H_RS# H_RS# H_RS# H_#[:] () H_#[:] are not supported in alero Interposer restline support bit address H_S# () H_ST# () H_ST# () H_NR# () H_PRI# () H_REQ# () H_EFER# () H_SY# () LK_MH_LK () LK_MH_LK# () H_PWR# () H_RY# () H_HIT# () H_HITM# () H_LOK# () H_TRY# () H_INV#[:] () H_STN#[:] () H_STP#[:] () H_REQ#[:] () H_RS#[:] () K/F.U/V N P/N JSLTT <check list>.u close to within mils QUNT OMPUTER GMH Host(/) Size ocument Number Rev MX ate: Friday, October, Sheet of

5 U <check list> Vcc_ for alero Vcc_/Vcc_ for restline._peg R R R () L_KLT_TRL () INT_LVS_LON.V_RUN /F_ /F_ /F_ INT_RT_LU INT_RT_GRN INT_RT_RE R R () INT_LVS_EILK () INT_LVS_EIT () INT_LVS_IGON <check list & R> For alero :.K For resstline:.k () INT_TXLLKOUT- () INT_TXLLKOUT () INT_TXULKOUT- () INT_TXULKOUT () INT_TXLOUT- () INT_TXLOUT- () INT_TXLOUT- () INT_TXLOUT () INT_TXLOUT () INT_TXLOUT () INT_TXUOUT- () INT_TXUOUT- () INT_TXUOUT- () INT_TXUOUT () INT_TXUOUT () INT_TXUOUT () INT_RT_LU () INT_RT_GRN () INT_RT_RE () INT_RT_LK () INT_RT_T <check list & R> R.K/F () INT_HSYN For alero : () INT_VSYN For resstline:.k/f For external VG: ohm K_ K_ R.K_ T INT_RT_LU INT_RT_GRN INT_RT_RE J H E E K LVS_IG L LVS_VG L N N E G E F G E F G E E G K F J L M P H G K J F E K G R /F HSYN F RTIREF R /F VSYN E L_KLT_TRL L_KLT_EN L_TRL_LK L_TRL_T L LK L T L_V_EN LVS_IG LVS_VG LVS_VREFH LVS_VREFL LVS_LK# LVS_LK LVS_LK# LVS_LK LVS_T#_ LVS_T#_ LVS_T#_ LVS_T_ LVS_T_ LVS_T_ LVS_T#_ LVS_T#_ LVS_T#_ LVS_T_ LVS_T_ LVS_T_ TV_ TV_ TV_ TV_RTN TV_RTN TV_RTN TV_ONSEL_ TV_ONSEL_ RT_LUE RT_LUE# RT_GREEN RT_GREEN# RT_RE RT_RE# RT LK RT T RT_HSYN RT_TVO_IREF RT_VSYN LVS PI-EXPRESS GRPHIS TV VG PEG_OMPI PEG_OMPO PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ N EXP OMPX M J L N T T U Y Y W G H G G PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN J PEG_RXP L PEG_RXP M PEG_RXP U PEG_RXP T PEG_RXP T PEG_RXP W PEG_RXP W PEG_RXP PEG_RXP Y PEG_RXP PEG_RXP PEG_RXP H PEG_RXP G PEG_RXP H PEG_RXP G PEG_RXP N _PEG_TXN U _PEG_TXN U _PEG_TXN N _PEG_TXN R _PEG_TXN T _PEG_TXN Y _PEG_TXN W _PEG_TXN W _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN H _PEG_TXN E _PEG_TXN H _PEG_TXN M _PEG_TXP T _PEG_TXP T _PEG_TXP N _PEG_TXP R _PEG_TXP U _PEG_TXP W _PEG_TXP Y _PEG_TXP Y _PEG_TXP _PEG_TXP _PEG_TXP _PEG_TXP _PEG_TXP G _PEG_TXP E _PEG_TXP H _PEG_TXP R./F_ PEG_RXN[:] () <check list> SVO/PIE/LVS not implement lanes N PEG_RXP[:] ().U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_ PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXN[:] () PEG_TXP[:] () RESTLINE_GM FG QS QUNT OMPUTER GMH Graphics(/) Size ocument Number Rev MX ate: Friday, October, Sheet of

6 Strapping table ll strap are sampled with respect to the leading edge of the GMH power ok signal FG[:] have internal pull-up FG[:] have internal pull-down ny FG signal strapping option not list below should be left N pin Pin Name FG[:] FG[:] FG FG FG FG FG FG[:] FG[:] FG[:] FG FG[:] FG FG SVO_TRLT Strap escription FS Frequency Select MI X Select PU Strap Low Power PI Express PI Express Graphics Lane Reversal XOR/ LLZ/ lock Un gating FS ynamic OT MI Lane Reversal SVO/PIe concurrent SVO Present onfiguration = FS MHz = FS MHz = MI X = MI X (efault) = = Mobile PU (efault) = Normal mode = Low Power mode (efault) = Reverse Lanes = Normal operation (efault) = = LL-Z Mode Enabled = XOR Mode Enabled = lock Gating Enabled (efault) = ynamic OT disable = ynamic OT Enable (efault) = Normal operation (efault) = Reverse Lanes = Only SVO or PIE x is operation (efault) = SVO and PIE x are operating simultaneously via the PEG port = No SVO ard present (efault) = SVO ard Present () PM_MUSY# (,,) IH_PRSTP# () PM_EXTTS# () PM_EXTTS# (,,) ELY_VR_PWRGOO () PLTRST#_N (,) PM_THRMTRIP# (,) PM_PRSLPVR INTEL R.UF (,) PU_MH_SEL (,) PU_MH_SEL (,) PU_MH_SEL T T T T T T T R _ R _ R _ R _ R _ R *_N R _ M_ROMP M_ROMP# SM_ROMP_VOH SM_ROMP_VOL SM_VREF_MH LK_REFLK LK_REFLK# LK_REFSSLK LK_REFSSLK# LK_PIE_GPLL LK_PIE_GPLL# MH_GFX_VI_ MH_GFX_VI_ MH_GFX_VI_ MH_GFX_VI_ R *_N L_LK M R L_LK () L_T K L_T () J.V_RUN L_PWROK T K/F_ N_ MPWROK (,) K N_ L_RST# N L_RST# () K.V_L_VREF PM_EXTTS# L_VREF M R K_ N_ L MH_FG_ R *.K/F_N N_ L R K_ PM_EXTTS# N_ L R MH_FG_ R *.K/F_N N_ L N_ K.U/V_ /F.V_RUN MH_FG_ R *.K/F_N N_ J N_ SVO_TRL_LK H E MH_FG_ MH_FG_ R *.K/F_N N_ SVO_TRL_T K R *.K/F_N N_ LK_REQ# G LK_GPLLREQ# () MH_IH_SYN# () MH_FG_ MH_FG_ N_ IH_SYN# G R *.K/F_N R *.K/F_N N_ N_ GMH_TEST N_ TEST_ R _ K GMH_TEST R K_ SM_ROMP_VOH.V_SUS SMR_VREF.V_SUS R K/F_ N_ TEST_ R RESTLINE_GM FG QS R R.U/V_.U/.V R.K/F_ *K/F_N KLL SM_ROMP_VOL QUNT SM_VREF_MH R R OMPUTER *K/F_N.U/V_.U/V_.U/V_.U/.V GMH Strapping(/) K/F_ Size ocument Number Rev MX ate: Friday, October, Sheet of T T T T.U/V_ U P RSV P RSV R RSV N RSV R RSV R RSV M RSV N RSV J RSV R RSV M RSV L RSV M RSV RSV H RSV RSV J RSV K RSV F RSV H RSV K RSV J RSV F RSV G RSV RSV RSV H RSV W RSV K RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV P FG_ N FG_ N MH_FG_ FG_ MH_FG_ FG_ MH_FG_ FG_ F MH_FG_ FG_ N MH_FG_ FG_ G MH_FG_ FG_ J MH_FG_ FG_ MH_FG_ FG_ R MH_FG_ FG_ L MH_FG_ FG_ J MH_FG_ FG_ E MH_FG_ FG_ E MH_FG_ FG_ K MH_FG_ FG_ M MH_FG_ FG_ M MH_FG_ FG_ L MH_FG_ FG_ N MH_FG_ FG_ L FG_ PM_MUSY#_R G IH_PRSTP#_R PM_M_USY# L PM_EXTTS#_R PM_PRSTP# L PM_EXTTS#_R PM_EXT_TS#_ J PM_EXT_TS#_ W RST_IN#_MH PWROK V PM_THRMTRIP#_GMH RSTIN# N PM_PRSLPVR_GMH THERMTRIP# G PRSLPVR RSV PM N R MUXING LK FG MI GRPHIS VI ME MIS SM_K_ V SM_K_ SM_K_ SM_K_ V SM_K#_ W SM_K#_ SM_K#_ W SM_K#_ W SM_KE_ E SM_KE_ Y SM_KE_ SM_KE_ G SM_S#_ G SM_S#_ K SM_S#_ G SM_S#_ E SM_OT_ H SM_OT_ J SM_OT_ J SM_OT_ E SM_ROMP L SM_ROMP# K SM_ROMP_VOH K SM_ROMP_VOL L SM_VREF_ R SM_VREF_ W PLL_REF_LK PLL_REF_LK# PLL_REF_SSLK H PLL_REF_SSLK# H PEG_LK K PEG_LK# K MI_TXN MI_RXN_ N MI_TXN MI_RXN_ J MI_TXN MI_RXN_ N MI_TXN MI_RXN_ N MI_TXP MI_RXP_ M MI_TXP MI_RXP_ J MI_TXP MI_RXP_ N MI_TXP MI_RXP_ N MI_RXN MI_TXN_ J MI_RXN MI_TXN_ J MI_RXN MI_TXN_ M MI_RXN MI_TXN_ M MI_RXP MI_TXP_ J MI_RXP MI_TXP_ J MI_RXP MI_TXP_ M MI_RXP MI_TXP_ M GFX_VI_ E GFX_VI_ GFX_VI_ GFX_VI_ GFX_VR_EN E M_LK () M_LK () M_LK () M_LK () M_LK# () M_LK# () M_LK# () M_LK# () M_KE () M_KE () M_KE () M_KE () M_S# () M_S# () M_S# () M_S# () M_OT () M_OT () M_OT () M_OT () MI_TXN[:] () MI_TXP[:] () MI_RXN[:] () MI_RXP[:] () T T T T SUS# (,,) INTEL R RESSTLINE SHOUL USE ohm <check list & R> R Value select For alero :.ohm For resstline:ohm ut check list use.ohm <FE>.ohm M_ROMP M_ROMP#.V_SUS LK_REFLK () LK_REFLK# () LK_REFSSLK () LK_REFSSLK# () LK_PIE_GPLL () LK_PIE_GPLL# ().V_RUN R /F_ R /F_

7 N(Memory controller) () M Q[:] M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q U R S_Q_ W S_Q_ S_Q_ Y S_Q_ R S_Q_ R S_Q_ T S_Q_ W S_Q_ S_Q_ F S_Q_ G S_Q_ J S_Q_ S_Q_ G S_Q_ H S_Q_ E S_Q_ W S_Q_ E S_Q_ G S_Q_ E S_Q_ F S_Q_ H S_Q_ G S_Q_ F S_Q_ R S_Q_ W S_Q_ T S_Q_ W S_Q_ W S_Q_ Y S_Q_ V S_Q_ T S_Q_ V S_Q_ T S_Q_ W S_Q_ V S_Q_ U S_Q_ T S_Q_ S_Q_ S_Q_ E S_Q_ S_Q_ S_Q_ Y S_Q_ G S_Q_ W S_Q_ S_Q_ S_Q_ S_Q_ Y S_Q_ T S_Q_ T S_Q_ Y S_Q_ S_Q_ R S_Q_ R S_Q_ R S_Q_ N S_Q_ M S_Q_ N S_Q_ T S_Q_ N S_Q_ M S_Q_ N S_Q_ R SYSTEM MEMORY RESTLINE_GM FG QS S_S_ S_S_ S_S_ S_S# S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_RS# S_RVEN# S_WE# K F L T W W G Y N T E H P T H P J K H L K J J L E G J J E Y M M M M M M M M M M M M M M M M M QS M QS M QS M QS M QS M QS M QS M QS M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS# M M M M M M M M M M M M M M M TP_S_RVEN# () M Q[:] UE M Q M S () P M Q S_Q_ S_S_ Y M S () M S () R M Q S_Q_ S_S_ G M S () M S () W M Q S_Q_ S_S_ G M S () M S# () W M Q S_Q_ M S# () N M Q S_Q_ S_S# E M M[:] () N M Q S_Q_ M M[:] () V M M M Q S_Q_ S_M_ R V M M M Q S_Q_ S_M_ M M M Q S_Q_ S_M_ K M M M Q S_Q_ S_M_ L M M M Q S_Q_ S_M_ H E M M M Q S_Q_ S_M_ J M M M Q S_Q_ S_M_ F Y M M M Q S_Q_ S_M_ W M QS[:] () F M Q S_Q_ M QS[:] () F M QS M Q S_Q_ S_QS_ T J M QS M Q S_Q_ S_QS_ J M QS M Q S_Q_ S_QS_ K J M QS M Q S_Q_ S_QS_ K L M QS M Q S_Q_ S_QS_ J K M QS M Q S_Q_ S_QS_ L K M QS M Q S_Q_ S_QS_ E M QS M QS#[:] () K M QS#[:] () M Q S_Q_ S_QS_ V K M QS# M Q S_Q_ S_QS#_ U J M QS# M Q S_Q_ S_QS#_ L M QS# M Q S_Q_ S_QS#_ L J M QS# M Q S_Q_ S_QS#_ K J M QS# M Q S_Q_ S_QS#_ K K M QS# M Q S_Q_ S_QS#_ K J M QS# M Q S_Q_ S_QS#_ F L M QS# M Q S_Q_ S_QS#_ V M [:] () K M [:] () M Q S_Q_ K M M Q S_Q_ S_M_ E M M Q S_Q_ S_M_ G K M M Q S_Q_ S_M_ G M M Q S_Q_ S_M_ W M M Q S_Q_ S_M_ F E M M Q S_Q_ S_M_ E M M Q S_Q_ S_M_ G M M Q S_Q_ S_M_ J M M Q S_Q_ S_M_ Y L M M Q S_Q_ S_M_ K M M Q S_Q_ S_M_ G L M M Q S_Q_ S_M_ E K M M Q S_Q_ S_M_ K M M Q S_Q_ S_M_ G M M () J M () M Q S_Q_ S_M_ E J M RS# () M Q S_Q_ S_RS# V TP_S_RVEN# M RS# () F M Q S_Q_ S_RVEN# Y T T H M Q S_Q_ G M WE# () M Q S_Q_ S_WE# M WE# () M Q S_Q_ K M Q S_Q_ E M Q S_Q_ M Q S_Q_ J M Q S_Q_ M Q S_Q_ M Q S_Q_ R M Q S_Q_ T M Q S_Q_ Y M Q S_Q_ Y M Q S_Q_ U M Q S_Q_ T S_Q_ R SYSTEM MEMORY RESTLINE_GM FG QS QUNT OMPUTER GMH RII(/) Size ocument Number Rev MX ate: Friday, October, Sheet of

8 VSM_LF VSM_LF VSM_LF VSM_LF VSM_LF VSM_LF VSM_LF.V_VP.V_VP.V_VP.V_VP.V_VP.V_SUS.V_VP Size ocument Number Rev ate: Sheet of QUNT OMPUTER MX GMH Power-(/) Friday, October, Size ocument Number Rev ate: Sheet of QUNT OMPUTER MX GMH Power-(/) Friday, October, Size ocument Number Rev ate: Sheet of QUNT OMPUTER MX GMH Power-(/) Friday, October, N(Power-) H=. H=. H=. U/.V_ U/.V_.U/.V_.U/.V_.U/.V_.U/.V_.U/V_.U/V_ U/V_ U/V_.U/.V_.U/.V_.U/V_.U/V_ U/V_ U/V_ POWER V ORE V SM V GFX V GFX NTF V SM LF UG RESTLINE_GM FG QS POWER V ORE V SM V GFX V GFX NTF V SM LF UG RESTLINE_GM FG QS V_ V_ K V_ J V_ J V_ H V_ H V_ H V_ F V_ T V_ V_SM_ V_SM_ F V_SM_ J V_SM_ W V_SM_ Y V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ E V_SM_ E V_SM_ E V_SM_ U V_SM_ F V_SM_ G V_SM_ G V_SM_ G V_SM_ H V_SM_ H V_SM_ H V_SM_ J V_SM_ J V_SM_ U V_SM_ K V_SM_ K V_SM_ K V_SM_ K V_XG_NTF_ U V_XG_NTF_ U V_XG_NTF_ U V_XG_NTF_ U V_XG_NTF_ U V_XG_NTF_ U V_XG_NTF_ V V_XG_NTF_ V V_XG_NTF_ V V_XG_NTF_ V V_XG_NTF_ T V_XG_NTF_ V V_XG_NTF_ V V_XG_NTF_ V V_XG_NTF_ Y V_XG_NTF_ Y V_XG_NTF_ Y V_XG_NTF_ Y V_XG_NTF_ Y V_XG_NTF_ Y V_XG_NTF_ Y V_XG_NTF_ T V_XG_NTF_ Y V_XG_NTF_ Y V_XG_NTF_ Y V_XG_NTF_ Y V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ T V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ F V_XG_NTF_ F V_XG_NTF_ H V_XG_NTF_ H V_XG_NTF_ H V_XG_NTF_ H V_XG_NTF_ T V_XG_NTF_ J V_XG_NTF_ J V_XG_NTF_ J V_XG_NTF_ K V_XG_NTF_ K V_XG_NTF_ L V_XG_NTF_ L V_XG_NTF_ L V_XG_NTF_ L V_XG_NTF_ L V_XG_NTF_ T V_XG_NTF_ L V_XG_NTF_ M V_XG_NTF_ M V_XG_NTF_ M V_XG_NTF_ M V_XG_NTF_ M V_XG_NTF_ P V_XG_NTF_ P V_XG_NTF_ P V_XG_NTF_ T V_XG_NTF_ P V_XG_NTF_ P V_XG_NTF_ P V_XG_NTF_ U V_XG_NTF_ U V_SM_ L V_SM_ V V_SM_ W V_XG_NTF_ T V_ T V_SM_ U V_XG_ R V_XG_ T V_XG_ W V_XG_ W V_XG_ Y V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ F V_XG_ F V_XG_ H V_XG_ H V_XG_ H V_XG_ H V_XG_NTF_ P V_XG_NTF_ P V_XG_NTF_ R V_XG_NTF_ R V_XG_NTF_ R V_XG_NTF_ R V_XG_NTF_ R V_ R V_XG_ H V_XG_ J V_XG_ N V_SM_LF W V_SM_LF V_SM_LF E V_SM_LF V_SM_LF V_SM_LF W V_SM_LF T V_XG_ V_XG_ V_ H V_XG_NTF_ M V_SM_ U V_XG_NTF_ V V_XG_NTF_ V V_XG_NTF_ V V_XG_NTF_ Y.U/.V_.U/.V_.U/V_.U/V_.U/V_.U/V_ U/V U/V.U/.V_.U/.V_ U U U_ U_ U/V U/V.U/.V_.U/.V_ U_ U_ U/V_ U/V_.U/V_.U/V_.U_.U_.U/V.U/V U_ U_.U/V_.U/V_.U.U U/V_ U/V_ POWER V NTF NTF S V XM V XM NTF UF RESTLINE_GM FG QS POWER V NTF NTF S V XM V XM NTF UF RESTLINE_GM FG QS V_NTF_ V_NTF_ K V_NTF_ P V_NTF_ U V_NTF_ F V_NTF_ F V_NTF_ H V_NTF_ H V_NTF_ H V_NTF_ H V_NTF_ J V_NTF_ K V_NTF_ K V_NTF_ K V_NTF_ V_NTF_ L V_NTF_ L V_NTF_ V_NTF_ P V_NTF_ R V_NTF_ R V_NTF_ T V_NTF_ T V_NTF_ T V_NTF_ U V_NTF_ V_NTF_ U V_NTF_ U V_NTF_ U V_NTF_ U V_NTF_ V V_NTF_ V V_NTF_ V V_NTF_ V_NTF_ V_NTF NTF_ T _NTF_ T _NTF_ U _NTF_ U _NTF_ V _NTF_ V _NTF NTF NTF_ V_NTF NTF NTF NTF_ F _NTF_ K _NTF_ M _NTF_ P _NTF_ R _NTF_ R _NTF_ R V_NTF_ Y V_XM_ K V_XM_ K V_XM_ J V_XM_ J V_XM_NTF_ L V_XM_NTF_ L V_XM_NTF_ L V_XM_NTF_ M V_XM_NTF_ M V_XM_NTF_ M V_XM_NTF_ M V_XM_NTF_ P V_XM_NTF_ P V_XM_NTF_ R V_NTF_ Y V_NTF_ Y V_NTF_ Y V_NTF_ Y _S _S _S _S L _S L _S V_NTF_ V_NTF_ V_NTF_ V_NTF_ J V_NTF NTF_ F V_NTF_ J V_XM_ K V_XM_NTF_ L V_XM_NTF_ L V_XM_NTF_ L _NTF_ M V_XM_NTF_ M V_XM_NTF_ M V_NTF_ M _NTF_ P V_XM_NTF_ P V_XM_NTF_ P V_XM_NTF_ R V_XM_NTF_ R V_XM_ T V_XM_ T V_NTF_ V.U/V_.U/V_.U_.U_

9 N(Power-).V_RUN L UH_.V_RUN <FE> INT VG disable VSYN connect to.u_ RT/TV isable/enable guideline all Enable isable all V_RT.V V TVO V_RT.V V_TVO Enable.V.V isable.v LVS isable/enable guideline Signal V_LVS V_LVS If SVO isable LVS isable If SVO enable LVS isable.v.v If SVO enable LVS enable.v U/.V_.U/V_.V_RUN L KPHS-T.U_ N_ VQ_RT.V V TVO.V V TVO.V VG_.V G_ V_SYN.V VTX_LVS EXTERNL.V INTERNL.V_RUN.V_RUN L.V_RUN UH_ U/.V_ L L U/.V_ R REOMMEN OHM@MHz Rdc=.OHM (max) L KPHS-T U_ UH.V_VP J V_TV_ R VSYN VTT_ U V_V_RT_ VTT_ U V_RT VTT_ U.U/V_.U/V_.U/V V_RT VTT_ U U/.V_.U_ N_ VTT_ U H=..U/V_ V_V G VTT_ U V G VTT_ U VTT_ U G VTT_ U VTT_ U.V_V_PLL VTT_ T V_PLL VTT_ T.V_RUN.V_V_PLL VTT_ T H V_PLL VTT_ T KPHS-T.VM_V_HPLL VTT_ T L *U/.V N V_HPLL VTT_ T U/V.VM_V_MPLL VTT_ T M V_MPLL VTT_ T.U/V_ VTT_ T U/.V_.V_SUS R.VSUS_V_LVS VTT_ R V_LVS VTT_ R.V_RUN VTT_ R KPHS-T _LVS P_ U/V_ V_X_ T U/V V_X_ U K R.V_RUN R _ V_V_PEG_G V_PEG_G V_X_ U./F.U/V_ V_X_ T K _PEG_G V_X_ T V.M_MPLL_R V_X_ T.V_RUN.U/V_.V_V_PEG_PLL U V_PEG_PLL V_X_NTF R.V_RUN R.VM_V_SM W.U/V_ V_SM_ V_XF_ V V_SM_ V_XF_ U POWER V_SM_ V_XF_ U L UH_.V_SUS.U/V U/.V_ U/V V_SM_ U H=. U/.V_ V_SM_ V_MI J T R /F V._SMK_R V_SM_ T.VSUS_V_SM_K V_SM_K_ K.U/V_ U/.V_ V_SM_ T V_SM_ V_SM_K_ K T.V_RUN R V_SM_ V_SM_K_ J T V_SM_ V_SM_K_ J R V_SM_NTF_ R V_SM_NTF_ U/.V_.U/V_.VSUS_V_TX_LVS L UH_.V_SUS.VM_V_SM_K V_TX_LVS V_SM_K_ V_SM_K_ V_V_HV V_TV_ V_HV_ V_TV V_HV_ P_ U/V V_TV V_TV H=..U_ V_TV V_PEG_ V_TV V_PEG_ W._PEG V_TV V_PEG_ W V_PEG_ V R V_PEG_ V M V_RT L V_TV L nh.v_vp.v_v_q V_RXR_MI_ H.U_ N V_Q V_RXR_MI_ H.V_RUN R.VM_MH_V_HPLL N V_HPLL.U/V_.V_V_PEG_PLL VTTLF U U/V V_PEG_PLL VTTLF F <FE> V_RXR_MI and V_PEG VTTLF H.U/V_ J V_LVS_ H=..U_ connect to.v H.U/V_ V_LVS_.V_RUN L KPHS-T RESTLINE_GM FG QS R /F_ RT PLL K SM PEG LVS TV TV/RT LVS X XF SM K MI PEG VTT HV VTTLF.U/.V_.U/.V_.U/.V_ U/.V_ <FE> INT VG disable V_TV still.v V.S_PEGPLL_F.U/V_.V_RUN.U/V_ R _.U_ N/V_ N_.V_SUS R.V_V_LVS.V_VP SMKL--F.V_S QUNT V_V_HV U U.V_RUN R OMPUTER <R>.U/V_ GMH Power-(/).V N.M shall be Size ocument Number Rev.V for alero Interposer MX ate: Friday, October, Sheet of R

10 Size ocument Number Rev ate: Sheet of QUNT OMPUTER MX GMH Power-(/) Friday, October, Size ocument Number Rev ate: Sheet of QUNT OMPUTER MX GMH Power-(/) Friday, October, Size ocument Number Rev ate: Sheet of QUNT OMPUTER MX GMH Power-(/) Friday, October, N(Power-) UJ RESTLINE_GM FG QS UJ RESTLINE_GM FG QS _ E _ E _ E _ E _ E _ E _ F _ F _ F _ F _ F _ G _ G _ G _ G _ G _ G _ G _ G _ G _ G _ G _ G _ H _ H _ H _ H _ J _ J _ J _ J _ J _ J _ J _ J _ K _ K _ K _ L _ L _ L _ L _ L _ L _ L _ L _ M _ M _ M _ M _ M _ M _ M _ N _ N _ N _ N _ N _ N _ N _ N _ N _ N _ P _ P _ P _ P _ P _ R _ T _ T _ T _ U _ U _ U _ W _ W _ W _ W _ W _ W _ Y _ Y _ Y _ V _ V _ Y _ Y _ Y _ Y _ Y _ P _ T _ T _ T _ R F _ F _ T _ V _ H UI RESTLINE_GM FG QS UI RESTLINE_GM FG QS E _ E _ E _ F _ F _ F _ F _ G _ G _ G _ G _ G _ H _ H _ H _ H _ H _ J _ J _ J _ J _ J _ J _ J _ J _ J _ K _ K _ K _ K _ K _ K _ L _ M _ M _ M _ M _ M _ M _ N _ N _ N _ N _ N _ N _ P _ P _ P _ R _ R _ R _ R _ R _ R _ T _ T _ T _ T _ W _ W _ W _ W _ W _ W _ Y _ Y _ Y _ Y _ Y _ Y _ Y _ Y _ E _ E _ E _ E _ E _ E _ E _ F _ F _ F _ G _ G _ G _ G _ G _ G _ G _ G _ H _ H _ H _ H _ H _ J _ J _ J _ J _ J _ J _ K _ K _ K _ K _ U _ U _ U _ U _ U _ U _ U _ V _ V _ W _ W _ K _ K _ K _ L _ L K _ K _ L _ L _ L _ L _

11 RT VRT.V_LW RV R_VRT RV R K_ RT_RST# JP R K_ N SUY_FGNL S Strap s Intel's review(pr.,,), internal VR must be enabled. INTVRMEN LN_SLP VRT R K/F Low = Internal VR disable High = Internal VR enable(efault) IH_INTVRMEN U/V RT-TTERY U/V Low = Internal VR disable High = Internal VR enable(efault) VRT R K/F LN_SLP *RT_RST_N () ST_RXN () ST_RXP () ST_TXN () ST_TXP () ST_RXN () ST_RXP () ST_TXN () ST_TXP P/V Y.KHZ P/V VRT s Intel's review(pr.,,), the GLN_OMPO/OMPI connection to.-v rail through the. ohm % remains even if non-intel LN is used. R R./F R M M.V_GLN () Z_SIN T T T () Z_SOUT T T () ST_LE# T P/V_ P/V_ P/V_ P/V_ LK_KX LK_KX RT_RST# IH_INTRUER# IH_INTVRMEN LN_SLP IH_GPIO Z_LK Z_SYN Z_RST# Z_SOUT GPIO# GPIO# ST_LE# ST_TXN_ ST_TXP_ R R ST_TXN_ ST_TXP_ G F F F E H J J E J H H E E G F F F H H G G J J F F E E U RTX RTX RTRST# INTRUER# INTVRMEN LN_SLP GLN_LK LN_RSTSYN LN_RX LN_RX LN_RX LN_TX LN_TX LN_TX GLN_OK#/GPIO GLN_OMPI GLN_OMPO H_IT_LK H_SYN H_RST# H_SIN H_SIN H_SIN H_SIN H_SOUT H_OK_EN#/GPIO H_OK_RST#/GPIO STLE# STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP IH LN / GLN RT IE PU LP ST FWH/L FWH/L FWH/L FWH/L FWH/LFRME# LRQ# LRQ#/GPIO GTE M# PRSTP# PSLP# FERR# PUPWRG/GPIO IGNNE# INIT# INTR RIN# NMI SMI# STPLK# THRMTRIP# TP S# S# E F G F G E F G F E G F E H G E V U V T V T T T R T V V U V U Y Y LRQ# IH_GPIO GTE H_PRSTP#_R H_PSLP#_R H_PWRG_R RIN# H_THERMTRIP_R IH_TP P P P P P P P P P P P P P P P P P P P L (,) L (,) L (,) L (,) LFRME# (,) T T GTE () H_M# () R _ R _ R _ R H_IGNNE# () H_INIT# () H_INTR () RIN# () H_NMI () H_SMI# () H_STPLK# () /F_ T P[:] () P[:] () PS# () PS# () R *./F_N.V_VP R *./F_N H_PWRG ().V_VP R./F_ R IH_PRSTP# (,,) H_PSLP# () Placement close S L<" *_N.V_VP R./F_ PM_THRMTRIP# (,) H_FERR# () H () IT_LK_UIO () Z_SYN_UIO R _ Z_LK R _ Z_SYN () LK_PIE_ST# () LK_PIE_ST R <check list> L<mils./F_ ST_IS ST_LKN ST_LKP G STRIS# G STRIS IHM REV. IOR# IOW# K# IEIRQ IORY REQ W W Y Y Y W PIOR# () PIOW# () PK# () IRQ () PIORY () PREQ () () Z_RST#_UIO () Z_SOUT_UIO R _ R _ Z_RST# Z_SOUT lose to S,Length <.".V_RUN RIN# GTE R *K N R.K_ QUNT OMPUTER IHM Host(/) Size ocument Number Rev MX ate: Friday, October, Sheet of

12 S-PIE/US/MI S-PI NEW R WLN ROSON GLN () PIE_RXN () PIE_RXP () PIE_TXN () PIE_TXP () PIE_RXN () PIE_RXP () PIE_TXN () PIE_TXP () PIE_RXN () PIE_RXP () PIE_TXN () PIE_TXP () PIE_RXN () PIE_RXP () PIE_TXN () PIE_TXP () GLN_RXN () GLN_RXP () GLN_TXN () GLN_TXP.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_ () US_O_# () US_O# () N_EN# PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ GLN_TXN_S GLN_TXP_S US_O_# US_O# O# O# O# O# N_EN# O# O# U P PERN P PERP N PETN N PETP M PERN M PERP L PETN L PETP K PERN K PERP J PETN J PETP H PERN H PERP G PETN G PETP F PERN F PERP E PETN E PETP PERN/GLN_RXN PERP/GLN_RXP PETN/GLN_TXN PETP/GLN_TXP SPI_LK SPI_S# E SPI_S# SPI_MOSI F SPI_MISO J O# G O#/GPIO G O#/GPIO E O#/GPIO F O#/GPIO G O#/GPIO O#/GPIO J O#/GPIO O# H O# IHM REV. PI-Express irect Media Interface SPI US MIRXN V MIRXP V MITXN U MITXP U MIRXN Y MIRXP Y MITXN W MITXP W MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MI_LKN T MI_LKP T MI_ZOMP Y MI_IROMP Y USPN G USPP G USPN H USPP H USPN H USPP H USPN J USPP J USPN K USPP K USPN K USPP K USPN L USPP L USPN M USPP M USPN M USPP M USPN N USPP N USRIS# F USRIS F USP- USP US_RIS_PN <R>.US_RIS_PN<mils.void routing next to clock/high speed signals MI_RXN () MI_RXP () MI_TXN () MI_TXP () MI_RXN () MI_RXP () MI_TXN () MI_TXP () MI_RXN () MI_RXP () MI_TXN () MI_TXP () MI_RXN () MI_RXP () MI_TXN () MI_TXP () LK_PIE_IH# () LK_PIE_IH () MI_IROMP_R.V_RUN USP- () USP () US USP- () USP () US USP- () USP () US USP- () USP () EL USP- () USP () LUETOOTH USP- () USP () NEW R USP- () USP () MINI PIE USP- () USP () USP- () USP () Wireless US T T R./F R./F_ (,) [..] <R> MI_IROMP_R<mils ard Reader MINI PI () INT# () INT# () INT# INT# INT# INT# INT# U E E G F E E E E PI Interrupt I/F F PIRQ# PIRQ# PIRQ# PIRQ# IHM REV. REQ# GNT# REQ#/GPIO E GNT#/GPIO REQ#/GPIO GNT#/GPIO F REQ#/GPIO GNT#/GPIO GNT# REQ# GNT# REQ# GNT# REQ# GNT# REQ# GNT# IRY# EVSEL# PERR# LOK# SERR# STOP# TRY# FRME# YI YI INTG# INTH# SWP Override strap PI_GNT# PI Pull-Up /E# /E# E /E# F /E# E IRY# PR PIRST# G EVSEL# PERR# PLOK# SERR# F STOP# TRY# FRME# PLTRST# PILK PME# PIRQE#/GPIO F PIRQF#/GPIO G PIRQG#/GPIO F PIRQH#/GPIO R G PLT_RST-R# PLK_IH G Low = swap override enabled High = efault *K_N REQ# () GNT# () ard Reader REQ# () GNT# () MINI PI T T E# (,) E# (,) E# (,) E# (,) IRY# (,) PR (,) PIRST# (,,) EVSEL# (,) PERR# (,) SERR# (,) STOP# (,) TRY# (,) FRME# (,) R PLK_IH () PI_PME# () YI (,) YI () PLTRST#_N () PLK_IH R *_N *P/V_N.V_RUN.V_S O# O# N_EN# US_O_# O# R R RP.KX.K_.K_.V_S.V_S.V_S O# US_O# O# O# U PLT_RST-R# TSHFU.V_RUN.U/V_ R K PLTRST# (,,,,,).V_RUN.V_RUN EVSEL# YI INTG# SERR# TRY# LOK# IRY# PERR# RP.KX RP STOP# REQ# FRME# REQ#.V_RUN YI INT# REQ# INT#.KX.V_RUN RP.V_RUN REQ# INTH# INT# INT#.KX QUNT OMPUTER IHM PIE/PI/US(/) Size ocument Number Rev MX ate: Friday, October, Sheet of

13 S-GPIO s Intel's review(pr.,,), add ohm between SMus & SMLINK to let SMus of IHM work in slave mode. () VR_PWRG_K#.V_RUN () MH_IH_SYN# SM_LK_ME SM_T_ME R <FE> R STP_PI# PU is no stuff. R STP_PU# always keeps high to ensure ME alive in M state. (LK_MH_LK/# must keep alive to make ME work) I think there will be update for this design, I suggest you to keep PU and isolation resistors for this signal. R NSZ () KSMI# (,) LI_HLL_EN# (,) YINS# R *K N R _.V_RUN PLK_SM PT_SM (,,) PLK_SM (,,) PT_SM T.V_RUN T () SYS_RST# R R () PM_MUSY# *K_N *K_N R () PM_STPPI# R () PM_STPPU#.V_RUN (,,) LKRUN#.U/V_ (,,,,) PIE_WKE# U (,,) SERIRQ () THERM_LERT_S# add for RST_Y#.U/V U TSHFU RST_Y#_R () RST_Y# T HH-PT HH-PT T HH-PT () SI# RST_Y#_R <check list> internal P T () STLKREQ# T T () PSPK PLK_SM PT_SM L_RST# SM_LK_ME SM_T_ME RI# LP_P# SYS_RST# SM_LERT# PM_STPPI_IH# PM_STPPU_IH# LKRUN# PIE_WKE# SERIRQ VR_PWRG_LKEN TP KSMI#_IH LI#_IH IH_GPIO SI# YINS#_R OR_I OR_I OR_I OR_I IH_GPIO STLKREQ# IH_GPIO IH_GPIO IH_GPIO PSPK MH_IH_SYN#_R IH_TP U J SMLK SMT G LINKLERT# SMLINK E SMLINK F RI# F SUS_STT#/LPP# SYS_RESET# G MUSY#/GPIO G SMLERT#/GPIO E STP_PI#/GPIO G STP_PU#/GPIO H LKRUN#/GPIO E WKE# F SERIRQ THRM# J VRMPWRG J TP J TH/GPIO J TH/GPIO H TH/GPIO E GPIO GPIO G TH/GPIO H GPIO E GPIO G SLOK/GPIO H QRT_STTE/GPIO QRT_STTE/GPIO G STLKREQ#/GPIO F SLO/GPIO J STOUT/GPIO STOUT/GPIO SPKR J MH_SYN# J TP IHM REV. PLK_SM R SM SYS GPIO ST GPIO locks Power MGT MIS GPIO ontroller Link STGP/GPIO STGP/GPIO STGP/GPIO STGP/GPIO LK LK SUSLK SLP_S# SLP_S# SLP_S# S_STTE#/GPIO PWROK PRSLPVR/GPIO TLOW# PWRTN# LN_RST# RSMRST# K_PWRG LPWROK SLP_M# L_LK L_LK L_T L_T L_VREF L_VREF L_RST# MEM_LE/GPIO ME_E_LERT/GPIO E_ME_LERT/GPIO WOL_EN/GPIO.V_S.K_ J J F G G G G F H E J E H G E E J F E F F H J J J F G R R R R M_IH LKUS_ SLP_S# SLP_S# SLP_S# IH_GPIO IH_PWROK PM_PRSLPVR_R R PM_TLOW#_R PM_LN_ENLE_R PM_RSMRST#_R T L_VREF_S L_VREF_S IH_GPIO IH_GPIO IH_GPIO.K_.K_.K_.K_ T T R R T T T T.V_RUN R _ M_IH () LKUS_ () K_PWRG () MPWROK (,) L_LK () L_T () R /F_ /F_ /F_ NSWON# () R K_ L_RST# () YON# () K_ YI (,) SUS# (,,) SUS# () <FE> Since your PU VRM has no PRSTP# pin, connect PM_PRSLPVR to IMVP is correct.v_s PM_PRSLPVR (,).V_S M_IH.V_RUN LKUS_ If no use internal LN M connect LN_RST# to PLTRST# Use internal LN M connect LN_RST# to RSMRST# should go high no sooner than ms after both VccLN_ and VccLN_ have reached their nominal voltages. R */F N ontroller Link VREF for IMT support only R *.K/F_N *.U/V N lose to S R * N *P N R.K/F R /F_ R * N *P N.U/V_ R K R *_N PT_SM SM_LK_ME SM_T_ME R R R.K_ K_ K_ RI# PIE_WKE# PM_TLOW#_R YINS#_R SI# L_RST# R R R R R R K_ K_.K_ K K_ *K_N.V_S No Reboot strap H_SPKR PSPK KSMI#_IH LI#_IH Low = efault High = No Reboot.V_RUN R *K N R R K_ K_ INTEL FE (/) "dd RSMRST# isolation (important!!! See ww Santa Rosa MoW)" R * N.V_S R SM_LERT# R K_ Q.K_ IH_GPIO R K_ MMT SYS_RST# R K_ PM_RSMRST#_R RSMRST# ().V_RUN XOR hain Entrance Strap INTEL R SHOW IT IH_GPIO R K_ TO IH FROM ur(e) IH_RSV H_SOUT escription R RST_Y#_R R K_ K_ R RSV.V_RUN *K_N SERIRQ R K_ V Z_SOUT () Enter XOR hain IH_GPIO R K_ LKRUN# R.K_ IH_TP IH_GPIO R K_ Normal opration(efault) VR_PWRG_LKEN R K_ R Set PIE port config bit IH_PWROK R K_ V *K_N en_: change I from to for Ramp R.V_RUN.K_.V_RUN.V_RUN.V_RUN.V_RUN.U/V_ oard I I I I I (,,) ELY_VR_PWRGOO ELY_VR_PWRGOO U IH_PWROK EVT R R R R () PWROK_E PWROK_E TSHFU *K N K_ *K N *K N R K_ VT- OR_I OR_I OR_I OR_I QUNT VT- R R R R OMPUTER PVT K_ *K N K_ K_ IHM GPIO(/) Ramp Size ocument Number Rev MX ate: Monday, October, Sheet of

14 VREF_SUS_S.V_MI TP_VSUS IH_ TP_VSUS IH_ TP_VSUS IH_ TP_VSUS IH_ TP_VL IH.V_ TP_VSUS IH_.V_PLL V_VLN TP_VSUS IH_.V_V_PU_IO.V_IH TP_VSUS IH_ VMIPLL_IH TP_VL IH V._US_IH TP_VSUS IH_ VL INT_IH VREF_S.V_VP.V_VP.V_RUN.V_RUN.V_VP.V_RUN.V_RUN.V_S.V_RUN V_RUN V_S.V_RUN.V_RUN.V_RUN.V_RUN.V_RUN.V_RUN.V_RUN.V_RUN.V_S VRT.V_S.V_GLN.V_VP.V_RUN Size ocument Number Rev ate: Sheet of QUNT OMPUTER MX IHM Power(/) Friday, October, Size ocument Number Rev ate: Sheet of QUNT OMPUTER MX IHM Power(/) Friday, October, Size ocument Number Rev ate: Sheet of QUNT OMPUTER MX IHM Power(/) Friday, October, Intel use.uh inductor (u) (m) (m) (m) (m) (.) (m) (m) (m) (m) (m) (m) (m) (m) (m) (m) (m) (.) H=.mm use ap U, as intel "VREF Platform esign Guide Update _.pdf" H= U/V U/V.U/V_.U/V_ R _ R _ T T U/V U/V.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_ T T R _ R _.U/V.U/V L uh_m L uh_m SMKL--F SMKL--F.U/V_.U/V_ R R T T.U/V_.U/V_ T T.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_ U/.V_ U/.V_.U/.V.U/.V R R L FMJHS-T_ L FMJHS-T_.U/V.U/V U/V U/V.U/V.U/V.U/V_.U/V_.U/V_.U/V_ U/V U/V U/V_ U/V_.U/V_.U/V_ T T.U/V_.U/V_ U/.V_ U/.V_ R R R R.U/V_.U/V_ U/.V_ U/.V_.U/V_.U/V_.U/V_.U/V_ SMKL--F SMKL--F U/V_ U/V_ U/V_ U/V_ U/V U/V L UH_ VMN L UH_ VMN.U/V_.U/V_ R _ R _.U/V_.U/V_ *.U N *.U N ORE VGP TX RX IE US ORE PI GLN POWER VP_ORE VPSUS VPUS UF IHM REV. ORE VGP TX RX IE US ORE PI GLN POWER VP_ORE VPSUS VPUS UF IHM REV. VREF[] VREF[] T VREF_SUS G V [] V [] V [] V [] V [] V [] V [] V [] V [] E V [] E V [] E V [] F V [] F V [] G V [] H V [] H V [] J V [] J V [] K V [] K V [] L V [] L V [] L V [] M V [] M V [] N V [] N V [] N V [] P V [] P V [] R V [] R V [] R V [] R V [] T V [] T V [] T V [] T V [] T V [] U V_[] F VMIPLL R V [] E V [] F V [] G V [] H V [] J VSTPLL J V_[] V [] V [] V [] V [] V [] VUSPLL VLN_[] F VLN_[] G V_[] V_[] V_[] V_[] V_[] V_[] E V_[] F V_[] G V_[] L V_[] L V_[] L V_[] L V_[] L V_[] L V_[] M V_[] M V_[] P V_[] P V_[] T V_[] T VLN_[] F VLN_[] G VH VSUSH V_PU_IO[] V_PU_IO[] V_[] V_[] U V_[] V V_[] W V_[] W V_[] W V_[] Y V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] E V_[] E V_[] F VRT VSUS_[] VSUS_[] VSUS_[] VSUS_[] G VSUS_[] H VSUS_[] P VSUS_[] P VSUS_[] VSUS_[] N VSUS_[] P VSUS_[] P VSUS_[] P VSUS_[] P VSUS_[] P VSUS_[] R VSUS_[] R VSUS_[] R V [] V [] V [] V [] V [] G V [] G VSUS_[] J VSUS_[] F V [] F V [] L V [] L V [] M V [] M VSUS_[] V_[] V [] W V_[] U V_[] V V_[] V V_[] V V_[] U V_[] V V_[] V V_[] V VGLN_[] VGLN_[] VGLN_[] VGLN_[] VGLN_[] VGLN_ VGLNPLL V_[] F V_[] V_[] E V_[] VSUS_[] R V [] H VSUS_[] V [] V [] VSUS_[] J V_MI[] E V_MI[] E VL_ G VL_[] G VL_[] F VL_ V [] W V [] V V [] U V [] Y V [] V V [] V R R UE IHM REV. UE IHM REV. [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] E [] E [] E [] E [] [] E [] E [] E [] E [] F [] F [] F [] F [] F [] G [] G [] H [] H [] H [] H [] H [] F [] H [] H [] H [] H [] H [] H [] J [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] E [] E [] E [] E [] F [] E [] F [] F [] F [] G [] E [] G [] G [] G [] G [] G [] G [] G [] H [] H [] H [] H [] H [] J [] J [] J [] J [] J [] J [] K [] K [] K [] K [] K [] L [] L [] L [] L [] L [] L [] L [] M [] M [] M [] M [] M [] M [] M [] M [] M [] M [] N [] N [] N [] N [] N [] N [] N [] N [] N [] N [] N [] N [] N [] N [] P [] P [] P [] P [] P [] P [] P [] P [] P [] R [] R [] R [] R [] R [] R [] R [] R [] R [] R [] T [] T [] T [] T [] T [] T [] T [] U [] U [] U [] U [] U [] U [] U [] U [] U [] U [] U [] V [] V [] V [] V [] W [] W [] W [] Y [] Y [] Y [] _NTF[] _NTF[] _NTF[] _NTF[] _NTF[] H _NTF[] H _NTF[] J _NTF[] J _NTF[] J _NTF[] J _NTF[] _NTF[] [] [] [] [] [] U [] K [] W R _ R _.U/V.U/V U/V_ U/V_ T T.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_

15 M M Q M Q M Q _S _S M Q M QS M QS# M QS# M QS M S# M Q M M WE# M S M QS M QS# M S# M_S# M Q M WE# M_KE M Q PM_EXTTS# M QS M QS# _S _S M_OT M Q M M M QS[:] M S M QS M QS# M Q M Q M_KE M_OT LK_SLK LK_ST M M M S M M M M S M M WE# M M_S# M M M M Q M M QS#[:] M RS# M RS# M S# M S# M M QS M QS# M M M Q PM_EXTTS# M S M RS# M M M Q M Q M QS# M Q M M M QS M Q M M QS M QS# M QS# M QS M M QS# LK_ST M QS M Q M S M_OT M WE# M_S# M Q M M[:] LK_SLK M Q M_S# M Q M Q M Q M Q M S M Q M S# M M M M M Q M Q M Q M M QS M M M QS# M_KE M Q M M M M Q M_OT M M LK_SLK M Q M M[:] LK_ST M Q M QS#[:] M S[:] M_LK M [:] M_S# M Q[:] M Q M WE# M QS[:] M M QS# M M M M M_OT M Q M QS M_LK# M M Q _S M_KE M M M Q M Q M QS# M M M QS M Q M Q M S M QS# M Q M M M Q M Q M_LK M Q M M M M M M M QS M M RS# M_KE M Q M_LK# M Q M Q M S M Q M Q M M M M_S# M Q M Q[:] M Q M_LK M_LK# M Q M Q M Q M M M QS M QS# M_S#[:] M QS# M_LK#[:] M_KE[:] M_OT[:] M_LK[:] M S[:] M Q M QS M Q M_OT M Q M [:] M M M_LK# M_LK M Q M M M M M Q PM_EXTTS# PM_EXTTS# M M M M M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M S# M M RS# M M M M M_KE M S M M M M WE# M_S# M S M M_OT M M_KE M M M S M M M M M M M M RS# M M M S M_OT M_KE M_S# M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q _S _S M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M QS[:] () M M[:] () M Q[:] () M [:] () M QS#[:] () M S[:] () M WE# () M RS# () M S# () M S[:] () M QS#[:] () M [:] () M_OT[:] () M_LK#[:] () M S# () M QS[:] () M_LK[:] () M WE# () LK_SLK () M_S#[:] () M Q[:] () M RS# () M_KE[:] () LK_ST () M M[:] () PM_EXTTS# () PM_EXTTS# ().V_SUS.V_SUS.V_SUS.V_SUS.V_SUS SMR_VTERM SMR_VTERM.V_SUS SMR_VREF SMR_VREF SMR_VREF.V_RUN SMR_VREF.V_RUN SMR_VTERM SMR_VTERM.V_SUS.V_RUN SMR_VREF.V_RUN.V_RUN Size ocument Number Rev ate: Sheet of QUNT OMPUTER MX RII SO-IMM Monday, October, Size ocument Number Rev ate: Sheet of QUNT OMPUTER MX RII SO-IMM Monday, October, Size ocument Number Rev ate: Sheet of QUNT OMPUTER MX RII SO-IMM Monday, October, lose to IMM lose to IMM SO-IMM SMus ddress [] SMus ddress [] SO-IMM H=. H=. en_: change N material P/N from GMKS to GMK U/V_ U/V_ RP X_ RP X_ RP X_ RP X_ RP X_ RP X_.U/V_.U/V_.U/V_.U/V_ RP X_ RP X_ U/V_ U/V_.U/V_.U/V_ R K_ R K_.U/V_.U/V_ RP X_ RP X_ RP X_ RP X_.U/V_.U/V_ P R SRM SO-IMM (P) N R_SOIMM_H._RVS P R SRM SO-IMM (P) N R_SOIMM_H._RVS VREF Q Q QS# QS Q Q Q Q QS# QS Q Q Q Q QS# QS Q Q Q Q M N Q Q KE V N _ V V V /P WE# V S# S# V OT Q Q QS# QS Q Q Q Q Q Q M Q Q Q Q M K K# Q Q Q Q N M Q Q Q Q QS# QS Q Q KE V V V V RS# S# V OT V N Q Q M Q Q Q Q M Q Q Q Q NTEST QS# QS Q Q Q Q M Q Q S SL V(SP) QS# QS Q Q Q Q K K# M Q Q Q Q QS# QS Q Q S S.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_ RP X_ RP X_ RP X_ RP X_ RP X_ RP X_ R *K_N R *K_N.U/V_.U/V_ RP X_ RP X_ RP X_ RP X_.U/V_.U/V_ U/V_ U/V_.U/V_.U/V_ U/V_ U/V_ R _ R _ U/V_ U/V_ RP X_ RP X_.U/V_.U/V_.U/V_.U/V_ U/V_ U/V_ RP X_ RP X_.U/V_.U/V_.U/V_.U/V_ RP X_ RP X_ R *K_N R *K_N.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_ RP X_ RP X_ RP X_ RP X_.U/V_.U/V_.U/V_.U/V_ U/V_ U/V_ U/V_ U/V_ R K_ R K_.U/V_.U/V_.U/V_.U/V_ U/V_ U/V_.U/V_.U/V_.U/V_.U/V_ RP X_ RP X_.U/V_.U/V_ U/V_ U/V_.U/V_.U/V_ RP X_ RP X_.U/V_.U/V_ RP X_ RP X_ RP X_ RP X_ U/V_ U/V_.U/V_.U/V_ RP X_ RP X_.U/V_.U/V_ U/V_ U/V_ P R SRM SO-IMM (P) N R_SOIMM_H_RVS P R SRM SO-IMM (P) N R_SOIMM_H_RVS VREF Q Q QS# QS Q Q Q Q QS# QS Q Q Q Q QS# QS Q Q Q Q M N Q Q KE V N _ V V V /P WE# V S# S# V OT Q Q QS# QS Q Q Q Q Q Q M Q Q Q Q M K K# Q Q Q Q N M Q Q Q Q QS# QS Q Q KE V V V V RS# S# V OT V N Q Q M Q Q Q Q M Q Q Q Q NTEST QS# QS Q Q Q Q M Q Q S SL V(SP) QS# QS Q Q Q Q K K# M Q Q Q Q QS# QS Q Q S S.U/V_.U/V_.U/V_.U/V_ U/V_ U/V_.U/V_.U/V_.U/V_.U/V_ U/V_ U/V_ R K_ R K_ RP X_ RP X_.U/V_.U/V_.U/V_.U/V_.U/V_.U/V_ RP X_ RP X_.U/V_.U/V_.U/V_.U/V_ RP X_ RP X_ RP X_ RP X_ RP X_ RP X_ R _ R _.U/V_.U/V_ U/.V_ U/.V_.U/V_.U/V_ R K_ R K_ U/.V_ U/.V_

16 .V_RUN FS.V_RUN R *K_N R *K_N R *K_N PLK_IH_R.V_RUN R PI/TME (efault).v_run K_V_MIN L LMPGSN ohms@mhz.u/v R *K_N PIN Normal mode Trusted mode () LKUS_ (,) PU_MH_SEL (,) PU_MH_SEL (,) PU_MH_SEL () M_IH () PLK_ () PI_LK_ () PLK_EUG () PI_LK_MINI () LK_REFLK () LK_REFLK# () PLK_IH () K_PWRG PI_LK R PI_LK R = PI/TME, Internal PU K PLK_IH_R = PIF/ITP_SEL, Internal P K PIF/ITP_SEL (PIN) PIN (efault) SRT_ PUT_ITP Hybrid-UM K.U/V PIN SR_ PU_ITP.U/V LKUS_ R L R LMGSN.K M_IH PLK_ PI_LK_ PLK_EUG.U/V PLK_IH.U/V R.K R R R R R RP PR-S- R () LK_SLK () LK_ST U/.V_ K_V_MIN K_V_ K_V_REF LK_XTL_IN LK_XTL_OUT FS FS FS LKREF PLK R PI_LK R PLK_EUG_R FTSEL REFLK REFLK# K_V_MIN PLK_IH_R LK_SLK LK_ST SMus ddress [].MHz Y LK_XTL_IN.MHz P/V U V_SR_ V_SR_ V_SR_ V_SR_ V_PI_ V_PI_ V_PU V_REF XIN XOUT M/FS FS/TEST_MOE REF/FS_TEST_SEL REF PI PI/TME PI PI/FTSEL OTT/M_NSS OT/M_SS V_ PIF/ITP_SEL SLK ST _ LK_XTL_OUT P/V K VTT_PWRG#/P(KPWRG/P#) PI_STP# PU_STP# LK_GPLLREQ# STLKREQ# LOM_LKREQ# NEW_LKREQ# MINILK_REQ# MINILK_REQ# V K_V_ MH_LK PUT_MH RP MH_LK# PU_MH PR-S- PU_LK RP PUT PU_LK# PR-S- PU PUT_ITP/SRT_ T PU_ITP/SR_ T PGMOE PGMOE R *K_N.V_RUN SRT_ SR_ LKREQ# SRT_ SR_ LKREQ# SRT_ SR_ LKREQ# SRT_ SR_ LKREQ# SRT_ SR_ LKREQ# SRT_ SR_ LKREQ# SRT_ SR_ LKREQ# SRT_ SR_ LKREQ# SRT_/STT SR_/ST LKREQ# SRT_/LMT SR_/LM YLFX PIE_MINI PIE_MINI# PIE_IH PIE_IH# PIE_MINI PIE_MINI# PIE_VG PIE_VG# RP PR-S- MINILK_REQ# RP PR-S- PIE_EXPR RP PIE_EXPR# PR-S- NEW_LKREQ# PIE_LOM RP PIE_LOM# PR-S- LOM_LKREQ# MH_GPLL MH_GPLL# RP PR-S- R /F LK_GPLLREQ# PIE_ RP PIE_# PR-S- PIE_ST PIE_ST# R R R R R R REFSSLK REFSSLK#.V_RUN K K K K K K PGMOE RP PR-S- MINILK_REQ# RP PR-S- RP PR-S- STLKREQ# RP PR-S- Populate for Napa platforms only. Internal PU K PGMOE LK mode K (efault) K R *K_N PM_STPPI# () PM_STPPU# () LK_MH_LK () LK_MH_LK# () LK_PU_LK () LK_PU_LK# () PIN LK_PIE_MINI () LK_PIE_MINI# () MINILK_REQ# () LK_PIE_IH () LK_PIE_IH# () LK_PIE_MINI () LK_PIE_MINI# () MINILK_REQ# () LK_MXM () LK_MXM# () LK_PIE_NEW_ () LK_PIE_NEW_# () NEW_LKREQ# () LK_PIE_LOM () LK_PIE_LOM# () LOM_LKREQ# () LK_PIE_GPLL () LK_PIE_GPLL# () LK_GPLLREQ# () LK_PIE_ () LK_PIE_# () LK_PIE_ST () LK_PIE_ST# () STLKREQ# () LK_REFSSLK () LK_REFSSLK# () VTT_PWRG#/P K_PWRG/P# WLN Robson Hybrid-MXM Express ard LOM Hybrid-UM K_V_ R..U/V K_V_MIN L LMPGSN ohms@mhz.u/v.u/v K_V_ R..U/V K_V_REF R.U/V.U/.V U/.V_.U/.V These are for backdrive issue. (,,) PT_SM (,,) PLK_SM.V_RUN Q NW--F R *_N.V_RUN Q RP PR-.K LK_ST LK_SLK FS FS FS PU SR PI FTSEL = PI/FTSEL, Internal P K PI/FTSEL (PIN) = UM = iscrete PIN PIN PIN PIN OTT OT M_NSS M_SS *K_N FTSEL NW--F lock Generator R *_N RSV Size ocument Number Rev MX ate: Friday, October, Sheet of.v_run QUNT OMPUTER /M_T SRT R /M_ SR

17 PWR_SR N N s nvii's review (pr.,,), because of some MXM board have SLI singal through the pin to connection.please reserve one ohm resistor to ground to avoid signal conflict. PWR_SR PWR_SR PWR_SR PWR_SR mp PWR_SR PWR_SR PWR_SR PWR_SR PWR_SR(E).mp V_MXM.mp.mp.mp PWR_SR.V_MXM.V_MXM.V_MXM U/V/.U/V_.U/V_.U/V_.U/V_ R _ U/V_.U/V_ VRUN VRUN VRUN VRUN.V_MXM VRUN VRUN VRUN VRUN VRUN VRUN VRUN VRUN (E) MXM-HE ON *.u N *.u N LK_REQ# PEX_RST# SPIF *.u N PEX_REFLK# PEX_REFLK PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX PRSNT# PRSNT#.U/V_ *.u N PLTRST# LK_MXM# LK_MXM PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PWR_SR.U/V_ PEG_RXN[:] PEG_RXP[:] PEG_TXN[:] PEG_TXP[:] SPIF_MXM () MXM_PRS# () PLTRST# (,,,,,) V_MXM LK_MXM# () LK_MXM () PEG_RXN[:] () PEG_RXP[:] () PEG_TXN[:] () PEG_TXP[:] () PU to.v_lw by E internal PU. (,) THERM_LERT# (,,,) ST_SMT (,,,) ST_SMLK () EV_LVS_ULK# () EV_LVS_ULK () EV_LVS_UTX# () EV_LVS_UTX# () EV_LVS_UTX# () EV_LVS_UTX () EV_LVS_UTX () EV_LVS_UTX () EV_LVS_LLK# () EV_LVS_LLK () EV_LVS_LTX# () EV_LVS_LTX# () EV_LVS_LTX# () EV_LVS_LTX () EV_LVS_LTX () EV_LVS_LTX () EV_LVS_VEN () EV_LVS_LON () EV_LVS_L_RGHT () EV_LVS_LK () EV_LVS_T.V_MXM Q RHUN PWROK_MXM Q NW--F.V_MXM.V_MXM.V_MXM V_LW EV_LVS_ULK# EV_LVS_ULK EV_LVS_UTX# EV_LVS_UTX# EV_LVS_UTX# EV_LVS_UTX EV_LVS_UTX EV_LVS_UTX EV_LVS_LLK# EV_LVS_LLK EV_LVS_LTX# EV_LVS_LTX# EV_LVS_LTX# EV_LVS_LTX EV_LVS_LTX EV_LVS_LTX EV_LVS_VEN EV_LVS_LON EV_LVS_L_RGHT EV_LVS_LK EV_LVS_T s nvii's review(pr.,,), let those pins N is ok,if without TV and RT function. Q RHUN Q RHUN R K MXM_ON# Q NW--F.V_MXM R *K_N R.K_ MXMT R.K_ MXMLK V_LW THERM# R K MXM_ON LVS_ULK# LVS_ULK LVS_UTX#/VI TX# LVS_UTX#/VI TX# LVS_UTX#/VI TX# LVS_UTX# LVS_UTX/VI TX LVS_UTX/VI TX LVS_UTX/VI TX LVS_UTX LVS_LLK#/VI TX# LVS_LLK/VI TX LVS_LTX#/VI TX# LVS_LTX#/VI TX# LVS_LTX#/VI TX# LVS_LTX# LVS_LTX/VI TX LVS_LTX/VI TX LVS_LTX/VI TX LVS_LTX LVS_PPEN LVS_LEN LVS_L_RGHT _LK _T VG_HSYN VG_VSYN VG_RE VG_GREEN VG_LUE _LK _T TV_Y/HTV_Y/TV_VS TV_/HTV_Pr TV_VS/HTV_Pb THERM# SM_T SM_LK MXM-HE ON V_RUN Q V_MXM SIV R _ *P/V_N.U/V/.V_RUN Q.V_MXM SIV R _ *P/V_N.U/V/.V_SUS Q.VMXM SIY-T-E /TT# (efault) R _ U/V_.U/V_ U/V_.U/V_ U/V_.U/V_ MXM *P/V_N.U/V/ Size ocument Number Rev MX ate: Friday, October, Sheet of LVS RT TV VI- VI VI- VI LK# VI LK VI TX# VI TX# VI TX# VI TX VI TX VI TX VI HP _LK _T IGP_RSV/VI LK# IGP_RSV/VI LK IGP_RSV/VI TX# IGP_RSV/VI TX# IGP_RSV/VI TX# IGP_RSV/VI TX IGP_RSV/VI TX IGP_RSV/VI TX VI HP/ IGP_RSV IGP_RSV IGP_RSV IGP_RSV IGP_RSV IGP_RSV IGP_RSV IGP_RSV IGP_RSV IGP_RSV IGP_RSV IGP_RSV IGP_RSV IGP_RSV IGP_RSV RSV RSV RUNPWROK /TT# HMILK- HMILK HMITXN HMITXN HMITXN HMITXP HMITXP HMITXP HMI_HP_ MXM_HMI_LK MXM_HMI_T MXM_PWROK MXM_IN MM_IN = /TT#, Internal P K PIN R _ Q TYU Nominal performance High performance *.U/V N K.VMXM HMILK- () HMILK () HMITXN () HMITXN () HMITXN () HMITXP () HMITXP () HMITXP () HMI_HP_ (,,) MXM_HMI_LK () MXM_HMI_T () PWROK_MXM QUNT OMPUTER.V_MXM Mode attery Mode MXM Hi temperature L K L.U_ R K_ Q NE HIRR-_ HIRR-_ PWROK_MXM (,) MXM_ () MXM_ HI LOW LOW.V_MXM.U_

18 HYRI setting () INT_TXLLKOUT- () INT_TXLLKOUT () INT_TXLOUT- () INT_TXLOUT () INT_TXLOUT- () INT_TXLOUT () INT_TXLOUT- () INT_TXLOUT () EV_LVS_LLK# () EV_LVS_LLK () EV_LVS_LTX# () EV_LVS_LTX () EV_LVS_LTX# () EV_LVS_LTX () EV_LVS_LTX# () EV_LVS_LTX U PIPIE-ZHE V V V V.V_SUS V V V V.V_SUS.U/V_ SEL.U/V_ TXLLKOUT TXLOUT TXLOUT TXLLKOUT- TXLOUT- TXLOUT- TXLOUT- TXLOUT R K.U/V_ R.U/V_ MXM_UM# MXM_UM# () N FOX_GS--F(H.) PWR_SR Q TXULKOUT- FP mil TXULKOUT mil TXUOUT- TXUOUT R TXUOUT- TXUOUT K.U/V_.U/V_ TXUOUT- TXUOUT.V_RUN TXLLKOUT- R TXLLKOUT K TXLOUT- R TXLOUT K TXLOUT- (,,,) MINON Q TXLOUT *HH-PT_N NW--F TXLOUT- E_L_KLT_TRL () TXLOUT *HH-PT_N L_EILK EV_LVS_L_RGHT () L_EIT *HH-PT_N no PST support LVS_VJ L_KLT_TRL () V_LW.V_RUN LV SMUS ddress [] dd : H --ontrast ST_SMLK (,,,) H --acklight ST_SMT (,,,) INV_V *P/V_N *P/V_N L USP_ USP_ USP_- USP_- V_ *PLWSSQT_N L LMPGSN U_MI_IN () R V_MI L LMPGSN U_MI_LK () R P/V P/V INV_V USP () USP- () () INT_TXULKOUT- () INT_TXULKOUT () INT_TXUOUT- () INT_TXUOUT () INT_TXUOUT- () INT_TXUOUT () INT_TXUOUT- () INT_TXUOUT () EV_LVS_ULK# () EV_LVS_ULK () EV_LVS_UTX# () EV_LVS_UTX U V V V V V V V V.U/V_.U/V_.U/V_ TXULKOUT- TXULKOUT TXUOUT- TXUOUT TXUOUT- TXUOUT TXUOUT- TXUOUT.U/V_.V_RUN R *K_N.V_LW V_LW R K.V_RUN LV_ON R *K_N.U/V Q NW--F LV.U/V_ close to L connector LV.U/V_ () EV_LVS_UTX# () EV_LVS_UTX () EV_LVS_UTX# () EV_LVS_UTX PIPIE-ZHE SEL MXM_UM# LV_EN R K Q SIV-T-E U/V_ R.U/V_ Q NW--F R _.U/V.V_RUN V_LW.U/V_.U/V_ Q TEU--F MXM_UM# isplay mode Hybrid-UM Hybrid-MXM K <demo circuit> restline suggest K place close to connector place close to connector.v_run igital MER Power Switch R * N MI power () INT_LVS_EILK () EV_LVS_LK () INT_LVS_EIT () EV_LVS_T () INT_LVS_IGON () EV_LVS_VEN () INT_LVS_LON () EV_LVS_LON.U/V_ V U Y Y Y Y MXM_UM# / G R PIQE K R.K_ R.K_ L_EILK L_EIT LV_EN LVS_LON R E_FPK# ().U/V.U/V.U/V V_RUN U/.V/ESR U/V/ R K R <demo circuit> Q restline K () _POWERON TEU LVS/E-switch//MI suggest K Size ocument Number Rev MX ate: Friday, October, Sheet of Q SIS-T-E U/V/ R K_ V_ U/.V/.V_RUN U/.V/.U/V QUNT OMPUTER V_MI L LMS.U/V U/.V/

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