Merom / Crestline / ICH8-M

Transcription

1 VI ocking(rq) US (US) X LN 0/00/G MOEM udio/spdif JK RT/S-Video Parallel/Serial Port VI Port PS Port * attery harger VI / 0 hrontel PG US PORT X US0~ PG US~ PG Modularity PT O/H UX attery PG PG 0 SVO RII-SOIMM RII / MHz PG, luetooth US ST H US F(US) PG RII / MHz RII-SOIMM PG, FINGER PRINT US PG nd PT ST.KHz Merom ( Micro-FPG) restline PG,,,,,0, IH-M G VIEO RM * FS RII /00 MHz PG, VI bit/m ufg MI LINK X PI-E PG,,, PG, PI-EXPRESS MHz LOK GEN ISLPRS pins FOR restline (L/RT/S-VIEO) zalia PG PU THERML SENSOR PG TI PG,,0,, MHZ,.V PI PI-E M Module. PG.MHz M-s/M-s zalia ST00 WIRE PG L Panel RT S-Video Intel MHz PG N LOK IGRM PG PG PG Merom / restline / IH-M MINI PI-E ard * US US PG MX VGORE (.V/.V).V SYSTEM POWER(/V) PU ORE POWER ISL PG 0.V.0V/.V.VSUS/0.V HRGER MX & SELETER ISHRGE.MHz PG PG PG PG PG PG PG, PG RUS / IEEE ONTROLLER/F PI PG Internal H PG st LP mplifier MX PG SIM ard PG WIRE Smart ard IN R REER S/MM, MS,X RUS SLOT X ONN.KHz WIRE WIRE PG 0 PG 0 PG PG TPM PG IT LQFP PG SIO P PG RJ JK PG JK HEPHONE, N HEPHONE, MI udio oard PG RJ JK PG PI EVIES IRQ ROUTING EVIE ISEL # ardus/ REQ/GNT # 0 PI_INT,,, FN Touchpad Keyboard SPI FLSH PG PG PG PG PROJET : N Quanta omputer Inc.

2 () () () () () ().V_M imt ST_LKREQ# MINILK_REQ# PI_LK_ LK_PI_TPM PLK_LP_EUG LK_PI_IH L LMPG00SN.V () PI_LK_ () PI_LK_SIO PI/TME: PU be used, the K0 cannot over clock any of the clock for Trust Mode security purposes..v 0 0U/.V/XR_ PI/_Select: =MHz,0=SR_00MHz of Pin & Pin..V GLK_SM_M GT_SM_M K_V_MIN PU_LK 0.U/0V_ V IO PU0 0 PU_LK# V_PLL_IO PU0# V_SR_IO_ MH_LK ST_LKREQ# PU 0 MH_LK# MINILK_REQ# V_SR_IO_ PU# V_PU_IO LK_PU_ITP V_SR_IO_ SR/ITP T R 0K_ LK_PU_ITP# PI_LK_ SR#/ITP# T0 R _ STLKREQ#_R MH_GPLL# PI0/R#_ SR0# MH_GPLL R _ MINILK_REQ#_R SR0 PI/R#_ LK_GPLLREQ#_R PLK R SR/R#_H R _ R0 _ MINILK_REQ#_R PI/TME SR#/R#_G R _ R _ PI_LK_ R _ PI_LK R 0 PIE_MINI LK_PI_TPM PI SR R./F_ PIE_MINI# R./F_ FTSEL SR# PI/MHz_Select PELK_VG_R R _ PI_IH SR/R#_F PELK_VG#_R PIF/ITP_EN SR#/R#_E R 0K_@EV PLK_LP_EUG G_XIN 0 PIE_IH XTL_IN SR R0 *0K_@IV 0 PIE_IH# G_XOUT SR# XTL_OUT PIE_MINI FS SR 0 PIE_MINI# US_/FS SR# R LK_PI_IH R K_ PIF/ITP_EN: PU be used, the K0 will be configured to use Pin/ to PU ITP clock.if P be detect at powe-on,the K0 will setting Pin / to SR(efault is setting to SR) 0.U/0V_ K_V_MIN *0K_@N 0.U/0V_.U/0V/XR_ 0.U/0V_ 0.U/0V_ 0.U/0V_ FS.U/0V/XR_ U V_PI V_ V_PLL V_REF V_SR V_PU FS/TEST/MOE REF0/FS/TESTSEL VSS_PI VSS_ VSS_IO VSS_PLL VSS_PU VSS_SR VSS_SR VSS_SR VSS_REF 0 0.U/0V_ lock Gen K0 0.U/0V_ N SLK S PI_STOP# PU_STOP# SR/ST SR#/ST# SR/SE/MHz_NonSS SR#/SE/MHz_SS SR/R#_ SR#/R#_ SR0/OT SR0#/OT# KPWRG/PWRWN# ISLPRSGLFT/SLGSP 0 0.U/0V_ T PIE_ST PIE_ST# REFSSLK_R REFSSLK#_R REFLK_R REFLK#_R K_V_MIN 0 0.U/0V_ 0.U/0V_ 0 0.U/0V_ L LMPG00SN 0U/.V/XR_ GLK_SM_M (,) GT_SM_M (,) RP 0X RP 0X RP 0X LK_GPLLREQ# MINILK_REQ# RP 0X@EV RP 0X@EV UM & iscrete is/enable setting RP 0X RP0 0X RP 0X RP 0X RP *0X@IV RP *0X@IV.V_M imt H_STP_PI# () H_STP_PU# () LK_PU_LK () LK_PU_LK# () LK_MH_LK () LK_MH_LK# () LK_MH_GPLL# () LK_MH_GPLL () LK_GPLLREQ# () MINILK_REQ# () LK_PIE_MINI () LK_PIE_MINI# () LK_PIE_VG () LK_PIE_VG# () LK_PIE_IH () LK_PIE_IH# () LK_PIE_MINI () LK_PIE_MINI# () LK_PIE_ST () LK_PIE_ST# () REF_SSLK () REF_SSLK# () MH_REFLK () MH_REFLK# () LK_VG_M_NSS () LK_VG_M_SS ().V_M (,,,).V (,,,,,,,,,,0,,,,,,,,,,,,) imt (,,0) (,,0) iscrete MINILK_REQ# LK_GPLLREQ# ST_LKREQ# MINILK_REQ# IH_SMT IH_SMLK R R0 R R Q N00W--F Q N00W--F UM & iscrete setting LK iscrete / UM RP 0 N RP N 0 RP N 0 RP 0 N.V_M.V_M.V lock Gen I 0K_ 0K_ 0K_ 0K_ R 0K_ R 0K_ GT_SM_M GLK_SM_M 0 P/0V_ LK_PWRG () XTL length < 00mils Y.MHZ dd capacitor pads for improving WWN. () LK M () LK_IH_M (,) PU_MH_SEL0 (,) PU_MH_SEL (,) PU_MH_SEL () LK_IH_M () LK_SIO_M P/0V_ LK M LK_IH_M LK_IH_M LK_SIO_M R _ R _ R.K_ R00 0K_ R _ R0 _ *P/0V@N LK M *P/0V@N LK_IH_M *P/0V@N LK_SIO_M *P/0V@N LK_IH_M P/0V PI_LK_ *P/0V@N PI_LK_ *P/0V@N PLK_LP_EUG 0 *P/0V@N LK_PI_TPM 0 *P/0V@N LK_PI_IH 0 P/0V_ LK_GPLLREQ# P/0V_ MINILK_REQ# 0 P/0V_ ST_LKREQ# P/0V_ MINILK_REQ# E -0 PU lock select FS FS FS PU SR PI RSV 00 GLK_SEL = FTSEL FTSEL (PIN) PIN PIN PIN PIN 0=UM OTT OT SRT/LT_00 SR/LT_00 = External VG SRT0 SR0 Mout-NSS Mout-SS PROJET : N Quanta omputer Inc. Size ocument Number Rev lock Gen Monday, January, 00 ate: Sheet of

3 () H_#[..] PU(HOST) () H_ST#0 () H_REQ#[0..] () H_#[..] () H_ST# () H_0M# () H_FERR# () H_IGNNE# () H_STPLK# () H_INTR () H_NMI () H_SMI# H_#[..] H_REQ#[0..] H_#[..] H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_REQ#0 H_REQ# H_REQ# H_REQ# H_REQ# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# J L L K M N J N P P L P P R M K H K J L Y U R W U Y U R T T W W Y U V W V U []# []# []# []# []# []# []# [0]# []# []# []# []# []# []# ST[0]# REQ[0]# REQ[]# REQ[]# REQ[]# REQ[]# []# []# []# [0]# []# []# []# []# []# []# []# []# []# [0]# []# []# []# []# []# ST[]# 0M# FERR# IGNNE# R GROUP 0 R GROUP XP/ITP SIGNLS ONTROL S# NR# PRI# EFER# RY# SY# R0# IERR# INIT# LOK# RESET# RS[0]# RS[]# RS[]# TRY# HIT# HITM# PM[0]# PM[]# PM[]# PM[]# PRY# PREQ# TK TI TO TMS TRST# R# THERML PROHOT# THERM THERM IH THERMTRIP# STPLK# LINT0 H LK LINT LK[0] SMI# LK[] H E G H F E F 0 H F F G G G E 0 H_IERR# H_RESET# ITP_PM#0 ITP_PM# ITP_PM# ITP_PM# ITP_PM# ITP_PM# ITP_TK ITP_TI ITP_TO ITP_TMS ITP_TRST# ITP_RESET# H_PROHOT# H_THERM H_THERM R H_THERMTRIP_R# T T T T0 T T R0 _ R./F_ R 0_ LK_PU_LK () LK_PU_LK# () H_S# () H_NR# () H_PRI# () H_EFER# () H_RY# () H_SY# () H_R0# ().0V_VP H_INIT# () H_LOK# () H_RESET# () H_RS#0 () H_RS# () H_RS# () H_TRY# () H_HIT# () H_HITM# () ITP_RESET# () *./F_@N.0V_VP R *0@N.0V_VP H_THERMTRIP# (,).0V_VP <check list> efault PU ohm if no use.serial R N If connect to power side PU ohm. Q *MMST0--F@N IMVP_PROHOT# (0) () PU Thermal monitor () () (,,) (,,) () THLK_SM THT_SM LK T THERM_LERT# SYS_SHN# Q N00W--F LK Q0 N00W--F T Q N00W--F.V.V.V V THLK_SM THT_SM OVERT# PU FN 0 mil 0U/0V/XR_ R.V R 0K_ R 0K_ Routing 0:0 mils and away from noise source with ground gard R VFN PY00T-00Y-N-_ R0 0K_ *0_@N 0.U/0V_ R 0_ R *0K_@N U0 SLK S LERT# OVERT# GP RESS: H N FN V V XP XN GN 0.U/0V_ H_THERM 00P/0V_ H_THERM M N T V F RSV[0] RSV[0] RSV[0] RSV[0] RSV[0] RSV[0] RSV[0] RSV[0] RSV[0] RSV[0] RESERVE () () PWM_FN FNSIG.V R.K_ 000P/V_ 000P/V_ () () () () ().0V_VP H_#[0..] H_STN#0 H_STP#0 H_INV#0 H_#[0..] () () () (,) (,) (,) H_STN# H_STP# H_INV# PU_MH_SEL0 PU_MH_SEL PU_MH_SEL H_#[0..] H_#[0..] Place voltage divider within 0." of GTLREF pin R K/F_ R K/F_ T R R0 T R *K_@N *K_@N *0.U/0V_@N *0_@N H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_GTLREF PU_TEST PU_TEST PU_TEST PU_TEST PU_TEST PU_TEST E F E G F G E E K G J J H F K H J H H N K P R L M L M P P P T R L T N L M N F F Place close to the PU_TEST pin. Make sure PU_TEST routing is reference to GN and away from other noisy signal. Merom all-out Rev a U [0]# []# []# []# []# []# []# []# []# []# [0]# []# []# []# []# []# STN[0]# STP[0]# INV[0]# []# []# []# []# [0]# []# []# []# []# []# []# []# []# []# [0]# []# STN[]# STP[]# INV[]# GTLREF TEST TEST TEST TEST TEST TEST SEL[0] SEL[] SEL[] T GRP T GRP 0 MIS T GRP T GRP []# []# []# []# []# []# []# []# [0]# []# []# []# []# []# []# []# STN[]# STP[]# INV[]# []# []# [0]# []# []# []# []# []# []# []# []# []# [0]# []# []# []# STN[]# STP[]# INV[]# OMP[0] OMP[] OMP[] OMP[] PRSTP# PSLP# PWR# PWRGOO SLP# PSI# Y V V V T U U Y W Y W W Y U E 0 E F E F E F 0 R U Y E E Merom all-out Rev a H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# OMP0 OMP OMP OMP H_#[0..] H_#[0..] R R R0 R H_#[0..] () H_STN# () H_STP# () H_INV# () H_#[0..] () omp0, connect with Zo=.ohm,omp, connect with Zo=ohm, make those traces length shorter than 0.".Trace should be at least mils away from any other toggling signal. H_STN# () H_STP# () H_INV# ()./F_./F_./F_./F_ H_PRSTP# (,,0) H_PSLP# () H_PWR# () H_PWRGOO () H_PUSLP# () H_PSI# (0) RV V-PORT-00-0K-V0 RV V-PORT-00-0K-V0 IH_PRSTP# need to daisy chain from IH to IMVP to PU. Populate ITP00Flex for bringup H_RESET# ITP_TK ITP_TMS ITP_TI ITP_TO ITP_TRST# ITP_RESET# E -0 R0 R0 R0 R R0 R0.0V_VP */F_@N /F_ 0/F_ R0 _ /F_ /F_.V_S 0/F_ Signal TI TMS TRST# TK TO RESET# Resistor Value 0 ohm ± % ohm ± % 00 to 0 ohm ± % ohm ± % ohm ± %. ohm ± % series resistor and pullup ohm ± %. ITP00 layout guidelines onnect To VP VP GN GN VP VP Resistor Placement Place the pull-up near PU Within 00ps of ITP connector Place the pull-up near PU onnect to TK pin of PU and then connect it to FO pin of ITP connector in daisy chain. Place the pull-down near TK0 pin of ITP connector Place the pull-up near PU onnect to PURST# pin of GMH through the series resistor placed within 00ps of ITP connector. Place the pull-up after the series resistor from ITP connector. PROJET : N Quanta omputer Inc.

4 PU(Power) ll use 0U V(-0%,XS,00)Pb-Free. V_ORE U/V/XS_ 0U/V/XS_ 0U/V/XS_ 0U/V/XS_ V_ORE 0 0 0U/V/XS_ 0U/V/XS_ 0U/V/XS_ 0U/V/XS_ inside cavity, north side, secondary layer. V_ORE U/V/XS_ 0U/V/XS_ 0U/V/XS_ 0U/V/XS_ V_ORE 0 0 0U/V/XS_ 0U/V/XS_ 0U/V/XS_ 0U/V/XS_ inside cavity, south side, secondary layer. V_ORE 0 0U/V/XS_ 0U/V/XS_ 0U/V/XS_ 0U/V/XS_ inside cavity, north side, primary layer. V_ORE 0 0U/V/XS_ 0U/V/XS_ 0U/V/XS_ 0U/V/XS_ inside cavity, south side, primary layer. 00 0U/V/XS_ 0U/V/XS_ 0 0U/V/XS_ 0U/V/XS_ 0U/V/XS_ 0U/V/XS_ 0 0U/V/XS_ 0U/V/XS_ V_ORE U 0 V[00] V[0] V[00] V[0] 0 V[00] V[00] V[00] V[0] V[00] V[0] V[00] V[0] V[00] V[0] V[00] V[0] 0 V[00] V[0] V[00] V[0] V[0] V[0] 0 0 V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] 0 E V[0] V[0] E0 V[0] V[0] 0 E V[00] V[0] E V[0] V[0] E V[0] V[0] E V[0] V[00] E V[0] V[0] E0 V[0] V[0] F V[0] V[0] 0 F0 V[0] V[0] F V[0] V[0] F V[0] V[0] F V[00] V[0] F V[0] V[0] F V[0] V[0] E F0 V[0] V[00] E V[0] E0 G V[0] VP[0] E V V[0] VP[0] E J V[0] VP[0] E K V[0] VP[0] E M V[0] VP[0] E J V[00] VP[0] E0 K V[0] VP[0] F M V[0] VP[0] F N V[0] VP[0] F0 N V[0] VP[0] F R V[0] VP[] F R V[0] VP[] F T V[0] VP[] F T V[0] VP[] F V V[0] VP[] F0 W V[00] VP[] V[0] V[0] V[0] 0 V[0] V[0] V[0] V[0] VI[0] F V[0] VI[] E V[0] VI[] F V[0] VI[] 0 E V[0] VI[] F V[00] VI[] 0 E V[0] VI[] 0 V[0] V[0] V[0] VSENSE F V[0] V[0] V[0] VSSSENSE E Merom all-out Rev a. <REV.NO. 0./REF.NO.> Ivcc Max Ivccp Max (VP supply before Vcc stable) Max (VP supply after Vcc stable) Ivcca Max 0m.0V_VP 0.U/0V_ VI0 (0) VI (0) VI (0) VI (0) VI (0) VI (0) VI (0) 0.U/0V_ Route VSENSE and VSSSENSE traces at.ohms and length matched to within mil. Place PU and P within inch of PU. 0.U/0V_ Layout out: Place these inside socket cavity on North side secondary..0v_vp V_ORE 0.U/0V_ 0U/.V/_ 0.0U/V_ R 00/F_ R 00/F_.V 0.U/0V_ 0 0U/.V/XR_ 0.U/0V_ Place near PIN. VSENSE (0) VSSSENSE (0) U VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] F VSS[00] VSS[00] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[00] E VSS[0] E VSS[0] E VSS[0] F VSS[0] F VSS[0] F VSS[0] F VSS[0] F VSS[0] F VSS[0] F VSS[00] F VSS[0] F VSS[0] G VSS[0] G VSS[0] G VSS[0] G VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[00] J VSS[0] J VSS[0] J VSS[0] J VSS[0] K VSS[0] K VSS[0] K VSS[0] K VSS[0] L VSS[0] L VSS[00] L VSS[0] L VSS[0] M VSS[0] M VSS[0] M VSS[0] M VSS[0] N VSS[0] N VSS[0] N VSS[0] N VSS[00] P VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] P P P R R R R T T T T U U U U V V V V W W W W Y Y Y Y E E E E E E E E E F F F F F F F F Merom all-out Rev a. PROJET : N Quanta omputer Inc.

5 N(HOST) R./F_ R /F_ R 00/F_.0V_VP H_SWING.0V_VP R./F_ R0./F_ 0.U/0V_ H_SOMP H_SOMP# H_ROMP.0V_VP R K/F_ R K/F_ () () () 0.U close to Impedance ohm H_#[0..] 0:0 mils(width:spacing) 0.U/0V_ H_RESET# H_PUSLP# H_REF H_#[0..] Place the 0. uf decoupling capacitor within 00 mils from GMH pins. H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_SWING H_ROMP H_SOMP H_SOMP# U E H_#_0 G H_#_ G H_#_ M H_#_ H H_#_ H H_#_ G H_#_ F H_#_ N H_#_ H H_#_ M0 H_#_0 N H_#_ N H_#_ H H_#_ P H_#_ K H_#_ M H_#_ W0 H_#_ Y H_#_ V H_#_ M H_#_0 J H_#_ N H_#_ N H_#_ W H_#_ W H_#_ N H_#_ Y H_#_ Y H_#_ P H_#_ W H_#_0 N H_#_ H_#_ E H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ Y H_#_ H_#_ E H_#_ H_#_ G H_#_ J H_#_ H H_#_ J H_#_0 E H_#_ E H_#_ H H_#_ J H_#_ H H_#_ J H_#_ E H_#_ J H_#_ J H_#_ E H_#_0 J H_#_ H H_#_ H H_#_ H_SWING H_ROMP W H_SOMP W H_SOMP# H_PURST# E H_PUSLP# H_VREF H_VREF RESTLINE_p0@MV HOST H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_S# H_ST#_0 H_ST#_ H_NR# H_PRI# H_REQ# H_EFER# H_SY# HPLL_LK HPLL_LK# H_PWR# H_RY# H_HIT# H_HITM# H_LOK# H_TRY# H_INV#_0 H_INV#_ H_INV#_ H_INV#_ H_STN#_0 H_STN#_ H_STN#_ H_STN#_ H_STP#_0 H_STP#_ H_STP#_ H_STP#_ H_REQ#_0 H_REQ#_ H_REQ#_ H_REQ#_ H_REQ#_ H_RS#_0 H_RS#_ H_RS#_ J M F L G K L J K P R H0 L M N J E E N G H G0 E F 0 M M H K E G0 K L E M K H L K J0 M E H E H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_#[..] H_#[..] () H_S# () H_ST#0 () H_ST# () H_NR# () H_PRI# () H_R0# () H_EFER# () H_SY# () LK_MH_LK () LK_MH_LK# () H_PWR# () H_RY# () H_HIT# () H_HITM# () H_LOK# () H_TRY# () H_INV#0 () H_INV# () H_INV# () H_INV# () H_STN#0 () H_STN# () H_STN# () H_STN# () H_STP#0 () H_STP# () H_STP# () H_STP# () H_REQ#0 () H_REQ# () H_REQ# () H_REQ# () H_REQ# () H_RS#0 () H_RS# () H_RS# () PROJET : N Quanta omputer Inc.

6 (,) (,) (,) () (,,0) (,) () (,0) () (,) (,0) R.0K/F_ R K/F_ PU_MH_SEL0 PU_MH_SEL PU_MH_SEL () () () () () () ().V_SUS.V R.0V_VP K/F_ SM_ROMP_VOH SM_ROMP_VOL R MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_0 PM_MUSY# H_PRSTP# PM_EXTTS#0 PM_EXTTS# ELY_VR_PG PLTRST#_N H_THERMTRIP# PM_PRSLPVR H0 J0 K F H0 Santa Rosa Platform MOW WW K For Gb RM support, J F change Pin-J to R M, G change Pin-E to R M. R 0.0U/V_ R 0.0U/V_ (,) (,) THRMTRIP#_GMH R M R M RESTLINE new pin define 0K_ 0K_ RV V-PORT-00-0K-V0.U/.V/XR_.U/.V/XR_ PM_EXTTS#0 PM_EXTTS# THRMTRIP#_GMH *./F_@N T T T T T T T T T0 T T R 0_ R 00_ R 0_ R 0_ T T T T T T T T T T T T0 T T T T0 T T REF_SSLK REF_SSLK# MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_0 MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_REFLK MH_REFLK# G L PM_EXTTS#0 L PM_EXTTS# J W PLTRST#_R V0 THRMTRIP#_GMH N0 PM_PRSLPVR_GMH G UM & iscrete setting TP_N J TP_N K TP_N K0 TP_N L0 TP_N L TP_N L TP_N L TP_N K TP_N J TP_N0 E TP_N TP_N TP_N 0 TP_N 0 TP_N TP_N K R R R R0 P P R N R R M N J R M L M 0 J E H W0 K0 P N N F N G J0 0 R L J E E0 K M0 M L N L U RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV FG_0 FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_0 FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_0 PM_M_USY# PM_PRSTP# PM_EXT_TS#_0 PM_EXT_TS#_ PWROK RSTIN# THERMTRIP# PRSLPVR N_ N_ N_ N_ N_ N_ N_ N_ N_ N_0 N_ N_ N_ N_ N_ N_ RESTLINE_p0@MV 0_@EV.K_@EV 0_@EV.K_@EV iscrete REFLK/ REFLK# 0 iscrete REFSSLK/ REFSSLK# 0 UM REFLK/ REFLK# N iscrete REFSSLK/ REFSSLK# N RSV R MUXING LK FG MI GRPHIS VI PM ME N MIS SM_K_0 SM_K_ SM_K_ SM_K_ SM_K#_0 SM_K#_ SM_K#_ SM_K#_ SM_KE_0 SM_KE_ SM_KE_ SM_KE_ SM_S#_0 SM_S#_ SM_S#_ SM_S#_ SM_OT_0 SM_OT_ SM_OT_ SM_OT_ SM_ROMP SM_ROMP# SM_ROMP_VOH SM_ROMP_VOL SM_VREF_0 SM_VREF_ PLL_REF_LK PLL_REF_LK# PLL_REF_SSLK PLL_REF_SSLK# PEG_LK PEG_LK# MI_RXN_0 MI_RXN_ MI_RXN_ MI_RXN_ MI_RXP_0 MI_RXP_ MI_RXP_ MI_RXP_ MI_TXN_0 MI_TXN_ MI_TXN_ MI_TXN_ MI_TXP_0 MI_TXP_ MI_TXP_ MI_TXP_ GFX_VI_0 GFX_VI_ GFX_VI_ GFX_VI_ GFX_VR_EN L_LK L_T L_PWROK L_RST# L_VREF SVO_TRL_LK SVO_TRL_T LK_REQ# IH_SYN# TEST_ TEST_.0V_VP E -0.0V_VP V V W0 W W E Y G G0 K G E H J J E L K K L R W H H K K N J N N M J N N J J M0 M J J M M E E M K0 T N M0 H K G G0 R SMROMPP SMROMPN SM_ROMP_VOH SM_ROMP_VOL MH_REFLK MH_REFLK# REF_SSLK REF_SSLK# MH_LVREF SVO_TRLLK SVO_TRLT GMH_TEST GMH_TEST SVO_TRLLK SVO_TRLT M_LK_R0 () M_LK_R () M_LK_R () M_LK_R () M_LK_R#0 () M_LK_R# () M_LK_R# () M_LK_R# () R_KE0_IMM (,) R_KE_IMM (,) R_KE_IMM (,) R_KE_IMM (,) R_S0_IMM# (,) R_S_IMM# (,) R_S_IMM# (,) R_S_IMM# (,) M_OT0 (,) M_OT (,) M_OT (,) M_OT (,) T T T0 T T iscrete 0 UM N (,,) () () V_R_MH_REF (,) V_R_MH_REF.U/0V/0.U/0V/0 R R MH_REFLK () MH_REFLK# () REF_SSLK () REF_SSLK# () LK_MH_GPLL () LK_MH_GPLL# () MI_MRX_ITX_N0 () MI_MRX_ITX_N () MI_MRX_ITX_N () MI_MRX_ITX_N () MI_MRX_ITX_P0 () MI_MRX_ITX_P () MI_MRX_ITX_P () MI_MRX_ITX_P () MI_MTX_IRX_N0 () MI_MTX_IRX_N () MI_MTX_IRX_N () MI_MTX_IRX_N () MI_MTX_IRX_P0 () MI_MTX_IRX_P () MI_MTX_IRX_P () MI_MTX_IRX_P () () ().V_M 0_@EV 0_@EV L_LK0 () L_T0 () IH_L_PWROK (,) IH_L_RST0# () SVO_TRLLK () SVO_TRLT () LK_GPLLREQ# () MH_IH_SYN# () INT KLT_TRL INT_LVS_LON R00 *0K_@IV L_TRL_LK.V R0 *0K_@IV L_TRL_T INT_LVS_EILK () INT_LVS_EILK INT_LVS_EIT () INT_LVS_EIT () INT_LVS_IGON.V_SUS INT_HSYN INT_VSYN HSYN/VSYN serial R place close to N R0 0_ R 0K_ R L_TRL_LK LVS iscrete / UM R0 L_TRL_T R00/R0 N 0K UM & iscrete setting R/R0 0 N LVS iscrete / UM R0 N.K R0 N 0 () () () () () () () () () () () () () () () () () () INT_TXLLKOUT- INT_TXLLKOUT INT_TXULKOUT- INT_TXULKOUT INT_TXLOUT0- INT_TXLOUT- INT_TXLOUT- INT_TXLOUT0 INT_TXLOUT INT_TXLOUT INT_TXUOUT0- INT_TXUOUT- INT_TXUOUT- INT_TXUOUT0 INT_TXUOUT INT_TXUOUT () INT_TV_OMP () INT_TV_Y/G () INT_TV_/R UM & iscrete setting.v TV iscrete / UM R/R N.K R/R 0 N () () ().V_M INT_RT_LU INT_RT_GRN INT_RT_RE INT_TV_OMP INT_TV_Y/G INT_TV_/R INT_RT_LU INT_RT_GRN INT_RT_RE LVS_IG TV_ONSEL_0 TV_ONSEL_ INT_RT_LK INT_RT_T INT_RT_LK INT_RT_T R0 *0/F_@IV INT_HSYN R 0_@MV RTIREF R *0/F_@IV INT_VSYN UM & iscrete setting RT iscrete / UM R 0.K/F R0 N 0 R N 0 imt External VG part, Internal VG part. 0_@EV 0_@EV R 0/F_ R 0/F_ 0 0.U/0V_ R R R K/F_ R /F_ R0 R0 *.K_@IV *.K_@IV *.K_@IV *0_@IV R R UM & iscrete setting LVS/RT iscrete / UM R 0 N R0 0 N R 0 N R 0 N INT_RT_LK INT_RT_T INT_LVS_EILK INT_LVS_EIT R R0 R R J0 H E E0 K0 L L N N0 E G E F G0 E0 F G E E G K F J L M P H G K J F E K G F E U UM & iscrete setting RT iscrete / UM R 0 N R 0 N R 0 0 Place 0 ohm R0 0 0 termination resistors R 0 0 close to GMH. R 0 0 R 0 0 R 0 0 R R R R0 R R R R T 0_@EV 0_@EV 0_@EV 0_@EV 0_@MV 0_@MV 0_@MV 0_@MV 0_@MV 0_@MV L_KLT_TRL L_KLT_EN L_TRL_LK L_TRL_T L LK L T L_V_EN LVS_IG LVS_VG LVS_VREFH LVS_VREFL LVS_LK# LVS_LK LVS_LK# LVS_LK LVS_T#_0 LVS_T#_ LVS_T#_ LVS_T_0 LVS_T_ LVS_T_ LVS_T#_0 LVS_T#_ LVS_T#_ LVS_T_0 LVS_T_ LVS_T_ TV_ TV_ TV_ TV_RTN TV_RTN TV_RTN TV_ONSEL_0 TV_ONSEL_ RT_LUE RT_LUE# RT_GREEN RT_GREEN# RT_RE RT_RE# RT LK RT T RT_HSYN RT_TVO_IREF RT_VSYN RESTLINE_p0@MV 0_@EV 0_@EV 0_@EV 0_@EV INT_HSYN INT_VSYN INT_TV_OMP INT_TV_Y/G INT_TV_/R INT_RT_LU INT_RT_GRN INT_RT_RE LVS PI-EXPRESS GRPHIS TV VG PEG_TXN0 PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN0 PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_OMPI PEG_OMPO PEG_RX#_0 PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_0 PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX_0 PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_0 PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_TX#_0 PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_0 PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX_0 PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_0 PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX PEG_TXP0 _PEG_TXN0 _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN PEG_RXP PEG_RXN N M J L N T T0 U0 Y Y0 W 0 G H G G J0 L0 M U T T W W 0 Y H G H G N U U N R0 T Y W W H E H M T T N0 R U W Y Y 0 G E0 H EXP OMPX PEG_RXN0 PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN0 PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXP0 PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP0 PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP _PEG_TXN0 _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN0 _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXP0 _PEG_TXP _PEG_TXP _PEG_TXP _PEG_TXP _PEG_TXP _PEG_TXP _PEG_TXP _PEG_TXP _PEG_TXP _PEG_TXP0 _PEG_TXP _PEG_TXP _PEG_TXP _PEG_TXP _PEG_TXP PEG_TXN[:0] () PEG_TXP0 PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP0 PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP UM & iscrete setting FOR SVO PORT iscrete N () V_PEG UM & iscrete setting UM N *0.U/0V_@IV *0.U/0V_@IV *0.U/0V_@IV *0.U/0V_@IV *0.U/0V_@IV *0.U/0V_@IV *0.U/0V_@IV *0.U/0V_@IV *0.U/0V_@IV *0.U/0V_@IV R./F_ V_PEG PEG_RXN[:0] () PEG_RXP[:0] () 0.U/0V_@EV 0.U/0V_@EV 0.U/0V_@EV 0.U/0V_@EV 0.U/0V_@EV 0.U/0V_@EV 0.U/0V_@EV 0.U/0V_@EV 0.U/0V_@EV 0.U/0V_@EV 0.U/0V_@EV 0.U/0V_@EV 0.U/0V_@EV 0.U/0V_@EV 0.U/0V_@EV 0.U/0V_@EV 0.U/0V_@EV 0.U/0V_@EV 0.U/0V_@EV 0.U/0V_@EV 0.U/0V_@EV 0.U/0V_@EV 0.U/0V_@EV 0.U/0V_@EV 0.U/0V_@EV 0.U/0V_@EV 0.U/0V_@EV 0.U/0V_@EV 0.U/0V_@EV 0.U/0V_@EV 0.U/0V_@EV 0.U/0V_@EV PEG_TXP[:0] () PEG_TXN0 PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN0 PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXP0 PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP0 PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP SVO_R () SVO_R- () SVO_G () SVO_G- () SVO_ () SVO_- () SVO_LK () SVO_LK- () SVO_INT () SVO_INT- () PROJET : N Quanta omputer Inc.

7 N(Memory controller) () R [0..] () R [0..] U UE R 0 R R S0 R 0 R S0 R S0 (,) P Y R S_Q_0 S_S_0 R S R S_Q_0 S_S_0 R S0 (,) W K R S R S (,) R G R S_Q_ S_S_ R S R S_Q_ S_S_ R S (,) F R S R S (,) W0 G R S_Q_ S_S_ R S_Q_ S_S_ R S (,) Y W R S_Q_ R S# R S_Q_ R L R S# R S# (,) N E R S_Q_ S_S# R S_Q_ S_S# R S# (,) R R M[0..] () N0 R S_Q_ R M0 R S_Q_ R M[0..] () T T V0 R0 R M0 R S_Q_ S_M_0 R M R S_Q_ S_M_0 W V R M R S_Q_ S_M_ R M R S_Q_ S_M_ 0 K R M R S_Q_ S_M_ R M R S_Q_ S_M_ F W 0 L R M R 0 S_Q_ S_M_ R M R 0 S_Q_ S_M_ G W H R M R S_Q_0 S_M_ R M R S_Q_0 S_M_ J G E0 J R M R S_Q_ S_M_ R M R S_Q_ S_M_ Y F R M R S_Q_ S_M_ R M R S_Q_ S_M_ G0 N Y W R M R S_Q_ S_M_ R S_Q_ S_M_ H R QS[0..] () F0 R S_Q_ R QS0 R S_Q_ R QS[0..] () E T F T0 R QS0 R S_Q_ S_QS_0 R QS R S_Q_ S_QS_0 W E J0 0 R QS R S_Q_ S_QS_ R QS R S_Q_ S_QS_ E J K R QS R S_Q_ S_QS_ R QS R S_Q_ S_QS_ G J K R QS R S_Q_ S_QS_ R QS R S_Q_ S_QS_ E0 L J R QS R 0 S_Q_ S_QS_ R QS R 0 S_Q_ S_QS_ F H K L R QS R S_Q_0 S_QS_ R QS R S_Q_0 S_QS_ H K E R QS R S_Q_ S_QS_ R QS R S_Q_ S_QS_ G0 P R QS R QS#[0..] () K V R QS#[0..] () R S_Q_ S_QS_ R QS#0 R S_Q_ S_QS_ F0 T K U0 R QS#0 R S_Q_ S_QS#_0 R QS# R S_Q_ S_QS#_0 R0 J 0 R QS# R S_Q_ S_QS#_ R QS# R S_Q_ S_QS#_ W0 L L R QS# R S_Q_ S_QS#_ R QS# R S_Q_ S_QS#_ T J K R QS# R S_Q_ S_QS#_ R QS# R S_Q_ S_QS#_ W J K R QS# R S_Q_ S_QS#_ R QS# R S_Q_ S_QS#_ W H K K R QS# R S_Q_ S_QS#_ R QS# R S_Q_ S_QS#_ Y J0 F R QS# R 0 S_Q_ S_QS#_ R QS# R 0 S_Q_ S_QS#_ V P L V R QS# R S_Q_0 S_QS#_ R S_Q_0 S_QS#_ T R M[0..] (,) K R M[0..] (,) R S_Q_ R M0 R S_Q_ V J K R M0 R S_Q_ S_M_0 R M R S_Q_ S_M_0 T 0 E G R M R S_Q_ S_M_ R M R S_Q_ S_M_ W K K G R M R S_Q_ S_M_ R M R S_Q_ S_M_ V H W R M R S_Q_ S_M_ R M R S_Q_ S_M_ U L F R M R S_Q_ S_M_ R M R S_Q_ S_M_ T K E E R M R S_Q_ S_M_ R M R S_Q_ S_M_ J R M R S_Q_ S_M_ R M R S_Q_ S_M_ J G R M R 0 S_Q_ S_M_ R M R 0 S_Q_ S_M_ E0 L J0 Y R M R S_Q_0 S_M_ R M R S_Q_0 S_M_ 0 L R M R S_Q_ S_M_ R M0 R S_Q_ S_M_ K G R M0 R S_Q_ S_M_0 R M R S_Q_ S_M_0 Y E L E R M R S_Q_ S_M_ R M R S_Q_ S_M_ G0 G0 K R M R S_Q_ S_M_ R M R S_Q_ S_M_ W J K0 G R M R S_Q_ S_M_ R S_Q_ S_M_ J R S_Q_ R S_Q_ J V R RS# R RS# (,) R S_Q_ R RS# R S_Q_ S_RS# R RS# (,) F T R S_Q_ S_RS# E R S_Q_ S_RVEN# Y Y H R 0 S_Q_ S_RVEN# Y0 T R 0 S_Q_ T G R WE# R WE# (,) R S_Q_0 R WE# R S_Q_0 S_WE# T R WE# (,) R S_Q_ S_WE# R S_Q_ Y K R S_Q_ R S_Q_ E R S_Q_ R S_Q_ R R S_Q_ R S_Q_ R J R S_Q_ R S_Q_ R R S_Q_ R S_Q_ N R S_Q_ R S_Q_ M R R S_Q_ R S_Q_ N0 T R 0 S_Q_ R 0 S_Q_ T Y R S_Q_0 R S_Q_0 N Y R S_Q_ R S_Q_ M U R S_Q_ R S_Q_ N S_Q_ T S_Q_ RESTLINE_p0@MV R SYSTEM MEMORY RESTLINE_p0@MV R SYSTEM MEMORY <OrgName> PROJET : N <Orgddr> <Orgddr> <Orgddr> <Orgddr> Quanta omputer Inc. Size ocument Number Rev GMH R/Strap( of ) Monday, January, 00 ate: Sheet of

8 GMH.0V current() Remark V ore V_XG V_X VTT V_PEG V_XM VR_RX_MI SUM 0 0.U/0V_.V_SUS Place 0 where LVS and R taps (. for external GFX ) for integrated Gfx FS VP for PIEG for IMT function MI.0V_VP IVSM supply current channel. channel. 0U/.V_ U/V/XS_ U/V/XS_.0V_VP T T H K J J H H H F R0 U U U V W W Y E E E F F G G G H H H J J J K K K K L U0 R0 T W W Y F F H0 H H H H J0 N UG V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_0 V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_0 V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_0 V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_0 V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_0 V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_0 V_XG_ V_XG_ V_XG_ V_XG_ V ORE POWER V SM V GFX V GFX NTF V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V SM LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF T T T T T T T U U U U U0 U U U V V V V0 V V V Y Y Y Y Y0 Y Y Y Y Y Y F F H H H H J J J K K L L L L0 L L M M M M0 M M P P P P P0 P P P R0 R R R R V V V Y W E W T.0V_VP VSM_LF VSM_LF VSM_LF VSM_LF VSM_LF VSM_LF VSM_LF.0V_VP 0 mils from edge..v Ivcc_XG Graphics core supply current. V_GMH_L *0.U/0V/XR_@IV *U/V/XS_@IV *U/.V/XR_@IV Inside GMH cavity for V_XG. UM & iscrete setting V_XG iscrete / UM R N 0 N N N N N 0U N 0U N 0.U N 0.U N 0.U N U 0 N U External VG part, Internal VG part. 0.U/.V/XR_ R 0_ *0U/.V/_@IV *0U/.V/_@N *0U/.V/_@IV 0.U/0V_ *0.U/0V_@IV 0.U/0V_ 0U/.V_ *0.U/0V_@IV Ivcc (External GFX.0, integrate. ) imt.0v_m E -0 0 mils from edge. *0U/.V/_@N UM & iscrete setting Inside GMH cavity..0v_m (,) Place close to GMH edge..0v_vp Ivcc_XM ontroller supply current 0m 0 U/V/XS_ 0.U/.V/XR_ 0.U/.V/XR_ U/V/XS_ 0.U/.V/XR_ 0.U/0V_ 0 0.U/.V/XR_ 0.U/0V_ HH-0PT 0U/.V/XR_ Inside GMH cavity for V_XG. 0.U/.V/XR_ 0.U/0V_ U/.V/XR_ 0.U/0V_ 0.U/.V/XR_ U/.V/XR_ F F H H H H J J K K K K J M L L P P R R Y Y Y Y Y T0 T T U U U U U U V V V V L L L M M M M M M P P P P L L L R R R UF V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_0 V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ RESTLINE_p0@MV V NTF VSS NTF POWER V XM NTF VSS S V XM VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ VSS_S VSS_S VSS_S VSS_S VSS_S VSS_S V_XM_ V_XM_ V_XM_ V_XM_ V_XM_ V_XM_ V_XM_ T T U U V V F F K M M P P R R R L L imt.0v_m T T K K K J J RESTLINE_p0@MV PROJET : N Quanta omputer Inc.

9 .V.V imt.v_m.v (,,).V L UM & iscrete setting PLL iscrete / UM L N 0uH N 0U 0 0.U L N 0uH N 0U 0 0.U L.V_M *0U/.V_@IV L PLL iscrete / UM UM & iscrete setting L N STUFF 0 N 0U R N 0 0 N N U R N 0 N N 0 0.U R N 0 N N 0 0.U R 0 N R N 0 L0 N 00 R N 0 N N 0 U N 0.U V_TV *nf/p@n *0uH/00m_@IV L0 VQ_TV *00/F_@IV.V (,,,,) imt *0.U/0V_@IV *0uH/00m_@IV *0U/.V_@IV *LMPGSN@IV 0 *0U/.V/XR_@IV L L R 0_ V_MPLL_L U/V/XS_.V_M 0_@MV 0_@MV R *nf/p@n R R *nf/p@n imt 0 *0_@IV.V.V.V.V_M R0 0./F_ IV_TV current U/0V_ LM0S IV_Q current 0.00 R *nf/p@n LM0S U/V/XS_ 0 *nf/p@n 00U/0V_ *0_@IV *0_@IV R R L V_RT *LMPGSN@IV E _@MV 0_@MV *0_@IV 0_@MV R 0_@MV IV G current _@EV *0_@IV R 0.U/0V_ V_TVG *0.0/F_@IV 0.U/0V_ U/V/XS_ R 0_ U/.V/XR_ V_VSYN IV_SYN current 0.0 *0_@IV imt.v UM & iscrete setting LVS iscrete / UM N 000P.V_M.V.V_SUS IV_RT_ current 0.0 IV_PLL~ current 0.0 IV_HPLL current 0.0 IV_MPLL current 0. IV_TV~_ current 0. IV_RT current 0.0 IV/_PEG_PLL current 0. E -0 R 0_@MV R R *nf/p@n *nf/p@n.u/0v/xr_ U/V/XS_ U/.V/XR_ *0_@IV *0_@IV 0.U/0V_ V_RT_R V_TVG_R V_PLL V_PLL V_HPLL V_MPLL IV_LVS current 0.0 V_TX_LVS V_PEG_PLL V_RT V_TV_R VQ_TV_R IV_HPLL current 0. L LMPGSN 0.U/0V_ V.S_PEGPLL_F 0U/.V/XR_ R 0.U/0V_ 0_@MV 0_@MV *U/V/XS_@N R /F_ 0 V_VSYN V_SM_K V_TV_R V_TV_R V_TV_R V_PEG_PLL V_LVS UM & iscrete setting RT iscrete / UM R N 0 R 0 0.U L N STUFF 0 0.U N N R N 0 R N 0.0 R N 0 N N 0 0.U K0 IV_PEG_G current 0.0 K 0 0.U/0V_ IV_LVS current 0. *0_@IV 0_@MV *000P/V_@IV U/.V/XR_ 0.U/0V_ *0U/.V/XR_@N J 0 H L M U W V U U U T T T T T R R M L N N U J H UH VSYN V_RT V_RT V G VSS G V_PLL V_PLL V_HPLL V_MPLL V_LVS VSS_LVS V_PEG_G VSS_PEG_G V_PEG_PLL V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_0 V_SM_ V_SM_NTF_ V_SM_NTF_ V_SM_K_ V_SM_K_ V_TV V_TV V_TV V_TV V_TV V_TV V_RT V_TV V_Q V_HPLL V_PEG_PLL V_LVS_ V_LVS_ RESTLINE_p0@MV If:SVO isabled,v_lvs to GN. If:SVO Enabled,V_LVS to.v. UM & iscrete setting LVS iscrete / UM R N 0 0 U N N External VG part, Internal VG part. RT PLL K SM PEG LVS POWER TV TV/RT LVS X SM K MI VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_NTF XF PEG VTT V_XF_ V_XF_ V_XF_ V_MI V_SM_K_ V_SM_K_ V_SM_K_ V_SM_K_ V_TX_LVS HV V_HV_ V_HV_ V_PEG_ V_PEG_ V_PEG_ V_PEG_ V_PEG_ V_RXR_MI_ V_RXR_MI_ VTTLF VTTLF VTTLF VTTLF V_V_HV E -0 V_V_HV U U U U U U U U U U T T T0 T T T T T T R R R T U U T T T0 R J0 K K J J 0 0 W0 W V V0 H0 H F H.0V_VP V_SM_K V_TX_LVS VTTLF VTTLF VTTLF 0 0.U/.V/XR_ *HH-0PT@N R 0_ V_X IV_HV current 0..0V_VP.V V_V_HV_L () Ivtt_FS core supply current 0..U/0V/XR_ 0 mil wide IV_TX_LVS current 0. V_V_HV V_PEG 0.U/.V/XR_ 0.U/.V/XR_ R *0_@N U/.V/XR_ 0.U/0V_ E -0.U/0V/XR_ *U/V/XS_@N U/.V/XR_ V_PEG 0U/.V/XR_ V_RXR_MI 0.U/.V/XR_ L0 0_ 0 0.U/0V_ 0 0.U/0V_ 0 Ivcc_X current 0. Ivcc_XF current 0. Ivcc_MI current 0. R U/V/XS_ 0U/.V/XR_ Ivcc_SM_K current 0. L 0 0U/.V/XR_ 0_@MV 0.U/.V/XR_ /F_ 0U/.V_ uh/00m_ V._SMK_R L.V_M.V.V.V_M (,,) imt.v (,).V_SUS UM & iscrete setting LVS iscrete / UM L N UH N 0U 0 000P L.V_SUS.0V_VP Ivcc_PEG PI-E current. Ivcc_RX_MI current 0..0V_VP PROJET : N Quanta omputer Inc. Size ocument Number Rev GMH Power-( of ) Monday, January, 00 ate: Sheet of L 0U/.V_ 0U/V_ *uh_@iv *0U/.V_@IV nh/. U/V/XS_ nh/.

10 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : N GMH Power-( of ) 0 Monday, January, 00 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : N GMH Power-( of ) 0 Monday, January, 00 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : N GMH Power-( of ) 0 Monday, January, 00 N(Power-) VSS_ VSS_00 0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 E0 VSS_0 E VSS_ E VSS_ E VSS_ E VSS_ E VSS_ F VSS_ F VSS_ F VSS_ F0 VSS_ F0 VSS_0 G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_0 G VSS_ G VSS_ H VSS_ H VSS_ H VSS_ H VSS_ J VSS_ J VSS_ J VSS_ J VSS_0 J VSS_ J VSS_ J VSS_ J VSS_ K VSS_ K VSS_ K VSS_ L VSS_ L VSS_0 L0 VSS_ L VSS_ L VSS_ L VSS_ L VSS_ L VSS_ M VSS_ M VSS_ M VSS_ M VSS_0 M VSS_ M0 VSS_ M VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_0 N VSS_ N VSS_ N VSS_ P VSS_ P VSS_ P VSS_ P VSS_ P0 VSS_ R VSS_ T VSS_0 T VSS_ T VSS_ U VSS_ U VSS_ U0 VSS_ W VSS_ W VSS_ W VSS_0 W VSS_ W VSS_ W VSS_ Y VSS_ Y VSS_ Y VSS_ V VSS_ V VSS_ Y VSS_ Y VSS_ Y VSS_ Y0 VSS_00 Y VSS_0 P VSS_0 T VSS_0 T VSS_0 T VSS_0 R VSS_0 VSS_0 VSS_0 VSS_0 F VSS_0 F VSS_ T VSS_ V VSS_ H0 VSS UJ RESTLINE_p0@MV VSS UJ RESTLINE_p0@MV VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ 0 VSS_ VSS_0 VSS_ VSS_ VSS_ 0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ 0 VSS_ VSS_0 E0 VSS_ E VSS_ E VSS_ F0 VSS_ F VSS_ F VSS_ F VSS_ G VSS_ G VSS_ G VSS_0 G VSS_ G0 VSS_ H VSS_ H0 VSS_ H VSS_ H VSS_ H VSS_ J VSS_ J VSS_ J VSS_0 J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ K0 VSS_ K VSS_ K VSS_ K VSS_0 K VSS_ K VSS_ L VSS_ M VSS_ M VSS_ M VSS_ M VSS_ M VSS_ M VSS_ N VSS_0 N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ P VSS_ P VSS_ P0 VSS_ R VSS_ R VSS_0 R VSS_ R VSS_ R VSS_ R VSS_ T0 VSS_ T VSS_ T VSS_ T VSS_ W VSS_00 W VSS_0 W VSS_0 W VSS_0 W VSS_0 W VSS_0 Y0 VSS_0 Y VSS_0 Y VSS_0 Y VSS_0 Y VSS_0 Y VSS_ Y VSS_ Y0 VSS_ 0 VSS_ 0 VSS_ VSS_ VSS_ 0 VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ 0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ 0 VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ E VSS_ E VSS_ E VSS_0 E0 VSS_ E VSS_ E VSS_ E VSS_ F VSS_ F VSS_ F VSS_ G VSS_ G VSS_ G VSS_0 G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ H VSS_ H0 VSS_ H VSS_ H VSS_ H VSS_0 J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ K VSS_ K VSS_ K VSS_ K VSS_ U VSS_ U VSS_0 U VSS_ U VSS_ U VSS_ U VSS_ U VSS_ V VSS_ V VSS_ W VSS_ W VSS_0 K VSS_ K VSS_ K VSS_ L VSS_ L VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ K0 VSS_ K VSS_ L VSS_ L VSS_ L VSS_0 L VSS_ VSS_ VSS_ VSS UI RESTLINE_p0@MV VSS UI RESTLINE_p0@MV

11 Strap table ll strap are sampled with respect to the leading edge of the GMH Power OK(PWROK) Signal FG[:] Have internal Pull-up FG[:] Have internal Pull-down ny FG signal strapping option not list below should be left N Pin Pin Name Strap description onfiguration FG[:0] FS Frequency Select 00 = FS 00MHz 0 = FS MHz FG[:] FG MI X Select 0 = MI X = MI X(efault) FG FG PU Strap 0 = = Mobile PU(efault) FG Low power PI Express 0 = Normal mode = Low Power mode FG PI Express Graphics Lane Reversal 0 = Reverse Lanes = Normal operation(efault) FG[:0] FG[:] XOR/LLZ 00 = 0 = XOR Mode Enable 0 = ll-z Mode Enabled = Normal operation(efault) FG[:] FG FS ynamic OT 0 = ynamic OT disable = ynamic OT Enable(efault) FG[:] SVO_TRLT SVO Present 0 = No SVO ard present(efault) = SVO ard Present FG MI Lane Reversal 0 = Normal operation(efault) = Reverse Lanes FG0 SVO/PIe concurrent 0 = Only SVO or PIE x is operation(efault) = SVO and PIE x are operating simultaneously via the PEG port MI X Select MH_FG_ Low = MIX High = IMIX(efault) MI Lane Reversal MH_FG_ Low = Normal operation(efault) High = Reverse Lane XOR /LLz /lock Un-gating MH_FG_ MH_FG_ onfiguration 0 0 lock gating disable PI Express Graphics MH_FG_ Low = Reverse Lane High = Normal operation(efault) SVO Present Strap define at External VI control page () MH_FG_.V 0 XOR Mode Enable () MH_FG_ 0 LL-z Mode Enable R *.0K/F_@N R *.0K/F_@N Normal operation(efault) R *.0K/F_@N FS ynamic OT MH_FG_ Low = OT isable High = OT Enable(efault) () MH_FG_ SVO/PIE oncurrent operation MH_FG_0 Low = Only SVO or PIE X is operational(efault) High = SVO andpie X are operating simultaneously via the PEG port () MH_FG_ () MH_FG_ R *.0K/F_@N R *.0K/F_@N () MH_FG_.V R *.0K/F_@N () MH_FG_0 R *.0K/F_@N Location of all MH_FG strap resistors needs to be close to minmize stub. PROJET : N Quanta omputer Inc.

12 R ual channel / PU 0.V_R_VTT RII HNNEL Layout note: Place cap close to every R-pack terminated to SMR_VTERM. 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.V_R_VTT RII HNNEL 0 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.V_R_VTT 0.V_R_VTT (,) (,) R M[0..] R M[0..] (,) R M R M RP X RP X R M R M R M R M RP X RP X R M R M (,) R RS# (,) R S RP X RP X R RS# (,) R S (,) (,) M_OT0 R M RP X RP X R M M_OT (,) (,) R S R M RP0 X RP X R M R M Please these resistor closely IMM,all trace length<0 mil. R M R M RP X RP X R M R M Please these resistor closely IMM,all trace length<0 mil. R M R M RP X RP X R M R M (,) R S0 R M0 R S0 RP X RP X R M0 R S0 (,) (,) R WE# (,) R S# RP X RP X R WE# (,) R S# (,) R M0 R M RP X RP0 X R M R M0 (,) M_OT (,) R_S0_IMM# (,) R_S_IMM# (,) R_KE0_IMM (,) R_KE_IMM (,) R M R M R _ R0 _ R _ R _ R _ R _ R _ R _ R _ R _ R _ R _ R _ R _ M_OT (,) R S (,) R_S_IMM# (,) R_S_IMM# (,) R_KE_IMM (,) R_KE_IMM (,) R M (,) R Thermal Sensor SO-IMM 0 &.V_M Uninstall.V_M (,,,) (,) GLK_SM_M (,) GT_SM_M (,) PM_EXTTS#0 () PM_EXTTS# R0 *0_@N U SLK V S XP LERT# XN OVERT# GN *LMIMM@N R *0_@N *0.U/0V_@N LM_V R_THERM *00P/0V_@N R_THERM *MMT0_NL@N Q0 PROJET : N Quanta omputer Inc.

13 GT_SM_M GLK_SM_M R M R QS R QS# R R R M R M R M0 R M R 0 R R M R R M R R R M R R R R R QS0 R QS R 0 R R R R R R 0 R R QS#0 R QS R R R R QS# R QS# R QS R QS# R R R R R 0 R R R R 0 R M R R M R M R M R M R M0 R R R QS R R M R QS R QS# R M R M0 R QS# R R M R R R R QS# R M R R R 0 R R R R R R R R R R 0 R R R R R R R M R QS R M R R R R R R R M GLK_SM_M GT_SM_M R M R QS R QS# R R R M R M R M R M0 R R R R M R R R M R R R R R QS0 R QS R 0 R R R R 0 R 0 R 0 R R QS#0 R QS R R R R QS# R QS# R QS R QS# R R R R R R R 0 R R R R M R M R M R 0 R R QS R QS# R R R R R M R M R M R M R M R M R M0 R M R R R M R R R R R QS# R QS R R R R R M R R R R R QS# R QS R R R 0 R R R R M R R R R R M0 R R R [0..] () R M[0..] () R [0..] () R M[0..] () R M (,) R M (,) R M[0..] (,) R M[0..] (,) R_S_IMM# (,) M_OT (,) R S (,) R S# (,) R WE# (,) R S0 (,) R_KE0_IMM (,) R_S0_IMM# (,) R QS#[0..] () R S (,) M_LK_R0 () R RS# (,) R QS[0..] () R_KE_IMM (,) M_LK_R# () M_LK_R () M_OT0 (,) M_LK_R#0 () R_S_IMM# (,) R S (,) M_OT (,) R S# (,) R WE# (,) R S0 (,) R_KE_IMM (,) R QS#[0..] () R QS[0..] () R_S_IMM# (,) R S (,) R RS# (,) R_KE_IMM (,) M_OT (,) M_LK_R () M_LK_R# () M_LK_R# () M_LK_R () PM_EXTTS#0 (,) PM_EXTTS#0 (,) GT_SM_M (,) GLK_SM_M (,) V_R_MH_REF (,).V_M (,,,) V_R_MH_REF.V_M.V_SUS.V_M V_R_MH_REF.V_SUS.V_SUS.V_SUS.V_M V_R_MH_REF.V_SUS.V_SUS V_R_MH_REF.V_M.V_SUS.V_M.V_SUS Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : N R SO-IMM(00P) Monday, January, 00 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : N R SO-IMM(00P) Monday, January, 00 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : N R SO-IMM(00P) Monday, January, 00 LOK 0, LOK, KE, KE 0, H. H. R ual channel / ONN imt imt imt SMbus address 0 is required to route to Top SoIMM for MT to function.this will need to change for M0 Place these aps near So-imm. Place these aps near So-imm. SMbus address imt imt elete 0.U/0V/XR_ 0.U/0V/XR_.U/.V/XR_.U/.V/XR_ 0 0.U/0V_ 0 0.U/0V_ 0.U/0V_ 0.U/0V_.U/.V/XR_.U/.V/XR_.U/.V/XR_.U/.V/XR_.U/.V/XR_.U/.V/XR_ 0.U/.V/XR_ 0.U/.V/XR_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ VREF VSS Q0 Q VSS QS#0 QS0 VSS Q Q VSS Q Q VSS QS# QS VSS Q0 Q VSS0 VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS M N VSS Q Q VSS KE0 V N _ V V 0 V0 0 0/P WE# 0 V S# S# V OT VSS Q Q VSS QS# QS VSS Q Q VSS Q0 Q VSS Q Q VSS M0 0 VSS Q Q VSS Q 0 Q VSS M VSS K0 0 K0# VSS Q Q VSS 0 VSS0 Q0 Q VSS N 0 M VSS Q Q VSS 0 Q Q VSS QS# QS 0 VSS0 Q0 Q VSS KE 0 V V 0 V V 0 0 RS# 0 S0# 0 V OT0 V N 0 VSS Q Q VSS M 0 VSS Q Q VSS Q 0 Q VSS VSS M VSS Q Q VSS0 Q Q VSS NTEST VSS0 QS# QS VSS Q0 Q Q Q VSS M VSS Q Q VSS S SL V(SP) QS# QS VSS 0 Q Q VSS Q Q 0 VSS K K# VSS M 0 VSS Q Q VSS Q0 0 Q VSS QS# QS VSS 0 Q Q VSS S0 S 00 VSS P00 R SRM SO-IMM (00P) N IMM_. P00 R SRM SO-IMM (00P) N IMM_. 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0 0.U/0V_ 0 0.U/0V_.U/.V/XR_.U/.V/XR_ R0 0K_ R0 0K_ 0.U/0V_ 0.U/0V_ R 0K_ R 0K_ 0.U/.V/XR_ 0.U/.V/XR_.U/.V/XR_.U/.V/XR_ VREF VSS Q0 Q VSS QS#0 QS0 VSS Q Q VSS Q Q VSS QS# QS VSS Q0 Q VSS0 VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS M N VSS Q Q VSS KE0 V N _ V V 0 V0 0 0/P WE# 0 V S# S# V OT VSS Q Q VSS QS# QS VSS Q Q VSS Q0 Q VSS Q Q VSS M0 0 VSS Q Q VSS Q 0 Q VSS M VSS K0 0 K0# VSS Q Q VSS 0 VSS0 Q0 Q VSS N 0 M VSS Q Q VSS 0 Q Q VSS QS# QS 0 VSS0 Q0 Q VSS KE 0 V V 0 V V 0 0 RS# 0 S0# 0 V OT0 V N 0 VSS Q Q VSS M 0 VSS Q Q VSS Q 0 Q VSS VSS M VSS Q Q VSS0 Q Q VSS NTEST VSS0 QS# QS VSS Q0 Q Q Q VSS M VSS Q Q VSS S SL V(SP) QS# QS VSS 0 Q Q VSS Q Q 0 VSS K K# VSS M 0 VSS Q Q VSS Q0 0 Q VSS QS# QS VSS 0 Q Q VSS S0 S 00 VSS GN 0 P00 R SRM SO-IMM (00P) N IMM_. P00 R SRM SO-IMM (00P) N IMM_..U/0V/XR_.U/0V/XR_.U/.V/XR_.U/.V/XR_ R 0K_ R 0K_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_.U/.V/XR_.U/.V/XR_ R 0K_ R 0K_ 0 0.U/0V_ 0 0.U/0V_.U/.V/XR_.U/.V/XR_ 0.U/.V/XR_ 0.U/.V/XR_ 0.U/0V_ 0.U/0V_

14 RT RT_ELL S Strap RT_ELL RT_ELL.V_LW VRT_ R K_ V_LW () () () () () () () () IH_Z_M_ITLK IH_Z_OE_ITLK IH_Z_M_SYN IH_Z_OE_SYN IH_Z_M_RST# IH_Z_OE_RST# IH_Z_M_SOUT IH_Z_OE_SOUT () () () () R R.K_ R K_ N0 H0H-0PT H0H-0PT JE-FI-SP-HF.K_ R0 M/F_.V_SUS VRT_ RT_ELL R 00 *0P/0V_@N VRT_ VRT_ R _ R _ R0 _ R _ R0 _ R0 _ R0 _ R0 _ ST_TX0-_ ST_TX0_ ST_TX-_ ST_TX_ Z_IT_LK Z_SYN Z_RST# Z_SOUT Place all series terms close to IH except for SIN input lines,which should be close to source.placement of R, R, R & R should equal distance to the T split trace point as R, R, R & R0 respective. asically,keep the same distance from T for all series termination resistors. 0 R istance between the IH- M and cap on the "P" signal should be identical distance between the IH- M and cap on the "N" signal for same pair. G *SHORT_P K_ 0 00P/V 00P/V 00P/V 00P/V U/0V/XR_ 0K_ *0P/0V_@N U/0V/XR_ Q MMT0_NL R0 *0K_@N.V_S (,) ENERGY_ET.V_PIE_IH.V_PIE_IH.V () () E -0 P/0V_ Y.KHZ () () () () P/0V_ () () () () () () () () () () GLN_LK LN_RSTSYN LN_RX0 LN_RX LN_RX LN_TX0 LN_TX LN_TX ENERGY_ET IH_Z_OE_SIN0 IH_Z_M_SIN T T R () () R *0_@N R R0 ST_RX0- ST_RX0 ST_TX0- ST_TX0 ST_TX- ST_TX ST_RX- ST_RX R 0M_ ST_LE# LK_PIE_ST# LK_PIE_ST R0./F_ 0K_ 0K_ L<00mils IH_RTX IH_RTX RTRST# SM_INTRUER# IH_INTVRMEN LN00_SLP ENERGY_ET GLN_OMP_S Z_IT_LK Z_SYN Z_RST# Z_SIN Z_SIN Z_SOUT GPIO GPIO ST_LE# ST_TX0-_ ST_TX0_ ST_TX-_ ST_TX_ ST_IS IH_INTVRMEN IHM Internal VR Enable Strap (Internal VR for VccSus.0, VccSus., VccL.) IH_INTVRMEN R R./F_ 0K_ 0K_ R0 *0_@N Low = Internal VR isabled High = Internal VR Enabled(efault) G F F F E0 0 H J J E J H H E E0 G F0 F F H H G G J J F F E E G G U RTX RTX RTRST# R K/F_ INTRUER# INTVRMEN LN00_SLP GLN_LK LN_RSTSYN LN_RX0 LN_RX LN_RX LN_TX0 LN_TX LN_TX GLN_OK#/GPIO GLN_OMPI GLN_OMPO H_IT_LK H_SYN H_RST# H_SIN0 H_SIN H_SIN H_SIN H_SOUT H_OK_EN#/GPIO H_OK_RST#/GPIO STLE# ST0RXN ST0RXP ST0TXN ST0TXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP ST_LKN ST_LKP STRIS# STRIS IHM REV.0 IH LN / GLN RT IE PU LP ST LRQ# GTE0 H_PRSTP# H_PSLP# H_FERR# RIN# IH_TP IE_0 IE_ IE_ IE_ IE_ IE_ IE_ IE_ IE_ IE_ IE_0 IE_ IE_ IE_ IE_ IE_ LN00_SLP IHM LN00 SLP Strap (Internal VR for VccLN.0 and VccL.0) IH_LN00_SLP FWH0/L0 FWH/L FWH/L FWH/L FWH/LFRME# LRQ0# LRQ#/GPIO 0GTE 0M# PRSTP# PSLP# FERR# PUPWRG/GPIO IGNNE# INIT# INTR RIN# NMI SMI# STPLK# THRMTRIP# TP S# S# IOR# IOW# K# IEIRQ IORY REQ E F G F G E F G F E G F E 0 H G E V U V T V T T T R T V V U V U Y Y W W Y Y Y W R K/F_ R *0_@N Low = Internal VR isabled High = Internal VR Enabled(efault) T H_THERMTRIP_R T0 IE_[0..] LP_L0 (,,,) LP_L (,,,) LP_L (,,,) LP_L (,,,) LP_LFRME# (,,,) LP_LRQ0# () GTE0 () H_0M# () H_PRSTP# (,,0) H_PSLP# () H_FERR# () H_PWRGOO () H_IGNNE# () H_INIT# () H_INTR () RIN# () H_NMI () H_SMI# () H_STPLK# () R IE_0 () IE_ () IE_ () IE_S# () IE_S# () IE_IOR# () IE_IOW# () IE_K# () IE_IRQ () IE_IORY () IE_REQ ().0V_VP /F_ IE_[0..] () R./F_ R *./F_@N H_PSLP# H_PRSTP# H_FERR# RIN# GTE0.V Placement close S L<" RV V-PORT-00-0K-V0 R *./F_@N.0V_VP R 0K_.V R0./F_ R 0K_ H_THERMTRIP# (,) XOR hain Entrance Strap.V IH_RSV0 H_SOUT escription 0 0 RSV R *K_@N 0 0 Enter XOR hain Normal opration(efault) Set PIE port config bit Z_SOUT R *K_@N IH_RSV () <OrgName> PROJET : N <Orgddr> <Orgddr> <Orgddr> <Orgddr> Quanta omputer Inc. Size ocument Number Rev IHM HOST( of ) Monday, January, 00 ate: Sheet of

15 () () Place TX blocking caps close IH. () () () () 0 E -0 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ () () () () () () (0) (,) (,) IH_SPI_LK IH_SPI_S0# IH_SPI_S# IH_SPI_IN IH_SPI_O US_O0# US_O# PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ GLN_TXN_ GLN_TXP_ WLN_RF_OFF# YINS# () () () () () () MiniWWN PIE_RX-/GLN_RX- PIE_RX/GLN_RX PIE_RX- PIE_RX PIE_RX- PIE_RX MiniWLN PIE_TX- PIE_TX PIE_TX- PIE_TX PIE_TX-/GLN_TX- PIE_TX/GLN_TX Rev: R _ R _ R _ R 0_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ GLN_TXN_ GLN_TXP_ SPI_S#_R US_O0# US_O# US_O# US_O# US_O# US_O# WLN_RF_OFF# YINS# O# O# P P N N M M L L K K J J H H G G F F E E E F J G G E F G J H U PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN/GLN_RXN PERP/GLN_RXP PETN/GLN_TXN PETP/GLN_TXP SPI_LK SPI_S0# SPI_S# SPI_MOSI SPI_MISO O0# O#/GPIO0 O#/GPIO O#/GPIO O#/GPIO O#/GPIO O#/GPIO0 O#/GPIO O# O# PI-Express irect Media Interface SPI US MI0RXN MI0RXP MI0TXN MI0TXP MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MI_LKN MI_LKP MI_ZOMP MI_IROMP USP0N USP0P USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USRIS# USRIS V V U U Y Y W W T T Y Y G G H H H H J J K K K K L L M M M M N N F F US_RIS_PN MI_MTX_IRX_N0 () MI_MTX_IRX_P0 () MI_MRX_ITX_N0 () MI_MRX_ITX_P0 () MI_MTX_IRX_N () MI_MTX_IRX_P () MI_MRX_ITX_N () MI_MRX_ITX_P () MI_MTX_IRX_N () MI_MTX_IRX_P () MI_MRX_ITX_N () MI_MRX_ITX_P () MI_MTX_IRX_N () MI_MTX_IRX_P () MI_MRX_ITX_N () MI_MRX_ITX_P () LK_PIE_IH# () LK_PIE_IH () MI_IROMP_R USP0- () USP0 () USP- () USP () USP- () USP () USP- () USP () USP- (0) USP (0) USP- () USP () USP- () USP () USP- () USP () USP- () USP () USP- () USP () System System System System ocking Y(F).V_PIE_IH Miniard WWN Miniard WWN FINGER PRINT LUETOOTH R./F_ MI_IROMP_R<00mils S-PI.V_S.V_S.V_S imt US_O# US_O0# US_O# O# 0 R R RP 0PR-0K 0K_ 0K_.V_S US_O# O# WLN_RF_OFF# YINS# US_O# US_O# IHM REV.0 IH oot IOS select LP PI SPI SPI_S#_R PI_GNT0# oot IOS Strap 0 0 GNT0# No stuff No stuff Stuff R R0 SPI_S# No stuff Stuff No stuff *K_@N *K_@N R./F_ SWP Override strap PI_GNT# PI_GNT# Short F and F at the package and keep length to less than 00mils. Trace Impedance should be 0ohms /- %. Low = swap override enabled High = efault R0 *K_@N PI Pullups.V () PI_[0..] () () () T PI_PIRQ# PI_PIRQ# PI_PIRQ# ardbus/ ardreader/ Smart ard PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# REQ0 0 E 0 E G 0 F E E E E F 0 GNT0 U PIRQ# PIRQ# PIRQ# PIRQ# PI PIRQ PIRQ PIRQ REQ0# GNT0# REQ#/GPIO0 GNT#/GPIO REQ#/GPIO GNT#/GPIO REQ#/GPIO GNT#/GPIO /E0# /E# /E# /E# IRY# PR PIRST# EVSEL# PERR# PLOK# SERR# STOP# TRY# FRME# PLTRST# PILK PME# Interrupt I/F IHM REV.0 PIRQE#/GPIO PIRQF#/GPIO PIRQG#/GPIO PIRQH#/GPIO PIRQ (For R) E F 0 E F E G F0 G 0 G F G F PI_REQ0# PI_GNT0# OR_I OR_I PI_REQ# PI_GNT# PI_REQ# PI_GNT# PI_IRY# PI_EVSEL# PI_PERR# PI_PLOK# PI_SERR# PI_STOP# PI_TRY# PI_FRME# PLTRST#_N LK_PI_IH YI0 YI IH_GPIO_PIRQG# IH_GPIO_PIRQH# PI_REQ0# () PI_GNT0# () OR_I () OR_I () T PI E0# () PI E# () PI E# () PI E# () PI_IRY# () PI_PR () PIRST# () PI_EVSEL# () PI_PERR# () PI_SERR# () PI_STOP# () PI_TRY# () PI_FRME# () LK_PI_IH () IH_PME# () YI0 (,) YI () LK_PI_IH R *0_@N for EMI. Place resister and cap close to IH. *0P/0V_@N.V 0 U TSH0FU(F) 0.U/0V_ R0 00K_ PLTRST#_N () PLTRST# (,,,,,).V.V PI_REQ# PI_REQ# PI_FRME# IH_GPIO_PIRQG# YI PI_TRY# PI_PIRQ# IH_GPIO_PIRQH# PI_REQ0# PI_PLOK# YI0 R R R 0 0 RP.KX RP.KX.K_.K_.K_.V.V PI_EVSEL# PI_STOP# PI_IRY# PI_SERR# PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PERR# PROJET : N Quanta omputer Inc.

16 ().V_S.V RST_Y#.V_S.V.V PNEL_ET imt MT / Non_MT R N 0K R0.K_ R *0K_@N R R R R R R0 R R R R R R R R R R R R R R0 R R0 LKRUN# Option to " isable " clkrun. Pulling it down will keep the clks running. No Reboot strap H_SPKR *0K_@N 0K_ 0K_ K_ 0K_@Non_MT Low = " Panel High = " Panel R 00K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ *0K_@N 0K_ 0K_.K_ *0K_@N 0K_ *.K_@N 0K_ K_ K_ M_ 0K_ IH_RI# SI# IH_PIE_WKE# PM_TLOW#_R KSMI# RST_Y_R# T_ON# NSWON# YON# E_ME_LERT ME_E_LERT LN_PHYP THERM_LERT# MH_IH_SYN#_R IRQ_SERIRQ VR_PWRG_LKEN# RSV_GPIO PNEL_ET SIM_ETET TPM_SENSE# FPK# Low = efault High = No Reboot R 0.U/0V_ IH_L_RST# R Z_SPKR U TSH0FU(F).V E - E - () () (,,0) (,,0) () (,) () () () () (,,) () (,,,) () () *0_@N ().V_S () () () () () () ().V_M LP_P# ITP_RESET# PM_MUSY# SI# PNEL_ET H_STP_PI# H_STP_PU# LKRUN# IH_PIE_WKE# IRQ_SERIRQ THERM_LERT# FPK# Z_SPKR MH_IH_SYN# IH_SMLK IH_SMT IH_L_RST# KSMI# LN_PHYP SIM_ETET () T_ON# Rev: ST_LKREQ# TPM_SENSE# IH_RSV imt R0 R0 R R0 R R0 PNEL_ET SIM_ETET (0).K_.K_ 0K_ 0K_ IH_SMLK IH_SMT MT_SMLK MT_SMT E -0 *0K_@MT *0K_@MT R R R0 0_ VR_PWRG_LKEN# H_STP_PI# H_STP_PU# IH_SMLK IH_SMT IH_L_RST# MT_SMLK MT_SMT IH_RI# LP_P# SI# H_STP_PI# H_STP_PU# LKRUN# IH_PIE_WKE# IRQ_SERIRQ THERM_LERT# VR_PWRG_LKEN SWPLINK FPK# RSV_GPIO KSMI# LN_PHYP OR_I0 0K_ OR_I 0K_ T_ON# RST_Y_R# ST_LKREQ# SWPLE SWPLE Z_SPKR T MH_IH_SYN#_R U NLSZFTG J G E F F G G E0 G H E F J0 J J J H E G H E G0 H G F J 0 J J.V U MT_SMLK MT_SMT SMLK SMT LINKLERT# SMLINK0 SMLINK RI# SUS_STT#/LPP# SYS_RESET# MUSY#/GPIO0 SMLERT#/GPIO STP_PI#/GPIO STP_PU#/GPIO LKRUN#/GPIO WKE# SERIRQ THRM# VRMPWRG TP VR_PWRG_LKEN R 00K_ SWPLE.V_S TH/GPIO TH/GPIO TH/GPIO GPIO GPIO TH0/GPIO GPIO GPIO0 SLOK/GPIO QRT_STTE0/GPIO QRT_STTE/GPIO STLKREQ#/GPIO SLO/GPIO STOUT0/GPIO STOUT/GPIO SPKR MH_SYN# TP IHM REV.0 0.U/0V_.V_S SM SYS GPIO R ST GPIO MIS GPIO ontroller Link (,0) LK Q *N00W--F@MT locks Power MGT Q *N00W--F@MT T ELY_VR_PG (,) 0K_ ST0GP/GPIO STGP/GPIO STGP/GPIO STGP/GPIO PWROK.V imt LK (,,) T (,,) LK LK SUSLK SLP_S# SLP_S# SLP_S# S_STTE#/GPIO PWROK PRSLPVR/GPIO TLOW# PWRTN# LN_RST# RSMRST# K_PWRG LPWROK SLP_M# L_LK0 L_LK L_T0 L_T L_VREF0 L_VREF L_RST# MEM_LE/GPIO ME_E_LERT/GPIO0 E_ME_LERT/GPIO WOL_EN/GPIO R 00K_ SW00PT J J0 F G G G G F H E J E H0 G E E J F E F F H J J J F G R K_ R 00K_ Q N00E.V LK_IH_M LK_IH_M IH_SUSLK SLP_S# SLP_S# SLP_S# IH_PWROK PM_PRSLPVR_R PM_TLOW#_R NSWON# PM_LN_ENLE_R PM_RSMRST#_R IH_L_PWROK L_VREF0_S L_VREF_S YON# ME_E_LERT E_ME_LERT LN_WOL_EN.V.V.V_SUS R 00K_ 0 T T SWPLE# R R0 R0 R E - R0 0_ R R U TSH0FU(F).K_.K_.K_.K_ 00/F_ 00/F_ R 00/F R 0_ R0 *0_@N R0 *0_@N R 00/F_ 0.U/0V_ IH_PWROK R 0K_ SWPLE# ().V PM_PRSLPVR RSMRST#.V efault RSV RSV RSV RSV R0 0K_ YI0 (,) LK_IH_M () LK_IH_M () SUS# () SUS# () S_STT# () PM_PRSLPVR (,0) NSWON# () PM_LN_RST# (,) PLTRST# (,,,,,) RSMRST# () LK_PWRG () IH_L_PWROK (,) SUSM# () L_LK0 () IH_L_LK () L_T0 () IH_L_T () IH_L_RST0# () YON# () ME_E_LERT () E_ME_LERT () LN_WOL_EN () oard I.V R0 0K_.V Place these close to IH. I.V_S.V LK_IH_M I 0 I0 0 0.V_M LK_IH_M If no use internal LN M connect LN_RST# to PLTRST# Use internal LN M connect LN_RST# to RSMRST# should go high no sooner than 0 ms after both VccLN_ and VccLN_ have reached their nominal voltages. I R /F_ R0 0K_ R *0_@N *0P/0V_@N R.K/F_ 0.U/0V_ imt R0 *_@N R0 /F_ ontroller Link VREF for IMT support only R K_ *0P/0V_@N R.K/F_ 0.U/0V_ GPIO[0]--Integrated Pull-own 0K. PM_PRSLPVR RSMRST# PM_LN_ENLE_R IH_L_PWROK LN_WOL_EN R0 R R00 R00 R *00K_@N 0K_ *M_@N M_ 00K_ SWP# SWPLE R 0K_ SWP# 0 SW00PT.V R 00K_ Z0 SWPLINK U TSETFU(TL,F,T) SWPLE# Q N00E 00Hz_LE# () SWPLE# () R *0K_@N R R R *0K_@N *0K_@N *0K_@N OR_I OR_I0 OR_I OR_I () OR_I OR_I () PROJET : N Quanta omputer Inc. Size ocument Number Rev IHM GPIO( of ) Monday, January, 00 ate: Sheet of