Alba Discrete ATI M92-LP gddr2 Schematics ufcpga Mobile Penryn Intel Cantiga-PM + ICH9M REV : SA

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1 lba iscrete TI M-LP gr chematics ufp Mobile Penryn Intel antiga-pm + IHM REV : : Nopop omponent M : Pop when antiga is M PM : Pop when antiga is PM /P : OM control if antiga is PM <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. over Page ize ocument Number Rev ustom lba iscrete ate: Monday, March, 00 heet of 0

2 L iscrete lock iagram PU / IL, INPUT OUTPUT P LYER L: Top L: N L: ignal L: ignal L: L: ignal L: N L: ottom RT L R RT LV(ual hannel) lock enerator LPVTR VRM(gR) Mbxx (M), TI M-LP PIe x,,, Intel Mobile PU Penryn ocket P Intel antiga-m TL+ PU I/F R Memory I/F External raphics, F 00/0MHz 0,,,,, RII 00 hannel R II 00 hannel Project code :.K0.00 Part Number :.K.0 P P/N : 00 Revision : RII 00 RII 00 lot 0 lot PIE x & U.0 x Power W TPRP 0 New ard (On Express ard board) 0 +PWR_R +PWR_R INPUT LO LTR +_ORE YTEM / TP INPUT +PWR_R YTEM / TP INPUT +.V_U OUTPUT +.0V_P OUTPUT +V_LW +.V_RT_LO +V_LW +.V_LW OUTPUT +.V_RUN YTEM / TP MIx ONTROL-LINK PIE x 0/00 LOM RTL0EL RJ ONN INPUT +PWR_R OUTPUT +.V_U ( in )/MM M/M Pro/x MI IN HP OUT (On Express ard board) (On Express ard board) igital Mic rray (Option) Internal Mic ardreader Realtek RT zalia OE OP MP IT H 0 U.0 ZLI Intel IH-M U.0/. ports () PI Express ports () High efinition udio T ports () LP I/F PI. PI/PI RIE,,0, T T PIE U.0 PI LP us K WINON WPEL U.0 x PIE x U.0 x U.0 x U.0 x Mini-ard 0.a/b/g/n MER (Option) luetooth Right ide: U x Left ide: U x YTEM / TP INPUT OUTPUT HRER MX INPUT OUTPUT +_IN +PWR_R +PTT +PWR_R +_FX_ORE LO TP00 INPUT OUTPUT +.V_U +V_R_MH_REF +0.V_R_VTT LO LTR INPUT OUTPUT H PEKER H O Flash ROM M Touch P Thermal Int. & Fan K EM0, <ore esign> +.V_U +.V_RUN Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. lock iagram ize ocument Number Rev ustom lba iscrete ate: Monday, March, 00 heet of 0

3 dapter +PWR_R TP I harger IL TP TP, +.V_U attery MX +PTT +_ORE +.0V_P +_FX_ORE TP TP00 LTR LTR +V_LW V_UX_ +V_LW +.V_LW +V_R_MH_REF +0.V_R_VTT +.V_RUN +.V_RUN +V_LW +.V_RT_LO TP0 O TP0 O0 TPRP O TPRP 0 +V_U +V_RUN +V_U +.V_LN +.V_RUX +.V_RUN +.V_R RTL0EL TP0R TPRP 0 I0 0 +V +LV +.V_R +.V_ELY Power hape Regulator LO witch <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Power lock iagram ize ocument Number Rev ustom lba iscrete ate: Monday, March, 00 heet of

4 IHM Mus lock iagram K Mus lock iagram E +V_RUN TouchPad onn. PT TPT TPT TPT +.V_LW +.V_RUN PLK TPLK TPLK TPLK IHM MLK MT 0 M_LK M_T RNKJ--P N00PT +.V_RUN RNKJ--P K WPL M_LK M_T Express ard M_LK M_T 0 IH_MLK IH_MT IH_MLK IH_MT IH_MLK IH_MT M_LK M_T IMM L Mus ddress:0 IMM L Mus ddress: lock enerator LK T Mus address: Minicard WLN M_LK M_T 0 L PIO/L PIO/ T_L T_ K_L K_ +.V_RT_LO RN00J--P PT_MLK Mus address: LK_M PT_MT T_M RNKJ--P +.V_RT_LO RNKJ--P N00W--P RN0KJ--P +.V_RUN attery onn. L MX +.V_RUN RNKJ--P THERM_L THERM_ L Mus address: Thermal Mus address: +.V_RUN RNKJ--P LK T L_LK L_T L onn. V LK MRT_LK +.V_ELY +V_RT_RUN MRT_T _T_ON T RNKJ--P +.V_ELY RNKJ--P _LK_ON RT ONN N00W--P <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. MU lock iagram ize ocument Number Rev lba iscrete Monday, March, 00 ate: heet of E

5 E Thermal lock iagram udio lock iagram PKR_PORT L+ PKR_PORT L- U_PK_L U_PK_L 0R-0-U-P U_PK_L_R U_PK_L_R PEKER PKR_PORT R- U_PK_R U_PK_R_R PKR_PORT R+ U_PK_R U_PK_R_R 0R-0-U-V-P 0P0VJN-P 0 N H_THERM THRM Thermal EM0 P P N H_THERM V_THERM V_THERM 0P0VJN-P THRM PLU MINU PU PU HP_PORT L HP_PORT R odec H HP0_PORT L HP0_PORT R VREFOUT OR_F U_HP_JK_L U_HP_JK_R U_EXT_MI_L U_EXT_MI_R U_VREFOUT_ HP OUT MI IN 0 MI_LK/PIO U_MI_LK U_MI_LK R P N PU_THERM PU_THERM 0P0VJN-P HW T sensor MMT0--P MI0/PIO PORT L PORT R VREFOUT_ U_INT_MI_L U_INT_MI_R U_VREFOUT_ RJ--P U_MI_IN0 U0VKX-P RJ--P U_MI_IN0_R INT_MI_L_R igital MI rray Internal MI KRJ--P <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Thermal/udio lock iagram ize ocument Number Rev ustom lba iscrete ate: Monday, March, 00 heet of E

6 ignal H_OUT E IH E Rev.. Usage/When ampled omment XOR hain Entrance/ llows entrance to XOR hain testing when TP PIE Port onfig bit, pulled low. When TP not pulled low at rising edge Rising Edge of PWROK. of PWROK, sets bit of RP.P (ofig Registers: offset h). This signal has weak internal pull-down. H_YN NT#/ PIO PIO0 NT#/ PIO NT#/ PIO F MI Lane Reversal 0 = Normal operation (efault): Lane Numbered in TLE# PKR TP PIO/ H_OK _EN# IHM Functional trap efinitions NT0#: PI_#/ PIO PI_MOI PIO PIE config bit0, Rising Edge of PWROK. PIE config bit, Rising Edge of PWROK. Reserved. EI trap (erver Only) Rising Edge of PWROK. Top-lock wap override. Rising Edge of PWROK. oot IO estination election 0:. Rising Edge of PWROK. PI Express Lane Reversal. Rising Edge of PWROK. No Reboot. Rising Edge of PWROK. XOR hain Entrance. Rising Edge of PWROK. Flash escriptor ecurity Override trap. Rising Edge of PWROK. This signal has a weak internal pull-down. ets bit0 of PR.P (onfig Registers: Offset h). This signal has a weak internal pull-up. ets bit of PR.P (onfig Registers: Offset h). This signal should not be pulled high. EI compatible mode is for server platforms only. This signal should not be pulled low for desktop and mobile. ampled low: Top-lock wap mode (inverts for all cycles targeting FWH IO space). Note: oftware will not be able to clear the Top-wap bit until the system is rebooted without NT# being pulled down. ontrollable via oot IO estination bit (onfig Registers: Offset 0h:bit :0). NT0# is M, 0-PI, 0-PI, -LP Integrated TPM Enable, ample low: the Integrated TPM will be disable. Rising Edge of LPWROK. ample high: the MH TPM enable strap is sampled low and the TPM isable bit is clear, the Integrated TPM will be enable. MI Termination Voltage. Rising Edge of LPWROK. The signal is required to be low for desktop applications and required to be high for mobile applications. ignal has weak internal pull-up. ets bit of MP.LR (evice : Function 0:Offset ). If sampled high, the system is strapped to the "No Reboot" mode (IH will disable the TO Timer system reboot feature). The status is readable via the NO REOOT bit. This signal should not be pull low unless using XOR hain testing. ampled low: the Flash escriptor ecurity will be overridden. If high, the security measures will be in effect. This should only be enabled in manufacturing environments using an external pull-up resister. IH Integrated pull-up and pull-down Resistors INL L_LK[:0] L_T[:0] L_RT0# PRLPVR/PIO ENERY_ETET H_IT_LK H_OK_EN#/PIO H_RT# H_IN[:0] H_OUT H_YN LN_OK# NT[:0]#/PIO[,,] PIO0 PIO L[:0]#/FHW[:0]# LN_RX[:0] LRQ[0] LRQ[]/PIO PME# PWRTN# TLE# PI_#/PIO/LPIO PI_MOI PI_MIO PKR TH_[:0] TP[] U[:0][P,N] IH E Rev.. Resistor Type/Value PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-OWN 0K PULL-UP 0K PULL-OWN 0K PULL-UP 0K PULL-OWN 0K PULL-OWN 0K PULL-OWN 0K PULL-OWN 0K The pull-up or pull-down active when configured for native LN_OK# functionality and determined by LN controller. PULL-UP 0K PULL-OWN 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP K PULL-UP 0K PULL-OWN 0K PULL-UP 0K PULL-OWN 0K PULL-UP 0K PULL-UP 0K PULL-OWN K antiga chipset and IHM I/O controller Hub strapping configuration F[:] F F[:] F[:] Order = Reverse Lanes MI x mode [MH->IH]: (->0, ->, -> and 0->) MI x mode [MH->IH]: (->0, ->) Pin Name F[:0] F F F F0 VO _TRLT Montevina Platform esign guide Rev.0. trap escription onfiguration itpm Host Interface Intel Management engine crypto strap PIE raphics Lane F0 PIE Loopback enable 0 = Enable (Note ) = isable (efault) F[:] XOR/LL 0 = The itpm Host Interface is enabled (Note ) = The itpm Host Interface is disabled (default) 0 = Transport Layer ecurity (TL) cipher suite with no confidentiality = TL cipher suite with confidentiality(efault) igital isplay Port 0 = Only igital isplay Port or PIE is (VO/P/iHMI) operational (efault) oncurrent with PIe = igital display Port and PIe are operating simulataneously via the PE port VO Present L T Local Flat Panel (LFP) Present NOTE: F Frequency elect 000 = F0 Reserved 0 = F 00 = F00 others = Reserved F MI x elect 0 = MI x = MI x (efault) 0 = Reserved Lanes, ->0, -> ect.. = Normal operation (efault): Lane Numbered in Order 00 = Reserve 0 = XOR mode Enabled 0 = LLZ mode Enable (Note ) = isabled (efault) F F ynamic OT 0 = ynamic OT isabled = ynamic OT Enabled (efault) 0 No VO ard Present (efault) = VO ard Present 0 = LFP isabled (efault) = LFP ard Present; PIE disabled. ll strap signals are sampled with respect to the leading edge of the ()MH Power OK (PWROK) signal.. itpm can be disabled by a 'oft-trap' option in the Flash-decriptor section of the Firmware. This 'oft-trap' is activated only after enabling itpm via F. Only one of the F0/F/F straps can be enabled at any time. PIE Routing U Table U LNE Miniard WLN Pair evice LNE LN 0 U U LNE New ard U REERVE MINI R REERVE LUETOOTH <ore esign> NEW R REERVE Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. REERVE 0 ard Reader MER Table of ontent ize ocument Number Rev ustom lba iscrete ate: Monday, March, 00 heet of

7 I = LOK NEWR_LKREQ# MINI_LKREQ# R0 0KRJ--P R0 0KRJ--P +.V_RUN +.V_RUN R0 0 U0VKX-P +.V_RUN R0 U0VKX-P 0R-0-U-P 0R-0-U-P 0 0UVMX-P 0UVMX-P 0 UVKX-P UVKX-P 0 UVKX-P UVKX-P 0 UVKX-P UVKX-P 0 LKTREQ# LKREQ#_ PLK_FWH PLK_K LK_PI_IH V_0_K0_IO 0 UVKX-P V_0_K0 UVKX-P L X00 0 LK_M_R 0 LK_M_IH 0 H_TP_PI# 0 H_TP_PU#,,0, IH_MLK,,0, IH_MT L X00 0 K_PWR R0 RF-L-P R0 RJ--P R0 RJ--P R0 RJ--P LK_XTL_IN LK_XTL_OUT LKTREQ# LKREQ#_ PI_TME _EL ITP_EN F U0 ILPRKLFT-P-U X X LK T V_0_K0 VREF V VPI VR VPU VPLL U_MHZ/FL PI_TOP# PU_TOP# K_PWR/P# PI0/R#_ 0 PI/R#_ PI/TME PI PI/_ELET PI_F/ITP_EN V_0_K0_IO V_IO VPLL_IO VR_IO VR_IO VR_IO VPU_IO RT R PUT0 PU0 0 PUT_F PU_F PUT_ITP/RT PU_ITP/R RT/R#_F R/R#_E 0 M 0000 RT R RT0 R0 RT/R#_H 0 R/R#_ RT R RT R RT/R#_ R/R#_ NEWR_LKREQ# LK_PIE_NEW LK_PIE_NEW# LK_PU_LK LK_PU_LK# LK_MH_LK LK_MH_LK# LK_PU_ITP LK_PU_ITP# LK_PIE_LN LK_PIE_LN# LK_PIE_V LK_PIE_V# LK_PIE_NEW LK_PIE_NEW# LK_PIE_MINI_ LK_PIE_MINI_# LK_MH_PLL LK_MH_PLL# LK_PIE_IH LK_PIE_IH# RN0 RN0J--P LK_PU_LK LK_PU_LK# LK_MH_LK 0 LK_MH_LK# 0 LK_PU_ITP LK_PU_ITP# LK_PIE_LN LK_PIE_LN# LK_PIE_V LK_PIE_V# LK_PIE_NEW 0 LK_PIE_NEW# 0 NEWR_LKREQ# 0 MINI_LKREQ# LK_PIE_MINI LK_PIE_MINI# LK_MH_PLL LK_MH_PLL# LK_PIE_IH LK_PIE_IH# 0 LK_M_IH F F Main source:.0.00 (LPVTR) econd source:.00.0 (RTMN-0-V-RT) FL/TET_MOE REF0/FL/TET_EL N# N NPI NREF N NR NR NR NPU N 0 RT/TT R/T MHZ_NON/RT/E MHZ_/R/E N RT0/OTT_ 0 R0/OT_ M 000 LK_PIE_T LK_PIE_T# MH_REFLK LK_PIE_T LK_PIE_T# MH_REFLK MH_REFLK# LK_MH_REFLK LK_MH_REFLK# M 0000 LK_V_M_N V_0_K0 V_0_K0 ITP_EN Output 0 R PU_ITP V_0_K0 0 UVKX-P 0 UVKX-P P0VJN-P 0 P0VN-P P0VN-P PM R 0RJ--P R 0KRJ--P UVKX-P UVKX-P 0 P0VJN-P X0 X-M-0P R0 RJ--P R0 RJ--P P0VN-P RN0 RN0 RN0 RN0 RN RN0 RN0 RN0 0 P0VN-P RN0J--P RN0J--P RN0J--P RN0J--P RN0J--P RN0J--P RN0J--P RN0J--P E0 P0VJN-P P0VN-P P0VN-P R RJ--P RN0 M MH_REFLK RN MH_REFLK# M LK_MH_REFLK RN0 LK_MH_REFLK# RN0J--P RN0J--P RN0J--P R 0KRJ--P ITP_EN R 0KRJ--P PI_TME R 0KRJ--P PI_TME 0 Output Overclocking of PU and R allowed Overclocking of PU and R not allowed R PM 0KRJ--P _EL E0 P0VJN-P R M 0KRJ--P MH_REFLK MH_REFLK# _EL PIN 0 PIN 0 OTT OT E0 P0VJN-P UM RT0 R0 iscrete EL F EL F EL0 F 0 00M X 0 0 M M 0 M M M 00M M 0M PU F PU_EL PU_EL PU_EL0 R 0KRJ--P R 0RJ--P R0 KRJ--P R KRJ--P R KRJ--P R KRJ--P F F F MH_LKEL0 MH_LKEL MH_LKEL <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. lock enerator LPVTR ize ocument Number Rev ustom lba iscrete ate: Monday, March, 00 heet of

8 I = PU PU OF TP 0 H_#[..] H_#[..] 0 H_T#0 0 H_REQ#[..0] 0 H_T# H_0M# H_FERR# H_INNE# H_TPLK# H_INTR H_NMI H_MI# TP0 TP0 TP0 TP0 TP0 TP0 TP TP0 TP0 TP0 TP0 H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_REQ#0 H_REQ# H_REQ# H_REQ# H_REQ# RV_PU_ RV_PU_ RV_PU_ RV_PU_ RV_PU_ RV_PU_ RV_PU_ RV_PU_ RV_PU_ RV_PU_0 RV_PU_ J # L # L # K # M # N # J # N 0# P # P # L # P # P # R # M T0# K REQ0# H REQ# K REQ# J REQ# L REQ# H_# Y H_# # U H_# # R H_#0 # W H_# 0# U H_# # Y H_# # U H_# # R H_# # T H_# # T H_# # W H_# # W H_# # Y H_#0 # U H_# 0# V H_# # W H_# # H_# # H_# # # V T# 0M# FERR# INNE# TPLK# LINT0 LINT MI# M RV#M N RV#N T RV#T V RV#V RV# RV# TET RV# RV# RV# F RV#F KEY_N REERVE R ROUP 0 R ROUP IH -KT-PU.000. XP/ITP INL ONTROL # NR# PRI# EFER# R# Y# R0# IERR# INIT# LOK# REET# R0# R# R# TR# HIT# HITM# PM0# PM# PM# PM# PR# PREQ# TK TI TO TM TRT# R# THERML PROHOT# THRM THRM THERMTRIP# HLK LK0 LK H E H F E F 0 PU_IERR# H F F E H_PURT# H_R#0 H_R# H_R# ITP_PM#0 ITP_PM# ITP_PM# ITP_PM# ITP_PM# ITP_PM# ITP_TK ITP_TI ITP_TO ITP_TM ITP_TRT# 0 ITP_REET# R0 0RJ--P R0 RJ--P H_THERM H_THERM R0 RJ--P H_# 0 H_NR# 0 H_PRI# 0 H_EFER# 0 H_R# 0 H_Y# 0 H_REQ#0 0 R0 RJ--P H_INIT# H_LOK# 0 H_PURT# 0, H_R#[..0] 0 H_TR# 0 H_HIT# 0 H_HITM# 0 ITP_PM#0 ITP_PM# ITP_PM# ITP_PM# ITP_PM# ITP_PM# ITP_TK ITP_TI ITP_TO ITP_TM ITP_TRT# ITP_REET# 0, +.0V_P H_THERM H_THERM +.0V_P +.0V_P PU_PROHOT# H_THRMTRIP#,,,0, LK_PU_LK LK_PU_LK# +.0V_P R KRF--P H_THRMTRIP# should connect to IH and MH without T-ing. R KRF--P PU_TLREF0 0 KP0VKX-P X H_TN#0 0 H_TP#0 0 H_INV#0 0 H_TN# 0 H_TP# 0 H_INV# R0 KRJ--P R0 KRJ--P R0 KRJ--P R0 KRJ--P PU_EL0 PU_EL PU_EL H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# TET TET PU_TET PU_TET H_INV#[..0] H_TN#[..0] H_TP#[..0] H_#[..0] PU OF E 0# F # E # # F # # E # E # K # # J 0# J # H # F # K # H # J TN0# H TP0# H INV0# N # K # P # R # L 0# M # L # M # P # P # P # T # R # L # T 0# N # L TN# M TP# N INV# TLREF TET TET TET F TET F TET TET EL0 EL EL T RP0 T RP T RP T RP MI H_INV#[..0] 0 H_TN#[..0] 0 H_TP#[..0] 0 H_#[..0] 0 # Y # # V # V # V # T # U # U 0# Y # W # Y # W # W # # # TN# Y TP# INV# U # E # 0# # # # # 0 # E # F # # E # 0# # # F # TN# E TP# F INV# 0 OMP0 R OMP U OMP OMP Y PRTP# E PLP# PWR# PWROO LP# PI# E H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# OMP0 OMP OMP OMP H_TN# 0 H_TP# 0 H_INV# 0 H_TN# 0 H_TP# 0 H_INV# 0 R RF-L-P R RF-L-P R0 RF-L-P R0 RF-L-P H_PRTP#,, H_PLP# H_PWR# 0 H_PWROO,0 H_PULP# 0 PI# Layout notes Z= Ohm 0." MX for PU_TLREF0 -KT-PU.000. Layout Note: omp0, connect with Zo=. ohm, make trace length shorter than 0.". omp, connect with Zo= ohm, make trace length shorter than 0.". <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PU-F(/) ize ocument Number Rev ustom lba iscrete ate: Monday, March, 00 heet of

9 I = PU +_ORE +_ORE PU OF E E E0 P E P E P E P E P E P E0 P F P F P F0 P F P F P F P F P F P F0 P 0 VI0 VI VI VI 0 VI VI 0 VI 0 ENE ENE -KT-PU E E0 E E E E E E0 F F0 F F F F F F0 V J K M J K M N N R R T T V W +_ORE PU_VI0 F PU_VI E PU_VI F PU_VI E PU_VI F PU_VI E PU_VI F E PU_VI[..0] +_ORE +_ORE +.0V_P layout note: "+.V_" as short as possible R0 P0 P0 UVMX-P UVMX-P 0 UVMX-P T0 T0UVM-LP R0 00RF-L-P-U P-LOE-PWR--P UVMX-P UVMX-P UVMX-P UVKX-P UVMX-P UVMX-P 0 UVMX-P UVKX-P 0UVKX-P +_ORE _ENE _ENE 0 UVMX-P UVMX-P UVMX-P UVKX-P 0 U0VKX-P UVMX-P 0 UVKX-P +.V_ +.V_RUN R0 UVMX-P UVMX-P UVMX-P 0 UVMX-P UVMX-P 0R-0-U-P 0 0UVMX-P 0 UVMX-P UVMX-P UVMX-P X UVKX-P 0 UVMX-P 0 UVMX-P 0 UVMX-P _ENE and _ENE lines should be of equal length. X UVMX-P UVMX-P UVMX-P UVMX-P UVMX-P UVMX-P Layout Note: Place as close as possible to the PU pin. 0 UVMX-P UVMX-P PU F E E E E E E E E E F F F F F F F F F H H H H J J J J K K K K L L L L M M M M N N N N P OF P P P R R R R T T T T U U U U V V V V W W W W Y Y Y Y E E E E E E E E E F F F F F F F F PU_N PU_N PU_N PU_N NTF PIN TP0 TP0 TP0 TP0 00RF-L-P-U P-LOE-PWR--P -KT-PU.000. X <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PU-Power(/) ize ocument Number Rev ustom lba iscrete ate: Monday, March, 00 heet of

10 I = MH H_WIN routing Trace width and pacing use 0 / 0 mil H_WIN Resistors and apacitors close MH 00 mil ( MX ) H_WIN H_ROMP routing Trace width and pacing use 0 / 0 mil H_ROMP R00 RF-L-P Place R00 near to the chip ( < 0.") 00 U0VKX-P +.0V_P R00 RF--P +.0V_P H_#[..0] H_VREF H_#[..0], H_PURT# H_PULP# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_WIN H_ROMP H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_INV#0 H_INV# H_INV# H_INV# H_TN#0 H_TN# H_TN# H_TN# H_TP#0 H_TP# H_TP# H_TP# H_REQ#0 H_REQ# H_REQ# H_REQ# H_REQ# H_R#0 H_R# H_R# H_#[..] H_# H_T#0 H_T# H_NR# H_PRI# H_REQ#0 H_EFER# H_Y# LK_MH_LK LK_MH_LK# H_PWR# H_R# H_HIT# H_HITM# H_LOK# H_TR# H_INV#[..0] H_TN#[..0] H_TP#[..0] H_REQ#[..0] H_R#[..0] H_#[..] H_INV#[..0] H_TN#[..0] H_TP#[..0] H_REQ#[..0] H_R#[..0] R00 00RF-L-P-U R00 KRF--P U00 F H_#_0 H_#_ F H_#_ E H_#_ H_#_ H H_#_ H H_#_ F H_#_ H_#_ H H_#_ M H_#_0 M H_#_ J H_#_ J H_#_ N H_#_ J H_#_ P H_#_ L H_#_ R H_#_ N H_#_ L H_#_0 M H_#_ J H_#_ N H_#_ R H_#_ N H_#_ N H_#_ P H_#_ N H_#_ L H_#_ N0 H_#_0 M H_#_ Y H_#_ H_#_ Y H_#_ Y0 H_#_ Y H_#_ Y H_#_ Y H_#_ W H_#_ H_#_0 Y H_#_ H_#_ H_#_ H_#_ H_#_ 0 H_#_ H_#_ E H_#_ E H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ E H_#_ F H_#_ H_#_ E H_#_ H_#_ E H_#_0 E H_#_ H_#_ H_#_ H_WIN E H_ROMP H_PURT# E H_PULP# H_VREF H_VREF H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_# H_T#_0 H_T#_ H_NR# H_PRI# H_REQ# H_EFER# H_Y# HPLL_LK HPLL_LK# H_PWR# H_R# H_HIT# H_HITM# H_LOK# H_TR# H_INV#_0 H_INV#_ H_INV#_ H_INV#_ H_TN#_0 H_TN#_ H_TN#_ H_TN#_ H_TP#_0 H_TP#_ H_TP#_ H_TP#_ H_REQ#_0 H_REQ#_ H_REQ#_ H_REQ#_ H_REQ#_ H_R#_0 H_R#_ H_R#_ F H M J P R N M E P F 0 J E0 H J0 L L J H0 K 0 F K L0 H F E 0 H H J F H E H J L Y Y L0 M E L M E K F F R00 KRF--P 00 UVKX-P HOT OF 0 NTI-M-P-U-NF <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. antiga-hot(/) ize ocument Number Rev ustom lba iscrete ate: Monday, March, 00 heet 0 of

11 I = MH * is current setting F trap +.V_RUN F F F F F F MI Lane Reserved F 0 VO concurrent with PIE VO_TRLT P_TRLT R0 KRF-P F R KRF-P F R0 K0RF-P F R K0RF-P F0 R KRF-P F R0 KRF-P F R0 KRF-P F R0 KRF-P F R K0RF-P F R KRF-P F0 R0 KRF-P F R0 KRF-P F R0 KRF-P F F dynamic OT disable VO/iHMI/P interface disabled PM_EXTT#0 PM_EXTT# Low MI X ITPM enable TL cipher suite with no confidentiality PIE FX lane reversed Normal operation Only PIE or VO is operational VO interface disable 0,, PM_PWROK,,,,0 PLT_RT#,,,0, H_THRMTRIP# 0, PRLPVR VO/iHMI/P interface enabled F setting High MI X ITPM disable TL cipher suite with confidentiality PIE FX lane numbered in oder F 0 PIE loopback enable PIE loopback disable F LLZ mode enable LLZ mode disable F XOR mode enable XOR mode disable * * * F ynamic OT enable Reverse MI lanes PIE and VO are operatiing simultaneously via the PE port VO interface enable L T LFP disable LFP card present RN0 RN0KJ--P MH_LKEL0 MH_LKEL MH_LKEL TP0 TP0 TP0 TP0 TP0 0 PM_YN#,, H_PRTP# PM_EXTT#0 PM_EXTT# R 0RJ--P R0 00RJ--P 0 00P0VJN-P * * * F F F F F F F F0 F F F F F F F F F F0 PWROK_R RTIN# M REERVE#M N REERVE#N R REERVE#R T REERVE#T H REERVE#H H0 REERVE#H0 H REERVE#H H REERVE#H K REERVE#K L REERVE#L K REERVE#K N REERVE#N M REERVE#M T REERVE#T Y U00 REERVE# REERVE# M REERVE#M REERVE#Y REERVE# F REERVE#F H REERVE#H F REERVE#F T F_0 R F_ P F_ P0 F_ P F_ F_ N F_ M F_ E F_ F_ F_0 N F_ P F_ T F_ R0 F_ M0 F_ L F_ H F_ P F_ R F_ T F_0 R PM_YN# PM_PRTP# N PM_EXT_T#_0 P PM_EXT_T#_ T0 PWROK T RTIN# T0 THERMTRIP# R PRLPVR N# F N#F N# N# H N#H N# E N#E H N#H F N#F N# H N#H H N#H H N#H H N#H N# H N#H F N#F H N#H N# E N#E N# F N#F N# N# F N#F N# NTI-M-P-U-NF RV F PM N R LK/ ONTROL/OMPENTION LK MI RPHI VI ME MI H OF 0 _K_0 P _K_ T _K_0 V _K_ U0 _K#_0 R _K#_ R _K#_0 U _K#_ V0 _KE_0 _KE_ Y _KE_0 Y _KE #_0 _#_ Y _#_0 V _#_ R _OT_0 _OT_ Y _OT_0 F _OT_ Y M_ROMP M_ROMP# H M_ROMP_VOH F M_ROMP_VOL H M_VREF V M_PWROK R M_REXT F M_RMRT# PLL_REF_LK PLL_REF_LK# PLL_REF_LK E PLL_REF_LK# F PE_LK F PE_LK# E MI_RXN_0 E MI_RXN_ E MI_RXN_ E MI_RXN_ H MI_RXP_0 MI_RXP_ MI_RXP_ MI_RXP_ M_ROMPP M_ROMPN M_ROMP_VOH M_ROMP_VOL NTI_M_VREF M_REXT LK_MH_REFLK LK_MH_REFLK# MH_REFLK MH_REFLK# LK_MH_PLL LK_MH_PLL# MI_ITXN0_MRXN0 MI_ITXN_MRXN MI_ITXN_MRXN MI_ITXN_MRXN E0 MI_ITXP0_MRXP0 E MI_ITXP_MRXP E MI_ITXP_MRXP H0 MI_ITXP_MRXP MI_IRXN0_MTXN0 MI_TXN_0 E MI_IRXN_MTXN MI_TXN_ E MI_IRXN_MTXN MI_TXN_ E MI_IRXN_MTXN MI_TXN_ H MI_TXP_0 MI_TXP_ E MI_TXP_ F MI_TXP_ H FX_VI_0 FX_VI_ FX_VI_ FX_VI_ F FX_VI_ E FX_VR_EN L_LK H L_T H L_PWROK N L_RT# J L_VREF H P_TRLLK N P_TRLT M VO_TRLLK VO_TRLT E LKREQ# K IH_YN# H TTN# H_LK H_RT# 0 H_I H_O H_YN MI_IRXP0_MTXP0 MI_IRXP_MTXP MI_IRXP_MTXP MI_IRXP_MTXP MH_LVREF TTN# M_LK_R0 M_LK_R M_LK_R M_LK_R M_LK_R#0 M_LK_R# M_LK_R# M_LK_R# M_KE0 M_KE M_KE M_KE M_0# M_# M_# M_# M_OT0 M_OT M_OT M_OT LK_MH_REFLK LK_MH_REFLK# MH_REFLK MH_REFLK# LK_MH_PLL LK_MH_PLL# MI_ITXN0_MRXN0 MI_ITXN_MRXN MI_ITXN_MRXN MI_ITXN_MRXN MI_ITXP0_MRXP0 MI_ITXP_MRXP MI_ITXP_MRXP MI_ITXP_MRXP MI_IRXN0_MTXN0 MI_IRXN_MTXN MI_IRXN_MTXN MI_IRXN_MTXN MI_IRXP0_MTXP0 MI_IRXP_MTXP MI_IRXP_MTXP MI_IRXP_MTXP L_LK0 0 L_T0 0 M_PWROK 0 L_RT#0 0 MH_LVREF ~= 0.V TP0 R RF--P LKREQ#_ MH_IH_YN# 0 M U0VKX-P +.0V_P +.V_U LK_MH_REFLK LK_MH_REFLK# MH_REFLK MH_REFLK# R KRF--P R RF--P R 0RF-L-P U0VKX-P R 0RF-L-P U0VKX-P TTN# +.0V_P M_ROMP_VOH M_ROMP_VOL +.V_U R 0R-0-U-P R 0KRF--P RN0 PM RN0J--P RN0 PM RN0J--P LKREQ#_ <ore esign> 0 U0VKX-P R RJ--P M V_RUN R 0KRJ--P R 0KRJ--P 0 0UVKX-P 0 0UVKX-P +V_R_MH_REF TTN#_K Q0 MMT0WT-P E 0 U0VKX-P R 0KRF--P +.V_RUN +.V_U TTN#_K Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. antiga-mi/f(/) ize ocument Number Rev ustom lba iscrete ate: Monday, March, 00 heet of R KRF--P R0 K0RF--P R KRF--P

12 I = MH M Q[..0] M Q[..0] M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q U00 J _Q_0 J _Q_ N _Q_ M _Q_ J _Q_ J0 _Q_ M _Q_ M _Q_ N _Q_ N _Q_ U0 _Q_0 T _Q_ N _Q_ N _Q_ U _Q_ U _Q_ V _Q_ Y _Q_ 0 _Q Q_ V _Q_0 Y _Q Q_ 0 _Q_ Y _Q Q_ V _Q_ T _Q_ Y _Q Q_ V _Q_0 W _Q Q_ U _Q Q Q_ U _Q_ V _Q Q Q Q_0 _Q_ U0 _Q_ V _Q Q Q_ Y _Q Q_ V _Q_ V _Q_ T _Q_0 N _Q_ U _Q_ U _Q_ T _Q_ N0 _Q_ M _Q_ M _Q_ J _Q_ J _Q_ N _Q_0 M _Q_ J _Q_ J _Q_ R YTEM MEMORY OF 0 0 _R# _# _WE# _M_0 _M M M M M M M Q_0 _Q Q Q Q Q Q Q Q#_0 _Q# Q# Q# Q# Q# Q# Q# M_0 _M M M M M M M M M M_0 _M M M M_ T 0 0 Y0 M T Y U Y T J J T W U M J T Y U M H F W H H Y M M0 M M M M M M M M M M M M M M M Q0 M Q M Q M Q M Q M Q M Q M Q M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M 0 M M M M M M M M M M 0 M M M M M M[..0] M Q[..0] M Q#[..0] M [..0] M #0 M # M # M R# M # M WE# M M[..0] M Q[..0] M Q#[..0] M [..0] M Q[..0] M Q[..0] M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q U00E K _Q_0 H _Q_ P _Q_ P _Q_ J _Q_ J _Q_ M _Q_ P _Q_ U _Q_ U _Q Q_0 Y _Q_ T _Q_ R _Q Q Q Q Q Q_ F _Q_ E _Q_0 _Q_ F0 _Q_ F _Q Q_ F _Q_ H _Q Q_ H0 _Q Q Q_0 H _Q_ H _Q Q_ H _Q Q_ H _Q_ F _Q_ F _Q Q Q_0 _Q_ Y _Q_ Y _Q_ F _Q_ F _Q Q Q_ V _Q_ U _Q_ R _Q_0 N _Q_ Y _Q_ V _Q_ P _Q_ R _Q_ L _Q_ L _Q_ J _Q_ H _Q_ M _Q_0 M _Q_ H _Q_ J _Q_ R YTEM MEMORY OF 0 0 _R# _# _WE# _M_0 _M M M M M M M Q_0 _Q Q Q Q Q Q Q Q#_0 _Q# Q# Q# Q# Q# Q# Q# M_0 _M M M M M M M M M M_0 _M M M M_ U F M Y 0 F P K L V H U N L V H H T N V U W U W T W Y H U M M0 M M M M M M M M M M M M M M M Q0 M Q M Q M Q M Q M Q M Q M Q M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M 0 M M M M M M M M M M 0 M M M M M M[..0] M Q[..0] M Q#[..0] M [..0] M #0 M # M # M R# M # M WE# M M[..0] M Q[..0] M Q#[..0] M [..0] NTI-M-P-U-NF NTI-M-P-U-NF <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. antiga-r(/) ize ocument Number Rev ustom lba iscrete ate: Monday, March, 00 heet of

13 MH_N MH_N MH_N MH_N PE_MP L LK L T PIE_MTX_RX P PIE_MTX_RX P PIE_MTX_RX P PIE_MTX_RX P PIE_MTX_RX P PIE_MTX_RX P PIE_MTX_RX P PIE_MTX_RX P PIE_MTX_RX P PIE_MTX_RX P PIE_MTX_RX P PIE_MTX_RX P PIE_MTX_RX P0 PIE_MTX_RX P PIE_MTX_RX P0 PIE_MTX_RX P PIE_MRX_TX_N0 PIE_MRX_TX_N PIE_MRX_TX_N PIE_MRX_TX_N PIE_MRX_TX_N PIE_MRX_TX_P0 PIE_MRX_TX_N PIE_MRX_TX_P PIE_MRX_TX_P PIE_MRX_TX_P PIE_MRX_TX_P PIE_MRX_TX_P PIE_MRX_TX_N[0..] PIE_MRX_TX_P0 PIE_MRX_TX_N0 PIE_MRX_TX_N PIE_MRX_TX_P PIE_MRX_TX_P PIE_MRX_TX_P PIE_MRX_TX_N PIE_MRX_TX_N PIE_MRX_TX_P PIE_MRX_TX_N PIE_MRX_TX_P PIE_MRX_TX_N PIE_MRX_TX_P PIE_MRX_TX_N PIE_MRX_TX_P PIE_MRX_TX_N PIE_MRX_TX_P PIE_MRX_TX_P[0..] PIE_MRX_TX_P PIE_MRX_TX_N PIE_MRX_TX_N PIE_MTX_RX_P[0..] PIE_MTX_RX_N PIE_MTX_RX_N0 PIE_MTX_RX_N PIE_MTX_RX_N0 PIE_MTX_RX_N PIE_MTX_RX_N PIE_MTX_RX_N PIE_MTX_RX_N PIE_MTX_RX_N PIE_MTX_RX_N PIE_MTX_RX_N PIE_MTX_RX_N PIE_MTX_RX_N PIE_MTX_RX_N PIE_MTX_RX_N PIE_MTX_RX_N PIE_MTX_RX_N[0..] PIE_MTX_RX_P PIE_MTX_RX_P PIE_MTX_RX_P PIE_MTX_RX_P PIE_MTX_RX_P PIE_MTX_RX_P PIE_MTX_RX_P PIE_MTX_RX_P PIE_MTX_RX_P PIE_MTX_RX_P PIE_MTX_RX_P PIE_MTX_RX_P PIE_MTX_RX_P0 PIE_MTX_RX_P PIE_MTX_RX_P0 PIE_MTX_RX_P PIE_MTX_RX N PIE_MTX_RX N0 PIE_MTX_RX N PIE_MTX_RX N0 PIE_MTX_RX N PIE_MTX_RX N PIE_MTX_RX N PIE_MTX_RX N PIE_MTX_RX N PIE_MTX_RX N PIE_MTX_RX N PIE_MTX_RX N PIE_MTX_RX N PIE_MTX_RX N PIE_MTX_RX N PIE_MTX_RX N L_TRL_LK RT LK RT T L_TRL_T RT_TVO_IREF +_PE PIE_MRX_TX_P[0..] PIE_MRX_TX_N[0..] PIE_MTX_RX_P[0..] PIE_MTX_RX_N[0..] ize ocument Number Rev ate: heet of Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. lba iscrete antiga-n/lv/v(/) Monday, March, 00 <ore esign> ize ocument Number Rev ate: heet of Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. lba iscrete antiga-n/lv/v(/) Monday, March, 00 <ore esign> ize ocument Number Rev ate: heet of Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. lba iscrete antiga-n/lv/v(/) Monday, March, 00 <ore esign> NTF PIN Place R0 close to MH within 00 mils. I = MH for iscrete M 000 M 000 U0VKX-P U0VKX-P R0 0RJ--P R0 0RJ--P U0VKX-P U0VKX-P U0VKX-P U0VKX-P PE_OMPI T PE_OMPO T PE_RX#_0 H PE_RX#_ J PE_RX#_ L PE_RX#_ L0 PE_RX#_ N PE_RX#_ P PE_RX#_ N PE_RX#_ T PE_RX#_ U PE_RX#_ Y PE_RX#_0 Y PE_RX#_ Y PE_RX#_ PE_RX#_ PE_RX#_ PE_RX#_ PE_RX_0 H PE_RX_ J PE_RX_ L PE_RX_ L PE_RX_ N0 PE_RX_ P PE_RX_ N PE_RX_ T PE_RX_ U PE_RX_ Y PE_RX_0 W PE_RX_ Y PE_RX_ PE_RX_ PE_RX_ PE_RX_ 0 PE_TX#_0 J PE_TX#_0 Y0 PE_TX#_ M0 PE_TX#_ M PE_TX#_ R PE_TX#_ N PE_TX#_ T0 PE_TX#_ U PE_TX#_ U0 PE_TX#_ M PE_TX#_ PE_TX#_ PE_TX#_ 0 PE_TX#_ PE_TX#_ PE_TX#_ M PE_TX_0 J PE_TX_ L PE_TX_ M PE_TX_ M PE_TX_ M PE_TX_ R PE_TX_ N PE_TX_ T PE_TX_ U PE_TX_ U PE_TX_0 Y PE_TX_ Y PE_TX_ PE_TX_ PE_TX_ PE_TX_ L_TRL_LK M L_TRL_T M L LK K L T J L_V_EN M LV_I LV_V LV_VREFH E LV_VREFL E LV_LK# LV_LK 0 LV_T#_0 H LV_T#_ E LV_T#_ 0 LV_T_ LV_T_ F0 LV_LK# LV_LK LV_T#_0 LV_T#_ H LV_T#_ LV_T_ LV_T_ F L_KLT_EN TV_ F TV_ H TV_ K TV_RTN H RT_LUE E RT LK H RT T J RT_REEN RT_HYN J RT_TVO_IREF E RT_RE J RT_IRTN RT_VYN L LV_T_0 H LV_T_0 L_KLT_TRL L TV_ONEL_0 TV_ONEL_ E LV_T#_ 0 LV_T_ 0 LV_T#_ J LV_T_ K LV PI-EXPRE RPHI TV V OF 0 U00 NTI-M-P-U-NF LV PI-EXPRE RPHI TV V OF 0 U00 NTI-M-P-U-NF 0 U0VKX-P 0 U0VKX-P R0 RF-P R0 RF-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P 0 U0VKX-P 0 U0VKX-P TP0 TP0 TP0 TP0 U0VKX-P U0VKX-P U0VKX-P U0VKX-P 0 U0VKX-P 0 U0VKX-P U0VKX-P U0VKX-P 0 U0VKX-P 0 U0VKX-P 0 U0VKX-P 0 U0VKX-P TP0 TP0 0 U0VKX-P 0 U0VKX-P U0VKX-P U0VKX-P R0 0RJ--P R0 0RJ--P U0VKX-P U0VKX-P TP0 TP0 U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P 0 U0VKX-P 0 U0VKX-P RN0 RN0J--P PM RN0 RN0J--P PM U0VKX-P U0VKX-P 0 U0VKX-P 0 U0VKX-P U R L W N J F Y T N L V R M V R P H F F H Y U T M F V U M J Y T N J E N L U M H Y U T M 0 0 V0 N0 H0 E0 T M J E N L H U H Y U T J F M E P L J F H Y U T F M J F E W V R L H P L H N K F N T N K H F V T R J E Y P K H F F H F H V R J Y N L J E F F W T N J H U T H L Y E Y J F R K J F H Y K J OF 0 U00I NTI-M-P-U-NF OF 0 U00I NTI-M-P-U-NF U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P 0 U0VKX-P 0 U0VKX-P W U P N H F R M J 0 0 W0 T0 J0 0 Y0 N0 K0 F0 0 0 W T R M H U N N K E W N J E N L E F V T M J Y N H Y N 0 V0 T0 J0 E0 0 H M N M0 F H Y L E Y U N J E N J V T M M H Y L J H F E V L _NTF F _NTF _NTF V _NTF J0 _NTF M _NTF F _NTF _NTF U _NTF U _NTF L0 _NTF V0 _NTF _NTF L _NTF J _NTF _NTF U _ H _ H _ N#E E N# N# N# N# N# N# N# N# N# N# N# N# N#F F N#E E N# N# R P R U P F W E F H J Y M K M P H V T U U U U L NTF N 0 OF 0 U00J NTI-M-P-U-NF NTF N 0 OF 0 U00J NTI-M-P-U-NF 0 U0VKX-P 0 U0VKX-P U0VKX-P U0VKX-P 0 U0VKX-P 0 U0VKX-P U0VKX-P U0VKX-P R0 0RJ--P R0 0RJ--P 0 U0VKX-P 0 U0VKX-P U0VKX-P U0VKX-P

14 I = MH U00F OF 0 +.0V_P +.0V_P R0 0R-0-U-P M R0 0R-0-U-P M lose to ()MH UVKX-P On the edge 0 UVKX-P /P UVMX-P UVMX-P UVKX-P M V_U U0VKX-P /P /P TP0 TP0 _X_ENE _X_ENE U00 P _M N _M H _M _M F _M _M _M _M _M Y _M W _M V _M U _M T _M R _M P _M N _M H _M _M F _M 0 _M H _M _M F _M _M _M _M _M Y _M W _M V _M U _M T _M R _M P _M +.0V_P_X Y _X E _X _X _X E _X _X _X Y _X E _X _X _X _X J _X _X E _X _X _X Y _X H0 _X F0 _X E0 _X 0 _X 0 _X 0 _X T _X T _X M _X L _X E _X J _X H _X _X F _X _X _X Y _X V _X U _X N _X M _X U _X T _X 000m _M/N _M/N _M/N _M/N W _M/N W _M/N T _M/N 00m J _X_ENE H _X_ENE POWER M FX NTI-M-P-U-NF FX NTF M LF OF 0 _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _M_LF _M_LF _M_LF _M_LF _M_LF _M_LF _M_LF W V W V W V W V W V M L K W V U M0 K0 W0 U0 M L +.0V_P_X K J H F E Y W V U M K H F E Y W V M L K J H F E Y W V U V M_LF_MH M_LF_MH M0M_LF_MH V M_LF_MH Y M_LF_MH M0M_LF_MH M_LF_MH M U0VKX-P 0 U0VKX-P /P UVKX-P 0 U0VKX-P /P UVMX-P 0 U0VKX-P /P U0VKX-P /P UVKX-P +.0V_P upply ignal roup Imax +.0V_P 00m +.0V_P VTT m +.0V_P _PE m +.0V_P _MI m +.0V_P _M 0m +.0V_P _M_K m +.0V_P _HPLL m +.0V_P _MPLL.m +.0V_P _HPLL.m +.0V_P _PE_PLL 0m +.0V_P _PE_PLL 0m +.0V_P _XF.m +.V_RUN _TV m +.V_U _M 000m +.V_U _M_K m +.V_RUN _PE_ u +.V_RUN _HV 0.m 0 UVKX-P 0 U0VKX-P R0 0R-0-U-P M 0 U0VKX-P UVKX-P 0 UVKX-P 0 U0VKX-P 0 UVKX-P Y V U M K J F E Y W V U H F J E H F J H F T 00m ORE NTI-M-P-U-NF <ore esign> POWER NTF +.0V_P _NTF M _NTF L _NTF K _NTF J _NTF H _NTF _NTF E _NTF _NTF _NTF Y _NTF W _NTF U _NTF M0 _NTF L0 _NTF K0 _NTF H0 _NTF 0 _NTF F0 _NTF E0 _NTF 0 _NTF 0 _NTF 0 _NTF Y0 _NTF W0 _NTF V0 _NTF U0 _NTF L _NTF K _NTF J _NTF H _NTF _NTF E _NTF _NTF _NTF Y _NTF W _NTF V _NTF L _NTF K _NTF L _NTF K _NTF K _NTF K _NTF K Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. antiga-power(/) ize ocument Number Rev ustom lba iscrete ate: Monday, March, 00 heet of

15 I = MH +.0V_P U00H OF 0 +.0V_P L0 LMPN-P 0ohm 00MHz L0 LMPN-P 0ohm 00MHz +.0V_P L0 LMN-P 0ohm 00MHz +.V_RUN L0 LMPN-P M 000 M MPLL +.0V_P 0R-0-U-P M R M HPLL UVKX-P 0UVMX-P X00 L +.0V_P R0 0V_RUN_PEPLL 0R-0-U-P 0UVMX-P 0UVKX-P M 000 /P U0VKX-P T0 T00UVM-P /P +.V_RUN R 0RJ--P VRUN_Q U0VKX-P U0VKX-P U0VKX-P U0VKX-P +.0V_P R0 0R-0-U-P +.V_RUN R 0RJ--P +.0V_P R0 0R-0-U-P U0VKX-P +.0V_P PLL M HPLL M MPLL For iscrete _PE_ 0 U0VKX-P 0V_RUN_PEPLL 0V_M 0 UVMX-P UVMX-P 0 U0VKX-P 0 UVMX-P U0VKX-P 0 UVKX-P 0V_M_K _TV R 0RJ--P VRUN_Q 0V_RUN_HPLL 0V_RUN_PEPLL U0VKX-P U0VKX-P 0 U0VKX-P F L E J J R0 P0 N0 R P N T R P P N P N N M M M L M L M L M L F M L _RT RT PLL _PLL _HPLL m _MPLL.m _LV _PE_ u _PE_PLL0m 0m.m _LV.m _M _M _M _M _M _M _M _M _M _M_K _M_K _M_K _M_K _M_K _M_K_NTF _M_K_NTF _M_K_NTF _M_K_NTF _M_K_NTF _M_K_NTF _M_K_NTF _M_K_NTF _TV TV_.m _H 0m _HPLL.m _PE_PLL0m _LV _LV 0.m m RT PLL LV PE M TV H _TV m _Q m LV POWER K TV/RT XF M K m.m 0.m m m m VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT _XF _XF _XF _M_K _M_K _M_K _M_K.m _TX_LV MI HV PE VTT VTTLF _HV _HV _HV _PE _PE _PE _PE _PE _MI _MI _MI _MI VTTLF VTTLF VTTLF U T U T U T U0 T0 U T U T U T U T U T V U V U T V U F H0 0 F0 K V U V U U H F H L 0V XF V M_K 0V MI VTTLF VTTLF VTTLF UVKX-P 0 U0VKX-P UVKX-P 0 U0VKX-P +.0V_P 0UVMX-P 0 U0VKX-P U0VKX-P 0UVMX-P 0UVMX-P E0 U0VKX-P +_PE 0 K MK00L--F-P 0 U0VKX-P +.V_U R0 0RJ--P R0 RF-P T0 T0UVM-LP R0 0 0UVMX-P 0RJ--P +.0V_P R0 0R-0-U-P 0UVMX-P +_PE R0 0R-0-U-P U0VKX-P +.V_RUN +.0V_P R0 0R-0-U-P R0 0R-0-U-P +.V_RUN U0VKX-P X0 00 NTI-M-P-U-NF UVKX-P UVKX-P 0 UVKX-P <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. antiga-power/filter(/) ize ocument Number Rev ustom lba iscrete ate: Monday, March, 00 heet of

16 I = MEMORY +0.V_R_VTT 0 UVKX-P +.V_U 0 U0VKX-P UVKX-P U0VKX-P UVKX-P M Q#[..0] M Q[..0] M M[..0] M Q[..0] M [..0] Layout Note: Place near M U0VKX-P Layout Note: Place one cap close to every pullup resistors terminated to +0.V_R_VTT. 0 UVKX-P U0VKX-P 0 UVKX-P U0VKX-P 0 UVKX-P 0 UVKX-P 0 UVKX-P U0VKX-P UVKX-P 0 UVKX-P UVKX-P UVKX-P +V_R_MH_REF U0VKX-P UVKX-P T0 T0UVM-LP UVKX-P M # M #0 M # UVKX-P UVKX-P M_OT0 M_OT M 0 M M M M M M M M M M 0 M M M M M # M #0 M # M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M Q0 M Q M Q M Q M Q M Q M Q M Q M_OT0 M_OT U0VKX-P M /P 0 / Q0 Q Q Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q 0 Q0 Q Q Q /Q0 /Q /Q /Q /Q /Q /Q /Q Q0 Q Q 0 Q Q Q Q Q OT0 OT VREF 0 N Height.mm R-00P-0-U.00. /R 0 /WE 0 / /0 0 / KE0 KE 0 K0 0 /K0 K /K M0 0 M M M M 0 M M 0 M L VP 0 00 N#0 0 N# N# N#0 0 N#/TET V V V V V V V 0 V 0 V V V V N 0 M_LK_R0 M_LK_R#0 M_LK_R M_LK_R# M M0 M M M M M M M M M M M M M M IH_MT IH_MLK +.V_U L X00 M R# M WE# M # M_0# M_# M_KE0 M_KE M_LK_R0 M_LK_R#0 M_LK_R M_LK_R# IH_MT,,0, IH_MLK,,0, PM_EXTT#0 0 UVKX-P M M M M +.V_RUN M_OT0 M_0# M # M R# M_OT M_# M # M WE# M 0 M M M <ore esign> M_LK_R0 M_LK_R#0 M_LK_R M_LK_R# 0 U0VKX-P Layout Note: Place these resistors close to M, all trace length Max=.". RN0 RNJ--P RN0 RNJ--P RN0 RNJ--P RN0 RNJ--P 0 UMMY- +0.V_R_VTT put near connector RN0 RNJ--P M_KE0 M # M R RJ--P RN0 RNJ--P RN0 M M M 0 M #0 M M M M_KE Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RII-OIMM LOT ize ocument Number Rev ustom lba iscrete ate: Monday, March, 00 heet of 0 UMMY- RNJ--P UMMY- UMMY-

17 I = MEMORY +0.V_R_VTT UVKX-P +.V_U UVKX-P U0VKX-P UVKX-P 0 U0VKX-P M Q#[..0] M Q[..0] M M[..0] M Q[..0] M [..0] Layout Note: Place near M U0VKX-P U0VKX-P Layout Note: Place one cap close to every pullup resistors terminated to +0.V_R_VTT. UVKX-P UVKX-P UVKX-P 0 U0VKX-P UVKX-P U0VKX-P 0 UVKX-P UVKX-P UVKX-P 0 UVKX-P UVKX-P UVKX-P 0 UVKX-P T0 T0UVM-LP UVKX-P +V_R_MH_REF 0 UVKX-P 0 UVKX-P M # M #0 M # M_OT M_OT M 0 M M M M M M M M M M 0 M M M M M # M #0 M # M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M Q0 M Q M Q M Q M Q M Q M Q M Q M_OT M_OT 0 U0VKX-P M /P 0 / Q0 Q Q Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q 0 Q0 Q Q Q Q0# Q# Q# Q# Q# Q# Q# Q# Q0 Q Q 0 Q Q Q Q Q OT0 OT VREF NP NP NP NP Height mm R-00P--P R# 0 WE# 0 # 0# 0 # KE0 KE 0 K0 0 K0# K K# 0 M0 M M M M 0 M M 0 M L VP 0 00 N#0 0 N# N# 0 N#0 N#/TET V V V V V V V 0 V 0 V V V V N 0 N 0 M_LK_R M_LK_R# M_LK_R M_LK_R# M M0 M M M M M M M M M M M M M M IH_MT IH_MLK L X00 +.V_U PM_EXTT# M R# M WE# M # M_# M_# M_KE M_KE M_LK_R M_LK_R# M_LK_R M_LK_R# IH_MT,,0, IH_MLK,,0, +.V_RUN M M M M M_OT M_# M 0 M 0 M #0 M WE# M # <ore esign> 0 UVKX-P M_LK_R M_LK_R# M_LK_R M_LK_R# 0 U0VKX-P 0 UMMY- +.V_RUN put near connector Layout Note: Place these resistors close to M, all trace length Max=.". RN0 RNJ--P RN0 RNJ--P RN0 RNJ--P +0.V_R_VTT RN0 RNJ--P RN0 RNJ--P M_KE M M M M M M M # M R# M_OT M_# M M M # M M_KE Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RII-OIMM LOT ize ocument Number Rev ustom lba iscrete ate: Monday, March, 00 heet of 0 UMMY- UMMY- RN0 RNJ--P RN0 RNJ--P UMMY-

18 I = IH 0 P0VJN-P IH_RTX R 0MRJ-L-P IH_RTX X0 X0 000 X0 000 X-KHZ-PU 0 P0VJN-P LP_LFRME# LP_L LP_L LP_L LP_L0 0RJ--P 0RJ--P 0RJ--P 0RJ--P 0RJ--P R R R R R0 LP_LFRME#_IN LP_L_IN LP_L_IN LP_L_IN LP_L0_IN For MINIR debug board. LP_LFRME#_IN LP_L_IN LP_L_IN LP_L_IN LP_L0_IN IH_Z_OE_ITLK IH_Z_OE_YN IH_Z_OE_RT# IH_OUT_OE H O R R R R +.V_RUN +RT_ELL X0 000 T_IRXN0_HTXN0_ T_IRXP0_HTXP0_ T_ITXN0_HRXN0 T_ITXP0_HRXP0 T_IRXN_OTXN_ T_IRXP_OTXP_ T_ITXN_ORXN T_ITXP_ORXP +RT_ELL R 0KRF-L-P 0 U0VKX-P R 0KRF-L-P IH_RTRT# Place within 00 mil of. RJ--P RJ--P RJ--P RJ--P 0 U0VKX-P R RF-L-P TP0 0 P-OPEN IH_IN_OE 0 0U0VKX-P 0 0U0VKX-P 0 0U0VKX-P 0 0U0VKX-P IH_RTRT# RTRT# M_INTRUER# IH_INTVRMEN LN00_LP R PIO 0KRJ--P LN_OMP Z_IT_LK Z_YN_R Z_RT#_R Removed X0 000 Z_TOUT_R T_LE# T_ITXN0_HRXN0_ T_ITXP0_HRXP0_ T_ITXN_ORXN_ T_ITXP_ORXP_ OF U0 RTX RTX RTRT# F0 RTRT# INTRUER# INTVRMEN LN00_LP E LN_LK LN_RTYN F LN_RX0 LN_RX LN_RX LN_TX0 LN_TX E LN_TX 0 LN_OK#/PIO LN_OMPI LN_OMPO F H_IT_LK H H_YN E H_RT# F H_IN0 H_IN H H_IN E H_IN H_OUT RT LP LN / LN PU IH H_OK_EN#/PIO E H_OK_RT#/PIO TLE# J T0RXN H T0RXP F T0TXN T0TXP H TRXN J TRXP TTXN F TTXP IHM-P-NF T FWH0/L0 FWH/L FWH/L FWH/L FWH/LFRME# LRQ0# LRQ#/PIO 0TE 0M# PRTP# PLP# FERR# PUPWR INNE# INIT# INTR RIN# NMI MI# TPLK# THRMTRIP# PEI TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP T_LKN T_LKP TRI# TRI K K L K K J J N J J E J F E L F F H H J F H J E0 F0 H J J H LP_L0 LP_L LP_L LP_L H_PRTP# H_FERR#_R H_THERMTRIP_R LP_L[0..] LP_LFRME# K0TE H_0M# H_PRTP#,, H_PLP# R0 RJ--P H_PWROO,0 H_INNE# H_INIT# H_INTR H_NMI H_MI# H_TPLK# H_THERMTRIP_ R0 RF-L-P R0 0RJ--P Placed Within " from. LK_PIE_T# LK_PIE_T TRI R0 RF-L-P Place within 00 mils from. LP_L[0..] +.V_RUN R0 0KRJ--P +.0V_P R0 RJ--P R0 0KRJ--P +.V_RUN +.0V_P R0 RJ--P H_FERR# KRIN# H_THRMTRIP#,,,0, IH_Z_OE_ITLK Removed X0 000 E0 P0VN-P Lay Out lose U0 +RT_ELL R 0KRF-L-P R0 0KRF-L-P IH_INTVRMEN LN00_LP integrated Vccus_0,Vccus_,VccL_ INTVRMEN High=Enable Low=isable integrated VccLan_0VccL_0 LN00_LP High=Enable Low=isable <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. R0 MRJ--P M_INTRUER# IH-LN/H/T/LP(/) ize ocument Number Rev ustom lba iscrete ate: Monday, March, 00 heet of

19 I = IH OF U0E 0 E E E E E E E0 E E E E E F F F F H F F F F F 0 H H H H H H H H H H J J J J 0 E E E E E E E E F F F H H H H IHM-P-NF H J J J K K L L L L L L L M M M M M M M M M N N N N N N N N N N P P P P P P P P P P P P R R R R R R R R R T T T T T T T U U U U U U U U U V V V V V V V V W W W Y Y Y Y Y H F H H J J J J Mini ard LN New ard IH_N IH_N IH_N IH_N,,,,0 +.V_LW PLT_RT# U_O# U_O# U_O# U_O# PIE_IRXN_MTXN PIE_IRXP_MTXP PIE_ITXN_MRXN PIE_ITXP_MRXP PIE_IRXN_RTXN PIE_IRXP_RTXP PIE_ITXN_LRXN PIE_ITXP_LRXP 0 PIE_IRXN_NTXN 0 PIE_IRXP_NTXP 0 PIE_ITXN_NRXN 0 PIE_ITXP_NRXP TP0 TP0 TP0 TP0 PLTRT_IH_ELY# NTF PIN PLT_RT# +.V_RUN RP0 0 U_O#0 U_O# U_O# U_O# RN0KJ-L-P R 0RJ--P TP0 TP U_O#0 U_O# U_O# UVKX-P UVKX-P UVKX-P UVKX-P UVKX-P UVKX-P U0 Y TP TP N LV0W--P R0 0RJ--P R RF-L-P +.V_LW PI_PLTRT# PIE_ITXN_MRXN_ PIE_ITXP_MRXP_ PIE_ITXN_LRXN_ PIE_ITXP_LRXP_ PIE_ITXN_NRXN_ PIE_ITXP_NRXP_ X0 000 U0 N PERN N PERP P PETN P PETP L PERN L PERP M PETN M PETP J PERN J PERP K PETN K PETP PERN PERP H PETN H PETP +.V_LW OF PI-Express irect Media Interface PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# MI0RXN V MI0RXP V MI0TXN U MI0TXP U MIRXN Y MIRXP Y MITXN W MITXP W MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP E PERN MI_LKN T E PERP MI_LKP T F PETN F PETP MI_ZOMP F MI_IROMP F PERN/LN_RXN PERP/LN_RXP UP0N PETN/LN_TXN UP0P PETP/LN_TXP UPN UPP PI_LK UPN PI_# PI_0# UPP F PI_#/PIO/LPIO UPN UPP PI_MOI UPN E PI_MIO UPP U_O#0 UPN N U_O# O0#/PIO UPP N U_O# O#/PIO0 UPN N U_O# O#/PIO U W UPP W P U_O# O#/PIO UPN Y M U_O# O#/PIO UPP Y N U_O# O#/PIO UPN W M U_O# O#/PIO0 UPP W M U_O# O#/PIO UPN V N U_O# O#/PIO UPP V N U_O#0 O#/PIO UP0N U P U_O# O0#/PIO UP0P U P O#/PIO UPN U U_RI_PN UPP U URI URI# IHM-P-NF PI RN0 U0 0 E E E0 0 F F E F0 0 F 0 F F H H 0 H J PIRQ# E PIRQ# J PIRQ# PIRQ# RNKJ--P U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN0 U_PP0 OF PI U_O# U_O# U_O#0 U_O# MI_IRXN0_MTXN0 MI_IRXP0_MTXP0 MI_ITXN0_MRXN0 MI_ITXP0_MRXP0 MI_IRXN_MTXN MI_IRXP_MTXP MI_ITXN_MRXN MI_ITXP_MRXP MI_IRXN_MTXN MI_IRXP_MTXP MI_ITXN_MRXN MI_ITXP_MRXP MI_IRXN_MTXN MI_IRXP_MTXP MI_ITXN_MRXN MI_ITXP_MRXP MI_IROMP_R REQ0# F NT0# REQ#/PIO0 NT#/PIO REQ#/PIO F NT#/PIO F REQ#/PIO E NT#/PIO F LK_PIE_IH# LK_PIE_IH U_PN0 U_PP0 U_PN U_PP U_PN U_PP TP0 TP0 U_PN U_PP TP TP U_PN U_PP U_PN 0 U_PP 0 TP0 TP TP TP U_PN0 0 U_PP0 0 U_PN U_PP /E0# /E# /E# /E# IR# PR E PIRT# R EVEL# PERR# E PLOK# ERR# J TOP# TR# F FRME# PLTRT# PILK PME# R Interrupt I/F IHM-P-NF PIRQE#/PIO H PIRQF#/PIO K PIRQ#/PIO F PIRQH#/PIO U U U PI_REQ0# PI_NT0# PI_REQ# PI_NT# PI_REQ# PI_NT# PI_REQ# PI_NT# PI_IR# PIRT# PI_EVEL# PI_PERR# PI_PLOK# PI_ERR# PI_TOP# PI_TR# PI_FRME# PI_PLTRT# IH_PME# MINI R PI_PIRQE# PI_PIRQF# PI_PIRQ# PI_PIRQH# +.V_RUN luetooth New ard ard Reader MER <ore esign> LK_PI_IH TP0 PI_PIRQF# PI_TR# PI_REQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_REQ0# PI_PIRQH# PI_TOP# PI_PLOK# PI_IR# PI_PERR# PI_ERR# PI_PIRQE# PI_PIRQ# PI_PIRQ# PI_NT0# R0 KRJ--P PI_# R KRJ--P PI_NT# R0 KRJ--P OOT IO trap PI_NT#0 PI_# 0 swap override strap PI_NT# R0 RF-L-P TP0 TP TP0 0 PI U Pair 0 0 U REERVE MINI R OOT IO Location PI LP(efault) low = swap override enable high = default U U evice REERVE LUETOOTH NEW R REERVE REERVE ard Reader MER +.V_RUN Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IH-PI/PIE/MI/U/N(/) ize ocument Number Rev ustom lba iscrete ate: Monday, March, 00 heet of RN0 RN0 RN0 RNKJ--P RN0 RNKJ--P RN0 PI_EVEL# PI_REQ# PI_FRME# PI_REQ# RNKJ--P RNKJ--P RNKJ--P

20 I = IH +.V_LW +.V_RUN R0 0KRJ--P RN00 RN00 RN0KJ--P RN00 RN00 RNKJ--P R0 0KRJ--P RNKJ--P R0 0KRJ--P RN0KJ--P R00 KRJ--P R00 KRJ--P R00 0KRJ--P R0 0KRJ--P R0 0KRJ--P R00 0KRJ--P M_T M_LK LINKLERT# ME_E_T ME_E_LK PIE_WKE# PM_TLOW#_R M_LERT# IH_RI# EMI# H_TP_PU# H_TP_PI# PM_LKRUN# INT_ERIRQ PIO EI# EWI# LKTREQ# 0 M_LK 0 M_T TP0, ITP_REET# PM_YN# H_TP_PI# H_TP_PU# PM_LKRUN#,0 PIE_WKE# INT_ERIRQ THERM_I#, VTE_PWR EI# TP00 R00 0RJ--P EWI# EMI# TP00 TP0 TP0 TP00 TP00 TP00 TP00 TP0 LKTREQ# TP0 TP00 _PKR MH_IH_YN# TP0 LINKLERT# ME_E_LK ME_E_T IH_RI# U_TT# ITP_REET# M_LERT# H_TP_PI# H_TP_PU# PIE_WKE# INT_ERIRQ VTE_PWR IH_TP EI# PLTRT_ELY#_ EWI# EMI# PIO PIO PIO PIO PIO0 PIO PIO PIO LK_EL0 LK_EL PIO itpm_en IH_TP OF U0 MLK MT E LINKLERT#/PIO0/LPIO MLINK0 MLINK F RI# R U_TT#/LPP# Y_REET# M PMYN#/PIO0 MLERT#/PIO TP_PI# E TP_PU# L LKRUN# E0 WKE# M ERIRQ J THRM# VRMPWR 0 T TH/PIO H TH/PIO TH/PIO PIO LN_PHY_PWR_TRL/PIO ENERY_ETET/PIO E TH0/PIO K PIO F PIO0 J LOK/PIO PIO PIO L TLKREQ#/PIO E LO/PIO TOUT0/PIO F TOUT/PIO H PIO PIO/LPIO M PKR J MH_YN# TP H0 PWM0 J0 PWM J PWM IHM-P-NF M T PIO locks Y PIO Power MT MI PIO ontroller Link T0P/PIO TP/PIO TP/PIO TP/PIO LK LK ULK LP_# LP_# LP_# _TTE#/PIO PWROK PRLPVR/PIO TLOW# PWRTN# LN_RT# RMRT# K_PWR LPWROK LP_M# L_LK0 L_LK L_T0 L_T L_VREF0 L_VREF L_RT0# L_RT# PIO/MEM_LE PIO0/U_PWR_K PIO/_PREENT PIO/WOL_EN H T0P F TP E TP 0 TP H F P E 0 0 M R 0 R R F F F 0 IH_ULK _LP_# PM_LP_# PIO PM_PWROK PM_TLOW#_R LN_RT# M_PWROK PM_LP_M# L_VREF0_IH PIO PIO0 PIO LK_M_IH LK_M_IH IH_ULK PM_LP_#,,0 TP0 TP00 PRLPVR, PM_PWRTN# RMRT#_K K_PWR M_PWROK TP00 L_LK0 L_T0 L_RT#0 TP00 TP0 TP0 +.V_RUN R0 KRF-P 00 U0VKX-P R0 RF--P T0P TP TP TP PM_PWROK PRLPVR LN_RT# RMRT#_K M_PWROK R0 RN00 RN0KJ--P R0 0KRJ--P R00 00KRJ--P R0 0RJ--P R00 0KRJ--P 0RJ--P +.V_RUN PM_PWROK,, +.V_RUN itpm elect(not trap Pin) itpm_en R0 00KRJ--P itpm_en R00 0KRJ--P LK_EL0 LK_EL itpm elect(not trap Pin) LK en select LK_EL0 0 = isable isable X X R00 R0 eligo = Enable 0KRJ--P 0KRJ--P Realtek 0 I 0 R0 0KRJ--P +.V_RUN LL_EL PLTRT_ELY#_ R00 PLTRT_ELY# 0RJ--P +.V_LW U00 _LP_# PM_LP_# Y N LV0W--P R00 0RJ--P PLTRT_ELY#, PM_LP_#,,0,,,,,0 RN00 RNKJ--P,,, IH_MT M_LK U00 N00PT M_T IH_MLK,,, <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IH-PIO/PM/L(/) ize ocument Number Rev ustom lba iscrete ate: Monday, March, 00 heet 0 of

21 +RT_ELL 0R-0-U-P R 0R-0-U-P +.0V_P R 0R-0-U-P +.0V_P R _V_PU_IO 0R-0-U-P +.V_LW R0 0RJ--P R +.V_LW R 0R-0-U-P OF +.0V_P U0F R I = IH 0 RT _0 VREF_0 _0 VREF m _0 VREF_ E VREF_U m _0 _0 E _0 F 0 L 0 L 0 L 0 L 0 L *Within a given well, VREF needs to 0 L V_MIPLL_IH_0 +.V_RUN be up before the corresponding.v rail 0 M 0 M L0 E V_MIPLL_IH_0 0 P E +.V_RUN +V_RUN +.V_LW +V_LW 0 P OIL-UH--P E 0 T E 0 T E 0 U F 0 U 0 R 0 R0 0 V MK00L--F-P 0RJ--P MK00L--F-P 0RJ--P H 0 V H 0 V J VREF_0 VREF _0 V J 0 V K MI 0 V K UVKX-P 0 L UVKX-P m MIPLL R L L M 0m MI W MI Y M N N m V_PU_IO V_PU_IO _V_PU_IO +.V_RUN +.V_PIE_IH N P +.V_RUN R0 P R _ J R 0RJ--P R 0 R T T F0 T +.V_RUN T 0 U U V F V +.V_RUN U +.V_RUN +TPLL W J W +.V_RUN L0 _ J 0 K _ K U0VKX-P Y R0 L-0UH--P Y _LN m H J 0R-0-U-P J TPLL m m UH J U_0[] U_0 TP0 U_0[] U_0 F TP0 R0 E U_[] U_ +.V_RUN F +.V_RUN U_[] 0R-0-U-P U_ F H J U_ +.V_RUN U U_ E U_ E R F _LN_PLL 0 0R-0-U-P U_ F H0 J0 U_ T +.V_LW U_ T U_ T U_ T _U U_ T U_ T 0R-0-U-P U_ U U_ U U_ V 0 U_ V +.V_RUN U_ W R0 U_ W V_U_0 U_ Y U_ Y IH_U_ 0R-0-U-P U_ T J UPLL m L_0 U0VKX-P 0 U0VKX-P UVKX-P UVKX-P U0VKX-P U0VKX-P U0VKX-P m 0UVMX-P 0UVKX-P ORE K K UVKX-P U0VKX-P m 0UVMX-P 0 UVKX-P 0 U0VKX-P U0VKX-P 0 U0VKX-P P 0m 0UVMX-P T0 T0UVM-LP P_ORE U0VKX-P 0UVMX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P PI 0 U0VKX-P 0 U0VKX-P RX 0 0UVMX-P 0 U0VKX-P U0VKX-P U0VKX-P PU TX 0 UVKX-P UVKX-P m 0UVMX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P PU m 0UVKX-P L_ UVKX-P U0VKX-P L_ L_ m U ORE 0 U0VKX-P U0VKX-P U0VKX-P LN0 0 LN_0 LN_0 U_0[] <ore esign> U0VKX-P _LN_ LN_ m LN_ U_[] +.V_RUN _LN_PLL LNPLL m Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, LN_ Taipei Hsien, Taiwan, R.O.. LN_ +.V_RUN E +.V_RUN LN_ E R0 UVKX-P LN L_ m IH-POWER(/) LN_ 0R-0-U-P ize ocument Number Rev IHM-P-NF ustom U0VKX-P U0VKX-P lba iscrete ate: Monday, March, 00 heet of LN POWER 0m U0VKX-P 0 U0VKX-P

22 I = UIO +.V_RUN IH_Z_OE_ITLK 0 P0VN-P R0 0KRJ--P MP_MUTE# +.V_RUN +.V_RUN IH_Z_OE_ITLK IH_IN_OE IH_OUT_OE IH_Z_OE_YN IH_Z_OE_RT# U_MI_IN0 X0 000 lose to codec U0VKX-P MP_MUTE# 0 UVKX-P lose to codec U_VORE IH_Z_OE_ITLK IH_IN_OE_0 IH_OUT_OE IH_Z_OE_YN IH_Z_OE_RT# U_MI_LK U_MI_IN0 MP_MUTE# PUMP_PN PUMP_PP U_ENE_ U_ENE_ U_EXT_MI_L U_EXT_MI_R U_VREFOUT_ U_HP_JK_L_ U_HP_JK_R_ U_INT_MI_R_L U_VREFOUT_ U_PK_L+ U_PK_L- U_PK_R- U_PK_R+ U0VKX-P +V U0VKX-P U_N U_P_EEP U_EXT_MI_L 0 U_EXT_MI_R 0 U_PK_L+ U_PK_L- U_PK_R- U_PK_R+ U_P_EEP Trace width> mils +V_RUN R 0RF-P R0 0RF-P U_N +PV U_VREFOUT_ 0 U_HP_JK_L U_HP_JK_R X0 000 R0 UMMY- INT_MI_L_R 0 U0VKX-P U0VKX-P U_HP_JK_R +V_RUN U_HP_JK_L 0 U_HP_JK_R 0 _PKR_R K_EEP_R R0 KRF--P X0 000 X From U_HP_JK_L _PKR 0 K_EEP From E U_MI_LK_ E0 P0VJN-P 0 U0VKX-P 0 UVKX-P R0 RJ--P 0UVMX-P 0 U0 V_ORE V V V PV V_IO PV ENE_ H_ITLK ENE_ H_I HP0_PORT L H_O HP0_PORT R VREFOUT OR_F H_YN HP_PORT L H_RT# HP_PORT R PORT L PORT R 0 VREFOUT_ MI_LK/PIO MI0/PIO PKR_PORT L+ 0 PKR_PORT L- MI/PIO0/PIF_OUT_ PKR_PORT R- PIF_OUT_0 PKR_PORT R+ EP P- P+ PORT_E_L PORT_E_R PORT_F_L PORT_F_R P_EEP MONO_OUT L0 0RJ--P U0VKX-P U0VKX-P R0 KRJ--P U0VKX-P 0 0UVMX-P L0 0RJ--P L0 0RJ--P R0 0KRF-L-P U_MI_LK_Y 0RJ--P R0 +.V_RUN U0 Y OE# N LV-P R0 RJ--P U_MI_LK U_N 0 P N HXNLXYX-P P VREFFILT V- VRE U_P U_VREFFLT U_V_ U_VRE 0 UVKX-P 0 0UVMX-P 0 0UVMX-P 0 UVKX-P U_N U_N U_N U_N +V_LW P0M-P Q0 Q0 P0M-P R 00KRJ--P Q0 P0M-P P0M-P Q0 lose to codec HP_OE_MUTE zalia I/F EMI IH_OUT_OE IH_Z_OE_OUT R0 RJ--P 0 U0VKX-P U_ENE_ +V U_N R KRF-P 000P0VJN-P-U lose to Pin R0 0KRF-L-P R KRF-L-P U_HP_J# 0 EXT_MI_J# 0 U_ENE_ MP_MUTE# +V U_N R KRF-P R 0KRF-L-P lose to Pin R Q0 N00-F-P 0R-0-U-P R 0R-0-U-P R 0R-0-U-P U_N <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. UIO OE H ize ocument Number Rev ustom lba iscrete ate: Monday, March, 00 heet of

23 (lank) <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. (Reserve) ize ocument Number Rev ustom lba iscrete ate: Monday, March, 00 heet of

24 (lank) <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. (Reserve) ize ocument Number Rev ustom lba iscrete ate: Monday, March, 00 heet of

25 I = LOM +V +V U0VKX-P LN_TX/RX# LN_TX/RX# +V 0 0 U0VKX-P U0VKX-P U0VKX-P Lay out close to Pin. MI+ MI- MI0+ MI0- +.V_LN MI0+ MI0- Use single trace feedback to PIN.. MI+ MI- TRL +V RET R0 KRF-P 0 U0 V MIP0 MIN0 N# MIP MIN N N# N# V N# N# N VTRL LNX LNX +.V_LN RET VTRL N# N# KXTL KXTL N#0 0 N# LE0 V V N HIP HIN REFLK_P REFLK_M VTX HOP HON NTX N# N# 0 V LE/EEK LE/EEI/UX LE/EEO EE N V V IOLTE# PERT# LNWKE# LKREQ# 0 RTL0EL-R-P +V LE/EEK LE/EEI LE/EEO EE +V +.V_LN LN_IOLTE# R0 0RJ--P R0 0RJ--P LN_LKREQ# LN_LINK00# LN_LINK0# R0 KRJ--P +.V_RUN R0 KRJ--P PLT_RT#,,,,0 PIE_WKE# 0,0 U0VKX-P LN_LINK00# LN_LINK0# +.V_LN LNX LNX 0 U0VKX-P 0 U0VKX-P Place close to PIN 0,, 0, 0 U0VKX-P U0VKX-P U0VKX-P R0 0MRJ-L-P +V PIE_IRXN_RTXN_LN PIE_IRXP_RTXP_LN 0 U0VKX-P U0VKX-P PIE_IRXN_RTXN PIE_IRXP_RTXP X P0VJN--P X0 LNX LNX XTL-MHZ-0-P X P0VJN--P +.V_LW UVKX-P UVKX-P R0 0R-0-U-P Q0 Lay out close to Pin. Max current: m LK_PIE_LN# LK_PIE_LN PIE_ITXN_LRXN PIE_ITXP_LRXP +.V_LN EE LE/EEK LE/EEI LE/EEO R0 KRJ--P U0 K I O OR N TN-H--P +.V_LN X V_LN U0VKX-P PM_LN_ENLE R0 0KRJ--P R0 KRF-P U0VKX-P Q0 N00-F-P O0-P. Rds= 0m ohm U0VKX-P 0 U0VKX-P 0 U0VKX-P UVKX-P 0 UVKX-P 0UVMX-P <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. LN Realtek-RTL0EL ize ocument Number Rev ustom lba iscrete ate: Monday, March, 00 heet of