CPU MEROM 34W NORTH BRIDGE. Nvdia NB8 CRESTLINE PAGE 24,25,26,27,28,29,30,31. Debug Conn. PAGE 70 SOUTH BRIDGE ICH8M TPM 1.2 INFINEON SLB9635 PAGE 76

Size: px
Start display at page:

Download "CPU MEROM 34W NORTH BRIDGE. Nvdia NB8 CRESTLINE PAGE 24,25,26,27,28,29,30,31. Debug Conn. PAGE 70 SOUTH BRIDGE ICH8M TPM 1.2 INFINEON SLB9635 PAGE 76"

Transcription

1 0 lock iagram * ystem etting * 0_PU-Merom(HOT) 0_PU-Merom(PWR) U ONN * I ROM * Fv/c 0 * 0 0_RETLINE(HOT) 0 0_RETLINE(MI & F) 0 0_RETLINE(RPHI) 0 0_RETLINE(R) 0 _RETLINE(PWR) _RETLINE(PWR) _RETLINE() LE * & T IN * ebug ONN. * T-H & O et R Mx x PE, R Mx x PE, PU MEROM W PE, * _-IHM() _-IHM() _-IHM() _-IHM(PWR) * 0_R O-IMM0 _R O-IMM _R TERMINTION * M()-PIE M()-Memory IF M()-F_VRM_ M()-F_VRM_ M()-&ecoupling M(()-LV&V&TV ()-MIO&PIO ()- RT LV & INVERTER ONNETOR FINER PRINT TV OUT ONN & VI * THER ENOR & FN * LOK EN-ILPRLF-T * Power on & Reset Freq. IHRE * LN-L M & RJ+ * MINI R-TV/Windigo MINI R-Robson MINI R-Kedron * R-R() REW HOLE * TPM PRIN_P T POWER EQUENE 0 POWER_VORE POWER_YTEM POWER_I/O_.V &.0V POWER_I/O_R & VTT POWER_I/O_+VO & +.V POWER_V_ORE & +.V POWER_+VFX (Empty) POWER_HUTOWN# (Empty) POWER_HRER POWER_PI(Empty) 0 POWER_ETET POWER_LO WITH POWER_FLOWHRT POWER_PROTET POWER_INL History L RT PE PE TV-OUT VI PE PE I ROM PE in ard Reader PE PE Nvdia N PE,,,,,,0, ebug onn. PE 0 TPM. INFINEON L E ITE IT Internal K PE 0 PE Touch Pad Ricoh R MINIRWindigo PE PE U Port X PE luetooth PE MO amera PE Finger Print PE PE 0 PE, PE NORTH RIE RETLINE OUTH RIE IHM PE,,,0,,, PE,,, R O-IMM0 R O-IMM0 R T H O PE PE MINIR Kedron MINIR Robson LNttansic L NEWR PE 0 PE ZLI OE Realtek L0 M PE PE 0,, MINIR TV PE, et JM0 PE PE LOK EN ILPRLF-T PE PE PE PE THERML ONTROL PE PE UIO MP EXT MI INT MI PE PE PE 0 R-R() in R REER NEWR * OE-L0 UIO MP & JK * ITTE Touch Pad & K UTek omputer IN. N ustom Fc Title : lock iagram Engineer: ajun_ho,, 00 ate: heet of.0

2 PIO E_ITTE ETTIN Pin 0 PWM/P PWM/P PWM/P PWM/P P Pin Name PWM0/P0 PWM/P PWM/P PWM/P RX/P0 TX/P MLK0/P MT0P ignal Name / FN_PWM / / H_LE_UP# PWR_LE_UP# / L_KOFF# NUM_LE P_LE RL_LE M0_LK M0_T Type O O O O O O O I/0 I/0 Pin Pin Name PL0 PL PL PL PL PH0 PH PH PH PH PH PH PH PI0 PI ignal Name PM TTE# VU_ON U_PWR VRM_PWR PM_PWRTN# U_E# PU_VRON IH-M PIO ETTIN / / / / / PM_RMRT# PM_PWROK LL_YTEM_PWR Type I I O O O O O O O O I Pin R REER lock enerator 0/P 0TE O Pin Pin Name ignal Name Type Pin Pin Name ignal Name Type Pins Pin Name evice KRT#/P R_IN# O PIO0/M_UY# PM_MUY# I PIO0/O# U_ON_O0# I PILK TPMPI P THRO_PU O J PIO/TH T_ET# I PIO/O# U_ON_O# I PILK ardus R LKOUT/P0 J_W# O F PIO/PIRQE# PI_INTE# I E PIO/O# U_ON_O# I ELPIEX0_L#PILK E ITE MLK/P M_LK I/0 PIO/PIRQF# PI_INTF# I F PIO/O# U_ON_O# I ITP_EN/PILK_F0 IH 0 MT/P M_T I/0 F PIO/PIRQ# PI_INT# I E PIO0/REQ# PI_REQ# OT_MHzL Miniard P / PIO/PIRQH# PI_INTH# I PIO/NT# PI_NT# OTT_MHzL Miniard TMRI0/WUI/P IN_O# I J PIO/TH IO_RE I/O PIO/REQ# PI_REQ# FL/U_MHz IH P OP_# O H PIO/TH WLN_LE_EN I F PIO/NT# PI_NT# PIeT_L MH TMRI/WUI/P T_IN_O# I E PIO EXT_MI# I PIO/REQ# PI_REQ# 0 PIe_L MH KKOUT/P / PIO/WOL_EN PIO I 0 PIO/NT# PI_NT# PIeT_L NP RI#/WUI0/P0 U# I J PIO0/LPIO / PIe_L NP RI#/WUI/P U# I PIO/MLERT# M_LERT# I PIeT_L Miniard(Rob) 0 LPRT#/WUI//P UF_PLT_RT# I PIO K_I# I PIe_L Miniard(Rob) EI#/P EXT_I# O H PIO/LN_OK# / PIeT_L IH P RF_ON_W# I F PIO/LPIO / PIe_L IH INT/P PM_LP_M# I E0 PIO/TP_PI# TP_PI# I/O PIeT_L Miniard TH0/P FN0_TH I J PIO/PRLPVR PM_PRLPVR O PIe_L Miniard TH/P OLOREN# O PIO/TH0 WLN_ON# O TLKT_L IH /PE0 T# I H PIO / TLK_L IH /PE INTERNET# I J0 PIO/TP PO O PUITPT_L / PIeT_L LN /PE MRTHON# I E PIO0 TLE_ON O PUITP_L / PIe_L LN 0 /PE ITP# I J PIO/T0P PU_elect I FIX/L_T/PIeT_L0 MM PWRW/PE PWR_W# I 0 PIO/LOK / OT_MHzL MM WUI/PE / E PIO/LRQ# LP_RQ# I/O PEREQ# / PIeT_L ET LPP#/WUI/PE / J PIO/LPIO0 / 0 PEREQ# / PIe_L ET LKRUN#/WUI/PE PM_LKRUN# O PIO/TP_PU# TP_PU# O PEREQ# Neward 0 PLK0/PF0 / H PIO/_TTE# PM TTE# O PEREQ# Miniard PT0/PF / H PIO/QRT_TTE0 T_ON# O 0 PIeT_L Neward PLK/PF / I/0 PIO/QRT_TTE _# O PIe_L Neward PT/PF / I/0 PIO/O# U_O# I PUT_LF MH PLK/PF TP_LK PIO0/O# NEWR_O# I PU_LF MH PT/PF TP_T J PIO/O# U_O# I PUT_L0 PU PLK/PF / H PIO/LKRUN# PM_LKRUN# O PU_L0 PU PT/PF INTNT_ON# I E0 PIO/Z_OK_EN# O X.MHz F/P0 F PIO/Z_OK_RT# X.MHz F/P F PIO/TLKREQ# PO O 0 REF0 IH 0 F/P F F PIO/TP PO O REF/FL/TET_EL X 0 F/P F PIO/TP P_I0 I Title : ystem etting F0/P LIW# I F PIO/LO P_I I Engineer: ajun_ho UTek omputer IN. N F/P / J PIO/TOUT0 P_I I LP0HL/P PMTHERM# O 0 PIO/TOUT / Fc ustom.0,, 00 ate: heet of LP0HL/P _PR_U# I PIO/PUPWR H_PWR O Pin Name PI PI PI K0/PM ignal Name / H_EN# E_LK_EN PI T_LERN PL PL PL / _ON# / U_E# PJ PPE#_E PJ P_HN# Type O O O O O I I O PI evice Kedron et PIE evice LN M-us evice O-IMM 0 O-IMM IEL# us PE(T/R)(p/n) PE(T/R)(p/n) PE(T/R)(p/n) PU Thermal ensor(mx) V Thermal ensor(mx) REQ/NT# PIE evice NEWR LN ILPRLF-T ETTIN 0 0 Robson M-us ddress 000x ( ) 00000x ( 0 ) 0000x ( ) 0000x ( ) Interrupts 0000x ( ) us PE(T/R)(p/n) PE(T/R)(p/n) PE(T/R)(p/n)

3 UTeK OMPUTER IN Title : chematic page name Engineer: ajun_ho ustom Fc,, 00 ate: heet of.0

4 H_#[:] H_T#0 H_REQ#[:0] H_#[:] H_T# H_0M# H_FERR# H_INNE# H_TPLK# H_INTR H_NMI H_MI# T00 T00 H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_REQ#0 H_REQ# H_REQ# H_REQ# H_REQ# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# TPT TPT PU0 J []# # L []# NR# L []# PRI# K []# M []# EFER# N []# RY# J []# Y# N [0]# P []# R0# P []# L []# IERR# P []# INIT# P []# R []# LOK# M T[0]# REET# K REQ[0]# R[0]# H REQ[]# R[]# K REQ[]# R[]# J REQ[]# TRY# L REQ[]# HIT# Y []# HITM# U []# R []# PM[0]# W [0]# PM[]# U []# PM[]# Y []# PM[]# U []# PRY# R []# PREQ# T []# TK T []# TI W []# TO W []# TM Y []# TRT# U [0]# R# V []# W []# []# THERML []# []# PROHOT# V T[]# THRM THRM 0M# FERR# THERMTRIP# INNE# TPLK# LINT0 H LK LINT LK[0] MI# LK[] M RV N RV T RV V RV RV RV RV RV RV F RV0 OKET H E H F E F 0 H F F E 0 H_IERR# TPT XP_PM# H_PREQ# H_TK H_TI H_TO H_TM H_TRT# H_R# H_PROHOT PU ebug Port If not use,mount Ohm. If use,mount Ohm. TPT TPT efault trapping When Not Used XP_PM# H_PREQ# H_TI H_TO H_TM H_R# H_# H_NR# H_PRI# H_EFER# H_RY# H_Y# H_R0# H_INIT# H_LOK# H_PURT# H_R#0 H_R# H_R# H_TRY# H_HIT# H_HITM# T00 PU_THERM_ PU_THERM_ PM_THRMTRIP#, T00 LK_PU_LK LK_PU_LK# T00 +VP +VP R00.Ohm % R00.Ohm % R0 % R0.Ohm % R0 Ohm % R0 R00 Ohm Q00 KOhm% R00 KOhm N00K_T_E +VP +V THRO_PU TL+ I/O Voltage Reference +VP R00 KOhm % R00 KOhm % LK F EL EL EL0 L H 00 H_#[:0] H_TN#0 H_TP#0 H_INV#0 H_#[:] H_TN# H_TP# H_INV# 00 L H H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H L E F E F E E K J J H F K H J H H N K P R L M L M P P P T R L T N L M N PU0 [0]# []# []# []# []# []# []# []# []# []# [0]# []# []# []# []# []# TN[0]# TP[0]# INV[0]# []# []# []# []# [0]# []# []# []# []# []# []# []# []# []# [0]# []# TN[]# TP[]# INV[]# H_OMP0 H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# Zo /L 0.inch/ mils TL_REF R H_OMP0 R00 TLREF OMP[0] KOhm MI U H_OMP TL+ I/O uffer R00 TET OMP[].Ohm H_OMP T00 TPT TET OMP[] Y H_OMP ompensation 00 TET OMP[] 0.UF/0V F T00 TET TPT F E T00 TPT TET PRTP# H_PRTP#,,0 TET PLP# H_PLP# PU_EL0 PWR# H_PWR# PU_EL0 PU_EL EL[0] PWROO H_PWR PU_EL PU_EL EL[] LP# H_PULP# PU_EL E EL[] PI# PM_PI# 0 OKET []# []# []# []# []# []# []# []# [0]# []# []# []# []# []# []# []# TN[]# TP[]# INV[]# []# []# [0]# []# []# []# []# []# []# []# []# []# [0]# []# []# []# TN[]# TP[]# INV[]# H_OMP Y V V V T U U Y W Y W W Y U E 0 E F E F E F 0 TL+ I/O uffer ompensation R00 %.Ohm R0 %.Ohm H_OMP H_OMP H_#[:] H_TN# H_TP# H_INV# H_#[:] H_TN# H_TP# H_INV# R00 %.Ohm R0 %.Ohm H_TK H_TRT# R0.Ohm % R0 Ohm RE OHM /W (00) % UTeK OMPUTER IN. N Title : PU-Merom(HOT) Engineer: ajun_ho ustom Fc,, 00 ate: heet of.0

5 PU +VORE Mid-Frequency apacitors 00 0UF/.V PU +VORE ulk-ecoupling apacitors 00 0UF/.V Place these upper side inside socket cavity on L 00 0UF/.V 0 0UF/.V 00 0UF/.V 0 0UF/.V 00 0UF/.V Place these lower side inside socket cavity on L 0 0UF/.V 0 0UF/.V Place these upper side inside socket cavity on L 00 0UF/.V 0 0UF/.V 0 0UF/.V 00 0UF/.V 0 0UF/.V Place these lower side inside socket cavity on L + E00 0UF/V 0 0UF/.V 0 0UF/.V +VORE E E E0 E E E E E E0 F F F0 F F F F F F PU0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V OKET V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V00 VP VP VP VP VP VP VP VP VP VP0 VP VP VP VP VP VP V V VI[0] VI[] VI[] VI[] VI[] VI[] VI[] VENE VENE 0 0 E E0 E E E E E E0 F F0 F F F F F F0 V J K M J K M N N R R T T V W F E F E F E F E R00 R00 H_VI0 H_VI H_VI H_VI H_VI H_VI H_VI +VORE R00 R00 0OHM 0OHM 0OHM 0OHM 0OHM 0OHM 0OHM 0OHM +VP_P RN00 RN00 RN00 RN00 RN00 RN00 RN00 RN PJP00 MM_OPEN_MIL 00 0.UF/0V 00 0.UF/0V +VORE 00 0.UF/0V 00 0.UF/0V VR_VI0 0 VR_VI 0 VR_VI 0 VR_VI 0 VR_VI 0 VR_VI 0 VR_VI 0 VENE 0 VENE 0 + E00 +.V_ +VP 00UF/.V 0 0.0UF/V PJP00 L_JUMP 0 0UF/.V +.V PU0 V V V V V V V V V V V V V V F V V V V0 V0 V V V V V V V V V V V V V V V V V V V00 V0 V0 V V0 V V0 V V0 V V0 V V0 V V0 V V0 V V0 V V0 V0 V V V V V V V V V E V V E V V E V V E V V E V V0 E V0 V E V V E V V E V V F V V F V V F V V F V V F V V F V V0 F V0 V F V V F V V V V V V V V V V H V V H V V H V V0 H V0 V J V V J V V J V V J V V K V V K V V K V V K V V L V V0 L V0 V L V V L V V M V V M V V M V V M V V N V V N V V N V V0 N V0 V P V V V OKET P P P R R R R T T T T U U U U V V V V W W W W Y Y Y Y E E E E E E E E E F F F F F F F F +VORE Mid-Frequency apacitor Intel: UF * F: 0UF * +VP ecoupling apacitor Intel: 0UF *, 0.UF * F: 00UF *, 0.UF * UTeK OMPUTER IN. N ustom Fc Title : PU-Merom(PWR) Engineer: ajun_ho,, 00 ate: heet of.0

6 UTeK OMPUTER IN Title : chematic page name Engineer: ajun_ho ustom Fc,, 00 ate: heet of.0

7 ROMP For alibrating the F I/O uffer H_ROMP R00.Ohm % OMP For lew Rate ompenssation on the F +VP +VP R00 R00.Ohm.Ohm % % H_OMP H_OMP# Voltage wing For Providing a Reference Voltage to The F ROMP circuits +VP R00 Ohm % H_WIN R UF/0V % +VP R00 KOhm % T 0mils/L 00mils/ mils H_VREF R00 H_VREF R00 00 KOhm 0.UF/0V % H_#[:0] H_PURT# H_PULP# N0 H_#0 E H_# H_#_0 H_# H_#_ H_# H_#_ M H_# H_#_ H H_# H_#_ H H_# H_#_ H_# H_#_ F H_# H_#_ N H_# H_#_ H H_#0 H_#_ M0 H_# H_#_0 N H_# H_#_ N H_# H_#_ H H_# H_#_ P H_# H_#_ K H_# H_#_ M H_# H_#_ W0 H_# H_#_ Y H_# H_#_ V H_#0 H_#_ M H_# H_#_0 J H_# H_#_ N H_# H_#_ N H_# H_#_ W H_# H_#_ W H_# H_#_ N H_# H_#_ Y H_# H_#_ Y H_# H_#_ P H_#0 H_#_ W H_# H_#_0 N H_# H_#_ H_# H_#_ E H_# H_#_ H_# H_#_ H_# H_#_ H_# H_#_ H_# H_#_ H_# H_#_ H_#0 H_#_ H_# H_#_0 H_# H_#_ H_# H_#_ Y H_# H_#_ H_# H_#_ E H_# H_#_ H_# H_#_ H_# H_#_ J H_# H_#_ H H_#0 H_#_ J H_# H_#_0 E H_# H_#_ E H_# H_#_ H H_# H_#_ J H_# H_#_ H H_# H_#_ J H_# H_#_ E H_# H_#_ J H_# H_#_ J H_#0 H_#_ E H_# H_#_0 J H_# H_#_ H H_# H_#_ H H_#_ H_WIN H_ROMP H_WIN H_ROMP H_OMP W H_OMP# H_OMP W H_OMP# H_PURT# E H_PULP# H_VREF H_VREF H_VREF H_VREF H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_# H_T#_0 H_T#_ H_NR# H_PRI# H_REQ# H_EFER# H_Y# HPLL_LK HPLL_LK# H_PWR# H_RY# H_HIT# H_HITM# H_LOK# H_TRY# H_INV#_0 H_INV#_ H_INV#_ H_INV#_ H_TN#_0 H_TN#_ H_TN#_ H_TN#_ H_TP#_0 H_TP#_ H_TP#_ H_TP#_ H_REQ#_0 H_REQ#_ H_REQ#_ H_REQ#_ H_REQ#_ H_R#_0 H_R#_ H_R#_ J H_# H_# H_# M H_# H_# F H_# L H_# H_#0 H_# K H_# H_# L H_# J H_# H_# K H_# P H_# R H_# H_#0 H0 H_# L H_# H_# M H_# N H_# J H_# H_# E H_# H_# H_#0 E H_# H_# H_# H_# N H_# H 0 E F 0 M M H K E 0 K L E M K H L K J0 M H_REQ#0 E H_REQ# H_REQ# H H_REQ# H_REQ# E H_#[:] H_# H_T#0 H_T# H_NR# H_PRI# H_R0# H_EFER# H_Y# LK_MH_LK LK_MH_LK# H_PWR# H_RY# H_HIT# H_HITM# H_LOK# H_TRY# H_INV#0 H_INV# H_INV# H_INV# H_TN#0 H_TN# H_TN# H_TN# H_TP#0 H_TP# H_TP# H_TP# H_REQ#[:0] H_R#0 H_R# H_R# RETLINE_PM UTeK OMPUTER IN. N Title : N-PM(HOT) Engineer: ajun_ho ustom Fc,, 00 ate: heet of.0

8 N0 F : MI trap 0 = MI x = MI x () R00 MH_F_.0KOHM F : Low Power PI-E 0 = Normal mode = Low Power Mode () R00 MH_F_.0KOHM F : PIE raphic Lane 0 = Reverse Lane = Normal Operation () R00 MH_F_.0KOHM F : F ynamic OT 0 = ynamic OT isable = ynamic OT Enable () R0 MH_F_.0KOHM +.M_X MH trapping F : MI Lane Reversal F[:] : MH Test Mode 0 = Normal Operation () 00= Partial LK ating isable = Lanes Reversed 0 = XOR Mode Enable +V R00 0 = ll Z Mode Enable MH_F_ = Normal Operation ().0KOHM R00 MH_F_ F0 : oncurrent VO / PIe.0KOHM 0 = Only one is operational () R00 = operate simultaneous MH_F_ +V R00.0KOHM MH_F_0.0KOHM VO_TRL_T : VO Present 0 = No VO () = VO Present VO_TRL_T R00 F : V select 0 =.0V() =.V +V R0 MH_F_.0KOHM % 0 PM_EXTT#_0 PM_EXTT#_ +V P RV P RV R RV N RV R RV R RV M RV N RV J RV R RV0 M RV L RV M RV 0 RV 00 0.UF/V ML 0.UF/V (00) XR 0% H0 RV0 RV J0 RV K RV F RV H0 RV K RV J RV F RV RV RV0 M RV 0, M J M M_, M E _M_ H RV W0 RV K0 RV LV_T#_ LV_T_ RV RV0 RV RV RV RV RV LK F EL EL EL0 L H H L H L MH_EL0 P F_0 MH_EL N F_ MH_EL N F_ F_ MH_F_ F_ F F_ N F_ MH_F_ F_ J0 MH_F_ F_ 0 F_ R F_0 L MH_F_ F_ J MH_F_ F_ E F_ E0 F_ K MH_F_ F_ M0 PM_EXTT#_0 F_ M PM_EXTT#_ MH_F_ F_ L MH_F_ F_ N MH_F_0 F_ L F_0 M_K_0 V M_LK_R0 0 M_K_ M_LK_R 0 M_K_ M_LK_R M_K_ V M_LK_R W0 M_K#_0 M_LK_R#0 0 M_K#_ M_LK_R# 0 M_K#_ W M_LK_R# M_K#_ W M_LK_R# E M_KE_0 M_KE0 0, Y M_KE_ M_KE 0, M_KE_ M_KE, M_KE_ M_KE, 0 M_#_0 M_#0 0, M_#_ K M_# 0, M_#_ M_#, E M_#_ M_#, M_OT_0 H M_OT0 0, M_OT_ J M_OT 0, J M_OT_ M_OT, E M_OT_ M_OT, L M_ROMP R00 % M_ROMP K M_ROMP# R00 M_ROMP# % K M_ROMP_VOH M_ROMP_VOH For alero 0 Ohm L M_ROMP_VOL M_ROMP_VOL For restline 0. Ohm R M_VREF_MH M_VREF_0 M_VREF_ W R0 PLL_REF_LK R0 PLL_REF_LK# H R00 PLL_REF_LK H R0 PLL_REF_LK# K PE_LK LK_MH_PLL PE_LK# K LK_MH_PLL# MI_TXN[:0] N MI_TXN0 MI_RXN_0 J MI_TXN MI_RXN_ N MI_TXN MI_RXN_ N MI_TXN MI_RXN_ MI_TXP[0..] M MI_TXP0 MI_RXP_0 J MI_TXP MI_RXP_ N MI_TXP MI_RXP_ N MI_TXP MI_RXP_ MI_RXN[0..] J MI_RXN0 MI_TXN_0 J MI_RXN MI_TXN_ M0 MI_RXN MI_TXN_ M MI_RXN MI_TXN_ MI_RXP[0..] J MI_RXP0 MI_TXP_0 J MI_RXP MI_TXP_ M MI_RXP MI_TXP_ M MI_RXP MI_TXP_ +.V R0 KOhm % MH_LVREF R0 00 Ohm 0.UF/0V % R V R0 KOhm % M_VREF_MH 0,, PM_MUY#,,0 H_PRTP# R0 +V 0KOhm,,0, PM_PWROK LK_MH_OE#,,,,,,,,, UF_PLT_RT#, PM_THRMTRIP#,0 PM_PRLPVR +.V R0 KOhm % M_ROMP_VOH R0 UF/0V 0.0UF/V.0KOhm % M_ROMP_VOL T00 R0 R0 0KOhm PM_EXTT#_0 R0 0KOhm r00 PM_EXTT#_ R0 R0 TPT 0 RT_IN_MH# L L J W V0 N0 J K K0 L0 L L L K J E 0 0 K PM_M_UY# PM_PRTP# PM_EXT_T#_0 PM_EXT_T#_ PWROK RTIN# THERMTRIP# PRLPVR N_ N_ N_ N_ N_ N_ N_ N_ N_ N_0 N_ N_ N_ N_ N_ N_ FX_VI_0 FX_VI_ FX_VI_ FX_VI_ FX_VR_EN L_LK L_T L_PWROK L_RT# L_VREF VO_TRL_LK VO_TRL_T LK_REQ# IH_YN# TET_ TET_ E E M K0 T N M0 H K 0 R R00 MH_LVREF INT P VO_TRL_T LK_MH_OE# R0 R0 L_LK0 PM_PWROK L_T0 INT P kohm L_RT#0 R0 MH_IH_YN# R0 00 KOhm 0.UF/0V % R0 KOhm % UF/0V 0.0UF/V RETLINE_PM UTeK OMPUTER IN. N Title : Engineer: RETLINE(MI & F) ajun_ho ustom Fc,, 00 ate: heet of.0

9 N0 +.V R00 R00 R00 R00 R00 R00 R00 R00 J0 H E E0 K0 L L N N0 E E F 0 E0 F E E K F J L M P H K J F E K F E L_KLT_TRL L_KLT_EN L_TRL_LK L_TRL_T L LK L T L_V_EN LV_I LV_V LV_VREFH LV_VREFL LV_LK# LV_LK LV_LK# LV_LK LV_T#_0 LV_T#_ LV_T#_ LV_T_0 LV_T_ LV_T_ LV_T#_0 LV_T#_ LV_T#_ LV_T_0 LV_T_ LV_T_ TV_ TV_ TV_ TV_RTN TV_RTN TV_RTN TV_ONEL_0 TV_ONEL_ RT_LUE RT_LUE# RT_REEN RT_REEN# RT_RE RT_RE# RT LK RT T RT_HYN RT_TVO_IREF RT_VYN PE_OMP R00.Ohm PE_OMPI N % PE_OMPO M PIEN_RXN[0..] J PIEN_RXN0 PE_RX#_0 PIEN_RXN PE_RX#_ L PIEN_RXN PE_RX#_ N T PIEN_RXN PE_RX#_ T0 PIEN_RXN PE_RX#_ PIEN_RXN PE_RX#_ U0 Y PIEN_RXN PE_RX#_ Y0 PIEN_RXN PE_RX#_ PIEN_RXN PE_RX#_ PIEN_RXN PE_RX#_ W PIEN_RXN0 PE_RX#_0 0 PIEN_RXN PE_RX#_ PIEN_RXN PE_RX#_ PIEN_RXN PE_RX#_ H PIEN_RXN PE_RX#_ PIEN_RXN PE_RX#_ PIEN_RXP[0..] J0 PIEN_RXP0 PE_RX_0 PIEN_RXP PE_RX_ L0 M PIEN_RXP PE_RX_ U PIEN_RXP PE_RX_ PIEN_RXP PE_RX_ T PIEN_RXP PE_RX_ T W PIEN_RXP PE_RX_ W PIEN_RXP PE_RX_ 0 PIEN_RXP PE_RX_ PIEN_RXP PE_RX_ Y PIEN_RXP0 PE_RX_0 PIEN_RXP PE_RX_ H PIEN_RXP PE_RX_ PIEN_RXP PE_RX_ H PIEN_RXP PE_RX_ PIEN_RXP PE_RX_ N PIEN_TXN0 PE_TX#_0 U PIEN_TXN PE_TX#_ U PIEN_TXN PE_TX#_ N PIEN_TXN PE_TX#_ R0 PIEN_TXN PE_TX#_ T PIEN_TXN PE_TX#_ Y PIEN_TXN PE_TX#_ W PIEN_TXN PE_TX#_ W PIEN_TXN PE_TX#_ PIEN_TXN PE_TX#_ PIEN_TXN0 PE_TX#_0 PIEN_TXN PE_TX#_ PIEN_TXN PE_TX#_ H PIEN_TXN PE_TX#_ E PIEN_TXN PE_TX#_ H PIEN_TXN PE_TX#_ M PIEN_TXP0 PE_TX_0 T PIEN_TXP PE_TX_ T PIEN_TXP PE_TX_ N0 PIEN_TXP PE_TX_ R PIEN_TXP PE_TX_ U PIEN_TXP PE_TX_ W PIEN_TXP PE_TX_ Y PIEN_TXP PE_TX_ Y PIEN_TXP PE_TX_ PIEN_TXP PE_TX_ PIEN_TXP0 PE_TX_0 0 PIEN_TXP PE_TX_ PIEN_TXP PE_TX_ PIEN_TXP PE_TX_ E0 PIEN_TXP PE_TX_ H PIEN_TXP PE_TX_ PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP0 PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP0 PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN0 PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP0 PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP0 PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN0 PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN0 PIE_RXN[0..] PIE_RXP[0..] RETLINE_PM UTeK OMPUTER IN. N Title : Engineer: N_PM(RPHI) ajun_ho ustom Fc,, 00 ate: heet of.0

10 ustom 0,, 00 UTeK OMPUTER IN. N N-PM(R).0 Fc ajun_ho ate: heet of Title : Engineer: M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q0 M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q0 M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q# M Q M M M M M M M M M M M M M Q M 0 M M M M M Q M M0 M Q M Q# M M M Q M M M M Q# M M 0 M Q# M M M Q# M M Q M Q# M Q#0 M M Q# M Q0 M Q M M M0 M M Q# M Q# M M M Q# M M M M M M Q M M Q M M Q# M M Q M Q M M M M M M M Q# M M Q M Q0 M Q M M Q M 0 M M M M M M M 0 M Q# M Q#0 M Q# N0E RETLINE_PM P R E0 Y F0 F J0 J J L W0 K K K K J L J J K J0 W L K K E K E N J0 L K L K K0 J J F H N0 K E J R T V0 Y Y U T V 0 0 Y E R0 K L H J F W T0 0 K K J L E V U0 0 L K K K F V E W F E Y V Y _Q_0 _Q Q_0 _Q Q Q Q Q Q Q Q Q Q Q_0 _Q Q Q Q Q Q Q Q Q Q Q_0 _Q Q Q Q Q Q Q Q Q Q Q_0 _Q Q Q Q Q Q Q Q Q Q Q_0 _Q Q Q Q Q Q Q Q Q Q Q_0 _Q Q Q Q Q Q 0 _# _M_0 _M M M M M M M Q_0 _Q Q Q Q Q Q Q Q#_0 _Q# Q# Q# Q# Q# Q# Q# M_0 _M M_0 _M M M M M M M M M M M R# _RVEN# _WE# N0 RETLINE_PM R W J 0 H E W E E0 F H 0 F0 R0 W0 T W W Y Y V T V T W V U T R E0 0 Y 0 W Y R T T Y R R R N M N0 T T N M N W F K F L T W W Y T E H P N T H P J 0 E 0 J K H L K J J L E Y0 _Q_0 _Q Q_0 _Q Q Q Q Q Q Q Q Q Q Q_0 _Q Q Q Q Q Q Q Q Q Q Q_0 _Q Q Q Q Q Q Q Q Q Q Q_0 _Q Q Q Q Q Q Q Q Q Q Q_0 _Q Q Q Q Q Q Q Q Q Q Q_0 _Q Q Q Q Q Q 0 _# _M_0 _M M M M M M Q_0 _Q Q Q Q Q Q Q M Q#_0 _Q# Q# Q# Q# Q# Q# Q# M_0 _M M_0 _M M M M M M M M M M M R# _RVEN# _WE# M Q[:0] 0 M Q[:0] M WE# 0, M R# 0, M [:0] 0, M # 0, M M[:0] 0 M Q[:0] 0 M Q#[:0] 0 M 0, M 0 0, M 0, M WE#, M R#, M #, M M[:0] M [:0], M Q#[:0] M Q[:0] M, M, M 0,

11 t Edge Pin Location Place on the Edge 0 mils from the Edge 00m - R 00m - ore 0m - ontroller Link t Package Edge In avity ore 00m ontroller Link t Package Edge ustom,, 00 UTeK OMPUTER IN. N RETLINE(PWR).0 Fc ajun_ho ate: heet of Title : Engineer: +.V +VP +VP +VP +VP 0.UF/V UF/.V 0 0.UF/0V R0 + E0 00UF/.V 0UF/0V POWER N0 RETLINE_PM K J J H H H F T F J W Y E E E U F H H H J J U K K K K U U U0 U U U V V V V0 T V V V Y Y Y Y Y0 Y Y T Y Y Y Y T F F H H H H T J J J K K L L L L0 L T L M M M M M P P P T P P0 P U U L V W T T U R0 T W W Y F F H0 H H H P P R0 R R R R R0 H J0 N W E W T H M0 U0 V V V Y V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_M_0 V_M_0 V_M_0 V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_X_NTF_0 V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_0 V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_0 V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_0 V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_0 V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_0 V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_0 V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_M_ V_M_ V_M_ V_X_NTF_ V_ V_M_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_0 V_X_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_0 V_X_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_0 V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_X_NTF_ V_ V_X_ V_X_ V_X_ V_M_LF V_M_LF V_M_LF V_M_LF V_M_LF V_M_LF V_M_LF V_X_ V_X_ V_ V_X_NTF_ V_M_ V_X_NTF_0 V_X_NTF_ V_X_NTF_ V_X_NTF_ + 00UF/.V 0 0.UF/0V 0UF/0V 0.UF/0V 0 0UF/0V 0 UF/0V 0.UF/0V 0.UF/0V + E0 00UF/.V 0UF/0V UF/.V 0 0UF/0V 0 UF/.V UF/0V 0 UF/0V 0.UF/0V POWER N0F RETLINE_PM K P U F F H H H H J K K K L L P R R T0 T T U U U U U V V V T T U U V V F K M P R R R Y K K J J L L L M M M M P P R Y Y Y Y L L J F J K L L L M M M M P P P R R T T V V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_XM_ V_XM_ V_XM_ V_XM_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_0 V_XM_NTF_ V_XM_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_ V_ V_ V_ V_ V_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_XM_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_NTF_ V_XM_NTF_ V_XM_NTF_ V_NTF_ V_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_ V_XM_ V_NTF_ 0.UF/0V 0 0UF/0V 0.UF/0V UF/.V 0 UF/.V 0 0.UF/0V

12 On the Edge In avity Max: m Max:?m Max: 0m Max: 00m Max: 0m Max: 00m Max: 00m Max: 00m Max: 00m Max: 0m Max: 0m Top Layer Max: m Max: 0m Max: 0m Max: 0m Max: 00m Top Layer Max:?m PLL V ustom,, 00 UTeK OMPUTER IN. N N-PM(PWR).0 Fc ajun_ho ate: heet of Title : Engineer: +.V_PLL +.V_PLL +.V_HPLL +.V_MPLL +V +.V_PE_PLL +.V_PE_PLL +.V +.V_TV +.V_QTV +.V +.V +.V +V_MI +.V_MPLL +.V +.V_QTV +.V_PE_PLL +.V_PLL +V_HV +V +.V_TV +.V +.V_PLL +.V_HPLL +.V +VP +.V +.V +.V +VP +.V +V_HV +.M_X +V_PIE +V_MI +VP +.V +V_PIE 0.UF/V 0 0UF/0V 0 0.UF/0V UF/.V 0UF/0V 0.UF/0V 0UF/0V 0UF/0V 0 0.UF/0V L0 /00Mhz 0 0UF/0V 0UF/0V 0 0.UF/0V 0UF/0V ML/+/-0% L0 /00Mhz L0 /00Mhz 0.UF/0V 0 UF/.V R0 L0 /00Mhz UF/.V 0UF/0V ML/+/-0% R0 Ohm % + E0 00UF/.V 0 0UF/0V UF/.V 0.UF/V 0.UF/V 0.UF/0V 0 0UF/0V 0UF/0V R L0 /00Mhz + E0 00UF/.V 0.UF/0V 0.UF/0V R0 R0 Ohm % R0 0.UF/0V R 0.UF/0V 0.UF/0V R0 0UF/0V 0 0UF/0V L0 0NH + E0 00UF/.V 0 UF/.V 0 0.UF/0V L0 /00Mhz 0.UF/0V 0 T 0 0UF/0V R0 0UF/0V ML/+/-0% R 0UF/0V R0 0.UF/0V L0 /00Mhz 0.0UF/V R0 Ohm % POWER N0H RETLINE_PM T R R R M K0 U H L M U T T T T T T0 T J N U U U U U U U U U T U 0 L F H H0 H K K J J J N U U T W V U U U T T T J0 K 0 0 T T R R H W0 W V V0 R T T0 T VTT_ VTT_0 VTT_ VTT_ V_RT V_PE_ V_PE_PLL V_RT V_RT V_PLL V_PLL V_HPLL V_LV V_MPLL V_TV V_TV V_TV V_TV V_TV V_TV V_PE_PLL VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VYN V_HPLL VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ V_M_K_ V_M_K_ V V_TV VTTLF VTTLF VTTLF V_RXR_MI_ V_RXR_MI_ V_M_K_ V_M_K_ V_M_K_ V_M_K_ V_LV_ V_Q V_X_ V_X_ V_X_ V_XF_ V_XF_ V_XF_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_MI V_TX_LV V V_LV V_PE_ V_HV_ V_HV_ V_PE_ V_M_0 V_M_ V_M_NTF_ V_M_NTF_ V_LV_ V_PE_ V_PE_ V_PE_ V_PE_ V_X_NTF V_X_ V_X_ V_X_ + E0 00UF/.V 0.UF/0V 0 0UF/0V 0UF/0V L0 /00Mhz 0UF/0V 0.UF/0V

13 ustom,, 00 UTeK OMPUTER IN. N RETLINE().0 Fc ajun_ho ate: heet of Title : Engineer: V N0J RETLINE_PM 0 E0 E E E E E F F F F0 F0 H H H H J J J J J J J J K K K L L L0 L L L L L M M M M M M0 M N N N N N N N N N N P P P P P0 R T T T U U U0 W W W W W W Y Y Y V V Y Y Y Y0 Y P T T T R F F T V H0 V_ V_00 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_00 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_ V_ V_ R0 R0 V N0I RETLINE_PM E0 E E F0 F F F 0 H H0 H H H J J J J J J J J J K0 K K K K K L M M M M M M N N N N N N P P P0 R R R R R R T0 T T T W W W W W W Y0 Y Y Y Y Y Y Y E E E E0 E E E F F F H H0 H H H J J J J J J K K K K U U U U U U U V V W W K K K L L K0 K L L L L V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_00 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ R0 R0

14 UTeK OMPUTER IN Title : chematic page name Engineer: ajun_ho Fc,, 00 ate: heet of.0

15 JK detect R VU R 0KOhm PIO T0 +V +RTT 0 +V_RT JK_W# R 00KOhm Q0 PM0 E TPT R0 T KOhm ON0 TT_HOLER_P T0 TPT 0 UF/0V 0 PF/0V X0.Khz _X_RT R0 0MOhm RTRT# R delay should be ms~ms IH_INTVRMEN(VU_0,VU_,VL_) Low - isabled Internal VR High - Enable Internal VR() IH_LN00 (VLN_0,VL_0) Low - isabled Internal VR High - Enable Internal VR() Z_IN0 Z_IN OE MOEM IH_TP XOR hain Entrance trap IH_TP +V_RT Z_OUT R0 kohm +V R KOhm R KOhm Z_OUT escription 0 UF/0V Request of for MO clear function Place Near the Open oor JRT0 L_JUMP 0PF/0V 0PF/0V Z_LK_M Z_LK_OE Z_YN_OE Z_YN_M, Z_RT#_OE Z_RT#_M Z_IN0 Z_IN RV Enter XOR hain Normal Operation () et PIe port config bit +V_RT +V_RT 0 0 Z_OUT_OE Z_OUT_M T_RXN0 T_RXP0 T_TXN0 T_TXP0 T_LE# T0 0 R0 R0 R0 Z_IN0 Z_IN R R R R R R R0 R PF/0V PIO 0KOhm 0KOhm OE MOEM 0 000PF/0V 000PF/0V 0 TPT LK_T_IH# LK_T_IH MOhm Ohm Ohm Ohm Ohm Ohm Ohm Ohm Ohm T0 T0 _X_RT IH_INTVRMEN IH_LN00 Z_LK Z_YN Z_RT# Z_OUT TPT TPT T_TXN0_ T_TXP0_ TRI/# R.Ohm % F F F E0 0 H J J E J H H E E0 F0 F F H H J J F F E E 0 RTX RTX RTRT# INTRUER# INTVRMEN LN00_LP LN_LK LN_RTYN LN_RX0 LN_RX LN_RX LN_TX0 LN_TX LN_TX LN_OK#/PIO LN_OMPI LN_OMPO H_IT_LK H_YN H_RT# H_IN0 H_IN H_IN H_IN H_OUT H_OK_EN#/PIO H_OK_RT#/PIO TLE# T0RXN T0RXP T0TXN T0TXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP T_LKN T_LKP TRI# TRI IH-M FWH0/L0 FWH/L FWH/L FWH/L FWH/LFRME# LRQ0# LRQ#/PIO 0TE 0M# PRTP# PLP# FERR# PUPWR/PIO INNE# INIT# INTR RIN# NMI MI# TPLK# THRMTRIP# TP # # IOR# IOW# K# IEIRQ IORY REQ E F F E F F E F E 0 H E V U V T V T T T R T V V U V U Y Y W W Y Y Y W LP_RQ#0 LP_RQ# R.Ohm % TPT IE_P0 IE_P IE_P IE_P IE_P IE_P IE_P IE_P IE_P IE_P IE_P0 IE_P IE_P IE_P IE_P IE_P T0 IE_P0 IE_P IE_P IE_P# IE_P# IE_PIOR# IE_PIOW# IE_PK# IE_PREQ LP_0,,0, LP_,,0, LP_,,0, LP_,,0, LP_FRME#,,0, TPT TPT +V T0 T0 0TE H_0M# H_PWR H_INNE# H_INIT# H_INTR RIN# H_NMI H_MI# H_TPLK# IE_P[:0] R.KOhm R.KOhm R0 Ohm +VP R Ohm R0 Ohm +VP INT_IRQ IE_PIORY R0 Ohm PM_THRMTRIP#, H_PRTP#,,0 H_PLP# H_FERR# UTeK OMPUTER IN. N Title : -IHM() Engineer: ajun_ho ustom Fc,, 00 ate: heet of.0

16 PI_[:0] PI_INT# PI_INT# PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_INT# PI_INT# E 0 0 E 0 0 F E E E E 0 F 0 PI REQ0# NT0# REQ#/PIO0 NT#/PIO REQ#/PIO NT#/PIO REQ#/PIO NT#/PIO /E0# /E# /E# /E# IRY# PR PIRT# EVEL# PERR# PLOK# ERR# TOP# TRY# FRME# PLTRT# PILK PME# Interrupt I/F PIRQ# PIRQE#/PIO PIRQ# PIRQF#/PIO PIRQ# PIRQ#/PIO PIRQ# PIRQH#/PIO IH-M E F 0 E F E F0 0 F F PI_REQ# PI_NT# PI_REQ# PI_NT# PI_REQ# PI_NT# PI_LOK# PLT_RT# TPT T0 PI_INTE# PI_INTF# PI_INT# PI_INTH# T0 TPT T0 TPT T0 TPT PI_/E#0 PI_/E# PI_/E# PI_/E# PI_IRY# PI_PR PI_RT#, PI_EVEL# PI_PERR# PI_ERR# PI_TOP# PI_TRY# PI_FRME# LK_IHPI PI_REQ0# PI_NT#0 LK_IHPI 0 0PF/0V U0 V Y NZ0PX PI_NT# PI_NT#0 PI_# +V R0 KOhm R0 0KOhm R0 KOhm wap override strip R0 KOhm Low : Enable High: efault IH oot IO elect LP PI PI H H uffer to Reduce Loading on PLT_RT# PI_INTH# PI_INT# PI_REQ0# PI_INT# PI_INTE# PI_IRY# PI_LOK# PI_PERR# NT#0 # UF_PLT_RT#,,,,,,,,, L RP0 RP0 RP0 RP0 RP0E RP0F RP0 RP0H H L H.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0 +V PIE_RXN_LN PIE_RXP_LN PIE_TXN_LN PIE_TXP_LN PIE_RXN_WLN PIE_RXP_WLN PIE_TXN_WLN PIE_TXP_WLN PIE_RXN_eT PIE_RXP_eT PIE_TXN_eT PIE_TXP_eT PIE_RXN_Robson PIE_RXP_Robson PIE_TXN_Robson PIE_TXP_Robson PIE_RXN_NEWR PIE_RXP_NEWR PIE_TXN_NEWR PIE_TXP_NEWR PIE_RXN_WWN PIE_RXP_WWN PIE_TXN_WWN PIE_TXP_WWN +VU RN0 U_ON_O0# 0KOhm RN0 U_O# 0KOhm RN0 0KOhm RN0 0KOhm RN0 0KOhm RN0 0KOhm RN0 U_O# 0KOhm RN0 NEWR_O# 0KOhm R0 0KOhm U_O# R 0KOhm U_O# R0 0KOhm U_ON_O# UF/0V 0 0.UF/0V 0 0.UF/0V 0.UF/0V PIE_TXN_LN_ PIE_TXP_LN_ PIE_TXN_WLN_ PIE_TXP_WLN_ P P N N M M L L 0 PERN PERP PETN PETP PERN PERP PETN PETP K PI_TRY# RP0F PERN MIRXN MI_RXN K 0 PIE_TXN_eT_ PERP MIRXP MI_RXP 0.UF/0V J PI_REQ# 0 0.UF/0V PIE_TXP_eT_ PETN MITXN MI_TXN RP0 J PETP MITXP MI_TXP PI_TOP# RP0H H PERN MIRXN MI_RXN H 0 0.UF/0V PIE_TXN_Robson_ PERP MIRXP MI_RXP PI_EVEL# PIE_TXP_Robson_ PETN MITXN MI_TXN.KOhm 0 0.UF/0V PI_REQ# PETP MITXP MI_TXP.KOhm PI_FRME#.KOhm F PI_REQ# PERN MI_LKN T LK_PIE_IH#.KOhm F T PIE_TXN_NEWR_ PERP MI_LKP LK_PIE_IH 0.UF/0V E PIE_TXP_NEWR_ PETN 0.UF/0V E Y MI_OMP R0.Ohm % PETP MI_ZOMP +.V_PIE_IH Y R0 MI_IROMP L<00mils R0 PERN/LN_RXN PERP/LN_RXP UP0N U_PN0 0 0.UF/0V PETN/LN_TXN UP0P U_PP0 U 0 U onn.(m/) 0.UF/0V H +V PETP/LN_TXP UPN U_PN H UPP U_PP U U onn.(m/) RN0 0KOhm H RN0 PI_LK UPN U_PN 0KOhm H U U onn.(/) PI_# PI_0# UPP U_PP E PI_# UPN J U_PN J U U onn.(m/) RN0 UPP U_PP 0KOhm K RN0 PI_MOI UPN U_PN 0KOhm F K PI_MIO UPP U_PP U luetooth(m/) UPN K U_PN U_ON_O0# J K O0# UPP U_PP U FINER PRINT(/) O#/PIO0 UPN L U_PN, U_ON_O# O#/PIO U UPP L U_PP U Newcard(M/) U_ON_O# E M U_O# O#/PIO UPN U_PN F M O#/PIO UPP U_PP U MO amera(/) RIN# U_O# M O#/PIO UPN U_PN Y_RT# NEWR_O# M U Windigo(M/) U_O# O#/PIO0 UPP U_PP J N U_O# O#/PIO UPN U_PN N EXT_MI#, U TV(M/) U_O# O# UPP U_PP _#, H O# F URI# URI# URI F R0.Ohm % IH-M MI0RXN MI0RXP MI0TXN MI0TXP MIRXN MIRXP MITXN MITXP V V U U Y Y W W L<00mils MI_RXN0 MI_RXP0 MI_TXN0 MI_TXP0 MI_RXN MI_RXP MI_TXN MI_TXP UTeK OMPUTER IN. N ustom PI_INTF# PI_INT# PI_ERR# PI_INT# PI_INT# Fc RP0 RP0 RP0 RP0 RP0E.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0 RN0 RN0 RN0 RN0 Title : -IHM() Engineer: ajun_ho,, 00 ate: heet of.0

17 0 E_LK_EN RIN# M_LK M_T LINKLERT# M_LINK0 M_LINK J E F MLK MT LINKLERT# MLINK0 MLINK RI# T0P/PIO TP/PIO TP/PIO TP/PIO LK LK J J0 F R0 PO PO P_I0 PU_elect LK_IH LK_U 0 LK_EN# Q0 R N00K_T_E VRMPWR,, PM_U_TT# Y_RT#,,,, PM_MUY# TP_PI# TP_PU# PM_LKRUN# PIE_WKE# INT_ERIRQ PMTHERM# R0 R0 M_LERT# VRMPWR F E0 H E F J0 U_TT#/LPP# Y_REET# MUY#/PIO0 MLERT#/PIO TP_PI#/PIO TP_PU#/PIO LKRUN#/PIO WKE# ERIRQ THRM# VRMPWR ULK LP_# LP_# LP_# _TTE#/PIO PWROK PRLPVR/PIO TLOW# PWRTN# LN_RT# R0 F R0 H E J E H0 TTE# R0 T_LL# R0 R ULK U#, U# TPT PM_PWROK,,0, PM_PWRTN# 0KOhm ll PWR PM_PRLPVR,0 00/0/ Int P.U T0 PM TTE# 0 0PF/0V R PF/0V R J TP RMRT# PM_RMRT# No Reboot trap Low = efault High = No Reboot, EXT_MI# WLN_ON# +V T0 R TPT T_ON#, _# T_LKREQ# R R 0KOhm T0 TPT R +V _PKR MH_IH_YN# TLE_ON T_ET# WLN_LE_ON EXT_I# IO_RE PO P_I P_I IH_TP T0 MH_YN# TPT KOhm J J H E H E 0 H F J 0 J J TH/PIO TH/PIO TH/PIO PIO PIO TH0/PIO PIO PIO0 LOK/PIO QRT_TTE0/PIO QRT_TTE/PIO TLKREQ#/PIO LO/PIO TOUT0/PIO TOUT/PIO PKR MH_YN# TP K_PWR LPWROK LP_M# L_LK0 L_LK L_T0 L_T L_VREF0 L_VREF L_RT# LPIO0/PIO LPIO/PIO0 LPIO/PIO WOL_EN/PIO E E J F E F F H J J J F LPM# L_VREF0 L_VREF R R IH_LKEN L_LK0 L_T0 L_RT#0 PM_PWROK +V PM_LP_M# R,MH PWR R.KOhm % R Ohm % 0 0.UF/0V +VU R.KOhm % R0 Ohm % 0 0.UF/0V IH-M R 00KOhm Mount for IO Recovery Place Near the Open oor +VU M_LK_ M_T_ RN0 M_LK 0KOhm RN0 M_T 0KOhm RN0 0KOhm RN0 0KOhm +V MH_IH_YN# R 0KOhm +V IO_RE R P_I[:0] 000: R.0 00: R. 00: R.0 R0 R R 0KOhm +V R 0KOhm 0KOhm IO_RE R 0KOhm +V Q0 M_LK N00K_T_E +V Q0 M_T N00K_T_E M_LK_ 0,,,,,, M_T_ 0,,,,,, +VU PIE_WKE# R KOhm M_LINK0 RN0 0KOhm M_LINK RN0 0KOhm RN0 0KOhm T_LL# RN0 0KOhm +VU T_ON# RN0 0KOhm RN0 U_O# 0KOhm RN0, U_ON_O# 0KOhm TP_PI# TP_PU# PO INT_ERIRQ PM_LKRUN# PMTHERM# T_ET# VRMPWR R R R R 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm RN0 RN0 RN0 RN0 +V +V 00KOhm P_I P_I P_I0 R 0KOhm R 0KOhm R0 0KOhm M_LERT# R LINKLERT# R WLN_ON# R VRMPWR R 0KOhm 0KOhm 0KOhm 0KOhm +VU PM_PWROK PM_RMRT# R R 0KOhm 00KOhm +V,, M_LK,, M_T R R M_LINK0 M_LINK PO PO R 0KOhm 0KOhm RN0 UTeK OMPUTER IN. N Title : -IHM() Engineer: ajun_ho ustom Fc,, 00 ate: heet of.0

18 istribute in PI ection On Edge IH_INTVRMEN(VU_0,VU_,VL_) Low - isabled Internal VR High - Enable Internal VR() IH_LN00 (VLN_0,VL_0) Low - isabled Internal VR High - Enable Internal VR() ustom,, 00 UTeK OMPUTER IN. N -IHM(PWR).0 Fc ajun_ho ate: heet of Title : Engineer: +VU_V_ VL INT +.V_TPLL +.V_IH_ +.V_IH_ TP_VL_0 TP_VU_0_ +.V_IH_ +.V_UPLL +.V_IH_ TP_VLan_0_ +V_V 0 +.V_MIPLL TP_VU +V_V 0 TP_VU TP_VU_0_ +VP_PU_IO TP_VLan_0_ +.V +.V +V +.V +V_._H_IO +.VU +VU +VU_.VU_H_IO +VU +VREF_U +V_RT +.V_PIE_IH +.V +VREF +VU +V +V +VU +.V +.V_PIE_IH +V +VP +V +V_PI +V_VPORE +V_IE +V_VPORE +V_IE +V_PI +V_PI +V +V +V +VU +VP R 0.UF/0V 0 UF/.V 0 0UF/0V R0 0.UF/0V T0 TPT 0 0.UF/0V R 0 0.0UF/V R0 + E0 00UF/.V R0 0.UF/0V 0.UF/0V 0.UF/0V 0 T R0 T0 TPT 0UF/0V L0 /00Mhz 0 0UF/0V UF/.V UF/.V L0 uh 0.UF/0V 0.UF/0V R0 0UF/0V R R R0 0E IH-M 0 E E E E E E E E F F F F F H0 H H H H F H H H H H H J 0 E E E E F E F F F E 0 H H H H H J J J J J J K K K K K L L L L L L L M M M M M M M M M M N N N N N N N N N N N N N N P P P P P P P P P R R R R R R R R R R T T T T T T T U U U U U U U U U U U V V V V W W W Y Y Y H H J J J J U K W V[00] V[00] V[00] V[00] V[00] V[00] V[00] V[00] V[00] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V_NTF[0] V_NTF[0] V_NTF[0] V_NTF[0] V_NTF[0] V_NTF[0] V_NTF[0] V_NTF[0] V_NTF[0] V_NTF[0] V_NTF[] V_NTF[] V[] V[0] V[] V[] V[] V[0] V[] T0 TPT 0 0.UF/0V T0 TPT UF/.V 0.UF/0V 0 0.UF/0V UF/.V 0 0UF/0V T0 TPT UF/.V R0 0.UF/0V 0.UF/0V R0 Ohm 0UF/0V T0 TPT 0UF/0V 0 0UF/0V 0 T L0 /00Mhz + E0 00UF/.V 0.UF/0V R 0UF/0V L0 0UH 0F IH-M T E E E F F H H J J K K L L L M M N N N P P R R R R T T T T T U F R E F H J J F E F L L L L L L M M P P T T F 0 U V W W W Y E0 E F 0 H P P N P P P P P R R R 0 J F0 F L L M M W U V V V U V V V F E R H J E E F0 W V U Y V V VREF[] VREF[] VREF_U V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [0] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [0] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [0] V_[0] VMIPLL V [0] V [0] V [0] V [0] V [0] VTPLL V_[0] V [0] V [0] V [0] V [0] V [0] VUPLL VLN_0[] VLN_0[] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[0] VLN_[] VLN_[] VH VUH V_PU_IO[] V_PU_IO[] V_[0] V_[0] V_[0] V_[0] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[0] V_[] V_[] V_[] V_[] VRT VU_[0] VU_[0] VU_[0] VU_[0] VU_[0] VU_[0] VU_[0] VU_[0] VU_[0] VU_[] VU_[] VU_[] VU_[] VU_[] VU_[] VU_[] VU_[] V [] V [] V [] V [] V [] V [] VU_0[] VU_0[] V [0] V [] V [] V [] V [] VU_[0] V_[] V [] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] VLN_[] VLN_[] VLN_[] VLN_[] VLN_[] VLN_ VLNPLL V_[0] V_[0] V_[0] V_[0] VU_[] V [] VU_[] V [] V [] VU_[] V_MI[] V_MI[] VL_0 VL_[] VL_[] VL_ V [] V [] V [] V [] V [] V [] 0.UF/0V T0 TPT R0 R R0 0 R 0 0.UF/0V 0.UF/0V 0UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0 0.UF/0V 0 0.UF/0V

19 UTeK OMPUTER IN Title : chematic page name Engineer: ajun_ho ustom Fc,, 00 ate: heet of.0

20 REV Type ustom 0,, 00 UTeK OMPUTER IN. N R O-IMM0.0 Fc ajun_ho ate: heet of Title : Engineer: M_LK_R M_LK_R0 M Q M Q M Q M Q M Q M Q# M M M M M Q M Q M Q# M M M M M M Q M Q M Q M Q0 M 0 M Q M Q M Q# M_LK_R#0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q# M M M Q0 M Q M Q M Q0 M Q# M Q M Q M Q M Q M Q M Q0 M Q M M M Q M Q M Q M Q0 M Q M Q M Q M Q# M M 0 M Q0 M Q M Q M M Q M Q M Q M Q M Q M Q M Q M Q M_LK_R# M Q M Q M Q M Q M Q M M M Q M Q M Q M Q M Q M M Q M Q M Q# M Q#0 M M M M Q M Q M Q M Q0 M M M M0 M Q M Q M Q0 M Q M Q M M M +.V +V IMM0 R_IMM_00P V V V V V V V V V V0 V V VP N N N N NTET VREF 0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V NP_N NP_N 00 0PF/0V N00 0.UF/V N00 0.UF/V 00 0PF/0V N00 0.UF/V N00 0.UF/V R00 00 UF/0V R00 IMM0 R_IMM_00P /P 0 0# # K0 K0# K K# KE0 KE # R# WE# 0 L OT0 OT M0 M M M M M M M Q0 Q Q Q Q Q Q Q Q#0 Q# Q# Q# Q# Q# Q# Q# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q _ Q 00 UF/0V 00 0UF/0V 00 0.UF/0V 00 0.UF/0V M [:0] 0, M M[:0] 0 M Q[:0] 0 M Q#[:0] 0 M 0, M 0 0, M 0, M_#, M_#0, M_LK_R#0 M_LK_R0 M_KE, M_KE0, M R# 0, M # 0, M_OT, M_OT0, M_LK_R# M_LK_R M_VREF_MH,, M Q[:0] 0 M WE# 0, PM_EXTT#_0 M_LK_,,,,,, M_T_,,,,,, M,

21 T Type ustom,, 00 UTeK OMPUTER IN. N R O-IMM.0 Fc ajun_ho ate: heet of Title : Engineer: M_LK_R M Q M Q M Q M Q M M Q M Q M Q M Q M M Q M Q M Q M Q M Q M Q0 M Q# M M M Q M Q M Q M Q M M M Q M Q0 M M 0 M Q0 M Q M Q M Q M Q M M M_LK_R M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M M M M Q M Q M Q M M0 M M M Q M Q M Q M Q# M M M Q M Q M Q0 M Q M Q M Q M_LK_R# M Q M Q#0 M Q M M M M_LK_R# M Q M Q M Q# M M M M M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q# M Q M Q M M M Q M Q M Q M Q0 M Q M Q# M Q# M Q# M Q M M 0 +V +.V +V IMM R V V V V V V V V V V0 V V VP N N N N NTET VREF 0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V NP_N NP_N N0 0.UF/V IMM R /P 0 0# # K0 K0# K K# KE0 KE # R# WE# 0 L OT0 OT M0 M M M M M M M Q0 Q Q Q Q Q Q Q Q#0 Q# Q# Q# Q# Q# Q# Q# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q _ Q N0 0.UF/V 0 0UF/0V 0 0PF/0V 0 0.UF/0V R0 0 0PF/0V 0 0.UF/0V N0 0.UF/V 0 UF/0V R0 R0 0KOhm 0 UF/0V N0 0.UF/V M Q[:0] 0 M M[:0] 0 M Q#[:0] 0 M Q[:0] 0 M [:0] 0, M_OT, M_#, M_KE, M_#, M R# 0, M WE# 0, M 0, M 0, M # 0, M 0 0, M_KE, M_OT, M_VREF_MH,0, M_LK_R M_LK_R# M_LK_R# M_LK_R PM_EXTT#_ M_T_,0,,,,, M_LK_,0,,,,, M,

22 0,0 M [:0] 0, M [:0] +0.V 0.V_VTT_REF,0 M_OT,0 M_#0,0 M_OT0 0,0 M R# 0,0 M,0 M_# 0,0 M 0 M_OT M_#0 M_OT0 M R# M M 0 M_# M 0 Ohm Ohm Ohm Ohm Ohm Ohm Ohm 0 Ohm RN0 RN0 RN0 RN0 RN0E RN0F RN0 RN0H N0 0.UF/V N0 0.UF/V N0 0.UF/V N0 0.UF/V L0 /00Mhz M_VREF_MH,0,,0 M 0,0 M WE#,0 M_KE Ohm M WE# Ohm M Ohm M Ohm M Ohm M 0 Ohm M Ohm M Ohm 0 M_KE Ohm R0 RN0 RN0 RN0 RN0 RN0E RN0F RN0 RN0H N0 0.UF/V N0 0.UF/V N0 0.UF/V N0 0.UF/V 0,0 M,0 M_KE0 M M M M M M M M_KE0 Ohm Ohm Ohm Ohm Ohm Ohm Ohm 0 Ohm RN0 RN0 RN0 RN0 RN0E RN0F RN0 RN0H N0 0.UF/V N0 0.UF/V N0 0.UF/V N0 0.UF/V 0,0 M # M # Ohm M Ohm R0 R0 0.UF/0V 0, M 0, M R# Ohm M Ohm M Ohm M 0 Ohm M Ohm M Ohm M R# Ohm M Ohm 0 M Ohm R0 RN0 RN0 RN0 RN0 RN0E RN0F RN0 RN0H N0 0.UF/V N0 0.UF/V N0 0.UF/V N0 0.UF/V, M_KE 0, M, M_KE M_KE M M M M M_KE M M Ohm Ohm Ohm Ohm Ohm Ohm Ohm 0 Ohm RN0 RN0 RN0 RN0 RN0E RN0F RN0 RN0H N0 0.UF/V N0 0.UF/V N0 0.UF/V N0 0.UF/V 0, M 0 0, M, M_# 0, M WE# 0, M #, M_OT M 0 M 0 M M M_# M WE# M # M_OT Ohm RN0 Ohm RN0 Ohm RN0 N0 0.UF/V Ohm RN0 N0 0.UF/V Ohm RN0E N0 0.UF/V Ohm RN0F N0 0.UF/V Ohm 0 RN0 Ohm RN0H, M_OT, M_# M_OT M_# Ohm Ohm R0 R0 0.UF/0V 0 UTeK OMPUTER IN. N ustom Fc Title : Engineer: R TERMINTION ajun_ho,, 00 ate: heet of.0

23 UTeK OMPUTER IN Title : chematic page name Engineer: ajun_ho ustom Fc,, 00 ate: heet of.0

24 E E Place near L0 0 m at least 0 mils 0 m Place near L0 place west of PU bottom side. place north of PU bottom side place near 00 m NP. place near alls place sourth of PU bottom side at least mils place near place near alls m at least mils 0/0 /PIF papter in : +V_PIF : HIH /PIF No papter in : +V_PIF : LOW,, 00 UTek OMPUTER IN M()_PI-E.0 Fc ajun_ho ate: heet of Title : Engineer: PIE_TXN PIE_TXP PIE_RXN PIEN_RXP PIE_RXP PIEN_RXN PIE_TXP PIEN_RXP PIEN_RXN PIE_TXN PIE_RXP PIE_RXN PIEN_RXP PIE_TXP PIEN_RXN PIE_TXN PIE_RXP PIE_RXN PIEN_RXP PIEN_RXN PIE_TXP PIE_TXN PIE_RXP PIE_RXN PIEN_RXN PIE_TXP PIEN_RXP PIE_TXN PIE_RXN PIE_RXP PIEN_RXN PIE_TXP PIEN_RXP PIE_RXP PIE_TXN PIEN_RXP PIEN_RXN PIE_TXP PIEN_RXP0 PIE_TXN0 PIE_RXP0 PIE_RXN0 PIE_TXN PIEN_RXP PIEN_RXN0 PIE_TXP0 PIE_TXP PIEN_RXN PIEN_RXP0 PIE_RXN PIEN_RXP PIEN_RXN PIEN_RXN0 PIEN_RXN PIEN_RXP +.VP_PEX_PLLV PIE_TXN PIEN_RXN PIEN_RXP PIEN_RXP PIEN_RXN PIEN_RXP PIEN_RXN PIE_RXP PIE_RXP PIE_RXN PIE_RXN PIE_RXN0 PIE_RXP0 PIE_RXP PIE_TXN PIE_RXP PIE_RXN PIE_TXP PIE_TXP PIE_TXP PIE_TXN PIE_RXP PIE_RXN PIE_RXN PIE_RXN PIE_TXN PIEN_RXP PIEN_RXN PIE_TXP PIE_TXN +.VP_PEXIOVQ PIE_TXN0 PIE_TXP0 PIE_RXN PIE_TXN PIE_TXP PIE_TXP PIE_TXN PIE_RXP PIE_RXP PIE_RXP PIE_RXN +.VP_PEX_PLLV +.VP_NV_PLLV +.VP_PEXIOV PIF_VIN_NV PIF_VIN_NV +.VP +V +V_VORE +.VP +.VP +V_VORE +.VP +V_VORE +V +V_PIF +V 0.UF/0V 0 0.UF/.V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V E Q0 PM0 0.UF/0V 0.UF/0V T0 TPT 0.UF/0V 0UF/.V.UF/.V 0UF/.V 0.UF/0V 0.UF/0V 0 0.UF/0V 0.UF/0V 0.UF/0V R0 0KOhm r00 0.UF/.V 0.UF/0V E Q0 PM0 0.UF/0V 0.UF/0V L0 0NH 0.0UF/V 0 0.UF/0V 0 0.UF/0V 0.UF/0V UF/.V.UF/.V 0.UF/0V 0 0.UF/0V 0.UF/0V T0 TPT R0 0.UF/0V 0 0.UF/0V 0.UF/0V 0 0.UF/.V 0.UF/V 0.UF/.V 0.UF/0V 0.UF/.V L0 /00Mhz 0.UF/0V UF/.V.UF/.V 0.UF/0V UF/.V UF/.V 0.UF/0V 0.UF/0V 0 0.UF/.V 0.UF/0V.UF/.V R0 00KOhm r UF/0V 0 0.UF/.V R0 0.UF/0V 0.UF/0V UF/.V 0.UF/0V U0 NP- L L H J M M J K L L H K K H J M M J K L L H K K H J M M J K L L0 H K0 K H0 0 M M H J L L J K K K H L L H M M H K K K J J H M M H H J M M M0 E E F M0 L L L0 K J H E E W0 U U0 T T0 P0 Y0 Y Y Y Y Y W W W W W V V U U U U U T T T T T R R P P P P P N0 N N N N N K K F F F F E E E F F F PEX_RX_N PEX_RX PEX_TX_N PEX_TX PEX_RX_N PEX_RX PEX_TX_N PEX_TX PEX_RX_N PEX_RX PEX_TX_N PEX_TX PEX_RX_N PEX_RX PEX_TX_N PEX_TX PEX_RX_N PEX_RX PEX_TX_N PEX_TX PEX_RX0_N PEX_RX0 PEX_TX0_N PEX_TX0 PEX_RX_N PEX_RX PEX_TX_N PEX_TX PEX_RX_N PEX_RX PEX_TX_N PEX_TX PEX_RX_N PEX_RX PEX_TX_N PEX_TX PEX_RX_N PEX_RX PEX_TX_N PEX_TX PEX_RX_N PEX_RX PEX_TX_N PEX_TX PEX_RX_N PEX_RX PEX_TX_N PEX_TX PEX_RX_N PEX_RX PEX_TX_N PEX_TX PEX_RX_N PEX_RX PEX_TX_N PEX_TX PEX_RX_N PEX_RX PEX_TX_N PEX_TX PEX_RX0_N PEX_RX0 PEX_TX0_N PEX_TX0 PEX_REFLK_N PEX_REFLK PEX_TTLK_OUT_N PEX_TTLK_OUT N N PEX_RT_N PIF N N N PEX_PLL PEX_PLLV PEX_PLLV V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_LP V_LP V_LP V_LP V_LP V_LP V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V_ENE V V V V V V V PEX_IOVQ PEX_IOVQ0 PEX_IOVQ PEX_IOVQ PEX_IOVQ PEX_IOVQ PEX_IOVQ PEX_IOVQ PEX_IOVQ PEX_IOVQ PEX_IOVQ PEX_IOV PEX_IOV PEX_IOV PEX_IOV PEX_IOV PEX_IOV T0 TPT 0.UF/.V 0.UF/0V 0.UF/0V 0 0.UF/0V L0 0NH 0.UF/0V 0.UF/.V 0.UF/0V.UF/.V 0.UF/0V.UF/.V 0 0.UF/.V 0.UF/0V 0.UF/.V 0 0.UF/0V 0.UF/.V R0 0KOhm r00 0.UF/0V 0.UF/0V.UF/.V 0.UF/0V 0UF/.V 0 0.UF/0V 0 0.UF/0V 0.UF/0V 0.UF/.V L0 /00Mhz 0.0UF/V 0.UF/0V 0.UF/.V 0.UF/0V 0 UF/.V 0.UF/0V R0 LK_PIE_FX# LK_PIE_FX UF_PLT_RT#,,,,,,,,, /PIFO, PIE_RXP[0..] PIEN_RXP[0..] PIE_RXN[0..] PIEN_RXN[0..]

25 at least mils 0 m Place elow PU 0 m. at least mils Normal 0/0 R. 00..,, 00 UTek OMPUTER IN M()--Memory IF.0 Fc ajun_ho ate: heet of Title : Engineer: +VRM_FVTT F_ F F F F_Q F_Q F F_Q F_ F_Q F F0 F_Q# F_Q#0 F F F0 F F_QM F F0 F_ F F F_ F F F_ F_0 F_0 F F F F F F F F F F F_Q F_ F_Q# F F_Q# F_QM F F_QM F_Q# F_Q# F F F_ F F F F F F F_QM F F_Q# F0 F F F F F F F_Q F F_Q# F F F_QM F F_QM0 F F_ F F0 F_ F F_QM F_ F_ F_QM F F F0 F F_Q F F_Q0 F F F F F0 +.VP_F_PLLV F_VREF +.VP_F_PLLV F_VREF +.VP_F_PLLV F_ F F F F_Q F F F F F F_QM F_Q# F0 F F F F0 F F_Q# F F_QM F F F F_QM0 F_Q0 F_Q F F F F_Q# F F F F F F F F F_QM F_Q# F_Q# F F_QM F_Q#0 F F0 F F_Q F F F F F0 F_QM F_Q# F0 F F F F F F F F F_Q F_Q F F F F_Q F F F F F0 F F F_QM F_Q# F0 F F F F F F F_QM F_Q F_M F_M F_R# F_ F_ F_ F_ F_ F_ F_ F_0 F_ F_ F_ F_ F_ F_ F_0 F_ F_ F_ F_ F_R# F_ F F +VRM +.VP +VRM +VRM +VRM +VRM +.VP +VRM +.VP T0 TPT 0.UF/0V.UF/.V 0.UF/.V 0.UF/0V 00PF/V T0 TPT T TPT 0.UF/0V U0 NP- F E E E F0 E E0 E0 F F E E E E E F E E E F E F E E E F0 F J H K 0 F 0 E F F E 0 F E E F F E 0 U T M L K K K K K K J J J J0 H H N FQ_RN FQ_RN FQ_RN FQ_RN FQ_RN FQ_RN FQ_RN FQ_RN0 FQ_WP FQ_WP FQ_WP FQ_WP FQ_WP FQ_WP FQ_WP FQ_WP0 FQM FQM FQM FQM FQM FQM FQM FQM0 F F F F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F F F F F F F F0 FL_TERM_ FL_PU_ FL_P_VQ N N N I_L I_ F_EU N0 F_M F_LK_N F_LK F_LK0_N F_LK0 F_M F_M F_M F_M F_M F_M F_M0 F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M0 F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M0 FVTT FVTT FVTT FVTT FVTT FVTT FVTT FVTT FVTT0 FVTT FVTT FVTT FVTT FVTT FVTT FVTT FVTT FVTT 0.UF/.V R0 KOhm U0 NP- E H F L K M H0 F L K L 0 0 K0 F 0 M0 M E F H F 0 E E0 E L0 M K J J0 J F0 M0 0 Y 0 E F E E F J E H H E0 0 E H F0 H K0 H0 L J0 L0 L N N0 N P0 J J K K L N M N Y0 Y R P Y U P R0 R W T0 V R U V0 V T W0 W U T T V T W W Y U0 P U P V V R R M M L L H H H H H H V R M J F K 0 F_VREF FQ_RN FQ_RN FQ_RN FQ_RN FQ_RN FQ_RN FQ_RN FQ_RN0 FQ_WP FQ_WP FQ_WP FQ_WP FQ_WP FQ_WP FQ_WP FQ_WP0 FQM FQM FQM FQM FQM FQM FQM FQM0 F F F F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F F F F F F F F0 F_PLL F_PLLV H_PLLV N N F_EU N F_M F_LK_N F_LK F_LK0_N F_LK0 F_M F_M F_M F_M F_M F_M F_M0 F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M0 F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M0 FVQ FVQ FVQ FVQ FVQ0 FVQ FVQ FVQ FVQ FVQ FVQ FVQ FVQ FVQ FVQ0 FVQ FVQ FVQ FVQ FVQ FVQ FVQ FVQ FVQ F_M FV FV FV FV FV FV FV FV FV0 FV FV FV FV FV FV FV FV F_M FV 0.UF/0V 0.UF/0V 00PF/V L0 R 0 0.0UF/V 0 000PF/V L0 0.UF/.V R0 0PF/0V R.UF/.V R KOhm % 0 000PF/V 0.UF/0V.UF/.V R KOhm 0.UF/.V 0 0.UF/.V R0.UF/.V R0 KOhm % 0 0.UF/0V R0 0.Ohm % 0 000PF/V 0PF/0V T TPT R 0.Ohm % 0 000PF/V 0.UF/0V 0 000PF/V 0 000PF/V 00PF/V 0.UF/0V L0 0.UF/.V T TPT 0 0.UF/0V.UF/.V T TPT 0PF/0V F[0..] F_QM[0..] F_Q[0..] F_Q#[0..] F[0..] F_Q[0..] F_QM[0..] F_[0..] F_[..] F_ NVF_OT F_[..] F_[0..] F_LK0# F_LK F_LK# F_LK0 F_LK0# F_LK F_LK# F_LK0 F_# F_0# F_KE F_0 F_WE# F_# F_ F_0# F_KE F_0 F_WE# F_R# F_R# F_Q#[0..] NVF_EU NVF_EU NVF_OT M_T,, M_LK,,

26 R ustom,, 00 UTek OMPUTER IN M()--F_VRM_.0 Fc ajun_ho ate: heet of Title : Engineer: F_KE F_LK0 F_LK0# F_KE F_KE F_LK F_LK# F_R# F_WE# F_0# F_# F_R# F_WE# F_0# F_# F_R# F_WE# F_0# F_# F_0 F_ F_ F F F_ F F F F_0 F F_ F0 F_ F F_ F F_ F F F_ F F_ F0 F_ F F_ F F_ F F_0 F_Q F_Q0 F_Q#0 F_Q# F_OT F_OT F_ F F F_ F F F_0 F F_ F0 F F0 F F F F_ F F_ F F_ F F_ F F_0 F_0 F_ F_ F_ F_0 F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 F_0 F_ F_ F_ F_0 F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 F_0 F_ F F0 F F F F F F F F F F F F F0 F F F F F F F F F F F F F F F F0 F F_Q F_Q F_Q# F_Q# F_Q F_Q F_Q# F_Q# F_Q F_Q F_Q# F_Q# F_OT F_OT F_QM0 F_QM F_QM F_QM F_QM F_QM F_QM F_QM F_VERF0 F_VERF F_VERF0 F_VERF F_VERF0 F_VERF F_OT F_KE F_ F_ F_0# F_ F_ F_ F_WE# F_ F_ F_ F_# F_ F_ F_LK F_LK0# F_LK0 F_LK# F_R# F_ F_ F_0 F_0 F_ F_ F_ F_0 F_ F +VRM +VRM +VRM +VRM +VRM +VRM +VRM +0.V +VRM +VRM +VRM +VRM 0.UF/V RN0 Ohm R0 0KOhm 000PF/0V R 0KOhm RN0E Ohm R0 KOhm 0.UF/V 0 0.UF/V U0 HYPFP E E E E E F F F F F F H H H H H H J J J J J J K K K K K L L L L L M M M M M N N N N N P P P P P R R R R R E V N V VQ UQ/Q VQ UM VQ UQ/Q VQ UQ/Q VQ VQ UQ0/Q0 VQ0 UQ/Q VQ UQ/Q UQ/Q VQ0 UQ/Q V N V VQ VQ LQ/Q VQ LM LQ VQ LQ/Q VQ LQ/Q VQ VQ LQ0/Q0 VQ LQ/Q VQ LQ/Q LQ/Q VQ LQ/Q VL VREF V VL K V KE WE# R# K# OT N/ 0 # # 0/P 0 V V V V N N N/ UQ UQ# VQ LQ# RN0 Ohm 0.UF/V 0.UF/V 0UF/.V 0 UF/V R0 RN0 Ohm 0.UF/V 0 UF/V RN0E Ohm 0 0.UF/V 0UF/.V RN0 Ohm RN0F Ohm 0.0UF/V 0 UF/V U0 HYPFP E E E E E F F F F F F H H H H H H J J J J J J K K K K K L L L L L M M M M M N N N N N P P P P P R R R R R E V N V VQ UQ/Q VQ UM VQ UQ/Q VQ UQ/Q VQ VQ UQ0/Q0 VQ0 UQ/Q VQ UQ/Q UQ/Q VQ0 UQ/Q V N V VQ VQ LQ/Q VQ LM LQ VQ LQ/Q VQ LQ/Q VQ VQ LQ0/Q0 VQ LQ/Q VQ LQ/Q LQ/Q VQ LQ/Q VL VREF V VL K V KE WE# R# K# OT N/ 0 # # 0/P 0 V V V V N N N/ UQ UQ# VQ LQ# RN0F Ohm RN0 Ohm 0.0UF/V 0.0UF/V 0 0UF/.V RN0 Ohm 0 RN0 Ohm 0.0UF/V 000PF/0V 0.UF/V R0.KOHM RN0H Ohm R0 Ohm RN0E Ohm 0.UF/V 0UF/.V RN0 Ohm 0 RN0 Ohm 0.UF/V R0.KOHM R0 Ohm RN0 Ohm RN0F Ohm 000PF/0V U0 HYPFP E E E E E F F F F F F H H H H H H J J J J J J K K K K K L L L L L M M M M M N N N N N P P P P P R R R R R E V N V VQ UQ/Q VQ UM VQ UQ/Q VQ UQ/Q VQ VQ UQ0/Q0 VQ0 UQ/Q VQ UQ/Q UQ/Q VQ0 UQ/Q V N V VQ VQ LQ/Q VQ LM LQ VQ LQ/Q VQ LQ/Q VQ VQ LQ0/Q0 VQ LQ/Q VQ LQ/Q LQ/Q VQ LQ/Q VL VREF V VL K V KE WE# R# K# OT N/ 0 # # 0/P 0 V V V V N N N/ UQ UQ# VQ LQ# 0.UF/V 0.0UF/V R0 KOhm 0 0.UF/V R0 0KOhm RN0 Ohm 0 0.0UF/V RN0 Ohm 0 0.UF/V 0 0.0UF/V 0 0.0UF/V 0.UF/V 0.UF/V RN0H Ohm 0.UF/V R0 0 UF/V 0.0UF/V RN0H Ohm RN0 Ohm RN0 Ohm RN0 Ohm 0 0.0UF/V 000PF/0V U0 HYPFP E E E E E F F F F F F H H H H H H J J J J J J K K K K K L L L L L M M M M M N N N N N P P P P P R R R R R E V N V VQ UQ/Q VQ UM VQ UQ/Q VQ UQ/Q VQ VQ UQ0/Q0 VQ0 UQ/Q VQ UQ/Q UQ/Q VQ0 UQ/Q V N V VQ VQ LQ/Q VQ LM LQ VQ LQ/Q VQ LQ/Q VQ VQ LQ0/Q0 VQ LQ/Q VQ LQ/Q LQ/Q VQ LQ/Q VL VREF V VL K V KE WE# R# K# OT N/ 0 # # 0/P 0 V V V V N N N/ UQ UQ# VQ LQ# 0.UF/V F_LK0 F_LK0# F_KE F_LK F_LK# F_# F_R# F_0# F_WE# F_Q#[0..] F_Q[0..] F_QM[0..] F_[0..] F[..] F[0..] F_0 F_ F_ F_ F_ F_ NVF_OT NVF_EU

27 R ustom,, 00 UTek OMPUTER IN M()--F_VRM_.0 Fc ajun_ho ate: heet of Title : Engineer: F F F F F F_R# F_WE# F0 F F F_0# F_# F F F F F F F0 F F_Q0 F_Q F_Q# F_Q#0 F_ F_QM F_QM F_0 F_ F_VERF0 F_KE F_0 F_0 F_OT F_OT F_LK0 F_LK0# F_KE F_0 F_OT F_ F_ F_0 F_ F_ F_ F_ F_0 F_ F_QM F_QM0 F_KE F_QM F_QM F_0 F_ F_ F_# F_0 F_VERF F_KE F_LK F_LK# F_VERF0 F_VERF F_ F_OT F_R# F_WE# F_0# F_OT F_R# F_WE# F_0# F_# F_Q F_Q# F_Q F_Q# F_QM F_QM F_0# F_VERF0 F_VERF F_# F_Q F_Q# F_Q F_Q# F_0 F_ F_ F_ F_ F_ F_ F_ F_0 F_ F_ F_ F_0 F_ F_ F F F F0 F F F0 F F F F F F F F F F0 F F F F F F F F F F F F F F0 F F_ F_ F_ F_ F_ F_ F_0 F_ F_ F_ F_0 F_ F_ F_ F_ F_ F_ F_ F_ F_0 F_ F_ F_ F_0 F_ F_ F_ F_ F_ F_ F_ F_LK F_LK# F_LK0 F_LK0# F_ F_ F_ F_ F_R# F_ F_ F_ F_WE# F_ F_ F_Q F F F0 F F F F F_Q# F F F F F F_Q# F F F_Q F F +VRM +VRM +VRM +VRM +0.V +VRM +VRM +VRM +VRM +VRM +VRM +VRM 0.0UF/V RN0 Ohm 0 UF/V RN0H Ohm 0.UF/V RN0F Ohm 000PF/0V 000PF/0V 0 0.UF/V RN0 Ohm UF/V R0 KOhm RN0 Ohm 0 R 0 0.UF/V R0.KOHM 0 0.0UF/V 0.UF/V RN0 Ohm 0 RN0 Ohm 0.UF/V RN0E Ohm 0.UF/V 0.0UF/V 0 UF/V 0.UF/V 0.0UF/V 0.0UF/V 0.UF/V RN0 Ohm 0.0UF/V 000PF/0V RN0 Ohm 0.0UF/V 0 0.UF/V RN0 Ohm 0.0UF/V R0 0KOhm R0 0KOhm R0 KOhm RN0H Ohm 0UF/.V RN0 Ohm 0 0.UF/V 0UF/.V RN0 Ohm U0 HYPFP E E E E E F F F F F F H H H H H H J J J J J J K K K K K L L L L L M M M M M N N N N N P P P P P R R R R R E V N V VQ UQ/Q VQ UM VQ UQ/Q VQ UQ/Q VQ VQ UQ0/Q0 VQ0 UQ/Q VQ UQ/Q UQ/Q VQ0 UQ/Q V N V VQ VQ LQ/Q VQ LM LQ VQ LQ/Q VQ LQ/Q VQ VQ LQ0/Q0 VQ LQ/Q VQ LQ/Q LQ/Q VQ LQ/Q VL VREF V VL K V KE WE# R# K# OT N/ 0 # # 0/P 0 V V V V N N N/ UQ UQ# VQ LQ# R0.KOHM 0.UF/V 0 UF/V 0.UF/V 0 UF/V U0 HYPFP E E E E E F F F F F F H H H H H H J J J J J J K K K K K L L L L L M M M M M N N N N N P P P P P R R R R R E V N V VQ UQ/Q VQ UM VQ UQ/Q VQ UQ/Q VQ VQ UQ0/Q0 VQ0 UQ/Q VQ UQ/Q UQ/Q VQ0 UQ/Q V N V VQ VQ LQ/Q VQ LM LQ VQ LQ/Q VQ LQ/Q VQ VQ LQ0/Q0 VQ LQ/Q VQ LQ/Q LQ/Q VQ LQ/Q VL VREF V VL K V KE WE# R# K# OT N/ 0 # # 0/P 0 V V V V N N N/ UQ UQ# VQ LQ# 0.UF/V RN0F Ohm 0.UF/V 000PF/0V RN0H Ohm 0.UF/V 0.0UF/V R0 Ohm RN0F Ohm U0 HYPFP E E E E E F F F F F F H H H H H H J J J J J J K K K K K L L L L L M M M M M N N N N N P P P P P R R R R R E V N V VQ UQ/Q VQ UM VQ UQ/Q VQ UQ/Q VQ VQ UQ0/Q0 VQ0 UQ/Q VQ UQ/Q UQ/Q VQ0 UQ/Q V N V VQ VQ LQ/Q VQ LM LQ VQ LQ/Q VQ LQ/Q VQ VQ LQ0/Q0 VQ LQ/Q VQ LQ/Q LQ/Q VQ LQ/Q VL VREF V VL K V KE WE# R# K# OT N/ 0 # # 0/P 0 V V V V N N N/ UQ UQ# VQ LQ# RN0E Ohm 0.UF/V RN0 Ohm RN0 Ohm R0 RN0 Ohm RN0E Ohm 0 0.UF/V 0UF/.V U0 HYPFP E E E E E F F F F F F H H H H H H J J J J J J K K K K K L L L L L M M M M M N N N N N P P P P P R R R R R E V N V VQ UQ/Q VQ UM VQ UQ/Q VQ UQ/Q VQ VQ UQ0/Q0 VQ0 UQ/Q VQ UQ/Q UQ/Q VQ0 UQ/Q V N V VQ VQ LQ/Q VQ LM LQ VQ LQ/Q VQ LQ/Q VQ VQ LQ0/Q0 VQ LQ/Q VQ LQ/Q LQ/Q VQ LQ/Q VL VREF V VL K V KE WE# R# K# OT N/ 0 # # 0/P 0 V V V V N N N/ UQ UQ# VQ LQ# R0 0KOhm RN0 Ohm RN0 Ohm R0 Ohm 0 0UF/.V F_[0..] F[..] F[0..] F_0 F_ F_0# F_WE# F_KE NVF_OT F_# F_R# F_ F_ F_ F_ F_LK F_LK# F_LK0 F_LK0# F_Q[0..] F_Q#[0..] F_QM[0..] NVF_EU

28 0m 0m at least mils at least mils LK_FX_ TYPE LK_FX_NO R0 R0 rystal mount mount X0,, mount 0/0 R ustom,, 00 UTek OMPUTER IN M()-&ecoupling.0 Fc ajun_ho ate: heet of Title : Engineer: +.V_IP_PLLV +.V_PLLV XIN_V XOUT_V +.VP +.VP U0M NP- T U0 T0 T U T U XTLIN PLL IP_PLLV PLLV XTLOUT XTLOUTUFF XTLIN 0.UF/.V R0 R0 0KOhm R0 0KOhm 0 PF/0V 0 PF/0V 0.UF/.V 0 00PF/V / U0 NP- J J J J H H F F F F F F F F M M M M0 M M M L L L L L L L L K K K J J J J J J0 J J J J0 H 0 F F F F F E E E 0 Y Y Y Y W W W W V V0 V V V V V V U U U U U T T T T T R R0 R R R R R R P P P P N N N N M M M M L L K K K K _ENE UF/0V 0.UF/.V 0 0.UF/0V 0 00PF/V L0 L0 T0 TPT X0 Mhz R0 R0 0.Ohm % LK_FX_NO LK_FX_, XTLOUTUFF

29 LV c00 PF/0V 0 TM_TXN TM_TXP c00 PF/0V 0 TM_TXN TM_TXP c00 PF/0V TM_TX0N c00 PF/0V 0 TM_TXN U0I 0 0.0UF/V M IFP_VPROE R0 KOhm L IFP_RET +VRM at least mils m L0 +.V_IFP_PLLV IFP_PLLV UF/.V.UF/.V 00PF/V 0PF/0V IFP_PLL +VRM at least 0 mils L0 0 m +.V_IFP_IOV F IFP_IOV F IFP_IOV.UF/.V 00PF/V 00PF/V IFP_TX_N J K IFP_TX IFP_TX0_N J IFP_TX0 H IFP_TX_N H H IFP_TX IFP_TX_N K IFP_TX J IFP_TX_N H IFP_TX J L IFP_TX_N IFP_TX K IFP_TX_N M IFP_TX M L IFP_TX_N IFP_TX M LV_LLKN LV_LLKP LV_L0N LV_L0P LV_LN LV_LP LV_LN LV_LP LV_ULKN LV_ULKP LV_U0N LV_U0P LV_UN LV_UP c00 PF/0V c00 PF/0V 0 TM_TXN TM_TXP U0J 0 0.0UF/V K IFP_VPROE R0 KOhm H IFP_RET +VRM at least mils m L0 +.V_IFP_PLLV 0 IFP_PLLV 0.UF/.V.UF/.V 00PF/V 0PF/0V 0 IFP_PLL TM_TX0P TM_TXN TM_TXP c00 PF/0V IFP_TX_N M IFP_TX M IFP_TX0_N E IFP_TX0 E F IFP_TX_N IFP_TX F IFP_TX_N H IFP_TX TM_TXP TM_TXN TM_TXP TM_TXN TM_TXP TM_TX0N TM_TX0P TM_TXN TM_TXP TM_TXN TM_TXP +V +V L0 L0 m at least mils.uf/.v 00 m.uf/.v 00PF/V at least mils 00PF/V 0PF/0V 0PF/0V 0.0UF/V 0.0UF/V NP- +V V _VREF _RET R0 Ohm % +V V _VREF _RET R0 Ohm %,,0, 0 H0 H V R R PM_PWROK U0F _V _VREF _RET NP- U0H _V _VREF _RET NP- dd ackrive +V V TV IFP_TX_N IFP_TX IFP_TX_N IFP_TX R0 R0 K K L K Q0 N00K_T_E R0 I_L I HYN _VYN _RE _REEN _LUE _IUMP _RE _REEN _LUE _IUMP LV_UN LV_UP 0KOhm K J F0 K0 H J H R T T V +V R R +V_IFP near PU 00 m.uf/.v Q0 I0_T_E +V_IFP L0.UF/.V OHM OHM RT_HYN RT_VYN 00PF/V 00PF/V at least mils +V_IFP_IOV R0 0KOhm R R0 R T-I/RM0FTN00 T-I/RM0FTN00 T-I/RM0FTN00 <> <> R R R T-I/RM0FTN00 T-I/RM0FTN00 T-I/RM0FTN00 <> <> 0 <> RT LK RT T TV_ TV_Y TV_V RT_RE RT_REEN RT_LUE <> T0 TPT T0 TPT T0 TPT TPT T0 T0 TPT R0 0/0 E 0KOhm F E H H U V U U U V V H F U0E N N N N N NP- IFP_IOV IFP_IOV NP- U0 _V _VREF _RET NP- PIO N N0 _YN PIO N N HP HPROM 0/0 IFP_TX_N IFP_TX IFP_TX_N IFP_TX IFP_TX_N IFP_TX IFP_TX_N IFP_TX _HYN _VYN _RE _REEN _LUE _IUMP U0 I_L I_ N V N N N L H J F E H J K L L J J +V_HPOROM HPROML HPROM T00_U OM HNE TO ROM_N ROM_O ROM_I ROM_LK IH_L IH_ UFRT_N TEREO WPRY_ N TETMOE W H TPT TPT TPT R 0KOhm HPROML HPROM F +V T R 0KOhm M WPRY_ R 0KOhm TETMEMLK H TETMOE L0 R0 0KOhm VI LK VI T T0 T0 T0 R TM_TXN TM_TXP TM_TXN TM_TXP TM_TXN TM_TXP +V 0KOhm 0 0.UF/0V +V near PU UTek OMPUTER IN Title : Engineer: M()_LV&V&TV ajun_ho ustom Fc,, 00 ate: heet of.0

30 +V U0N 0m MIO_VQ 00 MIO_VQ MIO_VQ 0.UF/0V MIO_VQ MIO_VQ T0 Y MIOL_P_VQ TPT T00 Y MIOL_PU_ TPT MIO0 MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO0 MIO N N N N W V Y W MIO0 MIO MIO MIO MIO MIO MIO MIO MIO T00 TPT T00 TPT T00 TPT R00 R00 R00 R00 R00 0KOhm 0KOhm 0KOhm 0KOhm KOhm MIO0 MIO MIO MIO MIO MIO MIO MIO MIO TRP R00 R00 R00 R00 R0 R0 R0 R0 0KOhm 0KOhm 0KOhm 0KOhm KOhm KOhm KOhm KOhm +V T0 Y MIO_VREF TPT NP- +V U0K 0m M MIO_VQ M 00 MIO_VQ R MIO_VQ T 0.UF/0V MIO_VQ U MIO_VQ T0 L MIOL_P_VQ TPT T0 L MIOL_PU_ TPT N W N W N0 V +V N Y MIO_VYN E T0 TPT R0 MIO_HYN F R0 MIO_E 0/0 MIO_TL R0 T0 TPT MIO_LKOUT T0 TPT MIO_LKOUT_N MIO_LKIN E R00 0KOhm P MIO0 MIO0 N MIO MIO MIO N T00 TPT MIO N T00 TPT MIO M T00 TPT M T00 TPT MIO P MIO MIO MIO N T00 TPT N MIO MIO M MIO MIO MIO0 L T00 TPT MIO L T00 TPT KOhm KOhm KOhm MIO0----RM_F0 MIO----RM_F MIO----RM_F MIO----RM_F RM_F[:0] onfig F us Width efinitions //NP-E 000 Mx R -bit amsung, Micron 000 Mx R -bit Qimonda 00 Mx R -bit Hynix ///NM-E 00 Mx R -bit amsung, Micron 00 Mx R -bit Qimonda 0 Mx R -bit Hynix MIO----PI_EVI0 NP-E 0x0 000 MIO----PI_EVI MIO----PI_EVI MIO---PI_EVI NM-E 0x PI_EVI(on't care) R0 KOhm MIO MIO0 MIO MIO MIO TRP R0 R0 R0 R0 KOhm KOhm KOhm KOhm +V wait check T0 L TPT MIO_VREF 0/0 MIO----U_VENOR MIO0----PEX_PLL_EN_TERM 0,YTEM IO,isable 0/0 MIO_HYN MIO_VYN MIO_E MIO_TL R00 KOhm R R P T0 TPT P MIO----IO_PF_LUT_R0 MIO----IO_PF_LUT_R MIO----IO_PF_LUT_R [:0] 00 for NV/NV 00 for x, NV MIO_LKOUT R MIO_LKOUT_N P N M NP- R0 wait check 0KOhm +V PU VI (PIO) PU VI0 (PIO) NVV Powermizer U0L RN00.KOhm RN00.KOhm V Max Performance.V alanced Mode.0V Max aving N F V_THRM_ V_THRM_ J K THERMN THERMP I_L I_ R0 Ohm R0 Ohm EI_LK,, EI_T,, T0 TPT +V RN00 0KOhm J RN00 0KOhm K 0KOhm RN00 K L RN00 0KOhm L wait check JT_TK JT_TM JT_TI JT_TO JT_TRT_N NP- PIO0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO0 PIO PIO K R0 0KOhm H K T0 TPT E J R0 R00 K E R0 V_OVERT# T0 TPT H F E R0 _IN_O#,,0 TM_HP L_V_EN PWRNTL_0 PWRNTL_ R0 0KOhm,,, PM_PWROK R0 R0 0KOhm 0KOhm R0 +V U00 V Y NLZ0XVT PIO0, -- Hot Plug etect (For VI) PIO -- Panel backlight brightness (PWM), PIO -- Panel power enable L_KLTEN_V PIO -- Panel backlight ON/OFF PIO -- PU VI0 PIO -- PU VI PIO -- PU VI or MEM VI PIO -- Thermal diode LERT PIO -- Fan control PIO -- HTV enable Title : M()_MIO&PIO UTeK OMPUTER IN Engineer: ajun_ho ustom Fc,, 00 ate: heet of 0.0

31 roup Place closer to PU +V_0 0 0PF/0V 0 0.UF/0V 0 0.UF/0V R0.Ohm 0.UF/.V +V XTLOUTUFF, LK_FX_ R0 Ohm R0 Ohm Place close to I0 LKIN_0 XTLIN R0 0KOhm U0 LKIN P# V LK T LKOUT/F_IN0 REF_OUT/F_IN I0MLF +V R0 0KOhm EI_LK 0,, EI_T 0,, I RE: 0xH FIN_ MHz PRE % EFULT M--> MHz -0. OWN MHz---> MHz -. OWN UTeK OMPUTER IN Title : M()- Engineer: ajun_ho ustom Fc,, 00 ate: heet of.0

32 PLE E iodes near ON0 ustom,, 00 UTeK OMPUTER IN RT.0 Fc ajun_ho ate: heet of Title : Engineer: _T_ON _LK_ON HYN_RT RT_LUE RT_RE VYN_RT RT_REEN _LK_V HYN_RT VYN_RT +V_RT T_V +V_RT_ +V_RT_ RT_R_ON_L RT ON_L RT ON_L RT_R_ON RT ON RT ON VYN_ON HYN_ON _T_ON HYN_ON VYN_ON _LK_ON +V +V +V +V +V +V +V +V +V +V +V +V 0 PF/0V c00 0PF/0V c00 0 0PF/0V c00 R0 L0 /00Mhz L0 Ohm/00Mhz RN0.KOhm 0 PF/0V c00 RTN0 _U_PR 0 0 PF/0V c00 0 PF/0V c00 0 PF/0V c00 R0 % R0 % L0 Ohm/00Mhz 0 PF/0V c00 L0 Ohm/00Mhz L0 Ohm/00Mhz R0 % Q0 N00K_T_E L0 /00Mhz 0 V Q0 N00K_T_E 0PF/0V c00 0 NW L0 Ohm/00Mhz 0 0PF/0V c00 RN0.KOhm R0 RN0.KOhm 0PF/0V c00 RN0.KOhm 0 V L0 Ohm/00Mhz 0 0PF/0V c00 0 V Q0 N00K_T_E Q0 N00K_T_E 0 V 0 V 0 PF/0V c00 RT_HYN RT_VYN RT T RT_LUE RT_REEN RT_RE RT LK

33 L Power LN0 TO_ON_0P 0 L_V_EN +V Q0 N00K_T_E R0 00KOhm r00 R0 00KOhm r00 +V Q0 N00K_T_E R0 0KOhm r00 R0 r00 0 NW 0 UF/V c00_h 0 Q0 IV +VL UF/V c00 0.0UF/V L0 /00Mhz 0 0.UF/V c00 +V 0 0 0UF/0V UF/0V c00 able Requirement: Impedence: 00 ohm +/- 0% Length Mismatch <= 0 mils Twisted Pair(Not Ribbon) Maximum Length <= " 0,, EI_LK 0,, EI_T +V_L 0 0.UF/V c00 LV_L0N LV_L0N LV_L0P LV_L0P LV_LN LV_LN LV_LP LV_LP 0 0 LV_LN LV_LN LV_LP LV_LP LV_LLKN LV_LLKN 0 LV_LLKP 0 LV_LLKP L0 /00MhzEILKON /00MhzEITON +V_L 0 L PF/0V 00PF/0V 0 0.UF/V c00 LV_UN LV_UN LV_UP LV_UP LV_U0N LV_U0N LV_U0P LV_U0P LV_UN LV_UN LV_UP LV_UP LV_ULKN LV_ULKN LV_ULKP LV_ULKP +V_EI L0 +V /00Mhz +V_L L LV Interface LV_LLKN LV_ULKN LV_LLKP.pF/0V LV_ULKP 0.pF/0V L acklight ontrol INVERTER Interface/peaker ONN. _T_Y_INV L0 /00Mhz +VIN_INV UF/V c00_h U_PN U_PP R0 R0 U_P- U_P+ L0 U_INVON_PWR +V /00Mhz + E0 0.UF/V 0UF/0V UF/.V c00 c00 +V, L_ U# LIW# LIW# 0OHM L_EN 0OHM 0OHM 0OHM RN0 RN0 RN0 RN0 +V_L R0 0KOhm 0 r00 TW LI_E#_ON L_EN_ON L ON +V_ON 0.UF/V 00PF/0V c00 INTMI_P 0.UF/V 0.UF/V INTMI_N c00 c00 amera +VIN_INV LI_E#_ON L_EN_ON L ON +V_ON U_P- U_P+ UF/0V +V INVN0 WTO_ON_0P R0 0KOhm r00 IM_LK, IM_T, IM_VPP, IM_RT, U_INVON_PWR IM_PWR 0 L_KLTEN_V L_KOFF# 0 TW L_EN UTeK OMPUTER IN Title : LV & INVERTER Engineer: ajun_ho ustom Fc,, 00 ate: heet of.0

34 U_PP R0 U_P+ U_PN R0 U_P- +V L0 /00Mhz 0 UF/0V U_P- U_P+ FPN0 IE IE WTO_ON_P_FI UTeK OMPUTER IN Title : FINER PRINT Engineer: Jack hen ustom Fc,, 00 ate: heet of.0

35 TV OUT +V 0 TV_V V 0 +V V 0 +V TV_Y TV_ TV_V TV_Y TV_ L0 /00Mhz V_ON L0 /00Mhz Y_ON L0 /00Mhz _ON R0 R0 R PF/0V.PF/0V.PF/0V.PF/0V.PF/0V.PF/0V c00 c00 c00 c00 c00 c00 _ON V_ON Y_ON TVN0 P_ P_ MINI_IN_P V PLE E iodes near TV port VI 0 +V +V_VI +V T RN0.KOHM RN0.KOHM +V RN0.KOHM RN0.KOHM Q0 TM_TXP TM_TXN TM_TXP TM_TXN TM_TXP TM_TXN R0 R0 R0 R0 VIN0 TM_T_+ _K TM_T_- _T TM_T_+ HOT_PLU_ETET TM_T_- 0 TM_T_+ TM_T_- Q0 N00K_T_E N00K_T_E R R Ohm Ohm VI LK VI T TM_TXP TM_TXN TM_TX0P TM_TX0N TM_TXP TM_TXN TM_TXP TM_TXN R0 R0 R R 0 TM_T_+ TM_T_- TM_T_0+ V_YN TM_T_0- TM_T_+ TM_T_- _for+v TM_LK+ +V_POWER TM_LK- TM_LK_hield P_ TM_/_hield P_ TM_T_/_hield TM_T_0/_hield NP_N NP_N L0 R0 /00Mhz 0KOhm 0 R 00KOhm 0PF/0V +V_VI 0 00PF/V 0 +V V TM_HP 0 VI_ON_P UTeK OMPUTER IN Title : TV OUT & VI ON. Engineer: ajun_ho ustom Fc,, 00 ate: heet of.0

36 UTeK OMPUTER IN Title : chematic page name Engineer: ajun_ho ustom Fc,, 00 ate: heet of.0

37 Thermal ensor Q0,, M_LK M_THRM +V +V N00K_T_E Q0 M_THRM M_THRM THRM_LERT# RN0 0KOhm RN0 0KOhm RN0 0KOhm RN0 0KOhm,, M_T M_THRM N00K_T_E M_THRM M_THRM 0 00PF/0V THRM_LERT# 0 00PF/0V Max: m U0 LK V XP LERT# XN OVERT# MXM +V_THM R0 0 0.UF/0V +V 0 PU_THERM_ PU_THERM_ O#_O PU_THERM_ PU_THERM_ O#_O PU_THERM_ PU_THERM_ 0 000PF/0V M_THRM M_THRM 0,, EI_LK 0,, EI_T R0 R0 R0 R0 M_THRM_R M_THRM_R U0 MLK V MT XP LERT# XN THERM# I ddre: 0xH for - +V +V_THM R0 0 V_THRM_ V_THRM_ R0 O#_O 0 0.UF/0V V_THRM_ 0 V_THRM_ 0 V_THRM_ V_THRM_ 0 000PF/0V FN ontrol +V +V_FN H0 H0 +V +V 0 T R0.KOhm + E0 UF/.V 0 NW 0 0.UF/0V FN_PWM FN0_TH ON0 IE IE Wto_ON_P_FN 0 00PF/0V 0 00PF/0V UTeK OMPUTER IN. N Title : Engineer: THER ENOR & FN ajun_ho ustom Fc,, 00 ate: heet of.0

38 UTeK OMPUTER IN Title : chematic page name Engineer: ajun_ho ustom Fc,, 00 ate: heet of.0

39 X0 +V_V +V_VREF.Mhz XIN_LK XOUT_LK +V 0 0 +/-0ppm/0PF 0.UF/0V 0.UF/0V 0 0 R0 PF/V PF/V 0KOhm LKEN0 L0 /00Mhz +V VPIEX VPIEX VPIEX PWRVE#* L0 +V_V 0 /00Mhz VPU +V V UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V XIN_LK X Q0 XOUT_LK X PU_elect N00K_T_E R Ohm LK_# LK_FX_NO Q0 FIX/L_T/PIeT_L0 _IN_O# 0,,0 N00K_T_E R Ohm LK_, LK_FX_ /L_/PIe_L0 V VREF PI/PIEX_TOP# PU_TOP# PUT_LF PU_LF PUT_L0 PU_L0 PUITPT_L/PIeT_L PUITP_L/PIe_L PEREQ#/PIeT_L PEREQ#/PIe_L 0 PIeT_L PIe_L +V_VPI +V 0 0 L0 0.UF/0V 0.UF/0V /00Mhz +V_VPI +V_V +V_VREF R0 R0 TP_PI# TP_PU# LK_MH R0 Ohm LK_MH_LK LK_MH# R0 Ohm LK_MH_LK# LK_PU R0 OHM LK_PU_LK LK_PU# R0 OHM LK_PU_LK# LK_PIE R0 Ohm LK_PIE_LN LK_PIE# R Ohm LK_PIE_LN# T_LK_REQ# R KOhm T_LKREQ# LK_PIE R Ohm LK_PIE_eT LK_PIE# R Ohm LK_PIE_eT# LK_PIE R Ohm LK_PIE_Robson LK_PIE# R Ohm LK_PIE_Robson# Latched Input elect ITP_EN/PILK_F 0 = R Pair = PU_ITP Pair ITP_EN PILK0/REQ_EL 0 = PILK0 (INT/P) = PEREQ# REQ_EL R0 ELPIEX0_L#PILK 0 = PIe/M/L_ = PIe0/OT (INT/PU) ELPIE0_L# R R0 ELL_#/PILK_F 0KOhm 0KOhm 0KOhm +V FL R LK_U.KOhm R0 Ohm _LK_M FL/U_MHz PIeT_L PIe_L LK_PIE LK_PIE# R Ohm R Ohm LK_PIE_FX LK_PIE_FX# 0 = FIX, = L (INT/PU) FL FL FL Reserved for ebug & Expriment +VP R KOhm KOhm KOhm KOhm KOhm R KOhm R KOhm FL FL FL RN0 RN0 RN0 RN0 R LK_KPI LK_PI LK_TPMPI MH_EL0 MH_EL MH_EL 0PF/0V R R OHM FL ELPIE0_L# _LK_PI If don't support Neward ebug ard,pls don't mount R R Ohm Ohm_LK_TPMPI FL/TET_MOE *ELPIEX0_L#PILK PILK PILK PIeT_L PIe_L PIeT_L PIe_L PIeT_L PIe_L PIeT_L PIe_L TLKT_L TLK_L 0 0 LK_PIE LK_PIE# LK_PIE LK_PIE# LK_PIE LK_PIE# LK_PIE LK_PIE# LK_T LK_T# R Ohm R Ohm R Ohm R Ohm R Ohm R0 Ohm R Ohm R Ohm R Ohm R Ohm LK_PIE_NEWR LK_PIE_NEWR# LK_PIE_WLN LK_PIE_WLN# LK_PIE_IH LK_PIE_IH# LK_MH_PLL LK_MH_PLL# LK_T_IH LK_T_IH# ELL_# R 0KOhm LK_PI R0 Ohm PIeT_L/OTT_MHzL LK_PIE R Ohm LK_PIE_WWN LK_PI LK_PI 0PF/0V R 0 LK_PI 0PF/0V 0PF/0V.PF/0V 0PF/0V R OHM LK_IHPI OhmREQ_EL ELL_# ITP_EN PILK0/REQ_EL** *ELL_#/PILK_F ITP_EN/PILK_F PIe_L/OT_MHzL *PEREQ# PEREQ#* VttPWR_/P# 0 LK_PIE# PEREQ# PEREQ# R R R Ohm IH_LKEN LK_PIE_WWN# LK_NEWR_REQ# LK_WLN_REQ#,0,,,,, M_LK_,0,,,,, M_T_ R R LK T REF/FL/TET_EL REF0 0 REF REF0 R R0 0KOhm Ohm FL LK_IH PU_EL0 PU_EL PU_EL LK 00 +V RN0 FL 0OHM RN0 FL 0OHM RN0 FL 0OHM RN0 0OHM PIE pread% EL EL EL0 00 +/- 0. L H H 00 +/- 0. L H L R % KOhm 0 00PF/0V R 0PF/0V 00PF/0V % VREF ILPRLF-T 0PF/0V UTeK OMPUTER IN. N Title : Engineer: LOK EN-ILPR ajun_ho ustom Fc,, 00 ate: heet of.0

40 UTeK OMPUTER IN Title : chematic page name Engineer: ajun_ho ustom Fc,, 00 ate: heet of 0.0

41 PWRW# TPT T0 W0 TP_WITH_P MRTHON# ITP# OLOREN# INTERNET# INTNT_ON# W0 TP_WITH_P W0 TP_WITH_P W0 TP_WITH_P W0 TP_WITH_P W0 TP_WITH_P R For witch PWR WITH R0 0KOhm +V PWR_W# R0 0KOhm PWRW# HUT_OWN# +V R0 00KOhm FORE_OFF# W0 FORE_OFF#,,, LI WITH LI_W# 0.0UF/0V Layout note: close to IT R0 0 R. LIW# Note: This LI_E# is a signal from inverter board, it is easy to cause high voltage damage when plugging inverter board connector to M/ with present. It needed to add bidirectional diode to protect this pin. 0 0.UF/V TP_WITH_P RF ON WITH +V_E 0 V LIW# Layout note: close to connector, RFON_W# R0 RF_ONW# R ITP# 0 0.UF/V OLOREN# 0 0.UF/V INTERNET# MRTHON# INTNT_ON# 0 0.UF/V 0 0.UF/V 0 0.UF/V UTeK OMPUTER IN ustom Fc Title : Power on & Res Freq Engineer: ajun_ho,, 00 ate: heet of.0

42 ustom,, 00 UTeK OMPUTER IN. N IHRE & EMI P.0 Fc ajun_ho ate: heet of Title : Engineer: +.V_IHR +V_IHR +V_IHR +V_IHR +0.V_IHR +V_IHR +VRM_IHR +.V_IHR +.V_IHR +VP_IHR +V_IHR +.V_IHR +0.V_IHR +.V_IHR +.V_IHR +V +.V +V +V +V 0.V_VTT_REF +V +VP +V +V +VRM +.V +.V +.V +0.V +.V +.V Q0 N00K_T_E Q N00K_T_E R0 Q0 N00K_T_E R0 R0 Q0 N00K_T_E Q0 N00K_T_E R R R R0 R0 Q0 N00K_T_E R0 R R0 Q N00K_T_E R0 Q N00K_T_E Q N00K_T_E Q N00K_T_E Q0 N00K_T_E Q0 N00K_T_E R 00KOhm R Q N00K_T_E R0 Q0 N00K_T_E R0 00KOhm Q0 N00K_T_E Q0 N00K_T_E R Q N00K_T_E U_E#, U_E#,,

43 UTeK OMPUTER IN Title : chematic page name Engineer: ajun_ho ustom Fc,, 00 ate: heet of.0

44 +.V_LN +.V_LN_ PIE_TXN_LN PIE_TXP_LN LK_PIE_LN_ 0 0.UF/V LK_PIE_LN c00 LK_PIE_LN#_ 0 0.UF/V LK_PIE_LN# c00 +.V_LN PIE_RXP_LN_ PIE_RXN_LN_ 0 0.UF/V c UF/V c00 PIE_RXP_LN PIE_RXN_LN +.V_LN_ LN0 L +.V_LN_ +VU +.V_LN +.V_LN_ +.V_LN +VU,,,,,,,,, UF_PLT_RT#,, PIE_WKE# 0 0.UF/V 0 0.0UF/0V R0.KOhm VH0/VV VL/VL PERTn VMIN_VLL WKEn TETMOE WITH_VUX/VLO MT WITH_VMIN/VV VL/VL VUX_VLL MLK VH0/VREF TWI_T LK_M/N TWI_LK 0 VL0/VL VH/N 0 XOUT_LN _PORn/N PI_LK XIN_LN XTLO PI_ +.V_LN_ XTLI PI_I VL/N PI_O NFIL VL/N +.V_LN_ RI VH/N VH/N VL0/VL LN_EET LN_EELK +.V_LN +.V_LN JP0 MM_OPEN_MIL +.VU EEPROM U0 0 V WP L T0N L0 /00Mhz +.V_LN_ +.V_LN_ +VU +VU +.V_LN_ 0 R0.Ohm RE. OHM /W(00)% 0.UF/V MIP0 R.Ohm RE. OHM /W(00)% 0.UF/V c00 MIN0 R.Ohm RE. OHM /W(00)% MIP R.Ohm RE. OHM /W(00)% 0.UF/V MIN R0 R0 R.Ohm RE. OHM /W(00)% MIP.KOhm.KOhm R.Ohm RE. OHM /W(00)% 0.UF/V MIN R.Ohm RE. OHM /W(00)% +.V_LN_ R0 +.V_LN_ MIP LN_EELK R.Ohm RE. OHM /W(00)% 0.UF/V R0 MIN +.V_LN LN_EET 0 0.UF/V c00 +.V_LN +.V_LN_ rystal X0 Mhz XIN_LN EER/0000 PF/0V c00 XOUT_LN PF/0V c00 +.V_LN 0.UF/V c00 0.UF/V c00 0UF/0V c UF/V c00 +.V_LN_ 0.UF/V c00 0.UF/V c00 0.UF/V c00 0.UF/V c00 +.V_LN JP0 MM_OPEN_MIL L0 /00Mhz +.VU +.V_LN_ 0.UF/V c00 0.UF/V c00 0.UF/V c00 0.UF/V c00 0.UF/V c00 0.UF/V c UF/V c00 +.V_LN_ +.V_LN R0 R0 +.V_LN_ 0.UF/V c00 UTeK OMPUTER IN. N ustom Fc Title : Engineer: LN-L ajun_ho,, 00 ate: heet of.0

45 hange to N0M0 M ONN. H0 H0 LE- LE- Z_OUT_M Z_YN_M Z_IN Z_RT#_M R0 MN0 0 0 JP0 R0 L_JUMP +V +VU Z_LK_M +V 0 0.UF/V c00 0PF/0V TO_ON_P 0 PF/0V LN ONN. +.V_LN R0 U0 MIP0 T+ MX+ L_TRLP0 MIN0 TT T- MT MX- L_MT0 L_TRLM0 L_TRLP0 L0 LTRLP0 MIP MIN MIP MIN R0 T+ TT T- T+ TT T- MX+ MT MX- MX+ MT MX- 0 L_TRLP L_MT L_TRLM L_TRLP L_MT L_TRLM L_TRLM0 L_TRLP L_TRLM L_TRLM L_TRLP L_TRLM0 L_TRLP0 ommon hoke IEEE 0OHM 0OHM 0OHM 0OHM RN0 RN0 RN0 RN0 LTRLM0 LTRLP LTRLM LTRLM LTRLP LTRLM0 LTRLP0 L_MT0 L_MT L_MT RN0 Ohm RN0 Ohm RN0 Ohm LN_ MIP MIN T+ MX+ 0 TT MT T- MX- M00 L_TRLP L_MT L_TRLM L_TRLM L_TRLP L_TRLM L_TRLP L0 ommon hoke LTRLM LTRLP LTRLM LTRLP L_MT RN0 Ohm 0 00PF/0V 0 00PF/0V 0 0.UF/V 0 0.UF/V 0 0.UF/V 0 0.UF/V LTRLP0 LTRLM0 LTRLP LTRLP LTRLM LTRLM LTRLP LTRLM ON0 P_ NP_N L_TRLP L_TRLM L_TRLP L_TRLM IEEE RN0 0OHM RN0 0OHM RN0 0OHM 0OHM RN0 LTRLP LTRLM LTRLP LTRLM ON0 IE IE WTO_ON_P MOEM_TIP_ON MOEM_RIN_ON L0 L0 KOhm/00Mhz KOhm/00Mhz MOEM_TIP 0 MOEM_RIN 0 NP_N P_ 0 MOULR_JK_P 0 000PF/KV 000PF/KV UTeK OMPUTER IN. N ustom Fc Title : M & RJ+ Engineer: ajun_ho,, 00 ate: heet of.0

46 UTeK OMPUTER IN Title : chematic page name Engineer: ajun_ho ustom Fc,, 00 ate: heet of.0

47 . TV. Windigo. Robson +.00V~+.V Max= 0 m TV +V_TV E0 0.UF/0V 0UF/0V 0UF/.V R R0 L0 L0 +.V +.V /00Mhz /00Mhz +V +V Windigo +.00V~+.V Max= 0 m Max=.W LK_PIE_WWN# LK_PIE_WWN mr WKE# T_T T_HLK LKREQ# REFLK- REFLK+.V_.V_ Reserved Reserved Reserved Reserved Reserved UF/0V 0UF/0V m_pwr R m_t R0 m_lk R m_rt R m_vpp R +.V~+.V Max= 00 m IM_PWR IM_T, IM_LK, IM_RT, IM_VPP, +V_TV PIE_RXN_WWN PIE_RXP_WWN PIE_TXN_WWN PIE_TXP_WWN 0 UF/.V 0.UF/0V Reserved Reserved PERn0 PERp0 PETn0 PETp0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved0 W_ILE# PERT#.Vaux.V_ Reserved Reserved 0 Reserved Reserved N LE_WLN# N.V_.V_ WLNm_ON R0 R U_P- U_P+ m_le WLN_LE# R R0 TPT R T0 WLN_ON, UF_PLT_RT#,,,,,,,,, +V +V_TV M_LK_,0,,,,, M_T_,0,,,,, IM_LE#, _ense#, Reserved R to +VU for Wake on WLN function! +.00V~+.V Max= 0 m NP_N NP_N 0 0.UF/0V MINI_R_LTH_P Put it the middle the board IM_PWR m_rt m_t m_lk 0 PF/V c00 0 PF/V c UF/0V 0 000PF/0V TV onn. U_PN R efault U_P- ON0 P_ P_ P_ P_ U_PP R efault U_P+ MMX_JK_P Part Number 0000 H0 H0 T T hange H0,H0 "000" from OM file. UTeK OMPUTER IN. N ustom Fc Title MINI : R-TV/Windigo Engineer: ajun_ho,, 00 ate: heet of.0

48 Windigo +V_TV Robson Robson Robson R LK_PIE_Robson# LK_PIE_Robson PIE_RXN_Robson PIE_RXP_Robson PIE_TXN_Robson PIE_TXP_Robson 0 UF/.V 0.UF/0V.Robson.Windigo.TV mr U_P- U_P+ R m_le TPT T0 R R0 +V R +V 0 0.UF/0V WKE# T_T T_HLK LKREQ# REFLK- REFLK+ Reserved Reserved PERn0 PERp0 PETn0 PETp0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved0 UF/.V.V_.V_ Reserved Reserved Reserved Reserved Reserved W_ILE# PERT#.Vaux.V_ Reserved Reserved 0 Reserved Reserved N LE_WLN# N.V_.V_ NP_N NP_N V_TV 0 0.UF/0V 0 0.UF/0V R R0 m_pwr R m_tr m_lk R m_rt R m_vpp R 0 0UF/0V 0 0UF/0V L0 R L0 /00Mhz /00Mhz +.V +.V +V +V Windigo +.00V~+.V Max= 0 m +.00V~+.V Max= 0 m Max=.W Robson +.V~+.V Max= 00 m IM_PWR IM_T, IM_LK, IM_RT, IM_VPP, WLN_ON, UF_PLT_RT#,,,,,,,,, M_LK_,0,,,,, M_T_,0,,,,, IM_LE#, _ense#, Windigo MINI_R_LTH_P_ The top side depends on -ROM connect to put the board Windigo m_rt m_pwr m_lk m_t 0 PF/V c00 0 PF/V c UF/0V 0 000PF/0V U_PN R U_P- H0 H0 U_PP R U_P+ 0M0-0M0- UTeK OMPUTER IN. N ustom Fc Title : MINI R-Robson Engineer: ajun_ho,, 00 ate: heet of.0

49 L0 L0 /00Mhz /00Mhz +V +V 0 0.UF/0V 0 0UF/0V R0 R0 +.V +.V WLNm0_WKE# R0 Tm0_T T_HT R0 Tm0_LK T_HLK R m0_req# LK_WLN_REQ# LK_PIE_WLN# LK_PIE_WLN mr0 WKE# T_T T_HLK LKREQ# REFLK- REFLK+.V_.V_ Reserved Reserved Reserved Reserved Reserved UF/0V 0 0UF/0V +.V~+.V Max= m PIE_RXN_WLN PIE_RXP_WLN PIE_TXN_WLN PIE_TXP_WLN Reserved Reserved PERn0 PERp0 PETn0 PETp0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved0 W_ILE# PERT#.Vaux.V_ Reserved Reserved 0 Reserved Reserved N LE_WLN# N.V_.V_ R WLN_ON UF_PLT_RT#,,,,,,,,, R +V M_LK_,0,,,,, M_T_,0,,,,, TPT T0 NP_N NP_N MINI_PI_LTH_P 0 0.UF/0V The left side depends on TV connect to put the board +V Q0,, PIE_WKE# WLNm0_WKE# N00K_T_E R0, WLN_ON WLN_ON Q0 Q0 Q0, RFON_W# N00K_T_E N00K_T_E WLN_ON# N00K_T_E _ON# H0 H0 LE- LE- UTeK OMPUTER IN. N ustom Fc Title : MINI R-Kedron Engineer: ajun_ho,, 00 ate: heet of.0

50 UTeK OMPUTER IN Title : chematic page name Engineer: ajun_ho ustom Fc,, 00 ate: heet of 0.0

51 +V --> _RT# ms < T < 00ms Use EEPROM R ustom,, 00 UTeK OMPUTER IN. N R-R().0 Fc ajun_ho ate: heet of Title : Engineer: PI_ X_EN IEL L M_EN _ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ X_EN PI_ PI_ PI_ PI_ PI_ PI_0 _RET# PI_ PI_0 PI_ PI_ M_EN PI_ PI_ IEL_ PI_ PI_ PI HWPN# PI_ PI_ PI_ PI RET# _L _ +V +V +V +V +V +V +V +V R0 0.0UF/V RN0 0KOhm 0 T 0 0UF/0V R UF/0V 0 0.UF/V R0 00KOhm 0 0.0UF/V 0 0UF/0V 0 0.0UF/V 0 0.0UF/V R0 00KOhm R0 0KOhm 0.UF/V RN0 0KOhm RN0 0KOhm R0 00KOhm 0 0.0UF/V 0 0.0UF/V 0PF/0V R0 00KOhm U0 T0N 0 V WP L 0 R_TQFP UIO UIO0/RIRQ# V_V INT# PME# /E0# /E# /E# /E# 0 HWPN# V_PIV_ V_PIV_ V_ROUT PR REQ# NT# ERR# PERR# TOP# EVEL# TRY# IEL IRY# FRME# LKRUN# PIRT# PILK RT# V_ROUT V_M INT# UIO UIO V_RIN TET UIO UIO MEN XEN V_PIV_ V_PIV_ V_PIV_ V_PIV_ V_ROUT V_ROUT V_ROUT 0 RN0 0KOhm 0 UF/0V PM_LKRUN#,, PI_IRY# LK_PI PI_/E# PI_EVEL# _#, PI_REQ0# PI_PERR# PI_TOP# PI_NT#0 PI_RT#, PI_/E#0 PI_INT# PI_/E# PI_FRME# PI_ERR# PI_/E# PI_[:0] PI_INT# PI_TRY# PI_PR INT_ERIRQ,,

52 +V 0 L0 /00Mhz V_PHYV_ V_PHYV_ V_PHYV_ V_PHYV_ UF/V 0 0.UF/V 0 UF/V 0 0PF/0V 0PF/0V 0 XIN_ X0.Mhz +/-0ppm/PF XOUT_ 00/0/0 Open for R XI XO FIL0 TPI0 TPN0 TPP0 TPN0 TPP R0 Ohm 0 R0 Ohm 0 TP0- TP0+ TP0- TP0+ 0.0UF/V 0.UF/V L0 ommon hoke IEEE LTP0- LTP0+ LTP0- LTP0+ ON0 IEEE_ RN0 _REXT 0 R0 R0 RN0 R0 0KOhm % REXT.KOhm R0 Ohm Ohm RN0 RN0 0OHM 0OHM 0OHM 0OHM 0 _VREF 0.0UF/V uard 00 VREF 0PF/0V 0 losed to R losed to onnector o-layout MIO x_t MIO x_t MIO x_t MIO x_t MIO 0 /M/x_T MIO /M/x_T MIO /M/x_T MIO0 /MM/M/x_T0 MIO0 PWR/x_WP# MIO0 /MMM_M_xWE# MIO x_le MIO x_le MIO0 x_e# MIO0 WP#/xR# MIO00 0 /MM#_x0# MIO0 M#/x# MIO0 /MM/MLK_xRE# RV MIO0 MIO0 MIO0 TPT T0 /M/MM/xPWR0 0PF/0V R_TQFP UTeK OMPUTER IN. N Title : Engineer: R-R() ajun_ho ustom Fc,, 00 ate: heet of.0

53 +V R0 0KOhm % Q0 I0_T_E +M_V /M/x_T Q0 olve M uo daptor short problem /x_t Q0 N00K_T_E /M/MM/xPWR0 N00K_T_E 0 0.UF/V 0 0.UF/V R0 0KOhm +V /M/x_T R0 0KOhm % Q0 Q0 N00K_T_E _ /x_t /MM#_x0# N00K_T_E +V R0 0KOhm % M#/x# 0 0PF/0V +M_V +M_V UF/0V 0.UF/0V /MMM_M_xWE# /M/x_T /MM/M/x_T0 /M/x_T M#/x# /M/x_T /MM/MLK_xRE# /x_t /M/x_T /MMM_M_xWE# /MM/MLK_xRE# /MM/M/x_T0 /x_t /MM#_x0# INN0 M_ X_ M_ X_ M_T X_R/ M_T0 X_RE M_T X_E M_IN X_LE M_T X_LE 0 M_LK X_WE M_V X_WP 0 M_ X T X_0 _T X M X X V X LK X X_ N X_ 0 _T0 X_V 0 _T N W _WP_W OM _WP_OM NP_N NP_N R_REER_P 0 N0K /MM#_x0# M#/x# WP#/xR# x_e# x_le x_le /MMM_M_xWE# PWR/x_WP# /MM/M/x_T0 /M/x_T /M/x_T /M/x_T x_t x_t +M_V x_t x_t WP#/xR# 0 UF/0V /MM/MLK_xRE# UTeK OMPUTER IN Title : in R REER Engineer: ajun_ho ustom Fc,, 00 ate: heet of.0

54 R,,, U_E#,,,, VU_ON P_HN# 0KOhm +V U0 R r00 TY# O# 0 HN#.VOUT_ R r00 PERT#.VOUT_ NEWR_O# +.V_PE U_PP R0 U_P+ R0 KOhm +V +.V +VU R 00KOhm.VIN_ UXOUT.VIN_.VIN_.VOUT_.VIN_.VOUT_ UXIN PPE# 0 PU# YRT# RLKEN N R00 +V +VU_PE +V_PE PPE# PU# REFLK_EN U_PN R0 U_P- 0 0 R. R. Q0 UF_PLT_RT#,,,,,,,,, R0 PERT# 0 00PF/0V R0 0KOhm R0 N00K_T_E +V R0 0 R0 KOHM T 0 0.UF/0V PPE# 00KOhm PE_EUEN# Q0 PM0 E R0 KOHM lock 0OHM 0OHM 0OHM 0OHM R RN0 RN0 RN0 RN0 U0 OE# V Y LVV +V lock TPT T0 LP_FRME#,,0,!! Expressard tandard.0: hange Pin from REERVE to MLK hange Pin from MLK to MT hange Pin from MT to +.V LP_FRME#_R +.V_PE +VU_PE +V_PE LK_PIE_NEWR# LK_PIE_NEWR PIE_RXN_NEWR PIE_RXP_NEWR PIE_TXN_NEWR PIE_TXP_NEWR U_P- U_P+ PU# M_LK_ M_T_ PIE_WKE#_ PERT# LKREQ#_ PPE#_ 0 0 Neward Header ON0 0 0 NP_N NP_N EXPRE_R_P LK_PI,,0, LP_,,0, LP_0,,0, LP_,,0, LP_,0,,,,, M_LK_,0,,,,, M_T_ LK_NEWR_REQ# PIE_WKE#_I PE_EUEN# U E# V X NTPWR PPE#_ LKREQ#_ PIE_WKE#_ M_LK_ M_T_ +V 0 0.UF/0V If don't support Neward ebug ard,pls do (a) NI all components of block (b) Mount lock (RN,R) Neward Ejecter ON0 P_ P_ P_ P_ P_ R_EJETOR_P +VU +V +.V +VU_PE +VU_PE 0 0.UF/0V 0 0.UF/0V.0V~.V ve= 00m Max= m.0v~.v +V_PE ve= 000m Max= 00 m 0 0UF/0V 0 0UF/0V 0 0.UF/0V 0.UF/0V.V~.V +.V_PE ve= 00 m Max= 0 m 0 UF/0V 0UF/0V 0 0.UF/0V 0.UF/0V,, PIE_WKE# Q0 N00K_T_E R PIE_WKE#_I REFLK_EN Q0 N00K_T_E LK_NEWR_REQ# UTeK OMPUTER IN. N ustom Fc Title : NEWR Engineer: ajun_ho,, 00 ate: heet of.0

55 UTeK OMPUTER IN Title : None Engineer: ajun_ho ustom Fc,, 00 ate: heet of.0

56 Z_LK_OE 0 PF/V c00 EPOP# R 0KOhm R0 R PF/0V.KOhm.KOhm INTMI_P MI_JK L0 _PKR 0 0 NW 0.UF/V c00 R0 KOhm 0 0.UF/V c00 P_EEP R0 KOhm _UIO R L0 Ver EPOP# _UIO 0 UF/V c00_h +.V R0.KOhm For T00 INTMI_P +V_OE RER_L RER_R R 0KOhm PIF_J LINE_J R0.KOhm R0 0 0.UF/V RER_L_.KOhm R RER_L_R 0.UF/V R0 RER_R_ R RER_R_R 0.UF/V 0 0.UF/V R0.KOhm R R 0KOhm 0KOhm OE0 R0 _UIO 0 0 UF/V 0.UF/V c00_h c00 _UIO _UIO +V_UIO +V L0 /00Mhz 0.UF/V 0.UF/V UF/V c00 c00 c00_h T00 R 0KOhm % _UIO ERPHONE_L ERPHONE_R, _UIO /PIFO +V_UIO _UIO 0 N V URR-L(PORT--L) JREF URR-R(PORT--R) V ENTER(PORT--L) LFE(PORT--R) N N EP PIFO LINE-R(PORT--R) LINE-L(PORT--L) MI-R(PORT--R) MI-L(PORT--L) -R 0 - -L MI-R(PORT-F-R) MI-L(PORT-F-L) LINE-R(PORT-E-R) LINE-L(PORT-E-L) ense T00 0 UF/V INTMI_P INTMI_P UF/V MI_R UF/V 0V/XR 00 MI_L UF/V 0V/XR 00 MI_JK _R UF/V 0V/XR 00 UF/V 0V/XR 00 _L UF/V 0 UF/0V INTMI_P 0V/XR 00 UF/0V ERPHONE_R_0 ERPHONE_R_0 ERPHONE_L_0 ERPHONE_L_0 L0 MI_JK _R _L_ 0PF/0V Z_OUT_OE Z_LK_OE +V_OE L0 Ver EPOP# L0-V-R R EXTMI_J LINE_J R 0KOhm R.KOhm R.KOhm _ense#, Z_IN0 Z_YN_OE, Z_RT#_OE R Ohm 000PF/0V P_EEP _UIO Vout=.*(+(00K/K)) +V UF/V c00 0.UF/V U0 MX HN# OUT IN ET MXTEUK +V_UIO L0 000PF/0V 0/00Mhz c00 R 00KOhm R0 0 KOhm UF/V 0.UF/V 0.UF/V 0.UF/V % c00 c00 c00 _UIO _UIO _UIO INTMI_N VREF_OE 0UF/.V 0.UF/V c00_h_rd c00 _UIO _UIO L0 /00Mhz _JK R R R R R R _UIO Engineer: ajun_ho UTeK OMPUTER IN. N ustom Fc Title : OE-L0,, 00 ate: heet of.0

57 ->- V/V 0->NORML XR To Internal peaker onnector HP_J Earphones Jack In : Low PIF Jack In or N : High Microphone In Jack EXTERNL MI HP_J H /PIF _OUT TYPE L L JK_W# H N LINE_OUT L H XR XR R R R R ustom,, 00 UTeK OMPUTER IN. N UIO MP & JK.0 Fc ajun_ho ate: heet of Title : Engineer: INTPKR+_ON LY_MP_HOWN# INTPKR+ INTPKL-_ON ER_POP_EN# ER_POP_EN# INTPKR- INTPKL- INTPKL+_ON INTPKL+ INTPKR-_ON LY_MP_HOWN# JK_W# HP_L_ON HP_R HP_R HP_L HP_L HP_R HP_R_ON HP_L JK_W# INTPKR- INTPKL- MP_IN0 MP_IN INTPKR+ INTPKL+ MP_IN0 HP_J MI_JK_ON HP_L HP_R MP_IN JK_W# HP_J _JK _UIO V_MP +V _UIO +V _UIO PV_MP +V PV_MP +V _JK _UIO _JK _JK _JK _JK _JK _UIO _UIO V_MP V_MP _UIO V_MP V_MP _UIO _UIO +V_PIF _UIO V_MP _UIO _UIO _UIO _UIO _JK _JK _JK _JK +V +V +V _UIO _UIO V_MP _UIO _UIO +V 0 TW R0 Ohm 0 000PF/0V 0 TW R 00KOhm r00 R R0 r00 Q0 N00K_T_E R 00KOhm r00 000PF/0V PKN0 WTO_ON_P_PK IE IE L0 L /00Mhz L L0 /00Mhz R 00KOhm r00 R0 MOhm r00_h Q0 N00K_T_E R 00KOhm r00 Q0 N00K_T_E L0 /00Mhz R 0.UF/V c PF/0V L0 /00Mhz 0 000PF/0V 000PF/0V V Vin M HPN0 PHONE_JK_P 0 R 00KOhm R E0 00UF/.V E0 0UF/V 000PF/0V c00 R 0KOhm r UF/V 0 00PF/0V 000PF/0V c00 Q0 N00K_T_E L0 E0 0UF/V 0.UF/V c00 R0 0KOhm r UF/V L /00Mhz R0 Ohm L0 E0 00UF/.V R0 0KOhm L0 /00Mhz R 0KOhm r00 Q N00K_T_E R R0 0KOhm 0.UF/V 00PF/0V 0 UF/V c UF/V OPMP0 TP0PWP 0 0 IN0 IN LOUT+ LIN- PV RIN+ LOUT- LIN+ YP N ROUT- PV V RIN- ROUT+ HUTOWN# L0 /00Mhz L0 Q0 N00K_T_E Q UMN 0.UF/V c PF/0V Q N00K_T_E R0 Q0 N00K_T_E R KOhm Q0 N00K_T_E R L UIO JK EXTMIN0 PHONE_JK_P 0 R 00KOhm % L0 /00Mhz R0 0KOhm r00 UF/V R r00 0 UF/V c00 Q N00K_T_E Q0 N00K_T_E Q N00K_T_E 0 T ERPHONE_L_0 ERPHONE_R_0 EPOP# OP_# ERPHONE_R Z_RT#_OE, ERPHONE_L RER_L EXTMI_J MI_JK RER_R /PIFO, JK_W# PIF_J LINE_J

58 +V +V LVPW_T LVPW_T V V, U_E# U_ON_E# U0 U0 0 +V +V PT LVPW_T LVPW_T R0 V V,,, U_E# U_ON_E# 0 U0 U0 0.0UF/V UTeK OMPUTER IN Title equence : ontrol Logic Engineer: ajun_ho ustom Fc,, 00 ate: heet of.0

59 PF/0V X0.Khz E_XIN E_XOUT PF/0V +V_E 0 UF/0V 0 0.UF/V 0 0.UF/V +V 0 0.UF/V +VPLL R0 +V_E 0 0.UF/V 0 UF/0V R0 +V 0 0.UF/V 0 RNV 0.UF/.V 0.UF/V 0 +V_E +VPLL +V +V 0 PM_RMRT#.PF/0V t=0. * 0^ * (sec) =. ms PM TTE# RN0 00KOhm U# RN0 00KOhm T U# RN0 00KOhm PM_LP_M# RN0 00KOhm E0 RN0,,0, LP_0 Ohm L0 MLK0/P M0_LK RN0 attery,,0, LP_ Ohm L MT0/P M0_T RN0,,0, LP_ Ohm RN0 L MLK/P M_LK,,,,0, LP_ Ohm 0 0 L MT/P M_T,, Thermal +V +V_E LK_KPI LPLK TPT T ensor,,0, LP_FRME# LFRME# 0/PK0 +V,,,,,,,,, UF_PLT_RT# 0 LPRT#/WUI/P /PK V_OVERT# 0 TPT T,, INT_ERIRQ ERIRQ /PK TPT T RN0 M_T, EXT_MI# EMI#/PM0 /PK.KOhm RN0 M_LK RIN# EI#/P /PK.KOhm R0 0KOhm EXT_I# M0_T RN0 0TE.KOhm R0 0KOhm 0TE 0/P /PK M0_LK RN0 RIN#.KOhm E_RT# KRT#/P TPT T0 T0 WRT# 0/PJ0 TPT 00 TPT PWUREQ#/PM /PJ T +VU /PJ 0 L_ 0 0 TEL_P# T FR# FR# /PJ TPT PM_PWRTN# R 0KOhm FWR# FWR# F# F# PWM0/P0 F0 F0 PWM/P FN_PWM TPT T0 +V F F PWM/P 0 TPT T0 +V_E F F PWM/P TP_LK.KOhm R F F PWM/P H_LE_UP# _PR_U# R 0KOhm TP_T.KOhm R F F PWM/P PWR_LE_UP# 0 TEL_# INTNT_ON# R 0KOhm EXT_I# 0KOhm R0 F F PWM/P TEL_# U_PWR R0 0KOhm T# 0KOhm R0 F F PWM/P L_KOFF# J_W# R 0KOhm V_OVERT# 0KOhm R F F F0 F0 RX/P0 NUM_LE F F TX/P P_LE F/ R0 F/R0 P RL_LE If you don't use udio J F/ R F/R RIN#/PWRFIL#/LPRT#/P THRO_PU function, please use this F/ PPEN F/PPEN J_W# F/ HM F/HM LKOUT/P0 schematics PWRLIMIT# TPT T F F P +V_E F F TMRI0/WUI/P _IN_O# 0,,0 F F P OP_# F F TMRI/WUI/P T_IN_O# 0 TPT LI_W# U_E# F0 KKOUT/P T RN0 0KOhm R.KOhm F0 _ON# RN0 U_E# R.KOhm F F 0KOhm 0 T_IN_O# RN0 F F RI#/WUI0/P0 U#, 0KOhm _IN_O# RN0 F F RI#/WUI/P U# 0KOhm F F P RFON_W#, 0 PPE#_E 0KOhm R F F INT/P PM_LP_M# F F/P0 TH0/P FN0_TH F F/P TH/P OLOREN# F 0 F/P 0 T# V/_ON# R 0KOhm F F/P /PE0 TV_ON# R 0KOhm /PE INTERNET# 0 KI0 KI0/T# /PE MRTHON# 0 KI KI/F# /PE 0 ITP# PWRLIMIT# KOhm R 0 KI KI/INIT# PWRW/PE PWR_W# TPT T0 +V 0 KI KI/LIN# WUI/PE 0 KI KI LPP#/WUI/PE 0 KI KI LKRUN#/WUI/PE PM_LKRUN#,, LOT_ON 00KOhm R OLOREN# RN0 0 KI KI 0KOhm 0 ITP# RN0 0 KI KI PLK/PF TP_LK 0 0KOhm MRTHON# RN0 0 KO0 KO0/P0 PT/PF LOT_ON TP_T 0 0KOhm 0 TPT T0 INTERNET# KO/P PLK/PF RN0 0 KO 0KOhm 0 KO KO/P PT/PF INTNT_ON# 0 KO KO/P 0 KO KO/P F0/P LI_W# KO/P F/P TPT T 0 KO PM_THERM# 0 KO KO/P LP0HL/P _PR_U# 0 KO KO/P LP0LL/P 0 KO KO/K# 0 KO 0 KO/UY PH0 VU_ON,,,, 0 KO0 KO0/PE PH U_PWR, 0 KO KO/ERR# PH VRM_PWR 0, 0 KO KO/LT PH PM_PWRTN# 0 KO KO PH 0 U_E#, 0 KO KO PH 0 KO KO PH PU_VRON 0 0 E_XIN PH PM_RMRT# 0 E_XOUT KK 0 KKE PI0 PM_PWROK,,,0 R0 PM_THERM# _PR_U# PI LL_YTEM_PWR PMTHERM# 0 TPT T Q0 PLK0/PF0 T TPT PI UMKN T TPT V/_ON# PT0/PF PI H_EN# T TPT TV_ON# PLK/PF PI PREH R0 T PT/PF PI E_LK_EN _PR_U PI T_LERN O#_O,,, FORE_OFF# R r00 N U0 OUT V E_RT# +V_E E_RT# +V JP0 MM_OPEN_MIL +V_E ITTE Q0 T0 TPT T TPT R0 r00 PPE#_E PPE# P_HN# _ON# T TPT R0 E_ U_E#,,, UMKN UTeK OMPUTER IN. N Title : ITTE Engineer: ajun_ho R r00 PM TTE# ustom Fc,, 00 ate: heet of.0

60 For Touch-Pad For Keyboard(Pin) Non KI KN0 +V +V_TP L00 /00Mhz 00 0.UF/V TP_T TP_LK LFET RIHT +V_TP TPN0 IE 0 0 IE FP_ON_P IE 0 0 IE 0 0 KO KO KO KO KO KI KI KI KI KI KI KI0 KI KO KO0 KO KO KO KO KO KO KO KO0 KO KO KO KO KO KO KI KI KI KI KI KI KI0 KI KO KO0 KO KO KO KO KO KO KO KO0 KO FP_ON_P LFET RIHT W00 TP_WITH_P W00 TP_WITH_P UTeK OMPUTER IN. N Title : Touch Pad & K Engineer: ajun_ho ustom Fc,, 00 ate: heet of 0.0

61 UTeK OMPUTER IN Title : chematic page name Engineer: ajun_ho ustom Fc,, 00 ate: heet of.0

62 U_PN R0 U_P- +V F0./V +V_Fuse L0 R0.KOhm /00Mhz +V_U_ON U_PP R0 U_P+ +V_U_ON + E0 UF/.V 0 0.UF/0V U_P- U_P+ UN0 IE_ V IE_ T0- T0+ IE_ IE_ U_ON_XP U_ON_O# R0.KOhm U_P- U_P+ 0 E00V0 0 E00V0 +V F0 +V_Fuse L0 /00Mhz +V_U_ON U_PP0 R0 U_P0+./V R0.KOhm U_PN0 R0 U_P0-0 U_ON_O0# R0.KOhm +V_U_ON +V_U_ON U_P0+ U_P0-0 UUN0 0P+ 0P- V IP0Z + E0 UF/.V U_P+ U_P- 0 0.UF/0V P+ P- V U_ON_XP U_PN R0 U_P- U_PP R0 U_P+ + E0 UF/.V 0 0.UF/0V UTeK OMPUTER IN ustom Fc Title : U ONN Engineer: ajun_ho,, 00 ate: heet of.0

63 UTeK OMPUTER IN Title : chematic page name Engineer: ajun_ho ustom Fc,, 00 ate: heet of.0

64 I ROM E Hardware trapping F/ R0 & F/ R F/ PPEN 00: PNPN ccess Register Pair re 00Eh and 00Fh 0: Normal 0: PNPN ccess Register Pair re 00Eh and 00Fh : K Interface Pins re witched to Parallel Port 0: PNPN ccess Register Pair re etermined by Interface for In-ystem Programming +V_E E omain Registers WLR and WHR. R0 : Reserved r00 F/ PPEN 0KOhm +V_E R0 0KOhm R0 r00 F/ R0 0KOhm R0 F/ HM 0KOhm F/ R 0: isable hared Memory with Host IO R0 R0 : Enable hared Memory with Host IO 0KOhm 0KOhm +V_E R0 F/ HM r00 0KOhm Note: ampled at VTY Power Up Reset R0 0KOhm F F/ R0 F/ R F/ PPEN F/ HM F F F F F0 F F F F F F F F F M TOP U0 F F0 F/ R0 0 Q0 F0 F F/ R Q F F F/ PPEN Q F F F/ HM Q F F F Q F 0 0 F F Q F F F Q F F F Q F 0 F0 Q F Q F 0 Q0 F Q F Q F Q F Q F0 F Q/- F0 F F# E# F# FR# OE# FR# FWR# WE# FWR# N0 REET# E_RT# 0 N RY/Y# YTE# +V_E N YTE# N Vss R0 Vcc Vss 0KOhm 0 MXLV00TT 0.UF/V UTeK OMPUTER IN. N Title : Engineer: I ROM ajun_ho ustom Fc,, 00 ate: heet of.0

65 UTeK OMPUTER IN. N Title : Engineer: PI ROM ajun_ho ustom Fc,, 00 ate: heet of.0

66 For LE for Num Lock For POWER LE +VU LE0 R0 + PWR_LE# REEN For TTERY LE +VO LE0 R0 + ORNE H_LE# For T LE +V LE0 R0 + T_LEON# +V R0 LE0 + NUM_LE# REEN NUM_LE# PWR_LE_UP# +VU PWR_LE# R0.KOhm Q0 N00K_T_E Q0 N00K_T_E R +VU H_LE_UP# H_LE# Q0.KOhm N00K_T_E Q0 N00K_T_E TLE_ON.KOHM.KOHM RN0 RN0 REEN Q N00K_T_E T_LEON# Q0 NUM_LE N00K_T_E for croll Lock +V LE0 R0 + RL_LE# REEN RL_LE# For T/IE LE +V LE0 R0 + H_LE# REEN +V For WireLess LE LE0 R0 + REEN WLNLE_EN# RL_LE Q0 N00K_T_E +V for ap. Lock T_LE# IE_LE# ET_LE# +V 0 +V.KOHM.KOHM 0 TW NW RN0 RN0 Q0 N00K_T_E Q0 N00K_T_E H_LE# WLN_LE_ON, IM_LE# WLNLE_EN# R0.KOhm Q0 0 N00K_T_E NW Q N00K_T_E R R.KOhm 00KOhm +V LE0 R0 + REEN Q0 P_LE N00K_T_E P_LE# P_LE# UTeK OMPUTER IN Title : LE Engineer: ajun_ho ustom Fc,, 00 ate: heet of.0

67 UTeK OMPUTER IN Title : chematic page name Engineer: ajun_ho ustom Fc,, 00 ate: heet of.0

68 IN _JK_IN TPT T0 TPT T0 TPT T0 TPT T0 J0 P_ P_ NP_N _PWR_JK_P L0 /00Mhz L0 /00Mhz 0 0.UF/V 0 00 R UF/V /_OK_IN 0 0 UF/V 0.UF/V TPT T0 TPT T0 TPT T0 TPT T0 T IN T_ON J0 P_ P_ 0 TPT T0 TPT T0 TPT T TPT T UF/V 00PF/0V 0 00PF/0V TPT TPT TPT L0 L0 L0 0 0.UF/V T T T /00Mhz /00Mhz /00Mhz M0_LK M0_T T#,0 TT_ON_P TPT T TPT T TPT T TPT T M0_LK M0_T Without attery & Pull out dapter _T_Y 0 K 0 K R0 00KOhm When _T_Y<V ctive 000PF/0V R0.KOhm U0 N V U VOUT PT0NR FORE_OFF#,,, UTeK OMPUTER IN. N Title : Engineer: & T IN ajun_ho ustom Fc,, 00 ate: heet of.0

69 UTeK OMPUTER IN Title : chematic page name Engineer: ajun_ho ustom Fc,, 00 ate: heet of.0

70 For ebug If support Neward ebug ard, Pls don't mount all components. +V,,, LP_0,,, LP_,,, LP_,,, LP_,,, LP_FRME# LK_PI ON00 IE 0 0 IE 00 0PF/0V FP_ON_P ottom ontact LP_FRME# R00 0 LP_ LP_ LP_ LP_0 RN00 0 RN00 0 RN00 0 RN00 0 UTeK OMPUTER IN Title : ebug ONN. Engineer: ajun_ho ustom Fc,, 00 ate: heet of 0.0

71 UTeK OMPUTER IN Title : chematic page name Engineer: ajun_ho ustom Fc,, 00 ate: heet of.0

72 HN0 NP_N NP_N T_RXN0_ 0 000PF/0V T_RXP0_ 0 000PF/0V T_TXP0 T_TXN0 T_RXN0 T_RXP NP_N 0 NP_N T_ON_P TPT T0 0 0.UF/V 0 0.UF/V 0 0UF/0V + E0 UF/.V +V +V T H O,,,,,,,,, UF_PLT_RT# IE_P[:0] IE_P0 IE_P IE_P IE_P IE_P IE_P IE_P IE_P IE_P IE_P IE_P0 IE_P IE_P IE_P IE_P IE_P +V IE_P# IE_P R0 R0 0KOhm Ohm IE_PK# IE_PIOR# +V +V IE_PREQ +V R0 R0 0KOhm 0KOhm r00 r00 R0 IERT# 0KOhm r00 _R_ Q0 UMKN 0 Q0 UMKN NW IE_P# IE_I IE_PK# IE_PIOR# IE_PREQ IE_P IE_P IE_P IE_P IE_P IE_P0 IE_P IE_P V PON0 to_on_0p _EL IE_PP# IE_P0 IE_P INT_IRQ IE_PIORY IE_PIOW# IE_P0 IE_P IE_P IE_P IE_P IE_P IE_P IE_P IERT# L_ IE_PP# IE_P# IE_P0 IE_P INT_IRQ IE_PIORY IE_PIOW# 0 0.UF/V c00 R0 0 0UF/0V c00 +V R0.KOhm +V R0 R0 IE_LE# Normal type High: lave Low : Master _EL UTeK OMPUTER IN. N Title : T-H & O Engineer: ajun_ho ustom Fc,, 00 ate: heet of.0

73 VV 0m R0 R0 0 0UF/0V +V VV Place near pin,, R0 VV UF/0V 0.UF/0V 0.UF/0V 0.UF/0V R0 R0 U0 JM0_LZ0 R0 ET_LE# V.V VV ET_MLK ET_MT R0 PI_RT#_eT, PI_RT# 0 0UF/0V VV VV R R.KOhm.KOhm ET_MLK ET_MT 0 ZPIO _ XTET YHLEn V _ V_ XMLK ZMT XRTn _ ET_TXP TPT TXP T0 ET_TXN TPT T0 TXN Place near the V.V V PIN ET_RXN TPT T0 RXN 0 ET_RXP TPT T0 RE K OHM /W (00) % RXP REXT R0 REXT KOhm VV V ET_XOUT XOUT ET_XIN XIN N R0 0MOhm X0 0 Mhz 0UF/0V EER/0000 PF/V PF/V 0UF/0V c00 c00 PIE_RXP_eT_ 0.UF/0V PIE_RXP_eT PIE_RXN_eT_ 0.UF/0V PIE_RXN_eT +.V R0 r00_h 0 0.UF/0V.m PV Place near pin PV 0 0.UF/0V 0 000PF/0V 0.m V.V Place near pin,, V.V 0UF/0V 0.UF/0V 0.UF/0V 0.UF/0V R.0 without ET LK_PIE_eT# LK_PIE_eT 0 0UF/0V PREXT 0UF/0V R KOhm RE K OHM /W (00) % Place near the PIN PIE_TXN_eT PIE_TXP_eT.m V.V Place near pin, V.V 0UF/0V 0.UF/0V 0.UF/0V +V F0./V L0 R.KOhm /00Mhz +V_U_ON U_PN U_PP R R U_P+ +V_U_ON U_P- ON0 IE_ V IE_ T0- T0+ IE_ IE_ U_ON_XP, U_ON_O# R.KOhm U_P- U_P+ 0 E00V0 0 E00V0 + E0 UF/.V 0.UF/0V UTeK OMPUTER IN. N Title : et & U Engineer: ajun_ho ustom Fc,, 00 ate: heet of.0

74 FOR V FOR PU FOR REW HOLE FOR LEFT UNER FOR RIHT UP FOR FN ustom,, 00 UTeK OMPUTER IN REW HOLE.0 Fc ajun_ho ate: heet of Title : Engineer: H I H0 N NP_N H0 T H0 N NP_N H I H T H0 N NP_N H0 N NP_N H0 TRXN NP_N H0 N NP_N H0 N NP_N H I H N NP_N H0 TN NP_N H0 N NP_N H N H N NP_N H N NP_N H0 RILL_N_N NP_N NP_N H T H RILL_N_N_R NP_N NP_N H N

T53S Main BD. R1.2 Block Diagram

T53S Main BD. R1.2 Block Diagram T Main. R. lock iagram LV PE Merom PU LV / ULV PE, F F 00/ MHz LOK EN. ILPRLF-T PE FN Thermal sensor PE 0 RT HMI PE PE M Nvidia NP- M PE 0,,,,,, PE udio L PE,, 0 F PI-E X zalia LP restline PM PE 0,,,,,

More information

VF-co-cc. F3Jr CPU CLOCK GEN. ATI M64-M or M76-M NORTH DDR2 SO-DIMM0 BRIDGE DDR2 SO-DIMM1 TPM 1.2 INFINEON SLB9635 SOUTH BRIDGE EC ITE IT8510E

VF-co-cc. F3Jr CPU CLOCK GEN. ATI M64-M or M76-M NORTH DDR2 SO-DIMM0 BRIDGE DDR2 SO-DIMM1 TPM 1.2 INFINEON SLB9635 SOUTH BRIDGE EC ITE IT8510E 0 0 0 0 0 0 0 lock iagram ystem etting * PU-YONH(HOT) PU-YONH(PWR) * N-PM(HOT) * U ONN * I ROM * LE * R Mx x Option PU YONH MEROM W W LOK EN I 0 FJr 0 0 0 N-PM(MI & F) N-PM(RPHI) N-PM(R) N-PM(PWR) 0 &

More information

F8V L80V N80V N81 Montevina Block Diagram

F8V L80V N80V N81 Montevina Block Diagram FV L0V N0V N Montevina lock iagram _IN & T ON PE 0 Penryn W & LE PE HMI RT PE PE LV & INV PE INTERNL KEYOR TOUH P PE IR IO PI ROM MI IN HP&PIF OUT OPMP PE Internal MI ON PE PE PE 0 V aughter PE FVa: M

More information

E chematic Index Page ystem page Ref. 0 lock iagram 0 chematic Information 0-0 PU-Penryn 0-09 R II O-IMM 0- antiga 0- IH9M PI ROM 9 LK-I9LPRLF-T 0- E_

E chematic Index Page ystem page Ref. 0 lock iagram 0 chematic Information 0-0 PU-Penryn 0-09 R II O-IMM 0- antiga 0- IH9M PI ROM 9 LK-I9LPRLF-T 0- E_ : PENRYN/NTI/IH9-M/N9M- LOK IRM mall-oard ub-oard R VRM*(MX) RT MI PREMP & INT MI LZI M UIO OR L0 PE mall-oard LV HMI TouchPad PE IO PI ROM PE INTERNL KEYOR PE PE PE PE UIO_MP & INT PK PE PE PE PE nvii

More information

Z96S CPU MEROM 34W P.3~5. DDR2 16Mx16 x4 CLOCK GEN ICS 9LPR364BGLF-T P.25. DDR2 16Mx16 x4 NORTH. nvidia DDR2 SO-DIMM0 BRIDGE

Z96S CPU MEROM 34W P.3~5. DDR2 16Mx16 x4 CLOCK GEN ICS 9LPR364BGLF-T P.25. DDR2 16Mx16 x4 NORTH. nvidia DDR2 SO-DIMM0 BRIDGE 0_lock iagram 0_ystem etting 0_Merom PU () 0_Merom PU () 0_PU P. 0_PM--PU () 0_PM--R/PE () 0_PM--R U () 0_PM--PWER () 0_PM--PWER () _PM--/TRPPIN () _IHM() _IHM() _IHM() _IHM--PEW/ () _R -IMM0 _R -IMM _R

More information

F7F CPU CLOCK GEN ICS NORTH DDR2 SO-DIMM0 BRIDGE DDR2 SO-DIMM1 SOUTH BRIDGE TPM 1.2 INFINEON SLB9635 AZALIA CODEC EC ITE IT8510E MDC NEWCARD

F7F CPU CLOCK GEN ICS NORTH DDR2 SO-DIMM0 BRIDGE DDR2 SO-DIMM1 SOUTH BRIDGE TPM 1.2 INFINEON SLB9635 AZALIA CODEC EC ITE IT8510E MDC NEWCARD 0_lock iagram 0_ystem etting 0_PU-YONH(HOT) 0_PU-YONH(PWR) 0_N-M(HOT) 0_N-M(MI & F) 0_N-M(RPHI) 0_N-M(R) _N-M(PWR) _N-M(PWR) _N-M() _-IHM() _-IHM() _-IHM() _-IHM(PWR) 0_R O-IMM0 _R O-IMM _R TERMINTION

More information

PART for BOM only 02G GPU NB8M

PART for BOM only 02G GPU NB8M RT_TY P PRT for OM only Function U Partnumber RT TY 000 LOTION Temp Modify 0: elete E,,,, already have in location elete E, No space to add elete,,0,,,,,,, No space to add TT PU NM 00000 Title Revision

More information

L53II0 M/B and Daughter P/N LIST:

L53II0 M/B and Daughter P/N LIST: Model : LII0 P P/N:L00- P P/N:L00- Intel Merom PU + M + IH-M hipset LII0 M/ and aughter P/N LIT: LII0 M/ ffiliated FF/able P/N LIT: P0 INEX P0 YTEM LOK IRM P0 POWER IRM & EQUENE P0 PIO & POWER ONUMPTION

More information

W7J: YONAH/CALISTOGA-PM/G72M BLOCK DIAGRAM

W7J: YONAH/CALISTOGA-PM/G72M BLOCK DIAGRAM WJ: YONH/LITO-PM/M LOK IRM PE LOK EN. I0 PE 0 MI PREMP & INT MI PE 0, PE PE PE R VRM* F TV OUT ZLI M PE LV RT ZLI L0 UIO_MP & INT PK PE PE PE nvii M PE,,,0,, PIF JK zalia PIE LP T PE,, PE,,,,0,, Yonah

More information

R&D Division. Board name : Mother Board Schematic Project : Z11D (Santa Rosa) Version : 0.4 Initial Date : March 02, Inventec Corporation

R&D Division. Board name : Mother Board Schematic Project : Z11D (Santa Rosa) Version : 0.4 Initial Date : March 02, Inventec Corporation Inventec orporation R& ivision oard name : Mother oard chematic Project : Z (anta Rosa) Version : 0. Initial ate : March 0, 00 Inventec orporation F, No., ection, Zhongyang outh Road eitou istrict, Taipei

More information

F80Q SCHEMATIC Revision 2.00

F80Q SCHEMATIC Revision 2.00 F0Q HMTI Revision.00 P 0 0 0 0 ontent YTM P RF. PU-Penryn() PU-Penryn() PU P, Thermal enor LOK N._ILPRLF N_-0L ()--PU N_-0L ()--R/P N_-0L ()--R bus N_-0L ()--POWR N_-0L ()--POWR N_-0L ()--/trapping R O-IMM_0

More information

Project Name :I36IAx Platform : Celeron GS40 + Park + ICH9M

Project Name :I36IAx Platform : Celeron GS40 + Park + ICH9M Project Name :IIx Platform : eleron + 0 + Park + IHM PE..... PU... 0_FF. 0...... -IHM.... 0.......... 0....... POWER... 0. ONTENT INEX YTEM LOK IRM POWER IRM & EQUENE Power on equence iagram PU Penryn

More information

A8S NVIDIA_NB8X VGA Board SCHEMATIC

A8S NVIDIA_NB8X VGA Board SCHEMATIC PE ontent YTEM PE REF. NVII_NX V oard HEMTI Thermal block diagram MXM N 06'0/ 0 ontent 0 MXM connector 0 PI-E Interface E FN M_LK M_T M_LK_V R M_T_V _LK_MXM _T_MXM R R V_THERM_LERT# R slave Mus Ext Thermal

More information

Extreme/Meron 2M/4M SV FSB:667 or 800 MHz 4~7. Host BUS 667/800MHz. PCIe x16 8~14. DMI I/F 100MHz. USB 2.0 USB x 427 SATA PATA PCI/PCI BRIDGE 22~25

Extreme/Meron 2M/4M SV FSB:667 or 800 MHz 4~7. Host BUS 667/800MHz. PCIe x16 8~14. DMI I/F 100MHz. USB 2.0 USB x 427 SATA PATA PCI/PCI BRIDGE 22~25 LT- lock iagram YTEM / TP0 INPUT OUTPUT 0 /MM M/M Pro/x 0 RJ ONN EXT MI LK EN ILPR Thermal ensor/ Fan control MT RII / RII / lot lot Ricoh R ardreader OROM M0/M 0/00M/000M TLE RJ ML0 ONN RELTEK H UIO OE

More information

ACER_BAP31 MAIN BOARD INVENTEC ACER_JM31 CODE EE DATE POWER DATE DRAWER DESIGN CHECK RESPONSIBLE TITLE

ACER_BAP31 MAIN BOARD INVENTEC ACER_JM31 CODE EE DATE POWER DATE DRAWER DESIGN CHECK RESPONSIBLE TITLE ER_P MIN OR 00.. Tuesday, March 0, 00 TE HNE NO. X0 REV EE TE POWER TE RWER EIN HEK REPONILE IZE= VER: FILE NME: XXXX-XXXXXX-XX P/N XXXXXXXXXXXX INVENTE ER_JM OE IZE O.NUMER REV --00-L X0 X0 HEET . chematic

More information

C45/C46 Block Diagram

C45/C46 Block Diagram / lock iagram LK EN I LPR.00.00W Mobile PU Merom /., Project code:.u0.00 Project code:.v00.00 P Number : 0 Revision : - YTEM / TP0 INPUT TOUT OUTPUT V_() V_() YTEM / INPUT TOUT OUTPUT 0V_0(.) V_(.) R /

More information

T76S: MEROM/965-PM/ICH8-M/NB8M-SE BLOCK DIAGRAM

T76S: MEROM/965-PM/ICH8-M/NB8M-SE BLOCK DIAGRAM TS: MEROM/-PM/IH-M/NM-SE LOK IRM LOK EN. ISLPRLF-T R VRM*(X) Merom PE ufp FN Thermal sensor F PE PE,, PE FS 00 MHz LVS nvii NM-SE PE RT PE POWER RESTLINE PM PIE * PE ~ R-II SO-IMM R MHz VORE PE 0 SYSTEM

More information

G60J Schematics for Calpella Platform Rev. 1.5

G60J Schematics for Calpella Platform Rev. 1.5 YTEM PE REF. 0. lock iagram 0. ystem etting 0. PU()_MI,PE,FI,LK,MI 0. PU()_R 0. PU()_F,RV,N 0. PU()_PWR 0. PU()_XP. R()_O-IMM0. R()_O-IMM. R()_/Q Voltage. VI ontroller 0. PH()_T,IH,RT,LP. PH()_PIE,LK,M,PE.

More information

G HDMI 4, 5. DVI ATI M76-M PCI-EG. Page.44~50 LAN 10/100/1000 PCI-E6. INTEL 82566MM Page.23,24 PCI-E3 PCI-E4 /USB 2.

G HDMI 4, 5. DVI ATI M76-M PCI-EG. Page.44~50 LAN 10/100/1000 PCI-E6. INTEL 82566MM Page.23,24 PCI-E3 PCI-E4 /USB 2. R lock iagram LK EN. / MHz R MI In x I LPR / MHz odec L /MHz ZLI OP MP Q INT.PKR x OK E R PI-E PI-Express U.0 PORT/PORT Repeater/ PIEQX0 ock Port x Jack In x RJ- Ethernet Port x HMI x RT x U.0 x udio In

More information

Z62Ha CPU. Card Reader TPM 1.2 GIGA LAN NEWCARD DDR2 SO-DIMM1 DDR2 SO-DIMM2 AZALIA CODEC CLOCK GEN MDC CONN. DDR2 32MX16M X4. Touch Pad.

Z62Ha CPU. Card Reader TPM 1.2 GIGA LAN NEWCARD DDR2 SO-DIMM1 DDR2 SO-DIMM2 AZALIA CODEC CLOCK GEN MDC CONN. DDR2 32MX16M X4. Touch Pad. lock iagram R MXM X L RT Internal K Touch Pad ynaptics TI PU M- ebug onnector TPM. INFINEON L PU MEROM ocket-p NORTH RIE I OUTH RIE R single hannel- R single hannel- MUTIOL MHz ITP ONN. LOK EN I LPR00

More information

M630/M640 Main Board.

M630/M640 Main Board. chematics Page Index ( / Revision / hange ate) Page of chematics Page Rev. ate Page 0 chematics Page Index 0 lock iagram 0 Merom(HOT U) / 0 Merom(HOT U) / 0 Merom(Power/nd) / 0 0 LOK N 0 restline (HOT)

More information

FOXCONN Title. Schematics Page Index (Title / Revision / Change Date) Project Code & Schematics Subject:

FOXCONN Title. Schematics Page Index (Title / Revision / Change Date)   Project Code & Schematics Subject: Page of chematics Page 0 chematics Page Index 0 lock iagram 0 Penryn(HOT U) / 0 Penryn(HOT U) / 0 Penryn (Power/nd) / 0 LOK N 0 antiga (HOT) / 0 antiga (MI) / 0 antiga (RPHI) / 0 antiga (RII) / antiga

More information

U35JC SCHEMATIC Revision 1.0

U35JC SCHEMATIC Revision 1.0 YTEM PE REF. PE ontent lock iagram ystem etting PU()_MI,PE,FI,LK,MI PU()_R PU()_F,RV, PU()_PWR PU()_XP R O-IMM_0 R O-IMM_ R _Q VOLTE 0 PH_IEX()T,IH,RT,LP PH_IEX()_PIE,LK,M,PE PH_IEX()_FI,MI,Y PWR PH_IEX()_P,LV,RT

More information

ME3 Block Diagram HDD G792 ICH8-M. Project code : 91.4X PCB P/N : Revision : PCB LAYER LPC DEBUG CONN. TPM SLB9635TT KBC. Intel CPU.

ME3 Block Diagram HDD G792 ICH8-M. Project code : 91.4X PCB P/N : Revision : PCB LAYER LPC DEBUG CONN. TPM SLB9635TT KBC. Intel CPU. M lock iagram RII lot 0 RII lot Power witch RJ ONN Line In INT.PKR Line Out (PIF) RJ INT. MI rray igital HMI (PIF),, Mini ard_ Robson Mic In -T ONN RII hannel RII hannel MP MP MOM -T IL 0/00 ontroller

More information

Alba Discrete ATI M92-LP gddr2 Schematics ufcpga Mobile Penryn Intel Cantiga-PM + ICH9M REV : SA

Alba Discrete ATI M92-LP gddr2 Schematics ufcpga Mobile Penryn Intel Cantiga-PM + ICH9M REV : SA lba iscrete TI M-LP gr chematics ufp Mobile Penryn Intel antiga-pm + IHM 00-0- REV : : Nopop omponent M : Pop when antiga is M PM : Pop when antiga is PM /P : OM control if antiga is PM Wistron

More information

X51C Main BD. R1.0 BLOCK DIAGRAM

X51C Main BD. R1.0 BLOCK DIAGRAM X Main. R.0 LOK IRM Merom PU LOK EN. ILPRLF-T PE ufp FN + Thermal sensor PE, PE 0 PE LV i0elv F 00 MHz PE TV PE RT im TE R MHz R-II O-IMM X PE,, PE PE 0,,,,,, MI * PIE * Miniard WLN onn. PE New ard onn

More information

N61Jv SCHEMATIC Revision 2.0

N61Jv SCHEMATIC Revision 2.0 YTEM PE REF. PE ontent lock iagram ystem etting PU()_MI,PE,FI,LK,MI PU()_R PU()_F,RV, PU()_PWR PU()_XP R OIMM_0 R OIMM_ R _Q VOLTE VI controller 0 PH_IEX()T,IH,RT,LP PH_IEX()_PIE,LK,M,PE PH_IEX()_FI,MI,Y

More information

C90S C90S CLOCK GEN ICS9LPR363AGLF-T P.03 CPU THERMAL CONTROL. MXM Interface NORTH DDR2 SO-DIMM0 BRIDGE DDR2 SO-DIMM1 SOUTH BRIDGE EC ITE IT8511EP.

C90S C90S CLOCK GEN ICS9LPR363AGLF-T P.03 CPU THERMAL CONTROL. MXM Interface NORTH DDR2 SO-DIMM0 BRIDGE DDR2 SO-DIMM1 SOUTH BRIDGE EC ITE IT8511EP. 0 00_00_000 LOK iagram HITORY Power equence LKEN-ILPRLF-T N-_ N-_ N-_ N-_ N-_ 0 L- L- L- L- RII_-IMMs RII_-Termination MXM Interface MXM Power & N NIO_-LV & Inverter NIO_-RT 0 NIO_-VIEO NIO_-HMI onnector

More information

Thurman Discrete VGA nvidia G86 Schematics Document. ufcpga Mobile Merom Intel Crestline-PM + ICH8M REV : -1(DELL:A00)

Thurman Discrete VGA nvidia G86 Schematics Document. ufcpga Mobile Merom Intel Crestline-PM + ICH8M REV : -1(DELL:A00) Thurman iscrete V nvidia chematics ocument ufp Mobile Merom Intel restline-pm + IHM 00--0 REV : -(ELL:00) Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Thurman iscrete

More information

CPU T2060 4xx,5xx Series PAGE 2,3. FSB 533MHz. GMCH-M Calistoga 943GML B0:02G PAGE 6,7,8,9,10,11 DMI Interface PCIE *1 ICH7-M PCIE *1

CPU T2060 4xx,5xx Series PAGE 2,3. FSB 533MHz. GMCH-M Calistoga 943GML B0:02G PAGE 6,7,8,9,10,11 DMI Interface PCIE *1 ICH7-M PCIE *1 TERE lock iagram PE FN ENR M0RMZ PE, PU T00 xx,xx eries PE PE LK EN 0 HRER RUT F MHz Power n equence PE 0 TP PE PE LV & NV RT MH-M alistoga ML 0:00000 PE,,,,0, M nterface R-MHz ual hannel R PE,, -MM X

More information

A8Jp/Jv/Je/Jn/Fm SCHEMATIC

A8Jp/Jv/Je/Jn/Fm SCHEMATIC Jp/Jv/Je/Jn/Fm HMTI P 0 0 0 0 ontent YTM P RF. Merom PU () Merom PU () PU P/THRML NOR LOK N. alistoga--pu alistoga--pi alistoga--r alistoga--powr alistoga--n alistoga--trap R O-IMM_0 R O-IMM_ R R TRMINTION

More information

FOXCONN Title. Schematics Page Index (Title / Revision / Change Date) Rev M/B P/N:

FOXCONN Title. Schematics Page Index (Title / Revision / Change Date) Rev M/B P/N: Page 0 0 0 0 0 0 0 0 0 0 0 0 of chematics Page chematics Page Index lock iagram Merom(HOT U) / Merom(HOT U) / Merom(Power/nd) / LOK N restline (HOT) / restline (MI) / restline (RPHI) / restline (RII) /

More information

2007/7/15. DDR2 x 1. DDR2 x 1 SATA1. 4 x SATA150,300 ports SATA2 SATA3 SATA4 IDE X1. USB2.0 8 ports WIFI. BIOS Flash ROM (SPI)

2007/7/15. DDR2 x 1. DDR2 x 1 SATA1. 4 x SATA150,300 ports SATA2 SATA3 SATA4 IDE X1. USB2.0 8 ports WIFI. BIOS Flash ROM (SPI) PI-EX x lot ch udio PI-EX x lot LN THERO RELTEK L PI lot PI lot V PKPL-VM/I PI-EX x PI-EX x PI-EX x zalia V PI U MHz Intel L Pentium (90/nm).Hz PU Intel MH earlake (North ridge) F 00/0/MHz MI U Intel IH

More information

Beyonce UMA Schematics Document. ufcpga Mobile Merom Intel Crestline-GM + ICH8M REV : -2 (DELL:A00)

Beyonce UMA Schematics Document. ufcpga Mobile Merom Intel Crestline-GM + ICH8M REV : -2 (DELL:A00) eyonce UM chematics ocument ufp Mobile Merom Intel restline-m + IHM 00-0- REV : - (ELL:00) Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. eyonce UM ize ocument Number

More information

G D8V_S3 667/8000MHz WXGA/SXGA+ LVDS. New card G577 USB 2.0. ACPI in 1 TRL8101E 23 PCI-E / USB 2.0 LPC BUS KBC.

G D8V_S3 667/8000MHz WXGA/SXGA+ LVDS. New card G577 USB 2.0. ACPI in 1 TRL8101E 23 PCI-E / USB 2.0 LPC BUS KBC. E YTEM / Project code: TP P0 lock iagram YTEM / Mobile PU PWQI LK EN. ILPRYLFT-P RTMT-0-V-RT HOT U Penryn, /00/0MHz@.0V Line Out odec H udio PI-E/U.0 L IHM New card PIe ports MI In PI/PI RIE M/M Pro/ U.0

More information

SWITCH BD ASSY R40II1 REV:02 PCB SW BD R40IIx REV *11.50*1.2 6L +*V_AUX +*V +*V_LDO +*V_DDR OFF. AC/DC S4/Moff (Suspend to Disk) OFF OFF OFF

SWITCH BD ASSY R40II1 REV:02 PCB SW BD R40IIx REV *11.50*1.2 6L +*V_AUX +*V +*V_LDO +*V_DDR OFF. AC/DC S4/Moff (Suspend to Disk) OFF OFF OFF Intel Penryn PU + antiga + IHM hipset R0IIx M/ / 0 VER PE 0 0 LK IRM MIELLNEU 0 PI 0 0 PU Penryn of PU Penryn of 0 N antiga of 0 N antiga of 0 N antiga of 0 N antiga of N antiga of N antiga of LK ENERTR

More information

Thurman UM chematics ocument ufp Mobile Merom Intel restline-m + IHM 00-0- REV : (ELL:X0) Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Thurman UM ize ocument Number

More information

Pamirs UMA Block Diagram

Pamirs UMA Block Diagram RJ ONN /IO/MM M/M Pro/x LK N ILPRKLFT-P RII / lot 0 RII / Ricoh R ardreader 0/00 NI Marvell 0 lot, Pamirs UM lock iagram RII hannel R II hannel PI LI Intel PU Meron M/M V F: or 00 MHz,, Host U /MHz restline-m/ml

More information

Model : M30EI0. Mobile Dothan with INTEL 915GM / ICH6-M Chipset

Model : M30EI0. Mobile Dothan with INTEL 915GM / ICH6-M Chipset Revision History / ORIINL RELEE Model : MEI Mobile othan with INTEL M / IH-M hipset P INEX P YTEM LOK IRM P POWER IRM & EQUENE P PIO & POWER ONUMPTION P PU anias/othan-/ P PU anias/othan-/ P LOK EN I P

More information

CPU Yonah Single core Yonah Celeron Page 2. AGTL+ 133/166MHz DDR2 533/667 RC415ME. Page 5,6,7,8,9 PCIE X4 SB600. LPC 33MHz. Debug Conn.

CPU Yonah Single core Yonah Celeron Page 2. AGTL+ 133/166MHz DDR2 533/667 RC415ME. Page 5,6,7,8,9 PCIE X4 SB600. LPC 33MHz. Debug Conn. FR LOK IRM PU Yonah ingle core Yonah eleron Page TL+ MHz LV Page 0 RT Page PIE RME R ingle hannel UL R O-IMM Page,, Page,,,, PIE X MINIR Page 00 LN 000 TTNI L LP MHz ebug onn. Page NEWR Page Page,,,, H

More information

Z62H CPU CLOCK GEN NORTH BRIDGE DDR2 SO-DIMM0 DDR2 SO-DIMM1 TPM 1.2 INFINEON SLB9635 SOUTH BRIDGE EC ENE3925 AZALIA CODEC.

Z62H CPU CLOCK GEN NORTH BRIDGE DDR2 SO-DIMM0 DDR2 SO-DIMM1 TPM 1.2 INFINEON SLB9635 SOUTH BRIDGE EC ENE3925 AZALIA CODEC. PU MERM ocket-p ITP NN. LK EN ZH L Internal K Touch Pad ynaptics E PI FLH LV i 0 ELV RT ebug onnector TPM. INFINEN L E ENE I - PI FLH HV us Vus R LP PI i F MHz/MHz NRTH RIE UTH RIE i MUTIL MHz R ingle

More information

4 4 IDT CV125PA G S 533/667MHz TPS PCI Express x16 ATI. 3D3V_S0 2D5V_S0 VRAM x4 11,12. 1D8V_S3 1D5V_S0 Codec. CARDBUS CardReader

4 4 IDT CV125PA G S 533/667MHz TPS PCI Express x16 ATI. 3D3V_S0 2D5V_S0 VRAM x4 11,12. 1D8V_S3 1D5V_S0 Codec. CARDBUS CardReader YTM / TP0 LW- lock iagram LK N. IT VP Yonah P TKUP YTM /.//. TP, TOP INPUT OUTPUT TVO 0V_0 HOT U 00//MHz TOUT LV "WX+ V_ R /MHz L TP00 0 MHz alistoga, PI xpress x V_ R_VRF_0 TI RT V M Ver.: MP / MP R Ver.:

More information

CPU. Diamondville FCBGA437. FSB533/400MHz NORTH LVDS BRIDGE 945GSE RGB. x2 DMI SOUTH BRIDGE LPC ICH7-M. Touch Pad PCIE USB USB_P1/2/3 USB_P4 USB_P7

CPU. Diamondville FCBGA437. FSB533/400MHz NORTH LVDS BRIDGE 945GSE RGB. x2 DMI SOUTH BRIDGE LPC ICH7-M. Touch Pad PCIE USB USB_P1/2/3 USB_P4 USB_P7 0_lock iagram 0_ystem etting 0_Power equence 0_lock en_ilpr 0_iamondville_U 0_iamondville_PWR 0_N-M(HT) 0_N-M(MI) 0_N-M(RPHI) 0_N-M(R) _N-M(PWR) _N-M(PWR) _N-M() _-IHM(PWR) _-IHM() _-IHM() _-IHM() _R IMM

More information

INTEL PINETRAIL Platform F10T. Notes: Version : A Drawing by :Wain

INTEL PINETRAIL Platform F10T. Notes: Version : A Drawing by :Wain over sheet LOK_IRM MU_&_IRQ_ROUTIN POWER_ON_EQUENE POWER_lock POWER_UET POWER_EQUENE LOK_EN PU PU N N N N N N R_OIMMO R_TEMINTION L_ON RT IHM IHN IHM IHM U_PORT H MINIR MOEM ON LN RIHO RIHO RU L OE UIO

More information

TV Out CRT LCD 13. Nvidia G72M-V 46 ~ 48, 51 ~ 55 PWR SW CP TI PCI ~ 25. Mini-PCI 30 LAN TXFM RJ45 RTL8111B DEBUG CONN 34

TV Out CRT LCD 13. Nvidia G72M-V 46 ~ 48, 51 ~ 55 PWR SW CP TI PCI ~ 25. Mini-PCI 30 LAN TXFM RJ45 RTL8111B DEBUG CONN 34 MYLL lock iagram a. Line In b. Mic In c. INT Mic d. Line Out e. INT.PKR R II O-IMM R II O-IMM P Layer tackup L: ignal L: V L: ignal L: ignal L: N L: ignal ~ LK N. IT V odec L OP MOM M ard ~ RM U / MHz

More information

FOXCONN Title Index Page

FOXCONN Title Index Page Page 0 0 0 0 0 0 0 0 0 0 0 0 0 of chematics Page chematics Page Index lock iagram LOK N (K0) MROM(HOT U) / MROM(HOT U) / MROM(Power/nd) / restline (HOT) / restline (MI) / restline (RPHI) / restline (RII)

More information

G792 C/Y LVDS. 0 Ohm resistor (Y40) RGB CRT S 6,7,8,9,10. RGB switch. To Port Replicator (Y41) ENE. CardReader LAN 88E8055. Mini Card 802.

G792 C/Y LVDS. 0 Ohm resistor (Y40) RGB CRT S 6,7,8,9,10. RGB switch. To Port Replicator (Y41) ENE. CardReader LAN 88E8055. Mini Card 802. Y lock iagram INPUT OUTPUT R LK N. IT V / MHz, R / MHz INT.PKR RJ MOM M ard H 0 ROM 0 Mobile PU Yonah eleron M, T PT HOT U 00//MHz alistoga,,, MINI U TXFM Phone lue-tooth OM LPT U x port U P RT PORT PORT

More information

4 4 RTM865T B0W 3 Max , 5 G TV Out CRT LCD. 3D3V_S0 2D5V_S0(130 ma) 11,12. Line In 1D8V_S3 1D5V_S0(5A) Codec

4 4 RTM865T B0W 3 Max , 5 G TV Out CRT LCD. 3D3V_S0 2D5V_S0(130 ma) 11,12. Line In 1D8V_S3 1D5V_S0(5A) Codec YTM / MX lock iagram RTMT-.00.0W P TKUP YTM / Max.00.00, TV Out TOP INPUT OUTPUT R LK N. / MHz, R / MHz /MHz Mobile PU Yonah eleron M HOT U 00//MHz@.0V alistoga TL+ PU I/F R Memory I/F INTRT RHPI Project

More information

RP-note4 Block Diagram

RP-note4 Block Diagram H F 0 pril 0 '0 Keyboard Light R Termination,ecap, FN Thermal ensor MX0 TPM(T0) RFI (P0) HP OUT 0 HP OUT Int. MI MI IN Mus MI IN tereo peaker x UNUFFR R OIMM Normal ocket 00-PIN R OIMM UNUFFR R OIMM Normal

More information

Model Name: 8I945AE-AE Revision 1.1

Model Name: 8I945AE-AE Revision 1.1 Model Name: IE-E Revision. HEET TITLE HEET TITLE 0 0 0 0 0 0 0 0 0 0 0 OVER HEET LOK IRM OM & P MOIFY HITORY P_L_ P_L_ P_L_ P_L_,E,F, MH-LKEPORT_HOT MH-LKEPORT_RII MH-LKEPORT_PI E, MI MH-LKEPORT_INT V

More information

Page 0 0 0 0 0 0 0 0 09 0 9 0 9 0 9 0 chematics Page Index ( / Revision / hange ate) of chematics Page chematics Page Index lock iagram R (MI,PE,FI) R (LK,MI,JT) R (R) R (POWER) R (RPHI POWER) R (N) R

More information

P901 CPU CLOCK GEN ICS9LPR G NORTH SODIMM 200P BRIDGE. AZALIA CODEC Realtek ALC269 SOUTH BRIDGE MDC MINICARD. Card Reader Alcor AU6336

P901 CPU CLOCK GEN ICS9LPR G NORTH SODIMM 200P BRIDGE. AZALIA CODEC Realtek ALC269 SOUTH BRIDGE MDC MINICARD. Card Reader Alcor AU6336 0_lock iagram 0_ystem etting 0_Power equence 0_lock en_ilpr 0_iamondville_U 0_iamondville_PWR 0_N-M(HT) 0_N-M(MI) 0_N-M(RPHI) 0_N-M(R) _N-M(PWR) _N-M(PWR) _N-M() _-IHM(PWR) _-IHM() _-IHM() _-IHM() _R IMM

More information

Merom. Page 3,4 HOST. 667/800MHz NORTH BRIDGE INTEL. Crestline. Page 5 ~ 10. DMI Interface SOUTH BRIDGE INTEL ICH8-M.

Merom. Page 3,4 HOST. 667/800MHz NORTH BRIDGE INTEL. Crestline. Page 5 ~ 10. DMI Interface SOUTH BRIDGE INTEL ICH8-M. MS- VER :.0 0 : LOK IRM 0 : PLTFORM 0 : Merom- (HOST US) 0 : Merom- (POWER/N) 0 : RESTLINE- (HOST US) 0 : RESTLINE- (MI/V) 0 : RESTLINE- (R) LVS 0 : RESTLINE- (POWER-) Page 0 : RESTLINE- (POWER-) 0 : RESTLINE-

More information

Size Document Number Rev A3. Date: Monday, November 15,

Size Document Number Rev A3. Date: Monday, November 15, ize ocument Number Rev ate: Monday, November, 00 heet of 0 [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP

More information

On Board Device: Main Memory: Dual-channel DDR-II * 4 (Max 8GB) Expansion Slots: PCI EXPRESS X16 SLOT *2 PCI EXPRESS X1 SLOT * 1 PCI SLOT * 2

On Board Device: Main Memory: Dual-channel DDR-II * 4 (Max 8GB) Expansion Slots: PCI EXPRESS X16 SLOT *2 PCI EXPRESS X1 SLOT * 1 PCI SLOT * 2 ONTENT over, lock diagram Intel L PU HEET - - TX Version:. NVII R IMM,,, R Terminations NVII R0 NVII MP PI lot & - - - - PU: Intel Pentium edar Mill / Prescott, Pentium mithfield / Presler and onroe /

More information

A8E/A8S Merom/GM965/PM965 BLOCK DIAGRAM CPU ... MEROM. 3,4 HOST BUS CRESTLINE GM965/PM965 11~15 X4 DMI PCI EXPRESS X1 3 3 SYSTEM

A8E/A8S Merom/GM965/PM965 BLOCK DIAGRAM CPU ... MEROM.  3,4 HOST BUS CRESTLINE GM965/PM965 11~15 X4 DMI PCI EXPRESS X1 3 3 SYSTEM E/S Merom/GM/PM LOK IGRM E Sub block iagram / OM option VI ual H. HOST US RT & TV ON LVS & INV ON VORE R SRM /MHz SYSTEM.VS &.0VS R & VTT +VO & +.VS HRGER PI ETET PROTET LO SWITH FLOWHRT VG ON US x /T

More information

立成网. 视频教程 LICHENGNB.COM

立成网. 视频教程 LICHENGNB.COM 本图纸版权属原厂家所有 仅在服务该产品使用者时使用 YTM / TP0 Project code: 9.Q0.00 INPUT OUTPUT LW- lock iagram LK N. IT VP Yonah P TKUP YTM /.//. TP, TOP INPUT OUTPUT TVO 0V_0 HOT U 00//MHz TOUT LV "WX+ V_ R /MHz L TP00 0 MHz

More information

CPU Diamondville N270 & N280 NORTH BRIDGE SOUTH BRIDGE. SATA FPC Conn

CPU Diamondville N270 & N280 NORTH BRIDGE SOUTH BRIDGE. SATA FPC Conn 0_lock iagram 0_ystem etting 0_Power equence 0_lock en_ipr 0_iamondville_U 0_iamondville_PWR 0_N-M(OT) 0_N-M(MI) 0_N-M(RPI) 0_N-M(R) _N-M(PWR) _N-M(PWR) _N-M() _-IM(PWR) _-IM() _-IM() _-IM() _R OIMM _R_Termination

More information

DR1 (Roberts) Schematics Document ufcpga Mobile Penryn Intel Cantiga-GM + ICH9M REV : A00

DR1 (Roberts) Schematics Document ufcpga Mobile Penryn Intel Cantiga-GM + ICH9M REV : A00 R () chematics ocument ufpg Mobile Penryn Intel antiga-gm + IHM 00-0-0 REV : 00 : Nopop omponent Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. over Page

More information

Yonah/RC410MD/IXP450 BLOCK DIAGRAM

Yonah/RC410MD/IXP450 BLOCK DIAGRAM YonahR0MIXP0 LOK IRM, Yonah M ufp LOK EN. I Thermal ensor (MX) LV & INV. on 0 HOT U TL.0V,00MHZ IN Jack, FN on RT on R0M,,, -link UL R O-IMM, POWER ON KTs, U X U.0 IE U 0 PI_U RU RIOH R 0 RU LOT V, V VPP,

More information

4, 5. SVIDEO/COMP LVDS TPS51100(G2997) ,13. Marvell 88E Mini Card. abgn/bg 23. (100mA) INT.MIC. PCIex1.

4, 5. SVIDEO/COMP LVDS TPS51100(G2997) ,13. Marvell 88E Mini Card. abgn/bg 23. (100mA) INT.MIC. PCIex1. Volvi lock iagram YTM / MX LK N. Merom -00 INPUT OUTPUT T-0 P TKUP eleron M 0 (I LPR0).0 :.MROM.0U TOP V_(). :.MROM.0U, TOUT R / MHz R, /MHz Mobile PU HOT U /MHz@.0V Intel L0 TL+ PU I/F R Memory I/F INTRT

More information

AMD CPU S1g1 ATI RS690M ATI SB600

AMD CPU S1g1 ATI RS690M ATI SB600 .'' active matrix color TFT.'' WX/WX ual hannel LV I/F PE PE PE RT TV OUT VI PE KEYP MTRIX PE PE LE ontrol, uage PE PE PE PE V VORE PE 0 PU VORE PE,, M Turion Mobile ual ore(taylor, pin,w,r,tl-0///0) M

More information

CPU Intel Penryn (Socket P) 3,4. FSB 800/1067 MHz. Cantiga GM LVDS. Panel CRT VGA. x4 DMI. 34 x 34mm 1329 FCBGA HDMI 10~15 DMI X4.

CPU Intel Penryn (Socket P) 3,4. FSB 800/1067 MHz. Cantiga GM LVDS. Panel CRT VGA. x4 DMI. 34 x 34mm 1329 FCBGA HDMI 10~15 DMI X4. NOTE " UM lock iagram 00/0/ PU Intel Penryn (Socket P), FS 00/0 MHz Thermal Sensor G0 FN 0 0 LOK GEN. ISLPRSGLFT RII SOIMM, RII antiga GM x MI LVS VG Panel RT RII SOIMM, RII x mm FG HMI LEVEL SHIFTER PERIOM

More information

Canary2 Block Diagram

Canary2 Block Diagram anary lock iagram 0- V_0 0V_0 Line Out R II IN LK N. IT V RJ- RIL PORT, RT HOT U lviso-m MI I/F IH-M PT Port Replicator ( PIN) PRINTR MHz 00MHz ROM 0 P PI U LP U MI LIN IN LIN OUT TV OUT K TM R 00/MHz

More information

Model Name: 965P-DQ6. Revision 1.01F

Model Name: 965P-DQ6. Revision 1.01F Model Name: P-Q HEET TITLE Revision.0F HEET TITLE 0 0 0 0 0 0 0 0 0 0 0 OVER HEET OM & P MOIFY HITORY LOK IRM POWER MP P_L_ P_L_ P_L_ P_L_ MH-ROWTER_HOT MH-ROWTER_RII MH-ROWTER_PI E, MI MH-ROWTER_T V MH-ROWTER_

More information

F3T Block Diagram. CPU S1g1 DDR2-667 PAGE 2,3,4. H.T 800 MHz C51MV PCIE *1 PCIE *1 PAGE 9,10,11,12,13 H.T MCP51 USB SATA USB 2.

F3T Block Diagram. CPU S1g1 DDR2-667 PAGE 2,3,4. H.T 800 MHz C51MV PCIE *1 PCIE *1 PAGE 9,10,11,12,13 H.T MCP51 USB SATA USB 2. FT lock iagram R M* R M* R M* R M* PE PU VORE PE,, PU g R- ual hannel R PE, O-IMM X bit H.T 00 MHz Power On equence PE LV & INV PE RT & TV OUT PE VI M PE,,,,,, PIE * MV PE,0,,, PIE * PIE * U PE MINI R

More information

S Note-3 Block Diagram

S Note-3 Block Diagram Jan. ' Keyboard Light Thermal ensor MX99 LM I us / M us TML TRFN LIN OUT Int. MI MI IN RJ ONN Mus UNUFFR On-oard R OIMM x,,,, H 9 -PIN R OIMM UNUFFR R OIMM ocket, OP MP MX9 9 O 9,, Modem/luetooth U U lock

More information

THERMAL EMC2102 CRT 17 LCD HDMI MXM CONN. CardReader JMicro JMB385 LAN. MS/MS Pro/xD /MMC/SD. Giga LAN 88E PWR SW. New card. Mini Card.

THERMAL EMC2102 CRT 17 LCD HDMI MXM CONN. CardReader JMicro JMB385 LAN. MS/MS Pro/xD /MMC/SD. Giga LAN 88E PWR SW. New card. Mini Card. iger lock iagram LK N. I LPRKLFT R IMM /00 MHz INT.MI Line In MI In INT.PKR Line Out (PIF) RJ R IMM /00 MHz odec L V OP MP Q OP MP MOM M ard IO/H Mb /00MHz /00MHz ZLI PI H T O T T Mobile PU HOT U /00/0MHz@.0V

More information

Morar Block Diagram 2005/05/28

Morar Block Diagram 2005/05/28 Morar lock iagram 00/0/ LK N. Mobile PU Project ode:.0.00 YTM / TP0, P:00- R II 0 MHz R II 0 MHz IT V,, HOT U Intel 0ML MI I/F 0MHz 00MHz,,,,0 R_VRF V_ R_VRF_ Line In Int. MI In, odec L 0MHz 0MHz LINK

More information

AG1(Alviso) Block Diagram 2005/11/01

AG1(Alviso) Block Diagram 2005/11/01 (lviso) lock iagram 00//0 LK N. Mobile PU Project ode:.0.00 P:0-0 Line Out R II 00 MHz R II 00 MHz Line In Int. MI In INT.PKR P Layer tackup L: ignal L:V L: ignal L: ignal L: N L: ignal IT V,, odec L OP

More information

PCB NO. DM205A SOM-128-EX VER:0.6

PCB NO. DM205A SOM-128-EX VER:0.6 V. M0 M M M M M M M MQM0 MQS0N MQS0P M M M0 M M M M M MQM MQSN MQSP U RM R0 Q00 M0 U Q0 M T Q0 M R Q0 M U Q0 M U Q0 M T Q0 M T Q0 M T M0 M U QS0N M U QS0P M0 M W0 Q0 M W Q0 M V0 Q0 M U0 Q M W Q W Q 0 V

More information

NV11,4Mx16 DDR, RGB, INTERNAL DVI-I, AGP.

NV11,4Mx16 DDR, RGB, INTERNAL DVI-I, AGP. . NV.V 00PF 00PF 00PF 0.UF 0.UF 0.UF 0.UF 0UF 0UF 0 0.UF 0.UF.V TO- -pin package Semtech Z, Unisem US0 00 NV O- RG-PWR-IN.V@ /- 0mV 0UF 00PF 00PF 0 00PF 0UF 00PF 0UF 0 0.UF 0 00PF 0.UF 0 O0 U POWR SNS

More information

Rev. SA SA SA SA SA SA SA SA SA SA. 43 Status LED & LID

Rev. SA SA SA SA SA SA SA SA SA SA. 43 Status LED & LID chematics Page Index ( / Revision / hange ate) Page of chematics Page 0 0 chematics Page Index lock iagram 0 R (MI,PE,FI) 0 R (LK,MI,JT) 0 R (R) 0 R (POWER) 0 R (RPHI POWER) 0 R (N) 09 R (REERVE) 0 PH

More information

SODIMM_EDP LEPUS MB P/N:6050A STAND OFF:CPU S4501,S4502,S STAND OFF:6052B INVENTEC

SODIMM_EDP LEPUS MB P/N:6050A STAND OFF:CPU S4501,S4502,S STAND OFF:6052B INVENTEC THI RW N PEIFITION,HERE,RE THE PROPERTY OF VENTE ORPORTION N HLL NOT E REPOUE,OPIE,OR UE WHOLE OR PRT THE I FOR THE MNUFTURE OR LE OF ITEM WITH WRITTEN PERMIION,VENTE ORPORTION,00 LL RIHT REERVE. F HF

More information

Mocha-1 Block Diagram

Mocha-1 Block Diagram May.0 Thermal ensor MX I us / M us us witch I 0 -in- lot RJ onn udio odec IOU ard Mus UNUFFR R OIMM Normal ocket 0-PIN R OIMM UNUFFR R OIMM Reverse ocket T H Media ard Reader U U.0 H U.0 H Media lice Finger

More information

Kendo-3 Workstation Block Diagram

Kendo-3 Workstation Block Diagram Feb. ' 0 RT Port Thermal ensor M 0 I / M us us witch I M us Keyboard Light.'' WUX+/ WX+ L RT LTION P connector isplay port to ocking UIO OMO Jack ual Link LV T H T O R RT isplay Port isplay Port et ombo

More information

J1B B1 B3 B5 B7 B9 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B35 B37 B39 B41 B43 B45 B47 B49 B51 B53 B55 B57 VCC VCC USB_DET

J1B B1 B3 B5 B7 B9 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B35 B37 B39 B41 B43 B45 B47 B49 B51 B53 B55 B57 VCC VCC USB_DET GP0 GP0 GP0 P0 GP0 GP GP GP GP GP GP GP P GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP00 UINO ONE PIN EFINE GP0 GP GP GP GP GP GP GP GP0 GP GP

More information

Leopard2 Block Diagram

Leopard2 Block Diagram LK N I0 Leopard lock iagram Mobile PU othan V_UX onn PMI Power LOT witch TP0 /M in ard lost PI RU /M/MM/M lviso Host U 00/MHz V TI MP Mini-PI 0.a/b/g RJ ONN RJ ONN 0, 0/00 RTL00 MOM M ard, PI U -LINK,,,,,0,,,

More information

915A01 Schematic Page Index

915A01 Schematic Page Index Foxconn Precision o. Inc. chematic Page Index Fab. ate: //. Index Page. Topology. Rest Map. lock istribution. Power elivery Map. Power equence. K locken. VR. (, P). VR. (). R POWER. Power.V/.V..V_MH. L

More information

Discrete/UMA Schematics Document Sandy Bridge Intel PCH REV : A00

Discrete/UMA Schematics Document Sandy Bridge Intel PCH REV : A00 iscrete/um chematics ocument andy ridge Intel PH 0-0-0 REV : 00 :None Installed UM:UM ONLY installed N: ONLY FOR N installed. Q:ONLY FOR Q installed. PL: K9 PL circuit for 0mW solution installed. 0mW:

More information

Appendix B:Schematic Diagrams

Appendix B:Schematic Diagrams ppendix B: This appendix has circuit diagrams of the M0E/M0E notebook s PB s. The following table indicates where to find the appropriate schematic diagram. iagram - Page iagram - Page iagram - Page ystem

More information

0_lock iagram 0_ystem etting 0_Power equence 0_E Pin efine 0_HTRY 0_lock en 0_othan_HT 0_othan_PWR_ 0_0ML_HT_M 0_0ML_RM _0ML_V_LV_TV _0ML_PWR _0ML H-M_zalia_P_P_LN _H-M_U_PE_M_E_T _H-M_PWR nboard RM_Top

More information

J400 C UF,50V,20% V-STBY 10.0K,1%,1/4W R63 R61 1M,5%,1/4W V-STBY R K,1%,1/4W AC-OK RY3A R11INT 1 NC NO COM 47K,5%,1/4W R11

J400 C UF,50V,20% V-STBY 10.0K,1%,1/4W R63 R61 1M,5%,1/4W V-STBY R K,1%,1/4W AC-OK RY3A R11INT 1 NC NO COM 47K,5%,1/4W R11 MNL-PIN J MNL-PIN J MNL-PIN J MNL-PIN J J00-00 MNL-PIN J MV J MNL-PIN PHS-REF (Sh. ) IN-RET (Sh.,) -OK (Sh. ) HOT-IN 0V(US) 00V(INT) MV LIN-XFER (Sh. ) +V OOST (Sh. ) TRIM (Sh. ) MNL-PIN MNL-PIN 0V(US)

More information

CPU NORTH BRIDGE SOUTH BRIDGE

CPU NORTH BRIDGE SOUTH BRIDGE 0_lock iagram 0_System Setting 0_Power Sequence 0_lock Gen_ISLPR 0_iamondville_US 0_iamondville_PWR 0_N-GMS(HOST) 0_N-GMS(MI) 0_N-GMS(GRPHI) 0_N-GMS(R) _N-GMS(PWR) _N-GMS(PWR) _N-GMS() _S-IHM(PWR) _S-IHM()

More information

MS Last Schematic Update Date: 11/06/2002

MS Last Schematic Update Date: 11/06/2002 over heet lock iagram MIN LOK EN & IE ONNETOR mp- INTEL PU ockets INTEL rookdale- /L MH R LOT R TERMINTOR INTEL IH H00 & VI TV OUT PI LOT / FWH U PORT LP I/O(Ms LPM) OM & LPT & F & FN K / M ONNETOR / POV

More information

TE1 Block Diagram. Intel. Merom (35W) FSB(667/800MHZ) Page 18 CRT. PCI-E 16X Lan. Crestline GM 533/ 667 MHZ DDR II. Page 5,7,8,9,10,11.

TE1 Block Diagram. Intel. Merom (35W) FSB(667/800MHZ) Page 18 CRT. PCI-E 16X Lan. Crestline GM 533/ 667 MHZ DDR II. Page 5,7,8,9,10,11. P STK UP TE lock iagram LYER : TOP LYER : S LYER : IN LYER : V LYER : IN LYER : IN LYER : S LYER : OT V_ORE HMI Page LE PNEL Page HMI RT Page 0 Transmitter Sil Page L PNEL Page LE river I Page zalia SVO

More information

SHINAI-3 Switchable Graphics System Block Diagram

SHINAI-3 Switchable Graphics System Block Diagram Keyboard Light HINI- witchable raphics ystem lock iagram P Layer tackup L: TOP L: INL RT Port Thermal ensor M 0 I / M us us witch I." WX+ RT LTION P connector isplay port to ocking M us Touch creen 0 UIO

More information

FS-1100A Page # Description Of Page

FS-1100A Page # Description Of Page F-00 ision escription Of hanges ate (M--Y) Phase R0. modify mm reset circuit (page ) 0-0-00. add PI bit function (page,, ). increase V power bypass cap (page 0, ). modify FN speed sensor circuit (page

More information

VER : 3A. Thermal Sensor & Fan P37 LVDS. E-switch PI2PCIE412-DZHE LVDS MXM III-NB8E (GT/SE/GLM) VRAM 256M VRAM 512M P18 HDMI HDMI P19 P17 SPDIF_MXM

VER : 3A. Thermal Sensor & Fan P37 LVDS. E-switch PI2PCIE412-DZHE LVDS MXM III-NB8E (GT/SE/GLM) VRAM 256M VRAM 512M P18 HDMI HDMI P19 P17 SPDIF_MXM Module Y Mini PI (for ebug) P H / O (ST) P P X'TL.MHz LOK GENERTOR YLFXT RII SO-IMM RII SO-IMM P H (ST) P H / O (PT) P P in ard Reader ontroller R P,P in ard Reader connector P ST ST PT PI us MX(Maddog.)

More information

1101HA Block Diagram (Silverthorne / Poulsbo)

1101HA Block Diagram (Silverthorne / Poulsbo) 0_LK RM 0_H P etting 0_E Pin efine 0_Power equrnse 0_Power equence 0_Power equence escription 0_lock en_lpr 0_PU-LVERTHRNE () 0_PU-LVERTHRNE () 0_PU-LVERTHRNE () _H_Poulsbo_HT () _H_Poulsbo_R () _H_Poulsbo_LV/V

More information

KiliManjaro. CS Build(A02) INVENTEC KiliManjaro POWER DRAWER DESIGN CHECK RESPONSIBLE TITLE SIZE = VER : REV CHANGE NO.

KiliManjaro. CS Build(A02) INVENTEC KiliManjaro POWER DRAWER DESIGN CHECK RESPONSIBLE TITLE SIZE = VER : REV CHANGE NO. C Build(A0) 00.0.0 RAWER EIN CHECK REPONIBLE EE ATE POWER ATE ATE CHANE NO. REV IZE = FILE NAME : XXXX-XXXXXX-XX P/N XXXXXXXXXXXX VER : IZE COE OC. NUMBER A C Model_No HEET OF REV X0 TABLE OF CONTENT PAE

More information

C uF T16 VDD T15 TMS TMS MCU_PORT_VDD T14 TDO TDO T13 JCOMP JCOMP PF3 T12 PF3 T11 VDDE3 5.0V PF4 T10 PF4 PJ5 PJ5 PF6 PF6 PF9 PF9 5.0V 5.

C uF T16 VDD T15 TMS TMS MCU_PORT_VDD T14 TDO TDO T13 JCOMP JCOMP PF3 T12 PF3 T11 VDDE3 5.0V PF4 T10 PF4 PJ5 PJ5 PF6 PF6 PF9 PF9 5.0V 5. Size FSM No. WG No. Rev of 9 Galen Street Floor M 0 US MP0EMO Schematic -- MU and Symbol V V P P P P P 9 P0 0 P P P P0 VE V REFYP V P PK P P P 9 P 0 P0 P P P V P P P P9 P P P0 P P 9 P 0 P P P9 P P P P

More information

FP7 (CULV) BLOCK DIAGRAM

FP7 (CULV) BLOCK DIAGRAM FP (ULV) LOK IGRM P STK UP 0 L HI TOP GN IN IN V OT PU SU00 eleron FS /00/0 P (G) 0W PGE,, PU THERML SENSOR PGE LK_PU_LK,LK_PU_LK# LK_MH_LK,LK_MH_LK# LK_PIE_VG,LK_PIE_VG#.MHz LOK GEN RTMN-0-V-GRT PGE RIII-on

More information

Z96J DDR2 SO-DIMM1 DDR2 SO-DIMM0 AZALIA CODEC NEWCARD MINICARD CLOCK GEN MDC BRIDGE BRIDGE SOUTH NORTH CPU. Card Reader M56P TPM 1.2 ATI LAN AUDIO AMP

Z96J DDR2 SO-DIMM1 DDR2 SO-DIMM0 AZALIA CODEC NEWCARD MINICARD CLOCK GEN MDC BRIDGE BRIDGE SOUTH NORTH CPU. Card Reader M56P TPM 1.2 ATI LAN AUDIO AMP R Mx x Option P. YONAH W CPU MEROM P.~ W CLOCK EN IC 0 P. ZJ R Mx x P. PB MHz THERMAL CONTROL P. LC CRT P. P. TV-OUT P. ATI MP PCI-E X NORTH BRIE Intel PM P.~0 P.~ R R R O-IMM0 P.0~ R O-IMM IA ROM TPM.

More information

ORION VCC_PEG_BUILD INVENTEC ORION DATE POWER DRAWER DESIGN CHECK RESPONSIBLE TITLE

ORION VCC_PEG_BUILD INVENTEC ORION DATE POWER DRAWER DESIGN CHECK RESPONSIBLE TITLE VCC_PE_BUIL 00..0 RAWER EIN CHECK REPONIBLE EE ATE POWER ATE ATE CHANE NO. REV IZE = VER : IZE COE OC. NUMBER FILE NAME : XXXX-XXXXXX-XX A C Model_No P/N XXXXXXXXXXXX HEET OF REV X0 TABLE OF CONTENT PAE

More information

Power supply, reset circuit, reference voltage and power indicator. Analogue and digital inputs with options for FET outputs

Power supply, reset circuit, reference voltage and power indicator. Analogue and digital inputs with options for FET outputs VR core and power 00v.0 Power supply, reset circuit, reference voltage and power indicator. Port 00v.0 nalogue and digital inputs with options for FET outputs Port 00v.0 igital inputs with optional FET

More information

HANGZHOU 1.0 MV_BUILD

HANGZHOU 1.0 MV_BUILD HANZHOU.0 MV_BUIL 00.0.9 www.masteram.su RAWER EIN CHECK REPONIBLE EE ATE POWER ATE ATE CHANE NO. REV IZE = FILE NAME : XXXX-XXXXXX-XX P/N XXXXXXXXXXXX VER : IZE COE OC. NUMBER C 0A0000-0 HEET OF REV A0

More information

C107 C108 C uF/10V Ta. 10uF/10V Ta. 100nF. 100nF. 100nF C106 C111 C110 VCC VCC AVCC (AD0)PA0 (AD1)PA1 (AD2)PA2 (AD3)PA3 (AD4)PA4 (AD5)PA5

C107 C108 C uF/10V Ta. 10uF/10V Ta. 100nF. 100nF. 100nF C106 C111 C110 VCC VCC AVCC (AD0)PA0 (AD1)PA1 (AD2)PA2 (AD3)PA3 (AD4)PA4 (AD5)PA5 ate: may 0 Kiad.... ize: Id: / RPIVR alarm v. File: rpialarm.sch heet: / pittnerovi.com P0 P P 0 P0 PI VR_ IRQ IRQ VR_ V R0 00k RFM_IRQ PWM LOOP LOOP0 comm comm.sch 00uF/.V R0 00k V VR_ K VR_ V V RT P0

More information

SYMETRIX INC th Avenue West Lynnwood, WA USA

SYMETRIX INC th Avenue West Lynnwood, WA USA ENE MI J XLR-FEMLE NOTE: ENE MI R K00 R K00 J (h ) isables phantom power for all mics. Remove R and/or R to disable phantom power for ense Mic and/or only. J XLR-FEMLE NP NP 0 NP R K00 R K00 NP R 0 NP

More information

Generated by Foxit PDF Creator Foxit Software For evaluation only.

Generated by Foxit PDF Creator Foxit Software   For evaluation only. I_ST I_SLK K_% R K_% R L_0 L_ L_ L_ KEY TON_STHL /F NN_ NN_ P M VS OUTL P OUTR VR MIIN VREF V HOSI LOSI R X pf LOSO.KHZ M_% pf HOSO X pf MHz HOSI 0 pf POWER Generated by Foxit PF reator Foxit Software

More information