FOXCONN Title Index Page

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1 Page of chematics Page chematics Page Index lock iagram LOK N (K0) MROM(HOT U) / MROM(HOT U) / MROM(Power/nd) / restline (HOT) / restline (MI) / restline (RPHI) / restline (RII) / restline (POWR,V) / restline (V OR) / restline (V) / RII(O-IMM_0) / RII(O-IMM_) / RII(Termination) / V(PI-) V(TRP) V(R) V(MULTIU) V(LV/V ) VRM(R)# / VRM(R)# / VRM(R)# / VRM(R)# / V(POWR) / V(POWR) / V(POWR) / VRM(YP) / VRM(YP) / VRM(YP) / VRM(YP) / TVIN and OUT/emi-PnP# RT LV HMI MINI PI (TV) IH-M( PI/U ) / IH-M(LP,I,T)/ IH-M( PIO) / chematics Page Index ( / Revision / hange ate) Rev. ate.0 00//.0 00//.0 00//.0 00//0.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00// // 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// Page of chematics Page IH-M( POWR) / IH-M( N) / LN (0 MRVLL) +K (0) Flash ROM/XU T H RI PT -ROM PI (PI U) PI ( ILINK) PI (M-T/UO/M/) PI ( PMI) luetooth Mini-PI ard XPR U.0 IR Reciver FN / HW THRML PROTTION aughter oard onn. M/OI Logo L UIO(O & POWR) UIO( MP & HP & PK) UIO (MUT & INTMI) UIO (econd odec) udio OR conn Power esign iagram IN&harger Y Power (+_V/+V) Y Power(+_V/+_0V) R Power(+_V/+0_V) PU_Vcore ---MX Others power plan OVP protection V POWR(+_V/ +_V) Inverter oost ircuit HOL & O HITORY(VT) Rev. ate.0 00//.0 00//.0 00//.0 00// // 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00//.0 00//0.0 00//.0 00//.0 00//.0 00// P. Leader heck by esign by Project ode & chematics ubject: M PVT Main oard P P/N: FOXONN Index Page HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of

2 M(eagle anta Rosa )lock iagram Red texts: New modified -OUT P LV WX+ P V -type-p P 0 HMI (HP) P M OM configuration unstuff NP- + NM-T NP- NM-T NM-T NM-T for L Model NX + Hynix VRM NM+Mx VRM NP + Mxbit VRM NM + Mxbit VRM NX + Infineon VRM NX + Infineon & amsung VRM NVI_ NX + Hynix & Infineon VRM NX + Mxbit VRM NX + Mxbit VRM *JP igital TV Tuner KU unstuff Mini PI ONN,T ONN, IR ONN,Felia ONN unstuff for L Model N_ NV_ NVH_ NVI_ udio aughter oard U.0 ONN udio board NVP_ NVM_ NVMM_ NVML_ NVNW NVNOR NVNOR NVH_ NV_ NV_ JTVN_ LN_ -OUT/LV/V/HMI PIF xt. Mic In Jack udio board H PHON JK udio board Int. peaker.0 Walt x P Int. Microphone P RJ udio board PMI onn. P M UO P P i.link P RJ P PIF P0KI-TRL P M. Modem pin P TI PIZHK ardus ardreader i.link P ~ PROM HMI KY L O P 0 NP Transformer Netswap, N0P, XK O P Mini stereo P - P -IN P F/PL P JP igital only FN P FX PWM nvii H NP-(HMI) M NM-T(HMI) L NM-T(HMI) R.V RM P ~ PIF for HMI ZLI ZLI ZLI U.0 MHZ,.V PI U Mini PI (TV) P thernet -LN 0 MRVLL 0/00/000 P Lid witch & L LI PI PI X PU Merom Processor Micro-F- (ocket -pin Micro FP) P ~ North ridge restline F-pin P ~ _pin KU(H):nhanced KU(M)(L):ase P ~ Touchpad ontroller Link0 Flash IO M X/X MI (irect Media Interface) outh ridge IHM / IHM- LQFP- P 0 P/ P P P F 00 MHZ LP N K0F I I T 00 PT O P M hannel M hannel TT ONN. P U.0 PI + U.0 PI U.0 U.0 T b/s T H -RI0 P lock en. K0 P Thermal ensor FM (PU/MH) uop- P I,ILPRYLFT T H -RI P O-IMM 0 MHZ R(II) P 00 pin O-IMM MHZ R(II) P Thermal ensor FM (V/IMM) uop P 0 X,TL.MHZ M/M/M/M P P 0 00 pin U.0 ONN.X xpress ard Mini-ard PI P M(.M) P 0 U.0 luetooth P Oide U.0 P 0 U.0 IR Reciver P FOXONN lock iagram HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of

3 / backup for MI request close to R N_0.U_0V_K 00_XR K_IO_VOUT +_VRUN R0 N J 00 Q This dumping resistor and F should be placed close to U, update for MOR requirement on/. 00 N_00P_0V_K_N PLK_MINI MHz Port PI0 (pin) PI (pin) PI (pin) PI (pin) PI (pin) PI-F (pin) Length as short as possible. 0 R 0_J 00 R N_0_J 00 N_ If LP0, populate R,R0,,Q and depopulate R. Ig LP0, populate R and depopulate R,R0,,Q. LK_ LK_U R 00_J 00 M0 N N ebug card/(k) PI0 TV tuner IH H0KF-T0 L 0R-00MHZ_00 Y ITTI_L MHZ_0P_0PPM 00 R_PLK_MINI H0KF-T0 L 0R-00MHZ_00 H0KF-T0 L 0R-00MHZ_00 0 P_0V_J_N 00 R0 0_J 00 R._F 00 R._F 00 M0 N N ebug card PI0 (K) IH 0.U_V_Y_Y 00 0.U_V_Y_Y 00 VP0 VP0 VP0 VP0 U_XTLIN U_XTLOUT R _F 00R_PI R0._F 00 R_PI_TM R0._F 00 L0 MMZ00T 0R-00MHZ_00 M bus ddress : 000 (IH) For clock generator 00 MHz Port M0 setting configuration /W etting this pin type /W etting LKRQ for this pin R0 (pin,) FX PI_P (b0=0) for use R0 R (pin,) (R0 /R only either one) R (pin,) PI T R (pin,) PI IH R# (b=;b=) (b=;b=0,b=0) for use R R (pin,) PI MINI (b=0) for use R R# (b=,b=) R(pin0,) R(pin,) R(pin,) R(pin0,) PI -LN N N MH PLL R# (not control) (b=,b=0,b=0) for use R(not control R#/F) R#F (not control) R# (b=) R0(pin,) PI XPR R#H (b=) R(pin,) R#(MH)/R#H(XPR) (b=0,b=0 for use LKRQ,H) 0.U_V_Y_Y 00 0.U_V_Y_Y 00 P_0V_J_N 00 VP0 0U_.V_M 00_XR VP0 0U_.V_M 00_XR VP0 0U_.V_M 00_XR VP0 0 0U_.V_M 00_XR R_LK_PI_IH# RP R_LK_PI_IH 00_PR R_RT_M_NON R_RT_M_NON R_R_M_ R_R_M_ +VRUN H0KF-T0 L 0R-00MHZ_00 R _F 00 +V_LK_ +V_LK_F +V_LK_ ILPRYLFT 0.0U_V_K_ 00 +V_LK_ +V_LK_F 0.0U_V_K_ 00 PU_L0 R.K_J 00R_FL_UM 0 PU_L R 0_J 00R_FL_TT_MO FL/U_MHZ FL/TT_MO TP MIL K_IO_VOUT N LK_IHPI PLK_ LK_KPI PLK_JI LK_PI_IH# LK_PI_IH H0KF-T0 L0 0R-00MHZ_00,,0, M_LK_U,,0, M_T_U 0 0 U V_IO VPU_IO 0 VPLL_IO VR_IO VR_IO VR_IO 0 X X R _F 00R_PI_F_ITP_N PI_F/ITP_N PI PI/TM R_PI_M_L PI/_elect LK T N N NR NR NR N NPU NPI NRF R/R#_ RT/R#_ +V_LK_ +V_LK_ +V_LK_ +V_LK_ VPU VR VRF VPI V VPLL RT//MHZ_nonss R//MHZ_ 0.0U_V_K_ 00 U_V_K_ 00 R _F 00 U_V_K_ 00 PUT_F PU_F PUT0 PU0 RT/PUT_ITP R/PU_ITP R_LK_PI_T R_LK_PI_T# OT_OR_R0 OT#_OR_R0# RP 00_PR R _F 00 R _F 00 R _F 00 0U_.V_M 00_XR PU_L R0 0K_J 00 +V_LK_ 0.0U_V_K_ 00 +V_LK_ +V_LK_ RP0 00_PR TP000 MIL RP 00_PR RP 00_PR R _F U_V_K_ 00 R_LK_MH_LK 0R_LK_MH_LK# RP 00_PR R_LK_PU_LK R_LK_PU_LK# RP 00_PR R_R_PUITP R_R#_PU#ITP TP MIL TP MIL R_RT_R#_F TP MIL 0 R_LK_MH_PLL R_LK_MH_PLL# RP 00_PR R_R_R#_ R_PI0_R#_ PI0/R#_ RT0/OTT_ R0/OT_ U_V_K_ 00 R _F 00 PI_TOP# PU_TOP# RT/R#_F RT R R/R#_ R_R RT R_R# R 0 R_R_R#_ R/R#_ R_LK_PI_MINI RT R_LK_PI_MINI# R R_PI_R#_ PI/R#_ R_LK_PI_XP# R0 R_LK_PI_XP RT0 R_RT_R#_H RT/R#_H RT/TT R/T K_PWR/P# R_LK_IH FL/RF0/TT_L PU_L0 PU_L PU_L RP 00_PR R R N_K_J 00 R R N_K_J 00 R 0_J 00 0_J 00 0_J 00 R N_K_J U_V_K_ 00 U_V_K_ 00 U_V_K_ 00 U_V_K_ 00 PM_TPPI# 0 TP 00// TP_PU# Roger request 0 MIL LK_MH_LK LK_MH_LK# LK_N 0 LK_IH 0 LK_PU_LK LK_PU_LK# LK_MH_PLL LK_MH_PLL# LK_PI_LN LK_PI_LN# LK_PI_MINI LK_PI_MINI# LK_PI_XPR# LK_PI_XPR onnect this pin via a 0 K series resistor to the F pin on the processor LK_PI_T LK_PI_T# LK_PI_P LK_PI_P# onnect this pin via a. K series resistor to the F pin on the processor, R N_K_J 00 R0 N_K_J 00 +_0VRUN +_0VRUN R N_K_J 00 F Frequency Table: FL FL FL PU R[:0] PI F / / / / / (Reserced) +VRUN +VRUN R N_0K_J00 R0 N_0K_J 00 R0 0K_J 00 R N_0K_J 00 R0 0K_J 00 +VRUN R0 N_0K_J 00 R_PI0_R#_ R_PI_R#_ R_RT_R#_H R_PI_F_ITP_N R_PI_TM R_PI_M_L +VRUN _F 00 R0 +VRUN _F 00 R0 +VRUN R_R_R# F 00 R +VRUN _F 00 R close to terminal side (For MI) N_0P_0V N LK_ 00 LK_U N_0P_0V N 00 LK_KPI N_0P_0V N 00 PLK_ N_0P_0V N 00 heck List.0 MH_L0 *.F[:0] do not have internal pullups or pull downs. Please refer to the latest restline volume for configuration options +_0VRUN *. k pull-up or pull-down or direct connect from processor. M0 MH_L only MH_L[0..]pull down K MH_L pin setting 0=R,=ITP for pin, pin setting 0= Overclocking of PU and R llowed = Overclocking of PU and R NOT allowed pin setting 0= L_T 00MHz differential clock. for pin, = MHz non-spread clock, R0 0K_J 00 R0 0K_J 00 R 0K_J 00 R 0K_J 00 FOXONN PLK_MINI N_0P_0V N 0 00 LK_IHPI N_0P_0V N 00 N_0P_0V N LK_IH 00 PLK_JI N_0P_0V N 00 LOK N(K0) ize ocument Number Rev (M0--0 )Mainoard (MX-) TLKRQ# 0 MINI_R_T# MH_LK_RQ# XPR_T# HON HI PRIION IN. O., LT. P - R& ivision ate: Friday, ugust, 00 heet of

4 Layout note: no stub on H_TPLK TP. H_TPLK# to be routed in daisy chain fashion from IH to LP slot and then to PU. H_#[..] H_T#0 H_RQ#[..0] H_T# H_0M# H_FRR# H_INN# H_TPLK# H_INTR H_NMI H_MI# dd H_#[..] TP MIL TP MIL TP0 MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP0 MIL TP MIL H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_RQ#0 H_RQ# H_RQ# H_RQ# H_RQ# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# TP_PU_RV0 TP_PU_RV0 TP_PU_RV0 TP_PU_RV0 TP_PU_RV0 TP_PU_RV0 TP_PU_RV0 TP_PU_RV0 TP_PU_RV0 TP_PU_RV0 U J []# L []# L []# K []# M []# N []# J N P P L P P R M K H K J L Y U R W U Y U R T T W W Y U V W V []# [0]# []# []# []# []# []# []# R ROUP 0 T[0]# RQ[0]# RQ[]# RQ[]# RQ[]# RQ[]# []# []# []# [0]# []# []# []# []# []# []# []# []# []# R ROUP [0]# []# []# []# []# []# T[]# 0M# FRR# INN# TPLK# LINT0 LINT MI# M RV[0] N RV[0] T RV[0] V RV[0] RV[0] RV[0] RV[0] RV[0] RV[0] F RV[0] IH RRV XP/ITP INL ONTROL # H NR# PRI# FR# H RY# F Y# THRML H LK R0# F IRR# 0 INIT# LOK# H RT# R[0]# F R[]# F R[]# TRY# HIT# HITM# PM[0]# PM[]# PM[]# PM[]# PRY# PRQ# TK TI TO TM TRT# R# PROHOT# THRM THRM THRMTRIP# LK[0] LK[] 0 H_IRR# H_R#0 H_R# H_R# XP_PM#0 XP_PM# XP_PM# XP_PM# XP_PM# XP_PM# XP_TK XP_TI XP_TO XP_TM XP_TRT# 00 PROHOT# H_THRM H_THRM PM_THRMTRIP# TP MIL TP MIL 00// Roger request MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP H_# H_NR# H_PRI# H_FR# H_RY# H_Y# H_RQ#0 H_INIT# H_LOK# H_PURT# H_R#[..0] H_TRY# H_HIT# H_HITM# PM_THRMTRIP# LK_PU_LK LK_PU_LK# +_0VRUN R _J 00 lose to PU side PM_THRMTRIP# PM_THRMTRIP# should connect to IH-M and MH without T-ing (No stub) IHM's PIO: VIL---> -0.V ~ 0.V VIH--->.0V ~.+0.V MROM's PROHOT#: VIL---> -0.V ~ 0.*VP VIH---> 0.*VP ~ VP+0. +_0VRUN R _J 00 +VRUN XP_TI 00 0_J R 00 _ XP_TM 00 N_._F R0 XP_PM# 00 _F R XP_TK 00 _F XP_TRT# R R ebug port not used. resistors close to PU. W/:0/0 (microstrip) +_0VRUN eagle=0r(%) R.0=.R(%) heck.0=0r(%) M0 VT=0R(%) eagle=r(%) R.0=.R(%) heck.0=r(%) M0 VT=R(0.%) eagle=--- R.0=.R(%) heck.0=--- M0 VT=N_.(%) eagle=r(%) R.0=.R(%) heck.0=r(%) M0 VT=R(%) eagle=0r(%) R.0=R(%) heck.0=00~0r(%) M0 VT=R(%) OVT_# Q +VRUN R.K_J TU +_0VRUN R _J 00 Q0 N00 PROHOT# ase on R change net name N_-0LM-XT_. N 0 N_0P_0V_K_ 00 PU OKT_P FOX_PZ-M-0 +V V V OUT U R +_0VRUN N_0_J 00,,,,,,,,, PLT_RT# R.K_J 00 PM_THRMTRIP# 00 Q +V Q R K_J 00 N00 00 MMT0 TP MIL H_THRM 00P_0V_K_ 00 TP MIL H_THRM 0,, OVT_# R_OVT_# R 00 0_J When using Reset I solution, & R need to change to N condition 0.U_V_M_ 00 RT# 0, R.K_J 00 0.U_V_M_ 00 U V MLK P MT N LRT# THRM# N M0--ZL-TR null M bus ddress : 000 = For FM Place Thermal-ensor near PU & MH. / change part from FM ( -FM-0000) to -Pf (-P-0000) FOXONN R.K_J 00 Merom(HOT U)/ R.K_J 00 R0.K_J 00 HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of M_THRM_LK 0, M_THRM_T 0, PM_THRM#

5 H_#[..0] H_TN#0 H_TP#0 H_INV#0 H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# U [0]# F []# []# []# F []# []# []# []# K []# J J H F K H []# [0]# []# []# []# []# []# J TN[0]# H TP[0]# H INV[0]# T RP 0 T RP []# Y []# []# V []# V []# V []# T []# U []# U [0]# []# []# []# []# []# []# []# Y W Y W W TN[]# Y TP[]# INV[]# U H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_TN# H_TP# H_INV# Place close to PU /0 change from 00 to 00 +_0VRUN mil(microstrip) R K_F 00 R K_F 00 N_0.U_V_M_ 00 0 Layout Note: Zo= ohm, 0." max for TLRF. H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_TN# H_TP# H_INV# Max Length 0. inch H_TLRF R N_K_J 00 PU_TT R N_K_J 00 PU_TT TP0 MIL PU_TT PU_TT 00_XR TP MIL PU_TT N_0.U_0V_KTP MIL PU_TT PU_L0 PU_L PU_L N []# K []# P []# R []# L M L M P P P T R L T RP TLRF TT MI TT TT F TT F TT TT [0]# []# []# []# []# []# []# []# []# []# T [0]# N []# L TN[]# M TP[]# N INV[]# L[0] L[] L[] T RP PU OKT_P FOX_PZ-M-0 []# []# [0]# []# []# []# []# []# []# []# []# []# [0]# []# []# []# OMP[0] OMP[] OMP[] OMP[] 0 F F TN[]# TP[]# F INV[]# 0 R U Y PRTP# PLP# PWR# PWROO LP# PI# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# OMP0 OMP OMP OMP R0._F 00 R._F 00 R._F 00 R._F 00 H_PRTP#,, H_PLP# H_PULP# PI# Layout Note: omp0, connect with Zo=. ohm, make trace length shorter then 0.". omp, connect with Zo= ohm, make trace length shorter then 0.". H_TN# H_TP# H_INV# H_PWR# H_PWR TP MIL 00// Roger request Layout: onnect test point with no stub TP 0MIL FOXONN Merom(HOT U)/ HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of

6 U_.V_M_ 00 VHOR VHOR VHOR VHOR VHOR ackup 0uF capacitors for uf shortage. VHOR U_.V_M_ 00 U_.V_M_ 00 U_.V_M_ 00 N_0U_.V_M 00_XR N_0U_.V_M 00_XR 0 N_0U_.V_M 00_XR U_.V_M_ 00 0 U_.V_M_ 00 U_.V_M_ 00 0 U_.V_M_ 00 N_0U_.V_M 00_XR N_0U_.V_M 00_XR U_.V_M_ 00 U_.V_M_ 00 U_.V_M_ 00 N_0U_.V_M 00_XR U_.V_M_ 00 N_0U_.V_M 00_XR U_.V_M_ 00 U_.V_M_ 00 U_.V_M_ 00 N_0U_.V_M 00_XR N_0U_.V_M 00_XR U_.V_M_ 00 N_0U_.V_M 00_XR N_0U_.V_M 00_XR N_0U_.V_M 00_XR U_.V_M_ 00 U_.V_M_ 00 U_.V_M_ 00 U_.V_M_ 00 VHOR VHOR F F F0 F F F F F F U V[00] V[00] V[00] V[00] V[00] V[00] V[00] V[00] V[00] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] PU OKT_P FOX_PZ-M F F0 F F F F F F0 VP[0] VP[0] V VP[0] J VP[0] K VP[0] M VP[0] J VP[0] K VP[0] M VP[0] N VP[0] N VP[] R VP[] R VP[] T VP[] T VP[] V VP[] W V[0] V[0] VI[0] VI[] VI[] VI[] VI[] VI[] VI[] VN VN F F F F VHOR H_VI0 H_VI H_VI H_VI H_VI H_VI H_VI VN PU_V---->0m PU_VP----->. PU_V------> eagle=0u R.0=NO heck.0=no M0 VT=NO VN ame Length Layout Note: Route VN traces at. Ohms with 0 mil spacing. Place PU and P within inch of cpu. width= mil spacing= mil +_VRUN PU +_0VRUN N_0U_.V_M 0.U_V_M_ 0.U_V_M_ 00_XR U_.V_M 00_XR R 0_J 00 R0 0_J 00 R 0_J 00 R 0_J 00 R 0_J 00 R 0_J 00 R 0_J 00 (esign check.0) 00.. No tuff. ± % pull-down to N near Intel MVP controller for testing purposes. 0.U_V_M_ 00 R 0_J U_V_M_ 00 VI0 VI VI VI VI VI VI VHOR +_VRUN R 00_F 00 R 00_F 00 0.U_V_M_ 00 0 mil LYOUT NOT: Place 0.0uF near PIN VN VN 00 mil 0.U_V_M_ 00 0.U_V_M_ 00 +_0VRUN P move from page fix P location,but change P val from N_U to 0U + FX0R 0U_V_T P M0 check U V[00] V[00] V[00] V[00] V[00] V[00] V[00] F V[00] V[00] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] F V[0] F V[0] F V[0] F V[0] F V[0] F V[0] F V[00] F V[0] F V[0] V[0] V[0] V[0] V[0] H V[0] H V[0] H V[0] H V[00] J V[0] J V[0] J V[0] J V[0] K V[0] K V[0] K V[0] K V[0] L V[0] L V[00] L V[0] L V[0] M V[0] M V[0] M V[0] M V[0] N V[0] N V[0] N V[0] N V[00] P V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] PU OKT_P FOX_PZ-M-0 P P P R R R R T T T T U U U U V V V V W W W W Y Y Y Y F F F F F F F F 0 N_0.U_V_M_ 00 N_0.U_V_M_ 00 N_0.U_V_M_ P_0V_K_ P_0V_K_ P_0V_K_ 00 FOXONN Merom(POWR/N) HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of

7 +_0VRUN +_0VRUN R0 00_F 00 R0._F 00 R0._F 00 +_0VRUN R0 _F 00 R0._F 00 W/ = 0/0mil H_WIN 0.U_V_M_ 00 W/ = 0/0mil H_ROMP H_OMP H_OMP# ifferent with PM ifferent with PM +_0VRUN R0 K_F 00 R00 K_F 00 H_#[..0] H_#[..0] ifferent with PM H_PURT# H_PULP# Place ap. near MH within 00 mils. 0.U_0V_K 00_XR H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_WIN H_ROMP H_OMP H_OMP# TP MIL R0 0_J 00 H_VRF H_VRF M H H F N H M0 N N H P K M W0 Y V M J N N W W N Y Y P W N Y J H J H J H J J J J H H U H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_WIN H_ROMP W H_OMP W H_OMP# H_PURT# H_PULP# H_VRF H_VRF 0 mil HOT restline MH-QN_ -RTL-0 H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# J M F L K L J K P R H0 L M N J N H_# H_T#0 H H_T# 0 H_NR# H_PRI# H_RQ# F H_FR# H_Y# HPLL_LK HPLL_LK# H_PWR# H_RY# H_HIT# H_HITM# H_LOK# H_TRY# H_INV#0 H_INV# H_INV# H_INV# H_TN#0 H_TN# H_TN# H_TN# H_TP#0 H_TP# H_TP# H_TP# 0 M M H K 0 K L M K H L K J0 H_RQ#0 M H_RQ# H_RQ# H_RQ# H H_RQ# H_R#0 H_R# H_R# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_INV#0 H_INV# H_INV# H_INV# H_TN#0 H_TN# H_TN# H_TN# H_TP#0 H_TP# H_TP# H_TP# H_RQ#0 H_RQ# H_RQ# H_RQ# H_RQ# H_R#0 H_R# H_R# dd H_#[..] H_# H_T#0 H_T# H_NR# H_PRI# H_RQ#0 H_FR# H_Y# LK_MH_LK LK_MH_LK# H_PWR# H_RY# H_#[..] H_HIT# H_HITM# H_LOK# H_TRY# H_INV#[..0] H_TN#[..0] H_TP#[..0] H_RQ#[..0] H_R#[..0] FOXONN restline (HOT)/ HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of

8 U F[:0] 00 = F 00 MHz 0 = F MHz +VRUN 0, R_LRT# R 0_J Form (U)thermal sanser & () 00 For layout convenience Wait to confirm with Page / R esign check.0 R onnect to PM_XT_T#0/ pins of MH, pull up with 0K to Vcc_ PM_XTT# PM_XTT#0 PM_XTT#0 TP MIL TP MIL TP MIL TP MIL TP MIL TP0 MIL TP MIL TP MIL TP MIL TP MIL TP0 MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP00 MIL TP0 MIL TP0 MIL TP0 MIL TP0 MIL R YTM MM TP0 MIL M0 /R, M, M TP0 MIL TP0 MIL TP0 MIL LV TP MIL M0 /R TP MIL TP0 MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL MH_F_ (PI Low = Reverse Lane raphics High = Normal Lane) operation R0 R0 MH_L0 MH_L MH_L TP MIL TP MIL TP0 MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP0 MIL TP MIL TP MIL TP MIL TP MIL TP MIL 0 PM_MUY#,, H_PRTP# PM_XTT#0 PM_XTT# 0, IMVP_PWR,,,,,,,,, PLT_RT# PM_THRMTRIP# 0, PRLPVR 0K_J 00 0K_J 00 MH_F_ MH_F_ MH_F_ MH_F_ MH_F_ MH_F_ MH_F_ MH_F_0 MH_F_ MH_F_ MH_F_ MH_F_ MH_F_ MH_F_ MH_F_ MH_F_ MH_F_ MH_F_0 R0 00_J 00 TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP0 MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL MH_RV_ MH_RV_ MH_RV_ MH_RV_ MH_RV_ MH_RV_ MH_RV_ MH_RV_ MH_RV_ MH_RV_0 MH_RV_ MH_RV_ MH_RV_ MH_RV_ MH_RV_0 MH_RV_ MH_RV_ MH_RV_ MH_RV_ MH_RV_ MH_RV_ MH_RV_ MH_RV_ MH_RV_ MH_RV_0 MH_RV_ M M MH_RV_ MH_RV_ MH_RV_ M_O_RXIN- M_O_RXIN+ MH_RV_ MH_RV_0 MH_RV_ MH_RV_ MH_RV_ MH_RV_ MH_RV_ PLTRT#_R PM_THRMTRIP# MH_N MH_N MH_N MH_N MH_N MH_N MH_N MH_N MH_N MH_N0 MH_N MH_N MH_N MH_N MH_N MH_N P P R N R R M N J R M L M 0 H0 J0 K F H0 K J F J H W0 K0 P F0 N F N F F F F F N F F J0 F 0 F R F0 L F J F F 0 F K F M0 F M F L F N F L F0 N0 RV RV RV RV RV RV RV RV RV RV0 RV RV RV RV RV0 RV RV RV RV RV RV RV RV RV RV0 RV _M _M RV RV RV LV_T# LV_T RV RV0 RV RV RV RV RV F[:] internal pull-up F[0:] internal pull-down PM_M_UY# L PM_PRTP# L PM_XT_T#0 J PM_XT_T# W PWROK V0 RTIN# THRMTRIP# PRLPVR J N K N K0 N L0 N L N L N L N K N J N N0 N N 0 N 0 N N K N restline MH-QN_ RV R MUXIN LK F MI RPHI VI PM M N MI M_K0 V M_K M_K M_K V M_K#0 W0 M_K# M_K# W M_K# W M_K0 M_K M_K M_K M_#0 M_# M_# M_# M_OT0 M_OT M_OT M_OT M_ROMP M_ROMP# M_ROMP_VOH M_ROMP_VOL M_VRF0 M_VRF PLL_RF_LK PLL_RF_LK# PLL_RF_LK PLL_RF_LK# P_LK P_LK# MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP FX_VI0 FX_VI FX_VI FX_VI FX_VR_N L_LK L_T L_PWROK L_RT# L_VRF VO_TRL_LK VO_TRL_T LKRQ# IH_YN# Y 0 K H J J L K K L R W H H K K N J N N M J N N J J M0 M J J M M M K0 T N M0 H K 0 TT TT R M_ROMP M_ROMP# M_ROMP_VOH M_ROMP_VOL MR_VRF RFLK RFLK# RFLK RFLK# MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP FT_VI_0 FT_VI_ FT_VI_ FT_VI_ FT_VR_N MH_LVRF VO_TRLLK VO_TRLT MH_LK_RQ# MH_TT_ MH_TT_ R0 0_F 00 R0 0_F 00 LK_MH_PLL LK_MH_PLL# MI_TXN[:0] MI_TXP[:0] MI_RXN[:0] MI_RXP[:0] R0 0K_J 00 MIL TP MIL TP MIL TP MIL TP MIL TP MH_LK_RQ# R0 0_J 00 M_LK_R0 M_LK_R M_LK_R M_LK_R M_LK_R#0 M_LK_R# M_LK_R# M_LK_R# M_K0, M_K, M_K, M_K, M_#0, M_#, M_#, M_#, +_VU L_LK0 0 L_T0 0 MPWROK 0 L_RT#0 0 M_OT0, M_OT, M_OT, M_OT, R0 NV_0_J 00 R00 NV_0_J 00 MH_LK_RQ# MH_IH_YN# 0 MIL TP R0 waiting change 0.% K_F 00 R0 waiting change 0.% K_F 00 Note:If the voltage regulator for the system memory interface already supplies a VRF output and meets the voltage tolerance and current requirements for these pins, then a voltage divider would not be needed. xternal raphics (MH RT/TVOUT isable) FOXONN +_VU RIMM_VRF R0.0K_F 00 R0 0_J 00 0.U_V_M_ 00 R0 NV_0_J 00 +_VRUN 0.U_0V_K 00_XR R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 restline (MI)/ 0.0U_V_K_ 00 MR_VRF R0 K_F 00 R0 _F 00 RFLK RFLK# RFLK RFLK# HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of 0.0U_V_K_ 00 0.U_V_M_ 00 M_ROMP_VOH.U_0V_Y 00_YV M_ROMP_VOL.U_0V_Y 00_YV

9 TYP is open drawn(output) heck list.k to.v M0.KK to.v R.KK to.v +VRUN 0/ hange N to stuff TP MIL TP MIL heck List=.K R=.K M0=.K R TP MIL N_.K_F 00 TP MIL R N_.K_J 00 +VRUN R N_.K_J 00 L_KLT_TRL L_KLT_N L_TRL_LK L_TRL_T L LK L T L_V_N L_I L_V R0 N_0_J 00 R0 N_0_J 00 M_ M_ M_ TV_ONL0 TV_ONL M_LU M_RN M_R M_LK M_T M_HYN_R RT_IRF M_VYN_R 0/ F suggest N to N TV_ONL0 TV_ONL U J0 L_KLT_TRL H L_KLT_N L_TRL_LK 0 L_TRL_T L LK L T K0 L_V_N L LV_I L LV_V N LV_VRFH N0 LV_VRFL LV_LK# LV_LK F K F J L M P LV_LK# LV_LK LV_T#0 LV_T# LV_T# 0 LV_T0 0 LV_T F LV_T LV_T#0 LV_T# LV_T# LV_T0 LV_T LV_T TV_ TV_ TV_ TV_RTN TV_RTN TV_RTN TV_ONL0 TV_ONL H RT_LU RT_LU# K RT_RN J RT_RN# F RT_R RT_R# K RT LK RT T F RT_HYN RT_TVO_IRF RT_VYN LV PI-XPR RPHI TV V P_OMPI P_OMPO N M P_OMP P_RXN0 P_RX#0 J P_RXN P_RX# L P_RXN P_RX# N P_RXN P_RX# T P_RXN P_RX# T0 P_RXN P_RX# U0 P_RXN P_RX# Y P_RXN P_RX# Y0 P_RXN P_RX# P_RXN P_RX# W P_RXN0 P_RX#0 P_RXN P_RX# 0 P_RXN P_RX# P_RXN P_RX# H P_RXN P_RX# P_RXN P_RX# J0 P_RXP0 P_RX0 L0 P_RXP P_RX M P_RXP P_RX U P_RXP P_RX T P_RXP P_RX T P_RXP P_RX W P_RXP P_RX W P_RXP P_RX 0 P_RXP P_RX Y P_RXP P_RX P_RXP0 P_RX0 P_RXP P_RX H P_RXP P_RX P_RXP P_RX H P_RXP P_RX P_RXP P_RX P_TXN0 P_TX#0 N P_TXN P_TX# U P_TXN P_TX# U P_TXN P_TX# N P_TXN P_TX# R0 P_TXN P_TX# T P_TXN P_TX# Y W P_TXN P_TX# W P_TXN P_TX# P_TXN P_TX# P_TXN0 P_TX#0 P_TXN P_TX# P_TXN P_TX# H P_TXN P_TX# P_TXN P_TX# H P_TXN P_TX# P_TX0 P_TX P_TX P_TX P_TX P_TX P_TX P_TX P_TX P_TX P_TX0 P_TX P_TX P_TX P_TX P_TX M T T N0 R U W Y Y 0 0 H P_TXP0 P_TXP P_TXP P_TXP P_TXP P_TXP P_TXP P_TXP P_TXP P_TXP P_TXP0 P_TXP P_TXP P_TXP P_TXP P_TXP +V_P R._F 00 (source)+_0vrun 00 NV_0.U_V_M_ P_RXN[..0] P_TXN0 00 P_RXN_0 0 NV_0.U_V_M_ P_TXN 00 P_RXN_ 0 NV_0.U_V_M_ P_TXN 00 P_RXN_ 0 NV_0.U_V_M_ P_TXN 00 P_RXN_ 0 NV_0.U_V_M_ P_TXN 00 P_RXN_ 0 NV_0.U_V_M_ P_TXN 00 P_RXN_ 0 NV_0.U_V_M_ P_TXN 00 P_RXN_ 0 NV_0.U_V_M_ P_TXN 00 P_RXN_ 0 NV_0.U_V_M_ P_TXN 00 P_RXN_ P_RXP[..0] 0 NV_0.U_V_M_ P_TXN 00 P_RXN_ 0 NV_0.U_V_M_ P_TXN0 00 P_RXN_0 NV_0.U_V_M_ P_TXN 00 P_RXN_ NV_0.U_V_M_ P_TXN 00 P_RXN_ NV_0.U_V_M_ P_TXN 00 P_RXN_ NV_0.U_V_M_ P_TXN 00 P_RXN_ NV_0.U_V_M_ P_TXN 00 P_RXN_ NV_0.U_V_M_ P_TXP0 00 P_RXP_0 NV_0.U_V_M_ P_TXP 00 P_RXP_ NV_0.U_V_M_ P_TXP 00 P_RXP_ NV_0.U_V_M_ P_TXP 00 P_RXP_ 0 NV_0.U_V_M_ P_TXP 00 P_RXP_ NV_0.U_V_M_ P_TXP 00 P_RXP_ NV_0.U_V_M_ P_TXP 00 P_RXP_ NV_0.U_V_M_ P_TXP 00 P_RXP_ NV_0.U_V_M_ P_TXP 00 P_RXP_ NV_0.U_V_M_ P_TXP 00 P_RXP_ NV_0.U_V_M_ P_TXP0 00 P_RXP_0 NV_0.U_V_M_ P_TXP 00 P_RXP_ NV_0.U_V_M_ P_TXP 00 P_RXP_ NV_0.U_V_M_ P_TXP 00 P_RXP_ 0 NV_0.U_V_M_ P_TXP 00 P_RXP_ NV_0.U_V_M_ P_TXP 00 P_RXP_ P_RXN_[..0] P_RXP_[..0] restline MH-QN_ xternal raphics (MH RT/TVOUT isable) R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 M_LU M_RN M_R RT_IRF M_ M_ M_ R0 NV_0_J 00 R0 NV_0_J 00 R00 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R00 NV_0_J 00 R0 NV_0_J 00 M_HYN_R M_VYN_R M_LK M_T L LK L T TV_ONL0 TV_ONL L_TRL_LK ase on below document: Mobile Merom Processor and restline hipset - anta Rosa Platform esign uide-,.0.pvd.pdf (May 00/ Rev.0)page Table. xternal raphics (MH Integrated raphics isable) onnect these signals to N R0 NV_0_J 00 L_TRL_T FOXONN restline(rphi)/ HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of

10 restline add page restline add page (M0--0 )Mainoard (MX-) restline(rii)/ 0 Friday, ugust, 00 ize ocument Number Rev ate: heet of HON HI PRIION IN. O., LT. P - R& ivision FOXONN M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q0 M Q M Q M Q M M0 M M M M M M M M M M M M M M M M Q M Q M Q M Q M Q M Q M Q M Q0 M M M M M M M 0 M M 0 M M M M M Q# M Q# M Q# M Q# M Q# M Q# M Q# M Q#0 _RVN# M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q# M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M M0 M M M M M M M M M M M M M M M Q0 M Q M Q M Q M Q M Q M Q M 0 M M M M M M M M M M 0 M M M M Q _RVN# TP MIL R YTM MMORY U restline MH-QN_ P R 0 Y F0 F J0 J J L W0 K K K K J L J J K J0 W L K K K N J0 L K L K K0 J J F H N0 K J R T V0 Y Y U T V 0 0 Y R0 K L H J F W T0 0 K K J L V U0 0 L K K K F V W F Y V Y _Q0 _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _0 _# _M0 _M _M _M _M _M _M _M _Q0 _Q _Q _Q _Q _Q _Q _Q _Q#0 _Q# _Q# _Q# _Q# _Q# _Q# _Q# _M0 _M _M0 _M _M _M _M _M _M _M _M _M _M _M _R# _RVN# _W# R YTM MMORY U restline MH-QN_ R W J 0 H W 0 F H 0 F0 R0 W0 T W W Y Y V T V T W V U T R 0 0 Y 0 W Y R T T Y R R R N M N0 T T N M N W F K F L T W W Y T H P N T H P J 0 0 J K H L K J J L Y0 _Q0 _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _0 _# _M0 _M _M _M _M _M _M _Q0 _Q _Q _Q _Q _Q _Q _Q _M _Q#0 _Q# _Q# _Q# _Q# _Q# _Q# _Q# _M0 _M _M0 _M _M _M _M _M _M _M _M _M _M _M _R# _RVN# _W# TP0 MIL M Q[..0] M Q[..0] M Q#[..0] M #, M, M, M 0, M M[..0] M [..0], M R#, M W#, M Q[..0] M Q[..0] M Q#[..0] M 0, M, M, M #, M M[..0] M [..0], M R#, M W#,

11 +_VRUN V.M_MH_PLL +_VRUN +_VRUN +V._PPLL_R 00_XR 0U_.V_M R0 0_J 00 L 0R-00MHZ_00 H0KF-T0 L 0R-00MHZ_00 H0KF-T0 00 U_.V_M_ R _F 0 0.0U_V_M 0U_0V_M 0.U_V_M_ 00_XR 00_XR 00 R00 _F 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J U_.V_M_ LLMPN 0R-00MHZ_00 +V.RUN HPLL +V.RUN MPLL +VRUN_YN +VRUN RT +V.RUN +V.RUN PLL +V.RUN PLL +V._TXLV +V._LV +V._Q m 0m 0m NFMR L_FILTR +V._TV +V._RT +V._TV +V._TV +V._TV 00_XR 0.U_0V_K / backup for MI request close to P +_VRUN +V._PPLL 0 00_XR 0.U_0V_K 0.U_V_M_ 00 N_0.U_0V_K 00_XR +VRUN +V._PPLL +_VRUN 00 U_.V_M_ + P 00U_.V_ FX0J0R V.M_MH_PLL 0.U_0V_K 00_XR 00 0 U_.V_Y_Y 00 U_.V_M_ +VRUN_YN +VRUN RT +V.RUN +V.RUN PLL +V.RUN PLL +V.RUN HPLL +V.RUN MPLL +V._TXLV +V._PPLL 00 U_.V_Y_Y 0.U_0V_K 00_XR 00 U_.V_M_ 0.U_0V_K 0 00_XR 0.U_0V_K 00_XR 00 U_.V_Y_Y +V._TV +V._TV +V._TV +V._RT +V._TV +V._Q 0m 00m +V._LV 00_XR.U_.V_K J 0 H L M K0 K U W V U U U T T R R N N U UH +VRUN V_YN V_RT_ V_RT_ V V V_PLL V_PLL V_HPLL V_MPLL V_LV V_LV V_P_ V_P_ V_P_PLL V_M V_M V_M V_M V_M T V_M T V_M T V_M V_M0 V_M V_M_NTF V_M_NTF V_M_K V_M_K V_TV_ V_TV_ V_TV_ V_TV_ V_TV_ V_TV_ M V_RT L V_TV V_Q V_HPLL V_P_PLL J V_LV H V_LV +_0VRUN RT PLL K M P LV POWR TV TV/RT LV restline MH-QN_ R0 0_J 00 X XF M K MI 00V-0-LF 0 P R0 0_J 00 VTT HV VTTLF +V._HV VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 VTT VTT U U U U U U U U U U T T T0 T T T T T T R R R V_X T V_X U V_X U V_X T V_X T V_X T0 V_X_NTF V_XF V_XF V_XF V_MI V_M_K V_M_K V_M_K V_M_K V_TX_LV V_HV V_HV R J0 K K J J 0 0 V_P V_P W0 V_P W V_P V V_P V0 V_RXR_MI V_RXR_MI VTTLF VTTLF VTTLF H0 H F H +V._HV VTTLF_P VTTLF_P VTTLF_P 00 0.U_.V_Y_Y 0m 0.U_.V_K 00_XR 00m 0 U_.V_Y_Y 00 0.U_0V_K 00_XR 00 0.U_.V_Y_Y 0m 00m 00m +V._TXLV 00m 0m 00 0.U_.V_Y_Y 0U_.V_M 00_XR 0U_.V_M 00_XR 0.U_.V_K 00_XR U_0V_Y 0_YV 0.U_0V_K 00_XR +_VRUN U_.V_Y_Y 00 +V_P 0.U_0V_Y_Y 00 +_VRUN 0.U_0V_K 00_XR 0.U_0V_K 00_XR P + 0U_.V_ TP0MI +V_MI +V_P R00 00 N_0_J To connect the P & MI to same rail (V_P) tuff R and Remove, P, L FOXONN 0 0.U_.V_Y_Y 00 +_VRUN 00 U_.V_M_ 0.U_0V_K 00_XR L 0.0UH_00 WF0-0NM-L0 +_0VRUN P + 0U_V_ FL0Y +V._M_K +_VU L U_00 L0-R0M 0. R0 _F 00 +V_MI L0.0UH_00 WF0-0NM-L0 P 0U_.V_M + 0U_.V_ 00_XR TP0MI 0U_.V_M 00_XR +_0VRUN +_0VRUN restline(powr,v)/ N_0.U_0V_K 00_XR / backup for MI request close to L HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of

12 Note: ll VM pins shorted internally. Place on the dge. Place where LV and R taps. avity apacitors Place on the dge. avity apacitors 0 mils from the dge.... (M0--0 )Mainoard (MX-) restline(v OR)/ Friday, ugust, 00 ize ocument Number Rev ate: heet of HON HI PRIION IN. O., LT. P - R& ivision FOXONN +_0VRUN +_VU +_VU +_0VRUN +_0VRUN +_0VRUN V_X V_X 0.U_0V_K 00_XR N_0.U_V_Y_Y 00 U_.V_M_ 00 0.U_0V_K 00_XR POWR V OR V M V FX V FX NTF V M LF U restline MH-QN_ K J J H H H F T F J W Y U F H H H J J U K K K K U U U0 U U U V V V V0 T V V V Y Y Y Y Y0 Y Y T Y Y Y Y T F F H H H H T J J J K K L L L L0 L T L M M M M M P P P T P P0 P U U L V W T T U R0 T W W Y F F H0 H H H P P R0 R R R R R0 H J0 N W W T H M0 U0 V V V Y V V V V V V0 V V V V V_M0 V_M0 V_M0 V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_X_NTF0 V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF0 V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF0 V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF0 V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF0 V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF0 V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF0 V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_M V_M V_M V_X_NTF V V_M V_X V_X V_X V_X V_X V_X V_X V_X V_X V_X0 V_X V_X V_X V_X V_X V_X V_X V_X V_X V_X0 V_X V_X V_X V_X V_X V_X V_X V_X V_X0 V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V V_X V_X V_X V_M_LF V_M_LF V_M_LF V_M_LF V_M_LF V_M_LF V_M_LF V_X V_X V V_X_NTF V_M V_X_NTF0 V_X_NTF V_X_NTF V_X_NTF 0.U_0V_K 00_XR U_.V_M_ 00 0 U_.V_M_ 00 R0 0_J U_.V_Y_Y U_0V_Y_Y 00 + N_0U_V_T P FX0R + P 0U_.V_ RTP0M 0.U_0V_K 00_XR 0.U_0V_K 00_XR U_.V_M_ 00 0.U_0V_Y_Y U_0V_Y_Y 00 0.U_0V_K 00_XR POWR V NTF V NTF V V XM V XM NTF UF restline MH-QN_ K P U F F H H H H J K K K L L P R R T0 T T U U U U U V V V T T U U V V F K M P R R R Y K K J J L L L M M M M P P R Y Y Y Y L L J F J K L L L M M M M P P P R R T T V V_NTF V_NTF0 V_NTF V_NTF V_NTF V_NTF0 V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF0 V_NTF V_NTF V_NTF V_NTF V_NTF0 V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF0 V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF0 V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF0 V_NTF V_NTF V_XM V_XM V_XM V_XM V_XM_NTF V_XM_NTF V_XM_NTF V_XM_NTF V_XM_NTF V_XM_NTF V_XM_NTF V_XM_NTF0 V_XM_NTF V_XM_NTF V_NTF V_NTF V_NTF V_NTF V_ V_ V_ V_ V_ V_ V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_XM V_XM_NTF V_XM_NTF V_XM_NTF V_NTF V_XM_NTF V_XM_NTF V_NTF V_NTF V_XM_NTF V_XM_NTF V_XM_NTF V_XM_NTF V_XM V_XM V_NTF 0.U_0V_Y_Y 00 R0 0_J 00 0.U_0V_Y_Y 00 0.U_0V_Y_Y 00 U_.V_M_ 00 0 U_.V_M_ 00 0.U_0V_K 00_XR

13 (M0--0 )Mainoard (MX-) restline (V)/ Friday, ugust, 00 ize ocument Number Rev ate: heet of HON HI PRIION IN. O., LT. P - R& ivision FOXONN V UJ restline MH-QN_ 0 0 F F F F0 F0 H H H H J J J J J J J J K K K L L L0 L L L L L M M M M M M0 M N N N N N N N N N N P P P P P0 R T T T U U U0 W W W W W W Y Y Y V V Y Y Y Y0 Y P T T T R F F T V H0 V V00 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V0 V V V V V V V V V V V V00 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V V V V UI restline MH-QN_ F0 F F F 0 H H0 H H H J J J J J J J J J K0 K K K K K L M M M M M M N N N N N N P P P0 R R R R R R T0 T T T W W W W W W Y0 Y Y Y Y Y Y Y F F F H H0 H H H J J J J J J K K K K U U U U U U U V V W W K K K L L K0 K L L L L V V V V V V V V V V V0 V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V00 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V V V0 V V V V V V V V V0 V V V V V V V V V V V V V V V0 V V V

14 0.U_V_M_ µf and. µf placed close to VRF pins,,,0, M_T_U,,0, M_LK_U +VRUN R_VRF.U_0V_Y_Y 00 M_K0 0, M R_VRF M Q0 M Q M Q#0 M Q0 M Q M Q M Q M Q M Q# M Q M Q0 M Q M Q M Q M Q# M Q M Q M Q M Q M Q M M M Q M Q M M M M M M M 0 M M M Q M Q M Q M Q M Q# M Q M Q0 M Q M Q M Q M M M Q M Q +_VU 0.U_V_M_ IMM_0 P00 R RM O-IMM N (00P) +_VU M M M 0 Place IMM_0 near MH.V per IMM=.0 M Q M Q M M0 M Q M Q M Q M Q M M M Q M Q M Q0 M Q R_XTT#0 M M M Q M Q M Q M Q M Q# M Q M Q0 M Q R_M M M M M Q# M Q M Q M Q M Q M Q M M M Q M Q M Q0 M Q M Q# M Q M Q M Q 0_IM0 _IM0 R 0_J 00 R0 0_J 00 0, M 0 0 R# M R# 0, 0, M W# 0 W# 0# 0 M_#0, V V 0, M # # OT0 M_OT0, M, M_# # V V, M_OT OT N 0 M Q V V M Q M Q Q Q M Q Q Q M Q# V V 0 M M M Q Q# M Q V M Q M Q V Q M Q M Q Q Q Q V 0 M Q M Q0 V Q M Q M Q Q0 Q 0.U_0V_Y_Y 00 VRF V Q0 Q V Q#0 Q0 V Q Q V Q Q V Q# Q V Q0 Q V0 V Q Q V Q# Q V Q Q V Q Q V M N V Q Q V K0 V N _ V V V0 0/P Q V M V Q Q V0 Q Q V NTT V0 Q# Q V Q0 Q 0 0 V Q Q V M V Q Q V L V(P) MFIX MFIX NPTH NPTH 0 0 V Q Q V M0 V Q Q V Q Q V M V K0 K0# V Q Q V V0 Q0 Q V N M V Q Q V Q Q V Q# Q V0 Q0 Q V K V V V 0 V V Q# Q V Q Q V Q Q V K K# V M V Q Q V Q0 Q V Q# Q V Q Q V R 0K_J 00 R 0K_J 00 R O-IMM_00P FOX_0_NR_F Mus ddress: 0(W)/(R) M_LK_R0 M_LK_R#0 M_K, M 0, M_LK_R M_LK_R# PM_XTT#0 M, Place these aps near o-imm0..u_0v_y_y 00 Place these aps near o-imm0. R_VRF (0 mil).u_0v_y_y 00 0.U_V_Y_Y 00 M M[0..] 0 M Q[0..] 0 M Q[0..] 0 M Q#[0..] 0 M [0..] 0, R_VRF 0.U_V_M_ 00.U_0V_Y_Y U_V_Y_Y 00 RIMM_VRF FOXONN R 0_J 00 R(II)O-IMM_0 ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of +_VU.U_0V_Y_Y 00 0.U_V_Y_Y 00.U_0V_Y_Y 00 +_VU 0.U_V_Y_Y 00 HON HI PRIION IN. O., LT. P - R& ivision

15 0.U_V_M_ 00 R_VRF 0.U_V_M_ µf and. µf placed close to VRF pins, / N.U_0V_Y_Y 00 0, M, M_K 0, M 0 0, M W# 0, M #, M_# M_OT,,0, M_T_U,,0, M_LK_U +VRUN 0 N_.U_0V_Y_Y 00 M Q0 M Q M Q#0 M Q0 M Q M Q M Q M Q M Q# M Q M Q0 M Q M Q M Q M Q# M Q M Q M Q M Q M Q M M M Q M Q M M M M M M M 0 M Q M Q M Q# M Q M Q M Q M Q0 M Q M M M Q M Q M Q M Q M Q# M Q M Q0 M Q M Q M Q M M M Q M Q 0.U_V_M_ 00 +_VU N VRF V Q0 Q V Q#0 Q0 V Q Q V Q Q V Q# Q V Q0 Q V0 V Q Q V Q# Q V Q Q V Q Q V M N V Q Q V K0 V N _ V V V0 0/P 0 W# V # # V OT V Q Q V Q# Q V Q Q V Q0 Q V M V Q Q V0 Q Q V NTT V0 Q# Q V Q0 Q IMM_ 0 0 V Q Q V M V Q Q V L V(P) MFIX MFIX P00 R RM O-IMM NPTH NPTH 0 0 V Q Q V M0 V Q Q V Q Q V M V K0 K0# V Q Q V V0 Q0 Q V N M V Q Q V Q Q V Q# Q V0 Q0 Q V K V V (00P) V 0 V R# 0# V OT0 V N V Q Q V M V Q Q V Q Q V Q# Q V Q Q V Q Q V K K# V M V Q Q V Q0 Q V Q# Q V Q Q V _VU.V per IMM=.0 M Q M Q M M0 M Q M Q M Q M Q M M M Q M Q M Q0 M Q R_XTT# M M M Q M Q M Q M Q M Q# M Q M Q0 M Q R_M M M M M M M 0 M M Q M Q M M M Q M Q M Q M Q M Q# M Q M Q M Q M Q M Q M M M Q M Q M Q0 M Q M Q# M Q M Q M Q 0_IM _IM R 0-IMM_00P FOX_0_N_F R R M_LK_R M_LK_R# 0/ wap strob,strob R 0_J 00 hange net name from PM_XTT#_L to R_XTT# 0/ wap strob,strob 0K_J K_J M_K, R0 0_J 00 M 0, M R# 0, M_#, M_OT, M_LK_R M_LK_R# +VRUN Mus ddress: (W)/(R) IMM_ is placed farther from the MH than IMM_0 PM_XTT# M, Place these aps near o-imm..u_0v_y_y 00.U_0V_Y_Y 00 Place these aps near o-imm. 0.U_V_Y_Y 00 FOXONN R(II)O-IMM_ ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of.u_0v_y_y 00 0.U_V_Y_Y 00 M M[0..] 0 M Q[0..] 0 M Q[0..] 0 M Q#[0..] 0 M [0..] 0,.U_0V_Y_Y 00 +_VU 0.U_0V_Y_Y 00 +_VU 0.U_V_Y_Y 00 0.U_V_Y_Y 00 HON HI PRIION IN. O., LT. P - R& ivision

16 +0_VU, M, M R 00 _J R 00 _J 0, M R# 0, M M M RP 00_PR RP 00_PR M M RP 00_PR M M RP 00_PR +0_VU 0, M 0 0, M W# 0, M # M 0 M M RP 00_PR RP 00_PR RP 00_PR 0, M [0..] M M RP 00_PR +0_VU 0, M [0..], M_OT M 0 M M RP0 00_PR RP 00_PR +0_VU M M RP 00_PR +0_VU 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 Layout note: Place cap close to every R-pack terminated to +0_VU 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0, M R# 0, M M M RP 00_PR RP 00_PR +0_VU, M_OT0 0, M M M RP 00_PR RP 00_PR +0_VU 0 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 M M M M RP 00_PR RP 00_PR Layout note: Place cap close to every R-pack terminated to +0_VU 0, M 0 0, M W# 0, M # M 0 M 0 M RP 00_PR RP0 00_PR RP 00_PR +0_VU,,,, M_K0 M_K M_K M_K R R R R 00 _J 00 _J 00 _J 00 _J +0_VU +0_VU +0_VU R 00 _J R 00 _J, M_#0, M_OT,,, M_# M_# M_# R R R0 00 _J 00 _J 00 _J, M_OT 0, M M R 00 _J R 00 _J R 00 _J FOXONN R(II)Termination HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of

17 P_RXN[0..] TXN[0..] +VRUN P_RXP[0..] P_RXP0 P_RXP TXP0 NV_0.U_V_M_ 00 TXP NV_0.U_V_M_ 00 TXP[0..] P_RXN0 TXN0 NV_0.U_V_M_ 00 P_RXN TXN NV_0.U_V_M_ 00 P_RXN TXN 0 NV_0.U_V_M_ 00 NX trap for R-ball 000 MxInfineon 000 MxHynix 00 Mxamsung 00 MxInfineon 00 MxHynix 0 Mxamsung RM_F0 RM_F RM_F RM_F MIO0 R0 NVH_K_J 00 R0 NVI_K_J 00 MIO R0 NVI_K_J 00 R0 NVH_K_J 00 MIO R0 NV_K_J 00 R0 NV_K_J 00 MIO R0 NV_K_J 00 R0 N_K_J 00 P_RXP P_RXP P_RXP P_RXP TXP NV_0.U_V_M_ 00 P_RXN TXN NV_0.U_V_M_ 00 U_VNOR UVNOR MIO TXP 0 (U YTM IO) R NV_K_J 00 NV_0.U_V_M_ 00 P_RXN TXN (U XTRNL ROM) NV_0.U_V_M_ 00 TXP NV_0.U_V_M_ 00 TXP NV_0.U_V_M_ 00 P_RXN TXN NV_0.U_V_M_ 00 P_RXN TXN NV_0.U_V_M_ 00 MIO0 is used to set the PI xpress PLL termination enable. FULT "0" PX_PLL_N_TRM MIO0 R NV_K_J 00 MIO MIO0 P_RXP TXP NV_0.U_V_M_ 00 P_RXN TXN 00 NV_0.U_V_M_ 00 P_RXP TXP NV_0.U_V_M_ 00 P_RXP TXP 0 NV_0.U_V_M_ 00 P_RXP TXP 0 NV_0.U_V_M_ 00 P_RXP0 TXP0 0 NV_0.U_V_M_ 00 P_RXP TXP 0 NV_0.U_V_M_ 00 P_RXP TXP 0 NV_0.U_V_M_ 00 P_RXP TXP NV_0.U_V_M_ 00 P_RXP TXP NV_0.U_V_M_ 00 P_RXP TXP NV_0.U_V_M_ 00 P_RXN TXN 0 NV_0.U_V_M_ 00 P_RXN TXN 0 NV_0.U_V_M_ 00 P_RXN0 TXN0 0 NV_0.U_V_M_ 00 P_RXN TXN 0 NV_0.U_V_M_ 00 P_RXN TXN 0 NV_0.U_V_M_ 00 P_RXN TXN NV_0.U_V_M_ 00 P_RXN TXN NV_0.U_V_M_ 00 P_RXN TXN NV_0.U_V_M_ 00 NX IO_PF[:0] 000 NM-T evice I setting mismatch between VIO and H/W traps hange R value from N_ to NVMH_ hange R value from NV_ to NVP_ NX PI_VI[:0] NP- X0 "X" NM-T X00 "X" IO_PF0 IO_PF IO_PF IO_PF PI_VI 0 PI_VI PI_VI PI_VI PI_VI MIO R N_K_J 00 MIO R NV_K_J 00 MIO R NV_K_J 00 MIO_HYN R NV_K_J 00 R N_K_J 00 MIO R NVM_K_J 00 MIO R N_K_J 00 MIO R N_K_J 00 MIO R NV_K_J 00 MIO_TL R N_K_J 00 R NV_K_J 00 R N_K_J 00 R0 N_K_J 00 R NVP_K_J 00 R NV_K_J 00 R NV_K_J 00 R N_K_J 00 R N_K_J 00 MIO MIO MIO MIO0 MIO MIO MIO MIO MIO MIO MIO MIO_TL MIO_HYN MIO MIO MIO MIO0 MIO MIO MIO MIO MIO MIO MIO MIO_TL MIO_HYN RYTL(NX) 0 (M Hz) (Reserved) RYTL MIO R NV_K_J 00 MIO FOXONN V (PI-XPR/TRP) OF HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of

18 +VRUN R0 N_0_J 00 R0 +VRUN,,,,,,,,, TXP[0..] TXN[0..] P_RXP_[0..] P_RXN_[0..] PLT_RT# NV_0K_J 00 TXP0 TXP TXP TXP TXP TXP TXP TXP TXP TXP TXP0 TXP TXP TXP TXP TXP TXN0 TXN TXN TXN TXN TXN TXN TXN TXN TXN TXN0 TXN TXN TXN TXN TXN P_RXP_0 P_RXP_ P_RXP_ P_RXP_ P_RXP_ P_RXP_ P_RXP_ P_RXP_ P_RXP_ P_RXP_ P_RXP_0 P_RXP_ P_RXP_ P_RXP_ P_RXP_ P_RXP_ P_RXN_0 P_RXN_ P_RXN_ P_RXN_ P_RXN_ P_RXN_ P_RXN_ P_RXN_ P_RXN_ P_RXN_ P_RXN_0 P_RXN_ P_RXN_ P_RXN_ P_RXN_ P_RXN_ U NV_H0W LK_PI_P LK_PI_P# 00MHz R0 NV J 00 LK_PI_P LK_PI_P# TXP0 TXN0 TXP TXN TXP TXN TXP TXN TXP TXN TXP TXN TXP TXN TXP TXN TXP TXN TXP TXN TXP0 TXN0 TXP TXN TXP TXN TXP TXN TXP TXN TXP TXN H H J J K H H H K J J H 0 H0 H K J J H H K J J H H K J J H U PX_RT# PX_RFLK PX_RFLK# PX_TX0 PX_TX0# PX_TX PX_TX# PX_TX PX_TX# PX_TX PX_TX# PX_TX PX_TX# PX_TX PX_TX# PX_TX PX_TX# PX_TX PX_TX# PX_TX PX_TX# PX_TX PX_TX# PX_TX0 PX_TX0# PX_TX PX_TX# PX_TX PX_TX# PX_TX PX_TX# PX_TX PX_TX# PX_TX PX_TX# P_RXP_0 K P_RXN_0 PX_RX0 K P_RXP_ PX_RX0# M P_RXN_ PX_RX M P_RXP_ PX_RX# L P_RXN_ PX_RX L P_RXP_ PX_RX# K P_RXN_ PX_RX K P_RXP_ PX_RX# L P_RXN_ PX_RX L P_RXP_ PX_RX# M P_RXN_ PX_RX M P_RXP_ PX_RX# K P_RXN_ PX_RX K0 P_RXP_ PX_RX# L0 P_RXN_ PX_RX L P_RXP_ PX_RX# M P_RXN_ PX_RX M P_RXP_ PX_RX# K P_RXN_ PX_RX K P_RXP_0 PX_RX# L P_RXN_0 PX_RX0 L P_RXP_ PX_RX0# M P_RXN_ PX_RX M P_RXP_ PX_RX# K P_RXN_ PX_RX K P_RXP_ PX_RX# L P_RXN_ PX_RX L P_RXP_ PX_RX# M P_RXN_ PX_RX M P_RXP_ PX_RX# L P_RXN_ PX_RX L PX_RX# NV_NP- PI XPR MULTI-U I/O INTRF MIO0 MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO0 MIO MIO0 MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO0 MIO MIO_HYN MIO_VYN MIO_ MIO_TL MIO_LKOUT MIO_LKOUT# MIO_VRF MIOL_PU_N MIOL_P_VQ MIO_HYN MIO_VYN MIO_ MIO_TL MIO_LKOUT MIO_LKOUT# MIO_LKIN MIO_VRF MIOL_PU_N MIOL_P_VQ P N N N M M P N N M L L R R P P R P L L L F Y Y Y MIO0 MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO0 MIO MIO0 MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO0 MIO MIO_HYN MIO_VYN MIO_ MIO_TL MIO_LKOUT MIO_LKOUT# MIO_VRF MIOL_PU_N MIOL_P_VQ MIO_HYN MIO_VYN MIO_ MIO_TL MIO_LKOUT MIO_LKOUT# MIO_LKIN MIO_VRF MIOL_PU_N MIOL_P_VQ MIO0 MIO MIO MIO MIO MIO0 MIO MIO MIO MIO MIO MIO MIO MIO R NV_K_F 00 MIO_HYN MIO_TL +VRUN R NV_0K_J 00 TP MIL TP MIL TP MIL TP MIL TP00MIL TP00MIL TP MIL TP00MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP0 MIL TP MIL TP0 MIL TP MIL TP0 MIL TP MIL TP MIL TP MIL TP MIL [MIO_HYN : LOT_LOK_F] 0 PU and MH share a common reference clock PU and MH do not share a common reference clock FOXONN V (PI XPR) OF HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of

19 , F[0:], FQM[..0] F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F FQM0 FQM FQM FQM FQM FQM FQM FQM N M N L K K J J P0 N N0 N L L0 J0 L H0 K0 H F0 H 0 0 H H J F F 0 Y 0 M0 F0 J J0 J K M L0 0 0 F H F M M0 0 F K0 0 0 U F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F FQM0 FQM FQM FQM FQM FQM FQM FQM R(-ROUP) F_M0 F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M0 F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M0 F_M F_M F_M F_M F_M F_M F_M F_LK0 F_LK0# F_LK F_LK# FQ_WP0 FQ_WP FQ_WP FQ_WP FQ_WP FQ_WP FQ_WP FQ_WP FQ_RN0 FQ_RN FQ_RN FQ_RN FQ_RN FQ_RN FQ_RN FQ_RN P U P U0 Y W W T V T T U W W0 T V V0 U R V T0 W R R0 P U Y F_ F_R# F_ F_ F_ F_ F_ F_# F_0# F_ F_# F_W# F_0 F_ F_ F_RT F_ F_0 F_K F_0 F_ F_ F_ F_ F_ F_ F_ Y0 F_ NX: dditional memory address bit to support dual rank bank memory configurations P R Y L K L F H0 M K L F H F_LK0 F_LK0# F_LK F_LK# FWQ0 FWQ FWQ FWQ FWQ FWQ FWQ FWQ FRQ0 FRQ FRQ FRQ FRQ FRQ FRQ FRQ F_[0..], U, F[0:] F0 F_ F F0 F_M0 F_R# F F F_M F_[..], F_ F_[..], F F F_M F_ F F F_M F_ F_R# F_R# F F F_M 0 F_R#, F_ F_ F_R#, F_ F F F_M F_, F_ F_ F_, F_ F F F_M F_, F_# F_0# F_, F_0# F F F_M F_0# F_0# F_# F_0# F F_# F F F_M F_#, F_ F_#, F0 F0 F F_M F_# F_#, F F0 F_M0 F_#, F_W# F_W#, F F F_M F_W#, F_0 F_0, F F F_M F F_0, F F F_ F F F_M F F F_ F F F_M F_RT F_RT, F F F F_M F_RT, F F F0 F F_ F F0 F_M F_0 F_K, F F F_M F_K F F F_M F_K, F F 0 F_0 F F F_M F 0 F_ F F F_M0 F_ F F F_M 0 F_ F F F_M F_ F F F_M F_ F0 F F_M F_ F F0 F_M F TP MIL F F F_ F F F_M 0 TP MIL F F F_ F F F_M 0 NX: dditional memory address bit F F 0 to support dual rank bank memory configurations F F F F F_LK0 F_LK0, F F F_LK0 F_LK0, F F_LK0# F_LK0#, F0 F F_LK0# F_LK0#, F F_LK F_LK, F F0 F_LK F_LK, F_LK# F_LK#, F F F_LK# F_LK#, F F F F F F F F F FWQ0 FWQ[..0], FWQ[..0], F F FQ_WP0 F 0 FWQ F F FQ_WP FWQ F F FQ_WP FWQ F0 F FQ_WP FWQ F F0 FQ_WP FWQ F F FQ_WP FWQ F F FQ_WP F0 FWQ F F FQ_WP F F F F F F F F FRQ0 FRQ[..0], FRQ[..0], F F FQ_RN0 FRQ F0 F FQ_RN FRQ F F0 FQ_RN FRQ F F FQ_RN FRQ F F FQ_RN FRQ F FQ_RN FRQ, FQM[..0] FQM0 FQ_RN F FRQ FQM FQM0 FQ_RN FQM FQM F FQM FQM FQM FQM FQM FQM F FQM FQM FQM FQM 0 FQM R(-ROUP) F_[0..], NV_NP- NV_NP- FOXONN V (R) OF HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of

20 M bus ddress : 0000() For FM +VRUN Use PU internal thermal sensor hange R,R form N to mount, M_THRM_LK, M_THRM_T NV_I_L R NV_.K_J 00 NV_I_ R NV_.K_J 00 M_THRM_LK M_THRM_T HMI RT R NV_0_J 00 R NV_0_J 00 HP ackup NV_I_L NV_I_ NV_I_L NV_I_ MIL TP0 MIL TP0 MIL TP0 MIL TP NV_I_L NV_I_ HP_L HP_ NV_I_L NV_I_ NV_I_L NV_I_ NV_I_L NV_I_ ROM_# ROM_O TP_ROM_I ROM_LK H H J K J W UF I_L I_ IH_L IH_ I_L I_ I_L I_ I_L I_ ROM# ROM_O ROM_I ROM_LK I ROM NRL INL THRMN J NV_THRMN THRMP K NV_THRMP UFRT# TRO WPRY_ MMTRPL0 MMTRPL MMTRPL MMTRPL F T M H H UFRT# TRO WPRY MMTRPL TP_MMTRPL MMTRPL MMTRPL0 TP00MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL 00 NV_00P_0V_K_ +VRUN R.K_J 00 U THRM# - + V Pf 0.U_V_M_ 00 R N_0_J 00 R N_0_J 00 N LRT# L R_LRT# M_THRM_T M_THRM_LK / change part from FM(VRIION:0.P) ( -FM-000) to Pf (-P0-0000) OVT_FX# NV_PIO To PU ackup PIO for PU thermal trigger signal hange R from mount to N for using internal thermal sensor From R_LRT#, +VRUN R N_0K_J 00 NV_I_L R0 NV_.K_J 00 NV_I_ R0 NV_.K_J 00 NV_I_L R NV_.K_J 00 NV_I_ R NV_.K_J 00 NV_I_L R NV_.K_J 00 NV_I_ R NV_.K_J 00 +VRUN NV_JT_TI R NV_0K_J 00 NV_JT_TM R NV_0K_J 00 NV_JT_TRT# R NV_0K_J 00 NV_JT_TK R NV_0K_J 00 HP_L HP_ R NV_0K_J 00 +VRUN R0 NV_0K_J 00 U L V N N N N N HP ROM MIL TP MIL TP MIL TP0 MIL TP0 MIL TP0 MIL TP0 IFP_VPRO IFP_VPRO PX_TTLK_OUT PX_TTLK_OUT# TTMO R0 NV_0K_J 00 MIL TP0 PROM_OI-P_K NV_JT_TK NV_JT_TM NV_JT_TI NV_JT_TO NV_JT_TRT# L NV_0.U_V_M_ 00 M K M M F H J K K L IFP_VPRO IFP_VPRO PX_TTLK_OUT PX_TTLK_OUT# F_U F_U TTMO JT_TK JT_TM JT_TI JT_TO JT_TRT_N NV_NP- NV_PIO0 R0 NV_0_J 00 NV_HMI_T_, NV_PIO R0 NV_00K_J 00 NV_RJ NV_RJ NV_LV_N# NV_LV_N# NV_INV_N NV_INV_N V_PIO V_PIO NV_PIO R 00 N_0_J TP0 MIL NV_PIO TP MIL NV_PIO R N_0_J 00 RT#, OVT_FX# OVT_FX# NV_PWR_MIZR NV_PWR_MIZR NV_RT_TL R0 N_0_J 00 HMI_ NV_PIO TP MIL NV_PIO TP MIL NV_PIO TP MIL NVII F suggestion: hange PU thermal alert signal input from PIO to PIO. elete TP and pull-up PIO (R.K to +VRUN) XTLIN R0 0_J 00 R_R_M_ XTLOUTUFF NV_XTLIN R0 0_J 00 R_RT_M_NON / F suggest If use internal spread function, U0 and related components can be N. 0/ hange R,R0 from N_ to NV_ for use internal spread spectrum. R N_0K_J 00 _0 R N_0K_J 00 PIO TT INL RYTL XTLOUTUFF XTLIN PIO0 K PIO H PIO K PIO PIO PIO J PIO PIO K PIO PIO PIO0 H PIO F PIO PIO PIO XTLIN XTLOUTUFF XTLIN XTLOUT U U T T U U R N_P_0V_J_N NV_XTLOUT N_0K_J 00 Y N_MHZ_0P_0PPM ITTI_L N_P_0V_J_N R N J 00 R R0 N_0K_J N J R N_0K_J 00 N_U_0V_Y_Y 00 XTLOUTUFF_R _0 VMOUT R place near PU R place near spectrum chip PIO PIO0 PIO PIO PIO PIO PIO PIO PIO 0//0 PVT hange N_000P_0V_M_ 00 U0 N_MK-0 PIO0 PIO I/O +VRUN RFLK Tis chip can use MK or P X/ILK X N V 0 P# LK RFLK I/O I I O O O O O I O TP Internal pull low Yes Yes Yes No Yes Yes No No No No PIO TL HMI Hot Plug etect 0(HP0) VI Hot Plug etect (HP) L L rightness(l0_l_pwm) Panel Power(L0_V) L acklight enable(l0_l_n) PU Power owngrade for NV_V Thermal lert Output (> egree) ctive Low ystem Power Limit lert Input Memory Vref switch(mm_vrf) HMI Function ackup NV_RJ 00 NV_0K_J R NV_INV_N 00 NV_0K_J R MIL PR PTRUM TTIN FOR MK 0 PR IRTION 0 OWN M OWN OWN 00// Update pread Percentage(%) = connect to N M= unconnected = connect directly to V ctive High ctive High ctive High ctive Low ctive High ctive Low ctive Low ctive High hange R from N to mount for using internal thermal sensor FOXONN V (POWR) OF NV_PIO 00 OVT_FX# 00 NV_.K_J R NV_.K_J R +VRUN PR PTRUM TTIN FOR P R PR pread PIN IRTION Percentage(%) 0 OWN -. OWN -. nvidia support own -.% HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet 0 of

21 NV_R R NV_0_F 00 NV_RN R NV_0_F 00 NV_LU R NV_0_F 00 NV RT R0 NV F 00 H U _RT _RT R NV RT R NV F 00 0 F F F F F 0 H J0 J J J J0 J J J J J K K K L L L L L L L L M M M M0 M M M UH N N N N N N N N N N0 N N N N N N N N N N0 N N N N N N N N N N0 N N N N N N N N N N0 N N N N N N N N N N0 N N N N N N N N N N0 N N N N N N N N N N0 N N N N N N N N N N0 NV_NP- N N N N N N N N N N N0 N N N N N N N N N N00 N0 N0 N0 N0 N0 N0 N0 N0 N0 N0 N N N N N N N N N N0 N N N N N N N N N N0 N N N N N N N N N N0 F F F F F F F F H H J J J J K0 K K K L L M M M M N N N N P P P P R R R R R R R0 R T T T T T U U U U U V V V V N V N V N V0 N V N W N W N W N W N Y N0 Y N Y N Y N L0 N N M0 LO TO PU N_N -R -RN -LU -HYN -VYN V-RT R HYN VYN V-LK V-T NV_R NV_RN NV_LU NV_HYN NV_VYN I L MIL TP0 MIL TP -R -RN -LU NV_R NV_R NV_LU MIL TP 0m MIL TP MIL TP NV_HYN NV_VYN IFP_TX# MIL TP IFP_TX MIL TP MIL TP MIL TP IFP_TX# IFP_TX IFP_RT -VIO Y H F F J K J H H H K J H J L K M M L M K K L K L _RT NV_RN MIL TP _RN NV_O_RXIN- NV_O_RXIN+ N_N NV_O_LKIN- NV_O_LKIN+ NV_O_RXIN0- NV_O_RXIN0+ NV_O_RXIN- NV_O_RXIN+ NV_O_RXIN- NV_O_RXIN+ NV_VN_LKIN- NV_VN_LKIN+ NV_VN_RXIN- NV_VN_RXIN+ NV_VN_RXIN0- NV_VN_RXIN0+ NV_VN_RXIN- NV_VN_RXIN+ MIL TP00 _R NV_RN J _RN NV_LU H _LU 0m NV_HYN _IUMP F0 NV_VYN _HYN K0 _VYN _R _LU _IUMP _HYN _VYN IFP_TX# IFP_TX IFP_TX0# IFP_TX0 IFP_TX# IFP_TX IFP_TX# IFP_TX IFP_TX# IFP_TX IFP_TX# IFP_TX IFP_TX# IFP_TX IFP_TX# IFP_TX IFP_TX# IFP_TX IFP_TX# IFP_TX IFP_RT NV_NP- OMPOIT -ONNTOR PR Y OMPOITP LIN LIN LIN VIO LV TM _R R NV_R _RN T NV_RN _LU _IUMP IFP_TX# IFP_TX IFP_TX0# IFP_TX0 IFP_TX# IFP_TX IFP_TX# IFP_TX IFP_TX IFP_TX# IFP_TX IFP_TX# IFP_TX IFP_TX# IFP_TX IFP_RT I L T V M M F F H L L J J H NV_LU 00m TM LK MHz VI_TM_LKIN- IFP_TX# H VI_TM_LKIN+ J VI_TM_- K VI_TM_+ VI_TM_- VI_TM_+ IFP_RT NV_HMI_TX- NV_HMI_TX+ NV_TM_- NV_TM_+ NV_TM_0- NV_TM_0+ NV_TM_- NV_TM_+ NV_O_LKIN- NV_O_LKIN+ NV_O_RXIN0- NV_O_RXIN0+ NV_O_RXIN- NV_O_RXIN+ NV_VN_RXIN- NV_VN_RXIN+ NV_VN_LKIN- NV_VN_LKIN+ NV_VN_RXIN- NV_VN_RXIN+ NV_VN_RXIN0- NV_VN_RXIN0+ VI_TM_- VI_TM_+ -R -RN -LU -HYN -VYN VI-I R HYN VYN VI-LK VI-T TP00MIL TP00MIL TP0MIL TP0MIL TP0MIL TP0MIL TP0MIL TP0MIL I L NV_R LO TO PU NV_RN R NV_0_F 00 NV_LU NV YN _YN U TP MIL NX: dd composite sync for RT support NV_R NV_RN NV_HMI_TX- NV_HMI_TX+ NV_TM_0- NV_TM_0+ NV_TM_- NV_TM_+ NV_TM_- NV_TM_+ TP0 MIL 0/ dd test point for TM channel cause by VI on docking been cacelled FOXONN R NV_0_F 00 R NV_0_F 00 V (POWR) OF HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of

22 +_VRUN +_VRUN +_VRUN V V R R R R N N N N J J U +_VRUN V V R R R R N N N N J J U U Mirror function on F F F F F F F F0 F0 F F F F F F F F F F F F0 F F F F F F F F F F F0 F F M M V V K K T T R R M N L M T0 T R0 R M0 N L0 M 0 F F0 0 0 F F V V V V V V V V V V Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 VQ VQ VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 RFU J H0 0 RFU 0 /P 0 M M M M0 RQ RQ RQ RQ0 J L K M K L K0 H K M K H K N N0 0 P P0 0 F_# F_ F_ F_0 FQM FQM FQM0 FQM FRQ FRQ FRQ0 FRQ F_R# R# H F_# # F F_W# W# H F_0# # F J F_LK0 K J0 F_LK0# K# H F_K K H VRM_VRF_ VRF0 WQ WQ WQ WQ0 MF N RT VRF P P V V H FWQ FWQ FWQ0 FWQ F_RT VRM_VRF_ F_#, F_, F_, F_0, F_ F_ F_0 F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 F F F F F F0 F F F F0 F F_R#, F F_#, F F_W#, F F_0# F F_LK0, F F_LK0#, F F_K, F0 F R0 F F NV_0K_J F 00 F F F F F F F F_RT, F F F F F M M V V K K T T R R M N L M T0 T R0 R M0 N L0 M 0 F F0 0 0 F F V V V V V V V V V V Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 VQ VQ VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 Minimum 00us delay required prior to applying any executable command after stable power and clock. F_# RFU J F_R# H0 F_0 F_ 0 F_ RFU J F_ L F_ 0 K F_ M F_0 /P K F_ L F_ K0 F_ H F_0 K F_ M F_ K F_ H K F_ 0 N FQM M N0 FQM M 0 FQM M FQM M0, P FRQ RQ P0 FRQ RQ 0 FRQ RQ FRQ RQ0 H F_ R# F F_0# # H F_K W# F F_# # J F_LK K J0 F_LK# K# H F_W# K H VRM_VRF_ VRF0 WQ WQ WQ WQ0 MF FWQ FWQ FWQ FWQ MF F_RT VRM_VRF_ F_ F_ F_ F_ +_VRUN U_ZQ RM_F-_M KJQ- R NV_0_F 00 R NV_0K_J 00 F_RT R(0 ohm-0 ohm) 0 ohm --> Output impedence 0 ohm +_VRUN VRM_VRF is 0%FVQ for R.V +_VRUN +_VRUN +_VRUN VRM_VRF_ VRM_VRF_ R0 00 _F VRM_VRF_ VRM_VRF_ VRM_VRF_ VRM_VRF_ U_V_M_ R 00.K_F U_V_M_ 0 00 N_U_0V_K N RT VRF P P V V H R NV_0K_F 00 F_[..0] F_LK, F_LK#, R NV_0_F 00 ZQ V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 0 L L V V0 J J VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 L L P P P P T T T T R 00.K_F RM_F-_M KJQ- R 00 _F R 00.K_F 00 N_U_0V_K 00 N_U_0V_K R 00 _F R 00.K_F U_V_M_ F_[..], F[0:], FQM[..0], FRQ[..0], FWQ[..0], U_ZQ ZQ V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 0 L L V V0 J J VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 L L P P P P T T T T VRM_VRF_ R 00 _F U_V_M_ 00 N_U_0V_K VRM_VRF_ R,R, R,R 0 0 R(NX) ohm 0.0uF 00 F_LK0 R NV F F_LK0# NVII F suggestion: Update ingle resistor between Fx_LK and Fx_LK* to ohm 00 F_LK F_LK# R NV F FOXONN VRM (R) OF ize ocument Number Rev ustom (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of HON HI PRIION IN. O., LT. P - R& ivision

23 +_VRUN +_VRUN +_VRUN V V R R R R N N N N J J U U Mirror function on Place on T-ide overlap with U +_VRUN V V R R R R N N N N J J U U Place on T-ide overlap with U F0 F F F F F F F F F F F F F F F0 F F F F F F F F0 F F F F F0 F F F F F M M V V K K T T R R M N L M T0 T R0 R M0 N L0 M 0 F F0 0 0 F F V V V V V V V V V V Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 VQ VQ VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 Minimum 00us delay required prior to applying any executable command after stable power and clock. RFU J H0 0 RFU 0 /P 0 J L K M K L K0 H K M K H K U_RFU F_R# F_0 F_ F_ F_ F_ F_ F_0 F_ F_ F_ F_0 F_ F_ F_ F_ TP0MIL F_R#, F_0, F_, F F M M V V K K V V V V V V V V V V VQ VQ VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 RFU 0 RFU 0 /P 0 J H0 J L K M K L K0 H K M K H K U_RFU F_ F_ F_0 FQM F FQM M N T FQM F0 Q M N FQM M N0 T FQM F Q0 M N0 FQM M 0 R FQM0 F Q M 0 FQM M0 R F Q M0, F_[..0] M FRQ F Q FRQ RQ P N FRQ F Q RQ P FRQ RQ P0 L FRQ F Q RQ P0 FRQ RQ 0 M FRQ0 F Q RQ 0 FRQ RQ0 T0 F Q RQ0 T F_ F Q F_R# R# H F_, R0 F_# F Q R# H R F_# # F F_#, F_K F Q0 # F M0 F_W# W# H F_# F0 Q W# H N F_# # F F_#, F_LK0 F Q # F L0 F_LK K J F_LK0, J F_LK0# F Q K M J0 F_LK# F_LK, K# J0 F_LK0#, F_W# F Q K# 0 H F_K F_LK#, K H F_W#, F Q K F_K, F VRM_VRF_ F Q F0 H VRM_VRF_ VRF0 H VRM_VRF_ F Q VRF0 VRM_VRF_ FWQ F Q 0 P FWQ WQ P FWQ F Q WQ P FWQ WQ P FWQ F Q0 WQ 0 FWQ WQ FWQ0 F Q WQ FWQ WQ0 R NV_0K_F 00 F Q WQ0 MF +_VRUN F0 Q MF F F Q MF F F Q N V V F_RT F Q N V V F_RT RT F_RT, F Q RT VRM_VRF_ F Q H H VRM_VRF_ VRF VRM_VRF_ F Q VRF VRM_VRF_ Q0 F_ F_ F_ F_ TP0MIL F_ F_ F_0 F_ F_ F_ F_ F_ F_0, F_ F_ F_ F_ F_[..] U_ZQ ZQ R NV_0_F 00 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 0 L L V V0 J J VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 L L P P P P T T T T RM_F-_M KJQ- U_ZQ R NV_0_F 00 ZQ V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 0 L L V V0 J J VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 L L P P P P T T T T RM_F-_M KJQ- R(0 ohm-0 ohm) 0 ohm --> Output impedence 0 ohm F[0:], FQM[..0], FRQ[..0], FWQ[..0], FOXONN VRM (R) OF HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev ustom (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of

24 +_VRUN +_VRUN +_VRUN V V R R R R N N N N J J U +_VRUN V V R R R R N N N N J J U U Mirror function on F F F F F F F F0 F F F0 F F F F F F F F F F0 F F F F F F F F F F F0 F F M M V V K K T T R R M N L M T0 T R0 R M0 N L0 M 0 F F0 0 0 F F V V V V V V V V V V Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 VQ VQ VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 RFU J H0 0 RFU 0 /P 0 M M M M0 RQ RQ RQ RQ0 J L K M K L K0 H K M K H K N N0 0 P P0 0 F_# F_ F_ F_0 FQM0 FQM FQM FQM FRQ0 FRQ FRQ FRQ F_R# R# H F_# # F F_W# W# H F_0# # F J F_LK0 K J0 F_LK0# K# H F_K K H VRM_VRF_ VRF0 WQ WQ WQ WQ0 MF N RT VRF P P V V H FWQ0 FWQ FWQ FWQ F_RT VRM_VRF_ F_#, F_, F_, F_0, F_ F_ F_0 F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 F F F F F F F F F0 F F F_R#, F F_#, F F_W#, F F_0# F F_LK0, F F_LK0#, F F_K, F0 F R F F NV_0K_J F 00 F F F F F F F F_RT, F0 F F F F M M V V K K T T R R M N L M T0 T R0 R M0 N L0 M 0 F F0 0 0 F F V V V V V V V V V V Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 VQ VQ VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 Minimum 00us delay required prior to applying any executable command after stable power and clock. F_# RFU J F_R# H0 F_0 F_ 0 F_ RFU J F_ L F_ 0 K F_ M F_0 /P K F_ L F_ K0 F_ H F_0 K F_ M F_ K F_ H K F_ 0 N FQM M N0 FQM M 0 FQM M FQM M0, P FRQ RQ P0 FRQ RQ 0 FRQ RQ FRQ RQ0 H F_ R# F F_0# # H F_K W# F F_# # J F_LK K J0 F_LK# K# H F_W# K H VRM_VRF_ VRF0 WQ WQ WQ WQ0 MF N RT VRF P P V V H FWQ FWQ FWQ FWQ MF F_RT VRM_VRF_ F_ F_ F_ F_ not have this R in reference R0 NV_0K_F 00 F_[..0] F_LK, F_LK#, +_VRUN F_[..], F[0:], FQM[..0], FRQ[..0], FWQ[..0], U_ZQ R NV_0_F 00 ZQ V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 0 L L V V0 J J VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 L L P P P P T T T T RM_F-_M KJQ- U_ZQ ZQ R NV_0_F 00 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 0 L L V V0 J J VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 L L P P P P T T T T RM_F-_M KJQ- R NV_0K_J 00 F_RT R(0 ohm-0 ohm) 0 ohm --> Output impedence 0 ohm VRM_VRF is 0%FVQ for R.V +_VRUN +_VRUN +_VRUN +_VRUN 00 R R 00 _F.K_F 00 R,R, R,R 0 0 VRM_VRF_ 0.U_V_M_ 00 N_U_0V_K R(NX) ohm 0.0uF VRM_VRF_ VRM_VRF_ VRM_VRF_ VRM_VRF_ VRM_VRF_ 00 F_LK0 R0 NV F 00 R R 00 _F.K_F 00 0.U_V_M_ 00 F_LK0# N_U_0V_K NVII F suggestion: Update ingle resistor between Fx_LK and Fx_LK* to ohm 00 F_LK F_LK# R NV F 00 R R 00 _F.K_F 00 0.U_V_M_ 00 N_U_0V_K FOXONN 00 R VRM (R) OF ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of R 00 _F.K_F 00 VRM_VRF_ 0.U_V_M_ 00 N_U_0V_K VRM_VRF_ HON HI PRIION IN. O., LT. P - R& ivision

25 +_VRUN +_VRUN +_VRUN V V R R R R N N N N J J U U Mirror function on Place on T-ide overlap with U +_VRUN V V R R R R N N N N J J U U Place on T-ide overlap with U F F F0 F F F F F F F F F F F F F0 F F F F F F F F0 F F F F F0 F F F F F M M V V K K T T R R M N L M T0 T R0 R M0 N L0 M 0 F F0 0 0 F F V V V V V V V V V V Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 VQ VQ VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 U_RFU RFU J TP0MIL F_R# H0 F_R#, F_0 F_0, F_ 0 F_, F_ RFU J F_ L F_ 0 K F_ M F_0 /P K F_ L F_ K0 F_ H F_0 K F_ M F_ K F_ H Minimum 00us delay F_ 0 K required prior to applying N FQM M any executable command N0 FQM0 M 0 FQM after stable power and clock. M FQM M0 P FRQ RQ P0 FRQ0 RQ 0 FRQ RQ FRQ RQ0 H F_ R# F_, F F_# # F_#, H F_K W# F_K, F F_# # F_#, J F_LK0 K F_LK0, J0 F_LK0# K# F_LK0#, H F_W# K F_W#, H VRM_VRF_ VRF0 VRM_VRF_ WQ WQ WQ WQ0 MF N RT VRF P P V V H FWQ FWQ0 FWQ FWQ MF F_RT VRM_VRF_ R NV_0K_F 00 F_RT, VRM_VRF_ +_VRUN F0 F F F F F F F F F F F F F F F F F F F F F0 F F F F0 F F F F F F F F M M V V K K T T R R M N L M T0 T R0 R M0 N L0 M 0 F F0 0 0 F F V V V V V V V V V V Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 VQ VQ VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 RFU J H0 0 RFU 0 /P 0 M M M M0 J L K M K L K0 H K M K H K N N0 0 P P V V H U_RFU F_ F_ F_0 FQM FQM FQM FQM FWQ FWQ FWQ FWQ F_RT VRM_VRF_ F_ F_ F_ F_ FRQ RQ P FRQ RQ P0 FRQ RQ 0 FRQ RQ0 F_R# R# H F_# # F H F_W# W# F F_# # J F_LK K J0 F_LK# K# H F_K K H VRM_VRF_ VRF0 WQ WQ WQ WQ0 MF N RT VRF TP0MIL F_ F_ F_0 F_ F_ F_ F_ F_ F_0, F_LK, F_LK#, VRM_VRF_ VRM_VRF_, F_ F_ F_ F_ F_[..0] F_[..] U_ZQ ZQ R NV_0_F 00 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 0 L L V V0 J J VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 L L P P P P T T T T RM_F-_M KJQ- U_ZQ R NV_0_F 00 ZQ V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 0 L L V V0 J J VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 L L P P P P T T T T RM_F-_M KJQ- R(0 ohm-0 ohm) 0 ohm --> Output impedence 0 ohm F[0:], FQM[..0], FRQ[..0], FWQ[..0], FOXONN VRM (R) OF HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev ustom (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of

26 +VRUN R NV_0_J 00 +VRUN 0/ elete, and change R from 00 to 00 for MIO is used to straps input and the current is very low. L +VRUN +VRUN R NV_0_J 00 NV_0R-00MHZ_00 M00 L0 NV_0R-00MHZ_00 M00 0m NV_0.U_V_M_ 00 0m NV_0.U_V_M_ 00 0m NV_.U_0V_Y_Y 00 0m 0 NV_.U_0V_Y_Y 00 R NV_0K_J 00 MIO_V MIO_V N_0.0U_V_K_ 00 N_0.0U_V_K_ 00 MIL TP0 NV V NV V NV VRF NV V NV VRF m M M R T U 0 V R H T U MIO_VQ MIO_VQ MIO_VQ MIO_VQ MIO_VQ MIO_VQ MIO_VQ MIO_VQ MIO_VQ MIO_VQ _V NV VRF H0 _VRF _V _VRF _V _VRF PLLV POWR IFP_PLLV IFP_PLLN IFP_IOV IFP_IOV IFP_IOV IFP_IOV IFP_PLLV F F 0 IFP_PLLV IFP_IOV IFP_IOV NV_000P_0V_M_ 00 IFP_IOV -- LV I/O power IFP_IOV -- LV I/O power IFP_IOV -- TM I/O power IFP_IOV -- TM I/O power IFP_PLLV NV_000P_0V_M_ 00 NV_0.U_V_M_ 00 NV_U_0V_Y_Y 00 NX: / change power rail from.v to.v L0 0m +_VRUN NV_0R-00MHZ_00 0 M00 NV_.U_0V_Y_Y 00 0m(m+m) NV_.U_0V_Y_Y 00 L0 NV_0R-00MHZ_00 M00 +_VRUN NX: / change power rail from.v to.v L0 0m +_VRUN NV_0R-00MHZ_00 M00 NV_0.U_V_M_ 00 NX: hange power rail from.v to.v L0 PX_V NV_0R-00MHZ_00 M00 m NV_000P_0V_M_ 00 NV_PLLV m IFP_IOV NV_0.U_V_M_ 00 00m(0m+0m) NV_.U_0V_Y_Y 00 NV_0.U_V_M_ 00 0 NV_000P_0V_M_ 00 U0 PLLN IFP_PLLN 0 NV_.U_0V_Y_Y 00 T0 VI_PLLV NV_NP- Q +VRUN NV_FNP_NL NV VRF NV_0.0U_V_K_ 00 NV VRF NV_0.0U_V_K_ 00 +VLW R NV_0K_J 00 RUN_IFP,,, RUN_ON Q NV_TU FOXONN V (POWR) OF HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of

27 +_VRUN For R FVTT require decoupling capacitor,fv don't require them 0 NV_.U_0V_Y_Y 00 NV_0.U_V_M_ 00 NV_000P_0V_M_ 00 NV_0.U_V_M_ 00 NV_000P_0V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 H H J0 J J J K K K K K K L M T U UI FVTT0 FVTT FVTT FVTT FVTT FVTT FVTT FVTT FVTT FVTT FVTT0 FVTT FVTT FVTT FVTT FVTT FVTT FVTT FV0 FV FV FV FV FV FV FV FV FV FV0 FV FV FV FV FV FV FV FV FV F_VRF 0 K F J M R V F_VRF N_0.U_V_M_ 00 R0 N_.K_F 00 R N_0K_F 00 +_VRUN.V PX_V.V PX_V L NV_0R-00MHZ_00 M00 L NV_0R-00MHZ_00 M00 m(frame uffer nalog Power) NV_.U_0V_Y_Y 00 NV_0.U_V_Y_Y 00 m(frame uffer nalog Power) NV_.U_0V_Y_Y 00 NV_0.U_V_Y_Y 00 0 NV_000P_0V_M_ 00 NV_000P_0V_M_ 00 F_PLLV F_PLLV FL_P_VQ FL_PU_N FL_TRM_N 0 K H J F_PLLV F_PLLN F_PLLV F_PLLN FL_P_VQ FL_PU_N FL_TRM_N POWR FVQ0 FVQ FVQ FVQ FVQ FVQ FVQ FVQ FVQ FVQ FVQ0 FVQ FVQ FVQ FVQ FVQ FVQ FVQ FVQ FVQ FVQ0 FVQ FVQ FVQ H H H H H H L L M M R R V V.(Frame uffer core power for I/O) 0 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 0 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_000P_0V_M_ 00 NV_0.U_V_M_ 00 +_VRUN NV_000P_0V_M_ 00 0/ Replace P0 by a higher R cap(0mohm) for cost down NV_.U_0V_Y_Y 00 P0 + NV_0U_0V_ 0TP0ML NV_NP- FL_P_VQ FL_PU_N R00 N_0._F 00 R NV_._F 00 R N_0_F 00 R0 NV_._F 00 +_VRUN NVII 0// update R(NM-T) FL_P_VQ. ohm FL_PU_N. ohm R(NP-). ohm. ohm 0 NV_PWR_MIZR Q N_N00PT F_VRF R N_.K_F 00 Memory Vref switch controlled by PIO0 FL_TRM_N R NV_0._F 00 FL_TRM_N 0. ohm 0. ohm NVII update NM VRM termination value FL_P_VQ. Ω FL_PU_N. Ω FL_TRM_N 0. Ω FOXONN V (POWR) OF HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of

28 .V PX_V.V.V NV_0U_.V_M 00_XR PX_V.U_0V_Y_Y 00.V PX_V NV_U_V_K_ N_000P_0V_M_.V NV_V +VRUN The trace impedance of PIF_OUT_HMI should be ohm +/- ohm L0 NV_U_V_K_ 00 00m 0m NV_0.U_V_M_ 00 (econdary internal core power) 0m(.V Power rail PIO,I,PU IITL LOI) Nx 0.V wing Nx.V wing 0nF 0nF R0 R. ohm No tuff No tuff No tuff R No tuff No tuff PX_PLL_V PX_PLL_V L_NV_V.(Internal logic core power) R circuit 00 NVV_N /0 F suggest to N N_0.0U_V_K_ 00 N_N NX: / change power rail from PX_V to NV_V W NV_U_.V_M_ NV_0.U_V_M_ NV_0.U_V_M_ NV_000P_0V_M_ V0 W 00 V V Y NV_000P_0V_M_ NV_000P_0V_M_ NV_000P_0V_M_ V_LP V Y Y V NV_000P_0V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 0 NV_0.U_V_M_ NV_0.U_V_M_ NV_0.U_V_M_ NFN TP MIL N M NFN N V TP MIL NFN TP0 MIL N V H_PLLV is new power rail for NM NFN0 N TP MIL L NFN N TP MIL NFN m(power rail) N N W TP MIL PX_V MIL TP0 H NFN TP MIL NV_0R-00MHZ_00 PIF_PU N N W J NFN TP MIL FM0KF-T0 MIL TP NFN N N0 V NFN +VRUN MIL TP NFN N N Y TP0 MIL M F NFN TP MIL NV_0.U_V_M_ NV_.U_0V_Y_Y MIL TP NFN N N M TP_F_PLLV TP MIL 00 MIL TP NFN N N 00 W H_PLLV 0/ Remove 0 for Internal HMI MIL TP0 N N F_VRF PIIF IN don't need Protection MIL TP NFN N N TP MIL TRP R F NFN0 N N TP0 MIL MIL TP V TTMMLK R N_0K_J 00 MIL TP NFN N0 N NFN N_.K_F U W MIL TP NFN N N TP MIL NFN TP MIL 00_XR V Y 00 N N HMI_PIF NV_NP- NV_0.0U_V_M R0 N_._F 00 NV_0.U_V_M_ 00 NV_U_.V_M_ 00 0 NV_0.U_V_M_ 00 NV_0R-00MHZ_00 P / backup M00 NV_.U_0V_Y_Y NV_0.U_V_M_ NV_000P_0V_M_ V P for MI request 00 V P NV_0.U_V_M_ NV_0.U_V_M_ NV_0.U_V_M_ V P close to L0 V 00 V R R NV_0_J 00 NV_U_V_K_ 00 L NV_0R-00MHZ_00 M00 NV_0.U_V_M_ 00 NV_000P_0V_M_ 00 NV_0.U_V_M_ 00 R NV_K_F 00 NV_U_V_K_ 00 NV_0.U_V_M_ 00 F P0 T0 T U0 U W0 H J K L0 L L M0 U PX_V PX_IOV0 V/VQ:00m (I/O Power) F NV_V PX_IOV L0 F PX_IOV F T NV_PLLV m(frame uffer nalog Power) PX_IOV NV_PLLV PX_IOV NV_0R-00MHZ_00 PX_IOV Place close to L0 M00 NV_U_0V_Y_Y 00 NV_0U_.V_M 00_XR NV_000P_0V_M_ 00 NV_0.U_V_M_ 00 0 NV_0.U_V_M_ 00 NV_U_V_K_ 00 F F F F PX_IOVQ0 PX_IOVQ PX_IOVQ PX_IOVQ PX_IOVQ PX_IOVQ PX_IOVQ PX_IOVQ PX_IOVQ PX_IOVQ PX_IOVQ0 PX_PLLV PX_PLLV PX_PLLN V_LP V_LP V_LP V_LP V_LP V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ POWR V0 V V V V V V V V V V V V V V0 V V V V V V V V V V V V K K N N N N N N0 P R T T T T U U U U U V V W W W Y Y Y0 NV_0.U_V_Y_Y 00 0 NV_0.U_V_M_ 00 NV_.U_0V_Y_Y 00 NV_0.U_V_M_ 00 NV_U_.V_M_ 00 NV_0.U_V_M_ 00 NV_U_.V_M_ 00 NV_V NX.V P + NV_0U_.V_ RTP0M FOXONN N_000P_0V_K_ 00 V (R/I/ROM) OF HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of

29 ecoupling for T-U MMORY +_VRUN Place around the MM +_VRUN. +_VRUN ecoupling for T-U MMORY Place around the MM NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 0 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 0 NV_0U_.V_M 00_XR NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 0 NV_0U_.V_M 00_XR NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_000P_0V_M_ 00 +_VRUN NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_000P_0V_M_ 00 NV_000P_0V_M_ 00 NV_0.U_V_M_ 00 NV_000P_0V_M_ 00 NV_000P_0V_M_ 00 NV_000P_0V_M_ 00 FOXONN VRM (R) OF HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of

30 ecoupling for T-U MMORY +_VRUN Place around the MM NV_0U_.V_M 00_XR NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 +_VRUN. ecoupling for T-U MMORY +_VRUN Place around the MM 0 NV_0.U_V_M_ 00 0 NV_0.U_V_M_ 00 0 NV_0.U_V_M_ 00 0 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_000P_0V_M_ 00 0 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 +_VRUN 0 NV_000P_0V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_000P_0V_M_ 00 NV_0.U_V_M_ 00 0 NV_0U_.V_M 00_XR 0 NV_0.U_V_M_ 00 NV_0.U_V_M_ NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 0 NV_000P_0V_M_ 00 NV_000P_0V_M_ 00 NV_000P_0V_M_ 00 FOXONN VRM (POWRYP) OF HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet 0 of

31 ecoupling for -U MMORY +_VRUN Place around the MM +_VRUN. +_VRUN ecoupling for -U MMORY Place around the MM +_VRUN NV_000P_0V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 0 NV_0.U_V_M_ 00 0 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 0 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 0 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0U_.V_M 00_XR NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0U_.V_M 00_XR NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_000P_0V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 0 NV_000P_0V_M_ 00 NV_000P_0V_M_ 00 NV_000P_0V_M_ 00 0 NV_000P_0V_M_ 00 FOXONN VRM (R) OF HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of

32 ecoupling for -U MMORY +_VRUN Place around the MM NV_0.U_V_M_ 00 +_VRUN. ecoupling for -U MMORY +_VRUN Place around the MM 0 NV_000P_0V_M_ 00 NV_0.U_V_M_ 00 NV_000P_0V_M_ 00 NV_000P_0V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 0 NV_0.U_V_M_ 00 +_VRUN NV_0U_.V_M 00_XR NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0U_.V_M 00_XR 0 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 0 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 0 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 0 NV_000P_0V_M_ 00 NV_000P_0V_M_ 00 NV_000P_0V_M_ 00 FOXONN VRM (POWRYP) OF HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of

33 _V_T# PN0YR _OUT PN0YR Y_OUT 0 PN0YR NV_RN NV_RN These compoent close to -Video connector within 00 mil R 0_F 00 0R-00MHZ_00 MMZ00T 0P_0V_J_N 00 0P_0V_K_ 00 -VIO ONNTOR P_0V_K_N 00 Y_OUT _OUT _V_T# Q +VRUN R N_.K_J 00 Q N_TU +VRUN R N_.K_J 00 N_TU NV_R R 0_F 00 L 0R-00MHZ_00 MMZ00T 0P_0V_J_N 00 0P_0V_K_ 00 P0 HP has level shift function, so backup this circuit hange Q,Q,R,R to N emi-pnp ircuit N_MVHFT (HMI) U0 NV_HMI_T_ MI +VRUN XT_V_N R 0_J 00 emi-pnp( IN) +VRUN 0 P_0V_K_N 00 L N Y N N NV_HMI_T_ NV_HMI_T_ 0, NV_R -VIO RPTL ONN_P FOX_MH--F R 0K_J 00 XT_V_N R0 R0 V_RT_T# (RT) V_RT_T# _V_T# (VIO) 0K_J 00 0K_J 00 U MVHFT FOXONN -VIO/emi-PnP HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of

34 0/ elete R0 for it is no use +VRUN _HIFT_+VRUN +VRUN Q0 V_RT_T# V_RT_T# 0 N_XT_V_N TPT +VRUN 0 NV_I_L emi-pnp( out) TU 0 NV_I_ NV_HYN NV_VYN Place near by RT onnector NV_I_L NV_I_ NV_HYN NV_VYN 0 0.U_V_Y 00_YV J_R J_LU J_RN U V_VIO V_ VIO_ V_YN VIO_ VIO_ YP 0 _IN _IN _OUT YN_IN YN_IN M00-0QR _OUT YN_OUT YN_OUT N 0.U_V_Y 00_YV _YV 0.U_V_Y M_RT_LK M_RT_T ecrease _HIFT_+VRUN ripple noise dd a () uf cap for _HIFT_+VRUN V_HYN Layout place close U pin V_VYN 0 0.U_V_Y 00_YV U_0V_K 00_XR _HIFT_+VRUN NV_LU / MOR side suggest to support old RT, so add F,L and F NV_LU V-0._0 0L0 RT_+VRUN_F L -00MHZ_0 HKF-0T0 RT ONNTOR +VRUN _HIFT_+VRUN M_RT_LK NV_RN NV_R L R-00MHZ_00 M000 N_0.0U_V_K_ 00 N 0 MPT R.K_J 00 NV_RN NV_R R 0_F 00 R 0_F 00 L L R-00MHZ_00 M000 R-00MHZ_00 M000 0P_0V_J_N 00 0P_0V_J_N 00 M_RT_LK V_RT_T# TP0MIL TP_V_I VYN RT_+VRUN J_LU HYN M_RT_T J_RN TP00 MIL J_R TP_V_I0 0 0 PTH NPTH NPTH PTH Z-N0-F V_HYN V_VYN R 0._F 00 R 0._F 00 HYN P_0V_J_N 00 VYN P_0V_J_N 00 _HIFT_+VRUN 0P_0V_J_N 00 R.K_J 00 M_RT_T R 0_F 00 0P_0V_J_N 00 / hange R,R from 0ohm to 0ohm for meet M00-0 termination pec 0P_0V_J_N 00 FOXONN RT HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of

35 INVRTR_V LV ONNTOR Place 0 and close to N. TOUT INVRTR_OOT N_0.U_0V_K_ 00 R0 0_J 0 R0 N_0_J 0 U_V_K 00_XR INVRTR_V ackup Inverter boost circuit and use TOUT as INVRTR_V hange R0 from N to mount hange R0 from mount to N 0 0.U_0V_K_ 00 0 NV_RJ INV_N_ NV_RJ U0,U,U can use ON (MVH0FT) H.H. PN:-MVH-0 U0 +VRUN INVRTR ONNTOR H0W INV_NL INV_RJ R 0K_J 00 INVRTR_V N MFIX MFIX TO HR ONN_P FOX_H0 hange net name from LV_PIO to MM_MO MM_MO# NV_O_LKIN- NV_O_LKIN+ NV_O_RXIN0- NV_O_RXIN0+ NV_O_RXIN- NV_O_RXIN+ NV_O_RXIN- NV_O_RXIN+ NV_VN_RXIN0- NV_VN_RXIN0+ NV_VN_RXIN- NV_VN_RXIN+ NV_VN_RXIN- NV_VN_RXIN+ NV_VN_LKIN- NV_VN_LKIN+ LV MM_N# MM_MO# NV_O_RXIN- NV_O_RXIN+ NV_O_RXIN0- NV_O_RXIN0+ NV_O_LKIN- NV_O_LKIN+ NV_VN_RXIN0- NV_VN_RXIN0+ NV_VN_RXIN- NV_VN_RXIN+ NV_O_RXIN- NV_O_RXIN+ NV_VN_RXIN- NV_VN_RXIN+ NV_VN_LKIN- NV_VN_LKIN MFIX MFIX NPTH UMMY P MFIX MFIX UMMY P NPTH N FP RPTL ONN_0P FOX_0-0-F LV, LIIN# 0 NV_INV_N +VRUN U LIIN# NV_INV_N H0W 0 INV_N_ LV INV_N_ NV_INV_N +VRUN U H0W INV_NL R0 0K_J 00 INV_NL,0 Use H/W selection to enable MM function. hange R,R from.k to 0ohm MM_N# MM_N# H: MM isable L: MM nable R N_0_J 00 R 0_J 00.U_0V_Y_Y U_V_Y_Y 00 0.U_V_Y_Y 00 Place 0 close to N urrent limit is from. to.. PNL I W K_J 00 YTM_I0 R H0-_W-LI LI0 0 LI 0 LI 0 +VLW R 00K_J 00 YTM_I0 0 NV_LV_N# +VRUN R K_J 00 +VRUN 0.U_V_Y 00_YV U IN IN N N OUT OUT OUT O PU LV 00 NV_0.U_V_Y_Y Q FNP_NL R _J 00 +VRUN IHR R K_J 00 Q MMT0 R.K_J 00 R 00 0K_J NV_LV_N# Type ize Vender evice Name Panel I heck[..0] WX+ " wide L.PHILIP LPWP-TL Lamps(New) 00 dd R,R for Instant On function been used again WX+ " wide L.PHILIP LPWP-TL Lamps(New) 00 FOXONN LV WUX " wide HRP LQ0ML Lamps(New) 00 WUX " wide HRP LQ0ML Lamps(Old) 0 HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of

36 +VRUN +VRUN +VRUN (TM inputs equalization control) P,P0 onfiguration 00: d, 0: d, 0: d, : 0 d R NV_0K_J 00 R N_0K_J 00 R N_0K_J 00 R NV_0K_J 00 NV_HMI_P0 NV_HMI_P HMI_RT_N# HMI_I_N# 0U_.V_Y 00_YV R0 N_0K_J 00 R NV_0K_J 00 R NV_0K_J P_0V_M 00_XR U_0V_Y_Y U_V_M 00_XR +VRUN 0 N_U_0V_Y_Y 00 NV_0.U_V_Y 00_YV NV_TM_0- NV_TM_0+ NV_HMI_TX- NV_HMI_TX+ NV_TM_- NV_TM_+ NV_TM_- NV_TM_+ NV_0.U_V_Y 00_YV NV_TM_0- NV_TM_0+ NV_TM_- NV_TM_+ NV_HMI_TX- NV_HMI_TX+ TM_+ TM_- +VRUN_HMI NV_0.U_V_Y 00_YV L NV_R-00MHZ_00 FMJHM0-T 0 N_ IN_- IN_+ V_ IN_- IN_+ N_ IN_- IN_+ V_ IN_- IN_+ THRML P NV_HMI_P0 NV_HMI_P HMI_I_N# R NV F 00 NV_HMI_T_ 0 N_ TT0 TT V N# N_ HP_INK _INK L_INK PR V_ O# N_ V_ P0 P N_ RXT HP L RT_N# V_ N_ NV_HMI_T_ 0 HMI_RT_N# U N_ OUT_- OUT_+ V_ OUT_- OUT_+ N_ OUT_- OUT_+ V_ OUT_- OUT_+ 0 NV_P0 NV_0.U_V_Y 00_YV TM_0- TM_0+ TM_- TM_+ HMI_TX- HMI_TX+ NV_TM_- NV_TM_+ TM_- TM_+ NV_0.U_V_Y 00_YV TM_+ TM_- TM_0+ TM_0- HMI_TX+ HMI_TX- NV_0.U_V_Y 00_YV 0.0U_V_M 00_XR 000P_0V_M 00_XR HTX+ HTX- L N_0R-00MHZ_0._0.R M0H-00-P-T R NV_0_J 00 HTX+ HTX- L N_0R-00MHZ_0._0.R M0H-00-P-T R NV_0_J 00 R NV_0_J 00 HTX+ HTX- L N_0R-00MHZ_0._0.R M0H-00-P-T R NV_0_J 00 R0 NV_0_J 00 HTX0+ HTX0- L N_0R-00MHZ_0._0.R M0H-00-P-T R NV_0_J 00 R NV_0_J 00 ata line capacitance to N need less than 0pF, so those parts need close to HMI connector R NV_0_J 00 0U_.V_Y 00_YV 0, NV_HMI_T_ dd HMI equalizer for M0 long trace issue ost down evaluation hange R,R from N_ to NVPMH_, hange R0,,U from NVPMH_ to N HMI capacitance to N need less than 0pF,so those parts need close to HMI connector HMI_+VRUN R NV_0_J 00 NV_I_L HMI_I_L R NV_0_J 00 NV_I_ HMI_I_ 0 NV_I_L 0 NV_I_ NV_HMI_T_ NV_I_L NV_I_ R N_0_J 00 U 0 V O# N N_NTPW R0 NV_00K_J 00 +VRUN HMI_I_L HMI_I_ U HMI_ LIN N 0 HMI_+VRUN_MP N LIN NV_HMI_T_ V N LIN N N LIN NV_Rlamp0M N_U_0V_Y_Y 00 HMI_L 0 HMI_ HMI_I_ HMI_I_L HTX+ HTX- HTX0+ HTX0- HMI_L NV_HMI_T_ +VRUN +VRUN HMI ONNTOR HMI_ Q NV_UPT HMI_L Q NV_UPT NV_HMI RPTL_P FOX_QJ-FF-F / hange new HMI connector P/N change from N-0000-MK0 to N-0000-MK0 N0 ata+ ata- TM ata hield ata0+ ata0- TM lock hield L / round Hot Plug etect NPTH NPTH TM ata hield ata+ ata- TM ata0 hield TM lock+ TM lock- HTX+ HTX- HTX+ HTX- HMI_ HMI_+VRUN PVT hange to -HUP-T000 HMI_ R0 NV_.K_F 00 HMI_L R0 NV_.K_F 00 0 Reserved +V Power PTH 0 PTH PTH PTH 0 NV_HUPT +VRUN FOXONN HMI +VRUN HMI_+VRUN_F F NV_V-0._0 M0P0TF / Replace F by 0. fuse for meet HMI pec 0 NV_HH-0PT HMI_+VRUN L NV_R-00MHZ_00 FMJHM0-T HMI_+VRUN NV_0.U_V_Y 00_YV HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of N_0.U_V_M_ 00

37 MFIX MFIX MFIX MFIX pecial mini stereo jack JTVN_00_J JTVN_00R-00MHZ_00 R 00 LM0N UIO_IN_L UIO_IN_L_ L UIO_IN_R UIO_IN_R_ JTVN_00_J JTVN_00R-00MHZ_00 L VIO_OMP R 00 LM0N JTVN_00R-00MHZ_00 L LM0N VIN_Y VIN_ -VIO IN N_0P_0V_J_N UIO_IN_R UIO_IN_L _W _W0 _RT _N _LK _N _IO _N _V _V 00 JTVN_00R-00MHZ_00 LM0N L VIN_Y_ L VIN JTVN_00R-00MHZ_00 LM0N JTVN_PN0YR N_0P_0V_J_N JTVN_PN0YR 0 N_0P_0V_J_N 00 N N_0P_0V_J_N 00 N_0P_0V_J_N VIO_OMP VIN_T# _W _W0 _RT _N _LK _N _IO _N _V _V LN_FF_0P FOX_RF00-00-F 00_NPO JTVN_P_0V_J 00_NPO N_PN0YR UIO F =.MHz VIO F =.MHz VIN_Y_N TV tuner "VIN_T#" signal no use. hange R0, to N 0 JTVN_PN0YR JTVN_P_0V_J N _LK _W _W0 _RT _IO _N _V UIO_IN_L_ UIO_IN_R_ VIO_OMP_ JTVN_-VIO RPTL ONN_P PLK_MINI FOX_MH--F N 00 VIN_T#_ VIN_T# R0 N_0_J Y N N VIN N VIN_Y VIN_ LN_FF_0P FOX_RF00-00-F JTVN_PN0YR JTVN_PN0YR 00_NPO JTVN_0P_V_K TV-TUNR not support LKRUN VIN_Y_N VIN N FT Test Pad TP 00_NPO JTVN_0P_V_K 00 TP TP TP TP TP TP0 tpct_00 tpct_00 tpct_00 tpct_00 tpct_00 tpct_00 tpct_00 N_0P_0V_J_N 00_NPO JTVN_00P_0V_K N JTVN_UIO JK_P R FOX_JL_00_TR L V V_IN_N JTVN_PN0YR JTVN_PN0YR 0 LN_0.U_V_Y_Y 00 R N J 00 +VRUN_TV (.V) +VRUN_TV N_P_0V_K_N 00 R0 JTVN_0_J 00 +VRUN_TV (.V) V_IN_N INT_PIRQ# VIN_Y_N PI_RQ#, PI_/#, PI_/#, PI_IRY# 0,,, PM_LKRUN#, PI_RR#, PI_PRR#, PI_/# LN_0.U_V_Y_Y 00 LN_0.U_V_Y_Y 00 JTVN_PN0YR V_IN_N V_IN_N +VRUN_TV INT_PIRQ# VIN_Y PLK_MINI PI_RQ# PI_ PI_ PI_ PI_ PI_/# PI_ PI_ PI_ PI_ PI_/# PI_IRY# PM_LKRUN# PI_RR# PI_PRR# PI_/# PI_ PI_ PI_0 PI_ PI_ PI_ VIO_OMP PI_ PI_ UIO_IN_L LN_0.U_V_Y_Y 00 LN_0.U_V_Y_Y 00 +VRUN LN_0.U_V_Y_Y 00 TV TUNR ONN R N_0_J 00.VUX_R N TIP PMJ- PMJ- PMJ- PMJ- L_RNP L_RNN HN INT#.V_ VIN_Y VIN_Y_N LK ROUN_ RQ#.V_ ROUN_ RRV_ /# ROUN_ ROUN_ /# IRY#.V_ LKRUN# RR# ROUN_ PRR# /# ROUN_ 0 ROUN_.V_ VIO_OMP V_ 0 VIO_OMP_N 0 _YN 0 _T_IN 0 _IT_LK 0 _O_I# MO_UIO_MON UIO_N_R Y_UIO_OUT Y_UIO_OUT N UIO_N_L UIO_IN_L V LN_MINI PI ONN_xP FOX_0-N-F LN_0.U_V_Y_Y 00 MFIX NPTH NPTH MFIX +VRUN RIN PMJ- PMJ- PMJ- PMJ- 0 L_YLP L_YLN RRV_ V_ INT# 0 VIN_.VUX_ RT#.V_ NT# 0 VIN N PM# RRV_ 0.V_ 0 IL ROUN_ 0 0 PR 0 ROUN_ FRM# TRY# TOP#.V_ 0 VL# ROUN_ 0 ROUN_ /0#.V_ 0 0 THRML_ONTROL VIN_N# 00 ROUN_ 0 MN 0 _T_OUT 0 _O_I0# 0 _RT# 0 UIO_IN_R ROUN_ Y_UIO_IN Y_UIO_IN N UIO_N 0 MPIT#.VUX_ LN_0.U_V_Y_Y 00 +VRUN +VRUN_TV (.V) INT_PIRQ# VIN_.VUX_R PI_RT# PI_NT# PI_PM# R_L PI_0 PI_ PI_ PI_ MINI_IL PI_0 R LN_00_J 00 PI_ PI_0 PI_PR PI_ PI_PR, PI_ PI_FRM# PI_TRY# PI_TOP# PI_VL# PI_ PI_ PI_ PI_ PI_/#0 PI_ PI_ PI_ PI_0 THRML_TL_ VIN_T# UIO_IN_R.VUX_R +VRUN_TV FOXONN MINI-PI ONN. LN_0.U_V_Y_Y 00 ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of INT_PIRQ# PI_RT#,, PI_NT# VIN N PI_PM#, R_L PI_FRM#, PI_TRY#, PI_TOP#, PI_VL#, TP0 MIL PI_/#0, PI_[..0], HON HI PRIION IN. O., LT. P - R& ivision

38 +VRUN +VRUN +VRUN PI_FRM# PI_TOP# PI_RR# PI_TRY# PI_VL# PI_RQ# PI_LOK# PI_PRR# 0_0PR /0 el PI_RQ# Net INT_PIRQ# INT_PIRQ# INT_PIRQ# PI Pullups RP0 0_0PR.K RP0.K RP0.K 0_0PR +VRUN PI_RQ#0 INT_PIRQF# INT_PIRQ# INT_PIRQ# +VRUN PI_RQ# PI_IRY# +VRUN INT_PIRQ# INT_PIRQH# PI_RQ# R 0_J 00 INT_PIRQF#_R INT_PIRQ#_R R 0_J 00 /0 el PI_RQ# Net, PI_[..0] INT_PIRQ# INT_PIRQ# INT_PIRQ# INT_PIRQ# PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ INT_PIRQ# INT_PIRQ# INT_PIRQ# INT_PIRQ# F F 0 U PI Interrupt I/F PIRQ# PIRQ# PIRQ# PIRQ# IHM-QM_ RQ0# NT0# RQ#/PIO0 NT#/PIO RQ#/PIO NT#/PIO RQ#/PIO NT#/PIO /0# /# /# /# IRY# PR PIRT# VL# PRR# PLOK# RR# TOP# TRY# FRM# PLTRT# PILK PM# PIRQ#/PIO PIRQF#/PIO PIRQ#/PIO PIRQH#/PIO F 0 F F0 0 F F PI_RQ#0 PI_NT#0 PI_RQ# PI_NT# PI_RQ# PI_NT# PI_RQ# PI_NT# PI_/#0 PI_/# PI_/# PI_/# PI_IRY# PI_PR PI_RT# PI_VL# PI_PRR# PI_LOK# PI_RR# PI_TOP# PI_TRY# PI_FRM# PLT_RT# LK_IHPI PI_PM# INT_PIRQ#_R INT_PIRQF#_R INT_PIRQ# INT_PIRQH# ifference IH&IH.el RQ/NT,RQ/NT.hange trap Pin station(nt#-->nt0#) MIL TP MIL TP0 PI_RQ# PI_NT# PI_/#0, PI_/#, PI_/#, PI_/#, PI_IRY#, PI_PR, PI_RT#,, PI_VL#, PI_PRR#, PI_RR#, PI_TOP#, PI_TRY#, PI_FRM#, PLT_RT#,,,,,,,,, LK_IHPI PI_PM#, R 0_J 00 R N_0_J 00 INT_PIRQ# NT0# is trap Pin For oot IO election. It's used Integrated pull_up / IH trap Pin change from IH NT# trap for oot-io LP(efault) NT0# Hi PI_# Hi PI Hi LOW PI LOW Hi 0/0/0 hange LV_PIO Net to MM_ontrol MM_MO# MM_N# PI_RQ#0 PI_NT#0 /0 New add High KU HRP panel MM function / hange R to no stuff +VLW U_O# U_O# U_O# U_O# 0 RP 0K 0_0PR PI_# PI_LK PI_MOI PI_MIO TP MIL It's used 0K Integrated pull_up PI_0# is Output Pin PI_# is trap Pin For oot IO election. It's used Integrated pull_up U_O#0 U_O# U_O# U_O# LN_RXN LN_RXP LN_TXN LN_TXP XPR_RXN XPR_RXP XPR_TXN XPR_TXP MINI_RXN MINI_RXP MINI_TXN MINI_TXP +VLW R0 0K_J 00 R0 0K_J U_V_M_ U_V_M_ 00 0.U_V_M_ 00 0.U_V_M_ 00 0.U_V_M_ 00 0.U_V_M_ 00 TP0 MIL TP0 MIL TP0 MIL TP00 MIL TP MIL TP MIL TP MIL TP MIL TP0 MIL TP0 MIL TP0 MIL TP0 MIL TP0 MIL TP0 MIL TP0 MIL TP0 MIL U_O#0 U_O# U_O# U_O# U_O# U_O#0 U_O# U_O# U_O# U_O# U_O# U_O# U_O# U_O# U_O# LN_TXN_ LN_TXP_ XPR_TXN_ XPR_TXP_ MINI_TXN_ MINI_TXP_ TP_PI_LK TP_PI_0# TP_PI_# TP_PI_MOI TP_PI_MIO P P N N M M L L K K J J H H F F F H U PRN PRP PTN PTP PRN PRP PTN PTP PRN PRP PTN PTP PRN PRP PTN PTP PRN PRP PTN PTP PI-xpress PRN/LN_RXN PRP/LN_RXP PTN/LN_TXN PTP/LN_TXP PI_LK PI_0# PI_# PI_MOI PI_MIO J O0# O#/PIO0 O#/PIO O#/PIO F O#/PIO O#/PIO O#/PIO0 J O#/PIO O# O# IHM-QM_ PI irect Media Interface U MI0RXN MI0RXP MI0TXN MI0TXP MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MI_LKN MI_LKP MI_ZOMP MI_IROMP V V U U Y Y W W T T Y Y UP0N UP0P UPN H UPP H UPN H UPP H UPN J UPP J UPN K UPP K UPN K UPP K UPN L UPP L UPN M UPP M UPN UPP UPN UPP URI# URI M M N N F F MI_RXN0 MI_RXP0 MI_TXN0 MI_TXP0 MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP LK_PI_IH# LK_PI_IH MI_OMP U_PN0 U_PP0 U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP R URI R._F 00 U_PN0 U_PP0 U_PN U_PP U_PN U_PP MIL TP0 MIL TP0 U_PN U_PP U_PN U_PP MIL TP0 MIL TP0 U_PN U_PP U_PN U_PP U_PN U_PP._F 00 MI_RXN MI_RXP MI_TXN MI_TXP Place within 00 mils of IH and don't routing next to high speed signals MI_RXN0 MI_RXP0 MI_TXN0 MI_TXP0 MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP LK_PI_IH# LK_PI_IH Place within 00 mils of IH U Port0 -- U Port0 U Port -- U Port U Port -- U Port(udio oard) U Port -- X U Port -- luetooth U Port -- xpress ard U Port -- X U Port -- amera (0/ modify) U Port -- OI U Port -- IR / updata base on MOR side suggest FOXONN +_VRUN IH-M( PI/U ) / HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of

39 RTRT# IH-M Internal VR nable trap (Internal VR for Vccus_0, Vccus_, VccL_) VRT IH-M LN00_LP trap (Internal VR for VccLN_0 and VccL_0) VRT VccRT HR_P FOX_H0 +V N 0 Min : ms IH datasheet error, PIO is not truer PIO Pin, IO can't control it's action hange _OUT from IH PIO to PIO IH pin H(PIO) add TP0 IH pin (PIO) del TP, link to X-U conn. R _OUT 0K_J 00 00V-0-LF R0 _F 00 VRT R R _F 00 M_J 00 RT_T_PWR0 T_L# +_V_PI +VLW +VRUN The traces inside this block should be wider. No digital signals routed under XTL QM00000 U_.V_M_ 00 P_0V_K_N 00 LK_KX R K_F 00 R0._F 00 R0 0K_J 00 T_RXN0 T_RXP0 T_TXN0 T_TXP0 T_RXN T_RXP T_TXN T_TXP 0.KHZ_.P_0PPM 00 P_0V_K_N 0/ F suggest LN_OK#/PIO can be left as N if internal LN is not used R0 N_0K_J 00 U_0V_Y 00_YV Y OPN_JUMP_OPN P H_UIO_TIN0 0 H_M_TIN H_UIO_TIN _OUT trap Pin mils R N_0_J 00 T_RXN_ R N_0_J 00 T_RXP_ TP_T_TXN TP MIL TP_T_TXP TP MIL LK_PI_T# Place close to IH LK_PI_T Within 00 mils of the IHM,and avoid routing next to clock pins. LK_KX R 0M_J 00 TP0 MIL TP00 MIL TP0 MIL TP0 MIL TP0 MIL TP0 MIL TP0 MIL TP0 MIL 00P_V_K_ 00 00P_V_K_ 00 00P_V_K_ 00 00P_V_K_ 00 00P_V_K_ P_V_K_ 00 00P_V_K_ 00 00P_V_K_ 00 NRY_T IH_ITLK IH_YN IH_TO M_INTRUR# INTVRMN LN00_LP TP_LN_RX0 TP_LN_RX TP_LN_RX TP_LN_TX0 TP_LN_TX TP_LN_TX LN_OMP TP_PIO TP MIL T_RXN0_ T_RXP0_ T_TXN0_ T_TXP0_ T_RXN_ T_RXP_ T_TXN_ T_TXP_ TRI R0._F 00 / R swap from LK_KXR to LK_KX U R LK_KX_R RTX F 0_J 00 RTX RTRT# F RTRT# 0 0 H J J 0 F0 F F H H J J INTRUR# F INTVRMN LN00_LP TP_LN_LK LN_LK TP_LN_RTYN LN_RTYN LN_RX0 LN_RX LN_RX LN_TX0 LN_TX LN_TX LN_OK#/PIO LN_OMPI LN_OMPO H_IT_LK H_YN IH_RT# H_RT# H_UIO_TIN0 J H_M_TIN H_IN0 H H_UIO_TIN H_IN H TP_H_IN H_IN TP MIL H_IN H_OUT H_OK_N#/PIO H_OK_RT#/PIO TL# T0RXN T0RXP T0TXN T0TXP TRXN TRXP TTXN TTXP F TRXN F TRXP TTXN TTXP T_LKN T_LKP TRI# TRI IHM-QM_ IH LN / LN RT I PU LP T INTVRMN FWH0/L0 FWH/L FWH/L FWH/L FWH/LFRM# LRQ0# LRQ#/PIO 0T 0M# PRTP# PLP# FRR# PUPWR/PIO INN# INIT# INTR RIN# NMI MI# TPLK# THRMTRIP# TP # # IOR# IOW# K# IIRQ IORY RQ F F V U V T V T T T R T V V U V U Y Y W W Y Y Y W Low= Internal VR isabled High= Internal VR nabled(efault) F F F 0 H LP_0 LP_ LP_ LP_ LP_FRM# LP_RQ#0 LP_RQ# H_0T H_0M# H_PRTP# H_PLP# H_PWR H_INN# H_INIT# H_INTR H_RIN# H_NMI H_MI# H_TPLK# PM_THRMTRIP_R H_TP I_P0 I_P I_P I_P I_P I_P I_P I_P I_P I_P I_P0 I_P I_P I_P I_P I_P I_P0 I_P I_P I_P# I_P# I_PIOR# I_PIOW# I_PK# INT_IRQ I_PIORY I_PRQ INTVRMN I_P[0..] LP_0, LP_, LP_, LP_, R0 K_F 00 LP_FRM#, LP_RQ#0 H_0M# H_PRTP#,, H_PLP# H_PWR H_INN# H_INIT# H_INTR H_NMI H_MI# H_TPLK# I_P0 I_P I_P I_P# I_P# I_PIOR# I_PIOW# I_PK# INT_IRQ I_PIORY I_PRQ +_0VRUN +_0VRUN R _J 00 R _J 00 I_P[0..] H_RIN# H_0T LN00_LP H_FRR# Low= Internal VR isabled High= Internal VR nabled(efault) +VRUN R 0K_J 00 +VRUN R0 0K_J 00 H_PRTP# H_PLP# H_INTR H_NMI H_MI# H_TPLK# H_TP LP_RQ# +VRUN +VRUN LN00_LP R N_0_J 00 Q N00W--F R00 K_F 00 MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP0 MIL TP MIL TP _RIN# _0T UIO ignal to ircuit Q N00W--F IH_ITLK R0 _J 00 R0 _J 00 R _J 00 H_M_ITLK 0 H_UIO_ITLK H_UIO_ITLK IH_RT# R0 _J 00 R0 _J 00 R _J 00 H_M_RT# 0 H_UIO_RT#, H_UIO_RT# R N_0_J 00 IH_TO R00 _J 00 R0 _J 00 R _J 00 H_M_TOUT 0 H_UIO_TO H_UIO_TO 0 H_M_YN H_UIO_YN H_UIO_YN R0 _J 00 R0 _J 00 R _J 00 R0 00 IH_YN N_K_J +VRUN FOXONN IH-M(LP,I,T)/ HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of

40 +VLW +VLW LI Pull High M_LK_U M_T_U LINKLRT# MLINK0 MLINK PM_RI# PM_U_TT# U_LK PM_U_TT# F _RT# PM_YRT# U_TT#/LPP# ULK 0MIL TP Q R0 0K_J 00 Y_RT# LP_# R PM_MUY# LP_# 00_J 00 PM_LP_# LP_# R 00_J 00,, PI_WK# PM_MUY# PM_YRT# MUY#/PIO0 LP_# F PM_LP_# LP_# R0 0_J 00 R0 0K_J 00 M_LRT# LP_# PM_LP_# N_N00 M_LRT# MLRT#/PIO TP_PIO / hange PIO from _OUT to TP R 0K_J 00 PM_TPPI# _TT#/PIO H 0MIL TP0 PM_TPPI# 0 TP_PU# TP_PI#/PIO IMVP_PWR_F TP_PU# TLOW# TP_PU#/PIO PWROK IMVP_PWR, R K_J 00 R.K_J 00 PM_LKRUN# H J 0 R LKRUN#/PIO PRLPVR/PIO 0_J 00 R 0_J 00,,, PM_LKRUN# PRLPVR, 0/0/0 hange R, R from.k to K _PI_WK# _PI_WK# TLOW# R K_J 00 INT_RIRQ WK# TLOW#,, INT_RIRQ F _THRM# RIRQ 0/ F suggest LINKLRT# THRM# PWRTN# PWRTN# onnect LN_RT# to N if no internal LN used. R N_0K_J00 VRMPWR J0 ee anta Rosa design guide table XTMI# VRMPWR LN_RT# H0 00 0K_J R0 R 0K_J 00 PM_RMRT_# TP 0MIL J WK_I# TP RMRT# PM_RMRT# R K_J 00 The spec K0 LK_N is high enable, R 0K_J 00 0/ F suggest 0 Port I/F: TP_PIO LK_PWR_IH TP 0MIL J not low enable, correct "#"mark wrong No stuff R. LINKLRT# can I_LP_PI# TH/PIO K_PWR LK_N H: LP bus J R 0_J 00 I_LP_PI# on schematic,hange IH pin be left as N if unused this function. RUNTIM_I# TH/PIO H MPWROK L: PI bus RUNTIM_I# /U pin net name from LK_N# +VRUN ee anta Rosa MOW WW XTMI# TH/PIO LPWROK MPWROK XTMI# OVT R PIO TP_LP_M# to LK_N J TP_PIO PIO LP_M# 0MIL TP TP0 0MIL TP_PIO TH0/PIO TP 0MIL H F L_LK0 _THRM# TP_PIO0 PIO L_LK0 L_LK R.K_F 00 TP 0MIL R.K_J 00 TP_PIO PIO0 L_LK L_LK TP000MIL 0 +VRUN INV_N_ LOK/PIO H F L_T0 INV_N_ RUNTIM_I# QRT_TT0/PIO L_T0 L_T TP00MIL QRT_TT/PIO L_T F L_T R.K_J 00 R N_.K_F 00 TLKRQ# LI TLKRQ#/PIO F L_VRF0_IH LI +VU INT_RIRQ LI LO/PIO L_VRF0 J H L_VRF_IH R.K_J 00 / hange PIO Net from M_PWRN to TP TP_PIO TOUT0/PIO L_VRF TP 0MIL 0 TOUT/PIO J R PM_LKRUN# H_PKR L_RT# L_RT#0 0.uF_0% _F H_PKR 0/ internal review R.K_J 00 PKR J TP_PIO 00 change +VU to +VRUN LPIO0/PIO 0MIL TP 00 MH_IH_YN# J J +VU=>Power on at I_LP_PI# MH_YN# LRT#/PIO0 IMVP_PH F WK_I# +VRUN=>Power off at R 0K_J 00 NTTT/PIO WK_I# J _RT# TP 0MIL TP WOL_N/PIO _RT# M_LK_U R.K_J 00 M_T_U R.K_J 00 +VRUN RP PM_RI# MLINK MLINK0 0K 00_PR R 0K_J 00 R 0K_J 00 R 0K_J 00 LI0 LI PIO +VU,,, M_LK_U,,, M_T_U LINKLRT# traps Pin J F, IMVP_OK,, OVT_# U MLK MT LINKLRT# MLINK0 MLINK RI# IHM-QM_ M Y PIO PIO MI T PIO locks Power MT ontroller Link R 0_J 00 R 0_J 00 R0 0_J HH-0PT LOO_L_N T0P/PIO J J0 PIO TP/PIO TP/PIO F LI TP/PIO MPWROK VRMPWR OVT R PM_RMRT_# LK LK LK_IH LK_U R0 0K_J 00 N_0.U_V_M_ LOO_L_N 0 LI0 LI LK_IH LK_U L_VRF ~=0.0V 00 R N F 00 R N_.K_F 00 R N_.K_F 00 eagle not support MT / hange +VRUN to +VWL +VLW +VU LI R 0K_J 00 LI R N_0K_J 00 / elete R, LW_PWR 0 HH-0PT IMVP_PWR_F Pull Low PM_RMRT# R 0K_J 00 IMVP_PWR R0 0K_J 00 INV_N_ R 0K_J 00 VRMPWR R 00K_J 00 M_LK_U M_T_U dds.h U V L V WP 0 PROM_OP-_x HTL0 +VRUN 0.U_V_M_ 00 R K_J 00 PM_YRT_J# YUTN H0-0PT P OPN_JUMP_OPN PM_YRT# 0.U_V_M_ 00 FOXONN IH-M( PIO) / HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet 0 of

41 +_VRUN +VLW R 0_J 00 +VLW +_VRUN +VRUN +_VRUN. for all V_ 0/0 hange LN Power from +VU to +RUN +VRUN 0.UF 0% 00V-0-LF 0.U_V_Y_Y 00 R 0_J 00 R _F 00 R0 0_J 00 R 00_J 00 +_VRUN VLNPLL 0/ F suggest May remove R, L. ue to no internal LN implemented, VLNPLL can connect to power without filter. +VRUN VRT 00V-0-LF 0.U_V_Y_Y 00 +_V_PI L0 VRF_U 0R-00M_0 HKF-T0 L 0UH_00 L0-00K R N F 00 P TP0ML 0U_.V_.U_0V_Y 00_YV + 0 0U_.V_Y 00_YV VRF 0/ hange 0 0.U_V_Y_Y 00 0.U_V_Y_Y 00 L N_UH_00 FI0F-R0K +VRUN U_0V_Y 0_YV 0/ F suggest hange to uf U_.V_M_ 00 0.U_V_Y_Y 00 VLNPLL N_0U_.V_Y 00_YV +_V_PI m m m 0 U_0V_Y 0_YV 0.U_V_Y_Y 00 TP MIL R _F 00 m U_0V_Y_Y 00 0m 0m m 0m m u VTPLL +V._LN_IH / IH dd.vrun Power(VLN_), hange Lan Power from VU to VRUN.U_V_Z 00_YV U_0V_Y_Y 00 0.U_V_Y_Y U_V_Y_Y 00 N_.U_V_Z 00_YV UF VRT T J F H J 0 F L L M M W F F 0 VRF[] VRF[] VRF_U V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [] F V [] F V [] V [] H V [] H V [] J V [] J V [] K V [] K V [0] L V [] L V [] L V [] M V [] M V [] N V [] N V [] N V [] P V [] P V [0] R V [] R V [] R V [] R V [] T V [] T V [] T V [] T V [] T V [] U V [0] U V [] V V [] V V [] V V [] W V [] Y V [] VTPLL V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [] V [] V [] V [] V [] V [] H V [] V [] V [] VUPLL V [0] V [] V [] V [] V [] V [] VLN_0[] VLN_0[] VLN_[] VLN_[] VLNPLL VLN_[] VLN_[] VLN_[] VLN_[] VLN_[] VLN_ IHM-QM_ +VRUN OR VP RX TX VP_OR I PI VPU U OR VPU LN POWR V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] F V_0[0] V_0[0] L V_0[0] L V_0[] L V_0[] L V_0[] L V_0[] L V_0[] M V_0[] M V_0[] P V_0[] P V_0[] T V_0[0] T V_0[] U V_0[] U V_0[] V V_0[] V V_0[] V V_0[] V V_0[] V V_0[] V VMIPLL V_MI[] V_MI[] V_PU_IO[] V_PU_IO[] V_[0] V_[0] R 0_J 00 R F V_[0] V_[0] V_[0] V_[0] F V_[0] V_[0] V_[0] V_[0] V_[] V_[] V_[] U V W W W Y V_[] V_[] V_[] V_[] V_[] V_[] V_[0] V_[] V_[] 0 V_[] V_[] F VH VUH VU_0[] VU_0[] VU_[] VU_[] VU_[0] VU_[0] VU_[0] VU_[0] VU_[0] VU_[0] J F0 J 0 H VU_[0] P VU_[0] P VU_[0] VU_[0] N VU_[] P VU_[] P VU_[] P VU_[] P VU_[] P VU_[] R VU_[] R VU_[] R VU_[] R VL_0 VL_ VL_[] VL_[] F0 VU_0 VU_ 0/ hange VccL_0 VccL_ 0.UF 0% m VMIPLL_IH 0.UF 0% 0.UF 0% 0.UF 0% 0.UF 0% 0.UF 0%. m 0m m m m MIL TP.U_0V_Y 00_YV 0.0U_0V_Y 00_YV MIL TP0 N_U_0V_Y_Y 00 R N_0_J 00 0.UF 0% 0 0.UF 0% MIL TP +VU 0.UF 0% 0.UF 0% L VMIPLL_IH_R UH_00 FI0F-R0K 0U_.V_Y 00_YV 0.UF 0% 0.UF 0% N_0.UF 0% N_0.UF 0% N_0.UF 0% 0.UF 0% m for all V_ m for all VU_ In non Intel MT systems, these rails should be powered at a minimun in 0-state since PI functionality is power from these wells. 0/ F suggest VL_ may connect to +VRUN, due to no imt implemented. FOXONN.U_0V_Y 00_YV N_0.0U_0V_Y 00_YV U_0V_Y 0_YV IH-M( POWR) / ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of 0.UF 0% 0.UF 0% R0 _F 00 +_0VRUN +_VRUN +_VRUN +_0VRUN +VRUN +VRUN +VLW +VLW HON HI PRIION IN. O., LT. P - R& ivision

42 (M0--0 )Mainoard (MX-) IH-M(N) / Friday, ugust, 00 ize ocument Number Rev ate: heet of HON HI PRIION IN. O., LT. P - R& ivision FOXONN U IHM-QM_ 0 F F F F F H0 H H H H F H H H H H H J 0 F F F F 0 H H H H H J J J J J J K K K K K L L L L L L L M M M M M M M M M M N N N N N N N N N N N N N N P P P P P P P P P R R R R R R R R R R T T T T T T T U U U U U U U U U U U V V V V W W W Y Y Y H H J J J J U K W V[00] V[00] V[00] V[00] V[00] V[00] V[00] V[00] V[00] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V_NTF[0] V_NTF[0] V_NTF[0] V_NTF[0] V_NTF[0] V_NTF[0] V_NTF[0] V_NTF[0] V_NTF[0] V_NTF[0] V_NTF[] V_NTF[] V[] V[0] V[] V[] V[] V[0] V[]

43 MFIX MFIX +VU 0R-00MHZ_00 LM0000 +V LN +V LN 0.U_0V_K 00_XR 0 U_V_M 0.U_0V_K 0.U_0V_K 0.U_0V_K 0.U_0V_K 0.U_0V_K 0_XR 00_XR 00_XR 00_XR 00_XR 00_XR VP_T +VRUN R 0_J 00 VP_LK TRL_ +V LN R.K_J 00 Q 0U_0V_M b e 00 00_XR c PT null +_V_V_LN 0.U_V_M_.K_J 00 VP_LK VP_T R R.K_J 00 L V N U 0.U_0V_K 00_XR 0 WP PROM_TOP-_K T0-0TU-. +_V_V_LN +V LN LN_RXP LN_RXN 0.U_V_Y_Y 00 LN_RXP_ 0.U_V_Y_Y 00 LN_RXN_ LN_TXN U TX_P 0 TX_N N N RX_N V VMIN_VLL TTMO VO_TTL V N N VP_T VO_TTL 0 V VP_LK PI_LK PI_ PI_I PI_O V N MIN[] MIP[] 0 N V +_V_V_LN MI- MI+ 0U_.V_Y_Y U_.V_M 00 00_XR 0.U_.V_K 00_XR 0.U_.V_K 00_XR 0.U_.V_K 00_XR 0 0.U_.V_K 00_XR 0.U_.V_K 00_XR 0.U_.V_K 00_XR 0.U_.V_K lose to chip 00_XR 0.U_.V_K 00_XR LN_TXP RX_P MIN[] MI- LK_PI_LN RFLKP MIP[] MI+ LK_PI_LN# RFLKN N +V LN N V L_Tn 0 L_LINK0/00n VO_TTL 0 N V V MIN[] MIP[] 0 MI- MI+ TRL_ R0.K_J 00 Q0 b e 00 c PT null 0.U_V_M_ 0U_0V_M 00_XR +_V_V_LN L_LINK000n V +V LN L_LINKn N thermal pad VO_TTL V TRL TRL RTn/TTPT WKn V VH(.V) WITH_VUX 0 LOM_ILn WITH_V VUX_VLL V XTLO XTLI RT MIN[0] MIP[0] 0-0-NNP_0 MI0- MI0+ Y XTLI XTLO 0 0U_0V_M U_0V_K 00_XR 00_XR 0.U_0V_K 00_XR 0.U_0V_K 00_XR 0.U_0V_K 00_XR 0.U_0V_K 00_XR 0.U_0V_K 00_XR TRL_ TRL_ +V LN R 0_J 00 XTLI_hip R.K_F 00 R 0_J 00 XTLI P_0V_J 00_NPO MHZ_0P_0PPM ITTI_L P_0V_J 00_NPO lose to chip,,,,,,,,, PLT_RT# 0,, PI_WK#.K_J R 00 XTLO +_V_V_LN L +_V_V_LN_ 0R-00MHZ_00 M P_V_K 00_XR 0 0 dd test point for FT Lan test 0.U_0V_K 00_XR L MI0+ TT MT MI0-0.U_0V_K 00_XR T+ MX+ T- MX- MI+ TT MT MI- 0.U_0V_K 00_XR T+ MX+ 0 T- MX- MI+ TT MT MI- 0.U_0V_K 00_XR T+ MX+ T- MX- 0 MI+ TT MT MI- T+ MX+ T- MX- :_0UH R R R R R R R0 R._F._F._F._F._F._F._F._F TR0P_RJ TR0N_RJ TRP_RJ TRN_RJ TRP_RJ TRN_RJ TRP_RJ TRN_RJ R0 _J 00 R _J 00 R _J 00 R _J 00 N_TR 00P_KV_K 0_XR FT Test Pad TRN_RJ TP0 tpct_00 TRP_RJ TP0 tpct_00 TRN_RJ TP0 tpct_00 TRP_RJ TP0 tpct_00 TRN_RJ TP0 tpct_00 TRP_RJ TP0 tpct_00 TR0N_RJ TP00 tpct_00 TR0P_RJ TP0 tpct_ U_V_Y_Y 0.U_V_Y_Y 0.U_V_Y_Y 0.U_V_Y_Y The Resistors and apacitors as close to LN ontroller as possible 0 N0 HR_P FOX_H0 TRN_RJ TRP_RJ TRN_RJ TRP_RJ TRN_RJ TRP_RJ TR0N_RJ TR0P_RJ 00P_KV_K 0_XR R M_F 00 FOXONN LN HON HI PRIION IN. O., LT. P - R& ivision N_TR ize ocument Number Rev (M0--0 )Mainoard (MX-) Friday, ugust, 00 ate: heet of

44 RP 0K 00_PR +V R 00K_J 00 +V LIIN# +VLW PWRW# +VLW KO KO KO KO TT_PR# TT_PR_# KO KO KO KO KO KO Q 00 +VLW N00W--F UNOK_RQ# XT_V_N XT_V_N PORT_T# PM_THRM# R 0K_J 00, LIIN# LIIN# K_Y_TT# T_WLN_W# R0 0K_J 00 TT_PR_# K_Y_I0# PWU,0 INV_NL R 0K_J 00 R 0_J 00 T_00 LK_M R K_J 00 T_M LK_00 LK_KM R K_J 00 +VRUN T_KM 00_RT# LK_TP LK_TP R 00K_J 00 T_TP T_TP PORT_T#,0 IMVP_PWR T_PR# W_IR0 0, LW_PWR R0 0_J 00 0 PWR Q K_Y_TT# N00W--F R N_0_J 00 PWR_IR# K_Y_I0# 00 / N_XT_V_N /W request MUT function change,0 R_LRT# from PIO to Keyboard matris TP MIL RUN_ON RUN_ON 0MIL TP0 (el R0 &MUT_W# on pin and ) 0, IMVP_OK R 0_J 00 T_00 T_00 LK_00 LK_00,0, OVT_# R 0_J 00 +VLW NH_# +VU +VRUN R00.K_J 00 Q N00W--F RP 0K 00_PR R N_0_J 00 RP 0K 00_PR R0 0K_J 00 IN_ +V +VLW,,, RUN_ON 0 PWRTN# R 00 0.U_V_Y_Y 00 0_J 00 0,, INT_RIRQ, LP_FRM#, LP_0, LP_, LP_, LP_ LK_KPI,0,, PM_LKRUN#,, U_PWR_0M LK_M LK_KM LK_TP,,,,,,,,, PLT_RT# T_M T_KM T_TP _RIN# _0T PWR R 00K_J 00 0 RUNTIM_I# PM_LP_# R 00K_J 00,0 RT# PM_LP_# R 00K_J 00 PM_LP_# R 00K_J 00 RUN_ON R 00K_J 00 KI0 U_ON R 00K_J 00 KI _PIO R0 00K_J 00 KI RUN_ON R 00K_J 00 KI XIO_F R 00K_J 00 KI KI RUN_ON R0 00K_J 00 KI KI, PWRW# NH#, IN N00W--F Q 0 PM_LP_# 0 PM_LP_# 0 PM_LP_# 0 PM_RMRT# 0 R_PWR RUN_ON W_IR00 RUN_PWR 0,, U_ON R 0_J INT_RIRQ LP_FRM# LP_0 LP_ LP_ LP_ LK_KPI PM_LKRUN# U_PWR_0M KI0 KI KI KI KI KI KI KI PLT_RT# _RIN# _0T RUNTIM_I# RT# PM_LP_# PM_LP_# PM_LP_# PM_RMRT# R_PWR W_IR00 RUN_PWR U_ON NH_# IN_ RUN_ON PWRTN# U V 0 0 K0F FN_L efinition Hi for FOXONN FN Low for MOR ooling Unit NLO_V XIO_F0 XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F0 XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F _PIO FN_TH LK_M R.K_J 00 T_M R.K_J 00 KO0 KO KO0/POK0 0 KO KO/POK R K_J 00 KO KO/POK KO KO/POK KO KO/POK XIO_F[..0] XIO_F0 KO KO/POK 0 XIO_F KO KO/POK XIO_F For version KO KO/POK 0 XIO_F KO KO/POK XIO_F signal "IPN_TP" 0 KO0 KO/POK XIO_F use KO0/POK0 XIO_F KO/POK XIO_F KO/POK 0 FR# KO/POK R# FR# FWR# KO/POK WR# FWR# IO# KO/POK IO# 0MIL TP MM# KO/POK MM# MM# KO/POK M_THRM_LK L M_THRM_LK,0 M_THRM_T PWU0 M_THRM_T,0 PWU L LK_M PWU 0 R 00_J 00 T_M 0 R 00_J 00 PWU XTMI# PWU PWM0/POW0 XTMI# 0 WK_I# PWU PWM/POW WK_I# 0 FN_PWM PWU/TIN PWM/POW/FNPWM FN_PWM PWU/TIN/FNF PWM/POW 0MIL PWM/POW TP0 _OFF PWM/POW 0MIL TP0 0 IMVP_VR_ON PWM/POW IMVP_VR_ON LOO_L_N_ PWM/POW/FNPWM LOO_L_N_ N N N N N N N RIRQ LFRM# L0 L L L LLK LKRUN#/PIO0 PIO0 LRT#/PIO KRT#/PIO0 0/PIO0 I# RT# KI0/PIK0 KI/PIK KI/PIK KI/PIK KI/PIK KI/PIK KI/PIK KI/PIK PLK PT PLK PT PLK PT 0/PI0 /PI /PI /PI /PI /PI /PI /PI PIO0 PIO0 TOUT/PIOF PIO0 PIO0/FNPWM/TT_TP PIO0/FNF/PLL_TP PIO0 PIO0 PIO0 PIO0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO V V V V V V V XIO#/PIO XIO#/PIO XIO#/PIO XIO#/PIO XIO#/PIO XIO#/PIO XIO#/PIO XIOF#/PIOF V N 0 0 0/PIO FNF/TOUT/PIO PLOK#/PIO FNLOK#/PIO ROLLLOK#/PIO0F NUMLOK#/PIO0 0/PO0 /PO /PO /PO /PO /PO /PO /PO IT0/PIO00 IT/PIO0 RX/PIO TX/PIO #/PIO0 XLKO _RT# 00_RT# UPN_L UPN_L POWR_L POWR_L TTRY HRIN L# TTRY HRIN L# R N_0_J 00 VIT_MUT# WLN_N T_ON, HW_POP_MUT_ +V PWRLIMIT# 0 R 0_J 00 OVT_FX# 0 RX RX TX TX FTUR_RT# FTUR_RT# KXLKO KXLKI XLKI 0 P_0V_J_N 00 0MIL TP0 R 0_J 00 R N_0M_J 00 Y RT_IR_ YTM_I0 YTM_I YTM_I YTM_I YTM_I YTM_I P_L# U_.V_M_ 00 0MIL TP0 YTM_I0 00 XIO_F[..0] ROLL_LOK_L# NUM_LOK_L# 0 P_0V_J_N 00 L 0.U_V_Y_Y 00 +VLW 0R-00MHZ_00 MMZ00T +VLW 000P_0V_K 00_XR.KHZ_.P_0PPM QM U_.V_Y_Y 00 FOR MI ysi0 "LogoL" definition nable : YTM_I0 is Low isable : YTM_I0 is High HH/HM(NVP) -- M VRM H(NVP) M(NVMM) L(NVML) H HM HH M MH L LH ysi ysi ysi ysi ysi NVH_00K_J R 00 NVML_00K_J R 00 NVH_00K_J R NVMM_00K_J R NVNOR_00K_J R R LO TO HIP N_000P_0V_K 00_XR R0 K_J 00 XIO_F XIO_F LW_ON,, 0.U_V_Y_Y 00 N_00K_J 00 R0 00K_J 00 R0 K_J 00 FN_TH + K K NN FOXONN R 0.U_V_Y_Y 00 K_J 00 NVMM_00K_J YTM_I R0 YTM_I YTM_I R N_00K_J00 N MFIX MFIX KI0 KI KI KO0 0 KO KO KI KO KO KO KO KO KO KI 0 KO KI KI KO0 KI KO KO KO KO KO HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev ate: Friday, ugust, 00 heet of NVHH_00K_J R (M0--0 )Mainoard (MX-) KO0 KO KO KO KO KO KO KO KO KO KI KI KO0 KI +V NVHH_00K_J R 00 NVML_00K_J 00 YTM_I R NVNW_00K_J 00 YTM_I R KO KO KO KO KO 00 R 00K_J 00 FP ONN_P FOX_0-000-F TP tpct_00 TP tpct_00 TP tpct_00 TP tpct_00 TP tpct_00 TP tpct_00 TP tpct_00 TP tpct_00 TP tpct_00 TP tpct_00 TP tpct_00 TP0 tpct_00 TP tpct_00 TP tpct_00 TP tpct_00 TP tpct_00 TP tpct_00 TP0 tpct_00 TP tpct_00

45 XIO_F[..0] XIO_F[..0] FLH IO +V XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F0 XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F U N 0 N N V V FLH_TOP-_M NLV00-0TP V XIO_F0 Q0 XIO_F Q XIO_F Q XIO_F Q XIO_F Q XIO_F Q 0 XIO_F Q XIO_F Q Q 0 Q Q0 Q Q Q Q XIO_F0 Q/- MM_M# # FR# O# FLH_RT# RT# RY/Y# FWR# W# YT# N 0 0.U_V_Y_Y 00 0/ hange FR# FWR# U_0V_Y_Y 00 +V R 0K_J 00 JI-0 +V N 0/0 elete FWH_INIT# net, ebug card have not use this net LP_0 LP_0,, LP_ LP_ LP_ LP_,, LP_ LP_ LP_FRM# LP_FRM#, LP_RQ#0 LP_RQ#0 I_LP_PI# 0 0 PM_U_TT# 0,,,,,,,,, PLT_RT# PLT_RT# PM_LKRUN# PM_LKRUN#,0,, 0,, INT_RIRQ INT_RIRQ PLK_JI R, PWRW# N_0_J 00 +VRUN 0 +VRUN +V PI_RT# PI_RT#,, RX RX 0MIL TP TX TX 0 _RT# 0 X-U XIO_F0 XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F0 XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F +V U XIO_F0 XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F MM# FR# FWR# R_INRT _OUT +V R_INRT R 0K_J 00 MM# MM_M# NHVR MFIX MFIX MFIX MFIX N TO ONN_x0P FOX_QT00-L0-F MFIX MFIX NPTH NPTH MFIX MFIX 0 0.U_V_Y_Y U_V_Y_Y 00 _OUT TO ONN_xP FOX_QT00-L0-F MM# R N_0_J 00 0/ t M0 MP don't use X-U N,U,R,0 need N R need stuff FOXONN Flash ROM + Jig-0 + XU HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev ate: Friday, ugust, 00 heet of (M0--0 )Mainoard (MX-)

46 +VRUN 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 +VRUN +VRUN T_TXP T_TXN T_RXN T_RXP T_TXP0 T_TXN0 T_RXN0 T_RXP NPTH MFIX MFIX MFIX MFIX MFIX MFIX MFIX MFIX MFIX MFIX MFIX0 NPTH N 0 FF ONN_P FOX_-00-F FOXONN T H RI HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of

47 / MOR side suggest IRQ and IORY pin add pull up resistance by +VRUN (N: R and R) Refer to M0 schematics. I_P[0..] I_P[0..] +VRUN +VRUN +VRUN +VRUN -ROM ONN O must Master H: lave L: Master +VRUN I_P# I_P0 I_P INT_IRQ I_PIORY I_PIOW# I_P# I_P0 I_P INT_IRQ I_PIORY I_PIOW# R.K_J 00 R N_.K_J 00 0 R.K_J 00,,,,,,,,, PLT_RT# O_N_ N_0.U_V_Y_Y 00 R N_.K_J 00 R R0 _J 00 0_J 00 TP0MIL I_P0 I_P I_P I_P I_P I_P I_P I_P O_RT# 00P_0V_K 00_NPO O_N_ L N_ N_ 0 L N_ N_ N_ N_ N_ +V_ +V_ +V_ +V_ 0 P# +V_ FX# FX# 0 PI# 0 INTRQ IO# IORY MK# IOW# N_ N_ IOR# 0 MRQ RT# UIO_N N_ UIO_L UIO_R PTH_ NPTH PTH_ NPTH N FOX_QTH00-HR-F TO ONN_0P 0 N_0.U_V_Y_Y 00 O_N_ 0.U_0V_Y_Y 00 I_P# I_P TP_PI IO# I_PK# I_PIOR# I_PRQ I_P I_P I_P I_P I_P I_P0 I_P I_P I_P I_P I_P I_P I_P I_P0 TP_PI VR FOXONN PT -ROM HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) N_0.U_V_Y_Y 00 0 N_0.U_V_Y_Y P_0V_M_ 00 I_P# I_P I_PK# I_PIOR# I_PRQ 0 0.U_V_Y_Y 00 R 0K_J 00 0.U_V_Y_Y 00 VR VR VR VR VR VR N_VPORT0000MV0_VR N_VPORT0000MV0_VR N_VPORT0000MV0_VR N_VPORT0000MV0_VR N_VPORT0000MV0_VR N_VPORT0000MV0_VR N_VPORT0000MV0_VR ate: Friday, ugust, 00 heet of

48 U, PI_[..0], PI_/#0, PI_/#, PI_/#, PI_/#, PI_PR PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_/#0 PI_/# PI_/# PI_/# R P U V W R0 U0 V0 R U V W V U R W W T T R P R R P N N N M M M M M W0 V U P U /0# /# /# /# PR PI interface Multifunction and Miscellaneous RI_OUT#/PM# MFUN0 MFUN MFUN MFUN MFUN MFUN MFUN _U_N# LK_ TT0 PHY_TT_M UPN# PKROUT L H H H J J J 0 F P P J H NONTN PI PI TP R 0K_J 00 PI R0 0K_J 00 R K_F 00 MIL R.K_J 00 +VRUN PI_PM#, INT_PIRQ# INT_PIRQ# INT_PIRQ# INT_RIRQ 0,, M_PWR_TRL_ M_PWR_TRL_M PM_LKRUN#,0,, LK_ +VRUN _PKOUT# PI_,, PI_RT#, PI_FRM#, PI_TRY#, PI_IRY#, PI_TOP#, PI_VL# PI R 00_J 00, PI_PRR#, PI_RR# PI_RQ#0 PI_NT#0 PLK_ NONTN R 0_J 00 R W V V U N R W L L L K K FRM# TRY# IRY# TOP# VL# IL PRR# RR# RQ# NT# PLK PRT# RT# lamp Voltage For PI (IO V/.V) VP VP VR_N# (IN.V/0m) VR_PORT VR_PORT P W K K K PI VRPORT PI 0.U_.V_K 00_XR 0 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_.V_K 00_XR +VRUN 0U_0V_Y 0_YV PIZHK PI R K_J 00 FOXONN PI (PI U) HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev ustom (M0--0 )Mainoard (MX-) Friday, ugust, 00 ate: heet of

49 +VRUN _V _V L 0-00MHZ_00 LMN +VRUN L 0R-00MHZ_00 M00 PI P P U U U V V (.V) V VPLL_ P R R K_J 00 PI 0U_0V_Y 0_YV 000P_0V_M_ 00 ilink ONN. 0U_0V_Y 0_YV This capacitor must be placed to I pin 000P_0V_M_ 00 ILINK U_V_Y_Y _L _ OTH R.K_F 00 OTH P T T VPLL_ L R0 R I a TP0P V TP0N W TP0P V TP0N TPI0 TPN TPP TPN W R W V W TP0+ TPI0 V NONTN TP TPP MIL NONTN TP MIL PI R0 K_J 00 PI R K_J 00 R._F N_0P_0V_J_N R._F U_V_K_ 00 R._F 00 OTH R.K_F R._F P_0V_J_N L TP+ TP- TP+ TP0- TP0+ TP0- TP- 0R-00MHZ_0R.0x.x. Place near PI. PTH TP0 TP0# TP0 TP0# PTH N RPTL ONN_P FOX_UV-WRP-F R R U U VPLL N N N TPI XO XI W R R PI 0.U_V_Y_Y 00 R 0_J 00 PI PI0 PI R M_J 00 Y P_0V_J_N P_0V_J_N PIZHK.MHZ_P_0PPM ITTI_L VRUN R.K_J 00 _L _ R.K_J 00 0.U_V_Y_Y 00 U V L V WP 0 PROM_OP-_x HTL0 L: R/W H: Read only FOXONN PI ( ILINK) HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of

50 +VRUN 0 0.U_V_Y_Y 00 0.U_V_Y_Y P_0V_K_ P_0V_K_ 00 0.U_V_Y_Y 00 F F F F J J L L P P P0 F F0 F H K K M N P P U V V V V V V V V V V0 V /MM/Memory tick/pro/mart Media/X N N N N N N N N N N0 N POWR UPPLY (.V) M_PWR_TRL_0 M_PWR_TRL_/M_R/# _# F M0 M0 M0 M_ M_PWR_TRL _PWR_TRL _# FIN _LK/M_R# R 00 _J _M _T0 _T _T _T M_IO_T0 M_T M_T M_T _WP M_# TP0 TP TP _LK FIN M_LK M_LK/_LK/M_L_WP# R _J 00 _M/M_L _T0/M T/M T/M T/M_ M_IO(T0)/_T0/M_0 M_T/_T/M_ M_T/_T/M_ M_T/_T/M WP/M_# M_# M_L X_#/M_PHY_WP# M_# M_/_M/M_W# RV0 RV RV RV RV RV RV RV RV F F F MIL MIL MIL V_TRL V_TRLM ONN. _WP _# _T _T0 0_J R 00 0_J R 00 _LK _M _T 0_J R _T 0_J R _J R 00 M T/UO ONN. M ONN. _R _R _R _R _R M_ M_R M_T 0_J R 00 M_R M_IO_T0 0_J R 00 M_R M_T 0_J R 00 M_R M_# 0_J R 00 M_T M_R M_LK 0_J R 00 N N N N NPTH N T_OUT N YN T_IN RT# NPTH 0 N WP OM 0 0 N V T T0 T IN T LK V V OM M NPTH NPTH ard etect ocket_p MOLX_-000 M M M M R O_0P YMIHI_J / hange Net name to H_M_* Pin efine for M T0M T T0 V LK V V M /T T N N R R +.V N N ITLK N0 0 T T0 V LK V V M /T T Write Protect TO PLU ONN_P FOX_QT0-0-F NPTH NPTH ase +VRUN R U_V_Y_Y 0 N J 00 N_P_0V_K_N 00 PIZHK +VRUN +VRUN 00 M_PWR_TRL 0U_0V_Y 0_YV R0 U N IN IN N OUT OUT OUT O# TP0 V_TRLM 0//0 PVT hange M Power switch to TP0 R 00K_J 00 0.U_V_Y_Y 00.U_0V_Y 00_YV +VRUN _PWR_TRL 0U_0V_Y 0_YV R0 U N IN IN N OUT OUT OUT O# TP0 V_TRL R00 00K_J 00 0.U_V_Y_Y 00.U_0V_Y 00_YV R.K_J 00 M_# 000P_0V_K_ 00 R.K_J 00 _# 000P_0V_K_ 00 K_J 00 K_J 00 FOXONN PI (M-UO/M) HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) U_V_Y_Y 00 0.U_V_Y_Y 00 0U_.V_M 00_XR H_M_TOUT H_M_YN H_M_TIN H_M_RT# H_M_ITLK 000P_0V_K_ 00 R.K_J 00 _WP ate: Friday, ugust, 00 heet 0 of

51 PMI ONN..V/V,000m.V/V,0m (M0--0 )Mainoard (MX-) PI ( PMI) Friday, ugust, 00 ize ocument Number Rev ate: heet of HON HI PRIION IN. O., LT. P - R& ivision FOXONN _R _R0 _R _R _R _R _R _R _R0 _R _R _R _R _R _R _R _R _R _R _R _R0 _R _R _R _R _R _T _T _T _T _T _T _T _T _T _T _T0 _T _T _T0 _T _T W# O# # IOR# # IOWR# R# WIT# RT V V INPK# # # IRQ# IOI# PKR# HT# TP_T TP_LOK TP_LTH V V WIT# PKR# W# IOI# _LK _R TP_T _T0 TP_LOK _T _T _T TP_LTH _T _T _T _T _T _T _T0 _T _T _T _T _T _R0 _R _R _R _R _R _R _R _R _R _R0 _R _R _R _R _R _R _R _R0 _R _R _R _R _R _R HT# # # # # INPK# IOR# IOWR# O# IRQ# R# RT NONTN +VRUN +VRUN +VRUN VPP V VPP V V 0U_V_Y 0_YV U TP0PWPR 0 0 V_ V_ T LOK LTH N_ V_ VPP V_ V_ N RT# N_ N_ N_ HN# N_0 N_ N_ N_ N_ O# N_.V THRML_P ard U / -it P ard ocket N PMI ONN_xP FOX_WZ--F / / FRM/ TRY/ VL/ TOP/0 LOK/ RV/ / LK/ IRY/ PRR/ PR/ // / /0 / // / 0/ / / / / / /0 / RV/ / / / /0 0/ / / / / / 0/ RV/ / /0 V V VPP VPP N N N N /IOR /IOWR /O NT/W 0/ /0/ //R RT/RT RR/WIT LKRUN/WP INT/RY UIO/V TH/V V/V V/V / / RQ/INPK H0 H H H H H H H H H H0 H H H H H NPTH NPTH 0.U_V_Y_Y 00 R _J 00 ard U / -it P ard ocket Housing N R U K_x FOX_-MM-F PTH PTH PTH PTH U_0V_Y 0_YV 0.U_V_Y_Y 00 N_U_0V_Y 0_YV.U_0V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 ard U / -it P ard Interface erial / Parallel P ard Power witch lamp Voltage For P R (IO V/.V) U PIZHK 0 0 F F H J J J L H F F H F M H H P N N M N M M L L L K K K N 0 J U V W /0 0/ / / /0 /0 / / / / / 0/ / / / / /IOWR# / /IOR# /0#/# PR/ FRM#/ TRY#/ IRY#/ TOP#/0 VL#/ LOK#/ PRR#/ LK/ RV/ RV/ /#/ /#/ /#/R# 0/ / / / / / / / / /0 0/# /O# / RR#/WIT# RQ#/INPK# NT#/W# TH/V(TH#/RI#) LKRUN#/WP(IOI#) INT#/RY(IRQ#) RT#/RT UIO/V(PKR#) #/# #/# V/V# V/V# RV/ V V T/V/VPP LTH/V/VPP0 LOK/V/V0# RV/V0/V# N N N N 0.U_V_Y_Y P_0V_M_ 00 0 U_0V_Y 0_YV 000P_0V_M_ 00 R K_J 00 0.U_V_Y_Y 00 PLT_RT#,,,,,,,,,

52 +VU T_V, T_ON U VIN VOUT N # P/F T_V LN_U_0V_Y_Y 00 LN_IT--T- LN_0.U_V_Y_Y LN_.U_0V_Y_Y / New lue tooth module luetooth connector T_V T_V R00 LN_0_J 00 T_ON Q R0 N_00K_J 00 N_TU T_HLK T_PR# +VU T_PIO R0 N_0_J 00 R0 LN_0K_J 00 R0 LN_0_J 00 FOX_QT00-H-F LN_ to _xp 0 T_V_R N T_PN_W_L T_PP_W_L 0/0/0 hange N from NI to FOXONN LN_0.U_V_Y_Y 00 T_T T_PIO# 00 LN_0_J R0 L 0 N_0R-00MHZ_0R 00 R0 LN_0_J T_PN_W T_PP_W 0/ Waiting conform /0 hange U0 nable from T_ON to T_V U LO Ton Max is 000us U0 U witch Ton Max is ns / hange luetooch circuit Value to LN_* for M0 VT L KU / hange R from K to.k, dd one K pull up resistance T_V R N_.K_J 00 T_ON R LN_0_J 00 U_PP U_T_N R N_K_J 00 U_PP T_PP_W U0 O V O N +VU T_ON T_PN_W U_PN LN_NQ0PW LN_0.U_V_Y_Y 00 U_PN To solve U0 enable pin (net name U_T_N)floating during U (T_V from LO )T_ON desable, dd Pull low K(R) at net U_T_N, hange R from 0K to K. FOXONN FN/luetooth HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of

53 MFIX MFIX MFIX MFIX +VU PTH MFIX PTH N MINI PI_P FOX_0_0K_F W F_W_M TP tpct_00 NPTH NPTH R 0K_J 00 Mini-PI ard connector N T_WLN_W# WIRL_HLK T_V WIRL_T R0 LN_0K_J 00 R LN_00K_J 00 R LN_0_J 00 /0 hange U Power from T_V to +VU +VU R N_0_J 00 T_V R LN_0_J 00 U LN_H0W T_HLK T_T 0,, PI_WK# MINI_RXN MINI_RXP MINI_TXN MINI_TXP MINI_R_T# LK_PI_MINI# LK_PI_MINI TP 0MIL TP 0MIL L_LK_KRON L_T_KRON L_RT_KRON R 0_J 00 WIRL_T WIRL_HLK 0 0 R 0_J 00 R 0_J 00 NPTH MFIX WK# +_V T_T N T_HLK +_V LKRQ# RRV N RRV 0 RFLK- RRV RFLK+ RRV N RRV RRV N RRV W_IL# 0 N PRT# PRn0 +_Vaux PRp0 N N +_V N RRV 0 PTn0 RRV PTp0 N N0 RRV0 RRVRRV RRV N 0 RRV N RRV L_WLN# RRV N RRV +_V RRV N 0 RRV +_V MFIX NPTH R 0_J 00 MINI_PI_+_V MINI_PI_+_V MINI_PI_+VUX MIL TP 0MIL TP 0 0MIL MINI_R L# 0MIL TP0 R N_0_J 00 R 00K_J 00 WLN_N / -N change N to mount (MOR side command) / hange WLN L control signal from WLN_N to WLN_L_N +VU MINI_PI_+VUX 0/ F suggest L_K/L_T/L_VRF can be left as N if unused imt. on't need to connect to WLN card. L_LK L_T R N_0_J 00 L_LK_KRON R N_0_J 00 L_T_KRON +VRUN MINI_PI_+_V LINKLRT# R N_0_J 00 L_RT_KRON 0MIL TP 0MIL TP R N_0_J 00 / hange luetooch circuit Value to LN_* for M0 VT L KU WLN_N PLT_RT#,,,,,,,,, Q N00PT 0.U_V_Y_Y 00 null MINI_R_L# MINI PI_P FOX_0_0N_F R0 0_J 00 U_0V_Y 0_YV.U_0V_Y_Y 00 0.U_V_Y_Y L_LK L_T R0 0_J 00 0 LINKLRT# N_U_0V_Y_Y 0 +_VRUN R 0_J 00 MINI_PI_+_V 0.U_V_Y_Y 00.U_0V_Y_Y 00 N_U_0V_Y_Y 0 FOXONN Mini-PI ard HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of

54 XPR ard +V_XPR_IN +_V_XPR_IN +VU PP# PU# +_V_PI_OUT +_V_PI_OUT +_VUX_PI_OUT PRT# PLT_RT#,,,,,,,,, R 0_J 00 U_PWR_0M,, R N_0_J 00 MOR not agree use N chip for second source hange xpress ard Power witch (U) from N PTF to TI TPPW +VU +VRUN R N_0_J 00 U _Vin Vin Vin Vin_ UXIN 0 R 0_J 00 PP# PU# N_ N TPPW _Vout Vout Vout Vout_ UXOUT TY# HN# O# 0 PRT# RLKN YRT# +V_XPR_IN 0.U_V_M_ 00 LKN XPR_TY# XPR_T# XPR_LKN# Q N00 +VU U XPR_TXP XPR_TXN R 0_J 00 0 R 0_J 00 R N_0R-00MHZ_0R 0_J 00 L0 0 LK_PI_XPR LK_PI_XPR# 0,, PI_WK#,,,0 M_T_U,,,0 M_LK_U U_PP U_PN R 0_J 00 L N_0R-00MHZ_0R XPR_TXP_R XPR_TXN_R R N_0_J 00 R N_0_J 00 R 0_J 0 00 XPR_RXP XPR_RXN LK_PI_XPR_R LK_PI_XPR#_R PP# XPR_LKN# +_V_PI_OUT PRT# +_VUX_PI_OUT U_PP_R U_PN_R L N_0R-00MHZ_0R R 0_J 00 +_V_PI_OUT XPR XPRLK PU# N 0 0 R ONNTOR_P FOX_H0-K 0 +_VU +_VRUN R N_0_J 00 R 0_J 00 +_V_XPR_IN 0 0.U_V_M_ 00,,, RUN_ON PP# N_MVHTF XPR_TY# +_VUX_PI_OUT XPR XPRLK N R0 0_J 00 PTH onstant-voltage +_VU +VU / Load current test fial,.v transfer.v drop Voltage too large./ hange Q0 from -N-N000 to --T00, hange Q0 Power from +_VU to +VU PTH XPR R HOUIN_P FOX_X0-T R.K_J 00 R.K_J 00 +_VU 0m 0 N_0U_0V_Y 0_YV R N_0_J 00 N_I-T- Q0 N_0U_0V_Y 0_YV R N_00K_J 00 R N_K_J 00 U0 _VU_OPOUT _VU_F OUT V _VU_VR IN- OUT IN+ IN- N IN+ N_LMR +VU +VU R N_K_F 00 _VU_VR R0 N_0K_F 00 +VU 0 0.U_V_Y_Y 00 upply Max m +_VUX_PI_OUT 0.U_V_Y_Y 00.U_.V_K 00_XR upply Max 00m +_V_PI_OUT 0.U_V_Y_Y 00.U_.V_K 00_XR 0U_0V_Y 0_YV upply Max 0m +_V_PI_OUT 0.U_V_Y_Y 00 0 N_.U_.V_K 00_XR 0U_0V_Y 0_YV +_VU TP0 tpct_00 FOXONN XPR R HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of

55 U connector * +VU U_V0 F0 V_._ minim0f-,, U_PWR_0M 00 U_V_Y 00_YV U_V_Y_Y U VIN VOUT N FL# RT0P U_V0 U_O#0 U_PN0 U_PP0 R0 N_0_J 00 L 0R-00MHZ_0R R0 0 N_0_J 00 N N N_RJ U_V L 0R-00MHZ_00 M00 P + U_.V_ TPM U_V0_F U_V0-_F U_V0+_F 0 0P_0V_K_ 00 V V- V+ N PTH PTH N U ONN_P FOX_U-0-FR L 0R-00MHZ_00 M00 U_V_Y 00_YV U_PWR_0M 00 0.U_V_Y_Y U VIN VOUT N FL# RT0P U_V U_O# U_PN U_PP R N_0_J 00 L 0R-00MHZ_0R R0 0 N_0_J 00 N N N_RJ P + U_.V_ TPM U_V_F U_V-_F U_V+_F 0P_0V_K_ 00 V V- V+ N PTH PTH N U ONN_P FOX_U-0-FR FOXONN U.0/OKIN ONN. HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of

56 IR Rreceiver connector U_PP U_PN LN_0_J R 00 L 0 N_0R-00MHZ_0R +VLW 0mils F LN_V-._0 0L0 00m 00_YV LN_.U_V_Z 00 LN_0.U_V_Y_Y R LN_0_J 00 +VU 0mils 00m +VU W_IR00 W_IR0 FTUR_RT# PWR_IR# F LN_V-._0 0L0 +VLW F R 00K_J 00 N_V-0._0 0L0 R N_00K_J 00 R N_00K_J 00 R N_00K_J 00 U_V_F U_PP_F U_PN_F 00_YV LN_.U_V_Z IR_LP_VPU IR_LP_PWR 00 LN_0.U_V_Y_Y 0 N IR_LP_P R N_0_J 00 MFIX MFIX LN_HR_P FOX_H RT_IR# RT_IR_ TP tpct_00 Q LN_N00 olve W of instant on latter issue for V->V level shift / FOR NW MK IR module compatily.hange stuff to N:F,R,R,R,. Page PIO0(0),PI() pin swape / hange IR circuit Value to LN_* for M0 VT L KU U_V_F U_PP_F U_PN_F IR_LP_VPU W_IR00 W_IR0 FTUR_RT# PWR_IR# IR_LP_PWR TP tpct_00 TP tpct_00 TP tpct_00 TP0 tpct_00 TP tpct_00 TP tpct_00 TP tpct_00 TP tpct_00 TP tpct_00 TP tpct_00 t Only U Internal IR, it's U Power FOXONN L/LI W#/Touch P HON HI PRIION IN. O., LT. P - R& ivision ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Friday, ugust, 00 heet of