THERMAL EMC2102 CRT 17 LCD HDMI MXM CONN. CardReader JMicro JMB385 LAN. MS/MS Pro/xD /MMC/SD. Giga LAN 88E PWR SW. New card. Mini Card.

Transcription

1 iger lock iagram LK N. I LPRKLFT R IMM /00 MHz INT.MI Line In MI In INT.PKR Line Out (PIF) RJ R IMM /00 MHz odec L V OP MP Q OP MP MOM M ard IO/H Mb /00MHz /00MHz ZLI PI H T O T T Mobile PU HOT U /00/0MHz@.0V X MI 00MHz Penryn antiga TL+ PU I/F R Memory I/F INTRT RHPI LV, RT I/F IHM PIe ports PI/PI RI T PI.0 T U.0/. ports THRNT (0/00/000Mb) High efinition udio LP I/F erial Peripheral I/F Matrix torage Technology(O) lue Tooth (U) -Link0 ctive Managemnet Technology(O) et,,,,,0,,0,, U PIex PIex PIex PIex PIex PIex LP U amera (U) U Port THRML M0 ardreader JMicro JM LN iga LN 0 New card K N0 Touch INT. Pad K Finger Printer RT L HMI MXM ONN M/M Pro/x /MM/ in TXFM Mini ard Kedron IO Winbond WX0 M its Launch uttom 0 a/b/g/n RJ PWR W RU Mini ard Kedron a/b/g/n IR LP U ONN Port Replicator Project code:.z0.00 P P/N :.Z0.00 RVIION : 0- - TOP N OTTOM P TKUP YTM / TP INPUT TOUT YTM / TP INPUT TOUT RT0 V_ RT0 V_ V_ Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. OUTPUT V_ 0V_0 V_ OUTPUT R_VRF_0 R_VRF_ V_0 V_0 FXOR / IL INPUT TOUT OUTPUT VFXOR 0.~.V PU / IL INPUT TOUT HRR Q INPUT TOUT V_0 OUTPUT _OR_0 0.~.V OUTPUT T+ TOUT LOK IRM ize ocument Number Rev ustom iger - Tuesday, pril 0, 00 ate: heet of 0

2 IHM Functional trap efinitions ignal H_OUT antiga chipset and IHM I/O controller Hub strapping configuration Montevina Platform esign guide 0. page H_YN PI config bit0, This signal has a weak internal pull-down. L_RT0# PULL-UP 0K NT#/ PIO PIO0 NT#/ PIO NT#/ PIO NT0#: PI_#/ PIO PI_MOI Reserved This signal has a weak internal pull-up. ets bit of RP.P(onfig Registers:Offset 0h) This signal should not be pulled high. Intel Management engine rypto strap F F ynamic OT 0 = ynamic OT isabled PIO TL# PKR TP PIO/ H_OK _N# Usage/When ampled XOR hain ntrance/ PI Port onfig bit, Rising dge of PWROK Rising dge of PWROK. PI config bit, Rising dge of PWROK. I trap (erver Only) Rising dge of PWROK Top-lock wap Override. Rising dge of PWROK. oot IO estination election 0:. Rising dge of PWROK. Integrated TPM nable, Rising dge of LPWROK omment llows entrance to XOR hain testing when TP pulled low.when TP not pulled low at rising edge of PWROK,sets bit of RP.P(onfig Registers: offset h). This signal has weak internal pull-down ets bit0 of RP.P(onfig Registers:Offset h) I compatible mode is for server platforms only. This signal should not be pulled low for desttop and mobile. ampled low:top-lock wap mode(inverts for all cycles targeting FWH IO space). Note: oftware will not be able to clear the Top-wap bit until the system is rebooted without NT# being pulled down. MI Termination Voltage, The signal is required to be low for desktop Rising dge of PWROK. applications and required to be high for mobile applications. PI xpress Lane Reversal. Rising dge of PWROK. No Reboot. Rising dge of PWROK. XOR hain ntrance. Rising dge of PWROK. Flash escriptor ecurity Override trap Rising dge of PWROK ignal has weak internal pull-up. ets bit of MP.LR(evice :Function 0:Offset ) Flash-decriptor section of the Firmware. This 'oft-trap' is PI Routing LN LN LN LN LN LN N LN MRVLL 0 Miniard WLN Miniard WWN/TV JM ard Reader Neward ontrollable via oot IO estination bit (onfig Registers:Offset 0h:bit :0). NT0# is M, 0-PI, 0-PI, -LP. page ample low: the Integrated TPM will be disabled. ample high: the MH TPM enable strap is sampled low and the TPM isable bit is clear, the Integrated TPM will be enable. If sampled high, the system is strapped to the "No Reboot" mode(ih will disable the TO Timer system reboot feature). The status is readable via the NO ROOT bit. This signal should not be pull low unless using XOR hain testing. ampled low:the Flash escriptor ecurity will be overridden. If high,the security measures will be in effect.this should only be enabled in manufacturing environments using an external pull-up resister. U Table Pair 0 0 IH Rev.. U U U U U(OK) U MINI NW N evice luetooth FP WM MINI Mus K IHM IHM Integrated Pull-up and Pull-down Resistors M_Therm M_Therm T_L T_ INL L_LK[:0] L_T[:0] PRLPVR/PIO NRY_TT H_IT_LK H_OK_N#/PIO H_RT# H_IN[:0] H_OUT H_YN Thermal MXM TTRY M_IH LPRKLFT R IH Rev.. Resistor Type/Value LN_OK# The pull-up or pull-down active when configured for native LN_OK# functionality and determined by LN controller NT[:0]#/PIO[,,] PULL-UP 0K PIO[0] PIO[] L[:0]#/FHW[:0]# LN_RX[:0] LRQ[0] LRQ[]/PIO PM# PWRTN# TL# PI_#/PIO/LPIO PI_MOI PI_MIO PKR TH_[:0] TP[] U[:0][P,N] Media oard HRR O-IMM PULL-UP 0K PULL-UP 0K PULL-OWN 0K PULL-UP 0K PULL-OWN 0K PULL-UP 0K PULL-OWN 0K PULL-OWN 0K PULL-OWN 0K PULL-OWN 0K PULL-OWN 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP K PULL-UP 0K PULL-OWN 0K PULL-UP 0K PULL-OWN 0K PULL-UP 0K PULL-UP 0K PULL-OWN K Pin Name F[:0] F[:] F F[:] F[:] F F F F F0 F[:] F F0 VO_TRLT L T trap escription F Frequency elect Reserved MI x elect itpm Host Interface PI raphics Lane PI Loopback enable XOR/LL MI Lane Reversal igital isplay Port (VO/P/iHMI) oncurrent with PIe VO Present Local Flat Panel (LFP) Present onfiguration 000 = F0 0 = F 00 = F00 others = Reserved 0 = MI x = MI x (efault) 0= The itpm Host Interface is enabled(note) =The itpm Host Interface is disalbed(default) 0 = Transport Layer ecurity (TL) cipher suite with no confidentiality = TL cipher suite with confidentiality (default) 0 = Reverse Lanes,->0,-> ect.. = Normal operation(efault):lane Numbered in order 0 = nable (Note ) = isabled (default) 00 = Reserve 0 = XOR mode nabled 0 = LLZ mode nabled (Note ) = isabled (default) = ynamic OT nabled 0 = Normal operation(efault): Lane Numbered in Order 0 = LFP isabled (efault) Reference (efault) = Reverse Lanes MI x mode[mh -> IH]:(->0,->,->and0->) MI x mode[mh -> IH]:(->0,->) 0 = Only igital isplay Port or PI is operational (efault) =igital display Port and PIe are operting simulataneously via the P port 0 =No VO ard Present (efault) = VO ard Present = LFP ard Present; PI disabled NOT:. ll strap signals are sampled with respect to the leading edge of the ()MH Power OK (PWROK) signal.. itpm can be disabled by a 'oft-trap' option in the activated only after enabling itpm via F. Only one of the F0/F//F straps can be enabled at any time. Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev iger - ate: Tuesday, pril 0, 00 heet of 0

3 V_0 R0 V_MPWR_0 MI PLK_IH R N_XTL_OUT LK_MH_LK X PUT_F.000. LK_MH_LK# N X X PU_F.000. X-M-P PUT_ITP/RT LK_PI_LN LK_PI_LN# LN N_XTL_OUT_R 0 LK_IH R RJ--P LK PU_ITP/R, PU_L0 R KRJ--P U_MHZ/FL P0VJN--P RT/R#_F LK_PI_NW R/R#_ 0 LK_PI_NW# New ard V_0 0 PM_TPPI# PI_TOP# V_ 0 PM_TPPU# PU_TOP# RT LK_PI_IH 0 MI R LK_PI_IH# 0 MI RN LK_PI_P_ RN LK_PI_P 0 PLKLK RT0 near X LK_PI_P_#,, M_IH LK_PI_P# 0 MXM PLKLK0 LK R0,, M_IH I T RT/R#_H LK_PI_RRR 0 0 LK_PWR K_PWR/P# R/R#_ LK_PI_RRR# JM R RT LK_PI_MINI LK_PI_MINI# MINI PLKLK0 R V_0 0 TLKRQ# R LK_MH_O# R PLKLK PI0/R#_ RN 0 LK_MH_PLL PLKLK PI/R#_ RT LK_MH_PLL# N LK PLKLK PLK_FWH R RJ--P PLKLK PI/TM R PLK_K PLKLK PI LK_PI_MINI PLKLK 0 PLK_IH PLKLK PI/_LT RT/R#_ LK_PI_MINI# MINI PLKLK PI_F/ITP_N R/R#_ RN RNJ--P-U RN0KJ--P RT/TT LK_PI_T R/T LK_PI_T# T, PU_L PLK_K, PU_L R 0KRJ--P PU_L_R FL/TT_MO RF0/FL/TT_L RFLK_ RN RFLK MI 0 LK_IH R RJ--P MHZ_NON/RT/ RFLK#_ RN0J--P RFLK# 0 N# MHZ_/R/ N LK near R RFLK_ RN RT0/OTT_ 0 RFLK RFLK#_ RN0J--P R0/OT_ RFLK# L=0pF±0.pF P0VJN--P N_XTL_IN ILPRKLFT setting table PIN NM RIPTION PI0/R#_ PI/R#_ PI/TM PI near R V_LKPLL_0 LK_IH yte, bit 0 = PI0 enabled (default) = R#_ enabled. yte, bit controls whether R#_ controls R0 or R pair yte, bit 0 = R#_ controls R0 pair (default), = R#_ controls R pair yte, bit 0 = PI enabled (default) = R#_ enabled. yte, bit controls whether R#_ controls R or R pair yte, bit 0 = R#_ controls R pair (default) = R#_ controls R pair 0 = Overclocking of PU and R llowed = Overclocking of PU and R NOT allowed V_0 V_MPWR_0 PIN NM R/R#_ R/R#_ RT/R#_H V_LKN_0 RIPTION V_LKPLL_0 LK_IH yte, bit 0 = R enabled (default) = R#_ enabled. yte, bit 0 controls whether R#_ controls R or R pair yte, bit 0 0 = R#_ controls R pair (default) = R#_ controls R pair V_LKN_0 LK_PU_LK LK_PU_LK#.V PI clock output yte, bit 0 = R# enabled (default) R/R#_ = R#_F controls R 0 = Pin as R-, Pin as R-#, Pin0 as OT, Pin as OT# = Pin as MHz, Pin as MHz_, Pin0 as R-0, Pin as R-0# PI/M_L PI_F/ITP_N RT/R#_ UVZY-P 0 =R/R# = ITP/ITP# MI R near R 0 0 yte, bit 0 = R enabled (default) = R#_ enabled. yte, bit controls whether R#_ controls R0 or R pair yte, bit 0 = R#_ controls R0 pair (default), = R#_ controls R pair UVZY-P U0VZY-P 0UVZY-P UVZY-P 0 UVZY-P P0VN-P UVZY-P R U 0 RTMN-0-V-RT-P ILPRKLFT-P RT/R#_F VRF V VPI VR VPU VPLL N NPI NRF N NR NR NR NPU N 0 V_IO VPLL_IO VR_IO VR_IO VR_IO VPU_IO yte, bit 0 = R enabled (default) = R#_F controls R yte, bit 0 = R# enabled (default) = R#_ controls R yte, bit 0 = R enabled (default) = R#_H controls R0 N U0VZY-P PUT0 PU0 0 MI near R UVZY-P UVZY-P L F UVZY-P L F L0 F R 0 lock enerator PU V_0 PU N LK ( MHz) F 0 00M X 0 0 M M 0 M M M 00M M 0M Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev iger - ate: Tuesday, pril 0, 00 heet of 0 UVZY-P

4 H_#[..] H_#[..] H_TN#[..0] U OF TP H_TN#[..0] H_TP#[..0] H_TP#[..0] H_# J 0V_0 H_# # # H H_# L H_#[..0] H_# # NR# H_NR# H_#[..0] L H_# # PRI# H_PRI# K H_# # M H_# # FR# H H_FR# N Place testpoint on H_# # R# F H_R# R00 J H_IRR# with a N H_#0 # Y# RJ--P H_Y# N 0." away H_# 0# P H_# # R0# F H_RQ#0 P H_# # L H_IRR# H_# # IRR# 0 TP P H_# # INIT# H_INIT# P H_# # R # LOK# H H_LOK# H_T#0 M H_PURT#, U OF T0# H_RQ#[..0] H_RQ#0 RT# H_R#[..0] K H_R#0 H_#0 H_# H_RQ# RQ0# R0# F H_R# H_# 0# # Y H H_# H_RQ# RQ# R# F F H_R# H_# # # K H_# H_RQ# RQ# R# H_# # # V J H_# H_RQ# RQ# TR# H_TR# H_# # # V L H_# RQ# F H_HIT# H_THRM H_# # # V H_# H_# HIT# H_HITM# H_# # # T Y H_# H_# # HITM# H_# # # U U H_# H_# # XP_PM#0 H_# # # U R H_#0 H_#0 # PM0# TP K XP_PM# H_# # 0# Y W H_# H_# 0# PM# TP XP_PM# H_THRM H_#0 # # W U H_# H_# # PM# TP J XP_PM# H_# 0# # Y Y TP H_# H_# # PM# J XP_PM# H_# # # W U H_# H_# PR# TP # H XP_PM# H_# # # W R H_# H_# # PRQ# TP0 F XP_TK TP H_# # # T H_# H_# # TK K XP_TI 0V_0 H_# # # T TP H_# H_# # TI H XP_TO # # W H_TN#0 J H_TN# H_# # TO TP XP_TM TP TN0# TN# Y W H_TP#0 H H_TP# H_# # TM XP_TRT# TP TP0# TP# Y H_INV#0 H H_INV# H_#0 # TRT# XP_RT# INV0# INV# U ide and U H_# 0# R# 0 TP R V R-P Non TL H_# # W H_# N H_# H_# # H_# # # K H_# H_# # THRML H_# # # P H_#0 H_# # PU_PROHOT# PU_PROHOT#_R H_# # 0# R H_# # PROHOT# H_#0 # # H_# H_T# V THRM H_THRM R T# L H_THRM H_# 0# # M H_# THRM H_0M# H_# # # L H_# 0M# H_FRR# PM_THRMTRIP-#,,,0 H_# # # 0 M H_# FRR# THRMTRIP# H_INN# H_# # # P H_# INN# H_# # # F P H_# H_TPLK# H_# # # P H_# TPLK# H_INTR LK_PU_LK H_# # # HLK T H_# LINT0 LK0 0V_0 H_NMI LK_PU_LK# H_# # # R H_#0 LINT LK H_MI# H_# # 0# L H_# MI# PM_THRMTRIP# H_#0 # # T H_# RV_PU_ should connect to H_# 0# # F TP M N H_# RV_PU_ IH and MH # # TP RV#M N H_TN# L H_TN# RV_PU_ without T-ing TN# TN# TP RV#N T R H_TP# M H_TP# RV_PU_ ( No stub) TP# TP# F TP RV#T V KRF--P H_INV# N H_INV# RV_PU_ RV#V Layout Note: INV# INV# 0 TP TP RV_PU_ RV# "PU_TLRF0" PU_TLRF0 OMP0 RV_PU_ 0." max length. TT TLRF OMP0 R R RF-L-P TP RV# MI OMP RV_PU_ TT TT OMP U R RF-L-P TP RV# OMP TP RV_PU_ RV# RV_PU_ TT OMP R RF-L-P R0 TP OMP RV_PU_0 RV# 0 TT TT OMP Y R RF-L-P TP F KRF--P RV#F F TP RV_PU_ TT F H_PRTP#,, TP RV_PU_ RV_PU_ TT PRTP# TP KY_N TT PLP# H_PLP# PWR# H_PWR# -KT--P-U, PU_L0 L0 PWROO H_PWR,0,.00.0, PU_L L LP# H_PULP#.00.00, PU_L L PI# PI# XP_TM XP_TI XP_PM# H_PURT# R0 RRV 0V_0 R RF-L-P R0 RF-L-P R RF-L-P R ROUP 0 R ROUP IH XP/ITP INL ONTROL Follow emo ircuit TT R TT R TT XP_TK R RF-L-P 0 XP_TRT# R RF-L-P V_0 ll place within " to PU XP_RT# R0 0V_0 H_INV#[..0] H_INV#[..0] T RP0 T RP Net "TT" as short as possible, make sure "TT" routing is reference to N and away other noisy signals T RP T RP -KT--P-U Layout Note: omp0, connect with Zo=. ohm, make trace length shorter than 0.". omp, connect with Zo= ohm, make trace length shorter than 0.". Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. XP_TO R PU ( of ) ize ocument Number Rev iger - ate: Tuesday, pril 0, 00 heet of 0

5 _OR U OF _OR _OR _OR _OR P U OF P T P T00UVM--P 0 R.0.0 R R TP R F N T P P P P T T T 0 U U _OR U 0 0 U V V 0 V V W 0 W 0 W 0 W Y P P P P P P P P P P P P P P Y Y Y 0 F 0 0V_0 F0 F F F 0 F 0 00 F 0V_0 F0 0 P_0 P P V P J P K P M P J F 0 P K F F P M F F P N F F0 P N layout note: "V 0" F F P R as short as possible F F P R F F P T F F P T F F V_0 P V F0 V 0 P W L 0 H H_VI[..0] 0 H0KFT0-P H H_VI0 VI H H_VI _OR VI F H H_VI VI J H_VI VI F J 0 H_VI VI J H_VI VI F R J 0 H_VI VI 00RF-L-P-U TP K 0 K 0 K _N_PU N F _N K L 0 L _N_PU N _N L L TP M -KT--P-U R M TP RF-L-P-U F M F M F N Layout Note: F N F N N and N lines F N should be of equal length. F P TP F TP0 Layout Note: Provide a test point (with -KT--P-U no stub) to connect a.00.0 differential probe between N and N at the location where the two.ohm resistors terminate the ohm transmission line. U0VKX-P U0VKX-P Not tuff o 0UVKX-P Not tuff o 0UVMX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P UVKX-P UVKX-P Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PU ( of ) ize ocument Number Rev iger - ate: Tuesday, pril 0, 00 heet of 0

6 H_WIN routing Trace width and pacing use 0 / 0 mil H_WIN Resistors and apacitors close MH 00 mil ( MX ) H_WIN 0 U0VKX-P H_ROMP routing Trace width and pacing use 0 / 0 mil R RF-L-P Place them near to the chip ( < 0.") 0V_0 H_ROMP R RF--P R 00RF-L-P-U H_#[..0] 0V_0 R KRF--P H_#[..0], H_PURT# H_PULP# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_WIN H_ROMP H_VRF U F H_#_0 H_#_ F H_#_ H_#_ H_#_ H H_#_ H H_#_ F H_#_ H_#_ H H_#_ M H_#_0 M H_#_ J H_#_ J H_#_ N H_#_ J H_#_ P H_#_ L H_#_ R H_#_ N H_#_ L H_#_0 M H_#_ J H_#_ N H_#_ R H_#_ N H_#_ N H_#_ P H_#_ N H_#_ L H_#_ N0 H_#_0 M H_#_ Y H_#_ H_#_ Y H_#_ Y0 H_#_ Y H_#_ Y H_#_ Y H_#_ W H_#_ H_#_0 Y H_#_ H_#_ H_#_ H_#_ H_#_ 0 H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ F H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_WIN H_ROMP H_PURT# H_PULP# H_VRF H_VRF HOT OF 0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_# H_T#_0 H_T#_ H_NR# H_PRI# H_RQ# H_FR# H_Y# HPLL_LK HPLL_LK# H_PWR# H_R# H_HIT# H_HITM# H_LOK# H_TR# H_INV#_0 H_INV#_ H_INV#_ H_INV#_ H_TN#_0 H_TN#_ H_TN#_ H_TN#_ H_TP#_0 H_TP#_ H_TP#_ H_TP#_ H_RQ#_0 H_RQ#_ H_RQ#_ H_RQ#_ H_RQ#_ H_R#_0 H_R#_ H_R#_ F H M J P R N M P F 0 J 0 H J0 L L J H0 K 0 F K L0 H F 0 H H J F H H J L Y Y L0 M L M K F F H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_INV#0 H_INV# H_INV# H_INV# H_TN#0 H_TN# H_TN# H_TN# H_TP#0 H_TP# H_TP# H_TP# H_RQ#0 H_RQ# H_RQ# H_RQ# H_RQ# H_R#0 H_R# H_R# H_#[..] H_# H_T#0 H_T# H_NR# H_PRI# H_RQ#0 H_FR# H_Y# LK_MH_LK LK_MH_LK# H_PWR# H_R# H_HIT# H_HITM# H_LOK# H_TR# H_INV#[..0] H_TN#[..0] H_TP#[..0] H_#[..] H_INV#[..0] H_TN#[..0] H_TP#[..0] H_RQ#[..0] H_R#[..0] R KRF--P UVZY-P NTI-M-P-U-NF.NTI.00U.NTI.U Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. antiga ( of ) ize ocument Number Rev iger - ate: Tuesday, pril 0, 00 heet of 0

7 V_0 R V_ R KRF--P R0 K0RF--P R KRF--P F0 V_ 0,, 0, M_ROMPP M_ROMPN R0 0RF-L-P VT_PWR PWROK 0,,,0,,,, 0 PM_YN#,, H_PRTP# M_ROMP_VOH M_ROMP_VOL layout take note R PLT_RT# R,,,0 PM_THRMTRIP-# 0, PM_PRLPVR Pin Name trap escription onfiguration F0 igital isplayport (VO/P/HMI) oncurrent with PI 0UVKX-P 0UVKX-P R 0RF-L-P UVMX--P 0 UVMX--P R R,,, F F PU_L0 PU_L PU_L R 00RJ--P 00P0VJN-P F0 PM_YN# H_PRTP# PM_XTT#0 PM_XTT# PWROK_ RTIN# PM_THRMTRIP-# PM_PRLPVR Low = Only digital isplayport (VO/P/HMI) or PI is operational (default) RV F PM N R LK/ ONTROL/OMPNTION LK MI RPHI VI M MI H R 0KRJ--P V_0 High = igital isplayport (VO/P/HMI) and PI are operating simultaneously via the P port M N R T H H0 H H K L K N M T M Y F H F T R P P0 P N M N P T R0 M0 L H P R T R N P T0 T T0 R F H H F H H H H H F H F F U RRV#M RRV#N RRV#R RRV#T RRV#H RRV#H0 RRV#H RRV#H RRV#K RRV#L RRV#K RRV#N RRV#M RRV#T RRV# RRV# RRV#M RRV#Y RRV# RRV#F RRV#H RRV#F F_0 F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 PM_YN# PM_PRTP# PM_XT_T#_0 PM_XT_T#_ PWROK RTIN# THRMTRIP# PRLPVR N# N#F N# N# N#H N# N# N#H N#F N# N#H N#H N#H N#H N# N#H N#F N#H N# N# N# N#F N# N# N#F N# NTI-M-P-U-NF.NTI.00U OF 0 _K_0 _K K_0 _K K#_0 _K# K#_0 _K# K_0 _K K_0 _K #_0 _# #_0 _# OT_0 _OT OT_0 _OT_ M_ROMP M_ROMP# M_ROMP_VOH M_ROMP_VOL M_VRF M_PWROK M_RXT M_RMRT# PLL_RF_LK PLL_RF_LK# PLL_RF_LK PLL_RF_LK# P_LK P_LK# MI_RXN_0 MI_RXN_ MI_RXN_ MI_RXN_ MI_RXP_0 MI_RXP_ MI_RXP_ MI_RXP_ MI_TXN_0 MI_TXN_ MI_TXN_ MI_TXN_ MI_TXP_0 MI_TXP_ MI_TXP_ MI_TXP_ FX_VI_0 FX_VI_ FX_VI_ FX_VI_ FX_VI_ FX_VR_N L_LK L_T L_PWROK L_RT# L_VRF P_TRLLK P_TRLT VO_TRLLK VO_TRLT LKRQ# IH_YN# TTN# H_LK H_RT# H_I H_O H_YN LK_MH_O# P T V U0 R R U V0 Y Y Y V R Y F Y H F H M_ROMPP M_ROMPN M_ROMP_VOH M_ROMP_VOL V R : connect to N R F M_RXT R RF--P TP_M_RMRT# R : Leave as N TP RFLK RFLK# RFLK RFLK RFLK# RFLK# RFLK F RFLK# F H 0 H0 H F H F H H N J H N M K H 0 MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP FXVR_N LPWROK_MH MH_LVRF MH_TTN# H_LK H_RT# H_I H_O H_YN MH_TTN# FXVR_N M_LK_R0 M_LK_R M_LK_R M_LK_R M_LK_R#0 M_LK_R# M_LK_R# M_LK_R# M_K0 M_K M_K M_K M_0# M_# M_# M_# M_OT0 M_OT M_OT M_OT FX_VI0 FX_VI FX_VI FX_VI FX_VI 0V_0 LK_MH_PLL LK_MH_PLL# MI_TXN0 0 MI_TXN 0 MI_TXN 0 MI_TXN 0 MI_TXP0 0 MI_TXP 0 MI_TXP 0 MI_TXP 0 MI_RXN0 0 MI_RXN 0 MI_RXN 0 MI_RXN 0 MI_RXP0 0 MI_RXP 0 MI_RXP 0 MI_RXP 0 For HMI port R0 R R FXVR_N V_0 R_VRF_ L_LK0 0 L_T0 0 PWROK 0, L_RT#0 0 MH_HMI_LK MH_HMI_T LK_MH_O# MH_IH_YN# 0 TP RN0 RNJ--P-U 0RJ--P RN RNJ--P-U R RJ--P R 00KRJ--P FX_VI[..0] U0VKX-P U0VKX-P MH_HYN MH_VYN 0V_0 R KRF--P R RF--P Z_IT_LK_R Z_RT#_R Z_IN Z_TOUT_R Z_YN_R L_KLTTL MH_L_ON MH_LK MH_T LK I T I MH_H MH_V L_KLTTL MH_L_ON LTL_LK LTL_T LK I T I MH_LU MH_RN MH_R RN RNJ--P-U TP TP FOR antiga:00 ohm Teenah: ohm MH_TXOUT0+ MH_TXOUT+ MH_TXOUT+ MH_TXOUT0- MH_TXOUT- MH_TXOUT- MH_LV_ON MH_LV_ON LI TP L_LV R MH_LV_VRF 0RJ--P MH_TXLK- MH_TXLK+ MH_TXLK- MH_TXLK+ MH_TXOUT0- MH_TXOUT- MH_TXOUT- MH_TXOUT0+ MH_TXOUT+ MH_TXOUT+ TV_ TV_ TV_ MH_LU MH_RN MH_R MH_LK MH_T RT_IRF R K0RF--P FOR antiga:.0k_% ohm Teenah:.k ohm RT_IRF routing Trace width use 0 mil RFLK RFLK# RFLK RFLK# L M M K J M 0 H 0 0 H F0 0 H J F K F H K H J H J J L U NTI-M-P-U-NF.NTI.00U RN I L_KLT_TRL L_KLT_N L_TRL_LK L_TRL_T L LK L T L_V_N LV_I LV_V LV_VRFH LV_VRFL LV_LK# LV_LK LV_LK# LV_LK LV_T#_0 LV_T#_ LV_T#_ LV_T#_ LV_T_0 LV_T_ LV_T_ LV_T_ LV_T#_0 LV_T#_ LV_T#_ LV_T#_ LV_T_0 LV_T_ LV_T_ LV_T_ TV_ TV_ TV_ TV_RTN TV_ONL_0 TV_ONL_ RT_LU RT_RN RT_R RT_IRTN RT LK RT T RT_HYN RT_TVO_IRF RT_VYN LV PI-XPR RPHI TV V MH_LU MH_RN MH_R TV_ TV_ TV_ OF 0 P_OMPI P_OMPO P_RX#_0 P_RX#_ P_RX#_ P_RX#_ P_RX#_ P_RX#_ P_RX#_ P_RX#_ P_RX#_ P_RX#_ P_RX#_0 P_RX#_ P_RX#_ P_RX#_ P_RX#_ P_RX#_ P_RX_0 P_RX_ P_RX_ P_RX_ P_RX_ P_RX_ P_RX_ P_RX_ P_RX_ P_RX_ P_RX_0 P_RX_ P_RX_ P_RX_ P_RX_ P_RX_ P_TX#_0 P_TX#_ P_TX#_ P_TX#_ P_TX#_ P_TX#_ P_TX#_ P_TX#_ P_TX#_ P_TX#_ P_TX#_0 P_TX#_ P_TX#_ P_TX#_ P_TX#_ P_TX#_ P_TX_0 P_TX_ P_TX_ P_TX_ P_TX_ P_TX_ P_TX_ P_TX_ P_TX_ P_TX_ P_TX_0 P_TX_ P_TX_ P_TX_ P_TX_ P_TX_ P_MP R TXN0 TXN TXN TXN TXN TXN TXN TXN TXN TXN TXN0 TXN TXN TXN TXN TXN TXP0 TXP TXP TXP TXP TXP TXP TXP TXP TXP TXP0 TXP TXP TXP TXP TXP P_RXN0 P_RXN P_RXN P_RXN P_RXN P_RXN P_RXN P_RXN P_RXN P_RXN P_RXN0 P_RXN P_RXN P_RXN P_RXN P_RXN P_RXP0 P_RXP P_RXP P_RXP P_RXP P_RXP P_RXP P_RXP P_RXP P_RXP P_RXP0 P_RXP P_RXP P_RXP P_RXP P_RXP TO level shifter RN FOR iscrete,change to 0 ohm.r00.l R T T H J L L0 N P N T U Y Y Y H J L L N0 P N T U Y W Y 0 J M M M0 M R N T0 U U0 Y0 0 J L M M M R N T U U Y Y RN0J--P _.R00.L:I FOR iscrete,change to 0 ohm.r00.l TXN0 TXN TXN TXN TXP0 TXP TXP TXP 0V_0 I I I I I I I I I I 0 I I I I I I I I I I I 0 I I I I I I I I I I I 0 _.R00.L:I RJ--P R _.R00.L:I RJ--P R0 _.R00.L:I RJ--P RF-P lose to MH as 00 mils. P_RXN[..0] 0 P_RXP[..0] 0 P_RXP R 0RJ--P LI RT_IRF LTL_LK LTL_T PM_XTT#0 PM_XTT# P_TXN0 P_TXN P_TXN P_TXN P_TXN P_TXN P_TXN P_TXN P_TXN P_TXN P_TXN0 P_TXN P_TXN P_TXN P_TXN P_TXN P_TXP0 P_TXP P_TXP P_TXP P_TXP P_TXP P_TXP P_TXP P_TXP P_TXP P_TXP0 P_TXP P_TXP P_TXP P_TXP P_TXP U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P 0 U0VKX-P U0VKX-P MH_L_ON MH_LV_ON R MH_H MH_V R R 00KRJ--P 00KRJ--P KRF-P RN RN RN0KJ--P RN I RN0KJ--P P_TXN[..0] 0 P_TXP[..0] 0 HMI_T- HMI_T- HMI_T0- HMI_LK- HMI_T+ HMI_T+ HMI_T0+ HMI_LK+ HMI_TT# V_0 Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. antiga ( of ) ize ocument Number Rev iger - Tuesday, pril 0, 00 ate: heet of 0

8 M Q[..0] M Q[..0] M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q U J _Q_0 J _Q_ N _Q_ M _Q_ J _Q_ J0 _Q_ M _Q_ M _Q_ N _Q_ N _Q_ U0 _Q_0 T _Q_ N _Q_ N _Q_ U _Q_ U _Q_ V _Q_ Y _Q_ 0 _Q Q_ V _Q_0 Y _Q Q_ 0 _Q_ Y _Q Q_ V _Q_ T _Q_ Y _Q Q_ V _Q_0 W _Q Q_ U _Q Q Q_ U _Q_ V _Q Q Q Q_0 _Q_ U0 _Q_ V _Q Q Q_ Y _Q Q_ V _Q_ V _Q_ T _Q_0 N _Q_ U _Q_ U _Q_ T _Q_ N0 _Q_ M _Q_ M _Q_ J _Q_ J _Q_ N _Q_0 M _Q_ J _Q_ J _Q_ R YTM MMORY OF 0 0 T _R# 0 _# 0 _W# Y0 _M_0 M _M_ T _M_ Y _M_ U _M M_ Y _M_ T _M_ J _Q_0 J _Q_ T _Q Q Q_ W _Q Q_ U _Q_ M _Q#_0 J _Q#_ T _Q# Q# Q#_ Y _Q# Q#_ U _Q#_ M _M_0 _M M M_ H _M M M M M_ F _M_ W _M_0 _M M_ H _M_ H _M_ Y M M0 M M M M M M M M M M M M M M M Q0 M Q M Q M Q M Q M Q M Q M Q M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M 0 M M M M M M M M M M 0 M M M M M M[..0] M Q[..0] M Q#[..0] M [..0] M #0 M # M # M R# M # M W# M M[..0] M Q[..0] M Q#[..0] M [..0] M Q[..0] M Q[..0] M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q U K _Q_0 H _Q_ P _Q_ P _Q_ J _Q_ J _Q_ M _Q_ P _Q_ U _Q_ U _Q Q_0 Y _Q_ T _Q_ R _Q Q Q Q Q Q_ F _Q Q_0 _Q_ F0 _Q_ F _Q Q_ F _Q_ H _Q Q_ H0 _Q Q Q_0 H _Q_ H _Q Q_ H _Q Q_ H _Q_ F _Q_ F _Q Q Q_0 _Q_ Y _Q_ Y _Q_ F _Q_ F _Q Q Q_ V _Q_ U _Q_ R _Q_0 N _Q_ Y _Q_ V _Q_ P _Q_ R _Q_ L _Q_ L _Q_ J _Q_ H _Q_ M _Q_0 M _Q_ H _Q_ J _Q_ R YTM MMORY OF 0 0 _R# _# _W# _M_0 _M M M M M M M Q_0 _Q Q Q Q Q Q Q Q#_0 _Q# Q# Q# Q# Q# Q# Q# M_0 _M M M M M M M M M M_0 _M M M M_ U F M Y 0 F P K L V H U N L V H H T N V U W U W T W Y H U M M0 M M M M M M M M M M M M M M M Q0 M Q M Q M Q M Q M Q M Q M Q M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M 0 M M M M M M M M M M 0 M M M M M M[..0] M Q[..0] M Q#[..0] M [..0] M R# M # M W# M #0 M # M # M M[..0] M Q[..0] M Q#[..0] M [..0] NTI-M-P-U-NF.NTI.00U NTI-M-P-U-NF.NTI.00U Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. antiga ( of ) ize ocument Number Rev iger - ate: Tuesday, pril 0, 00 heet of 0

9 V FXOR _X_N _X_N U P _M N _M H _M _M F _M _M _M _M _M Y _M W _M V _M U _M T _M R _M P _M N _M H _M _M F _M 0 _M H _M _M F _M _M _M _M _M Y _M W _M V _M U _M T _M R _M P _M _M/N _M/N _M/N _M/N W _M/N W _M/N T _M/N Y _X _X _X _X _X _X _X Y _X _X _X _X _X J _X _X _X _X _X Y _X H0 _X F0 _X 0 _X 0 _X 0 _X 0 _X T _X T _X M _X L _X _X J _X H _X _X F _X _X _X Y _X V _X U _X N _X M _X U _X T _X J _X_N H _X_N NTI-M-P-U-NF.NTI.00U POWR M FX FX NTF M LF OF 0 _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _M_LF _M_LF _M_LF _M_LF _M_LF _M_LF _M_LF _FXOR R W V W 0V_0 V I W V W V W V M L K W _FXOR V U M0 K0 W0 U M T L K..0L J H F Place on the dge oupling P Y W V U M K H F Y W V M L K J H F Y W V U Place P where LV and R taps FOR M Place on the dge V M_LF_MH M_LF_MH M0M_LF_MH V M_LF_MH Y M_LF_MH M0M_LF_MH M_LF_MH U0VKX-P U0VKX-P U0VKX-P U0VKX-P UVZY-P U0VKX-P 0UVMX-P U0VKX-P 0 U0VKX-P 0 U0VKX-P 0UVMX-P U0VKX-P 0UVMX-P 0UVMX-P T..0L 0UVMX-P 0UVMX-P 0UVMX-P U0VKX-P 0 0UVMX-P U0VZY-P V_ U0VKX-P 0 U0VKX-P 0 0UVMX-P 0 0UVMX-P 0UVMX-P oupling P 0 mils from the dge 0 0UVMX-P 0 0 U0VKX-P U0VKX-P 0 U0VKX-P oupling P UF Y V U M K J F Y W V U H F J H F J H F _MH_ T OR NTI-M-P-U-NF.NTI.00U POWR NTF OF 0 _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF 0V_0 M L K J H Y W U M0 L0 K0 H0 0 F Y0 W0 V0 U0 L K J H Y W V L K L K K K K place near antiga Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. antiga ( of ) ize ocument Number Rev iger - Tuesday, pril 0, 00 ate: heet of 0

10 V_0 0V_0 0V_ ohm 00MHz.00. 0ohm 00MHz 0V_ ohm 00MHz V_0 L FM0KF--P L FM0KF--P L FM0F-T0-P L UVZY-P RN RN0J--P R R 0ohm 00MHz Imax = 00 m U 0 0UVMX-P 0UVMX-P H0K-T0P VIN VOUT N N/N# N# 0-0TU-P.000.0F.0.F 0V_U_MH_PLL Not tuff o UVKX-P U0VKX-P U0VKX-P V_0_ m M PLL m M PLL 0 U0VKX-P U0VKX-P U0VKX-P 0 U0VKX-P UVZY-P U0VKX-P m M HPLL M MPLL 0V_RUN_PPLL VRUN_TV VRUN_Q V_0_.m 0m.m R UV0KX-P RN I V_0_ R 0R-0-U-P V_0 0V_0 0V_0 V_0_ V_0 R 0V_U_MH_PLL R 0R-0-U-P m R 0UVMX-P L U0VKX-P R 0m 0UVMX-P H0K-T0P ohm 00MHz 0.m 0UVMX-P 0 I R R0 0RJ--P m 0UVKX-P U0VKX-P U0VKX-P V_ 0 0UVKX-P U0VKX-P V_TXLV_ KP0VKX-P 0 U0VKX-P 0.m R o Not tuff V_RT_0 RN I VTV 0UVKX-P R0 I U0VKX-P M M PLL M PLL M HPLL M MPLL _P_ m 0V_M_K 0m _H U0VKX-P U0VKX-P U0VKX-P VRUN_TV VRUN_Q V_U_LV.m m 0R-0-U-P 0 0UVMX-P UH _RT RT F L J J _PLL _PLL _HPLL _MPLL _LV _P_ R0 _M P0 _M N0 _M R _M P _M N _M T _M R _M P _M P _M_K N _M_K P _M_K N _M_K N _M_K M _M_K_NTF M _M_K_NTF M _M_K_NTF L _M_K_NTF M _M_K_NTF L _M_K_NTF M _M_K_NTF L _M_K_NTF _TV TV_ M L F _LV 0V_RUN_PPLL 0V_M _P_PLL U0VKX-P 0 _TV _Q _HPLL 0V_RUN_PPLL _P_PLL _H M _LV L _LV RT PLL LV P M TV H LV NTI-M-P-U-NF.NTI.00U R I POWR K TV/RT XF M K MI HV P LF OF 0 _XF _XF _XF _M_K _M_K _M_K _M_K _TX_LV _HV _HV _HV _P _P _P _P _P _MI _MI _MI _MI LF LF LF U T U T U T U0 T0 U T U T U T U T U T V U V U T V U F H0 0 F0 K V U V U U H F H L LF LF LF UVKX-P 0m m m UVKX-P V_HV_0 UVKX-P U0VKX-P UVKX-P UVKX-P UVMX--P U0VKX-P UVKX-P 0UVMX-P UVKX-P m V_U_M_K V_TXLV_ UVMX-P KP0VKX-P U0VKX-P UVKX-P 0V_0 V_U_M_K_R R RF-P 0V_0 m 0V_0 00m m U0VKX-P UVMX-P 0UVMX-P 0V_0 V_0 R 0V_HV_0 T--P.000.Z R 0UVMX-P 0 0UVMX-P 0RJ--P 0V_0 V_ R V_ R 0R-0-U-P 0UVMX-P R I V_HV_0 Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. antiga ( of ) ize ocument Number Rev iger - ate: Tuesday, pril 0, 00 heet 0 of 0 U0VKX-P

11 UI U R L W N J F Y T N L Y V R M V R P H F F H Y U T M F V U M J Y T N J N L U M H Y U T M 0 0 V0 N0 H0 0 T M J N L H U H Y U T J F F W T N J H K U NTI-M-P-U-NF.NTI.00U OF 0 M P L J F H Y U T F M J F W V R L H P L H N K F N T N K H F V T R J Y P K H F F H F H V R J Y N L J F Y T J H F R L K J F H Y J UJ 0 OF 0 L W U P N H F R M J 0 0 W0 T0 J0 0 Y0 N0 K0 F0 0 0 W T R M H U N N K W N J N L _NTF _NTF F _NTF V _NTF T _NTF M _NTF _NTF J _NTF _NTF _NTF _NTF Y _NTF N _NTF H _NTF _NTF Y _NTF N NTF #H 0 NTF #H V0 NTF # T0 NTF # J0 NTF # 0 0 N# M0 N# F N# N# N N# M N# N# N# N# H N# N# V N# T N# N#F N# N# N# NTI-M-P-U-NF.NTI.00U NTF TT PIN:,,,H,H NTF N H Y L Y U N J N J V T M M H Y L J H F V L R P F W U R P J H F Y M K M P H U U U U F V J0 M F U U L0 V0 L J U H H F TP TP TP0 TP TP Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. antiga ( of ) ize ocument Number Rev iger - ate: Tuesday, pril 0, 00 heet of 0

12 PRLLL TRMINTION M M [..0] R_VRF_ M 0 0 M 0 /R 0 M R# 0 M /W 0 M W# 00 M / M # Put decap near power(0.v) and pull-up resistor RN M M 0 M_K0 M /0 M_0# M # M / M_# M M M K0 M_K0 0 M_K RNJ--P M K M M 0/P K0 M_LK_R0 RN 0 M M /K0 M_LK_R#0 M_OT0 M M_0# M K M_LK_R M R# M /K M_LK_R# TP M M0 M M[..0] M # 0 RNJ--P / M0 M M M M M M #0 0 0 M RN M M M # 0 M # M 0 M M M 0 M Q0 M M M M M Q Q0 M M M M M Q[..0] 0 M Q Q M M M M Q Q M RNJ--P M Q Q M_IH,, M Q Q V_0 M_IH,, M Q Q L RN M # M Q Q M Q Q VP M_OT M Q Q M_# M Q0 Q 0 00 M Q Q0 RNJ--P M Q Q 0 0 M Q Q N#0 M Q Q N# RN M M Q Q N# 0 M M Q Q N#0 M M Q Q N#/TT M M Q Q M Q Q RNJ--P M Q0 Q V M Q Q0 V M Q Q V RN0 M M Q Q V M M Q Q V M M Q Q V M_K M Q Q V 0 M Q Q V 0 RNJ--P M Q Q V V_ M Q Q V M Q0 V Q RN M #0 M Q Q0 V M M Q Q M 0 M Q Q M W# M Q Q M Q Q RNJ--P M Q Q M Q Q M Q Q M Q Q M Q0 Q M Q Q0 M Q Q M Q Q M Q Q 0 M Q Q M Q Q 0 M Q Q M Q Q V_ Place these aps near M M Q ecoupling apacitor Q M Q0 Q M Q Q0 M Q Q R_VRF_ M Q Put decap near power(0.v) Q 0 M Q Q 0 M Q Q and pull-up resistor M Q Q M Q Q M Q Q 0 M Q Q M Q0 Q 0 M Q Q0 M Q Q M Q Q Q M Q#0 M Q# /Q0 M Q#[..0] M Q# /Q 0 M Q# /Q M Q# /Q M Q# /Q M Q# /Q M Q# /Q 0 /Q M Q0 M Q Q0 M Q[..0] M Q Q M Q Q 0 M Q Q M Q Q M Q Q M Q Q R_VRF Q M_OT0 OT0 M_OT OT 0 VRF 0 0 N N 0 UVZY-P UVZY-P UVZY-P UVZY-P UVZY-P UVZY-P UVZY-P UVZY-P UVZY-P RVR TYP KT-OIMM00UP High.mm UVMX--P UVMX--P UVMX--P UVMX--P UVMX--P Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. R ocket 0 (M) ize ocument Number Rev iger - Tuesday, pril 0, 00 ate: heet of 0

13 M [..0] M M 0 R# M R# 0 0 R_VRF_ M W# M W# 00 PRLLL TRMINTION M # M # M 0 M 0# M_# RN Put decap near power(0.v) and pull-up resistor M M # M_# M M M M K0 M_K 0 M K M_K M M_LK_R RNJ--P M 0/P K0 0 M K0# M_LK_R# RN M_K M M M K M_LK_R M # M K# M_LK_R# M_K TP0 M M0 M M[..0] M # 0 / M0 M M RNJ--P M M #0 0 M M 0 M RN M M M # 0 M M 0 M M M M M M M 0 M Q0 M 0 M M M W# M Q Q0 M M M M Q[..0] M Q Q M RNJ--P M Q Q M Q Q RN M_IH,, M M Q Q V_0 M_IH,, M_OT M Q Q L M_OT M Q Q M R# M Q Q VP M Q Q RNJ--P M Q0 Q 0 00 R_0 M Q Q0 R M Q Q RN 0 0 0KRJ--P M # M Q Q N#0 M M Q Q N# M 0 M Q Q N# 0 M M Q Q N#0 M Q Q N#/TT RNJ--P M Q Q M Q Q RN M Q0 Q V M M Q Q0 V M M Q Q V M M Q Q V M M Q Q V M Q Q V RNJ--P M Q Q V 0 M Q Q V 0 M Q Q V RN0 V_ M #0 M Q Q V M # M Q0 Q V M_# M Q Q0 V M_# M Q Q M Q Q RNJ--P M Q Q M Q Q M Q Q M Q Q M Q Q M Q Q M Q0 Q M Q Q0 M Q Q M Q Q M Q Q 0 M Q Q M Q Q 0 M Q Q M Q Q M Q Q M Q0 Q M Q Q0 M Q Q M Q Q 0 M Q Q 0 M Q Q V_ Place these aps near M M Q Q M Q Q M Q Q ecoupling apacitor M Q Q M Q0 Q 0 Put decap near power(0.v) 0 M Q Q0 R_VRF_ M Q Q and pull-up resistor M Q Q Q M Q#0 M Q# Q0# M Q#[..0] M Q# Q# M Q# Q# M Q# Q# M Q# Q# M Q# Q# M Q# Q# 0 0 Q# M Q0 M Q Q0 M Q[..0] M Q Q M Q Q 0 M Q Q M Q Q M Q Q M Q Q R_VRF Q M_OT OT0 M_OT OT 0 VRF 0 N N 0 UVZY-P UVZY-P UVZY-P UVZY-P UVZY-P UVZY-P UVZY-P UVZY-P MH M MH RVR TYP R-00P--P-U High.mm MH MH UVMX--P UVMX--P UVMX--P UVMX--P UVMX--P Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. R ocket (M) ize ocument Number Rev iger - Tuesday, pril 0, 00 ate: heet of 0

14 V_0 V_0 RP RN0KJ--P INTRNT# WIRL_TN# T_TN# MIL# V_0 V_ LI_LO# INTRNT# WIRL_TN# T_TN# MIL# 0 LI_LO# T_L# WLN_L# INTRNT# WIRL_TN# T_TN# MIL# LUNH 0 -M V_0 LI_LO# T_L# WLN_L# INTRNT# WIRL_TN# T_TN# MIL# TP TP TP TP TP TP TP TP0 TP -ON--P 0.K0.0 0.K0.0 T_L# R WLN_L# WLN_L#_M RJ--P WLN_L# INTRNT# WLN_TT_L Q N00--P.N0. WIRL_TN# T_TN# T_L# MIL# R R Q TZU--F-P T_L Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. LUNH ize ocument Number Rev iger - ate: Tuesday, pril 0, 00 heet of 0

15 0 0 LON_OUT TOUT 0UVKX-P - L/INVRTR/ ONN UPN UPP V_0 R RJ--P F V_0 L_I_LK L_I_T _PWR RIHTN_N LON_OUT PWR_INVRTR POLYW-V-P - L MI_T MI_LK -ONN0-P 0.F F0.00 0U0VZY-P MI_T MI_LK LV MI_T_R MI_LK_R LV_TXLK+ LV_TXLK- LV_TXOUT+ LV_TXOUT- LV_TXOUT+ LV_TXOUT- LV_TXOUT0+ LV_TXOUT0- LV_TXLK+ LV_TXLK- LV_TXOUT+ LV_TXOUT- LV_TXOUT+ LV_TXOUT- LV_TXOUT0+ LV_TXOUT0- RN Pin Pin MI_T_R MI_LK_R Inverter Pin ymbol Vin rightness LON N Pin Vin N ymbol _PWR U- U+ N N LV_TXOUT0- LV_TXOUT0+ LV_TXOUT- LV_TXOUT+ LV_TXOUT- LV_TXOUT+ LV_TXLK- LV_TXLK+ LV_TXOUT0- LV_TXOUT0+ LV_TXOUT- LV_TXOUT+ LV_TXOUT- LV_TXOUT+ LV_TXLK- LV_TXLK+ LV_TXLK+ LV_TXLK- LV_TXOUT+ LV_TXOUT- RN RN0J--P RN RN0J--P RN RN0J--P RN RN0J--P RN I MH_TXOUT0- MH_TXOUT0+ MH_TXOUT- MH_TXOUT+ MH_TXOUT- MH_TXOUT+ MH_TXLK- MH_TXLK+ MH_TXOUT0- MH_TXOUT0+ MH_TXOUT- MH_TXOUT+ MH_TXOUT- MH_TXOUT+ MH_TXLK- MH_TXLK+ _TXLK+ 0 _TXLK- 0 _TXOUT+ 0 _TXOUT- 0 UPP -M MI UPN MI RIHTN_N LON_OUT 0 RN--P R R0 0RJ--P R 0KRJ--P L_KLTTL RIHTN LON_OUT P0VJN-P P0VJN-P LV_TXLK+ LV_TXLK- LV_TXOUT+ LV_TXOUT- LV_TXOUT+ LV_TXOUT- LV_TXOUT0+ LV_TXOUT0- LV_TXOUT+ LV_TXOUT- LV_TXOUT0+ LV_TXOUT0- RN I RN I RN I _TXOUT+ 0 _TXOUT- 0 _TXOUT0+ 0 _TXOUT0-0 _TXLK+ 0 _TXLK- 0 _TXOUT+ 0 _TXOUT- 0 _TXOUT+ 0 _TXOUT- 0 _TXOUT0+ 0 _TXOUT0-0 V_0 MH_LV_ON 0 LV_ON LV_ON_ LV Layout 0 mil 0 L_I_LK 0 L_I_T V_0 _PWR U0VZY-P R I R R 0KRJ--P 0RJ--P U0VZY-P UVZY-P U IN# N OUT IN# N IN# N IN# IN# RU-P.0.0 U0VZY-P RNKJ--P RN L_I_LK L_I_T F V_0 FU-V--P LK I T I RN RN0J--P Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. L ONN ize ocument Number Rev iger - ate: Tuesday, pril 0, 00 heet of 0

16 Q TZU--F-P.00.K R R V_0 FRONT_PWRL PWRL#_ TY_L#_ R FRONT_PWRL#_R 0RJ--P R TY_L#_R 0RF-P L V_ -M V_0 TP TP Q TZU--F-P.00.K R R L-O--P..0 V_0 Media_LK_ Media_T_ MI_INT# TP TP0 TP TY_L _TFULL Q0 TZU--F-P.00.K Q TZU--F-P.00.K R R R R _TFULL# HR_L# R _TFULL#_R 0RF-P R HR_L#_R 0RF-P L L-Y-0-P..0 V_ V_ R V_UX_ R 0RJ--P MI 0 PTWO-ON-P 0.K K0.00 Media_LK_ Media_T_ MI OR RN RN--P M_Therm,,0, M_Therm,,0, MI_INT# HR_L V_ PWRN V_0 V_UX_ 0 K_PWRTN#_N PWRL#_ TY_L#_ L-line_L# NUM_L# P_L# MI_L# R 0KRJ--P K_PWRTN#_N 0 R K_PWRTN# UVZY-P -M -ON--P 0.K0.0 0.K0.0 K_PWRTN#_N NUM_L# P_L# MI_L# PWRL#_ TY_L#_ L-line_L# V_ V_0 TP TP TP TP TP TP TP TP TP TP MI_L# PWRL#_ TY_L#_ L-line_L# K_PWRTN#_N NUM_L# P_L# 0 o Not tuff o Not tuff o Not tuff o Not tuff o Not tuff Q TZU--F-P.00.K L-line_L R R L-line_L# Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Power & Media oard ize ocument Number Rev iger - ate: Tuesday, pril 0, 00 heet of 0

17 Layout Note: Place these resistors close to the RT-out connector RT_R_Y L RT_R F0F-P UVZY-P OK_IN_RT# RT Y L0 RT_ F0F-P RN HYN_ RT_HYN 0 RT_HYN I RT_VYN U RT Y L RT_ THTPW-P F0F-P RN..L RN MH_HYN VYN_ MH_VYN RN0J--P RT_VYN RN0J--P U THTPW-P..L Layout Note: * Must be a ground return path between this ground and the ground on the V connector. RT_R OK_IN_RT_# Pi-filter & 0 Ohm pull-down resistors should be as close as to RT ONN. R will hit Ohm first, pi-filter, then RT ONN. Ferrite bead impedance: 0 ohm@00mhz - RT_ RT_ P0VJN--P V_0 P0VN-P P0VN-P.000.K.000.K.000.K OK_IN_RT# V_0 R 00KRJ--P Q0 N00--P.N0. Hsync & Vsync level shift For ock RT VYN_ HYN_ V_0 V_0 0 U THTPW-P..L U THTPW-P..L HYN_ VYN_ RT I/F & ONNTOR _LK & T level shift V_0 V_0 V_0 V_RT_0 HH-0PT-P V_RT_0.R00.HH P0VJN--P 0UVKX-P P0VJN--P R V_0 RT_IN#_R RT_VYN RT_HYN 00P0VJN-P, RT_# RT_R RT_ RT_ 00P0VJN-P LK T MI RT _RT RT_R RT_ RT_ JV_V JV_H LK_I T_I VIO---P-U RJ--P NP NP NP NP N# N# N N N N N 0 N N.000.K 0 MH_T MH_LK 0 RT_T 0 RT_LK RN I RN RN0J--P RN RNKJ--P T Q LK Q F V_RT_ FU-V-P-U U N00KW-P.00.0F RT onnector RN0 RNKJ--P RT_IN#_R T LK Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev iger - ate: Tuesday, pril 0, 00 heet of 0

18 V_0 0 UVZY-P 0 TM TX- 0 TM TX+ 0 TM TX- 0 TM TX+ 0 TM TX- 0 TM TX+ 0 TM TX0-0 TM TX0+ TM_TX0- HMI_T- HMI_T+ HMI_T- HMI_T+ TM_TX0+_M TM_TX0-_M TM_TX+_M TM_TX-_M TM_TX+_M TM_TX-_M TM_TX+_M TM_TX-_M TM_TX- TM_TX+ TM_TX0- TM_TX0+ RN TM_TX- TM_TX+ TM_TX- TM_TX+ RN0J--P RN RN0J--P RN I RN I V_0 R TM_TX0+ TM_TX0- INP V_O_P_ INN RN TM_TX+ 0 TM_TX- INP RNKJ-P INN TM_TX+ N TM_TX- INP L_R INN _R L_R HP_R _R RXT_P HP_R RXT N I R R0 RF--P TM_TX+ TM_TX- TM_TX0+ Type HMI +V_POWR HMI_LK+ HMI_LK- HMI_T0+ HMI_T0- TM_T0+ TM_T0- TM_T+ TM_T- TM_T+ TM_T- TM_T0_HIL TM_T_HIL TM_T_HIL TM_LOK_HIL 0 TM_LOK+ TM_LOK- KT-U--P MH_HMI_LK MH_HMI_T 0 NV_VI_LK 0 NV_VI_T L /_ROUN HOT_PLU_TT RRV# N 0 N N N V_0 HMI_TT# HMI_ R HMI_HP_M I V_0 R0 KRF--P 0KRF-L-P TM_L TM_ TP HMI_HP_M RN RN0J--P RN K HMI_O_HP Q N00--P.N0.,,0, M_Therm,,0, M_Therm,,, OK_IN# V_0 V_0 Mbus/Pin MO RN0 RNKJ-P HP_R_R O#_P OK_IN_HMI O#_P OK_IN_HMI V_0 V_0 VI_P U OK_IN_HMI O#_P HMI_HP_OK OK_ OK_L V_0 TM_TX- TM_TX+ TM_TX- TM_TX+ TM_TX+ TM_TX- RN0J--P RN R Pin mode KRJ--P R0 R Mbus mode KRF-P Mbus mode R Pin mode UVZY-P U0VKX-P PQFN-P INN INP VI XT OUTP OUTN V_O_P_ V_0 R R I R 0RJ--P VI_P N 0 V_0 V_O_P_ OUTP OUTN W/_TL O#/L_TL I_TL_N HP _UXN L_UXP OUTN OUTP N OUTN OUTP OUTP OUTN 0 V_O_P_ V_O_P_ V_O_P_ UVZY-P UVZY-P R OUTP OUTN N L_UXP _UXN 0 HP MO/I_R OUTP OUTN OUTP OUTN I_R TM_TX+_M TM_TX-_M TM_TX0+_M TM_TX0-_M TM_TX+_M TM_TX-_M TM_TX+_M TM_TX-_M TM_L TM_ HMI_HP_M I_R TM_TX+_OK TM_TX-_OK R V_O_P_ V_0 TM_TX0+_OK TM_TX0-_OK TM_TX+_OK TM_TX-_OK TM_TX+_OK TM_TX-_OK V_ U0VKX-P 0U0VKX-P R KRJ--P R Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. VI ONNTOR iger ize ocument Number Rev ate: Tuesday, pril 0, 00 heet of 0 -

19 P0VJN--P RT_X RT RT_T PWR N MH MH MH MH T-ON-U-P MI 0 Z_RT#_R_MXM Z_YN V_ R V_UX_ RT_T_R LN_OK# 0KRJ--P V_0 R 0 0KRJ--P MI_L# R0 0 RJ--P V_0 M00LF-P-U.R00..R00. Z_RT#_R Z_TLK_M 0, Z_ITLK Z_IT_LK_R,0, Z_YN Z_YN_R, Z_RT# Z_RT#_R Z_TIN0 Z_TIN 0 Z_IN Z_IN Z_TOUT_R,0, Z_TOUT H O UVZY-P RT_UX_ R 0KRJ-L-P R 0KRJ-L-P R MRJ--P MI_L# T_RXN0_ T_RXP0_ T_TXN0 T_TXP0 T_RXN_ T_RXP_ T_TXN T_TXP H_OK_RT# UVZY-P V_0 R 0MRJ-L-P RT_X INTVRMN LN00_LP TP LN_RTYN LN_OMP place within 00 mil of IHM RN RNJ--P-U R0 RJ--P R0 RJ--P P0VJN--P RT_RT# RT_RT# F0 INTRUR# LN_OK# LN_OMP R RF-L-P Z_IT_LK_R Z_YN_R Z_RT#_R Z_IN Z_IN U RTX RTX RTRT# RTRT# INTRUR# INTVRMN LN00_LP LN_LK LN_RTYN F LN_RX0 LN_RX LN_RX LN_TX0 LN_TX LN_TX 0 F H_IT_LK H H_YN H_RT# F H_IN0 H_IN H H_IN H_IN LN_OK#/PIO LN_OMPI LN_OMPO TL# T_RXN0_ J T_RXP0_ T0RXN H T_TXN0_ T0RXP 0U0VKX-P F T_TXP0_ T0TXN 0U0VKX-P T0TXP H TRXN J T_TXN_ TRXP 0U0VKX-P 0U0VKX-P T_TXP_ TTXN F TTXP RT LP LN / LN PU IH Z_TOUT_R R0 RJ--P H_OUT H_OK_N# R H_OK_N#/PIO H_OK_RT#/PIO T OF FWH0/L0 FWH/L FWH/L FWH/L FWH/LFRM# LRQ0# LRQ#/PIO 0T 0M# PRTP# PLP# FRR# PUPWR INN# INIT# INTR RIN# NMI MI# TPLK# THRMTRIP# PI TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP T_LKN T_LKP TRI# TRI K K L K K J J N J J J F L F F H H J F H J 0 F0 H J J H LP_L0 LP_L LP_L LP_L LRQ0# V_LRQ_0 H_PRTP#_R R H_FRR#_R IH_TP et_rxn_ et_rxp_ et_txn_ et_txp_ LP_L[0..] TRI RF-L-P LP_LFRM#, TP TP K0T H_0M# H_PWR,0, H_INN# H_INIT# H_INTR KRIN# H_TPLK# H_THRMTRIP_R LK_PI_T# LK_PI_T R0 LP_L[0..], H_PRTP#,, H_PLP# H_NMI H_MI# Place within 00 mils of IH ball 0V_0 H_PLP# R0 RJ--P R 0V_0 0V_0 H_PWR 0V_0 V_0 R0 H_FRR# et_rxn_ et_rxp_ et_txn et_txp 0V_0 PM_THRMTRIP-#,,,0 Layout note: R needs to placed within " of IH, R must be placed within " of R w/o stub IHM-P-NF.IHM.00U.IHM.U RN RN0KJ--P RT_UX_ RT_UX_ R 0KRF-L-P LN00_LP integrated Vccus_0,Vccus_,VccL_ INTVRMN High=nable Low=isable integrated VccLan_0VccL_0 LN00_LP High=nable Low=isable H_INIT# H_INIT#_ FWH_INIT# FWH_INIT# KRJ--P R0 TP X X-KHZ-P UVZY-P R0 RJ--P R R 0KRF-L-P INTVRMN R0 R0 Q MMT0--P.00.L0 TP 0U0VKX-P 0U0VKX-P R0 RJ--P Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IH-M ( of ) ize ocument Number Rev iger - ate: Tuesday, pril 0, 00 heet of 0

20 INT_PIRQ# INT_PIRQ# INT_PIRQ# INT_PIRQ# IHM-P-NF.IHM.00U RP V_0 PI_PRR# 0 INT_PIRQ# INT_PIRQH# PI_RQ# PI_LOK# PI_RQ#0 INT_PIRQF# INT_PIRQ# INT_PIRQ# INT_PIRQ# INT_PIRQ# PI_RR# V_0 V_0 RNKJ--P-U RP V_0 PI_RQ# 0 PI_RQ# INT_RIRQ PI_VL# PM_LKRUN# PI_TOP# PI_FRM# V_0 LN PI_RXN PI_RXP PI_TXN PI_TXP PI_RXN PI_RXP PI_TXN PI_TXP MINIR PI_RXN PI_RXP PI_TXN PI_TXP MINIR PI_RXN PI_RXP PI_TXN PI_TXP RNKJ--P-U ard Reader U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P TXN TXP TXN TXP TXN TXP TXN TXP PI_IR# PI_PR PI_VL# PI_PRR# PI_LOK# PI_RR# PI_TOP# PI_TR# PI_FRM# IH_PM# INT_PIRQ# INT_PIRQF# INT_PIRQ# INT_PIRQH# RP 0 U N PRN N PRP P PTN P PTP L PRN L PRP M PTN M PTP J PRN J PRP K PTN K PTP PRN PRP H PTN H PTP RNKJ--P-U IHM-P-NF.IHM.00U PI-xpress PI TP0 PLK_IH TP irect Media Interface INT_PIRQ# PI_IR# PI_TR# I#_ OF V_0 MI0RXN V MI0RXP V MI0TXN U MI0TXP U MIRXN Y MIRXP Y MITXN W MITXP W MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP PI_RXN PRN MI_LKN T PI_RXP TXN PRP MI_LKP T PI_TXN U0VKX-P F TXP PI_TXP U0VKX-P PTN F PTP MI_ZOMP F NW R MI_IROMP F PRN/LN_RXN RN PRP/LN_RXP UP0N IH_PI_LK PTN/LN_TXN UP0P IH_PI_0# PTP/LN_TXP UPN RNJ--P IH_PI_LK_R UPP IH_PI_0#_R PI_LK UPN PI_# PI_#_R UPP R PI_0# RJ-P F PI_#/PIO/LPIO UPN PI_MOI_R PI_MOI_R UPP PI_MIO PI_MOI UPN PI_MIO PI_MIO UPP U_O#0 U_O#0 UPN N O0#/PIO UPP N V_0 U_O# U_O# O#/PIO0 UPN N U W U_O# O#/PIO UPP W P U_O# O#/PIO UPN Y U_O# M U_O# O#/PIO UPP Y N U_O# O#/PIO UPN W M U_O# O#/PIO0 UPP W R M U_O# O#/PIO UPN V N U_O# O#/PIO UPP V N U_O#0 O#/PIO UP0N U P U_O# O0#/PIO UP0P U P PI_MOI_R O#/PIO UPN U R U_RI_PN UPP U URI RF-L-P URI# U F F F0 0 F 0 F F H H 0 H PI Interrupt I/F J PIRQ# PIRQ# J PIRQ# PIRQ# OF PI_RQ#0 RQ0# F PI_NT#0 NT0# PI_RQ# RQ#/PIO0 NT#/PIO PI_RQ# RQ#/PIO F NT#/PIO F PI_RQ# RQ#/PIO PI_NT# NT#/PIO F /0# /# /# /# IR# PR PIRT# R VL# PRR# PLOK# RR# J TOP# TR# F FRM# PLT_RT#_R PLTRT# PILK PM# R PIRQ#/PIO H PIRQF#/PIO K PIRQ#/PIO F PIRQH#/PIO R V_0 V_ FP_I PLT_RT#,,,0,,,, R0 PIO R 00KRJ--P MI_RXN0 MI_RXP0 MI_TXN0 MI_TXP0 MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP LK_PI_IH# LK_PI_IH MI_IROMP_R UPN0 UPP0 UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN0 UPP0 0KRJ--P,, M_LK,, M_T V_0 Pair 0 U evice U U T-U U MINI NW 0 luetooth MINI PM_TPPI# PM_TPPU# Z_PKR MH_IH_YN# V_ PM_YN# LOK TOUT PWROK M_LINK_LRT# MLINK0 MLINK PM_RI# PM_U_TT# RT# R00 PM_LKRUN# L KRJ--P LKRUN#, WK# INT_RIRQ M RIRQ V_0 THRM# J THRM# PI_WK# 0,, VT_PWR VRMPWR R0 IH_TP RTL R R 0 T FP_I TP TH/PIO H TH/PIO I#_ TH/PIO WI# PIO PIO LK_L TP PIO LN_PHY_PWR_TRL/PIO TP PW_LR# NRY_TT/PIO /iscrete TH0/PIO K JMIRO_ JMIRO_ PIO F LOK PIO0 I J R LOK/PIO I R PKR_MUT# PIO WOFFR_MUT# PIO TLKRQ# L P_VR0 TLKRQ#/PIO TP P_VR LO/PIO TOUT TOUT0/PIO F PIO TOUT/PIO H TP PIO PIO PIO/LPIO R RN RN0KJ--P 0KRF-N-P TP PIO should be pulled down to N only when using Teenah. When using antiga, this ball should be left as No onnect. R RF-L-P N WM IH_TP No Reboot trap PKR LOW = efaule High=No Reboot U(OK) FP KRJ--P TP R PKR_MUT# U MLK MT LINKLRT#/PIO0/LPIO MLINK0 MLINK F R U_TT#/LPP# Y_RT# M IHM-P-NF.IHM.00U V_0 OOT IO trap PI_NT#0 U_O# PM_TLOW#_R WI# U_O#0 V_ P_VR0 P_VR V_0 PI_NT#0 R0 o Not tuff PI_# R o Not tuff NT0 and PI_# PI_NT# o Not tuff R have a weak internal pull up RI# RP U_O# 0 U_O# PM_RI# PI_WK# V_ PI_# OOT IO Location 0 PI 0 PI LP(efault) swap override strap PI_NT# PMYN#/PIO0 M_LRT# MLRT#/PIO 0KRJ--P R0 WOFFR_MUT# 0KRJ--P RN TP_PI# TP_PU# M PKR J MH_YN# TP H0 PWM0 J0 PWM J PWM RN0KJ--P R 0KRJ--P 0KRJ--P M T PIO locks Y PIO Power MT MI PIO ontroller Link low = swap override enable high = default T0P TP PIO PIO LP# V_ RP 0 V_ U_O# M_LINK_LRT# PIO0 M_LRT# R R 0KRJ--P R OF T0P/PIO H TP/PIO F TP/PIO TP/PIO 0 LK H LK F ULK P LP_# LP_# LP_# _TT#/PIO PWROK PRLPVR/PIO TLOW# PWRTN# LN_RT# RMRT# K_PWR LPWROK 0 0 M R 0 R R _TT# PM_PRLPVR PM_TLOW#_R PWRTN#_IH RMRT#_ PM_LP_M# LP_M# L_LK0 F L_LK L_T0 F L_T L_VRF0 L_VRF L_RT0# F L_RT# PIO/MM_L PIO0/U_PWR_K PIO/_PRNT PIO/WOL_N 0 RN0KJ-L-P RN0KJ-L-P R PIO PIO0 PIO PIO R0 00KRJ--P V_ U_O# RT# U_O# U_O# PlanarI (,0) : 0,0 :,0 : 0, :, RMRT#_K LK_IH LK_IH PWROK, L_LK0 L_T0 L_VRF0_IH L_VRF_IH L_RT#0 PM_U_LK PM_LP_#,0,,,0,,, PM_LP_#,,, TP TP R LK_PWR PWROK, TP TP TP R 0RJ--P ate: Tuesday, pril 0, 00 heet 0 of 0 V_ R PIO U_O#0 U_O# U_O# V_ PM_PRLPVR, PM_PWRTN#, V_0 RMRT#_ V_ Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IH-M ( of ) ize ocument Number Rev.000.Z --P.000.F RN0KJ--P U0VKX-P R0 RN R KRF-P RN RN0KJ--P R 0KRJ--P R 00KRJ--P R RF--P - iger

21 m V_0 V_0 VRF_0 Layout Note: Place near IH m VRF_ m *Within a given well, VRF needs to be up before the corresponding.v rail U0VKX-P V_0 V_ HH-0PT.R00.F 0 UVZY-P UVZY-P HH-0PT.R00.F V_0 V_ V_0 0 V_0 U0VKX-P m in 0;m in // UVKX-P V_0 0m R0 00RJ--P R 00RJ--P m V_0 V_0 RT_UX_ 0UVMX-P 0 U0VKX-P m L IN-UH-0-P.R0.0.R0.0. 0UVMX-P 00 U0VKX-P V_0 u in U0VKX-P V_PLL_0 UPLL=m U0VKX-P 0 U0VKX-P U0VKX-P m UVZY-P 0 0 U0VKX-P U0VKX-P 0UVMX-P UVZY-P VRF_0 VRF_ UVZY-P U0VKX-P UF VRF VRF_U F H H J J K K L L L M M N N N P P R R R R T T T T U U V V U W W K Y Y J TPLL F H J F 0 H0 J0 J RT 0 UPLL VccLan0 0 LN_0 U0VKX-P LN_0 LN_ LN_ LN_ LN_ LN_ LN LNPLL LN_ IHM-P-NF.IHM.00U P RX TX U OR LN POWR OR PU PU P_OR PI OF _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 MIPLL MI MI V_PU_IO V_PU_IO H UH U_0 U_0 U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ L_0 L_ L_ L_ F L L L L L L M M P P T T U U V V V V V V R W 0V_MI_IH_0 Y J 0 F0 0 F J J K J J Vccus_0 F F F T T T T T T U U V V W W Y Y T V_ 0 U0VKX-P U0VKX-P U0VKX-P Vccus_0[] m V_0 U0VKX-P. Layout Note:Place near IHM U0VKX-P 0UVMX-P 0 0 U0VKX-P U0VKX-P V_ V_0 V_0 _=0m U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P Vccus_[] TP U0VKX-P 0 U0VKX-P U0VKX-P V_0 m V_MIPLL_IH_0 0UVKX-P m H U0VKX-P m V_ m U0VKX-P V_ R UVKX-P U0VKX-P U0VKX-P UH 0V_0 m 0V_0 U0VKX-P 0V_0 m U0VKX-P 0 IN-UH-0-P.R0.0 0UVMX-P.R0.0 U0VKX-P U0VKX-P U0VKX-P 0 U0VKX-P L UVKX-P ate: Tuesday, pril 0, 00 heet of 0 V_0 V_0 V_ V_0 V_ Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IH-M ( of ) ize ocument Number Rev U0VKX-P RN0 RN0J--P RN I iger -

22 U OF H J J J K K L L L L L L L M 0 M M M M M M M M N N N N N N N N N N P P 0 P P P P P P F P F V_ V_0 P F P F P H R F R F R F R F R RN0 F R RNKJ--P R R R 0 T T T T V_0 T H T H T H H MU U H U H U H U Q H U 0,, M_LK M_IH,, H U H J U J U J U J V V N00KW-P 0,, M_T V M_IH,, V.00.0F V 0 V V V W W W Y Y Y Y Y H F F F F TP NTF_# NTF_# TP NTF_# TP NTF_# TP NTF_# TP NTF_# TP0 NTF_#J J TP TP0 NTF_#J J TP Wistron orporation NTF_#H H H TP F,, ec., Hsin Tai Wu Rd., Hsichih, NTF_#J J H TP Taipei Hsien, Taiwan, R.O.. NTF_#J J H TP NTF_#H H H NTF TT PIN:,,,,, H,J,J,H,J,J IHM-P-NF.IHM.00U IH-M ( of ) ize ocument Number Rev iger - ate: Tuesday, pril 0, 00 heet of 0

23 PWROK R M0_RT# 0,0,,,0,,, PM_LP_# V_ U Y PWROK,0 N LV0W--P V_0 V_0 R 0KRJ--P M0_FN_TH M0_FN_RIV V_0 MPT-P-U.R00.M R 0KRJ--P K M0_FN_TH_ K *Layout* mil FN 0 U0VZY-P 0 UVMX-P MPT-P-U.R00.M -ON-P-U 0.F F H_THRM H_THRM MMT0--P.00.L0 Q MMT0--P.00.L0 Q.For PU ensor must be near Q.HW T sensor RUN_POWR_ON V_0 Layout notice : oth H_THRM and THRM routing 0 mil trace width and 0 mil spacing Layout notice : oth N and P routing 0 mil trace width and 0 mil spacing must be near M0.ystem ensor, Put between PU and N. must be near Q 0 0P0VJN-P 0 0 R RF-P Layout notice : oth N and P routing 0 mil trace width and 0 mil spacing 0P0VJN-P must be near M0 M0_V_ 0 UVKX-P M0_N M0_P M0_N M0_P N = hannel OPN = hannel +.V = isabled V_0 R 0KRJ--P M0_HN M0_FN_mode N = Fan is OFF OPN = Fan is at 0% full-scale +.V = Fan is at % full-scale U N M_Therm,,0, M_Therm,,0, VT_PWR,0, LRT# LK_K M0_LK_L M0_RT#,,,0 PM_THRMTRIP-# V_0 THRM# 0 -M V_0 M0_FN_TH_ M0_FN_RIV N = Internal Oscillator elected +.V = xternal.khz lock elected V_0 RMRT# Q.00.L0 0 PM_U_LK K suspend clock output V_0 LK_K_R R 0RJ--P R 0KR-P V_0 LK_K V_UX_ PUR_HW_HUTOWN#.000.Z V_R TRIP_T Pin Voltage V_R =(((egree-)/) NOW is 0 PUR_HW_HUTOWN# V_V N P N P N P M0-ZK-P.00. TH N# V_Va M0 R Q.00.L0 R 0KRJ--P HN_L FNa FN_MO 0 FNb TRIP_T V_Vb Y_HN# MLK THRMTRIP# MT POWR_OK# N# N 0 LRT# LK_IN LK_L RT# N# R o Not tuff R TP0 TP TP0 R 0KRF--P R0 0KRJ--P 0P0VJN-P R R RN RN0KJ--P Q N00--P.N0. 0 UVZY-P UVZY-P R KRF-P RMRT# Q0 N00--P.N0. (dummy, K already delay) RMRT#,0 Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Thermal/Fan ontrollor ize ocument Number Rev iger - ate: Tuesday, pril 0, 00 heet of 0

24 T O onnector T onnector O T_RXN_ T_RXP_ V_0 K 0U0VKX-P 0U0VKX-P UVZY-P T0 0U0VZY-P T_TXP T_TXN TP 0KRJ--P T_RXN T_RXP R O_M O_P NP NP KT-TP+P--P-U T NP 0 0 NP T_RXP0 T_RXN0 T_TXN0 T_TXP0 T0 0U0VZY-P UVZY-P 0U0VKX-P 0U0VKX-P K V_0 R-P.R00.HM T_RXP0_ T_RXN0_ LP-ON-P-U 0.F T V_ NP et_txp et_txn et_rxn_ et_rxp_ 0U0VKX-P 0U0VKX-P 0 et_rxn et_rxp 0 NP KT-T+UP--P.0.Z.0.Z U_+ U_- V_T_0 R R T T0UVM-P UPP 0 UPN 0 0 mil U OUT# IN# OUT# IN# OUT# O# N N/N# PU-P U0VKX-P U_O# 0 U_PWR_N#,, - et_rxn et_rxp et_txp et_txn U_+ U_- MI Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. H & ROM & T ize ocument Number Rev iger - ate: Tuesday, pril 0, 00 heet of 0

25 LUTOOTH MOUL. / High ctive Voltage V V_T_0 put near LU / all U put one choke near connector by MI request V_T_0 LU -ON--P-U F0.00 U VOUT VIN N N# N/N# RT-P-P.0.F.00.F 0TU-P U_- U_+ V_T_0 V_0 LUTOOTH_N R0 R UPN 0 UPP 0 Finger printer MOV TO Page -M V_T_0 U_- U_+ TP TP TP TP,0, Z_TOUT,0, Z_YN Z_TIN, Z_RT# RN RNJ-P R M. ONN Z_TOUT Z_YN_ Z_TIN_ Z_RT#_M M NP 0 NP TYO-ONN--P-U 0.F0.0 0.F U0VZY-P _M 0R-0-U-P V_ U0VZY-P 00KRJ--P R I R00 R P0-P Z_TLK_M V_ V_ Z_TOUT Z_YN_ Z_TIN_ Z_RT#_M Z_TLK_M TP TP TP TP TP0 -M V_ TP TP Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. LUTOOTH M Finger printer ize ocument Number Rev iger - ate: Tuesday, pril 0, 00 heet of 0

26 V_ 0 0 UPN0 UPP0 R U_0- U_0+ U U T T00UVM-P 0.0.L0 V_U_0 0 mil U OUT# IN# OUT# IN# OUT# O# N N/N# PU-P U0VKX-P U_O#0 0 U_PWR_N#,, R KT--P--P-U.0.T.0.W UN 0 UPN 0 UPP 0 UPN 0 UPP 0 U U U_O#_U U_PWR_N#,, V_ R U_O# 0 N OR - MLX-ON--P 0.F M V_ TP TP -M TP UPN UPP UPN UPP U_O#_U U_PWR_N# TP0 TP TP TP TP TP N -UTTON# V_UX_ V_0 PTWO-ON--P-U 0.K K0.00 _TN#_N -UTTON# _TN#_N TP TP RN RN0KJ--P -UTTON# _TN#_N R -UTTON# rcad Key# UVZY-P -UTTON# rcad Key# U & N Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev iger - ate: Tuesday, pril 0, 00 heet of 0