Discrete/UMA Schematics Document Sandy Bridge Intel PCH REV : A00

Transcription

1 iscrete/um chematics ocument andy ridge Intel PH REV : 00 :None Installed UM:UM ONLY installed N: ONLY FOR N installed. Q:ONLY FOR Q installed. PL: K9 PL circuit for 0mW solution installed. 0mW: External circuit for 0mW solution installed. MUXLE:MUXLE solution installed. OPTIMU:OPTIMU solution installed. <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. over Page ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet of 0 00

2 .NP-E--P(Mxb*) WK P/N:..H0U HYNIX WK P/N:..I0U MUN TI : o-layout HMI coming from UM(default) & dpu by reserving Resistor(0ohm) for optional selection. NVidia : o-layout HMI coming from dpu(efault) & UM by reserving Resistor(0ohm) for optional selection. RT HMI Left ide: U x IN L 9 ##OnMainoard VRM HMI RT oard luetooth MER,9,90,9 R 00MHz Robson-XT& eymour-xt& Whistler-LP& NP-E VOTRO Finger Print ~W.,,, LV(igal hannel) R RT lock iagram (iscrete/um co-lay) PIe x (iscrete only) FIxx (UM only) iscreet/um o-lay U.0 x ZLI Intel PU andy ridge,,,,,9,0,,, MIx Intel PH ougar Point U.0/. ports ETHERNET (0/00/000Mb) High efinition udio T ports () PIE ports () LP I/F PI.,,9,0,,,,,, Project code : 9.IE0.00 P P/N : 00- Revision : 00 RIII 0/ hannel RIII lot 0 0/ RIII 0/ hannel PIE x U.0 x Tx / U.0x I/O oard onnector U.0 x PIE X U.0 x PIE x RIII 0/ lot PIE x U.0 x PIE x PIE x,u x ET/U/Powershare ombo Mini-ard 0.a/b/g 0/00/ 000 NI Realtek RTLE/0E NE U.0 UP000F Mini-ard WWN VOTRO Express ard (On daughter board) YTEM LO PL9 INPUT OUTPUT 0V_VTT HP MI IN 0V_0 RJ ONN U.0 X ONN IM PU / IL9HRTZ INPUT OUTPUT TOUT V_ORE YTEM / TP INPUT OUTPUT TOUT 0V_VTT YTEM / TPRER INPUT OUTPUT V_UX_ V_UX_ TOUT V_ V_ V_ YTEM / TPRUKR INPUT OUTPUT V_ TOUT 0V_0 R_VREF_ YTEM / IL9HRTZ INPUT OUTPUT TOUT V_FXORE V RT0 9 INPUT OUTPUT TOUT V_ORE TI HRER Q 0 INPUT OUTPUT +_IN_ +PTT TOUT YTEM / TP INPUT OUTPUT V_ V_0 YTEM / 9 INPUT OUTPUT V_ ~ V_V_0 9 Internal igital MI H PEKER zalia OE IT 9H 9 PI Flash ROM M LP us K NUVOTON NPE9P Touch P 9 Int. K T x LP debug port 0 / / Thermal P00 9 ardreader Realtek RT H O Fan ontrol P9 /MM+/M/ M Pro/x <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev QUEEN witches INPUT OUTPUT V_ V_ V_ lock iagram V_0 V_0 V_0 P LYER L:Top L:V L:ignal L:ignal L:N L:ottom ate: Tuesday, January 0, 0 heet of 0 00

3 PH trapping Name PKR INIT_V# NT#/PIO Huron River chematic hecklist Rev.0_ Processor trapping Huron River chematic hecklist Rev.0_ E chematics Notes NT#/PIO Mobile: Used as PIO only 0 NT#/PIO PI_MOI NV_LE N_LE H_OK_EN# /PIO[] V_0 V the desired settings. If a jumper option is used to tie this signal to N as H_O H_YN PIO PIO V_UX_K.V W, x ON for supporting eep leep states PIO PIE Routing LNE LNE LNE Reboot option at power-up efault Mode: Internal weak Pull-down. No Reboot Mode with TO isabled: onnect to Vcc_ with.-k [ - 0-k [ weak pull-up resistor. Weak internal pull-up. Leave as "No onnect". NT[:0]# functionality is not available on Mobile. Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc_power rail. Enable anbury: onnect to Vcc_ with.-k? weak pull-up resistor. isable anbury: Left floating, no pull-down required. Enable anbury: onnect to +NVRM_VQ with.-kohm weak pull-up resistor [R has it pulled up with -kohm no-stuff resistor] isable anbury: Leave floating (internal pull-down) MI termination voltage. Weak internal pull-up. o not pull low. Low (0) - Flash escriptor ecurity will be overridden. lso, when this signals is sampled on the rising edge of PWROK then it will also disable Intel ME and its features. High () - ecurity measure defined in the Flash escriptor will be enabled. Platform design should provide appropriate pull-up or pull-down depending on required by the functional strap, the signal should be pulled low through a weak pull-down in order to avoid asserting H_OK_EN# inadvertently. Note: R recommends -kohm pull-down for F Override. There is an internal pull-up of 0 kohm for _OK_EN# which is only enabled at boot/reset for strapping functions. Weak internal pull-down. o not pull high. ampled at rising edge of RMRT#. Weak internal pull-down. o not pull high. ampled at rising edge of RMRT#. Low () - Intel ME rypto Transport Layer ecurity (TL) cipher suite with no confidentiality High () - Intel ME rypto Transport Layer ecurity (TL) cipher suite with confidentiality Note : This is an un-muxed signal. This signal has a weak internal pull-down of 0 kohm which is enabled when PWROK is low. ampled at rising edge of RMRT#. R has a -kohm pull-up on this signal to +.V rail. PIO on PH is the Integrated lock Enable strap and is required to be pulled-down using a k +/- % resistor. When this signal is sampled high at the rising edge of RMRT#, Integrated locking is enabled, When sampled low, uffer Through Mode is enabled. efault = o not connect (floating) High() = Enables the internal VccVRM to have a clean supply for analog rails. No need to use on-board filter circuit. Low (0) = isables the VccVRM. Need to use on-board filter circuits for analog rails. ard Reader Mini ard(wln) T Table Mini ard(wwn) T U Table Pair 0 X evice Touch Panel / IM U Ext. port (H) Fingerprint LUETOOTH Mini ard (WWN) R REER Pin Name trap escription onfiguration (efault value for each bit is unless specified otherwise) F[] F[] F[:] F[] POWER PLNE V_0 V_0 V_0 0V_VTT 0V_0 0V_0 V_ORE V_FXORE V_V_0 V_V_0 V_V_0 V_UX_ V_ R_VREF_ T+ TOUT V_ V_UX_ V_ V_UX_ V_LN_ V_UX_ PI-Express tatic Lane Reversal PI-Express Port ifurcation traps PE EFER TRININ isabled - No Physical isplay Port attached to : Embedded isplayport. Enabled - n external isplay Port device is 0: connectd to the EMEE display Port LNE Onboard LN Pair evice ML_LK/ML_T X ML_LK/ML_T <Variant Name> LNE U.0 0 H U Ext. port / E-T /U HRER H 9 U Ext. port PH Mus Wistron orporation O-IMM (P) PH_MT/PH_MLK F,, ec., Hsin Tai Wu Rd., Hsichih, LNE Intel E LN N/ 0 U Ext. port O-IMM (P) PH_MT/PH_MLK Taipei Hsien, Taiwan, R.O.. igital Pot PH_MT/PH_MLK -ensor N/ PH_MT/PH_MLK LNE ock Mini ard (WLN) MINI PH_MT/PH_MLK O MER PH_MT/PH_MLK Table of ontent ize ocument Number Rev LNE Express ard ET Express ard QUEEN 00 VOLTE.V.V.V.0V V 0.V 0.V to.v 0. to.v.v.v V V.V 0.V V-.V V-.V V V.V.V.V evice.v Mus REE I / Mus ddresses E Mus attery HRER E Mus PH ep : 0: Normal Operation. Lane Numbers Reversed -> 0, ->,... : x - evice functions and disabled 0 : x, x - evice function enabled ; function disabled 0 : Reserved - (evice function disabled ; function enabled) 00 : x, x, x - evice functions and enabled efault Value : PE Train immediately following xxreet de assertion 0: PE Wait for IO for training Voltage Rails TIVE IN 0 ll states WOL_EN, x Ref es ERIPTION PU ore Rail raphics ore Rail rick Mode only Legacy WOL HURON RIVER OR ddress Hex us Powered by Li oin ell in and +VLW in x T_L/T_ T_L/T_ T_L/T_ ML_LK/ML_T ate: Tuesday, January 0, 0 heet of 0

4 I = PU ignal Routing uideline: PE_IOMPO keep W/=/ mils and routing length less than 00 mils. PE_IOMPI & PE_ROMPO keep W/=/ mils and routing length less than 00 mils. Note: Intel MI supports both Lane Reversal and polarity inversion but only at PH side. This is enabled via a soft strap. Note: Intel FI supports both Lane Reversal and polarity inversion but only at PH side. This is enabled via a soft strap. Note: Lane reversal does not apply to FI sideband signals. ignal Routing uideline: EP_IOMPO keep W/=/ mils and routing length less than 00 mils. EP_OMPIO keep W/=/ mils and routing length less than 00 mils. NOTE. Processor strap F[] should be pulled low to enable Embedded isplayport. tuff to disable internal graphics function for power saving. 0V_VTT PU OF 9 PE_IROMP_R R0 9RF-L-P PE_IOMPI J 9 MI_TXN[:0] N MI_TXN0 PE_IOMPO J MI_TXN MI_RX#0 PE_ROMPO H MI_TXN MI_RX# PE_RXN[0..] MI_TXN MI_RX# PE_RXN[0..] PE_RXN MI_RX# PE_RX#0 K PE_RXN 9 MI_TXP[:0] MI_TXP0 PE_RX# M PE_RXN MI_TXP MI_RX0 PE_RX# L PE_RXN MI_TXP MI_RX PE_RX# J PE_RXN MI_TXP MI_RX PE_RX# J PE_RXN0 MI_RX PE_RX# H PE_RXN9 9 MI_RXN[:0] MI_RXN0 PE_RX# H PE_RXN MI_RXN MI_TX#0 PE_RX# E PE_RXN MI_RXN MI_TX# PE_RX# 0 F PE_RXN MI_RXN MI_TX# PE_RX#9 F PE_RXN MI_TX# PE_RX#0 E PE_RXN 9 MI_RXP[:0] MI_RXP0 PE_RX# E PE_RXN MI_RXP MI_TX0 PE_RX# PE_RXN MI_RXP MI_TX PE_RX# F0 PE_RXN MI_RXP MI_TX PE_RX# PE_RXN0 MI_TX PE_RX# PE_RXP[0..] PE_RXP[0..] PE_RXP PE_RX0 J PE_RXP PE_RX L PE_RXP 9 FI_TXN[:0] FI_TXN0 PE_RX K PE_RXP FI_TXN FI0_TX#0 PE_RX H H9 PE_RXP FI_TXN FI0_TX# PE_RX H E9 PE_RXP0 FI_TXN FI0_TX# PE_RX F PE_RXP9 FI_TXN FI0_TX# PE_RX PE_RXP FI_TXN FI_TX#0 PE_RX F 0 PE_RXP FI_TXN FI_TX# PE_RX F0 PE_RXP FI_TXN FI_TX# PE_RX9 E E PE_RXP FI_TX# PE_RX0 E PE_RXP PE_RX F NOTE. PE_RXP 9 FI_TXP[:0] If PE is not implemented, the RX&TX pairs can be left as No onnect FI_TXP0 PE_RX PE_RXP FI_TXP FI0_TX0 PE_RX E 9 PE_RXP FI_TXP FI0_TX PE_RX E0 PE_RXP0 PE tatic Lane Reversal PE_TXN[0..] FI_TXP FI0_TX PE_RX PE_TXN[0..] FI_TXP FI0_TX 0 PE TXN PE_TXN FI_TXP FI_TX0 PE_TX#0 M9 0 MUXLE U0VKX-P 9 PE TXN PE_TXN FI_TXP FI_TX PE_TX# M 0 MUXLE U0VKX-P 9 PE TXN 0 MUXLE U0VKX-P PE_TXN FI_TXP FI_TX PE_TX# M F PE TXN 0 MUXLE U0VKX-P PE_TXN FI_TX PE_TX# L PE TXN PE_TXN PE_TX# L9 0 MUXLE U0VKX-P PE TXN0 PE_TXN0 9 FI_FYN0 J FI0_FYN PE_TX# K 0 MUXLE U0VKX-P PE TXN9 PE_TXN9 9 FI_FYN J FI_FYN PE_TX# K 0 MUXLE U0VKX-P PE TXN 0 MUXLE U0VKX-P PE_TXN PE_TX# J0 PE TXN PE_TXN 9 FI_INT H0 FI_INT PE_TX# J 09 MUXLE U0VKX-P PE TXN PE_TXN PE_TX#9 H9 0 MUXLE U0VKX-P PE TXN PE_TXN 9 FI_LYN0 J9 FI0_LYN PE_TX#0 MUXLE U0VKX-P PE TXN PE_TXN 9 FI_LYN H FI_LYN PE_TX# E9 MUXLE U0VKX-P PE TXN PE_TXN 09 Modify: PE_TX# F MUXLE U0VKX-P PE TXN PE_TXN un-stuff R0 base on Intel James feedback list. PE_TX# MUXLE U0VKX-P PE TXN PE_TXN PE_TX# F MUXLE U0VKX-P PE TXN0 PE_TXN0 P_OMP PE_TX# E MUXLE U0VKX-P PE_TXP[0..] 0V_VTT R0 9RF-L-P EP_OMPIO PE TXP PE_TXP PE_TXP[0..] R0 ep_hp EP_IOMPO PE_TX0 M MUXLE U0VKX-P PE TXP PE_TXP 0KRJ--P EP_HP PE_TX M MUXLE U0VKX-P PE TXP PE_TXP PE_TX M0 9 MUXLE U0VKX-P PE TXP PE_TXP PE_TX L 0 MUXLE U0VKX-P PE TXP MUXLE U0VKX-P PE_TXP EP_UX PE_TX L PE TXP0 PE_TXP0 EP_UX# PE_TX K0 MUXLE U0VKX-P PE TXP9 PE_TXP9 PE_TX K MUXLE U0VKX-P PE TXP PE_TXP PE_TX J9 MUXLE U0VKX-P PE TXP MUXLE U0VKX-P PE_TXP EP_TX0 PE_TX J F PE TXP MUXLE U0VKX-P PE_TXP EP_TX PE_TX9 H PE TXP PE_TXP EP_TX PE_TX0 MUXLE U0VKX-P PE TXP MUXLE U0VKX-P PE_TXP EP_TX PE_TX E PE TXP PE_TXP PE_TX F 9 MUXLE U0VKX-P PE TXP PE_TXP EP_TX#0 PE_TX 0 MUXLE U0VKX-P E PE TXP PE_TXP EP_TX# PE_TX E MUXLE U0VKX-P PE TXP0 PE_TXP0 EP_TX# PE_TX MUXLE U0VKX-P F EP_TX# N MI Intel(R) FI ep PI EXPRE* - RPHI KT-9909-H0.00. nd = add rd foxcon PU at Xuild batch run rd =.00. NOTE: elect a Fast FET similar to N00E whose rise/ fall time is less than ns. If HP on ep interface is disabled, connect it to PU VIO via a 0-k [ pull-up resistor on the motherboard. <Variant Name> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PU (PIE/MI/FI) ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet of 0 00

5 0V_VTT I = PU 0 Modify: dd 0 p 00 on H_PROHOT#. R0 RJ-P H_PROHOT# R : pf EKLT:pf 000 V. 0 P0VJN-P, H_N_IV# TP-P TP0 TP-P TP0 H_PEI,0, H_PROHOT#, H_THERMTRIP# KTO#_R H_TERR# onnect E to PROHOT# through inverting O buffer. N L N PU N_IV# KTO# TERR# PEI N MI THERML LOK R MI LK LK# PLL_REF_LK PLL_REF_LK# M_RMRT# LK_P_P_R LK_P_N_R LK_EXP_P 0 LK_EXP_N 0 R R KRJ--P 0V_VTT KRJ--P R0 K99RF-L-P 0 Modify: Joseph change RN0 to R,R K 00 Resistor. M_RMRT# R H_PROHOT#_R L M_ROMP_0 R0 0RF-P PROHOT# M_ROMP0 K M_ROMP_ M_ROMP R0 RF-P RJ--P M_ROMP_ M_ROMP R0 00RF-L-P N ignal Routing uideline: THERMTRIP# M_ROMP keep routing length less than 00 mils. OF 9 R isabling uidelines: If motherboard only supports external graphics: onnect PLL_REF_LK on Processor to N through K +/- % resistor. onnect PLL_REF_LK# on Processor to VP through K +/- % resistorpower (~ mw) may be wasted.,,,,, PLT_RT# 9 H_PM_YN 00 9 EMI, H_PUPWR R0 H_PUPWR_R 0R00-P R0 0KRJ--P 9, PM_RM_PWR R0 VPWROO 0RJ--P VPWROO R0 KRF--P E0 R09 0RF-P E0 M00TV-P-U M00TV-P-U UF_PU_RT# 0 0P0VKX-P M P 00 0 EMI 0 Modify: Reserved 0 0pF 00 on UF_PU_RT#. V add rd foxcon PU at Xuild batch run XP_PR# XP_PREQ# XP_TLK XP_TM XP_TRT# XP_TI XP_TO XP_REET# XP_PM0 XP_PM XP_PM XP_PM XP_PM XP_PM XP_PM XP_PM TP TP-P TP TP-P TP0 TP-P TP0 TP-P TP0 TP-P TP0 TP-P TP0 TP-P TP0 TP-P TP09 TP-P TP0 TP-P 00 Modify: Removed XP0 connector related circuit by layout limitation. XP_TO XP_TM XP_TI XP_TLK XP_TRT# 0 Modify: WP RN0 pin,, base on swap report. RN0 RNJ--P 0V_VTT V_0 0 Modify: Joseph Removed U0 uffer reset to PU circuit. 9 XP_REET# XP_REET# R 0KRJ--P 00 Modify: hange R 0K from K XP_TRT# 09 Modify: dd buffer for PLT_RT# based on Intel review. 0V_VTT V_0 XP_REET# uffered reset to PU,,,,, PLT_RT# UFO_PU_RT# R RJ-P UF_PU_RT# E0 KP0VKX-P 00 9 EMI R 0RJ--P R PM_YN UNOREPWROO M_RMPWROK REET# PWR MNEMENT JT & PM N KT-9909-H0.00. nd =.000. rd =.00. PR# P9 PREQ# P TK R TM R TRT# P0 TI R TO P R# L PM#0 T PM# R9 PM# R0 PM# T0 PM# P PM# R PM# T PM# R R RJ--P U0 IN IN V N OUT Y R RJ--P 0 U0VKX-P KP0VKX-P E0 VH09FT-P.009.H <Variant Name> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PU (THERML/LOK/PM ) ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet of 0 00

6 I = PU PU OF 9 PU OF 9 N M Q[:0] _LK0 M IM0_LK_R0 M Q[:0] M Q0 _LK#0 M IM0_LK_R#0 M Q[:0] M Q _Q0 _KE0 V9 M IM0_KE0 M Q _Q M Q _Q M Q _Q M Q _Q _LK M IM0_LK_R M Q _Q _LK# M IM0_LK_R# M Q _Q _KE V0 M IM0_KE M Q _Q F0 M Q9 _Q F M Q0 _Q9 0 M Q _Q0 _LK 9 M Q _Q _LK# F9 M Q _Q _KE W9 F M Q _Q M Q _Q M Q _Q K M Q _Q _LK K M Q _Q _LK# K M Q9 _Q _KE W0 J M Q0 _Q9 J M Q _Q0 J M Q _Q J M Q _Q _#0 K M IM0_#0 K M Q _Q _# L M IM0_# M M Q _Q _# N0 M Q _Q _# H N M Q _Q N M Q _Q M0 M Q9 _Q M9 M Q0 _Q9 _OT0 H M IM0_OT0 N9 M Q _Q0 _OT M IM0_OT M M Q _Q _OT M Q _Q _OT H M Q _Q K M Q _Q K M Q _Q H M Q#[:0] M Q _Q H M Q#0 M Q _Q _Q#0 J M Q# M Q9 _Q _Q# J M Q# M Q0 _Q9 _Q# J J M Q# M Q _Q0 _Q# M K M Q# M Q _Q _Q# L J9 M Q# M Q _Q _Q# M K9 M Q# M Q _Q _Q# R H M Q# M Q _Q _Q# M H9 M Q _Q L9 M Q _Q L M Q _Q P M Q[:0] M Q9 _Q N M Q0 M Q0 _Q9 _Q0 L M Q M Q _Q0 _Q F M M Q M Q _Q _Q K M M Q M Q _Q _Q N L M Q M Q _Q _Q L P M Q M Q _Q _Q M9 N M Q M Q _Q _Q R J M Q M Q _Q _Q M H M Q _Q L M Q9 _Q K M Q0 _Q9 L M Q _Q0 M 0 M [:0] K M Q _Q _M0 0 J M M Q _Q _M W H M Q _M W M M W M M V M M V M M W M 0 E0 M 0 _M W M F0 M _M V M V M 9 M9 W M 0 _M0 M M V M M W M # E M # _M F M R# 9 M R# _M V M WE# F9 M WE# _M V R YTEM MEMORY M Q[:0] M 0 M M M # M R# M WE# M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q F F F F J J K0 K9 J9 J0 K K M N N N M N M M M M R P N N N P P N9 T T P N R R R9 J T T9 H R J H T N R T T N R T 9 R 0 9 _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q9 _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q9 _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q9 _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q9 _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q9 _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q9 _Q0 _Q _Q _Q _0 _# _R# _WE# N R YTEM MEMORY _LK0 _LK#0 _KE0 _LK _LK# _KE _LK _LK# _KE _LK _LK# _KE _#0 _# _# _# _OT0 _OT _OT _OT _Q#0 _Q# _Q# _Q# _Q# _Q# _Q# _Q# _Q0 _Q _Q _Q _Q _Q _Q _Q _M0 _M _M _M _M _M _M _M _M _M9 _M0 _M _M _M _M _M E R9 E R0 T9 T0 E E E E M Q#0 F M Q# K M Q# N M Q# N M Q# P9 M Q# K M Q# P M Q# J M N P K P T R T T T T R T R R T 0 R R M Q0 M Q M Q M Q M Q M Q M Q M Q M 0 M M M M M M M M M 9 M 0 M M M M M M IM0_LK_R0 M IM0_LK_R#0 M IM0_KE0 M IM0_LK_R M IM0_LK_R# M IM0_KE M IM0_#0 M IM0_# M IM0_OT0 M IM0_OT M Q#[:0] M Q[:0] M [:0] N.00. nd =.000. rd = add rd foxcon PU at Xuild batch run N.00. nd =.000. rd = add rd foxcon PU at Xuild batch run <Variant Name> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PU (R) ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet of 0 00

7 I = PU 00 Modify: Reserved TP on F0. TP-P TP F0 F F F F F 00 Modify: Removed F,F,F~ TP. PUE K F0 K9 F L F L F K F L9 F L0 F M F M F M0 F9 M F0 M F N F N F N F M F K F N9 F N OF 9 RV#L L RV# RV#E E RV#K K RV#W W RV#T T RV#M M RV#J J RV#T T RV#J J RV#H H RV# F F R0 KRJ--P MUXLE R0 KRF--P PE tatic Lane Reversal F : Normal Operation; Lane # definition matches socket pin map definition 0:Lane Reversed isplay Port Presence trap F : isabled; No Physical isplay Port attached to Embedded isplay Port 0: Enabled; n external isplay Port device is connected to the Embedded isplay Port 0 Modify: Joseph hange M_VREF_Q_IMM0,M_VREF_Q_IMM, M_VREF IMM0,M_VREF IMM from net to power. M_VREF_Q_IMM0 M_VREF_Q_IMM M_VREF IMM0 M_VREF IMM M - Processor enerated O-IMM VREF_Q R0 0RJ--P R09 0RJ--P R0 0RJ--P R0 0RJ--P :VREF_Q H M_VREF_Q_IMM0_ M_VREF_Q_IMM_ R KRF--P 0 mils 09 Modify: Reserved R0 0ohm to N to follow EV board schematic. R0 0RJ--P :VREF_Q H R KRF--P H_VP_EL J H J H J F F F E J0 9 RV#J RV#H RV#J RV#H RV#J RV# RV# RV#F RV#F RV#F RV# RV# RV# RV#E RV# RV#0 RV# RV#0 RV#9 RV#0 RV# RV#0 RV#9 RV#J0 RV# RV#9 REERVE RV#R RV#T RV#T RV#P RV#R RV# RV# RV# RV# RV# RV#J RV#K RV#H RV#N RV#M RV#T RV#T RV#R R T T P R J K H 00 Modify N TP M TP T T R F F F TP TP R0 KRJ--P TP-P TP-P R0 KRJ--P R0 KRJ--P PIE Port ifurcation traps F[:] : x - evice functions and disabled PE EFER TRININ F 00 Modify: Removed LK_XP_ITP_P&N and reserved TP,TP. 0: x, x - evice function enabled ; function disabled 0: Reserved - (evice function disabled ; function enabled) 00: x,x,x - evice functions and enabled : PE Train immediately following xxreet de assertion 0: PE Wait for IO for training 0V_VTT J RV#J E0 U0VKX-P 09 Modify: Reserved E0 0.uF near R(OTTOM) for EM NEO suggestion. KT-9909-H0.00. nd =.000. N rd = add rd foxcon PU at Xuild batch run <Variant Name> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PU (REERVE) ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet of 0 00

8 I = PU V_ORE PUF N POWER OF 9 VIO Output ecoupling Recommendation: x 0 uf ( x 0 uf for 0 capable designs) x uf & x 00 no-stuff at ottom x uf & x 00 no-stuff at Top V_ORE Q 09 e-cap 0 Modify: un-stuff. PROEOR ORE POWER 0 0UVMX-P 0 Modify: Removed 0, 0uf 00 cap base on layout limitation. 0 0UVMX-P 0UVKX-P UVMX-LP Q 0 0UVMX-P 9 0UVMX-P 0 Modify: Removed 0uf 00 cap base on layout limitation. 0UVKX-P Q 0 Modify: Removed. 0 0UVMX-P Q 0 0UVMX-P Q 0 Modify: Removed,, 0UVKX-P Q 0UVMX-P 0UVKX-P X0 Modify: Reserved 0~0,0,0 0uF 00 for power team fine tune Vcore quality. X0 0 0UVMX-P 0UVKX-P Q 0 0UVMX-P 0 Modify: un-stuff. 0UVKX-P 0UVKX-P V Output ecoupling Recommendation: x 0 uf at ottom ocket Edge x uf at Top ocket avity x uf at Top ocket Edge x uf at ottom ocket avity UVMX-LP UVMX-P UVMX-P 09 e-cap 09 e-cap 0 9 F F F F F F0 F9 F F F Y Y Y Y Y Y0 Y9 Y Y Y V V V V V V0 V9 V V V U U U U U U0 U9 U U U R R R R R R0 R9 R R R P P P P P P0 P9 P P P V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V ORE UPPLY ENE LINE VI PE N R VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VILERT# VILK VIOUT V_ENE _ENE VIO_ENE IO_ENE H H0 0 0 Y0 U0 P0 L0 J J J J H H H F F F F E E E J J9 J0 J J J 0 0 H_PU_VILRT# H_PU_VILK H_PU_VIT PROEOR VIO:. 0 0UVMX-P Q 0 Modify: Removed 0,0,0 0uf 00 cap base on layout limitation. No-stuff sites outside the socket may be removed. No-stuff sites inside the socket cavity need to remain. 0 Modify: Joseph Removed,, VIO_ENE IO_ENE V_ORE 0000 V.0 H_PU_VIT VR_VI_LERT# H_PU_VILK H_PU_VIT 0V_VTT For R VIOUT need to pull high 0 ohm closr to PU and IMVP For R VILERT# need to pull high ohm close to PU R0 0 0UVMX-P RJ-P 9 0UVKX-P 09 0UVKX-P 0 0UVKX-P 0UVKX-P R0 00RF-L-P-U R0 00RF-L-P-U 0UVKX-P 0UVKX-P R0 9 0UVKX-P 0UVKX-P VENE ENE <ore esign> 0 0UVKX-P 0UVKX-P 0V_VTT 0UVKX-P 0RF--P 0V_VTT 00 Modify: Removed R0,R0, already PH closed PWM side. Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. N.00. nd =.000. rd = add rd foxcon PU at Xuild batch run PU (V_ORE) ize ocument Number Rev ustom QUEEN ate: Tuesday, January 0, 0 heet of 0 00

9 I = PU VX Output ecoupling Recommendation: x 0 uf at ottom ocket Edge x uf at Top ocket avity x uf at Top ocket Edge x uf at ottom ocket avity x uf at ottom ocket Edge 0 Modify: V_FXORE un-stuff 90. PU 0 Modify: Removed 90 PROEOR VX: T VX T VX T VX T0 VX T VX T VX R VX R VX R VX R0 VX R VX 0 Modify: R VX Removed 9,99 0uF 00 for V_FXORE. P VX P VX P VX P0 VX P VX P VX N VX N VX N VX N0 VX N 0 Modify: VX N Removed 90 0uf 00 cap. VX M 0 Modify: VX M stuff 90 0uF. VX M VX M0 0 VX M e-cap VX M VX L VX L VX L VX L0 VX L VX L VX K VX K VX K Removed I_ONLY isable Resistor. VX K0 VX K VX R90,R90,R90,R90 K VX J VX J VX J VX J0 VX J VX J VX H VX H VX H VX H0 VX H VX isabling uidelines for External raphics esigns: H VX an connect to N if motherboard only supports external graphics and if FX VR is not stuffed. an be left floating (fx VR keeps VX rail from floating) if the VR is stuffed V_0 90 0UVKX-P 90 0UVKX-P 90 UVKX-P 0 Modify: Joseph Removed T90, T90 0uF cap. 90 0UVKX-P PROEOR VPLL:. 9 0UVKX-P 9 U0VKX-P 90 0UVKX-P 90 0UVMX-P 9 U0VKX-P 90 0UVKX-P 9 0UVMX-P VPLL VPLL VPLL N VPLL Output ecoupling Recommendation: x 0 uf x uf x 0 uf N POWER RPHI.V RIL.00. nd =.000. rd =.00. ENE LINE RIL R -.V RIL VREF MI OF 9 VX_ENE K X_ENE K M_VREF +V_M_VREF_NT PROEOR V: VU_ENE H_F_ V_EL add rd foxcon PU at Xuild batch run V_X_ENE _X_ENE Refer to the latest Huron River Mainstream P (oc# ) for more details on power reduction implementation. +V_M_VREF_NT should have 0 mil trace width L VQ F VQ F VQ F VQ VQ VQ VQ Y VQ Y VQ Y VQ U VQ U VQ U VQ P VQ P VQ P V M V M V L V J V J V J V H V H V_ENE H F_ V_VI 0V_0 +V_M_VREF_NT Routing uideline: Power from R_VREF_ and +V_M_VREF_NT should have 0 mils trace width UVMX-P 9 0UVKX-P PROEOR VQ: UVMX-P 9 0UVKX-P 9 0UVMX-P 9 0UVKX-P VU_ENE H_F_ V_EL 9 0UVKX-P V_X_ENE _X_ENE TOUT V_FXORE V.0 V_0 nd =..L VQ Output ecoupling Recommendation: x 0 uf x 0 uf 0 Modify: Joseph Removed T90,T90 0uF cap. 09 Modify: Reserved E90 0.uF near 9 for EM NEO suggestion. V Output ecoupling Recommendation: x 0 uf x 0 uf at ottom ocket avity x 0 uf at ottom ocket Edge 0 Modify: Removed R90 0ohm closed PU side. 0 Modify: dd R90 00ohm PH to 0V_0. 0 Modify: Removed R90 PH. RN90 RNKJ--P 0 Modify: RN90 change to K PL from 0K base on Intel P updated. E90 U0VKX-P 9 0UVKX-P 9 0UVKX-P T90 X0 Modify: stuff E90 0.uF from EM Neo suggestion. R90 00RF-L-P-U 09 Modify: dd 90,9,99, uf stitching capacitors between V_ & V_0 based on Intel's review 90 U0VKX-P 9 T0UVM--P 9.9.0L U0VKX-P E90 R90 00RF-L-P-U U0VKX-P 99 U0VKX-P 9 U0VKX-P V_ <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PU (V_FXORE) ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet 9 of 0 00

10 I = PU PUH OF 9 PUI 9 OF 9 T T T9 T T T T9 T T T0 T T T R R R9 R R R0 R R R P P P P P P9 P P P0 P P P N0 N N N N9 N N N0 N N M9 M M M9 M M M0 M M M M M L L L L L L9 L L L0 L L L K K0 K K K K9 K K K0 K K J N J J9 J J J0 J J J J J H H H H0 H9 H H H H H9 H H H 9 F F F F E E E E E E0 E9 E E E E Y9 Y Y Y Y Y W W W W W W0 W9 W W W U9 U U U U U T T T T T T0 T9 T T T P9 P P P P P N N N N N N0 N9 N N N M L L0 L L9 L L L L L L L K K K9 K J J H H0 H H H H H H H0 H9 H H H H H H H H 9 0 F F F9 N F F9 E0 E E E E E E E0 E9 E E E E E E E E N.00. nd =.000. rd = add rd foxcon PU at Xuild batch run N.00. nd =.000. rd = add rd foxcon PU at Xuild batch run <Variant Name> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PU () ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet 0 of 0 00

11 (lanking) <Variant Name> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. XP ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet of 0 00

12 (lanking) <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev QUEEN Reserved ate: Tuesday, January 0, 0 heet of 0 00

13 (lanking) <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev QUEEN Reserved ate: Tuesday, January 0, 0 heet of 0 00

14 I = MEMORY 0 Modify: M [:0] R_VREF_ Joseph hange M_VREF_Q_IMM0,M_VREF_Q_IMM, M_VREF IMM0,M_VREF IMM from net to power Modify: Joseph hange M_VREF_Q_IMM0,M_VREF_Q_IMM, M_VREF IMM0,M_VREF IMM R_VREF_ from net to power. 00 0V_0 R0 0R00-P--P U0VKX-P R0 0R00-P--P M_VREF IMM M_VREF_Q_IMM 00 Modify: hange R0,R0 to 0ohm 00 from short pad. U0VKX-P U0VKX-P 9 UVKX-P U0VKX-P Place these caps close to VTT and VTT. 0 UVKX-P M M 0 M M Q[:0] M IM0_OT0 M IM0_OT M_VREF IMM M_VREF_Q_IMM, R_RMRT# 0 Modify: Joseph hange M_VREF_Q_IMM0,M_VREF_Q_IMM, M_VREF IMM0,M_VREF IMM from net to power. U0VKX-P U0VKX-P UVKX-P UVKX-P 0UVKX-P M Q#[:0] M Q[:0] 0V_0 M 0 M M M M M M M M M 9 M 0 M M M M M M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M Q0 M Q M Q M Q M Q M Q M Q M Q H =.mm R-0P--P.00.P nd =.00.N rd =.00.P th =.00.E /P / Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q Q Q 9 Q Q Q Q9 0 Q0 Q 0 Q Q Q 9 Q Q 9 Q Q Q9 Q0 0 Q 9 Q Q Q Q 0 Q Q 0 Q Q9 Q0 9 Q Q 9 Q Q Q Q 0 Q Q Q9 Q0 Q Q Q Q Q Q Q 9 Q 9 Q9 0 Q0 Q 9 Q 9 Q 0 Q0# Q# Q# Q# Q# Q# 9 Q# Q# Q0 9 Q Q Q Q Q Q Q OT0 0 OT VREF_ VREF_Q 0 M REET# 0 VTT 0 VTT 0 Modify: WP M and M location. NP NP NP NP R# 0 WE# # 0# # KE0 KE 0 K0 0 K0# 0 K 0 K# M0 M M M M M 0 M M 00 L 0 EVENT# 9 VP N# N# N#/TET V V V V V V V 9 V 9 V9 99 V V 0 V V V V V V V _IM _IM V_ M R# M WE# M # M IM0_#0 M IM0_# M IM0_KE0 M IM0_KE M IM0_LK_R0 M IM0_LK_R#0 M IM0_LK_R M IM0_LK_R# PH_MT,0,9, PH_MLK,0,9, T#_IMM0_ PRT NUMER.00.P U0VKX-P.00.N(nd) 0 0 U0VKX-P V_ Layout Note: Place these aps near O-IMM. Height.mm.mm V_0 TYPE REVERE _IM 0_IM 0 Modify: Joseph dummy T0 default un-stuff. 0 e-cap REVERE.00.P(rd).mm REVERE.00.E(th).mm REVERE 0 X0 Modify: M st change to.00.p; nd change to.00.n on T stage from ME updated connector list. T0UVM--P T0 U0VKX-P 0 0 0UVKX-P UVKX-P V_0 OIMM EOUPLIN 0 UVMX-P 0 e-cap UVKX-P R0 0KRJ--P R0 0KRJ--P 0 0U0VZY-P UVKX-P 0 0UVKX-P Thermal EVENT T#_IMM0_ 0 0UVKX-P <Variant Name> ate: Tuesday, January 0, 0 heet of 0 Note: If 0 IM0 = 0, _IM0 = 0 O-IMM P ddress is 0x0 O-IMM T ddress is 0x0 If 0 IM0 =, _IM0 = 0 O-IMM P ddress is 0x O-IMM T ddress is 0x V_0 R0 0KRJ--P 0 0U0VZY-P 09 0UVKX-P 0 0UVKX-P Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. R-OIMM ize ocument Number Rev ustom QUEEN 00

15 I = MEMORY 00 Modify: hange R0,R0 to 0ohm 00 from short pad. 0V_0 M_VREF IMM0 M_VREF_Q_IMM0 Place these caps close to VTT and VTT. M [:0] M M 0 M M Q[:0] R_VREF_ 0 Modify: Joseph hange M_VREF_Q_IMM0,M_VREF_Q_IMM, M_VREF IMM0,M_VREF IMM 00 R0 from net to power. 0R00-P--P U0VKX-P R_VREF_ 0 Modify: Joseph hange M_VREF_Q_IMM0,M_VREF_Q_IMM, M_VREF IMM0,M_VREF IMM R0 from net to power. 00 0R00-P--P U0VKX-P U0VKX-P U0VKX-P UVKX-P 0 Modify: Joseph hange M_VREF_Q_IMM0,M_VREF_Q_IMM, M_VREF IMM0,M_VREF IMM from net to power. U0VKX-P U0VKX-P 9 UVKX-P 0 UVKX-P UVKX-P M IM0_OT0 M IM0_OT M_VREF IMM0 M_VREF_Q_IMM0, R_RMRT# M Q#[:0] M Q[:0] 0V_0 M 0 M M M M M M M M M 9 M 0 M M M M M M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M Q0 M Q M Q M Q M Q M Q M Q M Q H =9.mm /P / Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q Q Q 9 Q Q Q Q9 0 Q0 Q 0 Q Q Q 9 Q Q 9 Q Q Q9 Q0 0 Q 9 Q Q Q Q 0 Q Q 0 Q Q9 Q0 9 Q Q 9 Q Q Q Q 0 Q Q Q9 Q0 Q Q Q Q Q Q Q 9 Q 9 Q9 0 Q0 Q 9 Q 9 Q 0 Q0# Q# Q# Q# Q# Q# 9 Q# Q# Q0 9 Q Q Q Q Q Q Q OT0 0 OT VREF_ VREF_Q 0 M REET# 0 VTT 0 VTT 0 Modify: WP M and M location. R-0P--P NP NP NP NP R# 0 WE# # 0# # KE0 KE 0 K0 K0# 0 0 K 0 K# M0 M M M M M M 0 M 00 L 0 EVENT# 9 VP N# N# N#/TET V V V V V V V 9 V 9 V V0 0 V 0 V V V V V V V _IM0 _IM0.00.Q nd =.00.N rd =.00.N th =.00.9 V_ M R# M WE# M # M IM0_#0 M IM0_# M IM0_KE0 M IM0_KE M IM0_LK_R0 M IM0_LK_R#0 M IM0_LK_R M IM0_LK_R# PH_MT,0,9, PH_MLK,0,9, T#_IMM0_ V_ Layout Note: Place these aps near O-IMM. PRT NUMER Height 9.mm _IM0 0_IM0 V_0 OIMM EOUPLIN 0 e-cap TYPE.00.Q 9.mm REVERE.00.N(nd).00.N(rd) 0 U0VKX-P 9.mm REVERE REVERE.00.9(th) 9.mm REVERE 0 U0VKX-P 0 0U0VZY-P 0 X0 Modify: M st change to.00.q; nd change to.00.n on T stage from ME updated connector list. 0 0U0VZY-P UVKX-P U0VKX-P 0 UVMX-P 0U0VKX-P 0 0UVKX-P 0U0VKX-P 0 0UVKX-P 0 e-cap 000 R0 R0 for change to parallel resistor RN0 RN0KJ--P U0VZY-P <Variant Name> 09 0UVKX-P Note: O-IMM P ddress is 0x O-IMM T ddress is 0x O-IMM is placed farther from the Processor than O-IMM 0 0UVKX-P ize ocument Number Rev ustom QUEEN ate: Tuesday, January 0, 0 heet of 0 Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. R-OIMM 00

16 (lanking) <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev QUEEN Reserved ate: Tuesday, January 0, 0 heet of 0 00

17 V_0 RN0 RNKJ--P RN0 RN00KJ--P 09 WP L_TRL_T L_TRL_LK L_KLT_EN LV_V_EN lose to PH side RT_RE RT_LUE RT_REEN L T(PE): This signal is on the LV interface. This signal needs to be left N if ep is used for the local flat panel display 09 WP RN0 RN0F--P Place near PH Impedance:90 ohm RT_LUE RT_REEN RT_RE RT_LUE RT_REEN RT_RE R0 KRF-P L_KLT_EN 9 LV_V_EN 9 L_KLT_TRL 9 LV LK_R 9 LV T_R TP-P TP0 9 LV_LK# 9 LV_LK 9 LV_T0# 9 LV_T# 9 LV_T# 9 LV_T0 9 LV_T 9 LV_T RT LK RT T RT_HYN RT_VYN RN LV LK_R LV T_R L_TRL_LK L_TRL_T LV_I LV_V LV_VREFH LV_VREFL 0 Modify: WP RN0 0 Modify: Joseph Removed LV related net for single LV channel base on ell updated spec. 09 X0 Modify: dd R0~R0 on R signal and reserved E0~E0 0.u from EM Neo suggestion. _IREF_R Notes: K 0.% 00. HIP RE K /W 00 PH J L_KLTEN M L_V_EN P 00 RT_LUE_N N R0 0R00-P--P RT_REEN_P9 P9 R0 0R00-P--P RT_RE_T9 T9 R0 0R00-P--P R0 KR--P RN0 00 0RPR-P L_KLTTL T0 L LK K L T T L_TRL_LK P9 L_TRL_T F LV_I F LV_V E LV_VREFH E LV_VREFL K9 LV_LK# K0 LV_LK N LV_T#0 M LV_T# K LV_T# J LV_T# N LV_T0 M9 LV_T K9 LV_T J LV_T F0 LV_LK# F9 LV_LK H LV_T#0 H LV_T# F9 LV_T# F LV_T# H LV_T0 H9 LV_T F LV_T F LV_T RT_LUE RT_REEN RT_RE T9 RT LK M0 RT T M RT_HYN M9 RT_VYN T _IREF T RT_IRTN ougar Point LV RT OUR-P-U-NF igital isplay Interface OF 0 VO_TVLKINN VO_TVLKINP VO_TLLN VO_TLLP VO_INTN VO_INTP VO_TRLLK VO_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P P M M0 P9 P0 P M9 T9 T T0 V V0 V V U U V V9 P P P P9 T Y Y9 Y Y 9 M M T T H F E F E J 00 Remove HMI from PH. U0VKX-P E0 U0VKX-P E0 U0VKX-P E0 <Variant Name> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PH (LV/RT/I) ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet of 0 00

18 I = PH 009 Modify: Removed INT_PIRQH# on RN0 pin. V_0,,,,, INT_PIRQ# INT_PIRQF# INT_PIRQ# R0 PLT_RT# RN0 0 9 INT_PIRQ# INT_PIRQE# INT_PIRQ# INT_PIRQ# KRJ--P PI_NT# swap override trap/top-lock wap Override jumper PI_NT# Low = swap override/top-lock wap Override enabled High = efault 0 _IT _IT0 Reserved V_0 OOT IO trap NT#/PIO TP/PIO9 OOT IO Location 0 0 LP 0 Reserved 0 Modify: Joseph Remove PLT_RT N gate logic I U0/0. 09 Modify: Reseved R 00K 00 on PLT_RT#. 000 V. RNKJ--P-U R0 KRJ--P R0 KRJ--P R 00KRJ--P PI(efault) 00 PI_PLTRT# _IT0 PU_HOL_RT# PU_PWR_EN# PU_HOL_RT# TP-P TP0 9 PU_PWR_EN# 9 H_FLL_INT T_O_# U0_MI# 9 K_LE_L_ET V_0 PU_PWR_EN# PU_PWM_ELET# TP-P TP0 R 0KRJ--P FF_INT_R 0 0P0VKX-P R0 0R00-P--P TP-P TP0 INT_PIRQ# INT_PIRQ# INT_PIRQ# INT_PIRQ# _IT PI_NT# TP-P TP0 PI_PME# K0 PME# 009 Modify: dd R 0ohm and connect to K_LE_L_ET. PI_PLTRT# PLTRT# (V Tolerance High ctive) LK_PI_LP R0 RJ--P LK_PI_LP_R H9 0 LK_PI_F R0 LK_PI_F_R LKOUT_PI0 RJ--P H LK_PI_K R0 LK_PI_K_R LKOUT_PI RJ--P J LKOUT_PI K LKOUT_PI H0 LKOUT_PI E0 P0VN-P 090 X0 Modify: K LK EMI dd R 0K PL on FF_INT_R(PIO) E0 0P0VJN-P E0 P0VN-P RN0 RN0KJ--P R KRJ--P OUR-P-U-NF 0 Modify: dd E0.pF 00 on LK_PI_LP base on EM NEO suggestion. 00 Modify: hange R,R,R to 0ohm 00 from short pad. 09 Modify: Reserved TP on LKOUT_PI, from vender feedback. V_ PHE TP J TP H TP J TP TP H TP H TP K TP K TP9 TP0 N0 TP H TP H TP M TP M TP Y TP K TP L TP TP9 TP0 TP M0 TP Y TP TP E TP 0 TP E TP J TP TP9 E0 TP0 F TP TP V TP TP U TP Y0 TP U TP Y TP V TP9 W0 TP0 K0 PIRQ# K PIRQ# H PIRQ# PIRQ# PU_ELET# REQ#/PIO0 REQ#/PIO E0 REQ#/PIO NT#/PIO E NT#/PIO F NT#/PIO R 0R00-P INT_PIRQE# R 0R00-P INT_PIRQF# PIRQE#/PIO 0 INT_PIRQ# PIRQF#/PIO R 0R00-P INT_PIRQH# PIRQ#/PIO R 0R00-P PIRQH#/PIO U_O#_ U_O#_ U_O#0_ ougar Point RV PI NVRM U RN0 0 9 U_O#_ U_O#_9 U_O#0_ U_O#_ RNKJ--P-U OF 0 RV Y RV V RV U RV RV T0 RV RV U RV T RV T RV T RV Y RV T RV V RV V RV RV RV RV RV RV E RV RV F RV V F_TV Y RV RV V0 T RV Y RV RV T RV F UP0N UP0P UPN UPP UPN UPP UPN K UPP H UPN E UPP UPN UPP UPN 9 UPP 9 UPN N UPP M UPN L0 UPP K0 UP9N 0 UP9P E0 UP0N 0 UP0P 0 UPN L UPP K UPN UPP E UPN UPP URI# URI O0#/PIO9 O#/PIO0 K0 O#/PIO O#/PIO O#/PIO L O#/PIO9 O#/PIO0 O#/PIO 09 Modify: F_TV (NV_LE) connect PRO_ELET# (H_N_IV#) with R0.K Ó% pull up resistor to PH VPNN rail and a R09 K Ó% series resistor base on Intel feedback. NV_LE NV_LE NV_ROMP U_RI U_O#0_ U_O#_ U_O#_ U_O#_ U_O#_9 U_O#0_ U_O#_ V_ FF_INT_R 9 U_PN0 9 U_PP0 9 U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP O[:0]# for evice 9 (Ports 0-) O[:]# for evice (Ports -) U_PN U_PP U_PN 9 U_PP 9 U_PN U_PP U_O#0_ U_O#_9 <Variant Name> NV_LE NV_LE V_0 MI & FI Termination Voltage anbury Technology: isabled when Low. Enable when High. NV_LE U Ext. port (H) External debug port use on Huron river platform 090 TP0 TP-P R RF-L-P U Table Pair Fingerprint X X R09 H_N_IV# V_0 Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PH (PI/U/NVRM) ize ocument Number Rev QUEEN KRJ--P et to Vss when LOW et to Vcc when HIH evice Touch Panel / IM U Ext. port (H) LUETOOTH Mini ard (WWN) R REER U Ext. port / E-T /U HRE U Ext. port U Ext. port Mini ard (WLN) MER Express ard 0 X0 Modify: Reserved U_O#0_ connect from PH PIO9. ate: Tuesday, January 0, 0 heet of 0 R0 KRJ--P R0 KRJ--P 00

19 I = PH MI_RXN[:0] MI_RXP[:0] MI_TXN[:0] MI_TXP[:0] PH OF 0 FI_TXN[:0] FI_TXP[:0] ignal Routing uideline: MI_ZOMP keep W= mils and routing length less than 00 mils. MI_IROMP keep W= mils and routing length less than 00 mils. 0V_VTT MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP RI_PY 000 V. 0 Modify: hange R90 to 00K 00 from 0K and default stuff. 09 Modify: Y_PWROK R9 connect to Y_PWROK. R9 0KRJ--P 00 Modify: R90 PWROK hange R90 change to 0ohm 00 from short pad. 00KRJ--P U_PWR_K UK# 00 Modify: R90 0R00-P stuff R9 and un-stuff R90. XP_REET# Y_REET# R9 0R00-P K V_0 R90 0KRJ--P Y_PWROK R9 P 0RJ--P, 0_PWR_OO PWROK R9 0R00-P L R90 0R00-P,,,9 RUNPWROK R90 MEPWROK 0RJ--P L0, PM_RM_PWR 0_PWR_OO after PM_LP_# delay 00 ms U_PWR_K R90 99RF-P MI_OMP_R R90 0RF-P PM_RMRT# E0 0 E 0 J J0 W W0 V Y Y0 Y U J H K MI0RXN MIRXN MIRXN MIRXN MI0RXP MIRXP MIRXP MIRXP MI0TXN MITXN MITXN MITXN MI0TXP MITXP MITXP MITXP MI_ZOMP MI_IROMP MIRI UK# Y_REET# Y_PWROK PWROK PWROK RMPWROK RMRT# ougar Point MI ystem Power Management FI UWRN#/UPWRNK/PIO0 FI_RXN0 FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXP0 FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_INT FI_FYN0 FI_FYN FI_LYN0 FI_LYN WVRMEN PWROK WKE# LKRUN#/PIO U_TT#/PIO ULK/PIO LP_#/PIO LP_# LP_# J Y E H J 0 9 F E J0 H9 W V 0 V 0 E 9 N N 0 H F WOVREN PH_PWROK PM_U_TT# U_LK PM_LP_# FI_TXN0 FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXP0 FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_INT FI_FYN0 FI_FYN FI_LYN0 FI_LYN R90 0R00-P PM_RMRT# R9 0KRJ--P PH_WKE# PM_LKRUN# TP90 TP-P R9 0R00-P TP90 TP-P For platforms not supporting eep /.VccU_ and VccW_ will rise at the same time (connected on board).pwrok and RMRT# will rise at the same time (connected on board).lp_u# and UK# are left as no connect.uwrn# used as UPWRNK/PIO0 RT_UX_ PH_ULK_K PM_LP_#,, PM_LP_#,,,, WOVREN - On ie W VR Enable HIH Enabled (EFULT) LOW isabled RT_UX_ PM_PWRTN# E0 PWRTN# LP_# 0 PM_LP_# TP90TP-P R9 0KRJ-L-P, _PREENT TLOW# H0 E0 PREENT/PIO TLOW#/PIO LP_U# PMYNH P PM_LP_U# H_PM_YN TP90TP-P H_PM_YN WOVREN R9 0KRJ-L-P PM_RI# 0 RI# LP_LN#/PIO9 K PM_LP_LN# TP90TP-P OUR-P-U-NF V_ 090 X0 WP RN90 RN90 TLOW# PM_RI# PH_WKE# U_PWR_K RN0KJ--P _PREENT R909 00KRJ--P R9 0KRJ--P PM_PWRTN# R90 0KRJ--P PM_LP_LN# R90 0KRJ--P PM_RMRT# PIE_WKE# R : K EKLT: 0K 090 X0 Modify: move PH_WKE# to RN90 pin dd R909 PH on _PREENT. 09 Modify: hange R90 to 0K ohm based on Intel review:.k to 0K pull-down is recommended. 0 Modify: Joseph removed Q90/R909/R9 V_V_POK and PM_RMRT# related control circuit. PM_RMRT# R9 0R00-P RMRT#_K PM_LKRUN# PH_ULK_K 0 Modify: Reserved E90 on PH_ULK_K for E90 EM NEO suggestion. P0VN-P <Variant Name> V_0 R99 KRJ--P Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PH (M I/FI/PM) ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet 9 of 0 00

20 I = PH PIE_RXN PIE_RXP PIE_TXN PIE_TXP PIE_RXN PIE_RXP PIE_TXN PIE_TXP PIE_RXN PIE_RXP PIE_TXN PIE_TXP PIE_RXN PIE_RXP PIE_TXN PIE_TXP 000 V. 0 Modify: WP WLN LK and LN LK routing each other. 0 Modify: Rename PIE_LK_LN_RQ# to PIE_LK_LN_REQ#. V_0 X0 Modify: ell required us to disable PIE port of WWN slot,if PIE port is disabled, it will cause all PIE port disabled,so change WWN to PIE port from port at T stage. LK_PIE_LN# LK_PIE_LN PIE_LK_LN_REQ# LK_PIE_U# LK_PIE_U U_PE_LKREQ# LK_PIE_NEW# LK_PIE_NEW LK_PIE_NEW# LK_PIE_NEW X0 00 U0VKX-P 00 U0VKX-P 0 U0VKX-P 0 U0VKX-P 009 U0VKX-P 00 U0VKX-P 000 V. LK_PH_M 0 Modify: hange PIE_LK_RQ#&LK_PIE_WLN_REQ# pull high power to V_0 from V_.(add RN0) RN0 RN0KJ--P PIE_LK_RQ# LK_PIE_WLN_REQ# PIELKRQ# and PIELKRQ# upport 0 power only LK_PIE_NEW_REQ# E00 E00 P0VN-P P0VN-P 00 U0VKX-P 00 U0VKX-P E00 P0VN-P RN 00 RN0 0RPR-P RN 00 RN0 0RPR-P RN RN TP-P TP00 TP-P TP00 PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_LK_RQ# LK_PH_R_N LK_PH_R_P LK_PH_R_N LK_PH_R_P PIE_LK_REQ# PE LKRQ# PIE_LK_REQ# LK_PH_R_N LK_PH_R_P ITPXP_N ITPXP_P 00 Modify: Removed XP LOK and reserved TP00,TP X0 Modify: Reserved E00,E00 on LK_PIE_NEW &LK_PIE_NEW# for EM suggestion. PERN J PERP V PETN U PETP E PERN F PERP PETN Y PETP PERN J PERP V PETN U PETP F PERN E PERP Y PETN PETP PERN H PERP Y PETN PETP J PERN PERP U PETN V PETP 0 PERN J0 PERP Y0 PETN 0 PETP ougar Point ard Reader LN W-WN WLN U.0 Intel E LN ock PIE_RXN E PERN PIE_RXP 00 PIE_TXN_ PIE_TXN U0VKX-P PERP W 00 PIE_TXP_ PIE_TXP U0VKX-P PETN Y PETP 00 LK_PIE_WWN# LK_PH_R0_N Y0 LK_PIE_WWN RN0 LK_PH_R0_P LKOUT_PIE0N Y9 0RPR-P LKOUT_PIE0P LK_PIE_WWN_REQ# J PIELKRQ0#/PIO 000 V WP RN0 LK_PIE_WLN# LK_PH_R_N 9 LK_PIE_WLN RN0 LK_PH_R_P LKOUT_PIEN 0RPR-P LKOUT_PIEP LK_PIE_WLN_REQ# M PIELKRQ#/PIO 00 RN0 0RPR-P RN NEW R LKOUT_PIEN LKOUT_PIEP V0 Y LKOUT_PIEN Y LKOUT_PIEP Y LKOUT_PIEN Y LKOUT_PIEP L V LKOUT_PIEN V LKOUT_PIEP L PIELKRQ#/PIO0 PIELKRQ#/PIO PIELKRQ#/PIO PIELKRQ#/PIO LKOUT_PE N 0 LKOUT_PE P E PE LKRQ#/PIO V0 LKOUT_PIEN V LKOUT_PIEP T PH PIELKRQ#/PIO V LKOUT_PIEN V LKOUT_PIEP LK_PIE_NEW_REQ# K PIELKRQ#/PIO K LKOUT_ITPXP_N K LKOUT_ITPXP_P OUR-P-U-NF PI-E* LOK MU ontroller Link MLERT#/PIO MLK MT ML0LERT#/PIO0 ML0LK ML0T MLLERT#/PHHOT#/PIO LKIN_MI_N F LKIN_MI_P E LKIN_N_N J0 LKIN_N_P 0 LKIN_OT_9N LKIN_OT_9P E LKIN_T_N K LKIN_T_P K E_WI# M_LK M_T RMRT_NTRL_PH ML0_LK ML0_T PH_PIO ML_LK ML_T L_LK L_T L_RT# LKOUT_PE N LKOUT_PE P LKOUT_MI_N LKOUT_MI_P LK_UF_EXP_N LK_UF_EXP_P LK_UF_PYLK_N LK_UF_PYLK_P LK_UF_OT9_N LK_UF_OT9_P LK_UF_K_N LK_UF_K_P LK_UF_REF LK_PI_F XTL_IN XTL_OUT PE_LKREQ#_R M_T M_LK JT_TK RJ--P JT_TK_V R00 LK U0 R0 RJ--P LK_PH_M LK_M_V_R PU_PRNT# V Prioritize ////-MHz FLEX on FLEX and FLEX V o not configure ////-MHz FLEX clock on FLEX0 and FLEX if more than PI clocks + PI loopback are routed. FLEX LOK OF 0 MLLK/PIO MLT/PIO L_LK L_T L_RT# LKOUT_PE N LKOUT_PE P REFLKIN LKIN_PILOOPK K H XTL_IN V XTL_OUT V9 RN RN E_WI# M_LK M_T RN00 0RPR-P RMRT_NTRL_PH ML_LK, TP00 TP-P TP00 TP-P TP00 TP-P ML_T, For I_PX mode or MXM mode. PE_LKREQ#_R R00 PE LKRQ#/PIO M0 PE_LKREQ# 0RJ--P LKOUT_MI_N V LKOUT_MI_P U XLK_ROMP LKOUTFLEX0/PIO LKOUTFLEX/PIO LKOUTFLEX/PIO LKOUTFLEX/PIO E H 9 E M M T P0 LKOUT_P_N M LKOUT_P_P M Y XLK_ROMP R00 909RF--P K F H K9 RN0 0RPR-P WP RN00,RN0 RN00 RN0KJ--P PL 0K FOR Integrated LOK EN mode. 0 Modify: R00 WP RN00 RN0KJ--P RN00 LK_UF_OT9_N LK_UF_OT9_P RN0 RN0KJ--P LK_PI_F LK_UF_K_N LK_UF_K_P 0 Modify: WP RN09 RN09 LK_UF_EXP_N LK_UF_EXP_P +VIFFLKN LK_UF_REF LK_PIE_V# LK_PIE_V LK_EXP_N LK_EXP_P 0 Modify: WP RN00 V_00 Modify: dd R00 from RN00. X0 R00 0KRJ--P V_0 For V_ M R00 LK_M_V 090 0RJ--P 00 Modify: Removed LN_XI for LN MHZ and reserved TP Modify: Removed R00 for U.0 MHZ. 009 Modify: dd R00 ohm for LK_M_V. 0 Modify: default stuff R00 ohm for LK_M_V. RN0KJ--P R00 0KRJ--P R00 0KRJ--P 09 WP RN00 XTL_IN XTL_OUT 000 V. V_0 V_0 <Variant Name> RNKJ--P Q00 M_LK M_T ML0_LK ML0_T ML_LK ML_T PIE_LK_REQ# PH_PIO nd =.M0.0F.N0.F N00KW-P R0 0KRJ--P 0KRJ--P RMRT_NTRL_PH R009 KRJ--P UM_I# PU_PRNT# 00 Modify: eparate RN009 0K to RN09, RN0,R00 for layout routing. V_ PH_MT,,9, PH_MLK,,9, UM_I# V_ PIE_LK_LN_REQ# LK_PIE_WWN_REQ# U_PE_LKREQ# Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PH (PI-E/MU/LOK/L) ize ocument Number Rev QUEEN 09 Modify: R009 change to K from 0K base on Intel James feedback list. R : K EKLT: 0K X0 Modify: hange X00 to.000. from.000. from ourcer ick updated. 00 X00 R00 MRJ-P R0 UM 0KRJ--P R0 MUXLE 0KRJ--P RN00 RNKJ--P RN00 RN0KJ--P 00 XTL-MHZ--P P0VJN-P UM_IRETE# UM: I :0 (PX) : 0 0 (Muxless) : 0 0 Modify: WP RN00 PIN,, RN0KJ--P 0 Modify: Move R0 to RN00. ate: Tuesday, January 0, 0 heet 0 of nd =.000. rd =.000. RN00 RN00 RNKJ--P RN00 RNKJ--P P0VJN-P RN0KJ--P RN00 E_WI# PIE_LK_REQ# LK_PIE_NEW_REQ# PE LKRQ# 00

21 I = PH R0 0MRJ-L-P RT_X RT_X RT_UX_ R 0KRJ-L-P R 0KRJ-L-P 00 modify: hange RN0 PH 0K to R,R 0K UVKX-P INTVRMEN- Integrated U.0V VRM Enable High - Enable internal VRs Low - Enable external VRs 0 P0VJN--P 9 H_OE_YN 9 H_OE_RT# 9 H_OE_ITLK 9 H_OE_OUT +V_+.V_H_IO X0 00 H_YN RJ--P H_YN R H_OUT H_OUT 00 Modify: un-stuff R ohm. 00 Modify: hange RN0 to R,R ohm 00. RN0 H_RT# H_ITLK RNJ--P-U RN0 RNJ--P-U 000 R R for change to parallel resistor R0 KRJ--P X-KHZ--P.000. nd = rd = P0VJN--P H_OUT H_YN_R Flash escriptor ecurity Overide Low = efault High = Enable V_0 NO REOOT TRP No Reboot trap R0 KRJ--P H_PKR Low = efault H_PKR High = No Reboot 0 UVKX-P 00 0 P-OPEN RT_UX_ ME_UNLOK 9 H_PKR 9 H_IN0 MRJ-P R0 R0 0KRF-L-P H_OUT R0 KRJ--P RT_X RT_X RT_RT# RT_RT# M_INTRUER# PH_INTVRMEN H_ITLK H_YN H_RT# Notes: ME_UNLOK (H_O) connect to E. Make sure E drive this pin "low" all the time. TP-P TP0 TP-P TP0 TP-P TP0 TP-P TP0 TP-P TP0 PH_PIO PH_JT_TK_UF PH_JT_TM PH_JT_TI PH_JT_TO K N L T0 K E N J H K H PH RTX RTX RTRT# RTRT# INTRUER# INTVRMEN H_LK H_YN PKR H_RT# H_IN0 H_IN H_IN H_IN H_O H_OK_EN#/PIO H_OK_RT#/PIO JT_TK JT_TM JT_TI JT_TO ougar Point RT IH JT T LP T OF 0 FWH0/L0 FWH/L FWH/L FWH/L FWH/LFRME# LRQ0# LRQ#/PIO ERIRQ T0RXN T0RXP T0TXN T0TXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TIOMPO TIOMPI TROMPO TOMPI E K V M M P P M0 M P P0 H H 0 F F Y Y Y Y Y Y0 LP_0 LP_ LP_ LP_ T_OMP LP_[0..] LP_FRME#, K_ET# 9 INT_ERIRQ LP_[0..], 009 Modify: K_ET# connect to PIO.(inter PH 0K) 000 V. 0V_VTT 0V_VTT T_RXN0 T_RXP0 T_TXN0 T_TXP0 09 Modify: Move ll of 0.0uF cap closed to all connector base on Layout guideline. R RF-P T_OMP R 99RF-P T_RXN T_RXP T_TXN T_TXP T_RXN T_RXP T_TXN T_TXP H H O ET +V_+.V_H_IO R0 KRJ--P H_YN This signal has a weak internal pull down. On ie PLL VR is supplied by.v when sampled high,. V when sampled low. Needs to be pulled High for Huron River platform. co-operate with R0,0 PI_LK_R,0 PI_0#_R,0 PI_I_R,0 PI_O_R PH_PI_LK R0 RJ--P PH_PI_0# R09 RJ--P PH_PI_I R0 RJ--P T Y T V U PI_LK PI_0# PI_# PI_MOI PI_MIO PI TRI TLE# T0P/PIO TP/PIO9 H P V P T_ET#0 _IT0 RI_T R 0RF-P T_LE# _IT0 H_YN PLL OVR VOLTE Low =.V (efault) High =.V H_YN: This strap is sampled on rising edge of RMRT# and is used to sample.v VccVRM supply mode. K external pull-up resistor is required on this signal on the board. ignal may have leakage paths via powered off devices (udio odec) and hence contend with the external pull-up. blocking FET is recommended in such a case to isolate H_YN from the udio odec device until after the trap sampling is complete. OUR-P-U-NF RUN_ENLE H_OE_YN N00K--P H_YN_R 0 Modify: Reserved E0,E0 on H_OE_ITLK&H_OE_OUT for EM NEO suggestion. H_OE_ITLK H_OE_OUT PI_0#_R INT_ERIRQ T_ET#0 _PIO RN0 V_0 09 X0 Modify: dd RN0 instead of R 0K. <Variant Name> Q0 R.N0.J 00KRJ--P N =.N Modify: Reserved Q0 for isolate OE and PH base on design guide update.0. 0 Modify: dd R between H_YN_R and H_YN. 00 Modify: dd R 00K and stuff Q0,R. E0 P0VN-P E0 P0VN-P E0 P0VN-P 0 Modify: Reserved E0 on PI_O#_R for EM NEO suggestion. FP_ET# PW_LR# RN0KJ--P RN0 RN0KJ--P Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PH (PI/RT/LP/T/IH) ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet of 0 00

22 V_0 V_0 V_0 R0 RT_ET# U_RT_ON# _EN T_O_PRNT# 00KRJ--P 09 Modify: 000 V. 0 Modify: tuff R0 00K 00 %(NNIE updated) WP RN0 RN0 H_0TE H_RIN# RN0KJ--P PIO has a weak[0k] internal pull up. To enable on-die PLL Voltage regurator, should not place external pull down. R 0KRJ--P PH_TEMP_LERT# MF_MOE PH_PIO R0 0KRJ--P PH_PIO 00 Modify: eparate PH_TEMP_LERT# from RN0 to R 0K base on layout limitation. 000 V. 09 Modify: hange R0 to 00K from 00K. R 0KRJ--P V_0 V_ 09 Modify: dd R 0K 00 on PH_PIO(NNIE updated) 009 Modify: Rename PH_PIO to _EN on R. 090 X0 Modify: change FF_INT_R from PH PIO to PIO Keep PH_PIO PH R0,PH_PIO PH R0 00 Modify: eparate MF_MOE from RN0 PW_LR# to R 0K base on layout limitation. I = PH Note: For PH debug with XP, need to NO TUFF R 0 X0 Modify: Rename PH_PIO to RT_ET# on PIO. 00 Modify: Removed _EN on PIO. 009 Modify: Rename PH_PIO to _EN. Rename PH_PIO to _EN. _PIO 0 E_MI# E_I# _PIO T_O_PRNT#,9,9 PU_PWROK RT_ET# _EN R PIO0 00RJ--P E_MI# PU_HP_INTR# E_I# I_EN# RT_ET# PH_PIO PH_PIO R 0R00-P PW_LR# FP_ET# RN0 0 E_MI# 09 X0 Modify: E_I# Move E_I#,_EN to RN0. PU_HP_INTR# Move _PIO to RN0. _EN Move PW_LR# to RN0. 09 WP X0 Modify: RN0KJ--P Rename FX_R_ET to ENOR_ET on PIO9. X0 Modify: Rename U_PWR_ON to PH_PIO. 0 X0 Modify: 0 X0 Modify: Rename PH_PIO to RT_ET# Reserved U_RT_ON# to control U_RT_ON# on PIO. U0 U power switch from PH PIO. RN0 RN0KJ--P R0 KRJ--P R 0KRJ--P TP-P TP0 TP-P TP0 P-OPEN TP-P TP0 PU_PWROK PH_PIO _EN PLL_OVR_EN MI_OVRVLT FI_OVRVLT MF_MOE ENOR_ET PH_PIO PH_TEMP_LERT# PH_NTF_ 0 Modify: dd TP0~TP09 on PH NTF pin. TP-P TP0 TP-P TP0 TP-P TP09 PH_NTF_ PH_NTF_ PH_NTF_ U_RT_ON# T H E 0 U 0 T E E P K K V M N M V V 9 E E9 F F9 PHF MUY#/PIO0 TH/PIO TH/PIO TH/PIO PIO LN_PHY_PWR_TRL/PIO PIO TP/PIO TH0/PIO LOK/PIO PIO/MEM_LE PIO PIO TP_PI#/PIO PIO TP/PIO TP/PIO LO/PIO TOUT0/PIO9 TOUT/PIO TP/PIO9 PIO NTF_# NTF_# NTF_# NTF_# NTF_# NTF_# NTF_# NTF_# NTF_# NTF_#9 NTF_#E NTF_#E9 NTF_#F NTF_#F9 OUR-P-U-NF ougar Point PIO NTF TET PIN:,,,,,,,,,9,E,E9,F,F9,,H,H,J,J,J,J,J,J,,,9,E,E9,F,F9 NTF PU/MI OF 0 TH/PIO TH/PIO9 TH/PIO0 TH/PIO 0TE PEI RIN# PROPWR THRMTRIP# INIT_V# T_ T_ T_ T_ N_ NTF_# NTF_# NTF_#H NTF_#H NTF_#J NTF_#J NTF_#J NTF_#J NTF_#J NTF_#J NTF_# NTF_# NTF_# NTF_#9 NTF_#E NTF_#E9 NTF_#F NTF_#F9 0 UM_I# VRM_IZE 0 P U P Y Y0 T H K H0 VRM_IZE H_PEI_R PH_THERMTRIP_R INIT_V# K0 T_ R9 0R00-P P H H J J J J J J 9 E E9 F F9 V_0 V_0 FI_OVRVLT T_O_PWRT UM_I# 0 TP0 TP-P TP0 TP-P MI_OVRVLT H_0TE H_RIN# H_PUPWR, PIO (FI_OVRVLT) PIO (MI_OVRVLT) I_EN# H_PEI, H_THERMTRIP#, FI TERMINTION VOLTE OVERRIE MI TERMINTION VOLTE OVERRIE Integrated lock hip Enable ENOR_T ENOR_I R0 0K R0 00K T ignal isable uideline: T_, T_, T_ and T_ should not float on the motherboard. They should be tied to N directly. 00 Modify: hange R9 change to 0ohm 00 from short pad. R0 0KRJ--P R0 0KRJ--P R09 0KRJ--P R0 0KRJ--P R0 0RJ--P R0 90RJ--P TP0 TP-P V_0 ENOR_ET LOW - Tx, Rx terminated to same voltage ( oupling Model EFULT) LOW - Tx, Rx terminated to same voltage ( oupling Model EFULT) Integrated lock Enable functionality is achieved via soft-strap. The default is integrated clock enable. HIH (R )- ILE [EFULT] R0 0KRJ--P R0 00KRJ--P 0 Modify: hange PL 00K 00 from PH on FX_R_ET. [VRM_IZE:VRM_IZE] LL=M / HL= / LH= 00 Modify: Removed R~R 0K 00 on VRM_IZE&. PLL ON IE VR ENLE PLL_OVR_EN R KRJ--P I_EN# R KRJ--P NOTE:This signal has a weak internal pull-up 0K ENLE -- HIH (R UNTUFFE) EFULT ILE -- LOW (R TUFFE) LOW (R)- ENLE PIO has a weak[0k] internal pull up. Integrated lock Enable functionality is achieved via soft-strap. The default is integrated clock enable. <Variant Name> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PH (PIO/PU) ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet of 0 00

23 I = PH 00 R0 V 0 0V_VTT (ufx) (0uFx_00) (uf x) 0V_VTT 0 0UVKX-P VVRM(Internal PLL and VRMs):..V for Mobile.. V for esktop 0 0UVKX-P 0 e-cap V_0 0 UVKX-P 0V_VTT 0V_VTT 0. (Totally V_ current) (0.uF x) V_0 0.9(Totally current of VVRM) TP-P TP0.(Total current of VORE) 0 UVKX-P 09 UVKX-P VFIPLL +.0V_V_MI 0 U0VKX-P 0.0 (Totally current of VMI) VORE VORE VORE VORE F VORE F VORE VORE VORE VORE VORE VORE 9 VORE J VORE J VORE J VORE J9 VORE J VORE N9 TP-P TP0 VPLLEXP (0uF x) J VPLLEXP.9(Total current of VIO) N VIO 0 UVKX-P 0 U0VKX-P 0 UVKX-P N N N N P P P P T N N H9 P P U0 PH VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO V_ VVRM VFIPLL VIO VMI POWER ougar Point V ORE VIO FI OUR-P-U-NF RT LV NN / PI MI HVMO OF 0 V VLV LV VTX_LV VTX_LV VTX_LV VTX_LV V_ V_ VVRM VMI VLKMI VccFTERM VccFTERM VccFTERM VccFTERM VPI U U K K M M P P V V T J J +V +V_V_LV 0. VVRM (0.uF/0.0uF x) (0uF x_00) +.V_VTX_LV UVKX-P 00 0UVKX-P (0.uFx) UVKX-P X0 Modify: hange V power source to V 0 from V_0. L0 H0KF--P 00 (ufx) V_0 V_0 0V_VTT R00-P--P T0 +.0V_V_MI R0 (uf x) 0R00-P--P 0 UVKX-P 0V_VTT +.0V_V_MI_I R0 0R00-P--P (ufx) (0uFx) UVKX-P V V_ R0 0R00-P 09 X0 Modify: hange R0 to 0R00 short pad from 0ohm. (0.uFx) V_0 V_0 V_0 V_0 (0.0uF x) (uf x) 9 X0 Modify: Reserved R0 on VVRM power rail. Refer to NPE9 shared PI flash architecture V_.V RT LO urrent Limit=0m V_0 V 0 U0 X0 Modify: Removed U0 LO for VVRM. VIN N EN VOUT N# 909-0TU-P.0909.JF nd =.099.F rd =.0.F 000 V. X0 Modify: dd 909 LO circuit for RT power to avoid monitor noise issue. X0 Modify: base on layout condition change V 0 circuit add rd Richtek(.099.F) on U0 at Xuild batch run config 0 UVKX-P U0VKX-P 9 U0VKX-P U0VKX-P R0 0UVKX-P 0UVKX-P 0R00-P--P 0UVKX-P.00.0 nd = rd =.00.0 R0 0R00-P U0VKX-P UVKX-P <Variant Name> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PH (POWER) ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet of 0 00

24 I = PH V_0 0V_VTT 0V_VTT L0 IN-0UH--P.000.0Y nd =.00E.0N 00 R0 00 +VIFFLK +V.0_V (0uFx) (ufx) +V._V_LKF 0 0V_VTT (ufx_00) (ufx) 0V_VTT 0.0 (ufx) (0uFx) L0 +.0V_V PL IN-0UH--P.000.0Y nd =.00E.0N 09 UVKX-P 0.0 L0 (ufx) (0uFx) +.0V_V PL IN-0UH--P.000.0Y nd =.00E.0N 0 UVKX-P R0 0R00-P--P 0R00-P--P 0UVMX-P 0UVMX-P 0UVKX-P UVKX-P UVKX-P 0 U0VKX-P 0V_VTT (ufx) 0 0UVKX-P U0VKX-P V_ 0V_VTT RT_UX_ (0.uFx) (0.uFx) 0.00 u (0.uFx) (ufx) TP-P TP R0 TP-P TP0 +VRTEXT 0V_VTT(0uFx) +VIFFLKN VLK +VPW PUYP +V._V_LKF +VPLL_PY_PH +VU.0 (Total current of VW) 0 Modify: Reserved, on +.0V_V PL, +.0V_V PL same as. 0 Modify: Joseph Rename V_0_V_0 to V_0 for VVRM. 0 0UVKX-P R0 0R00-P (0.uFx) (ufx) (0.uFx) (.ufx_00) UVKX-P TP-P TP0 TP-P TP0 UVKX-P 0. (Totally current of VVRM 0.0 0R00-P 0 UVKX-P V_0 +.0V_V PL +.0V_V PL +VIFFLK (ufx) e-cap +V.0_V U0VKX-P(uFx) +VT TP-P TP0 0 Modify: Removed 9 uf base on nnie updated schematic. 0 UVKX-P U0VKX-P U0VKX-P 0 U0VKX-P U0VKX-P PU 9 T V T H L9 L W W W W W9 W W N Y9 F PUYP VW VW VW VW VW VW VW VW VW VW VW VPLL F VIO F VIFFLKN F VIFFLKN VIFFLKN V VLK VW PRT VVRM VPLL V PT T PU V9 PU J PHJ VW_ V_ VPLLMI VIO PU VW VW VW VW VW VW VW VW V_PRO_IO VRT POWER lock and Miscellaneous PU RT OUR-P-U-NF ougar Point T PI/PIO/LP U MI H 0 OF 0 VIO VIO VIO VIO VIO VU_ VU_ VU_ VU_ VU_ VIO VREF_U PU VU_ VREF VU_ VU_ VU_ VU_ V_ V_ V_ V_ VIO VIO VIO VIO VPLLT VVRM VIO VIO VIO VW VW VW VUH N P P T T9 0V_VTT 0V_VTT +V_PH_VREFU +V_UU +V_PH_VREF +V.0_VPLL_T V_0 0.0 V_ +V_+.V_H_IO V_VTT V_ 0.09 (Totally current of VU_) T (0.uFx) T V V P T M N N P N0 N P0 P W T J F H H F K F T V T9 P U0VKX-P UVKX-P 0 U0VKX-P 9 U0VKX-P UVKX-P 0 e-cap U0VKX-P (0.uFx) (ufx) U0VKX-P 0 e-cap U0VKX-P V_ (0.uFx) V_ (ufx) (ufx) 0.00 TP0 TP-P 0V_VTT V_0 (0.uFx) (0.uFx) (ufx) nd =.R00.F V_0 0V_VTT 0V_VTT R (0uFx) 0RJ-0-U-P 0UVKX-P U0VKX-P U0VKX-P U0VKX-P <Variant Name> V_ nd =.R00.F V_0 +V_+.V_H_IO 0 HH-0PT-P.R00.F R0 U0VKX-P ate: Tuesday, January 0, 0 heet of 0 0RJ--P V_ V_0 0 HH-0PT-P.R00.F R0 (ufx) 0RJ--P U0VKX-P R09 0R00-P V_ Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PH (POWER) ize ocument Number Rev QUEEN (0.uFx) 00

25 I = PH PHI 9 OF 0 PHH H E E F0 F F F9 F F F F9 F F F F F F F F 9 H H H H9 H0 H H H J9 J J J J K K OUR-P-U-NF ougar Point OF 0 K K K K K L L L9 L L L L L L L L L M M M M9 M M M M N N9 N N P P9 P P0 P P P P P P R R T T T T T T T0 T T T9 T T T U U0 V V0 V V0 V V V V W W W W W W W W W W0 W V Y Y Y Y Y Y Y 9 9 F E E E0 F0 F F F0 F F F F F0 F F0 F H H H H9 H0 H H H H H9 H H 0 E E 0 H H H H H H0 H H F ougar Point H K K K9 K K L L L0 L L L L M P M M M M0 M M M M M M M N P0 N P P T P0 P P P R R T T T T W T T T V V V V V9 V V V9 V V W W9 W W W Y Y Y Y Y Y 9 N J E0 H T P M P P E J <Variant Name> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. OUR-P-U-NF PH () ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet of 0 00

26 (lanking) <Variant Name> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Reserved ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet of 0 00

27 I = K V_UX_K 0 Modify: hange 09,0 to E_N from N. R0 VT 0R00-P 0 Modify: R Move R to closed V_UX_K power R--U-P rail base on layout placement. V_UX_K_V 0 U0VKX-P 0 U0VKX-P 0 U0VKX-P 0 U0VKX-P 0 _I E_N E_N U0VKX-P P_VER_ 00 Modify: PI_E tuff 0.uF on _I. PU_THRM FN_ 9 L_TT 00 Modify: MEI_TN# Rename E_EN to MEI_TN# on PIO9. 00 Modify: Rename HRE_LE# to H_MER_LE# 9 U_PWR_K Rename _TFULL# to TT_WHITE_LE#. UHRER_0 U_PWR_ON U_PWR_ON Y_THRM 00 Modify: PL_IN Rename E_PIO to PL_IN MOEL_I_ET 00 Modify: TT_WHITE_LE# Rename IRETE# to MOEL_I_ET. EMI#_K Rename E_PIO for MEI_TN#. 9 P_LE _ENLE MEI_TN# 9 T_IN# 0 LI_LOE# 9 RMRT#_K 9,, PM_LP_# ME_UNLOK RI 09 Modify: PL_IN Rename TP_LOK_LE#&TT_WHITE_LE# PL_OUT 00 Modify: E_PIO Rename E_PIO0 to PL_IN WIFI_RF_EN Rename E_PIO to PL_OUT, LUETOOTH_EN 9, 0_PWR_OO TP_LOK_LE# U_PWR_EN# 9, _PREENT, IMVP_PWR R E_PIO9 0 U0VKX-P 00 Modify: 00 0R00-P--P RN0 pull-low 0K Resistor to K_VORF on LUETOOTH_EN. 00 Modify: K PIO change to IRETE# K PIO9 change to IMVP_PWR. 0 U0VKX-P 09 U0VKX-P RO Multi PIO setting 0 U0VKX-P U0VZY-P U0 Need very close to E V 9 V V V V 0 VREF 9 PIO90/0 9 PIO9/ 99 PIO9/ 00 PIO9/ 0 PIO9/0 0 PIO9/ 0 PIO9/ 9 PIO 9 PIO/ 9 PIO/ 0 PIO/ 9 PL_IN#_PIO 9 PIO/ PIO PIO 09 PIO0 PIO/IRRXL PIO 0 PIO PIO/TK 0 PIO/TM PIO/TI PIO/IRRXM/TRT# PIO PL_IN_PIO0 PL_OUT_PIO VKUP PIO PO/HM PIO 9 PIO 0 PO/IOX_LH/TET# PIO/IOX_LK/XORTR# 0 PIO9 VORF N N N N N N NPE9P0X-P-U 9 V 0 V E_N N 0 0 U0VKX-P OF LREET# LLK LFRME# L L L L0 ERIRQ PIO/LKRUN# 9 PIO/MI# 9 EI#/PIO PIO0/LPP# PIO/PWUREQ# PIO/0 KRT#/PIO PIO/PT/R# PIO0/PLK/TO PIO/PT 0 PIO/PLK PIO/PT PIO/PLK PIO/L PIO/ PIO/L PIO/ PIO/L PIO/ PIO/L PIO/ F_0# F_K 9 F_I/F_IO F_IO/F_IO0 V_0 09 Modify: Reserved 0.uF on all of input pins base on NUVOTON feedback list.(~) R 00 PLT_RT#_E PLT_RT#,,,,, 0R00-P--P LK_PI_K LP_FRME#, LP_ LP_ LP_[0..], LP_ LP_0 PNEL_LEN EI#_K EWI#_K _I_HW MEI_TN# E_ENLE#_ PROHOT_E E_PI_#_ E_PI_LK_ E_PI_I_ E_PI_O_ 0 U0VKX-P 0P0VKX-P 00 INT_ERIRQ PM_LKRUN# 9 HMI_IN# H_0TE H_RIN# LON_OUT 9 _I_HW 0 PH_WKE# 9 TPT 9 TPLK 9 P_VER_ T_L 9,0 T_ 9,0 ML_LK 0, ML_T 0, PM_LN_ENLE L_TT_EN 9 R RJ--P R9 RJ--P R 0R00-P--P R RJ--P NOTE: Locate resistors R,R9 and R close to the NPE9P. NOTE: onnect N and N planes via either 0R resistor or one point layout connection. 00 U0VKX-P V_UX_K E_N 00 Modify: Rename PH_TEMP_LERT# for HMI_IN# PI_0#_R,0 PI_LK_R,0 PI_O_R,0 PI_I_R,0 E_PI_I_ 00 Modify: Rename HRE_LE# to H_MER_LE# Rename _TFULL# to TT_WHITE_LE#. FN_TH 9 PM_PWRTN# 009 Modify:, PIE_WKE# E_PIO change to PH_WKE# to PH. 9,,,, PM_LP_# 009 Modify: K_ET# rename to MEI_TN# on K PIO. H_MER_LE# 9 K_EEP MEI_LE# 9 K_L_TRL 0 _I_HW MEI_LE# MEI_LE# PWRLE# 09 Modify: Rename PWRLE#&PWR_TN_LE#&HRE_LE#. 0 Modify: Removed PWR_TN_LE# on K PIO. 00 Modify: hange MEI_LE# to K PIO. dd _I_HW on K PIO. E_Rx E_Tx < TP R KRF-P R 00KRF-L-P Reserved Reserved < TTERY / HRER <------PH / ep R 00KRJ--P P VERION /(PIN9) PULL-LOW REITOR PULL-HIH REITOR VOLTE X00 X0 X0 00 Reserved Reserved, 0V_VTT 9 H_PEI 00.0K 00.0K 00.0K 00.0K 00.0K 00.0K 00.0K 00 Modify: K_PIO change to PIE_WKE#. 9 MP_MUTE# PH_ULK_K ERT# R RJ-P PEI E_VTT R0 0R00-P Need very close to E 0.0K 0.0K.0K.0K.9K. 00.0K V.0.0V.V.V.V.0V.V.V 00.0K.0K.V.0K Reserved 00.0K.0V Reserved 00.0K.0K.0V NOTE: The NPE9P PIO/PWM outputs that are connected to LEs have high drive buffers (0m) and can be connected directly to the LEs. UVKX-P 0 U0.0.L MOEL_I_ET U0VKX-P V_UX_K E_N 00 Modify: Rename IRETE# to MOEL_I_ET. hange R9 to 00K 00 from 0K. OF MOEL_I_ET(PIO0) R0 Q_TI KRF-P Q_NVII 0 N_UM Ventura need to change to K(..L) N_TI Q_UM Q_TI N_UM KOL[0..] 9 E_MI# PULL-LOW REITOR PULL-HIH REITOR VOLTE Q_UM 00.0K 0.0K.0V 00.0K 00.0K 00.0K 00.0K 00.0K 00.0K 0.0K.0K.0K.9K.K 00.0K 00.0K.0K.V N_TI 00.0K.0K.0V Q_Ventura 00.0K.0K.0V EMI#_K.V.V.V.0V.V.V K=..L Notes: The total PI interface signal between E and PH can t not exceed 00mil. The mismatch between PI signal must be within 00mil KOL0 V_UX_K PIO/T KOUT0/JENK# KOL PIO0/T KOUT/TK KOL 00 PIO/T KOUT/TM 0 KOL RN0 PIO0/T KOUT/TI 9 KOL MEI_TN# KOUT/JEN0# KOL MOEL_I_ET PIO/_PWM KOUT/TO KOL PIO/_PWM KOUT/R# KOL PIO/_PWM KOUT KOL RN00KJ--P PIO/_PWM KOUT KOL9 PIO/_PWM KOUT9/P_VI# KOL0 00 R9 R for change to parallel resistor PIO/H_PWM KOUT0/P0_LK 0 9 KOL E_N PIO/E_PWM KOUT/P0_T KOL PIO0/F_PWM KOUT/PIO KOL KOUT/PIO KOL 009 Modify: KOUT/PIO KOL Removed R 0K PH on E_PIO. V_POR# KOUT/PIO/XOR_OUT KOL 0 Modify: PIO0/KOUT U_ET# Un-stuff 0 and dd R0 between E_MI# and PIO/KOUT EMI#_K already confirm with NUVOTON and W. PIO/IRRXM/IN_R KROW0 KROW[0..] 9 PIO/OUT_R/TRIT# KIN0 KROW KIN KROW PIO/LKOUT/IOX_IN_IO KIN KROW 0 PIO00/EXTLK KIN KROW E_MI# KIN 9 KROW KIN KROW 0 EMI#_K PEI KIN KROW --P VTT KIN 0 Modify: dd U_ET# on K PIO/KOUT. NPE9P0X-P-U.000.K N =.000.F 00 R0 0R00-P--P L_KLT_EN K_PWRTN# 09 Modify: Reserved 0.uF on all of input pins base on NUVOTON feedback list.(~) 9 PU_THRM 0 U_PWR_ON Y_THRM PNEL_LEN R 0R00-P 00 Modify: Removed R 00K _IN#_K U0VKX-P U0VKX-P U0VKX-P TPT-P N =.000.Q.R00.E E_N PL_IN.R00.E N =.000.Q K_ON# 0 0mW TPT-P R0 0 E_PIO 0KRJ-L-P K_ON#_R _IN# V. E_WI# E_I# 090 X0 Modify: dd 0.uF between Q0 & pin for fixed leakage voltage to V_UX_K under mode. 09 X0 Modify: dd Q0 N00 to avoid leakage loop from V_ to V_UX_K issue when 0mW latched fail timing. V_UX_ K_ON#_TE 0 --P EWI#_K.000.K N =.000.F EI#_K V_UX_ E_N.000.K N =.000.F 0 Modify: Un-stuff 0,0 and dd R,R9 ohm confirm with NUVOTON and W. R EWI#_K 0 E_WI# 0R00-P--P 00 EI#_K E_I# R9 0R00-P--P RN0 RN0KJ--P U0VKX-P 0 --P R 0R00-P U0VKX-P N00K--P V_UX_K _ENLE Q0.N0.J N =.N0.0 0 Q0 MP0L--P N = E_PIO High ctive PROHOT_E _OK PL_OUT R 00KRJ--P PL OLUTION RT_UX OK R N00K--P Q0.N0.J N =.N0.0 PL R E_PIO 0mW 0R00-P--P 00 K_ON#_R 0RJ--P 00 Modify: dd Pull down 00k ohm at F_I for Power consumption concern. H_PROHOT#_E R 0R00-P 0 Modify: default stuff R, un-stuff R. 00 R PL 0RJ--P Q0 N00K--P.N0.J N =.N0.0 PL_IN PL R9 00KRJ--P V_UX_K 00 Modify: Rename E_PIO to PL_OUT _IN#_K E_ENLE#_ K_ON#,, H_PROHOT#,0, 0mW OLUTION V_UX_K R 0mW 00 Modify: Rename E_PIO0 to PL_IN E_PIO 0RJ--P 00 PL_IN PURE_HW_HUTOWN# VKUP PL_IN PL_OUT 00 K_ON# Q0.N0.J N =.N0.0 R 0mW K_ON#_R 0R00-P--P NOTE: Please make sure there's no pull-down resistor on U_PWR_EN#,_PREENT,E_TX. R 0R00-P--P N00K--P 0mW V_UX_ R0 0KRJ--P 0 Modify: Removed R FN_TH T_L T_ T_IN# _IN#_K _ENLE ERT# E_ENLE#_ E_Rx E LUETOOTH_EN Q0 FN_TH ERT# E PIO standard PH/PL 00 Modify: Removed LI_LOE# PH 0K on RN0. MMT90--P nd =.090.F.T90. RN0KJ--P 0 Modify: hange RN0 to R 0K 00 Resistor on FN_TH. R 0KRJ--P R0 0KRJ--P V_UX_K V_0 0 Modify: hange RN0 to R0 0K 00 Resistor on LUETOOTH_EN. 00 Modify: RN0 pull-low 0K Resistor to on LUETOOTH_EN. UVKX-P RN0 RNKJ--P RN0 RN00KJ--P RN0 R09 0KRJ--P 0 Modify: tuff R and Removed R Modify: dd R,R PH 00K to V_UX_K for MEI_TN#,MEI_TN#. dd R 00K to V_UX_K for PIE_WKE# from EVIE to K. K_ET# rename to MEI_TN# on K PIO. U_ET# MEI_TN# INTNT_ON# UET_ON# T_REOVERY# <ore esign> INTNT_ON# 0 Modify: dd 0 connect to MEI UTTON Instant_on#. 0 Modify: dd R,0 for UHRER ETET Function. UET_ON# 0 Modify: dd R,0 ase on ell Peter request, both / Media TN (Recovery utton) need support bootable capability. T_REOVERY# MEI UTTON ONTROL R 00KRJ--P R0 00KRJ--P MEI_TN# R 00KRJ--P PIE_WKE# R 00KRJ--P Q R 0RJ--P 0 Modify: TPT-P dd R 0ohm only for Q stuff, change 0 only for N stuff. MEI_TN# N 0 TPT-P 0 TPT-P 0.R00.E N =.000.Q K_ON#_R U_ET#.R00.E N =.000.Q K_ON#_R MEI_TN# V_UX_K.R00.E N =.000.Q K_ON#_R Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. K Nuvoton NPE9 ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet 0 of 00

28 I = Thermal R0 NT-00K--P 9 X0 Modify: hange U0,U0,U0 V power to V 0 from V_0. V 0 Layout notice : oth XN and XP routing 0 mil trace width and 0 mil spacing. N =.090.P.090.L0 Q0 PM90--P 0 U0VKX-P P00_XP 0 0P0VJN-P P00_XN.ystem ensor, Put on palm rest J Thermal sensor P00 P00 R0 KRF-P V 0 P00 R0 0KRF-P X0 Modify: Rename U0&U0 pin to THERM_Y_HN#_OTZ from THERM_Y_HN#.. egree U0VKX-P 0 P00 0 V 00P0VKX-P XP THERM_Y_HN#_OTZ XN OTZ P00E-P 00.H/W T hutdown.000. X0 Modify: J&J_V power source change to V 0 from V_0 to solve T shut down issue. J 00 Modify: If stuff P00E then must stuff R0,R0,0 but if stuff P000 should be unstuff. TR TL N J U0 Y_THRM PU_THRM FTP0 FTP0 FN_TH FN_TH_ FN_V 00 Modify: R0 change to 0ohm 00 from short pad and default un-stuff. R0 0R00-P X0 Fan controller P9 For linear FN 0 Modify: Removed 0 0.uF. R0 0RJ--P FON# FON# V_0 FN_V VIN VO FN_ VET *Layout* 0 mil 00 0 Modify: tuff R and Removed R0. FN_TH_ 0 Modify: hange FN connector part number to base on ME EMN and XF. 0 Modify: hange FN part number to 0.F9.00 from base on latest EMN and XF. *Layout* mil 09 UVKX-P 0 U0 99PU-P HH-0PT-P.R00.F FN_V 0 N =.R00.HH rd =.R00.0F N N N N nd =.09. rd = P0VKX-P V_0 0 0.F0.00 nd = 0.F.00 0 X0 Modify: dd nd 0.F.00 on FN from ME updated connector list. FN E-ON--P 0 0 UVKX-P U0VKX-P X0 Modify: dd R0 0hm between THERM_Y_HN#_OTZ and THERM_Y_HN#. R0 00 THERM_Y_HN#_OTZ 0RJ--P Q0 THERM_Y_HN# V_0 R09 00KRJ--P,, PURE_HW_HUTOWN# E0 EMI/E UVKX-P FN_V X0 U0VKX-P N00K--P.N0.J V_0 009 Modify: Removed R and connect V_0 to Q0. directly. 00 un-stuff U0 09TUF related circuit and R then stuff R0 V 0 X0 Modify: Reserved 09TUF for T solution KRF--P U0 sync with N. R0 R0 U0_ U0_ ET V THERM_Y_HN# N 0RF--P OUT# HYT U0VKX-P R 0RJ--P N =.N ancel V Thermal sensor P00 circuit 0009 X0: Reserve U0 for PURE_HW_HUTOWN# test X0: Reserve R0 to V_0 and R to N for HYT. 09TUF-P.0009.F R0 V 0 U0_ R 0RJ--P 00 0RJ--P Hysterisis: 0 for HYT= V for HYT=N <ore esign> X0 Modify: J&J_V power source change to V 0 from V_0 to solve T shut down issue. Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Thermal P00/Fan ontrollor P9 ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet of 0 00

29 I = UIO V_0 lose to codec 90 UVKX-P 90 U0VKX-P 90 U0VKX-P For EMI E90 U_MI_LK U_MI_IN0 E90 P0VJN-P P0VJN-P X0 Modify: change R90,R9 to ohm from 0ohm and stuff E90,E90 p from EM Neo updated. H_OE_OUT H_OE_ITLK H_IN0 H_OE_YN H_OE_RT# MP_MUTE# lose to codec U_VORE 90 0UVMX-P U_MI_LK_R U_MI_IN0_R H_OE_OUT H_OE_ITLK R90 H_OE_IN0 RJ--P H_OE_YN H_OE_RT# U_P_EEP 00 Modify: updated U90 part number from data base. MP_MUTE# U90 +PV U_PK_R+ U_PK_R- U_PK_L- U_PK_L+ +V U_VRE U_PK_R+ U_PK_R- U_PK_L- U_PK_L+ PUMP_PP PUMP_PN U_V_ U_HP_JK_R U_HP_JK_L U_EXT_MI_R U_EXT_MI_L +V +V 90 U0VKX-P LOE TO OE 9 U0VKX-P R90 0RF-P R90 0RF-P 9 9 U0VKX-P U0VKX-P V_0 Put 9 and 9 close to codec +PV 90 U0VKX-P U_HP_JK_R U_HP_JK_L MI_IN_R MI_IN_L U_P 909 U0VKX-P 90 0UVMX-P R90 0R00-P V_0 V_0 9 U_MI_IN0 9 U_MI_LK 00 00/0/0 hange to 9H (.9H.0) U_MI_IN0_R U_MI_LK_R 000 R90 R9 for change to parallel resistor U_ENE_ U_ENE_ U_P_EEP U_VREFFLT U_P U_VREFOUT_ U_VREFOUT_ 00 Modify: hange R9,R9,R9 change to 0ohm 00 from short pad. 0 Modify: Removed all of U_N and R9,R9,R9. U_VREFFLT U_V_ U_VRE lose to codec MP_MUTE# 9 U0VKX-P U_VREFOUT_ H_OE_ITLK U_P_EEP U_P_EEP Trace width> mils UMMY- U0VKX-P From 0KRJ-L-P R909 _PKR_R H_PKR K_EEP_R K_EEP R90 0KRJ--P From E 09 Modify: Move RN90 to closed UIO OE from speaker connector. U_VREFOUT_ THERML_P EP 0 PV 9 PORT_+R PORT_-R P PORT_-L PORT_+L PV V VRE/+_V V_LV MI_LK/PIO_ MI_0/PIO_ T_OUT ITLK T_IN V YN.9H.0 9 REET# 0 PEEP ENE_ ENE_ PORTF_L PORTF_R PORT_L PORT_R VREFFILT P VREFOUT_ VREFOUT_ P+ 0 P- 9 V- PORT_R PORT_L PORT_R PORT_L V 90 U0VKX-P R90 0R00-P R90 0R00-P R90 0KRJ--P RN90 RNJ--P 9HNXTX-P UVKX-P 9 0UVMX-P 9 0UVMX-P 9 UVKX-P 90 P0VN-P U0VKX-P RN90 RNKJ--P H_OE_OUT MI_IN_L PH_Z_OE_OUT R9 RJ--P 90 U0VKX-P U_ENE_ +V R9 R9 0KRF-L-P K9RF-P P0VJN-P-U R99 9KRF-L-P lose to Pin U_HP_J# EXT_MI_J# U_ENE_ +V R9 K9RF-P R9 0KRF-L-P lose to Pin MI_IN_R <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. udio odec 9H ize ocument Number Rev QUEEN 00 ate: Tuesday, January 0, 0 heet 9 of 0

30 (lanking) <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev QUEEN Reserved ate: Tuesday, January 0, 0 heet 0 of 0 00

31 (lanking) <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev QUEEN Reserved ate: Tuesday, January 0, 0 heet of 0 00

32 I = IO MHz clock input trace of characteristic impedance (Zo) must be 0 Ó%. V_R_0 V_R_0 0 LK_PH_M 0 U0VKX-P V_0 MX 0. V_R_0 PH PIO(M) confirm with W 0 UVKX-P 0 RREF 00P0VJN-P R0 KRF-P U_PN_R U_PP_R V 0 U0VKX-P RREF M P V_IN R_V V N LK_IN X_ P P P 0 P 9 X_# P P P P P 9 0 X_ P P P P U0 RT-R-P P0 PIO0 P9 P P P.0.00 X_ P P P P P0 P9 P P P P0 P9 P P P 0 U0VKX-P lose to chip 0 UVKX-P The maximum range of the PMO output current. x-picture ard: 0m. /MM ard: 0m. M/MPRO/uo-H: 0m P P P P P X_# POWER TRE.RT: pin (V_IN) trace fixed width is 0 mils (minimum)..rt: pin (R_V) trace fixed width is 0 mils (minimum)..rt: pin (V) trace fixed width is mils (minimum). Keep the trace routing lengths as short as possible..rt: pin (RREF) trace fixed width is mils (minimum)..rt: pin (RREF) trace must far away MHz clock trace..e-coupling and ulk capacitor should place near to RT chip and ombo ocket..it is recommended that use of ferrites bead on power trace..via size: Pad>= mils, Finished hole>= mils. P P P P P X_# U_PP U_PN The pin / pin (M/P) of RT chip trace layout with differential characteristic impedance (Zdiff) is 90 [ Ó 0% R 0R00-P--P 00 9 R0 U_PP_R U_PN_R 09 X0 Modify: stuff TR0 and un-stuff R,R0 at X0 stage from EM Neo suggestion. 0R00-P--P <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ard Reader-RT ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet of 0 00

33 E (lanking) <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev QUEEN Reserved ate: Tuesday, January 0, 0 heet of 0 E 00

34 (lanking) <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev QUEEN Reserved ate: Tuesday, January 0, 0 heet of 0 00

35 (lanking) <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev QUEEN Reserved ate: Tuesday, January 0, 0 heet of 0 00

36 I = Reset.uspend RO Run Power V_UX_ 00 stuff Q0 9, 0_PWR_OO 0 Modify: Removed R09,R0,R, and tuff R. 00, IMVP_PWR R Y_PWROK Q0 0R00-P--P P_NTRL 0U0VKX-P V_.N0.J N00K--P nd =.N0.0 R0 00KRJ--P 0 --P.000.K N =.000.F R0 V_RUN_ENLE 0KRJ--P V_ Power equence O MX 9 Rds(on) =.mohm nd = Y_PWROK 9 0 Modify: Utilize 0 iode instead of U0 N TE for Y_PWROK sequnece control. O-P U0 V_0 V_0 +V_RUN omsumption Peak current. 0 0U0VZY-P, H_PUPWR V_V_EN 0V_VTT R0 00KRJ-L-P R0 H_PWR_R KRJ--P 0 Modify: hange R0 to K from K Modify: efault stuff R PH Resistor to fix nnie demo board abnormal issue from nnie team updated. 0 U0VKX-P N =.000.F.000.K --P 0 R RJ--P R0 KRJ--P E Q0 HTPT-P H_THERMTRIP#, PURE_HW_HUTOWN#,, _ENLE P_NTRL R0 P_NTRL 00KRJ--P 9,,,, Q0 N00KW-P.N0.F nd =.M0.0F PM_LP_# RUN_ENLE V_ R0.V_RUN_ENLE 0KRJ--P 0 0U0VKX-P Rds(on) =.mohm O MX. nd = O-P U0 V_0 V_0 +.V_RUN omsumption Peak current. 0 0UVKX-P V_0 E0 U0VKX-P 09 Modify: Reserved E0 0.uF near 0 for EM NEO suggestion. 0 0U0VKX-P 0 Modify: Removed R,R 0ohm 00 Resistor, they are unnecessary for this power rail. Removed R,R9 0ohm 00 Resistor for V_R_0..V_RUN for V omsumption Peak current.9 +.V_RUN_PU omsumption Peak current +.V_RUN for Mini-ard omsumption Peak current V_ R0.V_RUN_ENLE 0KRJ--P 0 0U0VKX-P TP0-H-P MX Rds(on) =.~.m OHM U0 TP0-H-P.00.0 nd = rd =.00.0 V_0 0 Modify: hange U0 part number to.00.0 from dd nd and rd. V_0 MX urrent? m esign urrent? m Total= UVKX-P <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Power Plane Enable ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet of 0 00

37 lose to IMM Power Reduction ircuit M_RMPWROK 0V_0 V_0 lose to PU Power Reduction ircuit Processor VREF_Q Implementation R0 0RJ--P Q0 Q0_ R0 RJ--P 09 Modify Q0_ R0 0RJ-L-P 09 Modify +V_M_VREF_NT 9 M_VREF_Q_IMM0 +V_M_VREF R0 0R00-P 00 Modify: Removed Q0,R and connect RUN_ENLE to Q0. directly same as EV board. N00K--P.N0.J RUN_ENLE N =.N0.0 R0 00KRJ--P P_NTRL Q0 N00K--P.N0.J N =.N0.0 P_NTRL Q0 N00K--P.N0.J N =.N0.0 Power Reduction X0 009 lose to PU Power Reduction ircuit M_RMPWROK V_ 00 P_NTRL N00K--P Q0.N0.J N =.N0.0 0V_EN 00 9,,,, PM_LP_# R RJ--P.0VTT_PWR, 090 X0 Modify: R0 tuff Q0,R0; un-stuff R. 0R00-P--P U0 pin change to.0vtt_pwr from RUNPWROK. 0V_EN M_RMRT# R09 0RJ--P Q0 N00K--P.N0.J N =.N0.0 R0 KRJ--P Power Reduction ircuit M_RMRT# M_RMRT#_ R KRJ--P 0 00P0VJN-P R_RMRT#, 0 U0VKX-P RMRT_NTRL_PH 0 0 RMRT_NTRL_PH 009 Modify: hange U0 pin, to V_0 from V_. lose to PU Power Reduction ircuit M_RMPWROK 0UVKX--P,9 PM_RM_PWR V_0 R 00RF-L-P 090 X0 0V_EN PUH PULL U0 TZ0FU--P V_0.Z0.EH nd =.00.L0 rd =.Z0.H V_0 R0 00RF-L-P VPWROO_R EKLT V.0: PH to K,UP to 00R R9 90RF-P R0 0RF-P VPWROO 0 X0 Modify: hange U0 st to.z0.eh;nd to.00.l0;rd to.z0.h from ourcer Eason updated. NTI,9 PM_RM_PWR 0 R VPWROO_R 0RJ--P M_RMPWROK must have a maximum of ns rise or fall time over VQ * 0. Ó 00mV and the edge must be monotonic 009 Modify: U0 change to O type.009.h. 0 Modify: hange U0 to push pull type.00.l0. R0 change to 90ohm 00. R9 change to 0ohm 00. default un-stuff R0. PTER Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet of 0 00

38 I = PWR.upport (lanking) <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IN ize ocument Number Rev QUEEN 00 ate: Tuesday, January 0, 0 heet of 0

39 T+ 0 TT_ENE,0 T_L,0 T_ T_IN# U0VKX-P P-LOE-PWR--P 0 Modify: Merge R90~R90 to PRN90 ohm. PN90 RNJ--P 00 E90 E P0VKX-P FTP90 K PT_MLK PT_MT PT_PRE# T_LERT att onnecter 00 Modify: Removed 90 E iode on T_IN#. TOUT FTP90 FTP90 FTP90 FTP90 PT_PRE# PT_MT PT_MLK T+ X0 Modify: stuff E90 0.uF from EM Neo suggestion. For actual location, need to be swap all pin lose to att onnector T_L T_ T_IN# 90 V99--P-U P90 MT-P TT 0 9 0P0VJN-P LP-ON9--P-U nd = rd = V99--P-U T nd = K rd =.V99. 0P0VJN-P U0VKX-P E90 90 V99--P-U T nd = K rd =.V T nd = K rd =.V99. V_UX_K 090 X0 Modify: hange 90~90 main source to t for.v99. shortage issue. <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev QUEEN TT ONN ate: Tuesday, January 0, 0 heet 9 of 0 00

40 I = harger PR009 PR0 9K9RF-L-P + _I KRF--P + _IN_ PWR_H_OK + + PWR_H_IN P00 PWR_H_IN 0 V_UX_K U0VKX-P IN 00 Modify: hange PR0 from.k to 9.9K 00 Modify: VM 00 base on power team suggest. hange PR0 change to 0ohm 00 from short pad. P00 U0VKX-P PR0 PWR_H_OK 0R00-P OK _OK H_N,9 T_L PWR_H_L P00 P-LOE-PWR--P 0 L H_N This Resistor must be % tolerance. EMI/E P00 0U0VKX-P PR00 0KRJ-L-P PR0 _IN_ PWR_H_FO 0,9 T_ 00 Modify: hange PR00 to 0K from 0ohm base on power team rian updated. P0 PR0 00P0VKX-P KRF--P PR_0 0U0VKX-P PWR_H_OK Id=- Qg=-n Rdson=0~mohm + T+ _I_HW 0 Modify: Reserved E00,E00 on _IN_&PWR_H_OK for EM NEO suggestion. 09 Modify: Reserved E00 0.uF near PR00 for EM NEO suggestion. Reserved E00 0.uF near P0 for EM NEO suggestion. E00 P0VN-P KRF--P PR00 0KRJ--P P0 0P0VJN-P PU00 O0-P.00.F nd =.0.H PR0 KRJ--P PQ00 U0VKX-P E00 PR00 0KRF--P N00KW-P.N0.F nd =.M0.0F PR0 0RF-P P00 U0VKX-P E00 PR00 00KRJ--P P0 P0 0P0VJN-P P0 P0 P0VJN-P P0 0U0VKX-P U0VKX-P E00 P0VN-P PR0 00KRF-L-P 00 Modify: dd _I_HW related circuit from TOM suggestion. PQ00_ 00 PQ00 N00K--P.N0.J N =.N0.0 PWR_H_ P-LOE-PWR--P H_N PWR_H_VIM PWR_H_FO 09 X0 Modify: hange PR0 to 0R00 short pad from 0ohm. PWR_H_REF 00KRF-L-PPWR_H_REF PQ00_ PQ00 I_HW PR0 0R00-P--P H_N IREF H_N PR0 KRF-P 00 IREF H_N P +_TO_Y PR0 PR00 0KRF-L-P 09 X0 Modify: 0R00-P 00 hange PR00,PR00 to 0R00 short pad from 0ohm. PR0 PQ00_ 0R00-P--P P00 H_N U0VKX-P H_N PWR_H_EI FO PWR_H_EO EI PWR_H_REF EO PWR_H_E VREF E PR0 0R00-P N P09 UVKX-P 00 P00 U0VKX-P PQ00 N00K--P.N0.J N =.N0.0 9 IN N# VIM 00 PR0 00 IREF PU00 QRHR-P 00 N 9 00 PR0 KRF-P PR_0 09 X0 Modify: Reserved PQ00,PR0,PR0 for _I_HW function. PR0 _OK 0KRF--P P-LOE-PWR--P N IOUT OOT VP UTE PHE LTE 0 PN 9 OP ON N# P00 VF PR09 0R00-P PR00 P00 PWR_H_P U0VKX-P PWR_H_N PWR_H_IOUT PWR_H_OOT PR0 PWR_H_T K PWR_H_VP 0R00-P 0W--P PWR_H_UTE P0 PR0 U0VKX-P PWR_H_PHE 0R00-P PWR_H_LTE P0 0P0VJN-P PWR_H_OP PWR_H_ON PWR_H_VF PR0 0R00-P H_N _OK 0RF--P PR00 0RJ--P P0 UVKX-P PR_0,, H_PROHOT# _IN# 09 Modify: Reserved E00 0.uF near PR00 for EM NEO suggestion. 09 Modify: Reserved E00 0.uF near P00 TOUT for EM NEO suggestion. H_N H_N 0 Modify: Removed PR0 PH. PR00 0R00-P 00 P00 U0VKX-P PR00 KRJ-P P00 P-LOE-PWR--P P00 P00 U0VKX-P _IN# to K PR0 RJ--P PR0 0R00-P--P H_N P0 TT_ENE 9 00 Modify: hange PQ00 to single N00. P0 U0VKX-P U0VKX-P E00 PU00 Id= Qg=.n Rdson=~0mohm H_N P0 U0VKX-P.R0.F nd =.R0.F U0VKX-P U0VKX-P E00 P-LOE-PWR--P P00 P00 UVKX-P.00.0 nd =.00. P00 Q00 N00K--P.N0.J P-LOE-PWR--P P00 P0 00P0VKX-P PWR_H_LX H_N PWR_TOUT_H _OK P-LOE-PWR--P P00 PU00 IN-T-E-P P-LOE-PWR--P PWR_TOUT_H.00.0 nd =.00. PR0 0R00-P PU00 IN-T-E-P PL00 T+_R PR09 IN-UH--P-U 0RF--P.00.0 Id= Qg=.n Rdson=~0mohm PWR_H_OP_ <ore esign> + nd =.R0.0U.R0.0X Id=. R=9~mohm ize=.x.x 00 Modify: hange PR0 change to 0ohm 00 from short pad. 0 Modify: hange PU00 to.00.0 from power team rian updated. N =.N0.0 P00 0UVKX-P PR00 0R00-P P00 0UVKX-P P009 U0VKX-P 09 Modify P009_ H_N ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet 0 of 0 T+ T+ T+ harger urrent=.~. 00 Modify: change PL00 to.r0.0x..r0.0x P00 P-LOE-PWR--P PR00 0KRJ--P Id=- Qg=-n Rdson=0~mohm E00 00P0VKX-P P009 P-LOE-PWR--P PU00 PR0 0R00-P O0-P.00.F nd =.0.H P0 0UVKX-P P0 U0VKX-P E00 UVKX-P P0 0UVKX-P P0 0UVKX-P P0 0UVKX-P 00 Modify: dd P0 to.0.l. Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. HRER Q P0 0UVKX-P P09 U0VKX-P 00

41 E I = PWR.Plane.Regulator_vpv P0 T--F-P PWR_V_ENTRIP PWR_V_ENTRIP P0_ P0_ RO team 09 Modify 09 Modify P0 P0VJN--P P0 P0 P0 P0VJN--P T-F-P T-F-P.000.Y nd =.0R0.0 TOUT PWR_V_TOUT.00.0 P P-LOE-PWR 00 Modify: TOUT P0 P-LOE-PWR PWR_V_TOUT Id= hange PU0 to... 0 Modify: PWR_V_TOUT Qg=.n 0 Modify: hange PU0 to.000. hange PU0 to TP from RTMQW. P0 P from power team rian updated. 0 Modify: Rdson=~0mohm 00 Modify: dd P,P from P0 P-LOE-PWR P0 P P hange PR0 to.ohm from 0ohm from power team rian updated. power team rian updated. 00 hange MO follow rian. 09 X0 Modify: 090 PU0 and PU 0 horizontally mirror. dd nd source.00. on PU0, P P P P0 P-LOE-PWR PU0 base on rian updated nd soruce excel file. PU0 PU0 IN-T-E-P IN-T-E-P V_PWR V_ PU0 0 Modify: esign urrent = hange PR0 to 0ohm 00 from.00.0 nd =.00. esign urrent = P0 P-LOE-PWR 0909 X0 Modify:.ohm from power team rian updated..<op< nd =.00. hange PL0,PL0 to.r0.0 UVKX-P.<OP<. from.r0.0q base on rian updated. P PR0 P dd nd source.r.0j on PL0, PWR_V_OOT PWR_V_OOT 9 PWR_V_OOT PR0 PWR_V_VT_ 09 Modify: P09 P-LOE-PWR V_ V_PWR PL0 base on updated nd excel file. VT VT 0R00-P V_PWR UVKX-P PWR_V_UTE 0 PWR_V_UTE V_PWR Reserved E 0.uF for P0 P-LOE-PWR..0L.R0.0 R--U-P RVH RVH nd =.9.0 PL0 PL0 EM NEO suggestion. PWR_V_PHE 0 PWR_V_PHE P P-LOE-PWR IN-UH--P-U LL LL IN-UH--P-U 00 nd =.R.0J PWR_V_LTE 9 PWR_V_LTE RVL RVL.R0.0 P0 P-LOE-PWR..0L nd =.R.0J PT0 P PR0 nd =.9.0 P P-LOE-PWR RF--P PU0 PWR_V_VOUT PWR_V_VOUT PR0 P P0 E0 VO VO IN-T-E-P RF--P P P-LOE-PWR PWR_V_F PWR_V_F PT0.0.0 VF VF P P-LOE-PWR V_ nd =.00. PWR_VV_EN0 00 P P-LOE-PWR PR09 0KRF-P EN0 POO 00 PWR_V_ENTRIP PWR_V_ENTRIP PR0 PU0 00 P9 P-LOE-PWR PWR_VV_VREF TRIP TRIP 00KRJ--P P P-LOE-PWR P VREF N.0.0 0P0VKX-P PWR_VV_TONEL Mag..0uH.*.9* Id= 0P0VKX-P P P-LOE-PWR TONEL N IN-T-E-P Qg=.n V_V_POK R=~0mohm PWR_VV_KIPEL PWR_VV_EN P P0 P-LOE-PWR 0P0V-P Idc=, Isat= Rdson=.~.mohm KIPEL EN.0.0 P P-LOE-PWR TPRER-P nd =.00. PWR_V_NU P P-LOE-PWR PR PR V_UX_ 0R00-P P P-LOE-PWR PR 0RJ--P V_UX_ P KRF-P V_ PWR_V_F_R V_V_EN P P-LOE-PWR P P-LOE-PWR--P PR P0VJN--P 0RJ--P PR KRF-P PWR_V_F_R TOUT U0VKX-P P9 E0UVM--P lose to VF Pin (pin) 09 X0 Modify: Un-stuff PU0,P0,PR, PR,PR0 at X0 stage. PR 0KRF--P P-LOE-PWR--P 0UVKX-P TOUT U0VKX-P 0UVKX-P V_UX_ PWR_VV_VREF PWR_VV_VREF V_UX_ U0VKX-P P PR 0RJ--P PR 0R00-P PR0 0RJ--P PR 0R00-P PR 0RJ--P..0 PWR_VV_VRE VRE P UVKX-P VIN VRE 0UVKX-P P 0UVKX-P PR0 KRF-P 0U0VKX-P P 00 Modify: P efault un-stuff. UVMX-P PR0 KRF-P 00 Modify: hange PR0 to K from 00K. PWR_V_LTE PR0 0R00-P V_ PWR_V_NU V_PWR P0 P-LOE-PWR--P 0UVKX-P P P0VJN--P 0UVKX-P PWR_V_LTE_ K P0 ZT-P.R0.F nd =.R0.EF P0 KP0VKX-P U0VKX-P P0 UVKX-P.000.Y nd =.0R0.0 P0_ 09 Modify P0 UVKX--P P-LOE-PWR--P U0VKX-P PR9 KRF-P lose to VF Pin (pin) I/P cap: 0U V K0 XR/.0.L Inductor:.UH FVE00-RM=P TOKO mohm Isat =.rms.r.0 O/P cap: 0U.V PLV0JM() mohm.rms NE_TOKIN/..00L H/: F O-/ mohm/0mohm@.vgs/.0.0 L/: F90 O-/ mohm/mohm@.vgs/.090.e E0UVM--P P0 UVKX-P P0 UVKX-P V_ U0VKX-P 00 P09 UVKX-P E0 U0VKX-P TOUT E0 U0VKX-P E0 U0VKX-P PWR_V_TOUT P0 P-LOE-PWR P0 P-LOE-PWR P P-LOE-PWR 09 Modify: Reserved E0~E0 0.uF near PT0,P9 for EM NEO suggestion. PR 0KRF-P PU0_ PR 0KRF-P PU0 N00KW-P Vz=.V P0 MMPZPT-P PWR_VV_EN0.R0.EF nd =.PZ.VF PU0_ 09 Modify.N0.F 00KRF-L-P PR0 TONEL N VREF VRE or VRE H 00kHz 00kHz 00kHz H 0kHz khz 00kHz KIPEL Operating Mode VRE or VRE OO uto kip VREF(V) uto kip N PWM only <Variant Name> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. V/V(TPRER) ize ocument Number Rev QUEEN Tuesday, January 0, 0 ate: heet of 0 E 00

42 I = PU.Regulator Only for ual-core, Qual-core stuff KR (.0.L) 09 Modify P PR0 P_ PR P P_ 09 Modify RF--P 0P0VKX-P 9_NT 09 Modify 09 Modify 9_VW VUM- 09 Modify 9_OMP 9_F 00 Modify: Updated IMON and IMON circuit from power team rian. V_0 00 Modify: PU0 Removed PR0 N to 9_N. H_PU_VIT PR 0R00-P PR0 00 Modify: K9RF--P Removed PR. 09 Modify VW VR_VI_LERT# 9_POO IMON 9_ POO 9_LK LERT# H_PU_VILK PR0 V_PWR IMVP_VR_ON LK PR0 0R00-P 0R00-P VR_ON V_0 PR K9RF--P POO 9 H_PROHOT#_ IMON 9_IMON, IMVP_PWR 0 VR_HOT# PR0 9_VW NT Modify VW 0V_VTT PR0 &Q KRF-P RF--P Only for ual-core, Qual-core stuff KR (..LL) ENE IEN P0 PR UMMY-R 9_IMON _X_ENE UMMY-R P0 0P0VKX-P PR0 KRF-P P0 0U0VKX-P,,0 H_PROHOT# 0P0VKX-P UMMY- KRF-P 09 Modify P0 PR PR_ KRF--P 0P0V-P 09 X0 Modify: dd PR,P0 from vender suggestion. P0 000P0VJN-P-U KRF-P P0_ PR_ P09 VENE ENE 0V_VTT 9P0VJN-P P U0VKX-P PR 0R00-P 090 X0 Modify: hange PR to.k from.k from rian updated. 090 X0 Modify: hange PR to.0k from.k from rian updated. lose to PU PR9 PR 00 Modify: NT-0K-9-P tuff PR NT Resistor. 00 Modify: KRF-P hange all of 9_N to N for vender suggest nd = Place near high side MOFET of Phase PR 09 Modify KRF-P PR0 PR0 K0RF-P 9P0VJN-P P0 0UVKX-P PR0 K0RF-P P0 P0 PR 0RF--P UMMY- PR09 PR K0RF--P PR RF--P 09 Modify 9_OMP 9_F PR P P_ 09 Modify 99RF--P 0P0V--P 00 PR 9RF-L-P P0 000P0VJN-P-U P0 IL9HRTZ-T-P P0VJN-P P N 9 OMP F U0VKX-P P U0VKX-P P U0VKX-P IEN IEN IEN 9_PRO 9_IUMN PR NT 09 Modify PR_ 09 Modify OOT UTE PHE LTE 09 Modify 9_VIN 09 Modify 9_V PR_ LTE PHE UTE OOT 09 Modify 9_PRO IP IN UMMY- UMMY-R 09 Modify 0 Modify: hange PR to K from 9ohm from power team rian updated. OOT UTE PHE LTE Modify: hange P to uf from uf from power team rian updated. hange P to 0.0uF from 0.0uF from power team rian updated. Only for ual-core, 00 0 PR Qual-core stuff KR(.0.L) 0 Modify: Only for ual-core, KRF-P hange PR to.k from.k from power team rian updated. Qual-core stuff KR &Q (..L) P9 0P0VKX-P P 000P0VJN-P-U VEN RTN IP IN NT PRO OOT 0 KRF--P P U0VKX-P PR 00 RF-P &Q P0 P P 0P0VKX-P 0P0VKX-P P 0U0VKX-P PR9 KRF--P U 9 PH L OMP F IEN/F IEN IEN VEN RTN IUMN IUMP V VIN PRO 9 0 P 0P0VKX-P P0 000P0VJN-P-U OOT U PH P L VP PWM 0 L 9 P PH U OOT P UVKX--P TP0 TP-P PR P0 UVKX-P P 0UVKX-P PR KRF-P PR 0R00-P PR OOT UTE PHE LTE V_ 09 Modify PR_ V_X_ENE 9 _X_ENE 9 09 Modify: tuff PR NT resistor. 9_PWM LTE 09 Modify PHE UTE OOT 09 X0 Modify: dd PR,P from vender suggestion. PR0_ NT place near high side MOFET of Phase 9_VP PWR_VORE_TOUT 09 RF-P hange PU0 V power source to V_ from V_0 to avoid abnormal MVP_PWR waveform. PR KRF-L-P PR KRF--P PR NT-0K--P VUM nd = VUM- PR NT-0K-9-P nd = P U0VKX-P PR 0R00-P PR0 KRF-P 09 Modify P0 UMMY- PWM <Variant Name> 09 Modify IEN IEN IEN Place near choke of Phase PR9 KRF-P PR 0RJ--P P U0VKX-P V_0 IEN IEN IEN ate: Tuesday, January 0, 0 heet of 0 09 Modify: Reserved E0~E0 0.uF near PR(TOP) for EM NEO suggestion. 0 Modify: Removed E0~E0. PR 0R00-P P9 U0VKX-P V_FXORE 09 Modify: Reserved E0~E0 0.uF near 0(TOP),0,09,0, TP_LOK_LE for EM NEO suggestion. Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IL9_PU_ORE(/) ize ocument Number Rev QUEEN E09 U0VKX-P 00

43 PWM 00 Modify PWR_FM FM V_0 TOUT_IMVP PWR_VORE_TOUT P9 P-LOE-PWR P0 P-LOE-PWR P P-LOE-PWR P P-LOE-PWR P P-LOE-PWR P OOT 00 Modify UTE PHE LTE P-LOE-PWR UTE LTE PWR_VORE_OOT PR0 PWR_VORE_OOT_ PU0 R--U-P.00.0 IRP Id=0, Qg=.n, Rdson=.9~0 mohm PU0 IRP-T-E-P PR0 PWR_VORE_OOT_ R--U-P PHE PWR_VORE_PH PWR_VORE_H TOUT_IMVP PWR_VORE_TOUT nd = P P-LOE-PWR IR0P P Id=0,Qg=.n, Rdson=.~.mohm P-LOE-PWR P P-LOE-PWR PIN09 P-LOE-PWR P P-LOE-PWR P P-LOE-PWR P0 PR0 PU0 0R00-P PWM U0VKX-P V IL0RZ-TP-U N N 9 P0 UVKX-P OOT PHE UTE LTE P UVKX-P.00.0 IRP Id=0, Qg=.n, Rdson=.9~0 mohm PWR_VORE_L nd = IR0P Id=0,Qg=.n, Rdson=.~.mohm 09 Modify: hange PU0 part number to.00.0 from.0.0 base on power team rian suggestion. 0 Modify: rian updatede PU0 change to Modify: hange PU0 part number to.00.0 from.0.0 base on power team rian suggestion. 0 Modify: rian updatede PU0 change to PU0 PU0 Q Q nd = IR0P-T-E-P IR0P-T-E-P PU nd =.00. PU0 P0 UVKX-P IR0P-T-E-P IR0P-T-E-P PWR_VORE_VUM+_ nd = P0 UVKX-P IRP-T-E-P.00.0 nd =.00. Q P0 UVKX-P P0 UVKX-P PWR_VORE_VUM+_ PWR_VORE_VUM-_ PWR_VORE_TOUT PL0 L-UH--P.R0.0 nd =.R P0 P-LOE-PWR--P PWR_VORE_VUM-_ PL0 L-UH--P.R0.0 nd =.R P0 P-LOE-PWR--P P09 UVKX-P P0 P-LOE-PWR--P UVKX-P PR 0KRF--P PR KRF--P P-LOE-PWR--P PWR_VORE_TOUT P0 PR09 RF-P PR0 RF-P PR RF-P IEN VUM+ V_ORE 09 Modify: hange PU0 part number to.00.0 from.0.0 base on power team rian suggestion. 0 Modify: rian updatede PU0 change to PU0 PR OOT PWR_VORE_OOT_ P0 UVKX-P 0.V.L 0uF,.V,.R0.0 ER=9m [, Iripple=.0 0.uH, Idc=0, 00 Modify Isat= V_ORE R=. +/-% mohm 00 P0 nd =..L PR0 RF-P PR0 PR0 RF-P IEN 0KRF--P PR0 KRF--P P0 UVKX-P P UVKX-P VUM+ 00 Modify PT0 T0UVM--P PT0 T0UVM--P 9.9.0L nd =..L IEN IEN VUM L PR0 RF-P PT0 T0UVM--P IEN IEN VUM- TOUT U0_VIN+ Vcc_core Iomax= OP>9. UTE PHE LTE 00 Modify 00 Modify 00 PT09 T0UVM--P 9.9.0L nd =..L 00 no co-lay PR0 U0 HP00900INR-P U0_VIN- VIN+ VIN- N V VENTUR 0 L.00.0 PU09 IRP Q Id=0, Qg=.n, Rdson=.9~0 mohm nd = L nd =..L 00R0F-P PR 0RF-L-P VENTUR P9 VENTUR UVKX-P TOUT_IMVP R--U-P IN_0 IN_ Would be instead of IN9 by HP00900 FOR NVII VENTUR V_V_0 M_IN9,9 M_IN9, IR0P Id=0,Qg=.n, Rdson=.~.mohm 00 Modify: PR0 change to I IZE footprint for PU VENTUR. 00 Modify: R change to PR0 m ohm sense Resistor from m ohm. 00 Modify: Removed R sense Resistor base on VENTUR PE. R KRJ--P P UVKX-P PR 0RF-L-P VENTUR KRJ--P R VENTUR 00 Modify: dd PR,PR,P9. U0VKX-P R KRJ--P VENTUR 00 Modify: hange U0 power source to V_V_0 from V_0. 0 Modify: hange VENTUR solution part number to from R KRJ--P 0 0 VENTUR IRP-T-E-P IR0P-T-E-P P UVKX-P PWR_VORE_VUM+_ NTI PWR_VORE_TOUT Q.00.0 nd =.00. PL0 L-UH--P.R0.0 nd =.R PU0 IR0P-T-E-P nd = P UVKX-P P P P-LOE-PWR--P P UVKX-P P-LOE-PWR--P PWR_VORE_VUM-_ P UVKX-P PR 0KRF--P PR9 KRF--P 09 Modify: Reserved PT0 uf. 0 Modify: Removed PT0. PR RF-P PR RF-P PR RF-P P 00 Modify IEN VUM+ V_ORE TOUT_IMVP PWR_VORE_TOUT P0 TOUT 00 Modify nd =..L IEN IEN VUM- P-LOE-PWR P0 P-LOE-PWR P09 P-LOE-PWR P0 P-LOE-PWR Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IL9_PU_ORE ( of ) ize ocument Number Rev ustom QUEEN 00 ate: Tuesday, January 0, 0 heet of 0 UVKX-P PT L nd =..L P-LOE-PWR P0 P-LOE-PWR P0 T0UVM--P PT0 T0UVM--P 9.9.0L PT0 EUVM--P 9..FL nd = 9..0L

44 00 Modify TOUT_IMVP PWR_FXORE_TOUT P0 P-LOE-PWR 09 Modify: hange PU0 part number to.00.0 from.0.0 base on power team rian suggestion. 00 Modify: hange PU0 part number to.00.0 from.00.0 base on power team rian suggestionl. P0 P-LOE-PWR P0 P-LOE-PWR P0 P-LOE-PWR OOT UTE PHE LTE PR0 RJ-L-P.00.0 IRP-T-E-P Id=0, Qg=.n, Rdson=.9 mohm PWR_FXORE_OOT_ P0 UVKX-P PU nd = Modify: Removed PU0 MOFET. PU0 IRP-T-E-P.00.0 nd =.00. PU0 IR0P-T-E-P IR0P-T-E-P nd = Z0N0M Id=,Qg=~n, Rdson=.~.mohm PWR_FXORE_TOUT PWR_FXORE_IP_R 0 Modify: Removed P0 PL0 L-UH--P.R0.0 nd =.R0.0 P0 P-LOE-PWR--P P-LOE-PWR--P PWR_FXORE_IN_R PR0 0KRF--P P0 UVKX-P.R0.0 0.uH, Idc=0, Isat= R=. +/-% mohm P0 009 P0 P0 UVKX-P 09 Modify PR0 RF-P PR0 NT-0K--P KRF--P nd = UVKX-P PR0_ P09 U0VKX-P 09 Modify PR0_ PR0 P0 UVKX-P PR0 KRF-L-P P0 UVKX-P 9.9.0L nd =..L P0 0UVKX-P PT0 T0UVM--P 090 X0 Modify: hange P0 to 0.0u from 0.0uF from rian updated. P0 P-LOE-PWR P0 P-LOE-PWR P09 P-LOE-PWR V_FXORE 00 PT0 T0UVM--P 9.9.0L nd =..L PT0 T0UVM--P 0.V.L 0uF,.V, ER=9m [, Iripple= L nd =..L 09 Modify P0 PR0 P0_ 0UVKX-P PR0 9RF-P IP IN RF--P0 Modify: hange PR0 to ohm from 9ohm from P power team rian updated. 0UVKX-P V_FXORE Iomax= OP>0 EMI/E 0 Modify: dd E0~E0 for EM NEO suggestion. V_ORE V_ORE PWR_VORE_TOUT PWR_VORE_TOUT PWR_VORE_TOUT V_FXORE PWR_FXORE_TOUT U0VKX-P E0 U0VKX-P E0 U0VKX-P E0 U0VKX-P E0 U0VKX-P E0 U0VKX-P E0 U0VKX-P E09 U0VKX-P E0 NTI Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IL9_PU_ORE(/) ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet of 0 00

45 TOUT PWR_0V_TOUT P0 P-LOE-PWR P0 P-LOE-PWR P0 P-LOE-PWR P0 P-LOE-PWR TP for 0V X0 Modify: V_0 hange PR0 to K from.k for.0v OP set to 0 from rian. 0KRJ--P,.0VTT_PWR PU0 9,,,9 RUNPWROK PR0 PR0 PWR_0V_TRIP POO PWR_0V_EN TRIP PWR_0V_VF EN 0R00-P--P KRF-P PWR_0V_M VF 00 M KP0VKX-P P0 00 PR PR0 0KRF-P N VT 0 RVH 9 W VIN RVL TPR-P-U PR0 PWR_0V_VT PWR_0V_VT_R PWR_0V_RVH PWR_0V_W R--U-P PWR_0V_RVL.00.0 ZN0M Id=0, Qg=9.n, Rdson=.9 mohm 0 Modify: hange PR0 to.ohm from 0ohm from power team rian updated. P0 PU0 IRP-T-E-P U0VKX-P V_ 009 Id=. Qg=0.~n, Rdson=.~.mohm 09 Modify: hange PU0 part number to.00.0 from.0.0 base on power team rian suggestion. PWR_0V_TOUT P0 UVKX-P IR0P-T-E-P VTT_ENE_L _ENE_L 0909 X0 Modify: hange PL0 to.r0.0 from IN-UH--P base on rian updated. PU nd = P0 UVKX-P.00.0 nd =.00.0 Mag..0uH 0*.* R=.~mohm Idc=, Isat= PR RF--P PWR_0V_NU P0 UVKX-P P0 UVKX-P P09 0P0V-P 0 Modify: rian suggest change PU0 to hange PR0 to 9.K from 0K from power team rian updated. PR09 0R00-P P0 000P0VJN-P-U PR0 0R00-P PL0 P0 UVKX-P OIL-UH--P.R0.0 nd =.R.0I VTT_ENE_L PWR_0V_VF 09 _ENE_L VIO_ENE IO_ENE 0 Modify: PR0,PR0 change to 00ohm from 0ohm. stuff PR09,PR0 0ohm from rian updated. X0 Modify: stuff E0 0.uF from EM Neo suggestion. E0 U0VKX-P PR0 00RF-L-P-U PR0 9KRF--P PR0 0KRF-L-P esign urrent = 9.9.<OP<. P U0VKX-P 00 P0 U0VKX-P 0V_PWR E90UVM-P PT0 090 X0 Modify: hange PR0 to 0K from 0.K from rian updated. PR0 00RF-L-P-U 0V_PWR Vout=0.0V*(R+R)/R 9.9V.0L nd =.99.0L PT09 UVKX-P 0 Modify: Joseph hange PT0 to 0uF from 90uF base on layout placement status. 0 Modify: rian dd P uf. hange PT0 to 0u 9.9.L X0 Modify: hange PT0 to 9.9V.0L from 9.9.L0 from power team rian updated. 09 X0 Modify: dd nd source.99.0l on PT0 base on rian updated nd soruce excel file. 0V_VTT P0 P-LOE-PWR P0 P-LOE-PWR P0 P-LOE-PWR P0 P-LOE-PWR P09 P-LOE-PWR P0 P-LOE-PWR P P-LOE-PWR P P-LOE-PWR P P-LOE-PWR P P-LOE-PWR P P-LOE-PWR P P-LOE-PWR E0 U0VKX-P 09 Modify: Reserved E0,E0 0.uF near P(TOP) for EM NEO suggestion. NTI Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. TP_+.0V_VTT ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet of 0 00

46 I = PWR.Plane.Regulator_pv0pv V_PWR V_ 9,,,9 RUNPWROK 0 Modify: Removed PR,PR and connect 0V_EN to VTTEN directly. P0 UVKX-P P0 0UVKX-P K0RF-P PR0_ 09 hange PR0 to.0k from 0ohm for fine tune.v output Voltage. V_0 0V_EN PWR_V_EN PWR_V_VREF VREF PR0 0 Modify: 0KRF--P hange PR0 to K from.k from power team rian updated. PR0 KRF-P PR0 tate VR VTTREF VTT 0 / MOE PR0 PR00 00k ohm 00k ohm k ohm k ohm 00KRF-L-P PR0 0KRF-P 090 X0 Modify: hange PR0 to 0K from K from rian updated. 00 Modify: hange P0 to 0.u 00 from 00 from rian. Hi Lo Lo PR0 0KRJ-L-P Hi Hi Lo P0 UVKX-P N 00kHz 00kHz 00kHz 00kHz On On Frequency PU0 0 POO PWR_V_MOE9 MOE VTTEN EN/PV PWR_V_REFIN REFIN PWR_V_TRIP TRIP PWR_V_VTTREF VTTREF N On On On Off Off Off Off(Hi-Z) ischarge Mode VIN VT PN 0 VTTIN VTT Tracking ischarge Non-tracking ischarge V_ PR0 PWR_V_VT RJ--P PWR_V_RVH PWR_V_W TP_RVL 00 Modify: hange V power soluiton to TP from TP follow power team rian suggest. RVH W RVL VQ 9 VTT VTTN TPRUKR-P..0 PWR_V_VQ P U0VKX-P P0 U0VKX-P P 0UVMX-P.00.0 ZN0M Id=0, Qg=9.n, Rdson=.9 mohm 00 modify PR0_ ir0p-t-e Id=0, Qg=.n, Rdson=.~. mohm +0V_R_P P 0UVMX-P 0 Modify: un-stuff P from power team rian updated. +0V_R_P 0V_0 P0 P-LOE-PWR P0 P-LOE-PWR R_VREF_ PWR_V_VTTREF PR 0R00-P 00 Modify: dd PR 0ohm 00 pad on PWR_V_VTTREF. 09 Modify: hange PU0 part number to.00.0 from.0.0 base on power team rian suggestion. PU0 P9 UVKX-P IR0P-T-E-P PU nd = IRP-T-E-P V_PWR 9,, PM_LP_# P09 0UVKX-P.00.0 nd =.00.0 P0 U0VKX-P PR RF--P TP_PH_ET P 0UVKX-P P 0P0VKX-P +PWR_R_V.R0.0 nd =.R.0Q.R0.0 Id=~9 R=.~.mohm ize=0x.x 00 Modify: P0 uf00 on PWR_V_VTTIN. 00 PR0 P 0UVKX-P PL0 IN-UH--P-U 09 X0 Modify: dd nd source.r.0q on PL0 base on rian updated nd soruce excel file. PWR_V_VQ 0 Modify: Removed PR,PR and connect 0V_EN to VTTEN directly. 0R00-P--P P U0VKX-P P0 P-LOE-PWR--P P UVKX-P PWR_V_EN P0 U0VKX-P TOUT +PWR_R_V P0 P0 UVKX-P P-LOE-PWR P0 P-LOE-PWR P0 P-LOE-PWR P0 P-LOE-PWR esign urrent =..<OP<. P U0VKX-P V_PWR PT0 E90UVM-P V.0L nd =.99.0L E0 U0VKX-P 090 X0 Modify: hange PT0 to 9.9V.0L from 9.9.0L sync with Q-NV dd nd source.99.0l on PT0. 9.9V.0L 90uF,.V,.X. ER=0m [, Iripple=. P0 P-LOE-PWR P09 P-LOE-PWR P0 P-LOE-PWR P P-LOE-PWR P P-LOE-PWR P P-LOE-PWR P P-LOE-PWR P P-LOE-PWR P P-LOE-PWR P P-LOE-PWR P P-LOE-PWR P9 P-LOE-PWR P0 P-LOE-PWR P P-LOE-PWR P P-LOE-PWR P P-LOE-PWR P P-LOE-PWR P P-LOE-PWR <Variant Name> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. TP_+.V_U ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet of 0 00

47 I = PWR.Plane.Regulator_V_0 V_ TP PWM for V_0 P09 UVKX-P P0 00P0VJN-P PR09 P0 PR09 F_ 00P0VKX-P K9RF-P 09 Modify _OMP PU0 V N PN 0 9 F OMP VIN VIN PN PN VT P UVKX-P _VT PR0 _VT_ 0R00-P P 0UVMX-P P 0UVMX-P V_ +.V_RUN esign current =.9 V_RUN_PWR V_0 P0 9,,,, PM_LP_# 090 X0 Modify: hange PR to 0K from 0ohm and stuff P for fine tune V_0 ramp up sequence. V_0 9,,,9 RUNPWROK PR0 KRF-P _P 00KRJ--P PR _EN _W P0_ P 00P0VKX-P 09 Modify P_ V_RUN_PWR 090 X0 Modify: stuff P uf from rian updated. _F_ P0 P-LOE-PWR _F PR 0KRF--P PR 0KRJ--P P UVKX-P RE MOE POO EN TPRTR-P..0 W# W# W# P UVKX-P PL0 IN-UH--P-U.R0.0 nd =.R.0J PR 0RF-P P0 P-LOE-PWR--P PR0 0KRF-L-P P 0UVMX-P UVMX-P P P-LOE-PWR P0 P-LOE-PWR P0 P-LOE-PWR P09 P-LOE-PWR NTI Whistler Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. TP for V_0 ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet of 0 00

48 TP for V X0 Modify: set TP PWM solution dummy field for V_PWM and PL9 LO solution dummy field for V_LO. defualt stuff V_LO at T stage. V_ P0 V_PWM V_PWM UVKX-P VI0 L H H, VI L L.0VTT_PWR V_ PWR_V_VRV V 0.9V L H 0.V H PR0 RF-P V_PWM P P P V_PWM V_PWM UVKX-P UVKX-P UVKX-P P U0VKX-P P U0VKX-P V_PWM P Footprint = QFN-H0 0.V 0.V V_PWR V_0 V_0 PWR_V_POO PWR_V_OMP PWR_V_VREF PWR_V_OMP_ PL9_EN PWR_V_VI PWR_V_VI0 PWR_V_EN PWR_V_VOUT PWR_V_LEW PL9 for V X0 Modify: O-LY PL9 related circuit for V LO solution. 9 0 TPRER-P PR 0RJ--P V_LO PU0 000 V. for R board P UVKX-P PN PN PN VIN VIN VIN N..0 PR9 KRJ--P V_ Vout=0.*(+R/R) V_EL L H V_PWM N VREF OMP LEW VOUT MOE PR09 KRJ--P V_PWR 0.9V 0.V V_PWR PR KRF--P PWR_V_T PR0 PWR_V_T_R 0R00-P PWR_V_W 0V_0 V_EL 9 H_F_ 9 PR0 0R00-P.0VTT_PWR, V_PWM PR 00RF-L-P-U V_PWM 0R00-P P0 0U0VKX-P V_PWM PR0 K99RF-L-P V_PWM V_PWM P0 U0VKX-P V_PWM P UVKX-P V_LO VRV VFILT POO VI VI0 EN PR0 0R00-P V_PWM V_PWM T W# W#0 W#9 W# W# 0 9 P 00P0VKX-P V_PWM PR0 0R00-P PR0 0R00-P V_PWM V_LO POK EN PU0 PL9KI-TRL-P.09.0 VNTL N VIN VIN 9 VOUT VOUT V_LO P0 UVKX-P F V_PWM E0 U0VKX-P V_PWM PR0 PWR_V_VIN R P 0UVMX-P PWR_V_F R 0V_0 V_LO PWR_V_NU VU_ENE 9 P-LOE-PWR P0 P-LOE-PWR P09 P-LOE-PWR P0 P-LOE-PWR P 0V_VTT V_LO V_LO V_LO P-LOE-PWR P V_LO P-LOE-PWR P0 0UVMX-P PR 0KRF--P V_LO PR 0KRF-P V_LO P UVKX-P V_PWM V_PWM P0 V_LO V_LO PQ0 N00KW-P.N0.F nd =.M0.0F V_LO PR 0KRF-P PR0 RF--P PQ0_ V_PWR.R0.0M Id=.~ R=~.mohm ize=.x.9x PL0 IN-UH--P V_PWM.R0.0M nd =.R0.0V P09 0P0V-P Iomax= OP>9 V=0.V V_LO P 00P0VJN-P V_LO P 0UVMX-P PQ0_ V_0 UVMX-P P0 esign urrent =..<OP<. 0V_0 V_PWM V_PWM V_PWM V_PWM P9 0UVMX-P V_LO PR 0KRF--P PT0 T00UVM-P UVMX-P P0 PR UVMX-P P0 UVMX-P P0 P-LOE-PWR P0 V_EL 9 0V_0 V_LO V_LO P-LOE-PWR P0 P-LOE-PWR P0 P-LOE-PWR P0 0KRJ--P P U0VKX-P P0 P0 V_LO V_LO V_LO P-LOE-PWR P0 V_LO P-LOE-PWR UVKX-P PQ0_ <ore esign> X0 Modify: hange PT0 to 00u(.0.0L) from 0u from power team rian updated. X0 Modify: Updated V_LO circuit from Power team rian updated. Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. TP_V ize ocument Number Rev QUEEN&NIRVN Tuesday, January 0, 0 ate: heet of 0 00

49 I = VIEO 0909 X0 Modify: hange L to 0.F.00 for 0pin Re-assign L pin define base on Roy updated cable pin define list. LV ONNETOR L NP NP TOUT_L E909 U0VKX-P V_ P-ON0-P 90 KP0VKX-P TOUT_L L_RIHTNE U_MER# U_MER LON_OUT_ 0.F.00 nd = 0.F0.00 U_PN U_PP 90 U0VKX-P F90 0R00-P L_TT_ F90 90 U0VKX-P R90 RJ--P V_MER_0 U_MI_LK 9 U_MI_IN0 9 LV_LK LV_LK# LV_T LV_T# LV_T LV_T# LV amera Power TOUT V_MER_0 LV LK_R LV T_R V_0 U_MER# U_MER L_KLT_TRL not co-lay LV_T0 LV_T0# LV T_R LV LK_R TP90TP-P V_0 90 UVKX-P RNKJ--P RN90 X0 Modify: hange TR90 M choke to and un-stuff R90,R909 from EM Neo uggestion. POLYW-V-P-U nd = U0VKX-P E nd = FILTER-P--P TR90 U0VKX-P E UVKX-P L_RIHTNE L_TT_ LV_LK# LV_LK E90 E90 P0VN-P P0VN-P 09 X0 Modify: Reserved E90~E9 on LV signal for EM suggestion. For EMI request lose to LV connector LV_T0 LV_T0# LV_T LV_T# LV_T LV_T# E90 E90 E90 E9 P0VJN-P P0VJN-P P0VN-P E9 E9 E9 E9 P0VN-P P0VJN-P P0VJN-P P0VJN-P P0VJN-P I = VIEO L POWER for RO LV_V_EN L_TT_EN TPT-P 09 X0 Modify: hange TPNL to 0.F.00 from ouble updated EMN&XF. 09 X0 Modify: dd nd source 0.F.00;rd source 0.F.00 on TPNL from updated connector list. 90.R00.E N =.000.Q LV_EN LON_OUT_ L_TT_ U_PN0_ U_PP0_ X0 Modify: stuff 90 0.uF from EM Neo suggestion. R90 9K9RF-L-P R90 00KRJ--P LV RN90 LOE TO LV ONN L TPNL TPNL_V TPNL E-ON--P-U 0.F.00 nd = 0.F.00 rd = 0.F.00 Layout 0 mil U_PN0 U_PP0 NTI Whistler 090 X0 Modify: dd nd source.09.09f on U90 sync with nnie. U90 EN N OUT X0 Modify: stuff E90 0.uF from EM Neo suggestion. RN00J--P X0 Modify: hange RN90 to 00ohm p from p for improve layout place. TPNL U0VKX-P E UVKX-P UVKX-P IN# IN# TU-P.0.0F nd =.09.09F LON_OUT L_TT V_0 V_0 TOUH PNEL TPNL U0VKX-P E90 90 U0VKX-P R90 TPNL 00 0 U_PN0_ U_PP0_ X0 Modify: wap TR90 pin, and pin, each other base on onnie swap report. hange TR90 M choke to and un-stuff R9,R9 from EM Neo uggestion. hange R9,R9 to 00 from 00. Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. L onnector 00 9 ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet 9 of 0 0R00-P--P TR90 TPNL FILTER-P--P nd = UVKX-P 00

50 (lanking) <Variant Name> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RT onnector ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet 0 of 0 00

51 I = VIEO HMI_LK_R_ HMI_LK_R_# R0 0R00-P--P R0 0R00-P--P HMI_T0_R_ R0 0R00-P--P R0 HMI_T0_R_# 0R00-P--P HMI_LK_R ON HMI_LK_R_#_ON HMI_T0_R ON HMI_T0_R_#_ON HMI Level hifter & ONNETOR R0 HMI_T_R_ HMI_T_R ON 0R00-P--P 09 X0 Modify: dd R0~R0and reserved TR0~TR0 on all of HMI differential pair for EM suggestion. R0 HMI_T_R_# HMI_T_R_#_ON 0R00-P--P HMI_T_R_ R0 0R00-P--P R0 HMI_T_R_# 0R00-P--P HMI_T_R ON HMI_T_R_#_ON V_V_0 R 00KRJ--P HMI_PLL_N Q0 N00K--P.N0.J R 0RJ--P N =.N0.0 HMI ONN HMI KT-HMI--P-U.09. nd = Modify: hange HMI part number to.09. from.09. base on ME latest EMN and XF. 0 X0 Modify: hange HMI part number to.09. from.09. base on ME ouble updated. 090 X0 Modify: hange HMI part number to.09. from.09. base on ME ouble updated. HMI_T_R ON HMI_T_R_#_ON HMI_T_R ON HMI_T_R_#_ON HMI_T0_R ON HMI_T0_R_#_ON HMI_LK_R ON HMI_LK_R_#_ON _LK_HMI _T_HMI 0 U0VKX-P V_0 V_RT_0_R R 0KRJ--P TP-P FTP0 00 HMI leakage _T_HMI 0 Modify: dd F0 FUE for ELL suggesiton. 00 Modify: tuff F0 FUE from ELL suggestion. X0 0. HMI_IN# HMI_LK# HMI_LK HMI_T0# HMI_T0 HMI_T# HMI_T HMI_T# HMI_T V_0 R09 0KRJ-L-P HMI_LK# HMI_LK HMI_T0# HMI_T0 HMI_T# HMI_T HMI_T# HMI_T HMI_OE# R 0R00-P Q0 N00K--P.N0.J lose to HMI onnector X0 0 0 Modify: tuff R09 0K PH to V_0. N =.N HMI_IN# U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P 00 WP RN0 HMI_PLL_N 00 Modify: dd Q0,R09,R for HMI_IN# to K. RN0 RN0J--P HMI_LK_R_# HMI_LK_R_ HMI_T0_R_# HMI_T0_R_ HMI_T_R_# HMI_T_R_ HMI_T_R_# HMI_T_R_ RN0 RN0J--P 00 WP RN0 0 For NV 09 PU_HMI_LK V_V_0 R 0R00-P--P 00 V_0 R 0RJ--P RN RNKJ--P HP_HMI_ON R0 MRF-P PU_HMI_LK HMI_HP_ R KRF-L-P 09 Modify: Utilize Q0 N00 instead of P909 Level shifter base on Intel recommand on HMI. 00 V_V_0 Q0 V_0.090.L0 nd =.090.P rd =.090.T Q0 N00KW-P R Q0 PM90--P 09 Modify HMI_HP_E R 0RF-N-P R 0KRJ--P _LK_HMI V_RT_0_R KRF-L-P RN0 RNKJ--P 09 WP 00 PU_HMI_HP PEX_RT#,, HMI_HP_ET HP_HMI_ON PU_HMI_T Routing uidelines: TRLT must be routed longer than TRLLK within 000 mils (. mm). The total delay on TRLT should be longer than TRLLK. PU_HMI_T N00KW-P.N0.F _T_HMI nd =.M0.0F <Variant Name> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. HMI Level hifter/onnector ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet of 0 00

52 (lanking) <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev QUEEN Reserved ate: Tuesday, January 0, 0 heet of 0 00

53 (lanking) <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev QUEEN LV_witch ate: Tuesday, January 0, 0 heet of 0 00

54 (lanking) <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev QUEEN Reserved ate: Tuesday, January 0, 0 heet of 0 00

55 I = User.Interface (lanking) <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ITP/Fan onnector ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet of 0 00

56 I = T T H onnector 000 V. T_TXP0 T_TXN0 T_RXN0 T_RXP0 09 Modify: Move ll of 0.0uF cap closed to H connector base on Layout guideline. 0UVKX-P 0UVKX-P 0UVKX-P 0UVKX-P T_TXP0_ T_TXN0_ T_RXN0_ T_RXP0_ NP H X0 Modify: stuff E0 0pF from RF fine tune result. V_0 E0 0P0VJN-P V_ UVKX-P U0VKX-P V_0 0U0VZY-P 0 0 U0VKX-P 9 FF_INT TP-P TP0 TP-P TP0 TP-P TP H_0 0 H_ H_ NP TYO-ON--P-U 0.F0.0 nd = dd nd. 090 dd rd. 00 delete.00. T Zero Power O O onnector O NP P P P P P P NP 9 T_TXP_ T_TXN_ T_RX-_ T_RX+_ KT-TP-P-0-P-U.00.E0 nd =.00.0 rd = Modify: hange O connector part number to.000. base on ME EMN and XF. 00 Modify: hange O connector part number to.00.e0 base on latest EMN and XF. T_O_PRNT# T_O_#_ 000 V. T_RX- and T_RX+ Trace Length match within 0 mil Mars: Exchange O and ET differential pair each other. 0UVKX-P 0UVKX-P 0 0UVKX-P 0 0UVKX-P R0 0KRJ--P O_PWR_V 000 V. T_O_PWRT T_O_# 09 Modify: Move ll of 0.0uF cap closed to O connector base on Layout guideline. T_TXP T_TXN T_RXN T_RXP 0RJ--P R0 09 Modify: Move R0 PH 0K to RN0 PH. RN0 RN0KJ--P T_O_# V_0 UPPORT ZERO T O When the drive is powered on, the FET to the M/ pin drive is OFF. When the drive is powered off, the FET to the M/ pin is ON Q0 V_0 R0 00KRJ--P O_PWRT# T_O_#_ T_O_PWRT T_O_# 00 Modify: hange Q0 to UL N00 for isolate M/ signal between PH and O. N00KW-P.N0.F nd =.M0.0F T_O_PWRT V_0 09 0UVKX-P 09 Modify: Move R0 PH 0K to RN0 PH. <Variant Name> U0 FPU-P EN/EN# IN# IN# N O# OUT# OUT# OUT#.00.9 N = H/O O_PWR_V 0 0UVKX-P O_PWR_V Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. 00 mil ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet of 0 00

57 I = ET U HRER 09 Modify U0 00 Modify: hange U0 U HRER circuit to PIU0 from MX. 009 U_PP_R U_PN_R N + N 0 Y+ 9 Y- V - 0R00-P UHRER_0 R U_PP U_PN 009 V_ X0 Modify: hange TR0M choke to and un-stuff R,R9 from EM Neo uggestion. X0 Modify: hange R,R9 to 00 from uto PIU0ZEE-P +/- connects to Y+/- 0 U0VKX-P witch ontrol it: =0 (M):auto detection charger identification active. = (PM):connect P/M to TP/TM. ET ONN U_PN_R TR0 U_PN_ 0 U_PP_R FILTER-P--P nd = U_PP_ FTEP-P FTEP-P FTEP-P T_TXP T_TXN T_RXP T_RXN close to ET FTP FTP FTP0 V_U_ U_PN_ U_PP_ 0 0UVKX-P 0 0UVKX-P 0 0UVKX-P 0 0UVKX-P U_PP_ U_PN_ V_U_ T_TXP_ T_TXN_ T_RXP_ T_RXN_ 09 Modify: Move ll of 0.0uF cap closed to ET connector base on Layout guideline. 00 Modify: hange ET part number to.0.f base on latest EMN and XF. 0 Modify: dd UET_ON# on ET pin for U temporary detect solution ET ONN should be searched for detect type connector. 09 Modify: ME ouble provide temporary foxconn ET conn.090. for I stage function test. ET VU T T N N N N N N N N KT-ET-U-P--P-U.0.W nd =.09. E-T U.0 ombo E/H=-0./.mm with detect function R 0R00-P ET_ UET_ON# FTP FTEP-P <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ET ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet of 0 00

58 I = UIO U_PK_L- U_PK_L+ U_PK_R- U_PK_R+ 00 R0 0R00-P--P R0 0R00-P--P R0 0R00-P--P R0 0R00-P--P E0 0P0V--P E0 0P0V--P E0 0P0V--P X0 Modify: stuff E0~E0 0pF from EM Neo suggestion. U_PK_L-_ U_PK_L+_ U_PK_R-_ U_PK_R+_ E0 0P0V--P E-ON--P-U PK 0.F0.00 nd = 0.F X0 Modify: dd nd 0.F0.00 on PK from ME updated connector list. 09 X0 Modify: hange PK to 0.F0.00 from 0.F.00 from ouble updated. 09 X0 Modify: Re-assign PK pin define base on Roy updated excel file for 0.F0.00 TP-P TP-P TP-P TP-P FTP0 FTP0 FTP0 FTP0 U_PK_L-_ U_PK_L+_ U_PK_R-_ U_PK_R+_ <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev QUEEN PEKER ONN ate: Tuesday, January 0, 0 heet of 0 00

59 (lanking) <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev QUEEN Reserved ate: Tuesday, January 0, 0 heet 9 of 0 00

60 I = Flash.ROM PI FLH ROM (M byte) for PH V_ 00 Modify: hange RN00.K to R00,R00,R00.K 00 for layout routing. V_ Notes: The total PI interface signal between E and PH can t not exceed 00mil. The mismatch between PI signal must be within 00mil R00 KRJ--P R00 KRJ--P R00 KRJ--P PI_HOL_0# 00 0UVKX-P 00 U0VKX-P U00 V_, PI_0#_R, PI_O_R R00 RJ--P E00 P0VN-P PI_O PI_WP# # O WP# V HOL# LK I WQI--P.Q.0 nd =.0.0 rd =.P.0 09 Modify: hange U00 part number to.0.0 base on ourcer provide recommand ROM list. E00 P0VN-P E00 0P0VJN-P PI_LK_R, PI_I_R, 09 X0 Modify: E00 change to 0p from.p and default stuff from Neo suggestion. X0 X0 I = RTT V_UX_ 00 UVKX-P RT_PWR RT_UX_ RT_PWR.R00. nd =.0000.E Width=0mils X0 Modify: dd Q00,R00 fo FTORY RT detect function Q00 R00 00RJ--P N00K--P HFPT-P TP-P TP00 X0 +RT_V R00 KRJ--P TP-P TP00 +RT_V PWR N NP NP NP NP T-00P00E-P-U 00 Update RT RT nd = rd = Modify: hange RT connector part number to base on ME EMN and XF. R00 0MRJ-L-P Q00.N0.J N =.N0.0 RT_ET# VccRT is now connected to VccW_ through the chottky diode instead of the.v us well. <Variant Name> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Flash/RT ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet 0 of 0 00

61 I = U RT oard and OMO U Power V_ upport U0 U_O#_9 V_U_ X0 Modify: Removed 0,0. 0 U0VKX-P 0 U0VKX-P at least 0 mil U_PWR_EN# U_RT_ON# N IN EN# EN# FL OUT OUT FL P--P.0.0 nd =.00. rd = X0 Modify: hange U0 to dual U power switch from single for Layout limitation and placement. X0 Modify: hange U0 st(.0.0);nd(.00.) ;rd(.00.09) from ourcer Harrison suggestion. at least 0 mil U_O#0_ 0 U0VKX-P at least 0 mil 0 U0VKX-P V_U_ T0 0UVKX-P 00 T0 T00UVM--P 0.0.L nd =.0.0L <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. U Power W ize ocument Number Rev QUEEN&NIRVN ate: Tuesday, January 0, 0 heet of 0 00

62 (lanking) <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev QUEEN Reserved ate: Tuesday, January 0, 0 heet of 0 00

63 I = User.Interface R0 0RJ--P T_LE Q0 N00K--P.N0.J 0 Modify: dd Q0 and combine T_LE to WLN_WWN_LE#. N =.N0.0 WLN_WWN_LE# FTP0 FTP0 FTP0 FTP0 FTP0 luetooth Module conn. LUETOOTH_ET# WLN_T _ON LUETOOTH_EN T_LE LUETOOTH_PIO LUETOOTH_PIO 9 T HR-ONN-P-U NP 0 NP 0.F09.0 nd = 0.F Update T T_T U_PP U_PN FTP0 V_0 x0 change tolerant UVMX--P 0 Modify: hange 0 to.0.l follow common parts data base., WLN_WWN_LE# U_PP U_PN T_T, LUETOOTH_EN WLN_T R0 00KRJ--P T_T LUETOOTH_EN WLN_T E0 0P0VKX-P R0 0KRJ--P FTP09 FTP0 FTP0 FTP FTP FTP 009 Modify: PM confirmed there is no stand-alone T module, so T connector, add T enable signal and V_ power option on WLN connector pin. 0 Modify: tuff T relatek component to verify function. WLN_T LUETOOTH_EN T_T V_0 U_PP U_PN <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev QUEEN luetooth ate: Tuesday, January 0, 0 heet of 0 00

64 Finger Printer onnector 00 Modify: dd FP_ET# signal on FP pin. 0 Modify: dd FP_ET# signal on FP pin. 00 wap pin. 00 hange to pin. 0 hange to pin. X0 Modify: dd 0 0.uF,0 0pF and stuff 0 pf from RF fine tune result. V_0 E0 P0VJN-P iometric_upn iometric_upp E0 U0VKX-P E0 0P0VJN-P FP N E-ON--P 0.K00.00 nd = 0.K0.00 U_PN N R0 0RJ--P iometric_upn FTP FTP FTP V_0 iometric_upn iometric_upp 09 X0 Modify: stuff TR0 and un-stuff R0,R0 at X0 stage from EM Neo suggestion. U_PP 00 9 R0 iometric_upp 0RJ--P N 0 Modify: hange FP connector part number to 0.K00.00 base on ME EMN and XF. 00 Modify: hange FP connector part number to 0.K00.00 base on ME EMN and XF. 00 Modify: Reassign Figer print pin define base on EXEL FILE. 0 Modify: Reassign Figer print pin define base on EXEL FILE. Removed FP_ET# on FP. <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. REERVE QUEEN ize ocument Number Rev ate: Tuesday, January 0, 0 heet of 0 00

65 (lanking) <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev QUEEN REERVE ate: Tuesday, January 0, 0 heet of 0 00

66 (lanking) <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev QUEEN Reserved ate: Tuesday, January 0, 0 heet of 0 00

67 (lanking) <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev QUEEN Reserved ate: Tuesday, January 0, 0 heet of 0 00

68 I = User.Interface FRONT POWER LE Need change to LOW actived from K PIO PWRLE# T_LE# TP_LOK_LE# TT_WHITE_LE# H_MER_LE# RN0 RNKJ--P TPLOK LE PWRLE#_ T_LE#_ T H LE(White) attery LE(WHITE_LE) Need change to LOW actived from K PIO 00 Modify: Rename HRE_LE# to H_MER_LE# Rename _TFULL# to TT_WHITE_LE#. 09 Modify Q0_ WHITE_LE_T# MER_LE_T# attery LE(MER_LE) Need change to LOW actived from K PIO R0 KRJ--P RN0 RNKJ--P Need change to LOW actived from K PIO Q0 R Q0 R R R E PTET-P.00.M nd =.0.0 rd =.00.N E PTET-P.00.M nd =.0.0 rd =.00.N Q0 R R E PTET-P.00.M nd =.0.0 rd =.00.N V_ LE_PWR E0 0P0VKX-P V_0 V_0 T_LE_R TP_LOK_LE_R Q0 R NEE confirm with ME actual FPOWER_LE part number. X0 R E PTET-P.00.M nd =.0.0 rd =.00.N Q0 R R E0 0P0VKX-P E0 0P0VKX-P E PTET-P.00.M nd =.0.0 rd =.00.N H_LE_ R 90RJ--P V_ WHITE_LE_T V_ MER_LE_T R TP_LOK_LE_ 90RJ--P E0 0P0VKX-P 00 Modify: hange TP_LOK_LE part number to.9.j0 base on latest EMN and XF. FPLE NEE confirm with ME actual H_LE part number. T_WHITE R0 90RJ--P T_MER R0 90RJ--P NEE confirm with ME actual H_LE part number. 09 X0 Modify: nd = dd nd source.0090.z0 on TPLOKLE TPLOKLE from ourcer nya suggestion. 00 Modify: hange FPOWER_LE part number to.0.r0 base on latest EMN and XF. 00 FPOWER_LE_ K R0 90RJ--P LE-W--P POWER_W_LE_ R0 KRJ--P.0.R0 nd =.000.R0 POWER_W_LE_ R KRJ--P 00 9 delete Liteon for package HLE Modify: hange H_LE part number to.0.r0 base on latest EMN and XF. NEE confirm with ME actual H_LE part number. WHITE K_PWRTN#_ POWER_W_LE_ POWER_W_LE_, WLN_WWN_LE# LE-W--P 09 X0 Modify: dd nd source.000.j0 on FPOWERLE HLE,WLNLE from ourcer nya suggestion. nd =.000.R delete Liteon for package K.0.R0 E09 0P0VKX-P TPLE K N LE-Y--P.09.P0 TPLE K Q LE-Y--P.09.P0 nd = HLE + + ORNE 00 delete X0 Modify: dd nd source.00.0 on HRERLEfrom ourcer nya suggestion. 00 Modify: hange TP_LOK_LE part number to.9.j0 base on latest EMN and XF WHITE - ORNE LE-OW--P.0.X0 nd = Modify: WLN LE# rename to WLN_WWN_LE#. 00 Modify: dd PWRTN for Q,PWRTN FOR N. 00 PWRT N WLN_LE 09 Modify Q0 R Q0_ KRJ--P K WLE LE-W--P.0.R0 nd =.000.R delete Liteon for package 00 Modify: hange WLN_LE part number to.0.r0 base on latest EMN and XF. WLN_LE_ R 90RJ--P 09 X0 Modify: dd nd source.000.j0 on FPOWERLE HLE,WLNLE from ourcer nya suggestion. R R E PTET-P.00.M nd =.0.0 rd =.00.N V_0 0P0VKX-P E WLN_LE_R K_PWRTN# R0 00RJ--P PWRT 00 E-ON-0-P-U 0.K00.00 nd = 0.K Modify: Removed PWR_TN_LE# control circuit base on ell feedback. K_PWRTN#_ POWER_W_LE_ POWER_W_LE_ Q E-ON-0-P-U 0.K00.00 nd = 0.K0.00 K_PWRTN#_ FTP0 POWER_W_LE_ FTP0 POWER_W_LE_ FTP0 <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. LE ard/power utton ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet of 0 00

69 I = K I = Touch.Pad Internal Keyoard onnector 0 Modify: dd R90,R909 for TP co-lay power option. 00 Modify: hange K part number to 0.K0.00 base on ME updated EMN and XF. K JE-ON0--P 0.K0.00 nd = 0.K09.00 KROW KROW KROW KROW KROW KROW KROW KROW0 KOL KOL KOL KOL KOL KOL KOL KOL KOL0 KOL KOL KOL KOL KOL KOL9 KOL KOL0 P_LE FTP FTP FTP FTP FTP9 FTP0 FTP FTP FTP FTP FTP FTP FTP FTP FTP9 FTP0 FTP FTP FTP FTP FTP FTP FTP FTP FTP9 FTP0 P_LE_R FTP KROW[0..] KOL[0..] K_ET# High ctive from K PIO. R90 Q90_ KRJ--P P_LE_R P LE ONTROL Q90 R R E V_ X0 P_LE_R P_LE_Q P_LE_R R90 KRJ--P TPLK TPT TouchPad onnector TP_V 90 P0VJN-P 0 Modify: Removed TP LOKE ONTROL combin with KEYOR Function KEY. 0 Modify: hange TP power source to V_0 from V_0 base on ELL latest spec 0. 0 Modify: WP RN90 RN90 RN0KJ--P 09 TP_V 90 P0VJN-P FTP FTP FTP FTP TP_V TPLK TPT 00 Modify: hange TP part number to 0.K00.00 base on ME updated EMN&XF. 0 Modify: hange TP part number to 0.K00.00 from 0.K U0VKX-P TP E-ON-0-P-U 0.K00.00 nd = 0.K Modify: hange TP pin define to follow TOUH P THEET. 0 Modify: hange TP pin define to follow TOUH P THEET. TP_V R90 0RJ--P R909 0RJ--P V_0 V_0 09 X0 Modify: un-stuff R90 and stuff R90,Q90,R90 for V drive P LE. P_LE:(efault HIH actived) onnect to K driving internal LE directly.(mx m) PTET-P.00.M nd =.0.0 rd =.00.N R90 00RJ--P K acklight onnector V_0 +V_K_L F90 FUE-V--P R90 0RJ--P N K_LE_L_ET 0 Modify: hange K acklight control all of related circuit component column to VOTRO from. 00 Modify: R90 change to K 00 from 00ohm for K_LE_L_ET to PH PIO. updated KLIT pin define base on K T HEET. K_L_TRL N 90 U0VKX-P R90 N KRJ--P R90 00KRJ--P N MX 0m K_LE_ET_ R90 00KRJ--P N 90 U0VKX-P K_L_TRL# KLIT E-ON--P 0.K09.00 nd = 0.K0.00 Q90 P0M-P N N.P0.0 nd =.00. +V_K_L K_LE_ET_ K_L_TRL# FTP FTP FTP FTP 090 X0 Modify: hange KLIT to 0.K00.00 from 0.K0.00 base on ME updated X0 XF&EMN. Re-assign KLIT pin define sync with Q_NV. 09 X0 Modify: dd nd source 0.K0.00 on KLIT base on updated connector list. 09 X0 Modify: hange KLIT part number to 0.K09.00 and re-assign pin define base on Roy updated. <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Key oard/touch Pad ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet 9 of 0 00

70 HLL NP LI_LOE# V_ 00 swap FTP FTP FTEP-P V_ LI_LOE# FTP FTEP-P TN-ONN0-P NP 0.F.00 nd = 0.F09.00 FTEP-P 0 X0 Modify: dd nd 0.F09.00 on HLL from ME updated connector list. <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Hall ensor ize ocument Number Rev QUEEN ate: Tuesday, January 0, 0 heet 0 of 0 00

71 V_0, LP_0, LP_, LP_, LP_, LP_FRME#,,,,, PLT_RT# LK_PI_LP 9 0 P-0P-0-P ZZ.00P.Y 00 9 change to ZZ.00P.Y(solder kmask type) and keep un-stuffat X-uild stage <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev QUEEN ubug connector ate: Tuesday, January 0, 0 heet of 0 00

72 (lanking) <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev QUEEN Reserved ate: Tuesday, January 0, 0 heet of 0 00

73 (lanking) <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev QUEEN Reserved ate: Tuesday, January 0, 0 heet of 0 00

74 I = IO V_R_0 lose to R /X/M/MM+ ard Reader V_R_0 090 X0 Modify: hange R to 0.I09.00 from.00.9 from ME double updated latest XF&EMN on X0. P P _T0 P P _T P P _T X_0 0 P P P _T X_ P9 X_ P0 P P0 _LK X_ P P P _ X_ P P P _WP X_ P P0 P9 _M X_ P X_ X_ X_# P P P P P P P P P P P9 P P P P P9 P P 9 X0 Modify: dd nd 0.I0.00 on HLL from ME updated connector list. For EMI Reserved P P P P P P P P P9 P0 P P P P X_ X_# <ore esign> Wistron orporation E0 0P0VKX-P 0 0UVKX-P E 0P0VKX-P E0 0P0VKX-P 0 U0VKX-P E0 0P0VKX-P E 0P0VKX-P E0 0P0VKX-P 0 0UVMX-P 0 UVMX--P R P P _V M_V X_V X_ X_R/ X_RE X_E X_LE X_LE X_WE X_WP_IN P9 P P0 P P P P M_ M_IN M_LK M_T0 M_T M_T M_T _WP_OM/IO_N P OM/IO_N P _N P _N P M_N P M_N P P P P P MM_T MM_T MM_T MM_T X_N 9 X_N 9 NP NP NP NP R-PUH-P--P-U 0.I09.00 nd = 0.I0.00 E09 0P0VKX-P E 0P0VKX-P E 0P0VKX-P E0 0P0VKX-P E 0P0VKX-P E0 0P0VKX-P E 0P0VKX-P E0 0P0VKX-P E0 0P0VKX-P 0 U0VKX-P E 0P0VKX-P F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ate: Tuesday, January 0, 0 heet of 0 /X/M/MM ard ONN ize ocument Number Rev QUEEN 00

75 V_0_R Max. 0m, verage 00m. V_0_R Max. 00m, verage 000m V RUX Max. m 0 X0 Modify: ue to our NEW change to Express card to bottom side so re-assign NEW pin define same as Q-NV. 090 X0 Modify: dd nd source 0.K0.0 on NEW base on updated connector list. - NEW U_PP U_PN X0 Modify: hange TR0 M choke to and un-stuff R0,R0 from EM Neo uggestion. hange R0,R0 to 00 from nd = FILTER-P--P N TR0 U_PP_R 00 9 U_PN_R PIE_TXP PIE_TXN PIE_RXP PIE_RXN 0 LK_PIE_NEW 0 LK_PIE_NEW# 0 LK_PIE_NEW_REQ# V_0 V_, PIE_WKE# V_0 0 M_T 0 M_LK 9,, PM_LP_# 9,,,, PM_LP_#,,,,, PLT_RT# N R0 0RJ--PPIE_TXP_ON N PIE_TXN_ON R0 0RJ--P N PIE_RXP_ON R0 N 0RJ--PPIE_RXN_ON R0 0RJ--P N LK_PIE_NEW_ R0 N 0RJ--PLK_PIE_NEW#_9 R0 0RJ--P 0 N LK_PIE_NEW_REQ#_ON R09 0RJ--P N PIE_WKE#_ON R0 0RJ--P M_T 9 M_LK 0 PM_LP_# PM_LP_# PLT_RT# U_PP_R U_PN_R 09 X0 Modify: Rename NEW pin, to U_PP_R&U_PN_R. Rename NEW pin,9 to LK_PIE_NEW_&LK_PIE_NEW#_ N E-ON-P-U 0.K00.0 nd = 0.K0.0 FTEP-P FTP0 FTEP-P FTP0 FTEP-P FTP09 FTEP-P FTP0 FTEP-P FTP FTEP-P FTP FTEP-P FTP FTEP-P FTP FTEP-P FTP FTEP-P FTP FTEP-P FTP FTEP-P FTP FTEP-P FTP9 FTEP-P FTP0 FTEP-P FTP FTEP-P FTP FTEP-P FTP FTEP-P FTP V_ V_0 V_0 U_PN_R U_PP_R LK_PIE_NEW_REQ#_ON M_LK M_T PM_LP_# PM_LP_# PLT_RT# LK_PIE_NEW#_ LK_PIE_NEW_ PIE_TXN_ON PIE_TXP_ON PIE_RXN_ON PIE_RXP_ON PIE_WKE#_ON For EMI LK_PIE_NEW#_ LK_PIE_NEW_ E0 E0 P0VN-P P0VN-P 09 X0 Modify: dd R0,R0 and reserved E0,E0 on LK_PIE_NEW &LK_PIE_NEW# for EM suggestion. 09 X0 Modify: dd R0~R0 0ohm and reserved E0~E0 on PIE_TX&RX signal base on EM Lance suggestion. dd R09,R0 0ohm and reserved E0,E0 on LK_PIE_NEW_REQ#&PIE_WKE# signal base on EM Lance suggestion. PIE_TXP_ON PIE_TXN_ON PIE_RXP PIE_RXN E0 E0 E0 E0 P0VN-P P0VN-P P0VN-P P0VN-P LK_PIE_NEW_REQ# PIE_WKE# E0 E0 P0VN-P P0VN-P <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev QUEEN Express ard ate: Tuesday, January 0, 0 heet of 0 00

76 (lanking) <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev QUEEN Reserved ate: Tuesday, January 0, 0 heet of 0 00

77 (lanking) <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev QUEEN Reserved ate: Tuesday, January 0, 0 heet of 0 00

78 (lanking) <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev QUEEN Reserved ate: Tuesday, January 0, 0 heet of 0 00

79 I = User.Interface Free Fall ensor V_0 Note - no via, trace, under the sensor (keep out area around mm) - stay away from the screw hole or metal shield soldering joints - design P pad based on our sensor L pad size (add 0.mm) - solder stencil opening to 90% of the P pad size - mount the sensor near the center of mass of the N as possible as you can 90 0UVMX-P V_0,,0, PH_MLK,,0, PH_MT V_0 09/0 (#) Just pull +.V_RUN ~ Ref. Rothschild (#) FE/ is ok, chip internal pull-up resistors (#) From spec, lave dress() is 000xb Pull HIH is 000b Pull N is 0000b PH_MLK PH_MT R90 H_FLL_O 00KRJ--P U90 L/P /I/O O V REERVE# REERVE# ELTR-P V_IO 90 U0VKX-P.00.0 INT INT 00 Modify: hange -ENOR U90 back to ELTR. 00 Modify: hange UMMY column to:min source->i solution. second source->t solution. 9 N N N N 0 R90 00KRJ--P H_FLL_INT H_FLL_INT FF_INT_R 00 Modify: R0 and R90 double PH. V_0 V_0 Q90 N00KW-P.N0.F nd =.M0.0F R90 00KRJ--P R90 00KRJ--P FLL_INT V_0 R90 0RJ--P R90 0KRJ--P 00 FF_INT FF_INT_R Note () Keep all signals are the same trace width. (included V, N). () No VI under I bottom. <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev QUEEN Free Fall ensor ate: Tuesday, January 0, 0 heet 9 of 0 00

80 (lanking) <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev QUEEN Reserved ate: Tuesday, January 0, 0 heet 0 of 0 00

81 (lanking) <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev QUEEN Reserved ate: Tuesday, January 0, 0 heet of 0 00

82 IO oard X0 Modify: ONN 0 pin ell required us to disable PIE port of WWN slot,if PIE port is disabled, it will cause all PIE port disabled,so change WWN to PIE port from port at T stage LK_PIE_WWN_REQ# U_PP U_PN 0 PIE_LK_LN_REQ# U_PP U_PN X0 V_ U0_MI# WLN_T 0 U_PE_LKREQ#,,0,9 PH_MT,,0,9 PH_MLK U_PWR_ON 0 0 PIE_TXP PIE_TXN 0 PIE_RXN 0 PIE_RXP 0 0 PIE_TXN PIE_TXP 0 PIE_RXP 0 PIE_RXN 0 PIE_RXN 0 PIE_RXP PIE_TXP PIE_TXN PIE_RXN PIE_RXP PIE_TXP PIE_TXN 090 X0 Modify: dd nd source 0.F00.00 on RT base on updated connector list. 09 X0 Modify: Re-assign RT pin define base on EM suggestion. V_RT_0_R V_0 PI_E RI U_PN U_PP RT_HYN_ON RT_VYN_ON + rd = 0.F Modify: hange RT part number to 0.F09.00 from 0.F.00 base on EMN updated part number. 00 Modify: hange RT connector to 0.F.00 from 0pin base on ME ouble provide final solution. 0 Modify: re-assign RT pin define to follow Joseph release PIN define. RT oard onnector NP NP IO E-ONN0--P 0.F9.00 nd = 0.F90.00 RT E-ONN0-P NP NP 0.F.00 nd = 0.F RT_LUE RT_REEN RT_RE U_N 09 X0 Modify: hange R0~R0 to 0ohm from 00ohm. dd RN09 PH V_ on MEI_LE~# for PWM O mode. + RT T RT LK RT_RE RT_REEN RT_LUE LK_PIE_LN 0 LK_PIE_LN# 0 LK_PIE_WWN 0 LK_PIE_WWN# 0 LK_PIE_WLN 0 LK_PIE_WLN# 0 LK_PIE_U 0 LK_PIE_U# 0 V_0 V_0 V EN LK_PIE_WLN_REQ# 0 E_TX E_RX WIFI_RF_EN WLN_WWN_LE#, PM_LN_ENLE PLT_RT#,,,,, PIE_WKE#, X0 Modify: stuff E0,E0 0.u(closed H) LUETOOTH_EN, between N and N from EM Neo suggestion. T_T stuff E0 between V_ and N from R0 0R00-P--P EM Neo suggestion. U_HP_J# 9 EXT_MI_J# 9 MI_IN_L 9 MI_IN_R 9 V_ U_HP_JK_L 9 R0 U_HP_JK_R 9 0R00-P--P FTP0 FTP0 FTP0 FTP0 FTP0 FTP0 FTP0 MEI 9 RT T RT LK X0 MEI_ MEI_ MEI_ V_ INTNT_ON# V_ 00 MEI_ R0 MEI_ KRJ--P MEI_ RT_RE RT_REEN RT_LUE 09 X0 Modify: Keep original X00 IO pin define. 09 X0 Modify: hange IO part number to 0.F9.00 base on ouble updated latest XF&EMN. 090 X0 Modify: Re-assign IO pin define due to updated connector pin define is different as before. dd R0,R0 to isolated N and N. V_ MEI_LE# MEI_LE# R0 0KRJ--P MEI_LE# R0 0KRJ--P R0 0KRJ--P 9 X0 Modify: Reserved E0~E0 0p on all of T_REOVERY# MEI_LE# signal from EM Neo suggestion. MEI_TN# MEI_LE# MEI_LE# E0 0P0V--P MEI_LE# E0 0P0V--P E0 0P0V--P High active MEI_LE# MEI_LE# MEI_LE# INTNT_ON# T_REOVERY# MEI_TN# E-ON-9-P 0 X0 Modify: 0.K00.00 dd nd 0.K0.00 on MEI from RT LK ME updated connector list. RT T nd = 0.K0.00 X0 Modify: change Media resistor from 0 ohm to K on V_ both Q/N(R0, R0, R0) V_ for Media button LE light spot issue V_U_ 00 X0 Modify: V_RT_0_R R V_RT_0 V_0 Removed R,R and connect V_U_ to RT pin directly. 0RJ-0-U-P 0 0 X0 Modify: Reserved R,R 0ohm 00 on RT pin,9 to separate ET and RT U power in T build add rd T-conn(0.F9.00) at Xuild batch run 0 U0VKX-P E0 U0VKX-P E0 000 R0 R0 for change to parallel resistor RN0 RNKJ--P F0 FUE-V-P-U HH-0PT-P N =.R00.HH nd = rd =.R00.0F.R00.F RN0 RT_VYN_ON RT_VYN RT_HYN_ON RT_HYN U0VKX-P E0 X0 Modify: wap RN0 pin, and pin, each other base on onnie swap report X0 Modify: dd RN0 base on HYN&VYN report. RN--P <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IO oard onnector QUEEN ize ocument Number Rev ate: Tuesday, January 0, 0 heet of 0 00