U35JC SCHEMATIC Revision 1.0

Transcription

1 YTEM PE REF. PE ontent lock iagram ystem etting PU()_MI,PE,FI,LK,MI PU()_R PU()_F,RV, PU()_PWR PU()_XP R O-IMM_0 R O-IMM_ R _Q VOLTE 0 PH_IEX()T,IH,RT,LP PH_IEX()_PIE,LK,M,PE PH_IEX()_FI,MI,Y PWR PH_IEX()_P,LV,RT PH_IEX()_PI,NVRM,U PH_IEX()PU,PIO,MI PH_IEX()_POWER, PH_IEX()_POWER, PH_PI ROM,OTH 9 LK_I9LR9 0 E_IT0(/) E_IT0(/)K, TP RT_Reset ircuit Hybrid witch U_ebug RT_L Panel RT_-ub TV_HMI 0 FN_Fan & ensor X_H & O U_U Port * _ischarge PW_PROTET 0 & T onn. T_luetooth MO MO MER TO onn 0 ME_onn & kew Hole V_Madison UJ HEMTI Revision.0 HMI RT Page Page L Panel INT. MI Page Page LOK IRM Touchpad Page Keyboard Page udio mp Jack Page Page ããäã ãää NM-E Mx VRM IO_. äåãä ebug onn. E ITE IT0 Page 0 äåãä ãää Page Page 0 PI ROM zalia odec Realtek L9 Page Page äãããßèáá ääã ãèæççæ PU LRKFIEL/UURNLE (&Q) ãããßèâ ãäãßèá PH Ibex Peak-M äãäã 0 Page ~ Page 0~ O ããäáßâáááááááäãè äãããßèá åäã Page H() Page 9 0 R O-IMM Miniard WLN hirley Peak/ Echo Peak Miniard TV Tuner igaln R Expressard U Port() U Port() IO_. IO_. Page ~ Page Page Page Page Page Page RJ Page Power VORE ystem VTT_PH R & VTT +.V +NV +VFX_ORE harger Load witch MO amera Miniard TV Tuner luetooth Page 0 Page Page Page Page Page Page Page Page 9 NE UP000F U.0. Page Page Page Page PW_VORE PW_YTEM PW_I/O_VTT_PH PW_I/O_R& VTT PW_I/O_+.V PW_I/O_+NV PW_+VFX_ORE PW_HRER PW_LO WITH PW_INL PW_FLOWHRT ardreader U ardreader Page 0 Page 0 lock enerator I I9LR åäã PWM Fan Page 9 Page 0 et Page 9 ischarge ircuit Page Reset ircuit Page & TT. onn. Page 0 kew Holes Page UTeK OMPUTER IN. N Tuesday, March 0, 00 ate: heet of 99.0

2 PH_IEX PIO PH_IEX PIO Use s ignal Name Pull-up/down Power PIO 00 Native PIO0 EXT PU +V PIO 0 PIO [:] Native Native PIO PI_INT[E:H]# INT PU, EXT PU EXT PU +V +V PIO 0 PIO 0 PIO 0 PI PI PI PU_HP_INTR#_R U_MI# EXT_MI# INT PU, EXT PU INT PU, EXT PU EXT PU & INT PU +V +V +VU PIO 09 PIO 0 Native Native - - EXT PU EXT PU +VU +VU PIO PI EXT_I# EXT PU +VU_OR PIO Native PIO Native H_OK_RT# INT P - PIO Native - - +VU PIO PO T_LE INT P - PIO PO PU_HOL_RT# - - PIO PI PU_PWROK EXT P & INT PU PIO Native LK_REQ_TV# EXT PU +V PIO 9 Native TP EXT PU +V PIO 0 Native LKREQ#_WLN EXT P PIO Native T0P EXT PU +V PIO PO WLN_LE - - PIO Native LP_RQ# INT PU - PIO PO U0_EL - - PIO Native LKREQ_NEWR# EXT PU +VU_OR PIO PI LKREQ_U EXT P PIO Native VRM_EN INT PU - PIO PO WLN_ON# INT PU - PIO 9 Native ME_PM_LP_LN#_PH - - PIO 0 PO ME_usPwrnck EXT PU +VU_OR PIO PI ME PREENT_PH EXT PU +VU_OR PIO PI PM_LKRUN# EXT PU +V PIO PI H_OK_EN# EXT P, INT PU PIO Native PIO EXT PU - PIO Native T_LK_REQ# EXT P - PIO PO dpu_pwr_en#_pio - - PIO PI PU_PRNT# - - PIO PI P_I0 EXT P - PIO 9 PI P_I EXT P - PIO 0 Native - EXT PU +VU PIO Native - EXT PU +VU PIO Native - EXT PU +VU PIO Native - EXT PU +VU PIO Native LK_REQ# EXT PU +VU_OR PIO Native LK_REQ# EXT P, INT PU +VU_OR PIO Native LK_REQ# EXT PU +VU_OR PIO Native LKREQ_PE#_R EXT PU/P +VU_OR PIO Native PIO EXT PU +V PIO 9 PO PH_TEMP_LERT# EXT PU +V EXT PU PIO 0 PIO PIO PIO PIO PIO PIO PIO PIO PIO 9 PIO 0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO Native Native PO Native Native PI_REQ# Native PI_NT# Native LKREQ_LN# PO T_ON PI ML_LK Native - Native ML0LERT# Native PM_U_TT# Native U_LK Native LP_# Native LK_OUT0 Native LK_OUT PO PO LK_OUT LK_OUT Native PW_TLOW# Native LK_REQ0# Native MLLERT# PI ML_T PI_REQ# PI_NT# dpu_elet#_pio - Internal & External +V INT PU - - +V INT PU - EXT PU +V EXT PU, INT PU +V EXT P - - EXT PU +VU_OR EXT PU (Not used) +VU EXT PU +VU_OR INT P - INT P - INT P EXT PU, INT PU +VU_OR INT PU +VU_OR EXT PU +VU_OR EXT PU +VU_OR E PIO Use s ignal Name P0 P P O O O PWR_LE# H_LE# H_FULL_LE# P P P P P P0 P P P P P P P P0 P P P P O O O O IO IO O O O O IO IO O I - L_L_PWM FN_PWM - - TEL_0 TEL_ ME PREENT_E M0_LK M0_T 0TE RIN# PM_RMRT# lock_select_uc M_LK M_T PM_PWRTN# _IN_O# P O OP_# P P P0 I I I T_IN_O# RFON_W# PWRLIMIT# P P I I PM_U# UF_PLT_RT# P P P P P PE0 PE PE PE PE PE PE PE O O O I I I I I EXT_I# EXT_MI# L_KOFF# FN0_TH HMI_HP_E PWR_W# - LI_W# MRTHON# PF0 O - PF PF PF PF PF PF PF P0 P O O O I IO O I I I VU_ON VP_V0 VP_V TP_LK TP_T THRO_PU PH_PI_OV ME_usPwrnck_E PM_U# P - P - PH0 PH PH IO O O PM_LKRUN# FX_VR_ON H_EN PH PH O O U_E# U_E# PH PH O O NUM_LE# P_LE# PI0 I V_LERT# PI PI PI PI PI PI PI PJ0 PJ PJ PJ PJ I I I I I I I O O O O O U_PWR LL_YTEM_PWR VRM_PWR PH_TEMP_LERT# PU_IENE PU_IENE VORE_MET PU_VRON PM_PWROK VET_E IET_E PU_V0 PJ O PU_V E IT0 PIE PIE PIE PIE PIE PIE PIE PIE T T T Minicard WLN LN T 0 T H () M_U RE : lock enerator( I9LVKLFT) evice Identification U.0 UTeK OMPUTER IN. N U 0 U Port () U ard Reader(.0) U U Port () U U U U U U WiFi/WiMax U 9 amera U 0 U U luetooth U Wednesday, March 0, 00 ate: heet of 99.0

3 U00 MI_TXN0 F MI_RX#[0] MI_TXN J MI_RX#[] MI_TXN K MI_RX#[] MI_TXN J MI_RX#[] MI_TXP0 F9 MI_RX[0] MI_TXP J MI_RX[] MI_TXP K9 MI_RX[] MI_TXP J MI_RX[] MI_RXN0 H MI_TX#[0] MI_RXN K MI_TX#[] MI_RXN J MI_TX#[] MI_RXN F0 MI_TX#[] MI_RXP0 MI_TX[0] MI_RXP M MI_TX[] MI_RXP MI_TX[] MI_RXP J MI_TX[] FI_TXN[:0] FI_TXN0 L FI_TXN FI_TX#[0] N FI_TXN FI_TX#[] M FI_TXN FI_TX#[] P FI_TXN FI_TX#[] N0 FI_TXN FI_TX#[] R FI_TXN FI_TX#[] U FI_TXN FI_TX#[] W FI_TX#[] FI_TXP[:0] FI_TXP0 K FI_TXP FI_TX[0] N FI_TXP FI_TX[] N FI_TXP FI_TX[] R FI_TXP FI_TX[] N9 FI_TXP FI_TX[] R FI_TXP FI_TX[] U FI_TXP FI_TX[] W0 FI_TX[] FI_FYN0 FI_FYN[0] FI_FYN 9 FI_FYN[] FI_INT FI_INT FI_LYN0 FI_LYN[0] FI_LYN FI_LYN[] For Intel FX display MI Intel(R) FI PI EXPRE -- RPHI PE_IOMPI PE_IOMPO PE_ROMPO PE_RI PE_RX#[0] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[9] PE_RX#[0] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX[0] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[9] PE_RX[0] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_TX#[0] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[9] PE_TX#[0] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX[0] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[9] PE_TX[0] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] 0 H P H H F0 J M J K 9 N0 L M 0 L0 L N M J0 L0 N N 9 H J0 0 N M N F L0 PE_IROMP_R EXP_RI PIEN_RXN0 PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXP0 PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_TXN0 PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXP0 PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP R00 R % % 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 9.9Ohm PIE_RXN0 PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXP0 PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIEN_RXN[:0] 0 R00,R0,R0 near U00 PIEN_RXP[:0] 0 +VTT_PU For E request, to read PEI via E. onnection: R0.-->Q00.-->U00. R00 don't remove 0 H_PROHOT_# PIE_RXN[:0] 0 PIE_RXP[:0] 0 +VTT_PU,,,0,,,0 H_THRMTRIP# H_PURT# PM_YN# H_PUPWR H_RM_PWR H_VTTPWR H_PWR_XP UF_PLT_RT# % R00 % R00 9.9Ohm % R00 9.9Ohm % R00 H_OMP H_OMP H_OMP H_OMP0 TP_KTO# 9.9Ohm % R00 H_TERR# THRO_PU R0 H_PEI L00 00 R0 OHM L0 00 T00 L0 00 L09 00 H_PEI_IO H_PROHOT_#_R H_THRMTRIP#_R PM_YN#_R VPWROO R L00 00 T00 VPWROO_0_R L0 00 T00 VPWROO_R L0 00 T00 R0.KOhm % PLT_RT#_R T00 R09 % KTO#:pulled to ground on processor. may use to determine if PU is present U00 OMP 0 9 E M N N9 N N N0 M M Y M H Y0 OMP OMP OMP0 PRO_ETET TERR# PEI PROHOT# THERMTRIP# REET_O# PM_YN VPWROO_ VPWROO_0 M_RMPWROK VTTPWROO TPPWROO RTIN# Misc Thermal Power Management locks R Misc JT & MP LK LK# LK_ITP LK_ITP# PE_LK PE_LK# PLL_REF_LK PLL_REF_LK# M_RMRT# M_ROMP[0] M_ROMP[] M_ROMP[] PM_EXT_T#[0] PM_EXT_T#[] PRY# PREQ# TK TM TRT# TI TO TI_M TO_M R# PM#[0] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] LKREF LKREF# K K K J0 L J Y W J V P9 V0 V V R0 R LK_PU_LK LK_PU_LK# LK_ITP_LK_R LK_ITP_LK#_R LK_EXP_P LK_EXP_N LKREF LKREF# M_ROMP0 M_ROMP M_ROMP PM_EXTT# +VTT_PU RN00 0KOHM RN00 0KOHM U U9 T T009 N P9 T00 T9 XP_TI_R T XP_TO_R P XP_TI_M T0 XP_TO_M W J9 J J K K J K9 M9 H_R#_R N/ N/ R0 % R0 % R0 % L0 00 L0 00 R09 R00 00 L00 LK selection M_RMRT#, 0.9Ohm XP_PRY# XP_PREQ# XP_TLK XP_TRT# T0 T0 T0 T0 XP_O0 XP_O XP_O XP_O XP_O XP_O XP_O XP_O Main oard LK_ITP_LK LK_ITP_LK# LK_REF LK_REF# 0MHz from PH. PM_EXTT#0, T00 XP_TM XP_REET#, XP_O[:0] N0009 RMPWROK: (U R.) +.V LK_PU_P_PH LK_PU_N_PH L0 00 L0 00 LK_PU_LK LK_PU_LK# H_PURT# XP_TM R0 R0 +VTT_PU OHM Ohm VPWROO_R R00.KOhm % LK_MI_PH LK_MI#_PH L0 00 L0 00 LK_EXP_P LK_EXP_N XP_TI_R XP_PREQ# XP_TLK R0 R0 R0 Ohm Ohm Ohm R0.0KOHM % FI disable: (For discrete graphic). N: FI_TX#[0:],FI_TX[0:],FI_RX#[0:],FI_RX[0:] V_XENE,V_XENE. Pull-down to via K ± % resistor: FI_FYN[0:],FI_LYN[0:],FI_INT,FX_IMON ~mw power saving.( R0. P.0). onnected to : VX,. an be connected to directly: PLL_REF_LK,PLL_REF_LK#. onnect to +V.0 rail: VFIPLL FI_FYN0 KOhm R0 FI_FYN KOhm R0 FI_LYN0 KOhm R0 FI_LYN KOhm R0 FI_INT KOhm R0 R. P.: *FI_FYN[0],FI_FYN[], FI_LYN[0], FI_LYN[] can be ganged together with one resistor. *On the other hand,fi_fyn[0], FI_FYN[], FI_LYN[0], FI_LYN[], and FI_INT signals on PH side can be left as no connect without any power or functional impact. 0, PWRLIMIT# JT MPPIN XP_TI_R XP_TO_M XP_TI_M XP_TO_R H_PROHOT_# L0 00 R00 L0 R0 L0 00 RV-0 R.,item L0. Q00 N00 THRO_PU 0 XP_TI XP_TO XP_TRT# R0 Ohm dd test point for factory IT boundary scan. PU: (page) all# ignal Test Point LK T00 VTTPWROO T00 VPWROO_0 T00 VPWROO_ T00 RTIN# T00 TRT# T00 TK T009 TM T00 TI T0 TO T0 TI_M T0 TO_M T0 PH: (page 0,,) all# ignal Test Point JT_TK T0 JT_TM T0 JT_TI T0 JT_TO T0 JT_RT# T0 RMRT# T09 RTRT# T0 PWROK T0 MEPWROK T LN_RT# T LKIN_PILOOPK T INTVRMEN T09 Y_PWROK T RTRT# T00 UTeK OMPUTER IN. N Friday, pril 09, 00 ate: heet of 99.0

4 Main oard U00 U00 M Q[:0] M 0 M M M # M R# M WE# M Q0 T M Q T M Q M Q 9 M Q V M Q V M Q E M Q E M Q F M Q9 E M Q0 K M Q H M Q F9 M Q F M Q K M Q N M Q N M Q N9 M Q M Q9 K M Q0 K9 M Q M Q H M Q K M Q N0 M Q N M Q K M Q H M Q J0 M Q9 H M Q0 M Q M Q J0 M Q M M Q F M Q F M Q N0 M Q H M Q N M Q9 N M Q0 N M Q N M Q H M Q J M Q H M Q J M Q M M Q N M Q F M Q9 N M Q0 N M Q J M Q F M Q J M Q K M Q K M Q J M Q F M Q M Q9 M Q0 J M Q F M Q Y M Q 0 T H F K L F _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[9] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[9] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[9] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[9] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[9] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[9] _Q[0] _Q[] _Q[] _Q[] _[0] _[] _[] _# _R# _WE# R YTEM MEMORY _K[0] _K#[0] _KE[0] _K[] _K#[] _KE[] _#[0] _#[] _OT[0] _OT[] _M[0] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _Q#[0] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _M[0] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _M[9] _M[0] _M[] _M[] _M[] _M[] _M[] M P F0 K H K H0 J F L 0 J0 M N N H9 Y J N L H K P E Y J L N K H M0 E T P V N K J0 N0 F H H0 J F0 N N M M0 M M M M M M M M M M M M M M M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M Q0 M Q M Q M Q M Q M Q M Q M Q M 0 M M M M M M M M M 9 M 0 M M M M M M_LK_R0 M_LK_R#0 M_KE0 M_LK_R M_LK_R# M_KE M_#0 M_# M_OT0 M_OT M M[:0] M Q#[:0] M Q[:0] M [:0] M Q[:0] M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M 0 M M M # M R# M WE# W E Y F H R R J K U9 V0 R0 T T V V P V U P U9 V T P9 V9 V0 T0 T V V0 P9 T V V T P U T9 T P T U0 V9 V P0 R R R T N L9 J F0 K0 K 9 V V V U T0 T _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[9] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[9] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[9] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[9] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[9] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[9] _Q[0] _Q[] _Q[] _Q[] _[0] _[] _[] _# _R# _WE# R YTEM MEMORY - _K[0] _K#[0] _KE[0] _K[] _K#[] _KE[] _#[0] _#[] _OT[0] _OT[] _M[0] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _Q#[0] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _M[0] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _M[9] _M[0] _M[] _M[] _M[] _M[] _M[] U V T V U9 T P T V U9 L T P V V U F E M U T9 T V U 9 N V T T0 U V J9 T P0 V9 U0 V T T P V T U U T9 T V U M M0 M M M M M M M M M M M M M M M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M Q0 M Q M Q M Q M Q M Q M Q M Q M 0 M M M M M M M M M 9 M 0 M M M M M M_LK_R M_LK_R# M_KE M_LK_R M_LK_R# M_KE M_# M_# M_OT M_OT M M[:0] M Q#[:0] M Q[:0] M [:0] N0009 N0009 UTeK OMPUTER IN. N Friday, pril 09, 00 ate: heet of 99.0

5 F strapping information: F[:0]: PI Express Port ifurcation:(larksfield Only) - = x PE (efault) - 0 = x PE F[]: PIE tatic Numbering Lane Reversal.(uburndale Only) - :Normal Operation (efault) - 0:Lane Numbers Reversed -> 0, ->,... F[]: Embedded isplayport etection.(uburndale Only) - :isabled - No Physical isplay Port attached to Embedded isplayport - 0:Enabled - n external isplay Port device is connected to the Embedded isplay Port F[]: Fixed for PI Express.0 jitter specifications.(larksfield) larksfield (only for early samples pre-e) - onnect to with.0k Ohm/% resistor For a common motherboard design (for U and F), the pull-down resistor should be used. oes not impact U functionality. Unmount if Intel has fixed this issue. Note: (uburndale)hardware traps are sampled on the asserting edge of VPWROO_0 and VPWROO_ and latched inside the processor. Note: (larksfield)hardware traps are sampled after RTIN# de-assertion. F0 F F F T0 T0 T0 T0 T09 T0 T0 T0 T0 T00 T0 T0 T0 T0 T09 T0 T00 T09 R0 R0 R0 R0 R.,item F0 F F F F F F F F F9 F0 F F F F F F F T0 T0 % %.0KOHM.0KOHM R0 R0 T0 T0 % %.0KOHM.0KOHM L M K K K J T F H E F F U T T U V V W0 Y E F ep=.k P U00E F[0] F[] F[] F[] F[] F[] F[] F[] F[] F[9] F[0] F[] F[] F[] F[] F[] F[] F[] RV_TP[] RV RV RV RV RV9 RV0 RV RV RV RV RV RV Intel sighting #: 00(9) To drive a value of zero on F[0] pin use a 0 Ohm pull down resistor to Vss. RV_NTF[] RV_NTF[] RV_NTF[] RV_NTF[] REERVE VP0_ENE VP0_V_ENE RV RV_TP[] RV_TP[] RV RV RV9 RV_NTF[] RV_TP[] RV_NTF[] RV_NTF[] RV RV RV RV RV9 RV0 RV RV RV RV RV RV RV RV RV_TP[] RV_TP[] RV RV RV RV _TET_V _TET_V9 _TET_V _TET_V _TET_V _TET_V _TET_T _TET_T9 _TET_T _TET_T _TET_R _TET_R _TET_E _TET_E _TET TET_9 _TET TET TET_9 _TET TET_ W W 9 9 R R T R V V V9 K N9 P H K R M K9 U T0 R9 U9 T P N V U E9 E V V9 V V V V T T9 T T R R E E 9 9 T00 T00 T00 T00 T00 T0 T00 T009 R00 R0 H_TP TET_V_V9 H_TP TET_V_T H_TP TET_V_T H_TP TET_T_T9 H_TP TET H_TP TET_9_9 U00I U V U V U V U V U V U V U V U V U V9 U V0 U V U V U V U V P V N V N V M0 V M V9 M V0 M V M V M V L V L V L V L0 V L V L0 V9 K V0 K0 V K V K V K0 V J V J V J9 V J V H0 V9 H V0 H V H V H V H0 V H V V V F V F0 V9 F V0 F V E0 V E V E9 V E V V V 0 V V9 V0 9 V V V V V V 0 V V V9 9 V0 V V 0 V Y V Y V Y V Y9 V Y V Y V9 Y V0 R V0 R9 V R V R V R V R0 V R V R V R V R V9 R V0 R9 V R V R V R V R V R V P0 V P V N V9 N V0 Y V Y V Y V Y V Y V Y V Y0 V Y V Y V9 N0009 V Y V90 Y V9 Y V9 Y9 V9 Y V9 Y V9 Y V9 Y V9 Y V9 Y V99 W V00 W V0 W9 V0 W V0 W V0 W V0 W V0 W V0 W V0 V9 V09 V V0 U0 V U V U V U V U0 V U V U V U9 V U V9 U V0 U V U0 V U V U V U V U V U V U9 V U V9 U V0 U V U V T V T0 V R V R V R V R0 V R V9 N V N V N V N V N V N V N V M V M V9 L V0 L V L V L V L V L V L V L V L V L V9 K0 V0 K V K V K V K V K V K V K V K V K0 V9 K V90 K V9 K V9 K V9 K V9 K9 V9 K V9 K V9 J0 V9 H V99 H V00 H V0 V V0 V V0 T V0 R9 V0 R V0 R V0 N V0 N V09 L V0 L V R V H V F V E9 V E V V V E V9 V0 U00J H V0 H V0 H0 V0 H V0 H V0 H V0 H V0 H V09 H9 V0 H V H V H V H V H0 V H V H V H V H V9 H V0 H9 V H V H V H V V 9 V V F9 V F V9 F V0 E0 V E V V V V 0 V V V V9 V0 V 0 V V V 0 V V V V 0 V9 V0 V 9 V V V V V 0 V V V9 V0 V V 9 V V V V 9 V V V9 V0 V V 0 V V V 9 V V V V9 V0 0 V V V V V V 9 V F0 V F V E V E V E0 V E V9 E V0 V V V V V V 0 V V V9 0 V90 V9 V9 0 V N0009 V V0 V0 V0 V0 V0 V09 V0 V V V V9 V9 V9 V9 V9 V9 V99 V00 V0 V0 V0 V V9 V90 V9 V9 V9 V9 V9 V9 V9 V9 V99 V00 V0 V0 V0 V0 V0 V0 V0 V0 V09 V0 V V V V V V V V V9 V0 V V V V V V V V V9 V0 V V V V V V V V V9 V0 V V V V V V V V V9 V0 V V V V V V V V V9 V0 V V V V V V V V V9 V0 V V V W9 W W W W0 W W W W V0 U U U U U0 U U U9 U9 U T R0 R R R R0 R R R P N N N N0 N N0 N N M M M M L0 L L L L K K K K K K K K K K K J J J J J0 J9 H H H H F F F F Main oard N0009 UTeK OMPUTER IN. N Friday, March, 00 ate: heet of 99.0

6 ULV Max. +VORE U00H F V_ F V_ F V_ F V_ F0 V_ F V_ F V_ F V_ F V_9 F V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_9 V_0 V_ V_ V_ V_ V_ W V_ W V_ W V_ W V_9 W V_0 U V_ U V_ U V_ U V_ U V_ R V_ R V_ R V_ R V_9 R V_0 P0 V_ N V_ N V_ N V_ N V_ N V_ M0 V_ M V_ M V_9 L V_0 K0 V_ K V_ K V_ J V_ H0 V_ H V_ H V_ 0 V_ V_9 V_0 V_ F V_ E0 V_ E V_ E V_ E0 V_ E V_ E V_ 9 V_9 V_0 V_ V_ V_ 0 V_ V_ V_ V_ V_ 0 V_9 V_0 V_ 9 V_ V_ V_ V_ V_ 0 V_ V_ V_9 POWER PU ORE UPPLY VP0_ VP0_ VP0_ VP0_ VP0_ VP0_ VP0_ VP0_ VP0_9 VP0_0 VP0_ VP0_ VP0_ VP0_ VP0_ VP0_ VP0_ VP0_ VP0_9 VP0_0 VP0_ VP0_ VP0_ VP0_ VP0_ VP0_ VP0_ VP_ VP_ VP_ VP_ VP_ VP_ VP_ VP_ VP_9 VP_0 VP_ VP_ VP_ VP_ VP_ VP_ VP_ VP_ VP_9 VP_0 VP_ VP_ VP_ VP_ VP_ VP_ VP_ Y Y Y0 W W W0 U U U R R R N N N0 L L L0 K K K0 Y Y Y9 W W W9 U U U R R R N N N9 L L L9 K K K9 +VP0 +VP dd Jumper to measure power? UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 09 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 +VFX_ORE U00 N VX N0 VX VX_ENE N VX VX_ENE N VX N VX N VX N VX N9 VX FX_VI[0] L VX9 FX_VI[] L0 VX0 FX_VI[] L VX FX_VI[] L VX FX_VI[] L VX FX_VI[] L VX FX_VI[] L VX L9 VX R0.,P K VX FX_VR_EN K VX FX_PRLPVR J0 VX9 FX_IMON H VX0 H VX F VX VQ F VX VQ F VX VQ F VX VQ F VX VQ F9 VX VQ F VX VQ F VX9 VQ F VX0 VQ9 VX VQ0 VX VQ VX VQ VX VQ VX VQ 9 VX VQ +VTT_PU VX VQ VQ ULV VQ W VTT_ VQ9 W9 VTT_ VQ0 U VTT_ VQ U9 VTT_ VQ U VTT_ VQ U VTT_ VQ U VTT_ VQ U VTT_ VQ R VTT_9 VQ R9 VTT_0 VQ R VTT_ VQ9 R VTT_ VQ0 VQ VQ +VP VQ VQ VQ K VP_ VQ K0 VP_ K9 VP_ H0 VP_ VTT0_R H9 VP_ VTT0_R[] F0 VP_ VTT0_R[] F9 VP_ VTT0_R[] 0 VP_ VTT0_R[] 9 VP_9 VTT0_R[] 0 VP_0 VTT0_R[] 9 VP_ VTT0_R[] 0 VP_ VTT0_R[] 9 VP_ VTT0_R[9] W0 VP_ W9 VP_ VTT_ U0 VP_ VTT_ U9 VP_ VTT_ R0 VP_ VTT_ R9 VP_9 VTT_ VTT_ VTT_ VTT_9 VTT_0 UF/.V 0 UF/.V 09 UF/.V 0 0UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 09 0UF/.V 00 UF/.V 090 0UF/.V 0 N0009 RPHI PE & MI POWER ENE LINE RPHI VIs R -.V RIL F F0 F 0 H N M M0 H9 L L9 U0 U U N M L0 J H H F F W W0 W W W W W W9 W W W W W W VR_VI0 VR_VI VR_VI VR_VI VR_VI VR_VI VR_VI V_X_ENE V_X_ENE R00 VR_PWR_MON VR_VI[0:] R00 FX_VRON_EN L00 FXVR_PRLPVR_R 00 VR_PWR_MON UF/.V 0 0 0UF/.V 09 0UF/.V R00 UF/.V 0 UF/.V 0 0 0UF/.V 09 UF/.V UF/.V UF/.V R009.KOhm UF/.V 0 UF/.V 0 +VTT_PU FX_VR 0 R00 0KOhm UF/.V 0 R.,P xbuck tuffing option +VTT_PU KOhm T0 +VTT_PU Main oard FXVR_PRLPVR +.V R.,item FX_VR_ON 0, R00:Itel hecklist recommendation 0UF/V E00 PNONI/EEFX0XE ER=mOhm/Ir= R0 0KOhm N0009 UTeK OMPUTER IN. N Friday, pril 09, 00 ate: heet of 99.0

7 +VTT_PU UF/.V 0 UF/.V 0 UF/.V 09 UF/.V 0 0UF/.V 00 UF/.V 0 0UF/.V 00 ULV UF/.V 0 0UF/.V 00 UF/.V 0 0UF/.V 00 UF/.V 0 UF/.V 09 0.UF/V 0 0.UF/V 0 0.UF/V 09 U00F W VTT0_ W VTT0_ U0 VTT0_ U9 VTT0_ U F L00 VTT0_ PI# PM_PI# 0 R0 00 VTT0_ R9 VTT0_ VI[0] VR_VI0 0 R VTT0_ VI[] VR_VI 0 N0 VTT0_9 VI[] VR_VI 0 N9 VTT0_0 [0]/VI[] VR_VI 0 N VTT0_ []/VI[] VR_VI 0 N VTT0_ []/VI[] VR_VI 0 N VTT0_ VI[] VR_VI 0 N VTT0_ N N H_VTTVI VTT0_ VTT_ELET N VTT0_ M0 PM_PRLPVR_R VTT0_ PRO_PRLPVR F L00 L0 00 VTT0_ L9 VTT0_9 L VTT0_0 L VTT0_ L VTT0_ L I_MON_PU L00 VTT0_ IENE K 00 VTT0_ K VTT0_ F9 VTT0_ F VTT0_ F VTT0_ F VENE_R VTT0_9 V_ENE F F VENE_R VTT0_0 V_ENE F F0 VTT0_ 9 VTT0_ F0 VTT_ENE VTT0_ VTT_ENE N T00 F9 VTT0_ 0 R TP_V_ENE_VTT T00 VTT0_ V_ENE_VTT 9 VTT0_ 0 VTT0_ 9 VTT0_ Y0 VTT0_ W0 VTT0_ W VTT0_9 W VTT0_0 VTT0_ VTT0_ VTT0_ VTT0_. 0 VTT0_ W +.V_PLL +.V VTT0_ W R0 VTT0_9 W W9 VTT0_0 VPLL W0 W r0 VTT0_ VPLL W U VTT0_ VPLL W R9 VTT0_ VPLL W R VTT0_ VPLL W VTT0_ U VTT0_ U VTT0_ U VTT0_ U0 VTT0_9 U VTT0_0 U VTT0_ U VTT0_ U VTT0_ R VTT0_ 0. R VTT0_ R +.V_RLK +.V VTT0_ L00 R0 VTT0_ R VTT0_ VQ_K[] R 00 VTT0_9 VQ_K[] R VTT0_0 R VTT0_ Y0 VTT0_ N9 VTT0_ N0009.V RIL POWER PU VI ENE LINE POWER.V UF/.V 00.UF/.V 0 UF/.V 0 VTT_TET T T00 I_MON 0 PM_PRLPVR 0 +VORE R00 0 % R00 0 % VENE 0 VENE 0 Main oard +VTT_PU PU XP connector J00 IE IE 0 FP_ON_0P PUPWR_XP HPM# T0 HPM# T0 HPM# T0 HPM0# T09 Ohm R0 XP_RT#_R T00 T0 L00 00 KOhm R00 KOhm R00 H_PWR_XP XP_TRT# H_PUPWR, XP_PREQ# XP_PRY# XP_TO XP_TI XP_TM XP_TLK XP_REET#, H_PURT# M_T_,, M_LK_,, LK_ITP_LK# LK_ITP_LK () () (9) ( ) ( ) () () () () () () () (0) () +VTT_PU XP_RT#_R R0 UF_PLT_RT#,,0,,,0 T0 T0 T0 T0 T0 T0 T0 T09 XP_O0 XP_O XP_O XP_O XP_O XP_O XP_O XP_O T00 PM_PWRTN#_R J00 FF path UTeK OMPUTER IN. N Put these test point near J00. Put it away from the FF path. Friday, pril 09, 00 ate: heet of 99.0

8 UTeK OMPUTER IN. N ustom ate: Tuesday, March 0, 00 heet of 99.0

9 Main oard UTeK OMPUTER IN. N ustom ate: Tuesday, March 0, 00 heet 9 of 99.0

10 Main oard UTeK OMPUTER IN. N ustom ate: Tuesday, March 0, 00 heet 0 of 99.0

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12 Main oard UTeK OMPUTER IN. N ustom ate: Tuesday, March 0, 00 heet of 99.0

13 Main oard UTeK OMPUTER IN. N ustom ate: Tuesday, March 0, 00 heet of 99.0

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16 M M M M M M M M M M M M M M M M0 M Q M Q# M Q M Q M Q M Q# M Q M Q# M Q# M Q M Q# M Q#0 M Q M Q# M Q0 M Q# M M M M M 9 M M 0 M M M M M 0 M M M M Q M Q M Q M Q0 M Q M Q M Q M Q M Q9 M Q0 M Q9 M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q0 M Q M M Q9 M Q M Q M Q M Q M Q M Q9 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q9 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M [:0] M Q[:0] M_LK_R0 M_KE0 M_LK_R# M_LK_R M_KE M # M_LK_R#0 M M 0 M M M[:0] M Q#[:0] M Q[:0] M_T_,, M_LK_,, M WE# PM_EXTT#0, M_# M R# M_#0 M_OT0 M_OT M_RMRT#, +V +.V +0.V M_VREF_IMM0 M_VREFQ_IMM0 +0.V +.V ate: heet of Friday, pril 09, 00 UTeK OMPUTER IN. N.0 99 ate: heet of Friday, pril 09, 00 UTeK OMPUTER IN. N.0 99 ate: heet of Friday, pril 09, 00 UTeK OMPUTER IN. N.0 99 REV 9.mm Mus lave ddress: 0H Layout Note: Place these caps near O IMM 0 Layout Note: Place these caps near O IMM 0 R. R. 0 WP WP WP WP WP WP WP R.0 update Footprint R.0 update Footprint R0 R0 0 0.UF/V 0 0.UF/V 0 0UF/.V 0 0UF/.V 0UF/.V 0UF/.V 0 0.UF/V 0 0.UF/V 0 0.UF/V 0 0.UF/V.UF/0V.UF/0V 0 0UF/.V 0 0UF/.V 0UF/.V 0UF/.V 0 0.UF/V 0 0.UF/V 0.UF/V 0.UF/V UF/.V UF/.V R0 0KOhm R0 0KOhm 09 0UF/.V 09 0UF/.V UF/.V UF/.V 9 UF/.V 9 UF/.V UF/.V UF/.V.UF/0V.UF/0V 0.UF/V 0.UF/V EVENT# N N NP_N 0 NP_N 0 OT0 OT 0 R# 0 REET# 0 #0 # L 0 00 TET V V0 00 V 0 V 0 V V V V V V V V V V V V 9 V 9 V9 99 VP 99 VREF VREFQ V9 V 0 V 9 V V 9 V 9 V0 90 V V9 9 V V V 9 V V V V V V0 V 9 V9 V V V V 0 V V V 9 V V0 V V9 V V V V V V V V 0 V0 V V9 V 9 V V V V V V V V0 V VTT 0 VTT 0 WE# J0 R_IMM_0P J0 R_IMM_0P /P 0 /# # K#0 0 K# 0 K0 0 K 0 KE0 KE M0 M M M M M M 0 M Q0 Q Q0 Q Q Q Q Q Q 9 Q Q Q9 Q Q0 0 Q Q 0 Q Q Q 9 Q Q 9 Q Q9 Q Q0 Q 0 Q 9 Q Q Q Q 0 Q Q 0 Q9 Q Q0 Q 9 Q Q 9 Q Q Q Q 0 Q Q9 Q Q0 Q Q Q Q Q Q Q Q 9 Q9 9 Q Q0 0 Q Q 9 Q 9 Q Q Q9 Q#0 0 Q# Q# Q# Q# Q# Q# 9 Q# Q0 Q 9 Q Q Q Q Q Q J0 R_IMM_0P J0 R_IMM_0P R0 0KOhm R0 0KOhm 0.UF/V 0.UF/V 0UF/.V 0UF/.V.UF/0V.UF/0V

17 M M M M M M M M M M M M0 M Q# M Q M Q M Q M Q M Q# M Q# M Q#0 M Q M Q# M Q0 M Q# M M M M M 9 M M 0 M M M M M 0 M M M M Q9 M Q M Q M Q M Q M Q M Q M Q M Q M M Q M Q M Q0 M Q M Q9 M Q M Q M Q M Q M Q M Q M Q0 M Q9 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q9 M Q M Q M Q M Q M Q0 M Q9 M Q M Q M Q M Q M M M M M Q M Q M Q# M Q# M Q M Q9 M Q M Q0 M Q M Q M Q M Q M WE# M_# M_LK_R M_KE M_LK_R# M_LK_R M_KE M # M R# M_LK_R# M_# M_OT M_OT M_T_,, M_LK_,, M M[:0] M Q#[:0] M Q[:0] M M 0 M M_RMRT#, M [:0] M Q[:0] PM_EXTT#0, +0.V +0.V +.V M_VREF_IMM M_VREFQ_IMM +.V +V +V ate: heet of Friday, pril 09, 00 UTeK OMPUTER IN. N.0 99 ate: heet of Friday, pril 09, 00 UTeK OMPUTER IN. N.0 99 ate: heet of Friday, pril 09, 00 UTeK OMPUTER IN. N.0 99 Mus lave ddress: H Layout Note: Place these caps near O IMM Layout Note: Place these caps near O IMM T.mm R. R. WP WP WP WP WP R.0 update Footprint R.0 update Footprint 0UF/.V 0UF/.V 0.UF/V 0.UF/V.UF/0V.UF/0V.UF/0V.UF/0V UF/.V UF/.V 9 UF/.V 9 UF/.V UF/.V UF/.V UF/.V UF/.V 0UF/.V 0UF/.V R0 0KOhm R0 0KOhm R0 0KOhm R0 0KOhm 0.UF/V 0.UF/V 0 0.UF/V 0 0.UF/V 0 0UF/.V 0 0UF/.V 0 0.UF/V 0 0.UF/V /P 0 /# # K#0 0 K# 0 K0 0 K 0 KE0 KE M0 M M M M M M 0 M Q0 Q Q0 Q Q Q Q Q Q 9 Q Q Q9 Q Q0 0 Q Q 0 Q Q Q 9 Q Q 9 Q Q9 Q Q0 Q 0 Q 9 Q Q Q Q 0 Q Q 0 Q9 Q Q0 Q 9 Q Q 9 Q Q Q Q 0 Q Q9 Q Q0 Q Q Q Q Q Q Q Q 9 Q9 9 Q Q0 0 Q Q 9 Q 9 Q Q Q9 Q#0 0 Q# Q# Q# Q# Q# Q# 9 Q# Q0 Q 9 Q Q Q Q Q Q J0 R_IMM_0P J0 R_IMM_0P 0 0.UF/V 0 0.UF/V RX0 RX0 09 0UF/.V 09 0UF/.V 0 0.UF/V 0 0.UF/V 0.UF/V 0.UF/V EVENT# N N NP_N 0 NP_N 0 OT0 OT 0 R# 0 REET# 0 #0 # L 0 00 TET V V0 00 V 0 V 0 V V V V V V V V V V V V 9 V 9 V9 99 VP 99 VREF VREFQ V9 V 0 V 9 V V 9 V 9 V0 90 V V9 9 V V V 9 V V V V V V0 V 9 V9 V V V V 0 V V V 9 V V0 V V9 V V V V V V V V 0 V0 V V9 V 9 V V V V V V V V0 V VTT 0 VTT 0 WE# J0 R_IMM_0P J0 R_IMM_0P.UF/0V.UF/0V 0UF/.V 0UF/.V 0UF/.V 0UF/.V

18 alpella larksfield R O-IMM VREFQ Platform esign uide hange etails R Vref Intel ocument Number: 00 +.V M_VREF_R efault M R0 KOhm R.0_Item:9 L09 00 For R_VREF command & address. M_VREF_IMM0 L0 00 Near J0<000 mil 0.UF/V KOhm R0 +.V R L0 00 R.0_Item:9 M_VREF_IMM R KOhm L0 00 M_VREFQ_IMM0 L0 M_VREFQ_IMM 00 LR0 00 Near J0<000 mil 0 0.UF/V KOhm R +V +.V 0 0.UF/V R 0KOhm R 0KOhm + - U0 V+ V- LMVIVR 0 0.UF/V UTeK OMPUTER IN. N Tuesday, March 0, 00 ate: heet of 99.0

19 UTeK OMPUTER IN. N ustom ate: Tuesday, March 0, 00 heet 9 of 99.0

20 RT battery R.,item L +V +V_RT JP00 +RTT 00 +V_RT R00 MM_OPEN_MIL +RT_T KOhm TW 00 UF/.V +V_RT RTRT# R delay should be ms~ms R00 0KOhm % 00 UF/.V JRT00 L_JUMP MO ettings lear MO Keep MO Request by for MO clear function JRT00 hunt Open (efault) 00 PF/0V R.,item X00.Khz R00 0MOhm U00 R00 0KOhm % R00 MOhm Z_LK_U Z_YN_U Z_RT#_U Z_OUT_U TPM ettings lear ME RT Registers Keep ME RT Registers trap information: 00 UF/.V JRT00 hunt Open (efault) H_PKR: No reboot strap Low: isable. High:Enable JRT00 L_JUMP H_YN: elect VVRM.V or.v RN0 OHM RN0 OHM RN0 OHM RN0 OHM H_OK_EN# H_OK_EN#:.Flash descriptor security: ampled low: override ampled high: in effect..pio low on the rising edge of PWROK, Will also disable Intel ME. Z_LK Z_YN Z_RT# Z_OUT R0 KOhm 0 PH_PI_OV +VU_OR R.,item +VU_OR +V R.,item L +VU_OR XRT L R00: For Xtal measurement PF/0V T0 R.,item L PH_JT_TO PH_JT_TM PH_JT_TI +V H_OK_EN# PI_LK PI_#0 0 esign uide R. Update: page9 +VM_PI PIO: R.,item L This signal should be only asserted low through an external KOhm pull-down in manufacturing or debug environments ONLY. MoW0 IbexPeak JT requirements: Without connecting PIO, customers may not be able to override PI flash contents. tuff for pre-production R0 0 % R0 0 % R0 0 % R0 0 % R00 0KOhm R09 KOhm R0 0 % R09 0 % Q00 N00 T0 PI_I +VU_OR R00 KOhm R0 KOhm R00 0KOhm % +V_RT PH_JT_RT# R0 0KOhm % R0 Z_IN0_U T00 T00 PH_JT_TK PH_JT_TM PH_JT_TI PH_JT_TO PH_JT_RT# R00 T00 T0 T00 T0 H_OK_RT# Ohm PI_O PH_JT_TK T0 T0 X_RT X_RT RTRT# RTRT# M_INTRUER# 0KOhm T09 T0 T0 T0 Z_OUT _PI0# _PI# Z_LK Z_YN Z_RT# Z_IN_M R0 Ohm 0 9 P 0 0 F0 E F 9 H J0 M K K J J V Y Y V RTX RTX RTRT# RTRT# INTRUER# INTVRMEN H_LK H_YN PKR H_RT# H_IN0 H_IN H_IN H_IN H_O H_OK_EN#/PIO H_OK_RT#/PIO JT_TK JT_TM JT_TI JT_TO JT_RT# PI_LK PI_0# PI_# PI_MOI PI_MIO IEXPEK-M PI_LK 0 PF/V RT IH PI JT T PI_#0 0 PF/V LP FWH0/L0 FWH/L FWH/L FWH/L FWH/LFRME# LRQ0# LRQ#/PIO T0RXN T0RXP T0TXN T0TXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TIOMPI TLE# T0P/PIO TP/PIO9 PI_I ERIRQ TIOMPO 0 PF/V F 9 K K K K9 H H H9 H F F9 F F H H F F 9 F F T Y9 V PI_O 0 PF/V PH_RQ#0 LP_RQ# T0P TP T_OMP LP_0 0, LP_ 0, LP_ 0, LP_ 0, LP_FRME# 0, T00 T00 INT_ERIRQ 0 T_RXN0 T_RXP0 T_TXN0 T_TXP0 T,: E.0: T port,port may not be available in all PH KUs..Ohm % R00 +VTT_PH_VIO T_LE# MoW IbexPeak JT requirements: E Enable:Mount R0,R0,R0,R0,R00,R0,R0. NI R0,R09. (TO) E isable:mount R00,R0,R0. NI: others. INT_ERIRQ T0P TP 0KOhm R0 0KOhm R0 0KOhm R0 +V PI_MOI: itpm strap. Mount R0: Enable Unmount R0: isable(default) E Mount :R0,R0,R0,R0,R0,R09,R00,R0,R0. UTeK OMPUTER IN. N.0 Friday, pril 09, 00 ate: heet of 0 99

21 U00 PIE: TV turner PIE: WLN PIE: Newcard PIE: U.0 PIE: PIE--> PIE: LN PIE_RXN_MINIR PIE_RXP_MINIR PIE_TXN_MINIR PIE_TXP_MINIR PIE_RXN_U PIE_RXP_U PIE_TXN_ PIE_TXP_ PIE_RXN_LN PIE_RXP_LN PIE_TXN_LN PIE_TXP_LN LK_PIE_MINIR# LK_PIE_MINIR 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V PIE_TXN_WLN PIE_TXP_WLN PIE_TXN_U PIE_TXP_U PIE,: E.0: port,port may not be available in all PH KUs. T0 0 0 L0 00 L0 00 X0 X0 PIE_TXN_LN PIE_TXP_LN LK_REQ0# LKREQ_TV# LK_PH_R_N LK_PH_R_P LKREQ_WLN# 0 J0 F9 H9 W U0 T0 U V E F H J W T U U V J J K K P9 M M U M M N PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP LKOUT_PIE0N LKOUT_PIE0P PI-E* PIELKRQ0#/PIO LKOUT_PIEN LKOUT_PIEP PIELKRQ#/PIO LKOUT_PIEN LKOUT_PIEP PIELKRQ#/PIO0 Mus From LK UFFER ontroller PE Link MLERT#/PIO MLK MT ML0LERT#/PIO0 ML0LK ML0T MLLERT#/PIO MLLK/PIO MLT/PIO L_LK L_T L_RT# PE LKRQ#/PIO LKOUT_PE N LKOUT_PE P LKOUT_MI_N LKOUT_MI_P LKOUT_P_N/LKOUT_LK_N LKOUT_P_P/LKOUT_LK_P LKIN_MI_N LKIN_MI_P LKIN_LK_N LKIN_LK_P LKIN_OT_9N LKIN_OT_9P LKIN_T_N/K_N LKIN_T_P/K_P 9 H J M E0 T T T9 H N N T T W P P F E H H ML0LERT# MLLERT# ML_LK ML_T LKREQ_PE#_R LK_PIE_PE#_PH_L LK_PIE_PE_PH_L T0 T T T0 L 00 L 00 EXT_I# 0 L ML_LK ML_T L_LK L_T L_RT# LK_MI#_PH LK_MI_PH LK_REF# LK_REF LK_MI# 9 LK_MI 9 LK_PH_LK# 9 LK_PH_LK 9 LK_OT9# 9 LK_OT9 9 LK_T# 9 LK_T 9 To HVL To E LK_PIE_PE#_PH 0 LK_PIE_PE_PH 0 EXT_I# ML0LERT# L ML_LK ML_T MLLERT# 0KOhm R0 0KOhm R.KOhm R.KOhm R.KOhm R.KOhm R 0KOhm R +VU_OR R.,page : The pull-up resistor value for ML0T and ML0LK has been updated from. K ±% to. K ±% to support 00-kHz bus speed H H LKOUT_PIEN LKOUT_PIEP REFLKIN P LK_IH 9 LK_PIE_U#_PH LK_PIE_U_PH LKREQ_U# LK_PIE_LN# LK_PIE_LN L L L9 T Note: Place these resisters near to PIe lots L0 00 L 00 LKREQ_NEWR# PIELKRQ#/PIO LK_PH_R_N M LK_PH_R_P LKOUT_PIEN M LKOUT_PIEP LK_REQ#_U M9 PIELKRQ#/PIO J0 LKOUT_PIEN J LKOUT_PIEP LK_REQ# H PIELKRQ#/PIO LK_PH_PE_N K LK_PH_PE_P LKOUT_PE N K LKOUT_PE P LKREQ_LN# P PE LKRQ#/PIO IEXPEK-M lock Flex LKIN_PILOOPK XTL_IN XTL_OUT XLK_ROMP LKOUTFLEX0/PIO LKOUTFLEX/PIO LKOUTFLEX/PIO LKOUTFLEX/PIO J H X_IN H X_OUT F XLK_OMP T LK_OUT0 P LK_OUT T LK_OUT N0 LK_OUT T R 90.9Ohm % T T T R9 0PF/0V R 0PF/0V 9 LK_PI_F +VTT_PH_OR.OHM Ohm R.,item 9 0 PF/0V R X0 MOhm Mhz R0 XOUT 0 PF/0V R0: For Xtal measurement LK_U_U0 LK_R_REER_ PH LKREQ etting: R.,item L Not connected to device. +VU_OR LK_REQ0# R 0KOhm LK_REQ# R 0KOhm +VU_OR onnected to device. efault : lock free run. (P 0K). Reserver 0K PU for power saving purpose. +V R9 KOhm LKREQ_TV# LKREQ_WLN# R 0KOhm R 0KOhm +VU_OR, PU_PWROK Q0 N00 +V R LKREQ_PE#_R LKREQ_NEWR# LKREQ_LN# LK_REQ#_U LKREQ_TV# LKREQ_WLN# LKREQ_NEWR# LKREQ_LN# LK_REQ#_U LKREQ_PE#_R R R R R.,item L R.,item L R 0KOhm R 0KOhm R 0KOhm R 0KOhm R 0KOhm R9 0KOhm R.,item L 0KOhm 0KOhm 0KOhm 0 LKREQ_PE# Q0 N00 LKREQ_PE#_R UTeK OMPUTER IN. N.0 Friday, pril 09, 00 ate: heet of 99

22 pre-e not support Reversal Feature R.,page 9: UXPWROK_R R 0KOhm For platforms that do not support Intel LN, LN_RT# should be pulled down to ground via a. k to 0 k pull-down resistor. PM_LKRUN# R.KOhm +V +V +VTT_PH_OR R0 9.9Ohm % MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_OMP U00 MI0RXN J MIRXN W0 MIRXN J0 MIRXN MI0RXP MIRXP 0 MIRXP 0 MIRXP E MI0TXN F MITXN 0 MITXN E MITXN MI0TXP H MITXP 0 MITXP MITXP H MI_ZOMP F MI_IROMP MI FI FI_RXN0 FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXP0 FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_INT FI_FYN0 FI_FYN FI_LYN0 H J E F W J F H J FI_TXN0 FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXP0 FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_INT FI_FYN0 FI_FYN FI_LYN0 FI_LYN FI_LYN R.,item L KOhm R +V R 0KOhm T PM_RI# PM_TLOW# PIE_WKE# /9 NI ME_usPwrnck R 0KOhm R.KOhm R KOhm R0 0KOhm +VU_OR, XP_REET# E.0: Intel LN Enabled : LN_RT# connected to the same source as MEPWROK isabled : LN_RT# must be grounded R Y_REET# 0, LL_YTEM_PWR R 0,,0 VRM_PWR R PM_PWROK_PH H_RM_PWR isabled : LP_LN#-->N. PM_RMRT#_PH P. isabled : VLN connected to. 0 ME_usPwrnck PM_PWRTN#_R 0 PM_PWRTN# ME PREENT_PH L 00 L 00 T0 L MPWROK_R 00 T UXPWROK_R T L PM_RMRT#_R 00 T09 L 00 T M K 0 9 M P P Y_REET# Y_PWROK PWROK MEPWROK LN_RT# RMPWROK RMRT# U_PWR_K/PIO0 PWRTN# PREENT/PIO ystem Power Management WKE# LKRUN#/PIO U_TT#/PIO ULK/PIO LP_#/PIO LP_# LP_# LP_M# TP J Y P F E H P K N PM_U_TT# U_LK LP_# LP_#_R L0 00 LP_#_R L0 00 LP_M#_R PM_LP_W# T0 T0 T0 T T0 PIE_WKE# PM_LKRUN# 0 PM_U# 0 PM_U# 0 T0 PM_TLOW# TLOW#/PIO PMYNH J0 PM_YN# T0 PM_RI# F RI# LP_LN# F ME_PM_LP_LN#_PH T IEXPEK-M R.,item L 09'MoW0: Optional if ME FW is Ignition FW 0KOhm R +VU_OR 0KOhm R 0KOhm R Power failure solution (0-->,-->): PM_PWROK,PM_RMRT#: previous platform solution. ME_PWROK,ME PREENT: reserved for test. PM_PWROK_PH PM_RMRT#_PH ME PREENT_PH R9 0KOhm 0 PT R0 0KOhm 0 PT R 0KOhm 0 PT PM_PWROK 0 PM_RMRT#,0 ME PREENT 0 0 0: Prevent E drive hign, U_PWR sink low in -->. TW U_PWR 0,, 0 0KOhm R9 TW UTeK OMPUTER IN. N Friday, pril 09, 00 ate: heet of 99.0

23 +V L_TRL_LK L_TRL_T RN 0KOHM RN 0KOHM P_HP: Vil max=0.v, Vih min=v U00 EI_LK_PH EI_T_PH RN.KOhm RN.KOhm L_KEN L_V_EN L_KLTTL_PH EI_LK_PH EI_T_PH T0 T0 L_TRL_LK L_TRL_T T T Y Y V L_KLTEN L_V_EN L_KLTTL L LK L T L_TRL_LK L_TRL_T VO_TVLKINN VO_TVLKINP VO_TLLN VO_TLLP VO_INTN VO_INTP J J F H LV isable: (For discrete graphic). N: LV_T [:0], LV_T# [:0], LV_LK, LV_LK#, LV_T [:0], LV_T# [:0], LV_LK, LV_LK# L_V_EN, L_KLTEN, L_KLTTL, LV_VREFH LV_VREFL, LV_I, LV_V. onnected to : VccLV,VccTX_LV LV_LLKN_PH LV_LLKP_PH LV_L0N_PH LV_LN_PH LV_LN_PH LV_L0P_PH LV_LP_PH LV_LP_PH R R0.KOHM % R0 L 00 R P9 P T T V V Y V 0 Y9 V P P Y T9 U T Y T U0 T LV_I LV_V LV_VREFH LV_VREFL LV_LK# LV_LK LV_T#0 LV_T# LV_T# LV_T# LV_T0 LV_T LV_T LV_T LV_LK# LV_LK LV_T#0 LV_T# LV_T# LV_T# LV_T0 LV_T LV_T LV_T LV igital isplay Interface VO_TRLLK VO_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P T T J U J 0 0 W Y9 9 E T0 T0 V0 E0 TM_TXN_PH 0 0 TM_TXP_PH 0 F TM_TXN_PH 0 H TM_TXP_PH 0 TM_TXN0_PH 0 TM_TXP0_PH 0 TM_LKN_PH 0 TM_LKP_PH 0 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V TM_TRLLK TM_TRLT HMI_HP TM_TXN_PH TM_TXP_PH TM_TXN_PH TM_TXP_PH TM_TXN0_PH TM_TXP0_PH TM_LKN_PH TM_LKP_PH isplay Port isplay Port VO RT PH RT PH RT_R_PH RT_LUE RT_REEN RT_RE P_TRLLK P_TRLT U0 U RT isable: (For discrete graphic). N: RT_RE,RT_REEN,RT_LUE R R % R R % R % R _LK_PH _T_PH RT_HYN_PH RT_VYN_PH R R R0.9, R0.: K+/-0.% Intel checklist recommand:.0k P resistor to 0.% % KOhm V V Y Y RT LK RT T RT_HYN RT_VYN _IREF RT_IRTN IEXPEK-M RT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P T J0 0 J F H E isplay Port RT_HYN,RT_VYN. -k ±0.% pull-down to : _IREF esign guide. updated: _IREF F: Kohm/% ; R:Kohm/0.% Á %. onnected to : RT_ITRN. onnect to +V.: V UTeK OMPUTER IN. N Friday, pril 09, 00 ate: heet of 99.0

24 change to PI_LK to sync I 0 LK_PI_F LK_KPI_PH LK_EU T PI_RT# PI_PME#: Internal PU to suspend plane. Ohm Ohm Ohm T0 T0 T0 T0 T R R0 R0 PI_INT# PI_INT# PI_INT# PI_INT# PI_REQ0# PI_REQ# PU_ELET#_PIO PI_REQ# PI_NT0# PI_NT# PI_NT# PI_INTE# PI_INTF# PI_INT# PI_INTH# PI_RT# PI_ERR# PI_PERR# PI_IRY# PI_PR PI_EVEL# PI_FRME# PI_LOK# PI_TOP# PI_TRY# PI_PME# PLT_RT# LK_PI0_R LK_PI_F_R LK_KPI_PH_R LK_EU_R H0 N J 0 E H E0 0 M M F M0 M J K F0 K M J K L F J0 F M H J0 H H F M F K F H K K E E0 H F 9 M N P P P P U00E /E0# /E# /E# /E# PIRQ# PIRQ# PIRQ# PIRQ# REQ0# REQ#/PIO0 REQ#/PIO REQ#/PIO NT0# NT#/PIO NT#/PIO NT#/PIO PIRQE#/PIO PIRQF#/PIO PIRQ#/PIO PIRQH#/PIO PIRT# ERR# PERR# IRY# PR EVEL# FRME# PLOK# TOP# TRY# PME# PLTRT# LKOUT_PI0 LKOUT_PI LKOUT_PI LKOUT_PI LKOUT_PI PI NVRM U NV_E#0 NV_E# NV_E# NV_E# NV_Q0 NV_Q NV_Q0/NV_IO0 NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q9/NV_IO9 NV_Q0/NV_IO0 NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_LE NV_LE NV_ROMP NV_R# NV_WR#0_RE# NV_WR#_RE# NV_WE#_K0 NV_WE#_K UP0N UP0P UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UP9N UP9P UP0N UP0P UPN UPP UPN UPP UPN UPP URI# URI O0#/PIO9 O#/PIO0 O#/PIO O#/PIO O#/PIO O#/PIO9 O#/PIO0 O#/PIO Y9 P V9 P P T T9 V E +V_NVRM_VQ J NV_LE R KOhm J +V_NVRM_VQ NV_LE Y NV_LE R.,item NV_LE R KOhm U V Y Y V F Place within 00 mils of PH NJa Recommand settings H J U_PN0 U_PP0 0 U port (IO/) U_PN U_PP U port(io/) N0 P0 U_PN U_PP U port J0 T L0 T F0 0 TV turner 0 0 Newcard M N annot use LM(.0) or UW(./.0) annot use U port (th) or ocking H J U_PN U_PP WiFi/WiMax E F U_PN9 U_PP9 9 amera T09 T0 0 H U_PN U_PP ard Reader(.0) L M U_PN U_PP T (.) U_PN U_PP FP (.) T T R. URI_PN R +VU_OR.Ohm % Place within 00 mils of IH N 0KOHM RN0 J 0KOHM RN0 F 0KOHM RN0 L 0KOHM RN0 E 0KOHM RN0 0KOHM RN0 F 0KOHM RN0 T 0KOHM RN0 PI_INT# PI_INT# PI_TOP# PI_INTE# PI_INT# PI_IRY# PI_ERR# PI_INT# PI_PERR# PI_LOK# PI_EVEL# PI_INTH# PI_REQ# PI_FRME# PI_TRY# PI_REQ0# PI_INT# PI_INTF# PI_REQ# RP0 RP0 RP0 RP0 RP0E RP0F RP0 RP0H RP0 RP0 RP0 RP0 RP0E RP0F RP0 RP0H RP0 RP0 RP0 RP0 RP0E RP0F RP0 RP0H +V 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 9 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 9 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 9 0KOhm 0 0PF/0V 0 0PF/0V 0 IEXPEK-M 0.UF/V U0 V +V PLT_RT# NT0#,NT#: oot IO trap. oot IO trap PI_NT# PI_NT0# oot IO Location 0 0 LP NT#: swap override trap/ Top-lock swap override jumper Y NZ0PX_NL R UF_PLT_RT#,,0,,,0 0 0 PI Reserved Low=Enabled swap override/ Top-lock swap override PI (PH) ampled on rising edge of PWROK. +V High=efault R.,item PI_NT0# PI_NT# R0 0KOhm R 0KOhm PI_NT# R KOhm R KOhm R0 KOhm UTeK OMPUTER IN. N Friday, pril 09, 00 ate: heet of 99.0

25 U00F +V R 0KOhm +V R 0KOhm +V R9 0KOhm U_MI# T9 0 T0 T90 T9 EXT_MI# T9 PIO0 PIO PU_HP_INTR#_R U_MI# Y J F0 K9 MUY#/PIO0 TH/PIO TH/PIO TH/PIO PIO MI LN_PHY_PWR_TRL/PIO LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP 0TE H H F F U 0TE 0 +VTT_PU T_LE T PIO P_I0 U_MI# PU_HOL_RT# TP/PIO LKOUT_LK0_N/LKOUT_PIEN M LK_PU_N_PH R 0KOhm R 0KOhm P_I WLN_LE WLN_ON#, PU_PWROK U0_EL PIO :Enable VVRM,Low=disable. T9 efault internal pull up. T9 PU_PWROK VRM_EN PIO F Y H0 V M TH0/PIO LOK/PIO MEM_LE/PIO PIO PIO TP_PI#/PIO PIO PU LKOUT_LK0_P/LKOUT_PIEP PEI RIN# PROPWR THRMTRIP# M 0 T E0 0 L 00 PM_THRMTRIP# LK_PU_P_PH H_PEI RIN# 0 H_PUPWR, R0 OHM R OHM 00 L0 H_THRMTRIP# T0 T_LK_REQ# V TLKREQ#/PIO PU_PRNT# PU_PWR_EN#_PIO L0 00 P_I0 V TP/PIO TP/PIO LO/PIO TP TP TP W T T9 T P_I P TOUT0/PIO9 TP Y T T9 LK_REQ# H PIELKRQ#/PIO TP Y T T9 LK_REQ# F PIELKRQ#/PIO TP V T T99 PIO TOUT/PIO TP V T +VU_OR 0 PH_TEMP_LERT# T_ON F TP/PIO9 PIO TP TP9 TP0 F M N TP9_PH TP0_PH T T T EXT_MI# LK_REQ# LK_REQ# PH_TEMP_LERT# PU_HP_INTR#_R T T T T T 0KOhm R T T T 0KOhm R T9 T0 0KOhm R0 T T T T T T T T9 T0 T T T T T T T T +V T9 T0 T T 0KOhm R 0KOhm R TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF9 TP_V_NTF0 TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF9 TP_V_NTF0 TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF9 TP_V_NTF0 TP_V_NTF 9 0 E E F F H H H H J J J J9 J J0 J J E E V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_9 V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_9 V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_9 V_NTF_0 V_NTF_ IEXPEK-M NTF RV TP TP TP TP TP TP TP TP TP9 N_ N_ N_ N_ N_ INIT_V# TP J K K M N M0 N0 H T9 P 0 TP_PH T TP_PH TP_PH TP_PH TP_PH TP_PH TP9_PH TP_PH_N T TP_PH_N T TP_PH_N T TP_PH_N T TP_PH_N T INT_V# TP_PH_T T0 T T T T T9 T0 T T9 T PIO0 0KOhm R PIO 0KOhm R PIO 0KOhm R PIO 0KOhm R PU_PWROK R 0KOhm T_LK_REQ# R 0KOhm UTeK OMPUTER IN. N Friday, pril 09, 00 ate: heet of 99.0

26 PM_RMRT#,0 +VTT_PH_VPLL_EXP +VTT_PH_VPLL_FI +VTT_PH_VPLL_EXP +VTT_PH_V +VTT_PH_VPLL_FI +VTT_PH_VIO +VTT_PH_VIO +V_V +VTT_PH_VIO +VTT_PH_OR +VTT_PH_OR +VFI_VRM +.V +VTT_PH_.V_.V +.V +VTT_PH_OR +V_V_IO +V +VTT_PU +V +VM_VPEP +VM +V_NVRM_VQ +.V +.V_VMI_VRM +V +V +VTT_PH +VTT_PH_V +VTT_PH_OR +VTT_PH_OR +VTT_PH_VIO +V +VFI_VRM +.V_VMI_VRM +.V_VT_LV +V_V_LV +.V +V_NVRM_VQ +VU +VU +VU ate: heet of Friday, pril 09, 00 UTeK OMPUTER IN. N.0 99 ate: heet of Friday, pril 09, 00 UTeK OMPUTER IN. N.0 99 ate: heet of Friday, pril 09, 00 UTeK OMPUTER IN. N max m 0 idle 00m 0 max 9m 0 max 9m 0 max m 0 max m 0 max m 0 max m 0 max +VTT_PH_VPLL_EXP.. 0 max +VTT_PH_V_EXP.0 0 max U Item R.,item 0 0UF/.V 0 0UF/.V 00 L 00 L R R R R L0 KOhm/00Mhz L0 KOhm/00Mhz 0 TW 0 TW Q0 N00 Q0 N00 R R 0 0UF/.V R 0 0UF/.V R VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] F VORE[] F VORE[] F0 VORE[9] F VORE[0] H VORE[] H VORE[] H0 VORE[] H VORE[] J0 VORE[] J VPNN[] K9 VPNN[] K0 VIO[] N VIO[] N VIO[9] N VIO[0] N VIO[] N0 VIO[] N VIO[] T VIO[] T VIO[] U VIO[] U VIO[] V VIO[] V VIO[9] W VIO[0] W VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[9] E VIO[0] E VIO[] VIO[] VIO[] H VIO[] J VIO[] J V[] E0 V[] E VTX_LV[] P VTX_LV[] P VLV H VVRM[] T VVRM[] T VPLLEXP J VFIPLL J VPNN[] K VPNN[] K VPNN[] M VPNN[] M VIO[] K VTX_LV[] T VTX_LV[] T V_[] F V_LV H9 V_[] F VIO[] M V_[] V_[] V_[] V_[] N VME_[] M VME_[] M9 VME_[] P VME_[] P9 VPNN[] K VPNN[9] M VPNN[] M VMI[] T VMI[] U VIO[] N0 VIO[] N POWER V ORE MI PI E* RT LV FI NN / PI HVMO U00 IEXPEK-M POWER V ORE MI PI E* RT LV FI NN / PI HVMO U00 IEXPEK-M 00 L0 00 L0 0 UF/.V 0 UF/.V 0.0UF/V R 0.0UF/V R JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL 0.UF/V 0.UF/V R9 R9 L09 KOhm/00Mhz L09 KOhm/00Mhz 00 L 00 L 00 L R 00 L R 0.UF/V R 0.UF/V R 0 UF/.V 0 UF/.V 0.UF/V 0.UF/V 00 L 00 L 0 0UF/.V 0 0UF/.V 00 L 00 L JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL 00 L 00 L 0UF/.V 0UF/.V 9 UF/.V R 9 UF/.V R R 0KOhm R 0KOhm 0 0UF/.V 0 0UF/.V 00 L0 00 L0 L0 KOhm/00Mhz R L0 KOhm/00Mhz R 00 L0 00 L0 V[] 9 V[] 0 V[] V[] V[] V[] V[] 0 V[9] V[0] V[] V[] V[] V[] 0 V[] V[] V[] 9 V[] V[9] V[0] V[] V[] V[] V[] V[] V[] V[] V[] 0 V[9] V[0] V[] V[] V[] V[] 9 V[] V[] E V[] E V[9] F V[] F V[] P V[] F V[] F V[] F9 V[9] F V[0] F V[] V[] V[] H V[] H V[] H V[] H V[] H V[9] H V[0] H V[] H V[] J9 V[] J V[] J0 V[] J V[] J V[] J V[] J V[9] J V[0] J V[] T V[] J V[] K V[] K V[] K V[] K V[9] K V[0] K0 V[] K V[] K V[] K V[] K V[] K V[] K V[] K V[] K9 V[9] K V[90] K V[9] L V[9] L V[9] M V[9] M0 V[9] M V[9] M V[99] M V[00] M V[0] M0 V[0] M V[0] M V[0] M V[0] M V[0] M V[0] M9 V[09] M V[0] U0 V[] M V[] V V[] M9 V[] M V[] 0 V[] N V[] N0 V[9] N V[0] P V[] P V[] P V[] P9 V[] P V[] P V[] R V[] R V[] T V[] T V[] T V[] T V[] T V[] T V[] V V[] V V[] V0 V[9] V V[0] V0 V[] V V[] V V[] V V[] V V[] V9 V[] V V[] V V[] W V[9] W V[0] W V[] F9 V[] W V[] W V[] W0 V[] W V[] Y V[] Y V[] Y V[0] Y V[] U V[] N V[] 0 V[0] V[] V V[] U V[] M9 V[] M V[] N9 V[] H9 V[9] V[0] H V[0] V[9] V[9] U00H IEXPEK-M U00H IEXPEK-M JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL 0.0UF/V R 0.0UF/V R 0 UF/.V 0 UF/.V L0 KOhm/00Mhz L0 KOhm/00Mhz 0 0UF/.V 0 0UF/.V 0.UF/V 0.UF/V 0 UF/.V 0 UF/.V Q N00 Q N UF/V R UF/V R R R 00 L 00 L 0.UF/V 0.UF/V UF/.V UF/.V 0 UF/.V 0 UF/.V

27 +VT PRT +.0VM_OR_R +.0VM_OR_R +.0VM_OR_R +.0VM_OR_R +VTT_PH_V PL +VTT_PH_V PL +VTT_PH_V PL +V_VPU +.0VM_OR +VTT_PH_V_LK +.0VM_VUX +VTT_PU_VPPU +V_RT +VTT_PH_VIO +V_V_ +.0VM_OR +VTT_PU +VTT_PH_.V_.V +VU_OR +VTT_PH_V PL +VTT_PH_V PL +VTT_PH_VPLL +V_PH_VREF +VU_VPU +VTT_PH_VIO +VTT_PH_VIO +VTT_PH_OR +V +VU_OR +.0VM_OR +VU_OR +V_V_ +VU_OR +VTT_PH_VIO +V_V_ +V +VPLLVRM +VU_PH_VREFU +VTT_PH_OR +VTT_PH_V PL +VTT_PH_V PL +VTT_PH_OR +VTT_PH_.V_.V +VPLLVRM +VTT_PH +.0VM_OR +V +V_V_ +VU_H +VU_OR +VU +VU_OR +VU +VU_OR +VM TP_PH_VW +V.0_INT_VU ate: heet of Tuesday, March 0, 00 UTeK OMPUTER IN. N.0 99 ate: heet of Tuesday, March 0, 00 UTeK OMPUTER IN. N.0 99 ate: heet of Tuesday, March 0, 00 UTeK OMPUTER IN. N.0 99 m 0 max m 0 max 0 max m 0 max m 0 max?? +.VM_VEPW >m 0 max m 0 max +VTT_PH_V.99+m 0 max m 0 max +VTT_PH_VUORE m 0 max +VTT_PH_V_T +V_VPPI +V_VPORE 0mil trace R.,item 0.UF/V 0.UF/V 0UF/.V 0UF/.V 0 TW 0 TW UF/.V UF/.V 0.UF/V 0.UF/V JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL UF/.V UF/.V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 9 UF/.V 9 UF/.V R R 0 0.UF/V 0 0.UF/V JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL UF/.V UF/.V L0 KOhm/00Mhz L0 KOhm/00Mhz E0 0UF/V ER=0mOhm/Ir=.9 E0 0UF/V ER=0mOhm/Ir=.9 L0 KOhm/00Mhz L0 KOhm/00Mhz UF/.V UF/.V 0.UF/V 0.UF/V 0 0.UF/V 0 0.UF/V 00 L9 00 L9 JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL 00 L 00 L E0 0UF/V ER=0mOhm/Ir=.9 E0 0UF/V ER=0mOhm/Ir=.9 0.UF/V 0.UF/V 00 L9 00 L9 UF/.V UF/.V 0 TW 0 TW UF/.V UF/.V UF/.V UF/.V 0.UF/V 0.UF/V R 0 R 0 00 L 00 L L0 KOhm/00Mhz L0 KOhm/00Mhz 0.UF/V 0.UF/V 00 L 00 L 0 UF/.V 0 UF/.V 0.UF/V 0.UF/V 0.UF/V 0.UF/V JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL 0.UF/V 0.UF/V 00 L 00 L L0 KOhm/00Mhz L0 KOhm/00Mhz 00 L 00 L 0.UF/V 0.UF/V R R 0 UF/.V 0 UF/.V 00 L 00 L PUYP Y0 VME[] VME[] 9 VME[] VME[] F VME[] F VUH L0 VU_[] U VIO[] V VIO[] 9 VIO[] F0 VIO[] F9 VME[] V9 VME[] V VME[9] V VME[0] Y9 VME[] Y VME[] Y VREF K9 V_[] J V_[9] L V_[0] M V_[] N V_[] P V_[] U VRT VU_[] VU_[] VU_[] VU_[] VU_[] VU_[] E VU_[] E VU_[0] F VU_[9] F VU_[] VU_[] VU_[] H VU_[] H VU_[] J VU_[] J VU_[] L VU_[] L VU_[0] M VU_[9] M VU_[] N VU_[] N VU_[] P VU_[] P VU_[] U VU_[] U VU_[] U VU_[] V VIO[] 0 VIO[0] VIO[0] H9 VPLL[] VPLL[] VIO[] J VREF_U F VIO[] H0 VIO[] 9 VIO[] 0 VIO[9] VIO[] F V_[] VIO[9] H VVRM[] T0 PU Y VIO[] F VIO[] H VLN[] F VLN[] F VPLL[] VPLL[] VVRM[] U VLK[] P VLK[] P PRT V9 VIO[] F VME[] F VIO[] H VIO[] H PT V VTPLL[] K VTPLL[] K VME[] VME[] Y VME[] Y VME[] V_[] V V_[] V V_[] Y VU_[9] P VU_[0] U9 VU_[] U0 VU_[] U VIO[] V VIO[] V VIO[] Y VIO[] Y V_PU_IO[] T V_PU_IO[] U POWER T U lock and Miscellaneous H PU PI/PIO/LP RT PI/PIO/LP U00J IEXPEK-M POWER T U lock and Miscellaneous H PU PI/PIO/LP RT PI/PIO/LP U00J IEXPEK-M 00 L0 00 L0 0 UF/.V 0 UF/.V UF/.V UF/.V UF/.V UF/.V 0UF/.V 0UF/.V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V R 0 R 0.UF/.V.UF/.V JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL 0UF/.V 0UF/.V UF/.V UF/.V V[9] Y V[0] V[] V[] 9 V[] V[] V[] V[] 9 V[] V[] V[9] V[0] V[] V[] V[] 0 V[] V[] 0 V[] V[] V[] V[9] 9 V[0] V[] 0 V[] V[] V[] V[] V[] V[] V[] 0 V[9] V[90] V[9] H9 V[9] V[9] 9 V[9] V[9] E V[9] E V[9] E0 V[9] E V[99] E0 V[00] E V[0] E V[0] E V[0] E V[0] E V[0] E0 V[0] E V[0] E V[0] F V[09] F9 V[0] F V[] V[] V[] V[] 0 V[] H V[] H V[] H9 V[] H V[9] H V[0] H V[] H9 V[] H V[] H V[] H V[] V[] 0 V[] V[] E V[9] E V[0] E0 V[] E V[] E0 V[] E V[] E V[] E V[] E V[] E V[] K V[] K V[] L V[] L V[] L V[9] L V[0] L V[] L V[] L0 V[] L V[] M V[] M V[] M0 V[] N V[] M V[9] M V[0] M V[] M V[] M9 V[] M V[] M V[] N V[] P V[] P V[9] P0 V[90] P V[9] P V[9] P V[9] P V[9] P V[9] R V[9] R V[9] T V[9] T V[99] T V[00] T9 V[0] T V[0] T V[0] U0 V[0] U V[0] U V[0] U V[0] P V[0] V V[09] P V[0] V9 V[] V0 V[] V V[] V0 V[] V V[] V V[] V V[] E V[9] E V[0] F9 V[] F V[] 0 V[] V[] V[] V[] V[] V[] V[9] 0 V[0] V[] V[] V V[] V V[9] V V[0] V V[] V V[] V V[] V9 V[] V V[] V V[] V V[] W V[] W V[9] Y V[0] Y V[] Y V[] Y9 V[] Y V[] Y V[] Y0 V[] Y V[] Y V[] Y V[9] Y V[0] Y V[] Y V[] Y V[] Y V[] P9 V[] P V[] V[] F9 V[] H V[] H0 V[] H0 V[] H V[] H V[] H V[] T V[] V[] T V[9] V[0] Y V[] T V[] M V[] T V[] M V[] K V[] K9 V[] V V[] K V[] K V[9] H9 V[0] H V[] J U00I IEXPEK-M U00I IEXPEK-M 00 L 00 L 0.UF/V 0.UF/V 9 UF/.V 9 UF/.V

28 +VM_PI PH PI ROM R.,item L +V +V_M +VU +VM R R Reserved O setting for E. (choose way) Normal: Mount R0,R (efault) +V +V_M R R9 L_ M_LK R0 R M_LK_L Q0 UMKN M_LK EN 9 Thermal _ M_T R R M_T_L Q0 UMKN M_T EN 9 +VM_PI 0 0 PI_#0 PI_O R R Ohm PI#0 PIO0 L0 00 R.KOhm +VM_PI_WP0# U0 E# V O HOL# WP# K V I TVF0 (Mb) +VM_PI_00 PILK0 PII0 R.KOhm L0 0 0.UF/V 00 R.,item R0 R PI_LK 0 PI_I 0 MU Link device: [MJ] P, LKEN,EU,WLN, PU XP,PH XP,VI ONTROLLER [0J] FM00,ME LE, L_ Q0 UMKN +V R0.KOhm +V.KOhm R0 R N/ R N/ M_LK_,, L0 00 L0 00 PH _ Q0 UMKN M_T_,, 0 E_O_PH 0 E_E#_PH 0 E_I_PH 0 E_K_PH +VU E 0 M_LK ML_LK 0 M_T Q0 UMKN R0 R Q0 UMKN PH ML_T +V +V.KOhm R0.KOhm R0 M_LK_ 0, Q0 UMKN V Thermal M_T_ 0, Q0 UMKN UYTEM I : _ UTeK OMPUTER IN. N UYTEM I : ROM Friday, pril 09, 00 ate: heet of 99.0

29 Layout note: R9 RX90 FL R9 R9,R9:as close as possible to the net FL of RX90. +V_._I R9 0KOhm +V_I +V_.0 The oc and uc pin of M are open drain in next version. LK_PH_LK LK_PH_LK# O_LV T90 U_LV T90 +VTT_PH_OR L90 Layout note: +V_.0 V_I: pin -->0.uF to each pin put it at pin, 0 lock_select_uc 0 LK_PWR# +V_._I KOhm R90 R9 0KOhm R9 0KOhm LK FL 0 00 LK_IH M_T EN M_LK EN +V_._I R9 R90 LK_PWR Q90 N00ET +V_._I X_LK X_LK FL RX90 Ohm.KOhm.KOhm 9 0 +V_I +V_._I VPU_. PUT_LR PU_LR PU 0 O_.** 9 U_.** VPU_IO_LV VPIEX_. VTTPWR/P#_. REF X X VREF_. REF/FL** T_. LK_. V9_. 9 OT9T_LR OT9_LR V_. FIX T_TRK_. VPIEX_IO_LV PIEX_LR PIEXT_LR PIEX T_LR TT_LR 0 T 9 LK_ U90 I9LVKLF +V_.0 TP_PU# R90 0PF/0V 9 LK_MI# LK_MI LK_T# LK_T +V_._I R9 0KOhm NVM_ +.V +.V +.V +V +V /00Mhz L90 /00Mhz L90 L90 /00Mhz L90 /00Mhz /00Mhz L90 /00Mhz 90 0UF/0V Layout note: Layout note: +V_I V_I: pin -->0.uF to each pin put it at pin,, 90 0.UF/V 9 0.UF/V UF/V V_._I: pin -->0.uF to each pin put it at pin,9 90 0UF/0V 90 0.UF/V 90 0UF/0V 90 0.UF/V 90 0.UF/V 90 0.UF/V +V_._I LK_FIX R90 0PF/0V 9 NVM_NO LK_OT9# LK_OT9 R.0-.Mhz X90 X_LK XLK R90: For Xtal measurement X_LK R90 9 PF/0V 9 PF/0V R.0- UTeK OMPUTER IN. Friday, pril 09, 00 ate: heet of

30 0, LP_0 0, LP_ 0, LP_ 0, LP_ LK_KPI_PH 0, LP_FRME#,,,,,0 UF_PLT_RT# 0 INT_ERIRQ EXT_MI# EXT_I# 0TE RIN# E_RT# E_K_PH E_O_PH E_I_PH E_E#_PH E_RT# T0 ME_usPwrnck_E E_K L0 00 T09 E_O L0 00 E_I L0 00 E_E# L0 00 T00 R.0- R. KI0 KI KI KI KI KI KI KI PM_PWRTN# OP_# KO0 KO KO KO KO KO KO KO KO KO9 KO0 KO KO KO KO KO T0 VU_ON L0 VU_ON L0, VP_V0 00, VP_V L TP_LK R.0- TP_T attery Thermal sensor PH_PI_OVL H: override PH PI RNX00 OHM RNX00 OHM RNX00 OHM RNX00 OHM M0_LK M0_T M_LK M_T THRO_PU PH_PI_OV T0 E_XIN E_XOUT U00 P0 FK R0#/P FMIO FMOI FE# E0#/P +V_E +V +V L0 PWM0/P0 L PWM/P L PWM/P L PWM/P LPLK PWM/P LFRME# PWM/P LPRT#/WUI/P PWM/K/P ERIRQ PWM/P EMI#/P EI#/P RX/IN0/P0 0/P TX/OUT0/P KRT#/P TX0/TM0/P WRT# RIN#/PWRFIL#/KKOUT /LPRT#/P KI0/T# KI/F# KI/INIT# KI/LIN# KI KI KI KI KO0/P0 KO/P KO/P KO/P KO/P KO/P KO/P KO/P KO/K# KO9/UY KO0/PE KO/ERR# KO/LT KO KO KO KO/MOI/P KO/MIO/P KK KKE PLK0/TM0/PF0 PT0/TM/PF PLK/TR0#/PF PT/RT0#/PF PLK/WUI0/PF PT/WUI/PF MLK0/P MT0/P MLK/P MT/P MLK/WUI/PF MT/WUI/PF IT0E 0 9 VTY VTY VTY VTY VTY VTY(PLL) KMX LP FLH ROM P/ Mus VT V V V VORE V V V V V V UF/V E_ R0 RX0/P0 TMRI0/WUI/P TMRI/WUI/P PWUREQ#/O/P L0HLT/O/WUI/PE0 E/WUI/PE E#/WUI/PE ELK/WUI/PE PWRW/PE WUI/PE LPP#/WUI/PE L0LLT/WUI/PE PIO RI#/WUI0/P0 RI#/WUI/P INT/T0#/P TH0/P TH/TM/P UY/P/I LKRUN#/WUI/PH0/I0 RX/WUI/PH/I TX/WUI/PH/I HE#/WUI9/PH/I HK/PH/I HMIO/PH/I HMOI/PH/I 0/PI0 /PI /PI /PI /WUI/PI /WUI9/PI /WUI0/PI /WUI/PI 0/TH/PJ0 /PJ /PJ /PJ /0#/PJ /RI0#/PJ ME PREENT_E RFON_W# PH PH U_E#_ U_E#_ L0 L09 R0 for ITX & ITX 009 & 00 for ITX mil trace as possible R T0 L_L_PWM FN_PWM 0 T0 T0 T00 T0 VORE_MET PM_RMRT#, _IN_O#, T_IN_O# 0 PM_U# L_KOFF# FN0_TH 0 HMI_HP_E T0 T0 T0 T0 PWR_LE# H_LE# H_FULL_LE# PWR_W#, T0 R.0- LI_W#,, MRTHON# R.0- PM_U# PM_LKRUN# R0 L00 L NUM_LE# P_LE# PU_VRON PM_PWROK VET_E IET_E 009 0PF TEL_0 TEL_ lock_select_uc 9 PU_V0 0 PU_V 0 PWRLIMIT#, YNMI_VORE_TL 0 FX_VR_ON, H_EN U_E#, U_E#,,, For IT Power R. R.0- R.0- +V For PU / P +VU +V_E PM_U# PM_U# PU_VRON R.,item V_LERT# U_PWR,, R0 LL_YTEM_PWR, VRM_PWR,,0 FX_VR PH_TEMP_LERT# L00 PU_IENE 00 PU_IENE VORE_MET R. 0mil trace as possible For X'tal R0 RN00 RN00 RN00 RN00 VU_ON E_XIN R.,item R..KOHM.KOHM.KOHM.KOHM RN00 RN00 RN00 RN00 00KOhm +V_E T_IN_O# M0_LK M0_T M_LK M_T 00KOHM 00KOHM 00KOHM 00KOHM Note: EXT_MI#, EXT_I#, PU power plane depend on IH9 PIO. JP00 Note: load=.pf place close to E E_XOUT +VU +V_E +V_E +V +V For E Hardware trap E_ imt E strapping need to check 0 PF/0V MM_OPEN_MIL R00 R0 0MOhm 00KOhm X00.Khz +/-0ppm/.PF 00 L0 0 PF/0V I/O ase ddress Note: It can be programmable by E fireware hare Memory Note: It can be programmable by E fireware. PP Enable 00 0UF/0V RN00 RN00 RN00 RN00 RN00 RN00 RN00 RN00 RN00 RN00 RN00 RN00 Note: efault Int. Pull-Low R0: For Xtal measurement L UF/V 0KOHM 0KOHM 0KOHM 0KOHM.KOHM.KOHM.KOHM.KOHM 0KOHM 0KOHM 0KOHM 0KOHM 00 0.UF/V +V_E LI_W# PWRLIMIT# _IN_O# PWR_W# +V TP_LK TP_T U_E#_ U_E#_ 0TE RIN# PM_PWRTN# PM_RMRT# 00 0UF/0V 00 0.UF/V +V +V_E For imt pin name _PREENT PM TTE# _TTE_ON PM_LP_M# LP_M_ON E_WLN_PWR MP_PWR _PREENT LN_WOL_EN +VM_P +.VM_+VMLK_P UPWR_K +V E_ For Instant Key Note: lose to E R0 R0 L00 00 For Expressate & P 0KOhm 00 For +VPLL 0.UF/V Put beside pin 00 0.UF/V 0KOhm MRTHON# RFON_W# +V_E R00 0KOhm PU_IENE 00 0PF PU_IENE 0 0PF ME_usPwrnck T0 ME_usPwrnck ME_usPwrnck_E Q00 N00 L0 00 Mount R00,Q00,NI R0 for IT00 ME PREENT_E L0 00 ME PREENT ME PREENT T0 UTeK OMPUTER IN. Friday, pril 09, 00 ate: heet of