DDR Page 3 ~ 6 15W: 3.2GT/S 12W&9W: 2.0GT/S AMD RS880M. Page 10 ~ 18 EC KB3310 Page 30 ~ 31 AMD SB710. Page 20 ~ 28. SATA SATA HDD Page 51

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1 T LOK IRM M PU W/W/W HT.0 /.0 Page ~ W:.T/ W&W:.0T/ R 00 ingle hannel R O-IMM Page ~ LK EN Page FN + ENOR Page 0 ischarge Page LV Page HMI RT M R0M K Page IO OR PI-E PIE X Page 0 ~ E K0 Page 0 ~ U.0 X R NE/smedia U.0 ZLI odec L peaker HP/MI Page 0 M 0 Page 0 ~ LP PI ROM Page 0 ebug onn. Page U T T H Page MINIR/T.0 ard Reader U U Page U.0 with charge Page in ard Reader UTeK omputer IN lock iagram N/ ustom T.0 ate: Tuesday, ugust 0, 00 heet of 0

2 Reset I _T_Y mode: VU_ON assert after E_RT# T Mode: VU_ON assert after Press button +V +V +V_E VU_ON E_RT# E PWR_W# Power On WITH PWROK REET_L M eneva PU LTTOP_L +.VU +VU +VU +VU U_PWR PM_RMRT# PM_PWRTN# _RT# +.V U_PWR +V +._PU_V +.V +.V +V +V +0.V +0.V +.V_N VORE +V_N +.V_PU_N_ +PU_VN ' U_E# LL_YTEM_PWR ' 0 U_E# PU_VRON VRM_PWR E KRT# PM_U# PM_U# R_IN# PM_PWROK_E LP_# LT_P LP_# LT_RT# 0 (outh ridge) LT_TP# KRT# _RT# PWR_OO N_PWR PU_PWR PU_LT_RT# PU_LT_TOP# _RT# N_PWR LTTOP# YREET# POWEROO R0 (North ridge) 0 +V POWER-UP Vxxx LK EN UTeK.omputer.IN ustom T Power sequence N/ ate: Tuesday, ugust 0, 00 heet of 0.0

3 HT_PU_TX[0..] [0] [0] HT_PU_RX[0..] [0] HT_PU_RX#[0..] [0] HT_PU_RX_LK [0] HT_PU_RX_LK# [0] HT_PU_RX_LK0 [0] HT_PU_RX_LK#0 [0] HT_PU_RX_TL [0] HT_PU_RX_TL# [0] HT_PU_RX_TL0 [0] HT_PU_RX_TL#0 HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX0 HT_PU_RX#0 HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX0 HT_PU_RX#0 HT_PU_RX_LK HT_PU_RX_LK# HT_PU_RX_LK0 HT_PU_RX_LK#0 HT_PU_RX_TL HT_PU_RX_TL# HT_PU_RX_TL0 HT_PU_RX_TL#0 U00 W L0_IN_H W L0_IN_L U L0_IN_H U L0_IN_L R L0_IN_H R L0_IN_L P L0_IN_H P L0_IN_L L L0_IN_H L L0_IN_L J L0_IN_H0 J L0_IN_L0 H L0_IN_H H L0_IN_L L0_IN_H L0_IN_L T L0_IN_H T L0_IN_L T L0_IN_H T L0_IN_L P L0_IN_H P L0_IN_L P L0_IN_H P L0_IN_L M L0_IN_H M L0_IN_L K L0_IN_H K L0_IN_L K L0_IN_H K L0_IN_L H L0_IN_H0 H L0_IN_L0 M L0_LKIN_H M L0_LKIN_L M L0_LKIN_H0 M L0_LKIN_L0 Y L0_TLIN_H Y L0_TLIN_L V L0_TLIN_H0 V L0_TLIN_L0 L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H0 L0_OUT_L0 L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H0 L0_OUT_L0 L0_LKOUT_H L0_LKOUT_L L0_LKOUT_H0 L0_LKOUT_L0 L0_TLOUT_H L0_TLOUT_L L0_TLOUT_H0 L0_TLOUT_L0 E E E E H H K K H H Y Y Y Y F F F F K K F F Y Y V V HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX0 HT_PU_TX#0 HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX0 HT_PU_TX#0 HT_PU_TX_LK HT_PU_TX_LK# HT_PU_TX_LK0 HT_PU_TX_LK#0 HT_PU_TX_TL HT_PU_TX_TL# HT_PU_TX_TL0 HT_PU_TX_TL#0 HT_PU_TX_LK [0] HT_PU_TX_LK# [0] HT_PU_TX_LK0 [0] HT_PU_TX_LK#0 [0] HT_PU_TX_TL [0] HT_PU_TX_TL# [0] HT_PU_TX_TL0 [0] HT_PU_TX_TL#0 [0] HT_PU_TX#[0..] [0] UTeK.omputer.IN ustom T onesus HT I/F N/ ate: Tuesday, ugust 0, 00 heet of 0.0

4 H M H M0 H M H M H M H M H M H M H M H M H M H M H M H M H M0 H M H M H M H M H M H M H M H M0 H M H QP0 H QP H QN H QN0 H QP H QN H QP H QP H QN H QP H QN H QN H QP H QN H QN H QP H Q H Q0 H Q H Q H Q H Q H Q H Q H Q H Q H Q H Q H Q H Q H Q H Q H Q H Q H Q H Q H Q H Q H Q H Q0 H Q H Q H Q H Q H Q H Q0 H Q H Q H Q H Q H Q H Q H Q H Q H Q H Q H Q H Q H Q H Q H Q H Q0 H Q H Q H Q H Q H Q H Q H Q H Q0 H Q H Q H Q0 H Q H Q H Q H Q H Q0 H Q H Q H 0 H H H REET# H_PM_EXT_T# +.V H R# [] H #0 [] H # [] H M[..0] [] H WE# [] H RMRT# [] H # [] H OT [] H KE [] H OT0 [] H KE0 [] H_PM_EXT_T#0 [] H M[..0] [] H Q[..0] [] H QP[..0] [] H QN[..0] [] H [..0] [] H LKN0 [] H LKP0 [] H LKP [] H LKN [] ate: heet of 0 Tuesday, ugust 0, 00 UTeK.omputer.IN onesus R MEM I/F.0 T N/ ate: heet of 0 Tuesday, ugust 0, 00 UTeK.omputer.IN onesus R MEM I/F.0 T N/ ate: heet of 0 Tuesday, ugust 0, 00 UTeK.omputer.IN onesus R MEM I/F.0 T N/ hange list: LK 0 and reserved follow M chematic check list R. % change to % HT TPT HT TPT M_ P M_ P M_ J M_ T M_ T M_0 M_ T M_ V M_ U M_ V M_ V M_ W M_ Y M_ Y M_ Y M_0 M_NK R M_NK M_NK0 E M_HEK K M_HEK K M_HEK M_HEK F M_HEK L M_HEK K M_HEK H M_HEK0 M_Q_H J M_Q_L H M_Q_H M M_Q_L N M_Q_H L0 M_Q_L M0 M_Q_H N M_Q_L M M_Q_H N0 M_Q_L M0 M_Q_H M_Q_L M_Q_H M_Q_L M_Q_H M_Q_L 0 M_Q_H0 M_Q_L0 M_LK_H N M_LK_L M M_LK_H N M_LK_L M M_LK_H M_LK_L M_LK_H M_LK_L M_LK_H M_LK_L 0 M_LK_H M_LK_L 0 M_LK_H M_LK_L M_LK_H0 M_LK_L0 M_KE N M_KE0 P RV H RV K M0_OT0 H M0_OT K RV0 K RV F M0 L J M0 L0 F M_R_L F M L H M_WE_L M_REET_L L M_EVENT_L M M_T N M_T L M_T L M_T0 N M_T N M_T M M_T M M_T N M_T L M_T N M_T M M_T N M_T M M_T0 N M_T L M_T N M_T M M_T L M_T N M_T L M_T L M_T N M_T N M_T0 M M_T M M_T L0 M_T L M_T L M_T K M_T N M_T M M_T M M_T E M_T0 M_T M_T M_T F M_T F M_T M_T M_T 0 M_T M_T M_T0 M_T 0 M_T 0 M_T M_T M_T M_T M_T M_T M_T M_T0 M_T 0 M_T M_T M_T M_T M_T M_T M_T M_T M_T0 M_M H M_M N M_M N0 M_M K M_M N M_M M_M M_M 0 M_M0 U00 U00 HR KOhm HR KOhm M_T M_T H M_T J M_T0 J M_T F M_T F M_T M_T H M_T K M_T F M_T H M_T K0 M_T F M_T0 M_T F M_T M_T 0 M_T J0 M_T F M_T K M_T F M_T F0 M_T J M_T0 M_T F M_T F M_T H M_T K0 M_T J M_T M_T J M_T J M_T M_T0 M_T M_T E M_T F0 M_T E M_T F M_T H M_T H M_T M_T H M_T0 E M_T F M_T M_T M_T M_T M_T 0 M_T M_T F M_T 0 M_T0 F M_T M_T E M_T H M_T H M_T M_T H M_T E M_T E M_T E M_T0 F M_ P0 M_ M M_ M_ P M_ T0 M_0 M_ P M_ R M_ R M_ U M_ V0 M_ U M_ Y0 M_ M_ W M_0 M_NK R M_NK M_NK0 E M_M H0 M_HEK K0 M_HEK J M_HEK M_HEK F M_HEK L M_HEK L M_HEK H M_HEK0 H M_Q_H J M_Q_L J M_Q_H J M_Q_L K M_Q_H M_Q_L H M_Q_H H M_Q_L M_Q_H M_Q_L H M_Q_H E M_Q_L F M_Q_H E M_Q_L F M_Q_H M_Q_L H M_Q_H0 E M_Q_L0 F M_LK_H K M_LK_L J M_LK_H H M_LK_L M_LK_H Y M_LK_L Y M_LK_H M_LK_L M_LK_H W M_LK_L W M_LK_H P M_LK_L M M_LK_H M_LK_L F M_LK_H0 E0 M_LK_L0 E M_KE M0 M_KE0 M RV F RV J M0_OT0 M0_OT J0 RV H RV E M0 L H0 M0 L0 F M_R_L M L F0 M_WE_L E M_REET_L L M_EVENT_L M M_M L M_M K M_M K M_M J M_M E M_M E M_M H M_M0 U00 U00

5 E E +.V +.V add 0 optional to RN0 0 [0] PU_PWR RN0 0 RN0 0 PU_PWR PF/0V 0 PU_PWR +.V_PU_V /00Mhz L00 Irat= V 00.UF/.V 00 0.UF/.V 00 00PF/0V RN0 KOHM RN0 KOHM [,0] PU_LT_TOP# [0,] PU_LT_RT# PU_LT_TOP# PU_LT_RT# EL 00 at 0 H_V H_V PU_LT_RT# for warm reset JP00 L_JUMP [] [] R_PU_HT_LKP R_PU_HT_LKN 00PF/0V 00PF/0V H HR0 Ohm H K_HT_PUP_ Keep trace from resisor to PU within 0." keep trace from caps to PU within." K_HT_PUN_ [,0] [,0] LYOUT: ROUTE V TRE PPROX. 0 mils WIE (UE x mil TRE TO EXIT LL FIEL) N 00 mils LON. LK T HR HR V PU_PWR PU_LT_TOP# PU_LT_RT# /TI /TI K_HT_PUP_ K_HT_PUN_ PU_I PU_I LERT_L 0 E F N N M N U00 V_ V_ LKIN_H LKIN_L PWROK LTTOP_L REET_L I I V LERT_L ORE_TYPE V V THERM THERM THERMTRIP_L PROHOT_L M L M K N need check H_ORE_TYPE HR H_V [] H_V [] PU_THRM_ [0] PU_THRM_ [0] route as diff pair //,0mil +.V HR0 HR KOhm 0 R & heck list PU_THRMTRIP# HT PU_PROHOT# [0] PROHOT [0,] PWRLIMIT# E to PU/PWR 00 THRNTRIP PU_PROHOT# RV-0 PU_PWR R0 0KOhm 00 0.UF/V Q00 N00 From E. THRO_PU [0] NOTIE r0 Q00 N00 [] [] [] H_V_ENE H_V_ENE H_VN_ENE HT HR H 0.UF/V.Ohm PLE THEM LOE TO PU WITHIN " L00 H_TET Max c00 Length=." HT HT0 HT HT PU_TI PU_TRT# PU_TK PU_TM PU_REQ# VIO_ENE +H_M_VREF H_M_ZN_H H_M_ZN_L H_TET_H H_TET_L H_TET H_TET 00 H_TET M L K N E E M N F E H K J TI TRT_L TK TM REQ_L V_ENE VLT_ENE V_ENE VN_ENE VIO_ENE VR_ENE M_VREF M_ZN_H M_ZN_L TET_H TET_L TET TET TET TET TET TET TET TET TET TET TET TO RY RV PU_PREENT_L HTREF HTREF0 TET_H TET_L TET TET TET TET TET0 TET_H TET_L TET TET TET0 TET N H M J V0 V 0 0 K K H M H J M PU_TO PU_RY H_RV PU_PREENT H_HTREF H_HTREF0 H_TET_H H_TET_L H_TET H_TET H_TET H_TET H_TET0 H_TET H_TET H_TET0.Ohm.Ohm HT R. HT PU_VLT HR HR HR PU_I PU_I LERT_L PU_REQ# H_TET H_TET 0.Ohm H_TET KOHM RN0 Route as 0ohm, diff H_TET0 KOHM RN0 H_TET KOHM RN0 H_TET KOHM RN0 H_TET H_TET H_TET HR HR KOhm KOHM RN0 RN0 0 KOHM RN0 KOHM RN0 HR KOHM RN0 KOHM RN0 KOHM RN0 KOhm KOhm +.V HR0 NEE HEK follow M checklist follow M checklist PU_THRMTRIP# [0,,0,,0,] Q00 T0 TPT PM0 N/ UF_PLT_RT# FORE_OFF# FORE_OFF# [0,0] TET PU_RY HR PU_VLT +.V +H_M_VREF +.V H_TET0 HR [,] PU_LT_RT#_R +.V Q00 PM0 /HT_EU R0 0KOhm /HT_EU +V PU_LT_RT#_R R0 % /HT_EU PU_PWR R0 % /HT_EU PU_REQ# R0 PU_RY.KOhm PU_TK PU_TM PU_TI PU_TRT# PU_REET PU_TO PU_REET [] /HT_EU +.V ebug 000 HT J000 N REQ_L RY REQ_L RY REQ_L RY REQ_L RY RY REQ_L REQ_L RY RY REQ_L 0 P_00_0_K 0 0 PU_REET H 0.UF/V HR KOhm HR KOhm H 000PF/0V RM Interface Voltage Reference PLE LOE TO PU H 0.UF/V HR H_TET_H H_TET_L HR [] PU_TI PU_TI [] PU_TM PU_TM [] PU_TK PU_TK Title onesus : NT//THERM N/ UTeK.omputer.IN T.0 Tuesday, ugust 0, 00 ate: heet of 0

6 +VORE +VORE +.V PU_VLT EIN NOTE: VLT must be routed as a pour or a trace at least 00 mils wide. VLT may be routed from the source to either Lx balls or Fx balls. hoose whichever makes routing simpler. These six capacitors must be placed very near the selected balls. The "other" set of balls must be decoupled with a.uf cap. 0 UF/.V E E E F F F H H J E J0 J J J J0 J J J K0 K K K K0 K K N L L L L M0 M R M N N W N P P +VORE U00E V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ 0 UF/.V V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ ottom side decoupling need check with M,EMO has *0nf, but check list has *.uf 00 0 UF/.V UF/.V E E E 0 E 0 Y Y Y W W0 W W E V V V V T0 T T T0 R R R R P P UF/V 0.UF/.V 00 0PF/0V M Y U N U N0 P R R0 R U U0 W W0 W Y 0 E 0 E E0 F 0 V P N M K L T Y U00F VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_0 VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_0 VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_0 VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VLT VLT VLT VLT VLT VLT VLT VLT VR VR VR VR VR VR VR VR VN_ VN_ VN_ VN_ VN_ VN_ VR RV RV RV RV RV RV RV RV RV F F F F L L L L K0 L0 M0 N0 H J M N P P.V +0.V +PU_VN. U00 V_ N V_ N V_ N V_0 V_ V_ V_ M V_ V_ V_ V_ V_ V_ V_0 0 V_ P0 V_ P V_ P V_ P V_ P V_ V_ V_ V_ V_ R V_ V_ V_ V_ V_ V_0 V_ R V_ R V_ R V_ R0 V_0 V_ 0 V_ V_ E0 V_ E V_0 F V_ F V_ R V_ T V_ T V_ F0 V_ T V_ T V_ T V_ U V_0 F V_ N V_ V_ V_ V_ V_ V_ N0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_00 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_ V_ V_ V_ W W V0 V M L V L L0 L L L L L L L L0 L K M K K K M K M K M J W J W J J0 M J U J U J U U J J J J J H H H H H0 J M 0 N M F F E F F E E E E E0 E E E H E E0 E H0 H H H 0 0 H J J W W Y0 Y Y J J J J Y0 Y K K Y U00H V_0 V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_00 V_0 V_0 V_0 V_ V_ V_0 V_0 V_ V_0 V_ V_ V_ V_0 V_0 V_0 V_ V_ V_ K K K K K 0 K K K J H L M M M M M M M N N M V_N should not ramp before.v +VORE +.V 00 UF/.V 00 UF/.V 00 UF/.V 0 UF/.V 0.0UF/V 0.UF/.V 0 0PF/0V +.V_PU_N_ L0 /00Mhz Irat= N/ PU_VLT ML 0PF/0V (00) NPO % 0 UF/.V 0 UF/.V H 0UF/.V c00_h H.uF/.V H0.uF/.V H 0.UF/V H 0.UF/V H 0.0UF/V H 0.0UF/V 0.UF/.V 0.UF/.V H UF/.V 0.uF/.V 0.uF/.V 0 0.UF/.V 0 0.UF/.V 0 0PF/0V 0 0PF/0V ML 0PF/0V (00) NPO % +.V LYOUT NOTE: ecoupling between PU and IMMs, Place close to PU as possible H0.uF/.V c00 H.uF/.V c00 H 0.UF/V H 0.UF/V 0PF/0V +0.V H.uF/.V c00 H.uF/.V c00 0.UF/.V 0.UF/.V 0.UF/.V 0.UF/.V 0PF/0V 0PF/0V +PU_VN H.uF/.V H UF/.V H UF/.V H UF/.V onesus Power N/ UTeK.omputer.IN T.0 Tuesday, ugust 0, 00 ate: heet of 0

7 H M H M0 H M H M H M H M H M H M H M H M H M H M H M H M H M0 H M H M H M H M H M H 0 H H H M H M H M H QP H QP H QP H M0 H QN H QN H QN H QP0 H QN0 H QP H QP H QP H QP H QN H QN H QN H QN H Q H Q H Q H Q H Q H Q H Q0 H Q H Q H Q H Q H Q H Q H Q H Q H Q H Q0 H Q H Q H Q0 H Q H Q H Q H Q H Q H Q H Q H Q H Q H Q0 H Q H Q H Q H Q H Q H Q H Q H Q0 H Q H Q H Q H Q H Q H Q H Q H Q0 H Q H Q H Q H Q H Q H Q H Q H Q H Q H Q H Q H Q0 H Q H Q H Q H Q H Q H Q H VREF_IMM H VREF_IMMQ H_PM_EXT_T#0_R H VREF_IMMQ H VREF_IMM MLK_RM [,] MT_RM [,] +V +.V +0.V +.V +0.V +.V +.V +.V +0.V +.V H M[..0] [] H QP[..0] [] H [..0] [] H QN[..0] [] H M[..0] [] H Q[..0] [] H LKN [] H LKP [] H LKP0 [] H LKN0 [] H #0 [] H KE [] H KE0 [] H # [] H WE# [] H OT0 [] H # [] H OT [] H R# [] H RMRT# [] H_PM_EXT_T#0 [] ate: heet of 0 Tuesday, ugust 0, 00 UTeK OMPUTER IN R O-IMM0.0 T ate: heet of 0 Tuesday, ugust 0, 00 UTeK OMPUTER IN R O-IMM0.0 T ate: heet of 0 Tuesday, ugust 0, 00 UTeK OMPUTER IN R O-IMM0.0 T 0 lose pin 00 Follow M emo R. change IMM0 to IMM 0.UF/V 0.UF/V R KOhm R KOhm 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0UF/.V c00_h 0UF/.V c00_h EVENT# 0 0 N N NP_N 0 NP_N 0 TET V V0 00 V 0 V 0 V V V V V V V V V V V V V V VP VREF VREFQ V V 0 V V V V V0 0 V V V V V V V V V V V0 V V V V V V 0 V V V V V0 V V V V V V V V V V 0 V0 V V V V V V V V V V V0 V VTT 0 VTT 0 IMM R_IMM_0P IMM R_IMM_0P.uF/.V.uF/.V 0.UF/V 0.UF/V HR KOhm HR KOhm 0UF/.V c00_h 0UF/.V c00_h 0.UF/V 0.UF/V 0.UF/V 0.UF/V R KOhm R KOhm R R 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0 0.UF/V 0 0.UF/V + E 00UF/.V + E 00UF/.V R0 KOhm R0 KOhm 0.UF/V 0.UF/V.UF/.V.UF/.V 0.UF/V 0.UF/V 0.UF/V 0.UF/V R KOhm R KOhm 0 0/P 0 /# # K0# 0 K# 0 K0 0 K 0 KE0 KE M0 M M M M M M 0 M Q0 Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q Q0 Q Q Q Q Q Q Q 0 Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q Q Q Q Q#0 0 Q# Q# Q# Q# Q# Q# Q# Q0 Q Q Q Q Q Q Q # 0# OT 0 OT0 WE# R# L 0 00 REET# 0 IMM R_IMM_0P 00 IMM R_IMM_0P 00 0.UF/V 0.UF/V

8 R O-IMM UTeK OMPUTER IN ustom T.0 ate: Tuesday, ugust 0, 00 heet of 0

9 UTeK OMPUTER IN R_TERMINTION ustom T ate: Tuesday, ugust 0, 00 heet of 0.0

10 [] [] ignal R0 RX0 R0 HT_RXLP.R ().K 0R HT_RXLN.R (VHT) HT_TXLP 00R.K 0R HT_TXLN HT_PU_TX[0..] HT_PU_TX#[0..] [] [] [] [] [] [] [] [] HT_PU_TX_LK0 HT_PU_TX_LK#0 HT_PU_TX_LK HT_PU_TX_LK# HT_PU_TX_TL0 HT_PU_TX_TL#0 HT_PU_TX_TL HT_PU_TX_TL# R00 HT_PU_TX0 HT_PU_TX#0 HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX HT_PU_TX# HT_PU_TX0 HT_PU_TX#0 HT_PU_TX Y HT_PU_TX# Y HT_PU_TX W HT_PU_TX# HT_PU_TX HT_PU_TX# W0 V V0 HT_PU_TX HT_PU_TX# U0 U HT_PU_TX U HT_PU_TX# U HT_PU_TX_LK0 HT_PU_TX_LK#0 HT_PU_TX_LK HT_PU_TX_LK# HT_PU_TX_TL0 HT_PU_TX_TL#0 HT_PU_TX_TL HT_PU_TX_TL# HT_RXLP HT_RXLN U00 Y HT_RX0P Y HT_RX0N V HT_RXP V HT_RXN V HT_RXP V HT_RXN U HT_RXP U HT_RXN T HT_RXP T HT_RXN P HT_RXP P HT_RXN P HT_RXP P HT_RXN N HT_RXP N HT_RXN T T M M R R0 HT_RXP HT_RXN HT_RXP HT_RXN HT_RX0P HT_RX0N HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RXLK0P HT_RXLK0N HT_RXLKP HT_RXLKN HT_RXTL0P HT_RXTL0N HT_RXTLP HT_RXTLN HT_RXLP HT_RXLN R0M PRT OF HYPER TRNPORT PU I/F HT_TX0P HT_TX0N HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TX0P HT_TX0N HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXLK0P HT_TXLK0N HT_TXLKP HT_TXLKN HT_TXTL0P HT_TXTL0N HT_TXTLP HT_TXTLN HT_TXLP HT_TXLN HT_PU_RX0 HT_PU_RX#0 HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX0 HT_PU_RX#0 HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX HT_PU_RX# HT_PU_RX_LK0 HT_PU_RX_LK#0 HT_PU_RX_LK HT_PU_RX_LK# HT_PU_RX_TL0 HT_PU_RX_TL#0 HT_PU_RX_TL HT_PU_RX_TL# HT_TXLP HT_TXLN HT_PU_RX_LK0 [] HT_PU_RX_LK#0 [] HT_PU_RX_LK [] HT_PU_RX_LK# [] HT_PU_RX_TL0 [] HT_PU_RX_TL#0 [] HT_PU_RX_TL [] HT_PU_RX_TL# [] 0 0 change R00 value change R00 value E E F F F F H H J J K K K K F 0 H J0 J J K L J M L M P P M H H L L0 M M P R R00 HT_PU_RX[0..] [] HT_PU_RX#[0..] [] UTeK.omputer.IN R0M-HT LINK I/F ustom T N/ ate: Tuesday, ugust 0, 00 heet 0 of 0.0

11 [] PIE_RXP_U.0 [] PIE_RXN_U.0 [] PIE_RXP0_MINIR [] PIE_RXN0_MINIR [] PIE_RXP_LN [] PIE_RXN_LN [0] PIE N_RX0P [0] PIE N_RX0N [0] PIE N_RXP [0] PIE N_RXN [0] PIE N_RXP [0] PIE N_RXN [0] PIE N_RXP [0] PIE N_RXN U00 FX_RX0P FX_RX0N FX_RXP FX_RXN FX_RXP FX_RXN E FX_RXP F FX_RXN FX_RXP FX_RXN H FX_RXP H FX_RXN J FX_RXP J FX_RXN J FX_RXP J FX_RXN L FX_RXP L FX_RXN M FX_RXP L FX_RXN P FX_RX0P M FX_RX0N P FX_RXP M FX_RXN R FX_RXP P FX_RXN R FX_RXP R FX_RXN P FX_RXP P FX_RXN T FX_RXP T FX_RXN E PP_RX0P PP_RX0N E PP_RXP PP_RXN PP_RXP PP_RXN V PP_RXP W PP_RXN U PP_RXP U PP_RXN U PP_RXP U PP_RXN _RX0P Y _RX0N _RXP Y _RXN _RXP _RXN W _RXP Y _RXN R0M PRT OF PIE I/F FX PIE I/F PP PIE I/F FX_TX0P FX_TX0N FX_TXP FX_TXN FX_TXP FX_TXN FX_TXP FX_TXN FX_TXP FX_TXN FX_TXP FX_TXN FX_TXP FX_TXN FX_TXP FX_TXN FX_TXP FX_TXN FX_TXP FX_TXN FX_TX0P FX_TX0N FX_TXP FX_TXN FX_TXP FX_TXN FX_TXP FX_TXN FX_TXP FX_TXN FX_TXP FX_TXN PP_TX0P PP_TX0N PP_TXP PP_TXN PP_TXP PP_TXN PP_TXP PP_TXN PP_TXP PP_TXN PP_TXP PP_TXN _TX0P _TX0N _TXP _TXN _TXP _TXN _TXP _TXN PE_LRP PE_LRN E E F F F F H H H H J J K K K K M M M M N N P P Y Y Y Y V V E E E PIEN_TXP PIEN_TXN PIEN_TXP PIEN_TXN PIEN_TXP PIEN_TXN PIEN_TXP PIEN_TXN PP_TX0P_ 0.UF/0V PP_TX0N_ PP_TXP_ 0.UF/0V PP_TXN_ PP_TXP_ 0 PP_TXN TX0P TX0N TXP TXN TXP TXN TXP TXN_ PE_LRP PE_LRN 0 dd net name 0.UF/0V 0.UF/0V 0 0.UF/0V 0.UF/0V 0 0.UF/0V UF/0V 0 0.UF/0V 0 0.UF/0V 0 change P/N 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V PIE 0 PIE PIE 0 0.UF/0V 0 0.UF/0V 0 0.UF/0V 0.UF/0V 0 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V.KOhm R0 +.V_N KOHM R0 UTeK.omputer.IN U.0 VI_TX+ [] VI_TX- [] VI_TX+ [] VI_TX- [] VI_TX+ [] VI_TX- [] VI_LK+ [] VI_LK- [] PIE_TXP0_MINIR [] PIE_TXN0_MINIR [] PIE_TXP_LN [] PIE_TXN_LN [] PIE_TXP_U.0 [] PIE_TXN_U.0 [] EL, dd U.0 PIE_N TX0P [0] PIE_N TX0N [0] PIE_N TXP [0] PIE_N TXN [0] PIE_N TXP [0] PIE_N TXN [0] PIE_N TXP [0] PIE_N TXN [0] R0M-PIE LINK I/F RE REEN LUE LK N/ ustom T ate: Tuesday, ugust 0, 00 heet of 0.0

12 E E notice L0 L0 change L? 00 +.V L0 /00Mhz VHTPLL +V L0 /00Mhz V L0 /00Mhz VPIEPLL 000 [] [] [] RT_RE RT_REEN R. +.V_N RT_LUE hange to +.V_N form N_V_MUX V R0.KOhm TRP_T 0 V_N.0V.V 0OHM R0 R0 % R0 % R0.KOhm JP0 HORT_PIN JP0 HORT_PIN JP0 HORT_PIN +.V_N L0 [] [] [] EI_T [] EI_LK [] VI_T [] VI_LK [,] [,] [] [] RT_RE_N L0 RT_REEN_N RT_LUE_N N_PWR N_O +.V +.V RT_HYN RT_VYN RT T RT LK R. 0 +V for HMI +.V R. 000 L0 /00Mhz /00Mhz 0.UF/0V [0] L 00 EI_T EI_LK RT_RE_N RT_REEN_N RT_LUE_N PLLV 0.UF/.V N_RT# +.V R.0000 hange N_LLOW_LTTOP to LLOW_LTTOP /00Mhz n/a RN.KOHM RN.KOHM N/.UF/0V UF/0V VI VQ_L 0.UF/0V R0 PLLV 0 VHTPLL.UF/0V VPIEPLL N_PWR N_LT_TOP# LLOW_LTTOP R_N_HT_LKP R_N_HT_LKN N_REFLKP N_REFLKN R_N_FX_REFLKP R_N_FX_REFLKN T0 TPT T0 TPT R_N_PIE_RLKP R_N_PIE_RLKN T TPT Ohm F E F H H E F F E F E F E F H E 0 0 E F T T U U V V 0 U00 V V VI VI VQ VQ REERVE REERVE REERVE REERVE RE RE# REEN REEN# LUE LUE# _HYN _VYN L _RET PLLV PLLV PLLV VHTPLL VPIEPLL VPIEPLL YREET# POWEROO LTTOP# LLOW_LTTOP HT_REFLKP HT_REFLKN REFLK_P REFLK_N FX_REFLKP FX_REFLKN PP_REFLKP PP_REFLKN PP_REFLKP PP_REFLKN I_T I_LK _T0/UX0N _LK0/UX0P _LK/UXP _T/UXN TRP_T PRT OF RT/TVOUT LOKs PM PLL PWR LVTM MI. 0.UF/0V TXOUT_L0P TXOUT_L0N TXOUT_LP TXOUT_LN TXOUT_LP TXOUT_LN TXOUT_LP TXOUT_LN TXOUT_U0P TXOUT_U0N TXOUT_UP TXOUT_UN TXOUT_UP TXOUT_UN TXOUT_UP TXOUT_UN TXLK_LP TXLK_LN TXLK_UP TXLK_UN VLTP VLTP VLT_ VLT_ VLT_ VLT_ VLT VLT VLT VLT VLT VLT VLT LV_ION LV_LON LV_EN_L TM_HP HP U_TT# THERMLIOE_P THERMLIOE_N TETMOE 0.UF/0V E0 E F 0 E T0 TPT T0 TPT 0 R T TPT xr LV_K_EN VLTP_PLL_L 0.UF/0V L_TP0 [] L_TN0 [] L_TP [] L_TN [] L_TP [] L_TN [] L_LKP [] L_LKN [] VLTP_L.UF/.V L0 LV_V_EN [] LV_K_EN [] L0 0.UF/0V N_TM_HP [] U_TT# [] /00Mhz +.V +.V /00Mhz for HMI UX_L [,0] PU_LT_TOP# Q0 PM0 R 0KOhm R0 KOhm 0.UF/0V N_LT_TOP# R. for M review R % R0M R %.KOHM N_THRM N_THRM T0 TPT T0 TPT 0 U0 N V Y LV0W +.V R.0 change R0 tok [] R_N_HT_LKP [] R_N_HT_LKN EL serial R 0 for measurement near U00 have via for measurement T TPT R_N_HT_LKP R_N_HT_LKN [0] LLOW_LTTOP R KOhm [] R_N_FX_REFLKP [] R_N_FX_REFLKN T0 TPT T TPT R_N_FX_REFLKP R_N_FX_REFLKN T TPT for external graphic? NEE HEK T TPT +.V +V [] R_N_PIE_RLKP [] R_N_PIE_RLKN R_N_PIE_RLKP R_N_PIE_RLKN T TPT 00M FOR LINK NEE HEK R 0KOhm R.KOhm [,] PU_LT_RT#_R Q0 PM0 N/ R0 _N_RT# N_RT# R0M-Y I/F N/ UTeK.omputer.IN T.0 Tuesday, ugust 0, 00 ate: heet of 0

13 FT_PIO: LO_EEPROM_TRP elects Loading of TRP from EPROM E V E E Y E W Y V V W E U00 PR OF MEM_0 MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_0 MEM_ MEM_ MEM_ MEM_0 MEM_ MEM_ MEM_R# MEM_# MEM_WE# MEM_# MEM_KE MEM_OT MEM_KP MEM_KN MEM_OMPP MEM_OMPN _MEM/VO_I/F MEM_Q0 MEM_Q MEM_Q MEM_Q MEM_Q MEM_Q MEM_Q MEM_Q MEM_Q MEM_Q MEM_Q0 MEM_Q MEM_Q MEM_Q MEM_Q MEM_Q MEM_Q0P MEM_Q0N MEM_QP MEM_QN MEM_M0 MEM_M IOPLLV IOPLLV IOPLLV MEM_VREF 0 Y V Y 0 E 0 Y W 0 E W E E E E +.V +.V_N : ypass the loading of EEPROM straps and use Hardware efault Values 0 : I Master can load strap values from EEPROM if connected, or use default values if not connected R0:U_TT TRP_EU_U_PIE_ENLE Enables the Test ebug us using PIE bus: : isable ( an still be enabled using nbcfg register access ) 0 : Enable R0: configurable thru register setting only R0/R0: Enables ide port memory R0:HYN# elects if Memory IE PORT is available or not = Memory ide port Not available 0 = Memory ide port available Register Readback of strap: N_LKF:LK_TOP_PRE_[] R0M [,] RT_VYN R KOhm R KOhm +V [,] RT_HYN R KOhm +V /NoidePort R0M-PMEM/TRP N/ UTeK.omputer.IN T.0 Tuesday, ugust 0, 00 ate: heet of 0

14 VPIE VHTTX V_MEM_L +.V_N +.V_PU_N_ +.V +.V +V +.V_N +V_N ate: heet of 0 Tuesday, ugust 0, 00 UTeK.omputer.IN R0M-POWER.0 T N/ ate: heet of 0 Tuesday, ugust 0, 00 UTeK.omputer.IN R0M-POWER.0 T N/ ate: heet of 0 Tuesday, ugust 0, 00 UTeK.omputer.IN R0M-POWER.0 T N/.V(R0)/.V(RX0;R0) 00 m 00 delete R hange to +.V_N form N_V_MUX hange to 00 from 0 R. 000 R. 00 hange the N Part number to R0 () XR XR XR XR cost remove,0 0.uF reserved V_N should not ramp before.v.uf/.v.uf/.v 0 0.UF/0V 0 0.UF/0V 0UF/.V 0UF/.V 0.UF/0V 0.UF/0V 0 UF/.V 0 UF/.V 0UF/.V 0UF/.V.UF/.V.UF/.V 0.UF/0V 0.UF/0V 0 0.UF/0V 0 0.UF/0V 0.UF/0V 0.UF/0V 0 0.UF/0V 0 0.UF/0V.UF/.V.UF/.V L0 /00Mhz L0 /00Mhz 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0UF/.V N/ 0UF/.V N/ 0.UF/0V 0.UF/0V 0 0.UF/0V 0 0.UF/0V VHT J VHT K VHT L VHT M VHT P VHT R VHT T VHTTX E VHTTX VHTTX VHTTX VHTTX VHTTX Y0 VHTTX W VHTTX V VHTRX H VHTRX VHTRX F0 VHTRX E VHTRX V_ F V_ V_MEM E V_MEM VPIE J0 VPIE P0 VPIE K0 VPIE0 Y VPIE VPIE VPIE VPIE E VPIE W VPIE H VPIE VPIE VPIE VPIE VPIE E VPIE F VPIE VPIE H VPIE J VPIE M0 VPIE L0 V K V J V U VPIE M V J V K VPIE0 K V M V L V L V M V0 M V N V N V P V P V P V R V R V T V T V0 U V T V_ H V_ H V_MEM E0 V_MEM V_MEM Y V_MEM 0 V_MEM 0 V_MEM 0 VPIE T0 V J VPIE L VPIE R0 VPIE P VPIE R VPIE T VPIE V VPIE U VPIE U0 VHTRX VHTRX VHTTX U VHTTX0 T VHTTX R VHTTX P VHTTX M PRT / POWER U00E R0M PRT / POWER U00E R0M 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/.V 0.UF/.V 0 UF/.V 0 UF/.V 0.UF/.V 0.UF/.V 0.UF/0V 0.UF/0V L0 /00Mhz L0 /00Mhz 0.UF/.V 0.UF/.V 0.UF/0V 0.UF/0V UF/.V UF/.V VHT VHT VHT E VHT VHT VHT VHT H VHT J VHT L VHT0 L VHT L VHT L VHT M0 VHT N VHT P0 VHT R VHT R VHT R VHT R VHT U VHT V VHT W VHT W VHT W VHT Y VHT V V V E V0 E V J V K V M V L V L V M V N V P V P V R V R V T V U V0 U V U V V V W V W V V V Y V V V0 V V E0 VPIE VPIE VPIE VPIE VPIE E VPIE VPIE VPIE VPIE H VPIE0 J VPIE R VPIE L VPIE L VPIE L VPIE L V K VPIE M VPIE N VPIE P VPIE R VPIE0 R VPIE R VPIE V VPIE U VPIE V VPIE V VPIE W VPIE W VPIE W VPIE W VPIE0 W VPIE Y VPIE VPIE VPIE VPIE VPIE VPIE VPIE E VPIE E VPIE0 V E VHT0 H0 V V J PRT / ROUN U00F R0M PRT / ROUN U00F R0M 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0 0.UF/0V 0 0.UF/0V 0 0.UF/0V 0 0.UF/0V

15 heck PIE_RT# T0 TPT [] PIE N_RX0P [] PIE N_RX0N [] PIE N_RXP [] PIE N_RXN [] PIE N_RXP [] PIE N_RXN [] PIE N_RXP [] PIE N_RXN 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V _RT# 00 0.UF/0V UF/0V UF/0V UF/0V 00 _RX0P RX0N RXP RXN RXP RXN RXP RXN_ U00 N _RT# V PIE_TX0P V PIE_TX0N V PIE_TXP V PIE_TXN U PIE_TXP U PIE_TXN T PIE_TXP T PIE_TXN 00 Part of PI LK PILK0 P PILK P PILK P PILK P PILK T PILK/PIO T PIRT# N PI_LK0 PI_LK LK_PI_R LK_PI_R PI_LK_R PI_LK_R T00 TPT R00 R0 T0 TPT T0 TPT Ohm Ohm LK_PI [] LK_PI [,] PI_LK [] PI_LK [] +.V_PU_N_ [] PIE_N TX0P [] PIE_N TX0N [] PIE_N TXP [] PIE_N TXN [] PIE_N TXP [] PIE_N TXN [] PIE_N TXP [] PIE_N TXN R00 % Ohm PIE_LRP PIE_VR PIE_LRN L00 R00.0KOHM PIE_PV_L /00Mhz 00.UF/0V R_N_PIE_RLKP_R [] R PIE_RLKP R_N_PIE_RLKN_R [] R PIE_RLKN [] _O T0 TPT T0 U U U V R0 R R R T T P P N N K K M M P M M M J J L0 L M M0 N P L J J0 PIE_RX0P PIE_RX0N PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_LRP PIE_LRN PIE_PV PIE_PV PI EXPRE INTERFE PIE_RLKP/N_LNK_LKP PIE_RLKN/N_LNK_LKN N_IP_LKP N_IP_LKN N_HT_LKP N_HT_LKN PU_HT_LKP PU_HT_LKN LT_FX_LKP LT_FX_LKN PP_LK0P PP_LK0N PP_LKP PP_LKN PP_LKP PP_LKN PP_LKP PP_LKN M_M_M_O M_X M_X LOK ENERTOR PI INTERFE 0 U P V T V U V V T W 0 T R R R U U Y W V Y 0 Y Y Y 0 E0# W E# U E# E# Y FRME# EVEL# W IRY# TRY# Y PR U TOP# W PERR# W ERR# V REQ0# REQ# REQ# REQ#/PIO0 E REQ#/PIO NT0# NT# E NT# NT#/PIO NT#/PIO E LKRUN# LOK# V INTE#/PIO INTF#/PIO INT#/PIO E INTH#/PIO E PIO PIO TPT T0 TPT T0 _RT# TPT T0 TPT T0 TPT T0 TPT T00 TPT T0 TPT T0 TPT T0 TPT T0 TPT T0 TPT T0 TPT T0 T0 TPT R0.KOhm R00 U00 N V Y LVW +VU R0 Ohm N_RT# [] R0 Ohm UF_PLT_RT# [,,0,,0,] T0 TPT PIO PIO [] PIO PIO [] PIO PIO [] LP_LKE TPT K_XIN K_XOUT X X RT XTL LP LPLK0 LPLK L0 L L L LFRME# LRQ0# LRQ#/NT#/PIO MREQ#/REQ#/PIO ERIRQ E H H J J H H V LP_LK0_R LP_LK_R PIO R0 TPT T0 TPT T0 TPT T0 LP_LKEU [] Ohm LP_LKE [,0] LP_0 [0,] LP_ [0,] LP_ [0,] LP_ [0,] LP_FRME# [0,] INT_ERIRQ [0] 0 0PF/0V RT power. [] [] LLOW_LTTOP PU_PROHOT# [,] PU_LT_TOP# [,] PU_LT_RT# PU_PWR F F F LLOW_LTTP PROHOT# LT_P LT_TP# LT_RT# 00 PU RT RTLK INTRUER_LERT# VT INTRUER_LERT# TPT T0 VT T00 TPT 0 0.UF/0V RT_LK [] 0 UF/.V 00 R0 TPT T0 JRT L_JUMP T0 TPT 00 RF R0 R0 KOhm +V +RTT TPT T0 TPT T0 change 0,0 to pf 000 +RT_T 0 K_XIN [] HT_PU_PWR R. HNE % TO % +V +V R0 0KOhm Q00 UMKN R0 0KOhm Q00 [] PU_PWR PF/0V 0 PF/0V X00.Khz H=. mm N/ R0 0MOhm R0 K_XOUT change ctystal (0) _TT IE IE WTO_ON_P M RT_T UMKN N_RT# PU_PWR 0 0.UF/0V 00/00 dd 0 for N_RT# litch N/ UTeK.omputer.IN ize Project Name ustom T ate: Tuesday, ugust 0, 00 Rev.0 heet of _PU/PIE/LP/LK

16 00 R0 POWEROO is.v rail [] [,] MLK_RM [,] MT_RM [] N_PWR P_I0 internal pu.k P_I0 res. value 0k -> k to get LOW level < Vih(.V) R V 00 M review Z_IN0_U EMI 00 R.KOhm P_I [] ( I / PU ) R.KOhm R P_I R.KOhm U_MI# T T0 T0 T0 0 TPT TPT TPT TPT [0,] PF/0V /EMI T [] [] RF_W# [0] EXT_MI# [0] EXT_I# [0] PM_U# [0] PM_U# [0] PM_PWRTN# [] PM_PWROK [] U_TT# 0 [0] [0] T 0KOhm [] TPT 0TE R_IN# Y_RET# PM_RMRT# PIE_WKE# [] Z_IN0_U T TPT T0 TPT 0 TPT T T0 00 _THRMTRIP# TPT TPT RF_W# U_O# T T T TPT TPT R. dd Test Point PIO0 PIO PIO0 T 00 T0 T 0 TPT PIO0 PIO P_I TET TET TET0 TPT N_PWR_R 00 T TPT T TPT PIO PIO 0 P_I R_RT#_Via TPT R0 T T T0 TPT T TPT T TPT U_O0# Z_LK Z_OUT Z_YN Z_RT# PM#_VI TPT TPT TPT T0 TPT T0 TPT _PKR_R PI_# E E H F H H K H H H Y W K K F J H F J W E W V W0 W W K K 0 Y Y E F E M M J J L M L M L H H0 H F E E R. 00 hange the Part number to 00 () U00 00 Part of PI_PME#/EVENT# RI#/EXTEVNT0# ULK/M_M_M_O LP_/PM# LP_# U_ROMP LP_# PWR_TN# PWR_OO U_TT# TET U_FP TET U_FN TET0 0IN/EVENT0# U_FP KRT#/EVENT# U_FN LP_PME#/EVENT# LP_MI#/EXTEVNT# U_HP _TTE/EVENT# U_HN Y_REET#/PM# WKE#/EVENT# U_H0P LINK/PM# U_H0N MLERT#/THRMTRIP#/EVENT# N_PWR U_HP U_HN RMRT# U_HP U_HN T_I0#/PIO0 LK_REQ#/T_I#/PIO MRTVOLT/T_I#/PIO LK_REQ0#/T_I#/PIO0 LK_REQ#/T_I#/FNOUT /PIO LK_REQ#/T_I#/FNIN /PIO0 PKR/PIO L0/PO0# 0/PO# L/PO# /PO# _L/PIO _/PIO LL#/PIO MRTVOLT/HUTOWN#/PIO R_RT#/EVENT# U_O#/IR_TX/EVENT# U_O#/IR_TX0/PM# U_O#/IR_RX0/PM# U_O#/IR_RX/PM# U_O#/PM# U_O#/PM# U_O0#/PM0# Z_ITLK Z_OUT Z_IN0/PIO Z_IN/PIO Z_IN/PIO Z_IN/PIO Z_YN Z_RT# Z_OK_RT#/PM# IM_PIO0 IM_PIO PI_#/IM_PIO IE_RT#/F_RT#/IM_PO IM_PIO IM_PIO IM_PIO IM_PIO 00 H UIO U O INTERTE u PI / WKE UP EVENT INTERTE u U MI PIO U. U.0 U_HP U_HN U_HP U_HN U_HP U_HN U_HP U_HN U_HP U_HN U_HP U_HN U_HP U_HN U_H0P U_H0N IM_PIO IM_PIO IM_PWM0/IM_PIO0 L/IM_PIO /IM_PIO L_LV/IM_PIO _LV/IM_PIO IM_PWM/IM_PIO IM_PWM/IM_PO IM_PWM/IM_PO IM_PIO IM_PIO IM_PIO0 IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO0 IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO IM_PIO0 IM_PIO E E F E 0 dd net name H J0 E F 0 0 H E E H H F F E0 E E E _LK R U_ROMP R0.KOhm R. _LK R [] U_PP [] U_PN [] WLN conn. U_PP [] U_PN [] amera U_PP [0] U_PN [0] ard reader U_PP [] U_PN [] U.0 onn K UP U_PP [] U_PN [] U.0 onn K UP U_PP0 [] U_PN0 [] U.0 onn with charge LK [,0] T [,0] for TI _P [] _P [] U 0 External U U External U U U U U U ard reader U U MER U U 0 U WLN(Miniard) U U U U U_TT# R0.KOhm M review 0 +V U_TT# R0.KOhm MLK_RM.KOHM RN0 MT_RM.KOHM RN0 +VU RF_W# R0 0KOhm TET RN.KOHM TET RN.KOHM R. EMI R ohm change to ohm pf change to pf,mount TET0 RN.KOHM RN.KOHM +VU for strap PUT T 0M IE EXT_MI# EXT_I# RN0 0KOHM RN0 0KOHM [] Z_RT# EMI 00 Z_LK Z_RT# PF/0V R Ohm R Ohm Z_RT#_U Z_LK_U E enable trap Workaround Z_RT#_U [] Z_LK_U [] M review R 0KOhm Z_YN R Ohm Z_YN_U Z_YN_U [] Z_OUT R Ohm Z_OUT_U Z_OUT_U [] EMI 00 PF/0V /EMI UTeK.omputer.IN ustom T 00_PIO/U/H/PI N/ Tuesday, ugust 0, 00 ate: heet of 0.0

17 hange the Part number to 0 () U00 for T H [] T_TXP0 [] T_TXN0 [] T_RXN0 [] T_RXP0 0.0UF/V 0.0UF/V T_TXP0_R T_TXN0_R E 0 0 E0 0 E T_TX0P T_TX0N T_RX0N T_RX0P T_TXP T_TXN T_RXN T_RXP 00 Part of IE_IORY IE_IRQ IE_0 IE_ IE_ IE_K# IE_RQ IE_IOR# IE_IOW# IE_# IE_# Y Y Y Y R. change pf to pf 0 PF/0V +.V_PU_N_ L0 000 R0 N/ 0MOhm X0 Mhz /00Mhz Place T_L RE very close to ball of 00 R0 KOhm % % T_L [] T_LE# PLLV_T PLLV_T XTLV_T 0 PF/0V UF/.V T_X T_X 0.UF/0V T_TXP T_TXN E T_RXN T_RXP T_TXP E T_TXN T_RXN T_RXP E T_TXP T_TXN T_RXN E T_RXP T_TXP T_TXN E T_RXN T_RXP V T_L Y T_X T_X W T_T#/PIO PLLV_T W XTLV_T 00 T PWR ERIL T HW MONITOR IE_0/PIO IE_/PIO IE_/PIO IE_/PIO IE_/PIO IE_/PIO0 IE_/PIO IE_/PIO IE_/PIO IE_/PIO IE_0/PIO IE_/PIO IE_/PIO IE_/PIO IE_/PIO IE_/PIO0 PI_I/PIO PI_O/PIO PI_LK/PIO PI_HOL#/PIO PI_#/PIO LN_RT#/PIO ROM_RT#/PIO FNOUT0/PIO FNOUT/PIO FNOUT/PIO FNIN0/PIO0 FNIN/PIO FNIN/PIO TEMP_OMM TEMPIN0/PIO TEMPIN/PIO TEMPIN/PIO TEMPIN/TLERT#/PIO PI ROM T /00/ VIN0/PIO VIN/PIO VIN/PIO VIN/PIO VIN/PIO VIN/PIO VIN/PIO VIN/PIO0 V V E E0 0 E 0 0 E E F F U J PIO PIO PIO PIO PIO M M PIO M PIO P P R F PIO0 PIO_VI PIO TEMP_OMM PIO PIO PIO PIO U0_EL PIO PIO PIO0 T TPT T TPT T0 TPT P_I0 [] T TPT T TPT T TPT T TPT T TPT T0 TPT T TPT EHIEL#_ EHIEL#_ [] PIO T TPT T TPT T TPT T TPT U_HRE_ON_ [] T_ON/OFF# [] T TPT T TPT 0.UF/V WLN_LE [] T TPT T TPT +VU MINIR_EN# [] WLN_LE EHIEL#_ U_HRE_ON_ TEMP_OMM R0 R0 R0 00 R0 0KOhm 0KOhm 0KOhm +VU +V XTLV_T L0 HWM not Implemented: ecoupling caps not used. 0 trace at least 0mil wide /00Mhz 0.UF/0V UTeK.omputer.IN ustom T 00_PT/T N/ ate: Tuesday, ugust 0, 00 heet of 0.0

18 +V XR +.V_PU_N_ 0.UF/0V L0 +VU L 0UF/.V +.V_PU_N_ cost UF/.V L +V 000 cost.uf/.v 000 cost 000 cost 0UF/.V 000 cost 0 UF/.V UF/.V IE and Flash Interface Not Implemented: Tied to +.V_0. 0 UF/.V UF/.V UF/.V UF/.V 0.UF/0V 0.UF/0V PIE_VR 0.UF/0V 0.UF/0V V_T V_U 0.UF/0V 0 0.UF/0V change to 0uF hange the Part number to 0 () 000 R. 00 hange the Part number to 00 () U00 +.V_PU_N_ 00 L VQ_ V_ L U00E M VQ_ Part of V_ M T 0 VQ_ V_ M U VQ_ V_ N 000 cost UF/.V UF/.V 00 U VQ_ V_ P 0UF/.V 0.UF/0V 0.UF/0V V_ U VQ_ V_ P V_ V VQ_ V_ R V_ W VQ_ V_ R V_ Y VQ_ V_ T T0 V_T_ V_ F0 VQ_0 U0 V_T_ V_ VQ_ U V_T_ V_ H VQ_ U +.V_PU_N_ V_T_ V_ K V +.V_KV V_T_ V_ K V L0 V_T_ V_0 K W V_T_ V_ L Y V_T_ V_ L Y0 V KV_.V_ L Y 00 V_T_ V_ L0 V KV_.V_ L Y V_T_0 V_ L V KV_.V_ L Y V_T_ V_ L E V KV_.V_ L V_T_ V_ L UF/.V V_T_ V_ L V_T_ V_ M V_T_ V_ M0 V_T_ V_0 M V_T_ V_ M V_T_ V_ M POWER V_T_ V_ N E V_T_0 V_ N V_ N V_ P P PIE_VR_ P +.VLW_R L +VU V_ P PIE_VR_ V_ P0 P0 PIE_VR_ V_U_ V_ P P PIE_VR.V_ 00 V_U_ V_0 P R PIE_VR.V_ V_U_ V_ P R PIE_VR.V_ R V_U_ V_ R PIE_VR.V_ J V_U_ V_ R _.V_ J.UF/0V.UF/0V V_U_ V_ R _.V_ L V_U_ V_ R _.V_ L 000 V_U_ V_ R0 000 V_U_ V_ R E V_U_0 V_ R V_T_ F +.VLW_R L0 +.VU V_U_ V_ T V_T_ F V_U_ V_0 T V_T_ +.VU V_U_ V_ T V_T.V_ H 00 V_U_ V_ U V_T.V_ H V_U_ V_ U V_T_ J E V_U_ V_ V V_T_ J 000 cost UF/.V 0.UF/0V 0.UF/0V V_U_ V_ Y 0UF/.V J V_U_ V_ U_PHY_.V_ 0 J V_U_ V_ U_PHY_.V_ cost J V_U_0 V_ K0 L V_U_ V_ E K V_U_ V_0 E K +.V_U_PHY_R V_U_ K 00 V_U_ R. PIE_K_V_ P V_VREF PIE_K_V_0 R VTX_0 V_VREF E R0 KOhm +V HNE % TO % PIE_K_V_ R VTX_ VK_.V VTX_ VK_.V J L PIE_K_V_ T +V 0 PIE_K_V_ U VTX_ H VK_.V VTX_ VK_.V K PIE_K_V_ PIE_K_V_ U0 J /00Mhz PIE_K_V_ PIE_K_V_ V E VTX_ +V J F +.V_V VRX_0 V E PIE_K_V_ PIE_K_V_ V0 K F.UF/0V PIE_K_V_ PIE_K_V_ V VRX_ M F UF/0V TW PIE_K_V_ PIE_K_V_ W VRX_ M 00 HOTTKY TW-L OT- PIE_K_V_ PIE_K_V_ W VRX_ M PIE_K_V_ PIE_K_V_0 W VRX_ P PIE_K_V_ PIE_K_V_ W VRX_ F V VK Part of L 00 L V_PU_N_ PI/PIO I/O IE/FLH I/O -LINK I/O T I/O PLL LKEN I/O ORE.V_ I/O U I/O ORE 0 ROUN /00Mhz.UF/0V M review L +VU 0.UF/0V /00Mhz.UF/0V 0 00 move L and 00_POWER N/ UTeK.omputer.IN ustom T.0 Tuesday, ugust 0, 00 ate: heet of 0

19 Remove R0, R0,R R0, R, R0, R 000 NOTE: 00 H INTERNL K PULL UP REITOR FOR RT_LK +V +V +V +V +VU +VU R0 0KOhm R0 0KOhm R0 0KOhm R0 0KOhm 0 R0 0KOhm R.kOHM (PI_LK) [0] LK_PI (PI_LK) [0,] LK_PI [0] PI_LK [0] PI_LK 000 R. [0] LP_LKEU 00 (LP_LK0) [0,0] LP_LKE M review (LP_LK) [0] RT_LK [] Z_RT# [] _P [] _P REQUIRE TRP R0 0KOhm R 0KOhm R 0KOhm R 0KOhm R 0KOhm R 0KOhm EXT R 0KOhm R0.kOHM PI_LK PI_LK PI_LK PI_LK LP_LK0 LP_LK RT_LK Z_RT# P P PULL HIH OOTFIL TIMER ENLE UE EU TRP REERVE REERVE E ENLE LKEN ENLE INTERNL RT EFULT ENLE PI MEM OOT H,H = Reserved H,L = PI ROM PULL LOW OOTFIL TIMER ILE EFULT INORE EU TRP EFULT E ILE EFULT LKEN ILE EFULT EXT. RT (P on X, apply KHz to RT_LK) ILE PI MEM OOT EFULT L,H = LP ROM (efault) L,L = FWH ROM For 00 and later version 000 R. hange the Text omment UTeK.omputer.IN ustom T 00_TRP N/ ate: Tuesday, ugust 0, 00 heet of 0.0

20 +V VI_TX-_M VI_TX+_M VI_TX-_M VI_TX+_M VI_TX-_M VI_TX+_M VI_LK-_M VI_LK+_M lose to HMI ON(E Protection) IPZ0-T /E R0.KOhm IPZ0-T TM_H+ TM_H- TM_H+ TM_H- U0 TM_H+ TM_H- TM_H+ TM_H- U0 /E +V Q0 N N N N 0 N N N N 0 Q0 VI_TX-_M VI_TX+_M VI_TX-_M VI_TX+_M VI_TX-_M VI_TX+_M VI_LK-_M VI_LK+_M VI_T_M VI_LK_M +V 0 00 PJP0 MM_OPEN_MIL F0 0./V +V_HMI 0.UF/.V +V_HMI [] N_TM_HP R0 R0 +V.KOhm.KOhm /E RE REEN LUE LK 0 V R 00KOhm VI_T_M VI_LK_M VI_TX+_M VI_TX-_M VI_TX+_M VI_TX-_M VI_TX+_M VI_TX-_M VI_LK+_M VI_LK-_M VI_LK_M VI_T_M R0 0KOhm HMI ON HMI_ON P_ 0 P_ 0 0 P_ P_ HMI_ON_P 0X [] VI_T [] VI_LK R0 VI_T VI_LK.KOhm 0 0 0PF 0PF UMKN R R UMKN +V 0 V 0 V [] [] VI_TX- VI_TX+ R. RNX0 /00Mhz RNX0 L0 N/ VI_TX-_M VI_TX+_M [] VI_TX- RNX0 VI_TX-_M [] VI_TX+ R. /00Mhz RNX0 L0 N/ VI_TX+_M RE REEN LUE LK VI_TX+_M VI_TX-_M VI_TX+_M VI_TX-_M VI_TX+_M VI_TX-_M VI_LK+_M VI_LK-_M [] VI_TX- [] VI_TX+ R. RNX0 /00Mhz RNX0 L0 N/ VI_TX-_M VI_TX+_M +V Q0 N00 R0 R 00KOhm r00 R0 R0 R R R R0, R0, R0, R, R, R, R, R change to 0OHM R R [] VI_LK- [] VI_LK+ ustom T.0 ate: Tuesday, ugust 0, 00 heet of 0 R. R. EMI mount choke,unmount o ohm resistor RNX0 /00Mhz RNX0 L0 N/ VI_LK-_M VI_LK+_M UTek OMPUTER IN HMI N/

21 UTek omputer IN. luetooth N/ T ate: Tuesday, ugust 0, 00 heet of 0.0

22 [0,] [0,] LI_E_R# PWR_LE_UP YQ UMKN LI_E_R# YQ UMKN PWR_LE_UP /0, wap Pin, and, follow N PWRTN_LE [0,] PWR_W_E# [] PWR_W# [] U_MI# R. R0 /NO POWER LTH R0 +VU +.V PWR_W# U_MI#_R +V +V PWRTN_LE +VU +V0_U [] U_LK_ [] EHIEL#_ [0,,,,0] VU_ON [] U_PP [] U_PN [] LK_PIE_LN [] LK_PIE_LN# [] PIE_TXN_LN [] PIE_TXP_LN [] PIE_RXP_LN [] PIE_RXN_LN [] PIE_TXP_U.0 [] PIE_TXN_U.0 [] PIE_WKE# [,0,0,,0,] UF_PLT_RT# [] U_PP [] U_PN T0 TPT [] Z_IN0_U [] Z_LK_U [] Z_OUT_U [] Z_YN_U [] Z_RT#_U [0] OP_# [] H_NE_U_LK [] H_NE_U_LK# [] PIE_RXP_U.0 [] PIE_RXN_U.0 [] _MI_LK_R [] _MI_T_R _LN_M_R U_LK_ FP_P_HOL IE IE +V_U +V0_U J0 +VU_U PJP MM_OPEN_MIL PJP0 MM_OPEN_MIL UTek omputer IN. T mall brd onn N/ ate: Tuesday, ugust 0, 00 heet of 0.0

23 _LK R hange to small One follow 0P U_LK_ R0 MOhm R_LK_ N_O X0 XTL_LK XTL_LK _O 0 PF/0V.Mhz 0 PF/0V +.V_LK 0PF/0V 0PF/0V 0PF/0V 0PF/0V 0PF/0V R0 +.V_LK 0KOhm N REF [0] [] N_O _O U Ohm [] _LK R [] U_LK_ [0] R_LK_ U.0 WLN LN [] H_NE_U_LK# [] H_NE_U_LK [] LK_PIE_MINIR# [] LK_PIE_MINIR N/ [] LK_PIE_LN# [] LK_PIE_LN T0 TPT R 0N-.Mhz R.Ohm N/ % R N_O_EN EL_HTT XTL_LK XTL_LK R Ohm R0 LK R R Ohm R [,] MLK_RM R [,] MT_RM N/ N/ L0 L L0 L R0 R LK_PIE_U#_EN LK_PIE_U_EN LK_PIE_MINIR#_EN LK_PIE_MINIR_EN Ohm LK_PIE_LN#_EN Ohm LK_PIE_LN_EN LK_REQ_LN# +.V_LK VU_LK U0 REF **EL_/REF **EL_HTT/REF0 VREF REF VHTT X HTT0T/M X HTT0/M V HTT Mz_ *P# 0 PUK_0T MLK PUK_0 0 MT VPU VOT PU R/M_N **LKREQ# RT/M_ **LKREQ# OT V R RT T R VT 0 R **LKREQ# RT _R0T 0 VR _R0 R V_R R _R RT _RT R0 _R R0T TIT **LKREQ0# TI TI VTI 0 TIT TI RTM0T--V-RT N/ +.V_LK EL_ VREF_LK R_N_HT_LKP_EN R_N_HT_LKN_EN P# R_PU_HT_LKP_EN R_PU_HT_LKN_EN R_N_PIE_RLKP_EN R_N_PIE_RLKN_EN R PIE_RLKP_EN L R PIE_RLKN_EN L R_N_FX_REFLKP_EN L R_N_FX_REFLKN_EN L L0 L0 L L V_LK L L N/ N-HT R_N_HT_LKP [] R_N_HT_LKN [] PU R_PU_HT_LKP [] R_PU_HT_LKN [] LKREQ#_MINIR [] R_N_PIE_RLKP [] R_N_PIE_RLKN [] P# N R PIE_RLKP [0] R PIE_RLKN [0] R_N_FX_REFLKP [] R_N_FX_REFLKN [] IPLY LK_REQ_LN# LKREQ#_MINIR +.V_LK R0 0KOhm R0 0KOhm EL_HTT EL_ R0.KOhm N/ +.V_LK R0.KOhm R.KOhm R.KOhm +V L0 00 M review 0/00Mhz N/ 0 0.UF/V 00 00m+0m +.V_LK 0 0.UF/V 0.UF/V 0.UF/V N/ N/ N/ N/ 0m 0m +V VU_LK +V VREF_LK +V V_LK L0 L0 L0 0/00Mhz 0/00Mhz 0/00Mhz N/ N/ N/.UF/0V 0.UF/V 0UF/.V.UF/0V 0.UF/V UF/.V 0.UF/V R EL_ EL_HTT MHz differential spreading R clock MHz non-spreading singled clock on pin MHz spread clock on pin. 00 MHz differential HTT clock MHz.V single ended HTT clock N/ N/ N/ N/ N/ N/ UF/.V 0.UF/V 0.UF/V 0.UF/V 0.UF/V N/ N/ N/ N/ N/ RTM0T--V-RT UTeK OMPUTER IN N/ ustom T ate: Tuesday, ugust 0, 00 heet of 0.0

24 +V [0] INT_ERIRQ [0,] LP_FRME# [0,] LP_LKE [] H_LE_REEN# [0,] LP_0 [0,] LP_ [0,] LP_ [0,] LP_ [] R_IN# [] EXT_I# [] 0TE [,0,,,0,] UF_PLT_RT# [] [] OT0 OT O 0UF/.V KO[:0] KI[:0] [] aps_le# [,0] U_HRE_EN_E [] [] TP_LK TP_T attery [0,] _MLK [0,] _MT Thermal ensor [0] M_LK [0] M_T [,] MRTHON_E# [] H_LE_ORNE# [,] PWR_LE_UP OT OT0 O 0.UF/V OT OT KO0 KO KO KO KO KO KO KO KO KO KO0 KO KO KO KO KO N_KO N_KO KI0 KI KI KI KI KI KI KI E E OT LP_0 LP_ LP_ LP_ E_RT# RL_LE# U_HRE_EN_E PWR_LE_UP E E HOTKEY_W0# - HOTKEY_W# internal PU ERIRQ LFRME# PILK LKRUN# 0 L0 L L L KRT# 0 I# 0 PIRT# OU ERT# KO0 0 KO KO KO KO KO KO KO KO KO KO0 0 KO KO KO KO KO KO KO KI0 KI KI KI KI 0 KI KI KI PIO PIO PIO PLK0 PT0 PLK PT PLK PT L L 0 OR RF_W# HOTKEY_W# PIO0 [,] RF_W# PIO0 [] EXT_MI# PIO0 [,] PWRLIMIT# [,] LI_E_R# PIO0 OT TPLE# PIO0 OT LI_E_L# PIO0 PIO0 [,] PWR_W_E# PIO [] _OK PIO0 [] E_RMRT# PIO [] T_IN OR PI [] U_detect# OT PI PIO0 O 0.UF/V O 0.UF/V O 0.UF/V 0 PIO PIO PIO PIO K0QF O 0.UF/V LP I/F Key Matrix can M U PIO LE P I/F VER: O 0.UF/V V V V V V V V V/ V PWM / FN PI I/F URT 0 PWM0 PWM PIO PIO FNPWM0 FNPWM FNF0 FNF PO PO PO 0 POE POF PXIO00 PXIO0 PXIO0 PXIO0 00 XIO PXIO0 0 PXIO0 0 PXIO0 0 PXIO0 0 PXIO0 0 PXIO0 0 PXIO0 0 PXIO 0 PXIO0 0 PXIO 0 PXIO PXIO XIO PXIO PXIO PXIO PXIO MIO MOI 0 PILK PI# PIO 0 PIO PIO XLKI XLK XLKO VR +V OL +V T_ T_ T_ T_ L_PWM_ TEL# E FN0_PWM FN_PWM FN0_TH FN_TH PM_TLOW# PI_MOE# P-ON T_LERN T # VRM_PWR_E OR OR PI_LK_R OL0 /00Mhz E_TX E_RX K_XLKI K_XLKO K_VR /00Mhz +V_E +V_E OT O 0UF/.V OT OT OT OT [] L_PWM_ [] OT PM_PWRTN# [] OT OT L_KOFF# [] PI_O [] PI_I [] PI_LK [] PI_# [] O PF/0V [,0] FORE_OFF# +V OR VRM_PWR_E OT U_ON [,] VU_ON [,,,,0] PU_VRON [,0] U_ON [,,0] E_PWROK [] PM_LEVELOWN# [,,,,] H_EN# [] P-ON [] PI_WP# [] OP_# [] OT OT THRO_PU [] PM_U# [] PM_U# [] VRM_PWR FN0_PWM [0] FN0_TH [0] VU_PWR [,,] T T T OT OT O.UF/.V O 0.UF/V FOR RF N/ OR OT 00KOHM O0 UF/0V PU_LEVELOWN# [,,,] Hotkey Table Item OU OUT V N Pin Name 0 HOTKEY_W0# E E E E OR N/ RNV-TR-F +V E_RT# R_IN# OR 0KOhm 0TE OR 0KOhm INT_ERIRQ OR 0KOhm E [] E [] E [] E [] Function Home +V K_XLKI PM_PWRTN# TP_T TP_LK M_T M_LK PWRLIMIT# _MLK _MT MRTHON_E# PWR_W_E# R. change to pull down O 0.UF/V U_detect# OR 0KOhm /HRE PM_LEVELOWN# OR 0KOhm N/ PU_LEVELOWN# OR 0KOhm N/ T_IN _OK PM_U# PM_U# E_RT# PI_MOE# UTek omputer IN. +V 00KOHM ORN 00KOHM ORN ate: Tuesday, ugust 0, 00 heet 0 of 0 K_XLKO +VU +V +V +V R. T 0KOhm ORN 0KOhm ORN 0KOhm ORN.KOhm RN OR 0MOhm OX.Khz L 00 O PF/0V OR 0KOhm OR 00KOhm 00KOHM ORN 00KOHM ORN OR O OR 00KOHM 0KOhm ORN OR 00KOHM.KOhm RN KOHM 0.UF/V OR.KOhm N/ O PF/0V E_ENE K0 N/.0

25 follow 0T K_ON IE 0 0 IE KO KO0 KO KO KO KO KO KO KO KO0 KO KI KI0 KI KI KI KI KI KI KO KO KO KO KO +V +V_TP L [0] TP_LK [0] TP_T UF/0V 0 0.UF/V E PF/0V /EMI TP_L TP_L TT_WITH_P 000K +V_TP TOUH_P TP_R IE TP_L 0 0 IE E FP_ON_P PF/0V /EMI 00 TP_R TP_R 0.UF/V TT_WITH_P 000K For Touch-Pad 0.UF/V FP_ON_P For Keyboard onnector KO[:0] [0] KI[:0] [0] R. YR0 /NO POWER LTH MRTHON_E# [0,] RF_W# [,0] KI KI KI KO KI0 KI KI KI KO KO KO KO KO KO0 KO KI KO KO KO KO KO KO0 KO KO FOR RF and EMI N 0PF/0V N 0PF/0V N 0PF/0V N 0PF/0V N 0PF/0V N 0PF/0V N 0PF/0V N 0PF/0V N 0PF/0V N 0PF/0V N 0PF/0V N 0PF/0V N 0PF/0V N 0PF/0V N 0PF/0V N 0PF/0V N 0PF/0V N 0PF/0V N 0PF/0V N 0PF/0V N 0PF/0V N 0PF/0V N 0PF/0V N 0PF/0V EXP TT_WITH_P 000K MRTHON# R. EL PWR Y 0.UF/V N/ MRTHON# [] EXPRE TE & HE WFI_ON_OFF TT_WITH_P 000K UTek omputer IN. WLN_ON/OFF T Y 0.UF/V N/ K_Touch Pad N/ ate: Tuesday, ugust 0, 00 heet of 0.0

26 For ebug Resolve auto-boot issue +VU [0,0] LP_0 [0,0] LP_ [0,0] LP_ [0,0] LP_ [0,0] LP_FRME# [0,] LK_PI LP_0 LP_ LP_ LP_ +V 0 EU_ON IE 0 IE FP_ON_P 00 /EU [0,,] VU_PWR [0] E_RMRT# [0,,] VU_PWR [0] E_PWROK O TW TW O TW +V OR 0KOhm OR 0KOhm PM_RMRT# [] PM_PWROK [] PI ROM +V R +V_PI PI_WP# PI_HOL# 0KOHM RN 0KOHM RN +V_PI E_RMRT# L0 00 OR 0KOhm PM_RMRT# el +V_PI L0 U [0] PI_# 00 # V PI_HOL# [0] PI_O O(IO) HOL#(IO) [0] PI_WP# WP#(IO) LK PI_LK [0] I(IO0) PI_I [0] WQ0VI +V_PI 0.UF/V L0 E_PWROK 00 OR 0KOhm PM_PWROK 0PF/0V PF/0V /RF 0PF/0V UTek omputer IN. PI ROM/ ebug N/ T.0 ate: Tuesday, ugust 0, 00 heet of 0

27 UTek omputer IN T R/R N/ ate: Tuesday, ugust 0, 00 heet of 0.0

28 UTek omputer IN. T RJ N/ ate: Tuesday, ugust 0, 00 heet of 0.0

29 RN 0OHM [] [] U_PP U_PN RN 0OHM UPP L /00Mhz UPN [] [] _MI_LK_R _MI_T_R _MI_LK_R _MI_T_R +V +V_MER R0 +V R TPT T +V_MER +V_MI +V L 00 N/ +V_MI 0.UF/V 0UF/0V 0.UF/V 0 UF/V _MI_LK_R _MI_T_R UPP UPN 0PF/0V 0PF/0V amera_mi_on IE 0 IE WTO_ON_P 0000 UPP VI/O VI/O UPN +V VU _MI_LK_R VI/O _MI_T_R VI/O IP-Z UTek omputer IN. T.0 ate: Tuesday, ugust 0, 00 heet of 0 MO N/

30 NOTE V:00000 V:0000 UTek omputer IN. L N/ T ate: Tuesday, ugust 0, 00 heet of 0.0

31 UTek omputer IN. MI_HP_PK N/ T ate: Tuesday, ugust 0, 00 heet of 0.0

32 +.V_ From E [0] E V PU_LT_RT#_R U0 NLVPWR PU_LT_RT#_R [,] R PU_LT_RT# [,0] % / To HT Header To PU & N O Function R0 % / PU_REET [] Reserve Pull high onnect with PU ebug Port +.V [] [] PU_TM PU_TI E irect Route PU_TM PU_TI PU_TK R0 / R0 / R0 / KOhm KOhm KOhm [] PU_TK PF/0V / PU_TM PU_TI PU_TK OR0 / OR0 / OR0 / E E E E _TO R0 /.KOhm R0 +V onnect with OR E R0 [0] PIO % / R0 [0] E % / _TK +.V_ V U0 NLVPWR +.V +.V R0 +.V_ /.KOhm _TM R0 /.KOhm _TK R0 /.KOhm +.V_ R0 [0] [0] PIO E R0 % / R0 _TO V U0 NLVPWR 0.UF/V UF/.V % / +.V_ [0] [0] PIO E R0 % / R0 % / _TM 0 V U0 NLVPWR UTek omputer IN. ustom T N/ ate: Tuesday, ugust 0, 00 heet of 0.0

33 RN0 0OHM [] U_PN For card reader [] U_PP RN0 0OHM U_RN /00Mhz L U_RP +V +V_R R +V_R [] R_LK_ +V_R RR R UF/0V c00 RR +V_R R 0.UF/V R UF/0V c00 RR KOhm X00 ONT V +.V_R Mhz R UF/0V c00 OUT R 0PF/0V RR0 X_R_OUT _M_R_REER_R RR % R_REXT U_RP U_RN +V_R.UF/.V N/ c00 +V_ R.UF/.V N/ c00 R U00 EXTIN HIPREETN REXT VP P M VP VU F_V 0 V TRL XN XEN T U-LF-R T RR /LF /LF Option: If use LF package need mount RR resistor and unmount RR resistor. Option: If use LF package need mount RR resistor and unmount RR resistor. T T RR WP# TRL /LF # TRL RR T T /EF T0 T0 T T LK TRL0 T 0 M TRL T T T T T RR XWPN /EF +V_ T T M RR LK LK_R T0 T R R UF/0V 0PF/0V c00 R_REER P_ P_ 0 _OKET_P 000E 0 WP# # R 0PF/0V R 0PF/0V _U- UTeK OMPUTER IN N/ ustom T.0 ate: Tuesday, ugust 0, 00 heet 0 of 0

34 UTek omputer IN.. Module & External ntenna N/ ustom T.0 ate: Tuesday, ugust 0, 00 heet of 0

35 [] RT_RE 0ohm R.c R. L0 RT_R_JP PLE E iodes near V port +V R.0a RT_R_ON RT ON [] RT_REEN 0ohm R.c RT JP L0 RT ON 0.UF/0V HYN_ON RT ON 0.0UH 0 PF/0V c00 [] RT_LUE 0ohm R.c RT JP L0 RT ON 0 0PF/0V c00 [,] RT_HYN [,] RT_VYN R.c R.c RT_HYN_X RT_VYN_X +V Q0 HYN_L UMKN VYN_L R. RT_HYN_X RT_VYN_X +V HYN_L +V VYN_L R0 OHM R OHM R HYN_R R VYN_R HYN_ON +V_RT RT_R_ON PF/0V RT ON RT ON _T_ON HYN_ON VYN_ON _LK_ON [] RT T R.c RX0 OHM _T_ON +V_HMI 0.UF/0V R0 0OHM 0.0UH 0 PF/0V c00 RT_R_ON 0 0PF/0V c00 VI/O VI/O 0 VU VI/O VI/O R0 0 0PF/0V c00 IP-Z E PROTETION IP-Z VYN_ON V R0 0.0UH 0 PF/0V c00 Q0 UMKN U0 V Y LVV U0 V Y LVV /00Mhz /00Mhz VYN_ON PF/0V V RE_RTN RE REEN_RTN REEN LUE_RTN LUE +V N 0 _U_P P_ P_ N HYN VYN L 0V R..KOhm RN.KOhm RN PF/0V 0 V R.0d [] RT LK RX0 OHM +V_HMI _LK_ON +V_HMI +V_HMI PJP0 +V_RT PF/0V R.0d MM_OPEN_MIL +V_HMI 0 V UTek omputer IN. T Onboard V N/ ate: Tuesday, ugust 0, 00 heet of 0.0

36 VRN 0OHM VRN 0OHM [] L_TP L_TP_R [] L_TP L_TP_R [] L_TN [] L_LKP /00Mhz L [] L_TN [] L_TP0 /00Mhz L +V +VU [] L_LKN L_LKN_R [] L_TN0 L_TN0_R [] LV_V_EN R. FOR RF,mount this mlcc +VEI +V +VEI +V_L R R +L_LEIN E PF/0V /EMI L V witch +V +V_L T [] EI_LK [] EI_T +L_LEIN +V LI_E_R# [,0,,0,0,] UF_PLT_RT# [] LV_K_EN [0] L_KOFF# L_EN VR +V_L 0KOhm +V L_EN L Q0 UMKN /00Mhz L UF/V +VU R K LV_ON wtob_con_0p TW P 0.UF/V E /00Mhz L L_TN_R 0OHM VRN VRN 0OHM L_LKP_R L_TN_R 0OHM VRN VRN 0OHM L_TP0_R R0 00KOhm R0 00KOhm 0 0.UF/V R0 0 00KOhm NW +V +V Q0 +V_L IV UF/V 0UF/.V 0.UF/V 0 UF/0V 0.UF/V Q0 N00 Q lose to L onnector N00 R Q N00 0OHM VRN 0OHM VRN R 00KOHM Q0 /00Mhz UMKN R N/ 00PF/0V /00Mhz L R0 0 E E E E E E E E0 PF/0V L_TN0_R PF/0V L_TP0_R PF/0V L_TN_R PF/0V L_TP_R [0] L_PWM_ PF/0V L_TN_R PF/0V L_TP_R PF/0V L_LKN_R T0 TPT PF/0V L_LKP_R R0 N/ L_LKP_R L_LKN_R L_TP_R L_TN_R L_TP_R L_TN_R L_TP0_R L_TN0_R L_EN EITON EILKON R N/ EILKON EITON 00PF/0V _T_Y +L_LEIN PR r00_h PQ _T_Y EMFP0J PR 00KOHM P 0.UF/V PR 00KOhm ER 00KOHM LI_E_R# [,0] TW R 00KOHM Q N00 VWPT +V E UF/0V E 0.UF/V U V Output E--F E 0PF/0V acklight Enable ischarge LV onn N/ UTek omputer IN. ize Project Name ustom T ate: Tuesday, ugust 0, 00 Rev.0 heet of 0

37 FN +V O O FN0_PWM [0] FN0_TH OR FN_PWM +V 0UF/0V 0.UF/V c00 R0 N/ N/.KOhm N/ R0 FN_TH N/.KOhm OR +V O0.KOhm 00PF/0V % N/ R0.KOhm R0.KOhm N/ FN_PWM +V Wto_ON_P N N FN 0000 N/ +V_R OQ PM0 E O 00PF/0V [0] FN0_PWM N/ [,0,,0,,] UF_PLT_RT# Thermal ensor +V R 00KOHM O#_O Q N00 FORE_OFF# [,0] R T00 Pull up +V To E [0] M_LK [0] M_T THRM_L# PF/0V 00 00PF/0V PU Max: m U00 MLK V MT XP LERT# XN THERM# PF +V_THM R UF/0V O#_O +V PU_THRM_ [] PU_THRM_ [] PU_THRM_ 0 PU_THRM_ R PF/0V Pull up +V reserved for TI +.V Pull up +.V dd R0 for thermal sensor read wrong temp issue. 000 mount 0/0/ M_LK M_T /TI Q00 UMKN LK [,] T [,] FN_THERML ENOR Q00 UMKN /TI UTek omputer IN. N/ ustom T.0 ate: Tuesday, ugust 0, 00 heet 0 of 0

38 U.0 Fresco N/ UTek omputer IN. T.0 Tuesday, ugust 0, 00 ate: heet of 0

39 UTeK OMPUTER IN. N U.0_PORT N ustom T.0 ate: Tuesday, ugust 0, 00 heet of 0

40 U.0 with charge onnector(optional) +V_U0_ON For E RN0 0OHM U UPP0 +V [] [] U_PP0 U_PN0 U_PP0 U_PN0 RN RN 0OHM UPP0_L /UNHRE 0OHM UPN0_L /UNHRE RN0 0OHM UPP0 L /00Mhz UPN0 VW_L /E U VW_L /E UPN0 U U_detect# VW_L /E +V_U +V_U0 +V +V_U0_ON +V UF./V /UNHRE R. U change footprint from nb_usb_xp_hod_ra_lf to nb_usb_xp_hd_fn_lf /HRE UR 0 U_PP0 U_PN0 UU N N NO NO 0REU /HRE V 0 OM OM OE UR /HRE U 0.UF/V /HRE UR.KOhm % /HRE UR 0KOhm /HRE UR 0MOhm /HRE UR 0KOhm /HRE /HRE UPP0_L UPN0_L UR mount +V UR0 0KOhm /HRE UQ UMKN /HRE +V_U0_ON +VY_U OM:00000 UR 0KOhm /HRE [] UF /V /HRE U_O# UR.KOhm UR.KOhm UL /00Mhz l00_h +V_U0_ON + U UF/.V U0 0.UF/V U_detect UPN0 UPP0 U 0.UF/V UR U_ON_XP VU IE - P_ + P_ IE U 000P nb_usb_xp_hd_fn_lf UR U switch I U onn UQ UMKN /HRE UR /HRE U_HRE_ON_ [] /HRE U_detect# [0] mount UQ in the OM UR /UNHRE U [,0,,,0] VU_ON [0,0] U_HRE_EN_E +VY_EN [] TW /HRE T H onnector +V U.0 onnector H NP_N NP_N +V +V TRXN0 TRXP0 X0 X0 T_TXP0 [] T_TXN0 [] 0.0UF/V T_RXN0 [] 0.0UF/V T_RXP0 [] I 0uF/0V c00 I 0.UF/V N/ 0 0 NP_N 0 0 NP_N T_ON_P TPT T I 0uF/0V c00 N/ +V I 0uF/0V c00 I 0.UF/V N/ U Port N/ UTek omputer IN. T.0 Tuesday, ugust 0, 00 ate: heet of 0

41 +V WR 00KOhm +VU W 0.UF/V +V W 0.UF/V +V +V_PE WR r00_h WQ EMFP0J /WIFIP +V_PE [] T_ON/OFF# [] LKREQ#_MINIR [] LK_PIE_MINIR# [] LK_PIE_MINIR M_LKREQ# N/ WR +V_PE +VU_PE_R +VU_PE +V_PE [] MINIR_EN# T WLN WKE# T_T T_HLK LKREQ# REFLK- REFLK+.V_.V_ Reserved Reserved Reserved Reserved Reserved 0 T WR WR WR KOhm /WIFIP W 0.UF/V /WIFIP W 0.UF/V W 0.UF/V W 0UF/.V W 0UF/.V [] [] [] [] PIE_RXN0_MINIR PIE_RXP0_MINIR PIE_TXN0_MINIR PIE_TXP0_MINIR WR +V_PE WR PIE_RXN_W PIE_RXP_W WR Reserved Reserved PERn0 PERp0 PETn0 PETp0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved0 W_ILE# PERT#.Vaux.V_ Reserved Reserved 0 Reserved Reserved N LE_WLN# N.V_.V_ T WLN_ON PERT# UPN UPP LE_WLN# T LE_T# T T +VU +VU_PE WR W UF/0V W 0.UF/V EL Wake WLN_ON Q N00 MINIR_EN# NP_N NP_N MINI_PI_LTH_P 0000 WRN 0OHM [] [] U_PP U_PN WRN 0OHM UPP L /00Mhz UPN +V RN WR0 0KOHM /WIFIP W UF_PLT_RT# +V_PE RN 0KOHM /WIFIP PERT# [] LKREQ#_MINIR MINIR_EN# Q N00 TW /WIFIP W0 0.UF/V /WIFIP [,0,,0,,0] UF_PLT_RT# Q N00 /WIFIP UF_PLT_RT# /WIFIP W 0.UF/V UTek omputer IN. ustom T Mini WIFI N/ Tuesday, ugust 0, 00 ate: heet of 0.0

42 For POWER LE cenario Mode dapater Mode attery Mode +VU YR PWR_LE+ PWR_LE + LUE YT PWR_LE- attery power is between 00% 0% attery power is between 0% 0% Orange ON Orange linking lowly reen ON reen linking lowly [,0] PWR_LE_UP PWR_LE_UP YQ UMKN attery power is less than 0% Orange linking Quickly OFF / Mode cenario the same as above [] T_LE# +V YR +V +V YR YR0 0KOhm For IE/T LE.KOhm FLH_LE IE_FLH_LE LUE YQ UMKN YQ UMKN +V YR [] WLN_LE For WLN LE WL_LE WLN_LE+ + LUE WLN_LE +V PLOK_LE YR PLOK_LE+ + PLOK_LE- WLN_LE- YQ UMKN For P LOK LE FLH_LE+ + FLH_LE- +V LUE YR.KOhm P_LE [0] aps_le# YQ UMKN YQ UMKN YR YR For HRE LE +VU HRE_LE + reen + H_LE_REEN#_L H_LE_ORNE#_L YR [0] H_LE_REEN# YR Orange REEN/ORNE [0] H_LE_ORNE# UTeK OMPUTER IN LE/PWR WIH N T ate: Tuesday, ugust 0, 00 heet of 0.0