VF-co-cc. F3Jr CPU CLOCK GEN. ATI M64-M or M76-M NORTH DDR2 SO-DIMM0 BRIDGE DDR2 SO-DIMM1 TPM 1.2 INFINEON SLB9635 SOUTH BRIDGE EC ITE IT8510E

Size: px
Start display at page:

Download "VF-co-cc. F3Jr CPU CLOCK GEN. ATI M64-M or M76-M NORTH DDR2 SO-DIMM0 BRIDGE DDR2 SO-DIMM1 TPM 1.2 INFINEON SLB9635 SOUTH BRIDGE EC ITE IT8510E"

Transcription

1 lock iagram ystem etting * PU-YONH(HOT) PU-YONH(PWR) * N-PM(HOT) * U ONN * I ROM * LE * R Mx x Option PU YONH MEROM W W LOK EN I 0 FJr N-PM(MI & F) N-PM(RPHI) N-PM(R) N-PM(PWR) 0 & T IN * ebug ONN. * R Mx x THERML ONTROL N-PM(PWR) N-PM() * -IHM() -IHM() -IHM() -IHM(PWR) * T-H & O * REW HOLE * TPM * T * L RT TV-OUT TI M-M or M-M NORTH RIE Intel PM R O-IMM0 R O-IMM 0 R O-IMM0 0 POWER_VORE R O-IMM R TERMINTION * V_TI_MX-M_MIN() V_TI_MX-M_Memory() V_TI_MX-M_PI-E() V_TI_MX-M_POWER() V_TI_MX-M_VRM_() V_TI_MX-M_VRM_() V_PI_ROM () FINER PRINT RT LV & INVERTER ONNETOR * TV OUT ONN * THER ENOR & FN * LOK EN-I0 * Power on & Reset Freq. IHRE * LN-RTL M & RJ+ * MINI R * R-R() R-R() in R REER NEWR R PMI OKET * OE-L0 UIO MP & JK * E-IT0E Touch Pad & K POWER_YTEM POWER_IO_.V &.0V POWER_IO_R & VTT POWER_IO_+VO & +.V 0 POWER_V_ORE & RM POWER_+.VP POWER_HRER POWER_PI(Empty) POWER_ETET POWER_PROTET POWER_LO WITH POWER_FLOWHRT POWER_INL History I ROM in ard Reader VI TPM. INFINEON L Internal K ebug onn. E ITE IT0E Ricoh RR Touch Pad ard Reader PMI ILN Realtek RTL OUTH RIE IH-M PT H O ZLI OE U Port X luetooth M MINIR NEWR MO amera Finger Print T H Realtek L0 UTek omputer IN. N ustom FJr UIO MP EXT MI INT MI Title : lock iagram Engineer: Frank Xu,, 00 ate: heet of.0

2 O PE INTP F PIO0 PH PIOTP_PI# PWMP PU_VRON RI#WUIP O PH 0P MLK0P H_LE_UP# PI_INTH# ITP# TH0P LRQ#PIO PTPF IH_PWROK I OP_# LP0LLP PM_PRLPVR IH_PIO P IH_PIO PIOO# PH PI_INTF# M0_T I 0 M_LK EI#P PTPF ignal Name PIO0 UF_PLT_RT# PWMP O PLKPF I0 PIONT# 0 F IH_PIO T_ET#0 PI_NT# PI_REQ# PIOT0P PIO I F PM_PWRTN# Pin I PWR_W# ignal Name PI_INT# TMRI0WUIP PIO0 PIOO# PH U# MTP PIO PIO0O# U_O# IH_PIO PI PLKPF P PIO0 RI#WUI0P0 THP PI EXT_I# PWMP O PIOTP E PLKPF I PIOTP Type O O _# E0 PIO0PIRQH# WUIPE INTERNET# P_LE PIOZ_OK_EN# O P_I TP_T PIO I P_I0 U_ON PWMP O O PTPF MT0P Pin PIO0TP_PU# 0 E_IE_RT# T_IN_O# PWR_LE_UP# VU_# PWRWPE Pin PWM0P0 FP E PIO ETTIN I PIO PIOZ_OK_RT# NEWR_O# P I PLK0PF0 I 0 I H_EN# PM_RMRT# TXP F\ NUM_LE MRTHON# 0 O Type IH_PIO PIOPUPWR O H_PWR L_KOFF# O PIO PMTHERM# I PIO0PIRQF# 0 O PIOREQ# I0 I O E0 U_ON LPRT#WUIP FP LKRUN#WUIPE I ignal Name O PH PIO U LKOUTP0 H O O F O IH_PIO I PIOEL_RV FN0_TH I TP_PI# TMRIWUIP IH_PIO PI0 P PIO00M_UY# I M_LERT# WLN_LE_EN E I IO IH_PIO I R F I0 WLN_ON# PH0 Pin Name LP0HLP T_LL# H I 0 THRM_PU# IN_O# NT#PIO IH_PIO FP LP_RQ# Type O O 0 MLKP PIOEL_TTE IH-M PIO ETTIN P_ET# R_IN# PWMP PIO WTH_O# T_LERN Pin Name I KKOUTP TP_LK PE0 0 F 0 PIO0PIRQE# O RXP0 RF_ON_W# PM_LKRUN# I PI PIO0 PE PIOEL_TTE0 EXTMI# O E PI_REQ# _PR_U# F0P I0 PH 0TE U_O# PI_NT# E PE LPP#WUIPE I I P PIOTP K_I# 0 FP0 PH TP_LEON I RL_LE O PIO0PIRQ# 0 PI PUPWR_# IH_PIO I I VU_ON FP M0_LK LI_E# M_T P_I O I PI_INTE# PIO TLE_ON TP_PU# R PI PM_MUY# E I PIO PWMP PI 0 I PIOLKRUN# I O PU_elect I0 MLERT#PIO PIO0REQ# PT0PF U# PIO I0 KRT#P PWMP Pin Name O O E Interrupts 000x ( ) lock enerator IEL# O-IMM PI evice 0000x ( ) Thermal ensor 00000x ( 0 ) R REER() M-us evice 000x ( ) M-us ddress REQNT# (0) O-IMM 0 () FN_PWM IN_MP#_K OLOREN# T_ON# INTNTON# PREH O O O O O O O O O O O O O O (0) R U() O O I I I I I I O I ustom,, 00 UTek omputer IN. N ystem etting.0 FJr Frank Xu ate: heet of Title : Engineer:

3 UTeK OMPUTER IN ustom FJr Title : chematic page name Engineer: Frank Xu,, 00 ate: heet of.0

4 H_#[:] H_T#0 H_REQ#[:0] H_#[:] H_T# H_0M# H_FERR# H_INNE# H_TPLK# H_INTR H_NMI H_MI# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_REQ#0 H_REQ# H_REQ# H_REQ# H_REQ# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# U J []# L []# M []# K []# M []# N []# J []# N [0]# P []# P []# L []# P []# P []# R []# L T[0]# K REQ[0]# H REQ[]# K REQ[]# J REQ[]# L REQ[]# Y []# U []# R []# W [0]# U []# Y []# U []# R []# T []# T []# W []# W []# Y []# W [0]# Y []# V T[]# 0M# FERR# INNE# TPLK# LINT0 LINT MI# RV[] RV[] RV[] RV[] M RV[] N RV[] T RV[] V RV[] RV[] RV[0] RV[] OKETP # H E NR# PRI# H EFER# F RY# Y# E R0# F 0 IERR# INIT# LOK# H REET# R[0]# F F R[]# R[]# TRY# HIT# E HITM# PM[0]# PM[]# PM[]# PM[]# PRY# PREQ# TK TI TO TM TRT# 0 R# PROHOT# THERM THERM THERMTRIP# LK[0] LK[] RV[] T RV[] F RV[] RV[] RV[] F RV[] RV[] RV[] RV[0] H_IERR# TPT H_PREQ# H_TK H_TI H_TO H_TM H_TRT# TPT H_PROHOT# TPT TPT PU ebug Port efault trapping When Not Used H_PREQ# H_TI H_TM H_TO H_TK H_TRT# R R H_# H_NR# H_PRI# H_EFER# H_RY# H_Y# H_R0# H_INIT# H_LOK# H_PURT# H_R#0 H_R# H_R# H_TRY# H_HIT# H_HITM# T T H_THERM H_THERM PM_THRMTRIP#, T LK_PU_LK LK_PU_LK# T Ohm Ohm Ohm Ohm Ohm Ohm RN RN RN RN +VP +VP +VP R Ohm R Ohm HN00 Q _0 THRO_PU TL+ IO Voltage Reference +VP R KOhm % LK F EL EL EL0 H_#[:0] H_TN#0 H_TP#0 H_INV#0 H_#[:] H_TN# H_TP# H_INV# L L PU_EL0 PU_EL PU_EL L H H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# TL_REF R R KOhm KOhm % R.Ohm PU_EL0 PU_EL PU_EL H H E F E H F E E K J J H F K H H J N K P R L L L M P P P T R L T N M N M U [0]# []# []# []# []# []# []# []# []# []# [0]# []# []# []# []# []# TN[0]# TP[0]# INV[0]# []# []# []# []# [0]# []# []# []# []# []# []# []# []# []# [0]# []# TN[]# TP[]# INV[]# TLREF TET TET EL[0] EL[] EL[] OKETP MI []# []# []# []# []# []# []# []# [0]# []# []# []# []# []# []# []# TN[]# TP[]# INV[]# []# []# [0]# []# []# []# []# []# []# []# []# []# [0]# []# []# []# TN[]# TP[]# INV[]# OMP[0] OMP[] OMP[] OMP[] PRTP# PLP# PWR# PWROO LP# PI# H_OMP0 H_OMP V V W U U U W Y Y Y W Y V 0 E F E E F F F E 0 R U U V E E TL+ IO uffer ompensation TL+ IO uffer ompensation UTeK OMPUTER IN. N ustom H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_OMP0 H_OMP H_OMP H_OMP R %.Ohm R %.Ohm FJr H_OMP H_OMP H_#[:] H_TN# H_TP# H_INV# H_#[:] H_TN# H_TP# H_INV# H_PRTP#,0 H_PLP# H_PWR# H_PWR H_PULP#, PM_PI# 0 R0 %.Ohm R %.Ohm Title : PU-YONH(HOT) Engineer: Frank Xu,, 00 ate: heet of.0

5 PU +VORE Mid-Frequency apacitors 0UF.V Place these upper side inside socket cavity on L 0 0UF.V PU +VORE ulk-ecoupling apacitors 0UF.V 0UF.V Place these lower side inside socket cavity on L +VORE Mid-Frequency apacitor Intel: UF * RF: 0UF * +VP ecoupling apacitor Intel: 0UF *, 0.UF * RF: 0UF *, 0.UF * 0UF.V 0UF.V 0UF.V 0UF.V 0UF.V Place these upper side inside socket cavity on L 0 0UF.V 0UF.V 0UF.V + E 0UFV 0UF.V 0UF.V 0UF.V 0UF.V Place these lower side inside socket cavity on L +VORE E E E0 E E E E E E0 F F F0 F F F F F F U V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] OKETP V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[00] VP[] VP[] VP[] VP[] VP[] VP[] VP[] VP[] VP[] VP[0] VP[] VP[] VP[] VP[] VP[] VP[] V VI[0] VI[] VI[] VI[] VI[] VI[] VI[] VENE VENE 0 0 E E0 E E E E E E0 F F0 F F F F F F0 V J K M J K M N N R R T T V W F E F E F E F E +VORE +VP +.V H_VI0 H_VI H_VI H_VI H_VI H_VI H_VI R R R0. PU +VP ecoupling apacitors UF0V 0.UF0V +VORE 0.UF0V 0.UF0V VR_VI0 0 VR_VI 0 VR_VI 0 VR_VI 0 VR_VI 0 VR_VI 0 VR_VI 0 VENE 0 VENE 0 + E 00UF.V 0.0UFV PU +V ecoupling apacitors 0UF.V UTeK OMPUTER IN. N ustom E E E E E E E E E F F F F F F F F F H H H H J J J J K K K K L L L L M M M M N N N N P U V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] OKETP FJr V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] P P P R R R R T T T T U U U U V V V V W W W W Y Y Y Y E E E E E E E E E F F F F F F F F F Title : PU_YONH(PWR) Engineer: Frank Xu,, 00 ate: heet of.0

6 UTeK OMPUTER IN ustom FJr Title : chematic page name Engineer: Frank Xu,, 00 ate: heet of.0

7 ROMP For alibrating the F IO uffer H_XROMP H_YROMP R R.Ohm.Ohm % % OMP For lew Rate ompenssation on the F +VP +VP R R0.Ohm.Ohm % % H_XOMP H_YOMP Voltage wing For Providing a Reference Voltage to The F ROMP circuits +VP +VP R R Ohm Ohm % % H_XWIN H_YWIN R R 0 0.UF0V 0 0.UF0V % % H_#[:0] H_#0 F H_# J H_# H H_# J H_# H H_# K H_# H_# H_# K H_# K H_#0 K H_# J H_# H H_# J H_# K H_# H_# T0 H_# W H_# T H_# U H_#0 U H_# U H_# T H_# W H_# T H_# T H_# T H_# W H_# U H_# T H_#0 W H_# T H_# H_# H_# W H_# W H_# Y H_# Y H_# W H_# Y0 H_#0 H_# W H_# H_# H_# H_# H_# 0 H_# Y H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# 0 H_# H_# LK_MH_LK LK_MH_LK# H_XROMP H_XOMP H_XWIN H_YROMP H_YOMP H_YWIN E E E Y U W U H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_XROMP H_XOMP H_XWIN H_YROMP H_YOMP H_YWIN H_LKIN H_LKIN# QPM H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_# H_T#_0 H_T#_ H_VREF H_NR# H_PRI# H_REQ#0 H_PURT# H_Y# H_EFER# H_PWR# H_RY# H_VREF H_INV#_0 H_INV#_ H_INV#_ H_INV#_ H_TN#_0 H_TN#_ H_TN#_ H_TN#_ H_TP#_0 H_TP#_ H_TP#_ H_TP#_ H_HIT# H_HITM# H_LOK# H_REQ#_0 H_REQ#_ H_REQ#_ H_REQ#_ H_REQ#_ H_R#_0 H_R#_ H_R#_ H_LPPU# H_TRY# H H_# H_# E H_# H_# F H_# H_# F H_# H H_#0 J H_# H_# H_# J H_# H H_# J H_# F H_# H_# H_# H_#0 H_# H_# E H_# H_# F H_# H_# H_# H_# H_# H_#0 H_# E J H_VREF F J H K J W U 0 K T Y K T F E E E H_REQ#0 H_REQ# H_REQ# H_REQ# H_REQ# H_#[:] H_# H_T#0 H_T# H_NR# H_PRI# H_R0# H_PURT# H_Y# H_EFER# H_PWR# H_RY# H_INV#0 H_INV# H_INV# H_INV# H_TN#0 H_TN# H_TN# H_TN# H_TP#0 H_TP# H_TP# H_TP# H_HIT# H_HITM# H_LOK# H_REQ#[:0] H_R#0 H_R# H_R# H_PULP#, H_TRY# ustom TL+ IO Voltage Reference 0.UF0V UTeK OMPUTER IN. N FJr +VP R 0 % R 0 % Title : N-PM(HOT) Engineer: Frank Xu,, 00 ate: heet of.0

8 MH trapping F : MI trap 0 = MI x = MI x () MH_F_ F : PU trap 0 = TTranspotable PU = Mobile PU () MH_F_ F : PIE raphic Lane 0 = Reverse Lane = Normal Operation () MH_F_ F0 : HOT PLL VO elect 0 = Reserved = Mobility () MH_F_0 F : P x LK Enable 0 = x Enable = x Enable () MH_F_ R R R0 R R KOhm KOhm KOhm F[:] : MH Test Mode 00= Partial LK ating isable 0 = XOR Mode Enable 0 = ll Z Mode Enable = Normal Operation () F : IH REET isable 0 = IH Reset isable = Normal Operation () MH_F_ F : F ynamic OT 0 = ynamic OT isable = ynamic OT Enable () MH_F_ F : V elect 0 =.0V () =.V F : MI Lane Reversal 0 = Normal Operation () = Lanes Reversed Note: F[:] have internal pull-up while F[0:] have internal pull-down. LK F EL EL EL0 MH_F_ R 0,,,,,,, UF_PLT_RT# KOhm R KOhm KOhm MH_F_ R R R KOhm KOhm KOhm +.V +.V _REFLKIN +V +.V R 0KOhm r00 R 0KOhm r00 R R L L MH_EL0 MH_EL MH_EL PM_MUY# 0KOhm r00 0KOhm r00, PM_THRMTRIP#,0,0 VRM_PWR MH_IH_YN# L H _REFLKIN H H MH_F_ MH_F_ MH_F_ MH_F_0 MH_F_ MH_F_ MH_F_ MH_F_ MH_F_ T TPT PM_EXTT#_0 PM_EXTT#_ +.V RT_IN_MH# R0 0KOhm r00 R 0KOhm r00 T R F F F H J K0 J K K J F E F E E K H H J K J F H H H H H K H 0 Y Y W W 0 U RV_ RV_ RV_ RV_ RV_ RV_ RV_ RV_ TV_ONEL_0 TV_ONEL_ RV_ RV_ RV_ RV_ RV_ F_0 F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 PM_MUY# PM_EXTT#_0 PM_EXTT#_ PM_THRMTRIP# PWROK RTIN# VO_TRLLK VO_TRLT IH_YN# LK_REQ# N0 N N N N N N N N N N0 N N N N N N N N QPM M_K_0 M_K_ M_K_ M_K_ M_K#_0 M_K#_ M_K#_ M_K#_ M_KE_0 M_KE_ M_KE_ M_KE_ M_#_0 M_#_ M_#_ M_#_ M_OOMP_0 M_OOMP_ M_OT_0 M_OT_ M_OT_ M_OT_ M_ROMP# M_ROMP M_VREF_0 M_VREF LKIN# _LKIN _REFLKIN# _REFLKIN _REFLKIN# _REFLKIN MI_RXN_0 MI_RXN_ MI_RXN_ MI_RXN_ MI_RXP_0 MI_RXP_ MI_RXP_ MI_RXP_ MI_TXN_0 MI_TXN_ MI_TXN_ MI_TXN_ MI_TXP_0 MI_TXP_ MI_TXP_ MI_TXP_ Y R W W0 W T Y Y0 U0 T0 Y W W Y W L0 F0 Y0 U V T K K F 0 E F H E F E F H E F UTeK OMPUTER IN. N ustom R 0.Ohm % R 0.Ohm % M_VREF_MH MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP _REFLKIN _REFLKIN FJr M_VREF_MH M_LK_R0 0 M_LK_R 0 M_LK_R M_LK_R M_LK_R#0 0 M_LK_R# 0 M_LK_R# M_LK_R# M_KE0 0, M_KE 0, M_KE, M_KE, M_#0 0, M_# 0, M_#, M_#, M_OT0 0, M_OT 0, M_OT, M_OT, Title : Engineer: +.V M_VREF_MH 0,, LK_MH_PLL# LK_MH_PLL MI_TXN[:0] MI_TXP[0..] MI_RXN[0..] MI_RXP[0..] 0.UF0V UF0V N-PM(MI & F) Frank Xu,, 00 ate: heet of.0

9 +.V_PIE +VP +.V U L_KLTTL J0 L_KLTEN H0 L_LK_TL H L_T_TL L LK L T L_I L_V F L_VEN L_VREFH L_VREFL L_LK# L_LK E L_LK# E L_LK L_T#_0 L_T#_ L_T#_ L_T_0 L_T_ L_T_ 0 L_T#_0 0 L_T#_ F L_T#_ F0 L_T_0 L_T_ F L_T_ TV OUT TV OUT TV OUT J0 TV_IREF TV_IRTN TV_IRTN TV_IRTN E RT_LUE RT_LUE# RT_REEN RT_REEN# RT_RE RT_RE# T TPT T TPT RT LK RT T RT_HYN J RT_IREF H RT_VYN QPM EXP OMPI EXP OMPO EXP RXN_0 EXP RXN_ EXP RXN_ EXP RXN_ EXP RXN_ EXP RXN_ EXP RXN_ EXP RXN_ EXP RXN_ EXP RXN_ EXP RXN_0 EXP RXN_ EXP RXN_ EXP RXN_ EXP RXN_ EXP RXN_ EXP RXP_0 EXP RXP_ EXP RXP_ EXP RXP_ EXP RXP_ EXP RXP_ EXP RXP_ EXP RXP_ EXP RXP_ EXP RXP_ EXP RXP_0 EXP RXP_ EXP RXP_ EXP RXP_ EXP RXP_ EXP RXP_ EXP TXN_0 EXP TXN_ EXP TXN_ EXP TXN_ EXP TXN_ EXP TXN_ EXP TXN_ EXP TXN_ EXP TXN_ EXP TXN_ EXP TXN_0 EXP TXN_ EXP TXN_ EXP TXN_ EXP TXN_ EXP TXN_ EXP TXP_0 EXP TXP_ EXP TXP_ EXP TXP_ EXP TXP_ EXP TXP_ EXP TXP_ EXP TXP_ EXP TXP_ EXP TXP_ EXP TXP_0 EXP TXP_ EXP TXP_ EXP TXP_ EXP TXP_ EXP TXP_ 0 F H J L M N P R T V W Y F H J L M N P R T V W Y F 0 H J0 L M0 N P0 R T0 V W0 Y 0 0 F0 H0 J L0 M N0 P R0 T V0 W Y0 0 R.Ohm % PIEN_RXN0 PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN0 PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXP0 PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP0 PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_TXN0 PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN0 PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXP0 PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP0 PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_RXN[0..] PIEN_RXP[0..] PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP0 PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP0 PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN0 PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN0 0.UFV 0.UFV 0 0.UFV 0.UFV 0.UFV 0.UFV 0.UFV 0.UFV 0.UFV 0.UFV 0.UFV 0.UFV 0 0.UFV 0.UFV 0.UFV 0.UFV 0.UFV 0.UFV 0.UFV 0.UFV 0.UFV 0.UFV 0 0.UFV 0.UFV 0.UFV 0.UFV 0.UFV 0.UFV 0.UFV 0.UFV 0.UFV 0.UFV PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP0 PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP0 PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN0 PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN0 UTeK OMPUTER IN. N ustom PIE_RXN[0..] PIE_RXP[0..] FJr Title : Engineer: N_PM(RPHI) Frank Xu,, 00 ate: heet of.0

10 ustom 0,, 00 UTeK OMPUTER IN. N N-PM(R).0 FJr Frank Xu ate: heet of Title : Engineer: M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q0 M Q M Q M Q M Q0 M Q M Q M Q#0 M Q M Q# M Q# M M M M0 M M M M M M M M M M M Q# M M M M Q M Q M 0 M M M Q# M M M M M M M Q M Q M Q# M Q0 M Q# M Q# M 0 M Q M M M Q M M Q M Q M Q0 M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q0 M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q#0 M Q# M M Q# M Q M M M M Q M Q# M M M Q M 0 M M0 M M M M 0 M M M Q# M M M M M M M M M M M M Q# M M Q# M Q M Q0 M M Q# M M Q M Q M UE QPM K J P R J K N P T0 V U V P R0 W Y V R P U P P Y T U U W V W M L P N N M P L J H0 J N0 K H K0 J 0 W0 W Y0 Y W Y V R K K T K J J T V Y R K R T L H N M T U R R R0 R N M0 U T P P T0 T P Y W Y R T T U V V W V Y R U K K R _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q 0 _# _M_0 _M M M M M M M Q_0 _Q Q Q Q Q Q Q Q#_0 _Q# Q# Q# Q# Q# Q# Q# M_0 _M M M M M M M M M M_0 _M M M R# _RVENIN# _RVENOUT# _WE# U QPM J J M M J K J H N P R P N M M N K L M N K L M P P L P N0 L P P0 T R R P P T T L L K N K K P N T L Y W P N V T N L F F H F F U V 0 Y J M L N M L R H K T N M N N P K U N M M L N H Y U W U V U W T U T V0 V W K K Y _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q 0 _# _M_0 _M M M M M M M Q_0 _Q Q Q Q Q Q Q Q#_0 _Q# Q# Q# Q# Q# Q# Q# M_0 _M M M M M M M M M M_0 _M M M R# _RVENIN# _RVENOUT# _WE# M Q[:0] 0 M 0, M # 0, M 0, M 0 0, M R# 0, M WE# 0, M M[:0] 0 M [:0] 0, M Q[:0] 0 M Q#[:0] 0 M Q[:0] M R#, M 0, M, M #, M WE#, M, M M[:0] M Q#[:0] M [:0], M Q[:0]

11 t Package Edge t Edge Pin Location In avity.0v~.v Max:..V~.V Max:.(R ) In avity ustom,, 00 UTeK OMPUTER IN. N N-PM(PWR).0 FJr Frank Xu ate: heet of Title : Engineer: +.V +.V +VP +VP + E 00UF.V UF QPM W P N L J Y W V P N M L J W V T R P N M 0 Y0 W0 V0 U0 T0 R0 P0 N0 M0 L0 Y W V U R P M L Y V U T R P N M L P N M L P N L N M L P N M Y P N M L Y W P N M L W N M L 0 0 Y0 W0 P0 N0 M0 L0 Y N M L N M L P N M N M L U T M U0 Y W V U T R 0 Y0 W0 V0 U0 T0 R0 P0 N0 M0 M L K J H J H J H Y W V U T R J H J H J H J Y W V U T R P K J K K0 Y W V U T R P K J J J H J H Y W V U T R J J J H K J H K Y W V T R P Y W V T R P N L K J V J V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_00 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_M_0 V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_0 V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_0 V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_0 V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_0 V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_0 V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_0 V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_0 V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_0 V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_0 V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_ V_M_00 V_M_0 V_M_0 V_M_0 V_M_0 V_M_0 V_M_0 V_M_0 UF0V 0.UF0V 0.UF0V 0UF0V + E 00UF.V 0 0UF0V UF0V 0.UF0V UF0V 0UF0V 0 UF0V 0UF0V UF0V U QPM Y W V U T R Y W V U T R Y W V U T R Y W V U T R V U T R V U T R V U T R 0 V0 U0 T0 R0 V U T Y W V U T E E E E E E E E0 E E Y U F F F F F F F 0 F0 F R F R F E W V T R F E Y W V U T R F E Y W V U T R V_NTF0 V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF0 V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF0 V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF0 V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF0 V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF0 V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF0 V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF0 V_NTF V_NTF V_NTF0 V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF0 V_NTF V_NTF VUX_NTF0 VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF0 VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF0 VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF0 VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF0 VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF0 VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF UF0V UF0V

12 Top Layer.V~.V Max:. On the Edge In avity 0.V~.0V Max:..V~.V Max: 0m.V~.V Max: 0m.V~.V Max: m.v~.v Max: m.v~.v Max: 0m.V~.V Max: 0m.~.V Max: m R0. ustom,, 00 UTeK OMPUTER IN. N N-PM(PWR).0 FJr Frank Xu ate: heet of Title : Engineer: PLL_R_L VTTLF_P VTTLF_P VTTLF_P +.V_PIE +.V +.V_PLL +.V_RT +.V_PLL +.V_PLL +.V_HPLL +.V +.V_MPLL +.V_TV +.V_TV +.V_TV +.V +.V_TV +.V +.V +.V_PLL +.V_HPLL +.V_PLL +.V_MPLL +V +.V_QTV +VP +.V +.V_TV +.V_TV +.V_TV +V_TV +V_TV +.V +.V +.V_TV +.V_QTV +VP +.V 0UF0V 0.UF0V 0UF0V 0.UF0V L 00Mhz 0.UF0V + E 00UF.V 0 0.UFV L 00Mhz 0UF0V 0UF0V 0 0.UFV 0UF0V 0UF0V 0 0.UFV + E 00UF.V L 00Mhz 0.UFV 0UF0V UF0V L uh 0 0.0UFV L 00Mhz JP HORT_PIN 0 0.0UFV UH QPM H J Y V R N L H F E F F H0 0 E F 0 0 E0 F0 H H H K F E L0 K0 J0 H0 0 F0 E0 0 0 F E F E H J H J0 H0 H P P H P H F E Y F E F E W V T R P N M L Y W V U T R N M L Y W V U T R P N M L R P N M R0 P0 N0 M0 P N M R P N M P N M R P M R P N M P N M R P N M R P M R P N M VYN V_TXLV0 V_TXLV V_TXLV V0 V V V V V V V_PLL V_ V_ V_RT0 V_RT V_RT V_PLL V_PLL V_HPLL V_LV V_LV V_MPLL V_TV V_TV V_TV0 V_TV V_TV0 V_TV V_TV0 V_TV V_HMPLL0 V_HMPLL V_LV0 V_LV V_LV V_TV V_HV0 V_HV V_HV V_QTV VUX0 VUX VUX VUX VUX VUX VUX VUX VUX VUX VUX0 VUX VUX VUX VUX VUX VUX VUX VUX VUX VUX0 VUX VUX VUX VUX VUX VUX VUX VUX VUX VUX0 VUX VUX VUX VUX VUX VUX VUX VUX VUX VUX0 VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ 0 0.UF0V 0.UF0V 00 0.UF0V UF0V 0.UFV JP HORT_PIN 0 0.0UFV UF0V 0.UF0V L 0nH 0UF0V L0 00Mhz 0 0.0UFV 0.0UFV R 0.Ohm 0 0UF0V 0 0.0UFV R 0 0.UF0V 0 0.UFV 0.0UFV 0.UFV L 00Mhz 0.UF0V 0UF0V 0UF0V

13 ustom,, 00 UTeK OMPUTER IN. N N-PM().0 FJr Frank Xu ate: heet of Title : Engineer: UJ QPM T N M H W K J F K F E V R N L Y P K J H W0 R0 M0 0 K0 0 0 N W K H P H Y R P M K V N L J F N M K N M L T K U K H E V R N M L P F Y K H E Y J V0 P0 L0 J0 0 0 W0 U0 W R H Y R E U K V P L J H F R Y U N K H V F Y R P L J Y U R J F Y W V L H F T R P K J Y U T N J H F L V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_00 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_00 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 UI QPM W T P M J F V0 P0 N0 K0 J0 H0 0 F0 E0 0 Y W V R N J Y W V T R P N M L J H F T M H F E K H Y W V T R P N M L J H F Y W N H F E V R H Y W V T R P N M L J H F N K F E W V R E Y V T R M H F H F E Y V N J Y 0 E0 T N T N K E W U P M W J E P M K J F N M K F K P K H E U L W V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_00 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_

14 UTeK OMPUTER IN ustom FJr Title : chematic page name Engineer: Frank Xu,, 00 ate: heet of.0

15 +V +V_RT +RTT T TPT ON TT_HOLER R KOhm TPT T T UF0V PF0V X_RT X.Khz R 0MOhm +V_RT RTRT# R delay should be ms~ms Z_IN0 Z_IN R kohm OE MOEM UF0V Request of for MO clear function Place Near the Open oor INT_IRQ IE_PIORY JRT L_JUMP, +V +V_RT Z_LK_M Z_LK_OE Z_YN_OE Z_YN_M Z_RT#_OE Z_RT#_M Z_OUT_OE Z_OUT_M T_LE# T_RXN0 T_RXP0 T_TXN0 T_TXP0 R.KOhm R.KOhm R R0 R R R R0 R R0 R0 R PF0V r00 r00 r00 r00 Z_IN0 Z_IN r00 LK_T_IH# LK_T_IH Ohm Ohm Ohm Ohm Ohm Ohm MOhm 0KOhm X_RT Z_LK Z_YN Z_RT# OhmZ_OUT Ohm 000PF0V 000PF0V TRI# R.Ohm % IE_PIOR# IE_PIOW# IE_PK# IE_PREQ Y W W Y Y W V U U V T U V V U R R T T T T F F E H F E H F E H0 0 F H F H E U RTX RTX RTRT# INTRUER# INTVRMEN EE_ EE_HLK EE_OUT EE_IN LN_LK LN_RTYN LN_RX0 LN_RX LN_RX LN_TX0 LN_TX LN_TX Z_LK Z_YN Z_RT# Z_IN0 Z_IN Z_IN Z_OUT TLE# T0RXN T0RXP T0TXN T0TXP TRXN TRXP TTXN TTXP T_LKN T_LKP TRIN TRIP IOR# IOW# K# IEIRQ IORY REQ IHM IE L0 L L L LRQ0# LRQ#PIO LFRME# 0TE 0M# PULP# TPPRTP# TPPLP# FERR# PIOPUPWR INNE# INIT_V# INIT# INTR RIN# NMI MI# TPLK# THERMTRIP# # # Y E H F H LP_RQ#0 LP_RQ# TPT F F H F H F E F E F F H H H E F E R R.Ohm % IE_P0 IE_P IE_P IE_P IE_P IE_P IE_P IE_P IE_P IE_P IE_P0 IE_P IE_P IE_P IE_P IE_P T0 LP_0,0, LP_,0, LP_,0, LP_,0, TPT TPT T T LP_FRME#,0, 0TE_IH H_0M# H_PULP#, H_PRTP#,0 H_PLP# H_PWR H_INNE# H_INIT# H_INTR R_IN#_IH H_NMI H_MI# H_TPLK# IE_P[:0] IE_P0 IE_P IE_P IE_P# IE_P# +VP +VP R Ohm R Ohm UTeK OMPUTER IN. N ustom H_FERR# PM_THRMTRIP#, FJr Title : -IH-M() Engineer: Frank Xu,, 00 ate: heet of.0

16 +VU PIE_RXN_LN PIE_RXP_LN PIE_TXN_LN PIE_TXP_LN PIE_RXN_MINIR PIE_RXP_MINIR PIE_TXN_MINIR PIE_TXP_MINIR PIE_RXN_NEWR PIE_RXP_NEWR PIE_TXN_NEWR PIE_TXP_NEWR,,, PI_[:0] PI_INT# PI_INT# PI_INT# T T T0 T T PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_INT# PI_INT# TPT TPT TPT TPT TPT E F E E E E 0 F F0 E E E H U 0 PI Interrupt PIRQ# PIRQ# PIRQ# PIRQ# RV_ RV_ RV_ RV_ RV_ IHM MI REQ0# NT0# REQ# NT# REQ# NT# REQ# NT# REQ#PIO NT#PIO PIOREQ# PIONT# PLTRT# PILK PME# IF PIOPIRQE# PIOPIRQF# PIOPIRQ# PIOPIRQH# IH oot IO elect NT# NT# uffer to Reduce Loading on PLT_RT# M PI_REQ# RPE PERn MIRXN MI_RXN M PERp MIRXP MI_RXP L PI_REQ#0 RPF PETn MITXN MI_TXN L PETp MITXP MI_TXP PI_INT# RP P PERn MI_LKN E LK_PIE_IH# P E PI_IRY# RPH PERp MI_LKP LK_PIE_IH N PETn N MI_OMP PETp MI_ZOMP +.V_PIE_IH R.Ohm % MI_IROMP T PI_FRME# RP PERn T PERp UP0N F U_PN0 R U 0 U onn. PI_TOP# RP PETn UP0P F U_PP0 R PETp UPN U_PN U U onn. PI_REQ# RP UPP U_PP T TPT R H PI_LK UPN U_PN T TPT P H U U onn. PI_REQ# RP PI_# UPP U_PP T TPT P PI_R UPN J U_PN J U U onn. PI_TRY# RPE T TPT UPP U_PP P K PI_MOI UPN U_PN T TPT P K U FINER PRINT PI_REQ# RPF PI_MIO UPP U_PP L U_ON_O# UPN U_PN RN 0KOhm L U luetooth RP U_ON_O0# U_O# O0# UPP U_PP RN 0KOhm M U_ON_O0# O# UPN U_PN RN 0KOhm M U Newcard RPH RN U_O# U_ON_O# O# UPP U_PP 0KOhm N U_O# O# UPN U_PN E N U MO amera U_O# O# UPP U_PP O#PIO URI# NEWR_O# RN U_O# O#PIO0 URI# 0KOhm O#PIO URI R.Ohm % Y_RT# RN 0KOhm RIN# RN U_O# IHM 0KOhm RN NEWR_O# 0KOhm E0# E# E# E# IRY# PR PIRT# EVEL# PERR# PLOK# ERR# TOP# TRY# FRME# RV_ RV_ RV_ RV_ MH_YN# E E F E0 E 0 F F F F F E H F H0 PI_REQ# PI_REQ# PI_REQ# TPT PI_REQ# PI_REQ# PI_LOK# PLT_RT# PI_INTE# PI_INTF# PI_INT# PI_INTH# TPT TPT TPT TPT PI_NT# PI_NT# LK_IHPI LP PI PI H H L ustom H L H PI_LOK# PI_EVEL# U PI_INTH# RPF F V PERn MI0RXN MI_RXN0 F V PI_ERR# RP 0.UF0V PERp MI0RXP MI_RXP0 E PETn MI0TXN U MI_TXN0 0.UF0V E U PI_PERR# RPH PETp MI0TXP MI_TXP0 0.UF0V 0.UF0V 0 0.UF0V 0.UF0V H H K K J J PERn PERp PETn PETp PERn PERp PETn PETp MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP Y Y W W T T T T T MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP PI_REQ#0 PI_NT#0 PI_REQ# PI_NT# PI_E#0, PI_E#, PI_E#, PI_E#, PI_IRY#, PI_PR, PI_RT#, PI_EVEL#, PI_PERR#, PI_ERR#, PI_TOP#, PI_TRY#, PI_FRME#, LK_IHPI PI_PME# MH_IH_YN# R KOhm U R KOhm Y NZ0PX V PLT_RT# 0PF0V +V R0.KOhm PI_INT# PI_REQ# PI_INTE# PI_INT# PI_INT# PI_INTF# PI_INT# UF_PLT_RT#,,,,,,, UTeK OMPUTER IN. N FJr RP RP RP RP RPE RP RP RP RP.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0.KOHM 0 +V Title : -IHM() Engineer: Frank Xu,, 00 ate: heet of.0

17 RIN# M_LK M_T LINKLERT# M_LINK0 M_LINK U MLK MT LINKLERT# MLINK0 MLINK RI# PIOT0P PIOTP PIOTP PIOTP LK LK F H H E P_I0 PU_elect LK_IH LK_U _PKR PM_U_TT# Y_RT# PM_MUY# M_LERT# PKR U_TT# Y_RT# PIO0M_UY# MLERT#PIO ULK LP_# LP_# LP_# PWROK 0 F TPT T ULK U#,,,0 U# IH_PWROK PF0V 0PF0V,0 LK_EN# TP_PI# TP_PU# T_ET#,, PM_LKRUN#,, PIE_WKE#,,, INT_ERIRQ PM_THERM# Q TLE_ON HN00 WLN_LE_EN EXTMI# VRMPWR 0 F E U F0 H F0 E PIOTPPI# PIO0TPPU# PIO PIO PIO PIOLKRUN# PIOZ_OK_EN# PIOZ_OK_RT# WKE# ERIRQ THRM# VRMPWR PIO PIO PIO IHM PIO PIOPRLPVR TP0TLOW# PWRTN# LN_RT# RMRT# PIO PIO0 PIO PIO PIO PIO PIO PIO PIO PIO PIO Y E0 0 F E R E R 0 0 E0 T_ET#0 P_I P_I TPT T PM_PRLPVR 0 T_LL# PM_PWRTN# T Int P.U UF_PLT_RT#,,,,,,, PM_RMRT# WLN_ON# K_I# TP_LEON _#, TPT M_LK M_T +V P_I[:0] 000: R.0 P_I P_I P_I0 Q HN00 Q HN00 R 0KOhm R 0KOhm +V R 0KOhm R 0KOhm M_LK_ 0,,,, M_T_ 0,,,, R0 0KOhm R 0KOhm +VU M_LK_ M_T_ T_LL# M_LINK M_LINK0 LINKLERT# T_ET# WLN_ON# _# M_LERT# EXTMI# K_I# T_ET#0 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm RN RN RN RN RN RN RN RN RN RN RN RN RN0 RN0 RN0 RN0 +VU +VU +VU M_LK M_T +V TP_PI# TP_PU# PIE_WKE# PM_THERM# INT_ERIRQ PM_LKRUN# VRMPWR IH_PWROK PM_RMRT# R 0KOhm R 0KOhm R0 R R R 0KOhm 0KOhm 0KOhm 0KOhm KOhm RN RN RN RN 0KOhm 0KOhm +V 0KOhm TP_LEON +VU +V UTeK OMPUTER IN. N ustom FJr Title : -IHM() Engineer: Frank Xu,, 00 ate: heet of.0

18 On Edge istribute in PI ection ustom,, 00 UTeK OMPUTER IN. N -IHM(PWR).0 FJr Frank Xu ate: heet of Title : Engineer: +V +V +VU +VU +VREF +VREF_U +.V +.V +.V +.V +VU +VU +V_RT +V +V +.V +V +V +.V +.V +.V_PIE_IH +V +V +.V +VU +VP +VP 0.UFV T TPT 0.UFV 0.UFV 0.UFV 0.UFV 0.UFV T TPT T TPT 0.UFV 0.UFV VPUX UF IHM 0 F E E E F F H H J J K K L L M M N N P P R R R R R T T T T T U U V V W W Y Y E F H E Y L L L L L L M M P P T T U U V V V V V V V V W W U R E E H 0 0 F W P K K K K L L L L L M M N T F K 0 H H J J F H E0 F0 F H VREF_ VREF_ VREF_us Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc 0 Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc 0 Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc 0 Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc 0 Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc 0 Vcc Vcc Vcc Vcc VccMIPLL Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vccus VccUPLL Vccus_0VccLN_0_ Vccus_0VccLN_0_ Vcc_0_ Vcc_0_ Vcc_0_ Vcc_0_ Vcc_0_ Vcc_0_ Vcc_0_ Vcc_0_ Vcc_0_ Vcc_0_0 Vcc_0_ Vcc_0_ Vcc_0_ Vcc_0_ Vcc_0_ Vcc_0_ Vcc_0_ Vcc_0_ Vcc_0_ Vcc_0_0 Vccus_VccLN Vccus_VccLN Vccus_VccLN Vccus_VccLN Vcc_VccH Vccus_VccusH V_PU_IO V_PU_IO V_PU_IO Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc 0 Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc 0 Vcc VccRT Vccus Vccus Vccus Vccus Vccus Vccus Vccus Vccus Vccus Vccus 0 Vccus Vccus Vccus Vccus Vccus Vccus Vccus Vccus Vcc Vcc 0 Vcc Vcc Vcc Vcc Vcc Vccus_0_ Vccus_0_ Vccus_0_ Vcc Vcc Vcc Vcc Vcc 0 Vcc VccTPLL Vcc Vcc 0 Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc T TPT 0.UFV 0.UFV 0.UFV 0.UFV UFV 0.UFV 0.UFV 0.UFV 0.UFV R 0 0.UFV + E 00UF.V 0.UFV T 0 0.UFV 0.UFV 0.UFV T 0 0.UFV 0UF0V 0.UFV + E 00UF.V R Ohm T0 TPT L 00Mhz 0.UFV 0.0UFV L 00Mhz R 0.UFV 0.UFV UE IHM 0 0 E E E E E F F F F F F H H H H H H J J J J J J K K K L L L L L M M M M M M M M M M M M N N N N N N N N N N N N N N N P P P P P P P P P P P R R R R R R R R R T T T T T T T U U U U U U U U U U V V V V V V W W W W Y Y Y Y E E E E E E E E E F F F F F F 0 H H H H H H Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss00 Vss0 Vss0 Vss0 Vss0 Vss0 Vss0 Vss0 Vss0 Vss0 Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss0 Vss Vss Vss Vss 0.UFV

19 UTeK OMPUTER IN ustom FJr Title : chematic page name Engineer: Frank Xu,, 00 ate: heet of.0

20 REV Type ustom 0,, 00 UTeK OMPUTER IN. N R O-IMM0.0 FJr Frank Xu ate: heet of Title : Engineer: M_LK_R M_LK_R0 M Q M Q M Q0 M Q M Q M Q# M M M M M Q M Q M Q# M M M M M M Q M Q M Q M Q M 0 M Q M Q M Q# M_LK_R#0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q# M M M Q M Q M Q M Q0 M Q# M Q M Q M Q M Q M Q M Q0 M Q M M M Q M Q M Q M Q0 M Q M Q M Q M Q# M M 0 M Q0 M Q M Q M M Q M Q M Q M Q M Q M Q M Q M Q M_LK_R# M Q0 M Q M Q M Q M Q M M M Q M Q M Q0 M Q M Q M M Q M Q M Q# M Q#0 M M M M Q M Q M Q M Q0 M M M M0 M Q M Q M Q M Q M Q M M M +.V +V N 0.UFV N 0.UFV 0.UF0V ON V V V V V V V V V V0 V V VP N N N N NTET VREF 0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V NP_N NP_N 0.UF0V ON P 0 0# # K0 K0# K K# KE0 KE # R# WE# 0 L OT0 OT M0 M M M M M M M Q0 Q Q Q Q Q Q Q Q#0 Q# Q# Q# Q# Q# Q# Q# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q _ Q 0PF0V 0UF0V N 0.UFV 0PF0V UF0V N 0.UFV M [:0] 0, M M[:0] 0 M Q[:0] 0 M Q#[:0] 0 M 0, M 0 0, M 0, M_#, M_#0, M_LK_R#0 M_LK_R0 M_KE, M_KE0, M R# 0, M # 0, M_T_,,,, M_LK_,,,, M_OT, M_OT0, M_LK_R# M_LK_R M_VREF_MH,, M Q[:0] 0 M WE# 0,

21 T Type ustom,, 00 UTeK OMPUTER IN. N R O-IMM.0 FJr Frank Xu ate: heet of Title : Engineer: M_LK_R# M_LK_R M_LK_R# M Q M Q M Q M Q M Q# M Q M Q M Q M Q M Q M Q M Q0 M Q M Q0 M M Q M Q M Q0 M Q M Q M Q M M M M Q M Q M M0 M M Q M Q M Q M Q0 M Q M Q M Q M M M M Q M Q M Q M Q M Q0 M M M M M Q0 M Q M M M_LK_R M Q M Q M Q M Q M M Q M Q M Q# M Q# M M 0 M Q M Q M Q M Q M Q# M Q# M M Q M Q M Q M Q M Q M M Q M Q M Q M Q M Q# M Q M Q M Q M Q M Q M Q M Q M Q M M M 0 M M Q0 M Q M Q M M M M Q M Q0 M Q M Q M Q M M M Q M Q M Q# M Q#0 +.V +V +V 0.UF0V ON R P 0 0# # K0 K0# K K# KE0 KE # R# WE# 0 L OT0 OT M0 M M M M M M M Q0 Q Q Q Q Q Q Q Q#0 Q# Q# Q# Q# Q# Q# Q# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q _ Q R 0KOhm 0.UF0V 0PF0V 0UF0V UF0V N 0.UFV 0 0PF0V N 0.UFV N 0.UFV N 0.UFV ON R V V V V V V V V V V0 V V VP N N N N NTET VREF 0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V NP_N NP_N M Q[:0] 0 M M[:0] 0 M Q#[:0] 0 M Q[:0] 0 M [:0] 0, M_OT, M_#, M_KE, M_#, M R# 0, M WE# 0, M 0, M 0, M # 0, M 0 0, M_KE, M_OT, M_VREF_MH,0, M_LK_R M_LK_R# M_LK_R# M_LK_R M_T_,0,,, M_LK_,0,,,

22 0,0 M [:0] 0, M [:0] +0.V +VTTR,0 M_#0 0,0 M R#,0 M_OT,0 M_# 0,0 M WE# M M_#0 M R# M_OT M_# M WE# M 0 M Ohm Ohm Ohm Ohm Ohm Ohm Ohm 0 Ohm RN RN RN RN RNE RNF RN RNH N 0.UFV N 0.UFV N 0.UFV N 0.UFV +.V 0 0.UF0V R KOhm L 00Mhz L M_VREF_MH,0, 0,0 M 0,0 M 0,0 M_KE M M M 0 M 0 M M M M_KE Ohm Ohm Ohm Ohm Ohm Ohm Ohm 0 Ohm RN RN RN RN RNE RNF RN RNH N 0.UFV N 0.UFV N 0.UFV N 0.UFV 0.UF0V R0 KOhm 00Mhz 0,0 M,0 M_KE0 M M M M M M M M_KE0 Ohm Ohm Ohm Ohm Ohm Ohm Ohm 0 Ohm RN RN RN RN RNE RNF RN RNH N 0.UFV N 0.UFV N 0.UFV N 0.UFV 0,0 M #,0 M_OT0 M # Ohm M_OT0 Ohm R R 0.UF0V 0, 0,, 0,,,, 0, 0, 0,,, M M 0 M_KE M M_KE M_# M_OT M # M WE# M R# M_OT M_# M M M M M M 0 M 0 M M_KE M M_KE M M M M M M 0 M M_# M_OT M # M WE# M R# M M_OT M_# Ohm Ohm Ohm Ohm Ohm Ohm Ohm 0 Ohm Ohm Ohm Ohm Ohm Ohm Ohm Ohm 0 Ohm Ohm Ohm Ohm Ohm Ohm Ohm Ohm 0 Ohm Ohm Ohm RN RN RN RN RNE RNF RN RNH RN RN RN RN RNE RNF RN RNH RN RN RN RN RNE RNF RN RNH R0 R 0.UFV 0.UFV 0.UFV 0.UFV 0.UFV 0.UFV 0.UFV 0.UFV 0.UFV 0.UFV 0.UFV 0.UFV 0.UF0V N N N N N N N N N N N N UTeK OMPUTER IN. N ustom FJr Title : Engineer: R TERMINTION Frank Xu,, 00 ate: heet of.0

23 UTeK OMPUTER IN ustom FJr Title : chematic page name Engineer: Frank Xu,, 00 ate: heet of.0

24 E PIO[0]: Tx Power avings Enable 0: 0% Tx output swing V0 pread pectrum -----R : 0 N. +V : full Tx output swing (recommended) PRT OF +V +V_ P : x. (default 0, internal pull-down) L0 own pread 00Mhz pectrum for EMI MK : R0 PIO0 TXM 0KOhm T TPT M R0 0KOhm PIO T TPT VI_0 TXP L ttenuation T0 TPT VI_ J 0 0 R PIO[]: Tx e-emphasis Enable T TPT VI_ VI_ INTERTE TX0M H.UF.V 0.0UFV 0: Tx de-emphasis disbale T TPT VI_ TX0P +V_ M0 TM : Tx de-emphasis enable T TPT VI_ L0 VIP I V_R T TPT VI_ TXM (default 0, internal pull-down) J0 T0 TPT VI_ TXP H0 R VI_ R0 0KOhm VI_ T TXM TPT M R +V_ T VH_0 TXP TPT L U0 R0 mount for Enable H udio VH_ TIM_NO T0 TXM XIN XOUT TPT J R TF VPHTL TXP 0KOhm V_R V V T TPT L TIM_ R P# TI_M VPLK0 TXM T0 ModOUT REF TPT K VIPLK TXP R P_0R R T TPT M OHM Ohm PYN TXM T TXP TPT J VLI R Ohm TI_M EI_T TXM TIM_NO EI_T K EI_LK TXP TRT EI_LK M R KOhm R L PIO R.Ohm N_ K PIO R 0KOhm N_ N_0 +V R mount for MMM (JT Function) N VPNTL_MVP_0 TPV P V_LRM VPNTL_MVP_ TPV RN0.KOhm V_THERM# VPNTL_0 RN0.KOhm H RN0 V_ +V VPNTL_ TXVR_.KOhm H RN0 V_L VPNTL_.KOhm MULTI_FX TXVR_ H U0 MEM_I0 VPLK EXTERNL TXVR_ J R EI_T V_L MEM_I VPT_0 TM TXVR_.KOhm R.KOhm EI_LK V_ LK V J V_+ MEM_I VPT_ PIO V_LRM XP J R 0KOhm V_- MEM_I VPT_ TXVR_ K R 0KOhm PIO LERT# XN V_THERM# T VPT_ TXVR_ PIO OVERT# TPT K R VPT_ TXVR_ 0KOhm T0 TPT L R0 PIO T TPT PNEL_I0 VPT_ TXVR_ 0KOhm L MXM T TPT PNEL_I VPT_ TXVR_ L R0 mount for EEPROM Mb to support HP T0 TPT VPT_ TXVR_ M T VPT_ TXVR_ TPT M.V(? %).V(? %) L T TPT VPT_ TXVR_ N R M-M 0m M-M 0m T TPT VPT_0 TXVR_ +VRM_PU P VPT_ TXVR_0 T +VRM_PU TPT R +PV 00Mhz T TPT VPT_ N Ohm L T VPT_ N_ TPT R R0 T VPT_ N_ +.V TPT P V_VREF T TPT VPT_ N_ +V N 00Mhz T0 TPT VPT_ N_ R Ohm 0 T TPT VPT_ N_ P R UF.V 0.UFV 0UF0V T0 VPT_ N_ TPT P Ohm T TPT VPT_ N_ R 0.UFV T VPT_0 TPT N FOR MM,MM R=Ohm T VPT_ R TPT P VREF VOLTE IVIER I T VPT_ R TPT R (VREF = VR,(.V) =.V) INTLL PLL_PV TO +.V FOR MX-M VPT_ INTLL PLL_PV TO+.V FOR M-M PIO0 FOR MM,MM PIO PIO_0 F VREF VOLTE IVIER I +V_VORE PIO_ F VREF =.V =.V +MPV PIO_ M-M 0m M-M m E ENERL L0 PIO PIO_ E PURPOE L0 PIO PIO_ IO +V_VORE E PIO PIO_ HYN +VRM_PU 00Mhz R PIO_ VYN +PIE_PV, L_KLTEN_V 00Mhz PIO LON L0 0 V_OUT UF.V 0.UFV 0UF0V PIO PIO ROMO RET 0 V_IN PIO ROMI +.VP 0 V_K PIO PIO_0_ROMK V 00Mhz PIO PIO_ 0 PIO PIO_ VQ UF.V 0.UFV 0UF0V V_PIX_PLL R PIO PIO_ L0,,0 PWR_OK_V PIO HP VI PU_VI# 0_0 TIM_ PIO PWRNTL_0 VI +.VP TIM_ V_LRM PIO IN F INTLL PIE_PV TO +.V FOR MM,MM 00Mhz T0 PIO THERML_INT R TPT F INTLL PIE_PV TO +.V FOR MM,MM T TPT TF PIO HP R UF.V 0.UFV 0UF0V T PIO TF TPT PIO_0_PWRNTL_ V_EN PIO PIO EN 0 V_# T TPT PIO ROM +V * M Memory ize T TRT PIO LKREQ TPT T TPT PIO TRT R0 R0 R0 R0 T PIO TI TPT 0KOhm 0KOhm 0KOhm 0KOhm T0 TPT PIO TK 0 T TPT PIO TM Y T PIO TO OMP TPT F MEM_I0 MEM_I amsung T ENERI TPT F MEM_I MEM_I M T TPT ENERI VYN ENERI HYN amsung V_VREF R R R R M VREF V KOhm 0KOhm 0KOhm 0KOhm PIE_PV +PV R0 Hynix PLL_PV VQ.V(? %).0V(? %) P0 M PLL_PV M-MM-M 0m M-MM-M 0m VQ +PIE_PV M Hynix PIE_PV M M PIE_PV VI +V 0 0 VI +MPV Infineon MPV PLL R R R M MPV LOK RET KOhm 0KOhm 0KOhm TI_M R Infineon XTLIN T P M 0 0.V(? 0mV).0V(? %) XTLOUT LK PIO M-M m M-M V_PIX_PLL PIO Hynix PLL_V T 00m PIO M 0 0 T TPT V_FN_PWM LK T_FO THERML Infineon V_- T K R R R M 0 V_+ MINU LK M 0KOhm 0KOhm 0KOhm R 00KOhm PLU PIO[:] = 00: M memory aperture, same as ROM HPE T HPE HP LK strap 00 PIO[:] = 0: M memory aperture, same as ROM 0 MKF strap 0 MMHZPT E N N0 R0 P0 R P R P R P R P R P R P R P M L N N0 P R N P R N N N N N N N H H P R R P R0 P0 R P N N0 N R P R P M L M L M L K K K L M M L K H INTLL TERMINTION REITOR LOE TO I J R M L J H J J H lose to PU INTLL R ON R,, FOR MM,MM R_ RT_RE O NOT INTLL R ON R,, N INTLL 0R T I FOR MM,MM _ RT_REEN.V(? %).V(? %).V(? %).V(? %) M-M 00m M-M 00m M-M m M-M m L L _ RT_LUE +VRM_PU +VRM_PU +V 00Mhz +VI 00Mhz RT_HYN L L0 RT_VYN +.V +.V Ohm R 00Mhz 00Mhz V UF.V 0.UFV 0UF0V UF.V 0.UFV 0UF0V +VI INTLL V TO +.V FOR MX-M INTLL VI TO +.V FOR MX-M INTLL V TO +.V FOR M-M INTLL VI TO +.V FOR M-M TPT T R_.V(? %).V(? %) _0 M-M 0m M-M m L N.V(? %) TPT T0 M-M N M-M m _ +V_ELY +V 00Mhz +VQ TPT T0 L0 L _ +.V +VRM_PU 00Mhz 00Mhz TV_ TV_Y UF.V 0.UFV 0UF0V UF.V 0.UFV TV_V TPT T TPT T INTLL V TO +.V FOR MX-M INTLL VQ TO +.V FOR MX-M INTLL V TO +.V FOR M-M O NOT INTLL VQ FOR M-M +V V_ V_L 0 0.UFV +VQ +VI Ohm R0 R0 R0 R0 R R R +TPV +TXVR 0 0.UFV RT T RT LK VI T VI LK VI_LKN VI_LKP VI_TX0N VI_TX0P VI_TXN VI_TXP VI_TXN VI_TXP VI_TXN VI_TXP VI_TXN VI_TXP VI_TXN VI_TXP R _ RT_LUE RT_REEN RT_RE UF.V UF.V lose to connector R.Ohm.V(? %).V(? %) M-M m M-M m +VI UTek OMPUTER IN ustom +TPV +TXVR R0 Ohm R.Ohm 00Mhz 0 0UF0V INTLL TXVR TO +.V FOR MX-M INTLL TXVR TO +.V FOR M-M 00Mhz 0 0UF0V INTLL TXVR TO +.V FOR MX-M INTLL TXVR TO +.V FOR MX-M R0 Ohm FJr 00Mhz L0 L0 L0 00Mhz L R.Ohm R Ohm,, 00 ate: heet of.v(? %).V(? %) M-M 0m M-M 0m.V(? %).V(? %) M-M m M-M 00m +.V R _ R _ L 00Mhz L0 +VRM_PU +.V +VRM_PU R R +V +.V R R R 00Mhz UF.V 0.UFV 0UF0V INTLL VI TO +.V FOR MX-M INTLL VI TO +.V FOR M-M <Variant Name> R Title : TI_MX-M_MIN Engineer: Frank Xu.0

25 Read-Q & Write-Q for R memory. Read-Q & Write-Q for R memory. ustom,, 00 UTek OMPUTER IN TI_MX-M_Memory.0 FJr Frank Xu <Variant Name> ate: heet of Title : Engineer: M0 M M M0 QM# M M M M M0 QM#0 M Q# M M Q# TET_MLK TET_YLK M M M M M Q# M M QM# M0 M M M M Q M M M M0 M M M M M M M M Q# RM_RT M M M M Q# M M M0 M M Q M Q# M M M QM# M M M M M M0 M M Q#0 RM_RT M M M Q# M M M Q M0 M MVREF_ M M M Q M M M Q M M M Q M M M M Q# QM# M QM# M M0 M0 M M M0 M M M MVREF_0 Q M M M Q0 M QM# M0 M Q M Q# M M0 M M MVREF_ M Q M Q# M0 TET_YLK M0 M QM# M QM# M QM# M0 TET_MLK M M M M M Q M M M M MVREF_0 M M M M M M M M Q M Q# Q0 M M M M M M Q# M M QM# M M Q M M M M M Q QM# Q#0 M Q# M M M QM# M0 M M0 M M M QM#0 QM# QM# M M M M Q Q# M M M M M M +VRM_PU +VRM_PU 0 0.UFV R0 0 Part of V0 MKF H E H F 0 J0 H0 F0 F M M N N R R T T M M P P R R R U U U U V Y Y U U U V W W W W H H J J J J J F F J J J 0 E P R W V J 0 F P P W V H 0 E P P W V E E E F F K K K K K M L M K M0 H Q_0 Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_0 Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_0 Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_0 Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_0 Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_0 Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_0 Q_ Q_ Q_ M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_0 M_ M_ QMb_0 QMb_ QMb_ QMb_ QMb_ QMb_ QMb_ QMb_ Q_0 Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_0 Q_ Q_ Q_ Q_ Q_ Q_ Q_ OT0 LK0 LK0b R0b 0b 0b_0 0b_ KE0 WE0b M_ MVREF MVREF RM_RT TET_MLK TET_YLK MEMTET LKb LK b Rb KE WEb b_0 b_ OT TETEN PLLTET R0.KOhm R0 0 R0 0 R KOhm 0 0.UFV R0.KOhm 0 0.UFV T0 TPT R0 0 R UFV R0.KOhm R0 T0 TPT R 0 Part of V0 MKF P P P P M K K K M M L L J J H H K J J0 J F F 0 F 0 0 J H F J F H F E J E F E J E 0 E M K 0 E H M0 K E F M K E E E 0 0 N N H F H Q_0 Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_0 Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_0 Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_0 Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_0 Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_0 Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_0 Q_ Q_ Q_ M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_0 M_ M_ QMb_0 QMb_ QMb_ QMb_ QMb_ QMb_ QMb_ QMb_ Q_0 Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_0 Q_ Q_ Q_ Q_ Q_ Q_ Q_ OT0 LK0 LK0b R0b 0b 0b_0 0b_ KE0 WE0b M_ MVREF MVREF LKb LK b Rb KE WEb b_0 b_ OT R0 0 R0 0 OT # OT LK0# R0# LK M[..0] M[:0] LK WE0# LK# # Q[..0] KE Q#[..0] LK# WE# Q#[..0] KE0 KE0 M[:0] 0# 0# 0# OT0 QM#[..0] # R# LK0 R0# LK0# LK0 Q[..0] KE M[..0] # 0# WE# OT0 R# WE0# QM#[..0]

26 R0 Install.K for M-M,MM Install 0K for M-M,MM,, 00 UTek OMPUTER IN TI_MX-M_PI-E.0 FJr Frank Xu <Variant Name> ate: heet of Title : Engineer: PIE_TXP PIE_TXP PIE_TXP PIE_RXN PIE_TXN0 PIE_RXN PIE_RXN PIE_RXN PIE_TXN PIE_RXP PIE_TXN0 PIE_TXP PIE_RXP PIE_TXN PIE_TXP PIE_RXP PIE_RXN PIE_TXP PIE_RXN PIE_RXN0 PIE_RXP0 PIE_TXP PIE_TXN PIE_TXN PIE_RXN PIE_TXN PIE_RXP PIE_RXP PIE_TXP PIE_TXN PIE_RXN0 PIE_RXP PIE_RXP PIE_RXN PIE_TXN PIE_TXP PIE_RXN PIE_TXN PIE_RXP PIE_TXP PIE_TXN PIE_TXN PIE_RXP0 PIE_TXP0 PIE_RXN PIE_TXN PIE_RXP PIE_TXP PIE_RXP PIE_RXN PIE_TXP PIE_TXN PIE_TXP0 PIE_TXP PIE_RXN PIE_RXP PIE_RXP PIE_TXN PIE_RXP PIE_RXN PIE_RXP PIE_TXN PIE_RXN PIE_TXP PIEN_RXN PIE_TXN PIEN_RXP PIE_TXP PIEN_RXP PIE_TXP PIEN_RXP PIEN_RXN PIE_TXN PIEN_RXP PIEN_RXN PIE_TXN PIEN_RXP0 PIE_TXN PIEN_RXN PIE_TXN PIEN_RXP PIE_TXN0 PIE_TXP PIE_TXN0 PIEN_RXP PIE_TXP PIEN_RXP PIE_TXP0 PIE_TXN PIEN_RXN PIEN_RXN PIE_TXN PIE_TXP PIEN_RXN PIE_TXP PIE_TXP PIEN_RXP PIE_TXP PIE_TXN PIE_TXP PIEN_RXN PIEN_RXP PIEN_RXP PIEN_RXN PIE_TXP PIEN_RXN PIEN_RXP PIEN_RXN PIE_TXN PIE_TXP PIE_TXP PIE_TXN PIEN_RXN0 PIE_TXP PIE_TXN PIEN_RXN0 PIEN_RXN PIE_TXN PIEN_RXP PIEN_RXN PIEN_RXP PIE_TXN PIE_TXN PIEN_RXP0 PIEN_RXN PIE_TXP0 PIEN_RXP PIE_TXP +.VP 0.UFV R0 R0 Ohm 0 0.UFV 0.UFV 0 0.UFV 0.UFV 0.UFV 0.UFV 0.UFV 0 0.UFV 0.UFV 0.UFV 0.UFV 0 0.UFV 0 0.UFV R0.KOhm 0.UFV 0.UFV 0.UFV 0 0.UFV R0 KOhm % 0 0.UFV 0 0.UFV 0.UFV 0 0.UFV 0 0.UFV 0.UFV Part of ORE V0E MKF P P P R R R R R F R 0 U H F U J E V V T F V V M E0 K K K K K M K L P M M K M N W W W U P P Y U0 U U U F F F F E E N N N N N R P P P P P P0 R U P R0 R R R R V K U K K E K H J F J J J K0 J F K F F0 J J F J J H L L K V W V0 V V V V V K V W0 W W W W 0 0 F W F F F F F K0 F F F J H F 0 N K J J J F N K N R M K0 R R V_ V_ V_ V_ V_ PIE_V_ PIE_V_ PIE_V_ PIE_V_ PIE_V_ PIE_V_ PIE_V_ PIE_V_ V_ V_ V_ V_ PIE_V_ V_0 V_ V_ V_ PIE_V_0 V_ V_ PIE_V_ PIE_V_ PIE_V_ V_ V_ PIE_V_ PIE_V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ PIE_V_ PIE_V_ PIE_V_0 PIE_V_ PIE_V_ PIE_V_ PIE_V_ V_ V_ V_0 PIE_V_ PIE_V_ V_ V_ V_ PIE_V_ V_0 PIE_V_ PIE_V_0 PIE_V_ PIE_V_ PIE_V_ PIE_V_ PIE_V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_00 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ PIE_V_ PIE_V_ PIE_V_ PIE_V_ PIE_V_ PIE_V_ PIE_V_ PIE_V_0 PIE_V_ PIE_V_ PIE_V_ V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_ V_ V_ V_ V_ V_ RV_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 RV_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ MEH_ MEH_ MEH_ 0.UFV 0.UFV 0 0.UFV 0 0.UFV 0.UFV 0.UFV PRT OF alibration P I - E X P R E I N T E R F E lock V0 MKF 0 F F0 F F 0 K J J J H H 0 0 F E E E J J0 M W W0 W W V V0 Y Y W W V V U U0 U U R R0 V U U U T T R R J K K K PIE_TX0P PIE_TX0N PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_RX0P PIE_RX0N PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_REFLKP PIE_REFLKN PERT PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TX0P PIE_TX0N PIE_TXP PIE_TXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RX0P PIE_RX0N PIE_RXP PIE_RXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_LRN PIE_LRP PIE_LI RV_ RV_ 0.UFV 0.UFV PLT_RT# LK_PIE_MM# LK_PIE_MM PIEN_RXP[0..] PIE_RXN[0..] PIEN_RXN[0..] PIE_RXP[0..]

27 +VRM_PU N.V(? %) M-MM-M N M-MM-M 00m RR:.V 0 0 R:. ~ V 0UF0V 0UF0V 0UF0V R: R: 0. +VRM_PU +VRM_PU +VRM_PU +VRM_PU _0 FOR MM,MM,MM N MM VR OR VR N E.V OR.V FOR EXT TM ON V PORT FOR MM N MM VR N VR MUT E.V IF MULTI PU ON V PORT +V_ELY +VRM_PU +VR +VRM_PU +V +.V.V(? %).V(? %) M-M 0m M-M 0m 00Mhz INTLL LVR TO +.V FOR MM,MM LLOW TRP FOR POILE LVR TO +.V FOR MM,MM INTLL LVR TO+.V FOR MM,MM N.V(? %) M-M N M-M 0m L0 +VRM_PU 00Mhz LV FOR MM,MM INTLL LV TO +.V UF0V FOR MM,MM LV I NO ONNET +VRM_PU UF.V 0 UF.V UF.V +.V 000PF0V 0.UFV 0.UFV FOR MM,MM INTLL LPV TO+.V FOR MM,MM INTLL LPV TO+.V 000PF0V L 000PF0V L0 L0 L L L0 L 0 0UF0V.V(? %).V(? %) M-M 0m M-M 0m 0.UFV 0.UFV 000PF0V 000PF0V 00Mhz 00Mhz UFV 00Mhz 00Mhz 00Mhz 00Mhz 0.UFV 0.UFV 000PF0V 000PF0V UFV LVR UF.V UF0V +VRM_L +VRM_PU LPV 0.UFV 0.UFV 000PF0V 0.UFV,,0 0.UFV 0 UFV L0 L0 L0 L0 PWR_OK_V 00Mhz 00Mhz 0 0UF0V 00Mhz 0 0UF0V 00Mhz 0 0UF0V 0 0UF0V R0 UF.V UF.V UF.V UF.V +V_ELY OPTIONL R NETWORK TO FINE TUNE POWER EQUENIN 0 0.UFV 0.UFV 0.UFV KOhm 0.UFV +V_ELY +VR V_MEM_LK0 V_MEM_LK V_MEM_LK V_MEM_LK JP LPV +VRM Q0 IRLML0.V(? %) 0m.V(? %) 0m LVR LV 0.UFV L_JUMP R0 00KOhm Q0 HN00 0 0UF0V.V(? %) M-M. M-M. +V UFV.V(? %) M-M 0m M-M 0m J H K L M N N N N M P P M R R M J J L K +VRM_PU INTLL V_T TO +.V FOR MM,MM INTLL V_T TO +.V FOR MM,MM L +.V 00Mhz +V_T L +VRM_PU 00Mhz.V(? %).0V(? %) M-M 0m M-M 00m 0 0UF0V UF.V UF.V 0.UFV V_MEM_LK0 V_MEM_LK V_MEM_LK V_MEM_LK V0F PRT OF LVR_ LVR_ LV_ LV_ LVR_ LVR_ LVR_ LVR_ LVR_ LVR_ LVR_ LVR_ LVR_ LVR_0 LVR_ LVR_ LVR_ LVR_ LPV LPV MKF UFV +P +V_VORE ontrolvry_l 0.UFV ION TXLK_UP TXLK_UN TXOUT_U0P TXOUT_U0N TXOUT_UP TXOUT_UN TXOUT_UP TXOUT_UN TXOUT_UP TXOUT_UN TXLK_LP TXLK_LN TXOUT_L0P TXOUT_L0N TXOUT_LP TXOUT_LN TXOUT_LP TXOUT_LN TXOUT_LP TXOUT_LN 0.UFV 0 H H L L L L M0 M P0 T Y M K0 K K K L L L 0 F0 R R U U E E F E P R N P W U V V W L_KLTEN_V L L V0 VR_ VR_ VR_ VR_ VR_ VR_ VR_ VR_ VR_ VR_0 VR_ VR_ VR_ VR_ VR_ VR_ VR_ VR_ VR_ VR_0 VR_ VR_ VR_ VR_ VR_ VR_ VR_ VR_ VR_ V_T_ V_T_ V_T_ V_T_ V_T_ V_T_ V_T_ V_T_ VR_ VR_ VR_ VR_ VR_ VR_ VR_ VR_ VRH_ VRH_ VRH_ VRH_ VRH_ VRH_ VRH_ VRH_ N_ N_ P_ P_ V_ V_ MKF L RIHTNE ONTROL (PWM) J K L N N P R H K L R P N N P R P R P R R0 R0 PRT OF P O W E R 0KOhm LV_ULKP LV_ULKN LV_U0P LV_U0N LV_UP LV_UN LV_UP LV_UN LV_LLKP LV_LLKN LV_L0P LV_L0N LV_LP LV_LN LV_LP LV_LN ** FOR NO K IIN O NOT INTLL FET OR REULTOR LOI N INTLL E N REITOR PIE_VR_ PIE_VR_ PIE_VR_ PIE_VR_ PIE_VR_ PIE_VR_ PIE_VR_ PIE_VR_ PIE_V_ PIE_V_ PIE_V_ PIE_V_ PIE_V_ PIE_V_ PIE_V_ PIE_V_ PIE_V_ PIE_V_0 PIE_V_ PIE_V_ L_KLTEN_V, L_V_EN +V_VORE +V V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ VI_ VI_ VI_ VI_ R0 R L M N N N P P R U V V W W F N N N N N P P P P V V V W W W W E E E E R R R R R U U U U V M M P P R0 00KOhm R0 PIE_V PIE_V INTLL PIE_VR TO +.V FOR MM,MM PIE_VR I NO ONNET FOR MM,MM L0 00Mhz +VRM_PU INTLL PIE_V TO +.V FOR MX-M INTLL PIE_V TO +.V FOR M-M 0UF0V <Variant Name> UTek OMPUTER IN ustom +P +V_VORE 0KOhm 0.UFV R0 Q0 I0 V_EN 0 UF.V 0 UF0V 0UF.V 0.UFV 0 0.UFV 0UF.V UF0V.V(? %).0V(? %) M-MM-M. M-MM-M.00 0.V -.V(? %).0V -.V(? %) M-M ~ M-M ~ M-M ~0 M-M ~ Q0 I0_T_E FJr 0 0UF0V 0.UFV 0.UFV 0.UFV L0 00Mhz 00Mhz UF.V UFV 0UF.V Q0 HN00 0 UF0V 0.UFV 0.UFV R0 For MM Rev xx parts which do not support back bias,.v for Rev.V or.v for Rev x and x Title : Engineer:,, 00 ate: heet of UF0V 0.UFV UF.V UF.V 0.UFV R0 L +V_VORE +.VP +.V +.V TI_MX-M_POWER Frank Xu.0

28 ustom,, 00 UTek OMPUTER IN TI_MX-M_VRM_.0 FJr Frank Xu <Variant Name> ate: heet of Title : Engineer: KE0 LK# M0 VERF M WE# LK M M M VERF # M0 M VERF M OT0 # M M0 VERF VERF M0 M KE M M M M M LK0# M M M R0# M M M M M 0# M M M M LK0 M M VERF WE0# M M M M VERF M 0# M M M M M M M0 VERF M M M M M M M M M M M M0 OT M M0 M M0 M LK# LK LK0# LK0 R# QM# QM# QM# Q Q Q Q Q# Q# Q# Q# M M M M0 M M M M M M M M M M M M M M M M M0 M M M QM# M M M M M0 M M M R0# # WE0# OT0 M0 M # M M M M KE0 M M M M KE M M0 OT M M 0# WE# R# M 0# M M M M M M0 M M Q#0 Q0 Q# Q QM# QM#0 M M M M0 M M M M M M M0 M M M M M M M M M M0 M M M Q Q# Q Q# QM# QM# +VRM_R +VRM_R +VRM_R +VRM_R +0.V +VRM_R +VRM_R +VRM_R +VRM_R +VRM_R +VRM_R +VRM_R +VRM +VRM_R 0 0.0UFV 0UF0V RN0 Ohm RN0E Ohm R.KOhm 0.UFV RN0 Ohm R.KOhm UF.V RN0 Ohm RN0H Ohm VRM HYTFL_ E E E E E F F F F F F H H H H H H J J J J J J K K K K K L L L L L M M M M M N N N N N P P P P P R R R R R E V N V VQ UQQ VQ UM VQ UQQ VQ UQQ VQ VQ UQ0Q0 VQ0 UQQ VQ UQQ UQQ VQ0 UQQ V N V VQ VQ LQQ VQ LM LQ VQ LQQ VQ LQQ VQ VQ LQ0Q0 VQ LQQ VQ LQQ LQQ VQ LQQ VL VREF V VL K V KE WE# R# K# OT N 0 # # 0P 0 V V V V N N N UQ UQ# VQ LQ# 0.UFV RN0 Ohm R0.KOhm R0 Ohm 0.UFV 0.0UFV RN0F Ohm R Ohm RN0H Ohm 0.UFV 0 0.UFV c UFV 0.0UFV R0.KOhm R0.KOhm RN0 Ohm R0.KOhm VRM HYTFL_ E E E E E F F F F F F H H H H H H J J J J J J K K K K K L L L L L M M M M M N N N N N P P P P P R R R R R E V N V VQ UQQ VQ UM VQ UQQ VQ UQQ VQ VQ UQ0Q0 VQ0 UQQ VQ UQQ UQQ VQ0 UQQ V N V VQ VQ LQQ VQ LM LQ VQ LQQ VQ LQQ VQ VQ LQ0Q0 VQ LQQ VQ LQQ LQQ VQ LQQ VL VREF V VL K V KE WE# R# K# OT N 0 # # 0P 0 V V V V N N N UQ UQ# VQ LQ# 0.UFV R0 Ohm RN0 Ohm RN0 Ohm 000PF0V 0.UFV R0.KOhm 0.0UFV 0 0PF0V 0 0.UFV RN0 Ohm 0.UFV 0.UFV 0 0.UFV RN0E Ohm RN0 Ohm 0 RN0 Ohm 0 0.UFV 0.UFV 0.UFV RN0H Ohm L0 00Mhz 0.UFV L0 00Mhz 0 0UF0V RN0 Ohm 0 0.UFV RN0 Ohm 0 000PF0V 0.UFV L0 00Mhz 0 0PF0V RN0 Ohm UF.V VRM0 HYTFL_ E E E E E F F F F F F H H H H H H J J J J J J K K K K K L L L L L M M M M M N N N N N P P P P P R R R R R E V N V VQ UQQ VQ UM VQ UQQ VQ UQQ VQ VQ UQ0Q0 VQ0 UQQ VQ UQQ UQQ VQ0 UQQ V N V VQ VQ LQQ VQ LM LQ VQ LQQ VQ LQQ VQ VQ LQ0Q0 VQ LQQ VQ LQQ LQQ VQ LQQ VL VREF V VL K V KE WE# R# K# OT N 0 # # 0P 0 V V V V N N N UQ UQ# VQ LQ# RN0F Ohm R Ohm RN0E Ohm VRM HYTFL_ E E E E E F F F F F F H H H H H H J J J J J J K K K K K L L L L L M M M M M N N N N N P P P P P R R R R R E V N V VQ UQQ VQ UM VQ UQQ VQ UQQ VQ VQ UQ0Q0 VQ0 UQQ VQ UQQ UQQ VQ0 UQQ V N V VQ VQ LQQ VQ LM LQ VQ LQQ VQ LQQ VQ VQ LQ0Q0 VQ LQQ VQ LQQ LQQ VQ LQQ VL VREF V VL K V KE WE# R# K# OT N 0 # # 0P 0 V V V V N N N UQ UQ# VQ LQ# UFV 0.UFV R0 Ohm 0 0.UFV L0 00Mhz R0 Ohm R Ohm 000PF0V 0 UFV UFV 000PF0V 0 0.0UFV RN0 Ohm 0 0.0UFV RN0 Ohm RN0F Ohm R0.KOhm UFV LK R# LK# M[..0] OT # KE0 KE WE# QM#[..0] LK0# LK0 0# # M[..0] R0# Q#[..0] Q[..0] 0# WE0# M[..] OT0

29 ustom,, 00 UTek OMPUTER IN TI_MX-M_VRM_.0 FJr Frank Xu <Variant Name> ate: heet of Title : Engineer: VERF 0# M M M LK M LK0 M0 M0 M M M M M M M M VERF M LK# M M M M M M M M R0# # WE0# M KE M OT M M M0 R# M 0# M WE# M M M VERF M M KE0 M LK0# M # M M0 M VERF VERF M0 M0 M M M OT0 VERF LK# LK M M M M M M0 M M M M0 M M M M M M M M M0 M M M M M M M M M M M M M QM# Q# Q Q QM# Q# Q Q Q# QM# Q# QM# KE0 R# WE# M M0 M M M M M R0# M WE0# 0# M M M OT0 M 0# M0 # M OT KE # M Q Q# QM# M M M M M M M M0 Q Q# M0 M M M M M0 M Q M M M M M M QM# Q# Q#0 M M0 M M LK0 M M M0 M M M M LK0# M M VERF Q0 M M VERF M M M QM# QM#0 M0 M M M M M M M +VRM_R +VRM_R +VRM_R +VRM_R +VRM_R +VRM_R +VRM_R +VRM_R +VRM_R +VRM_R +VRM_R +VRM_R +0.V 0.UFV R0.KOhm RN0 Ohm RN0H Ohm 0 0.UFV R0.KOhm 0 0.UFV 000PF0V 0 pf0v 00 RN0 Ohm 0 000PF0V VRM_ L0 00Mhz 0.0UFV VRM_ R.KOhm 0 000PF0V VRM_ 0.UFV VRM_ 0.UFV RN0 Ohm VRM HYTFL_ E E E E E F F F F F F H H H H H H J J J J J J K K K K K L L L L L M M M M M N N N N N P P P P P R R R R R E V N V VQ UQQ VQ UM VQ UQQ VQ UQQ VQ VQ UQ0Q0 VQ0 UQQ VQ UQQ UQQ VQ0 UQQ V N V VQ VQ LQQ VQ LM LQ VQ LQQ VQ LQQ VQ VQ LQ0Q0 VQ LQQ VQ LQQ LQQ VQ LQQ VL VREF V VL K V KE WE# R# K# OT N 0 # # 0P 0 V V V V N N N UQ UQ# VQ LQ# RN0 Ohm R0.KOhm RN0 Ohm 0.UFV 0.0UFV VRM_ 0 0.0UFV VRM_ R0 Ohm RN0 Ohm UF.V VRM_ 0 0UF0V 0.0UFV VRM_ RN0 Ohm 0 RN0 Ohm UFV VRM_ 0 0.UFV c00 R0 Ohm 0.UFV R0.KOhm 0 0.0UFV 0.UFV VRM_ 0.UFV c00 0.UFV c00 VRM0 HYTFL_ E E E E E F F F F F F H H H H H H J J J J J J K K K K K L L L L L M M M M M N N N N N P P P P P R R R R R E V N V VQ UQQ VQ UM VQ UQQ VQ UQQ VQ VQ UQ0Q0 VQ0 UQQ VQ UQQ UQQ VQ0 UQQ V N V VQ VQ LQQ VQ LM LQ VQ LQQ VQ LQQ VQ VQ LQ0Q0 VQ LQQ VQ LQQ LQQ VQ LQQ VL VREF V VL K V KE WE# R# K# OT N 0 # # 0P 0 V V V V N N N UQ UQ# VQ LQ# RN0 Ohm RN0H Ohm 0 0.UFV VRM_ 0.UFV c00 0.UFV c00 RN0 Ohm R Ohm UFV VRM_ UFV VRM_ 0.UFV R0 Ohm L0 00Mhz 0.UFV VRM_ R0.KOhm 0 0.UFV c00 RN0 Ohm RN0F Ohm UF.V VRM_ RN0F Ohm L0 00Mhz R Ohm R Ohm RN0 Ohm 0 VRM HYTFL_ E E E E E F F F F F F H H H H H H J J J J J J K K K K K L L L L L M M M M M N N N N N P P P P P R R R R R E V N V VQ UQQ VQ UM VQ UQQ VQ UQQ VQ VQ UQ0Q0 VQ0 UQQ VQ UQQ UQQ VQ0 UQQ V N V VQ VQ LQQ VQ LM LQ VQ LQQ VQ LQQ VQ VQ LQ0Q0 VQ LQQ VQ LQQ LQQ VQ LQQ VL VREF V VL K V KE WE# R# K# OT N 0 # # 0P 0 V V V V N N N UQ UQ# VQ LQ# RN0 Ohm R.KOhm 0 0PF0V R0.KOhm RN0F Ohm RN0E Ohm 0 0.UFV c00 L0 00Mhz UFV VRM_ 000PF0V VRM_ R0 Ohm RN0H Ohm RN0E Ohm 0UF0V RN0 Ohm RN0E Ohm 0.0UFV VRM_ 0 0PF0V VRM HYTFL_ E E E E E F F F F F F H H H H H H J J J J J J K K K K K L L L L L M M M M M N N N N N P P P P P R R R R R E V N V VQ UQQ VQ UM VQ UQQ VQ UQQ VQ VQ UQ0Q0 VQ0 UQQ VQ UQQ UQQ VQ0 UQQ V N V VQ VQ LQQ VQ LM LQ VQ LQQ VQ LQQ VQ VQ LQ0Q0 VQ LQQ VQ LQQ LQQ VQ LQQ VL VREF V VL K V KE WE# R# K# OT N 0 # # 0P 0 V V V V N N N UQ UQ# VQ LQ# RN0 Ohm 0.UFV WE# KE0 # LK0# 0# M[..] LK0 QM#[..0] # R0# Q#[..0] WE0# Q[..0] R# LK KE LK# OT0 OT 0# M[..0] M[..0]

30 +V +V V_# upport HP : pull low 0K ohm R00 0KOhm R00 0KOhm R00 0KOhm V_IN +V U00 V_K Q V_OUT # W# HOL# MP0_VMNTP <Variant Name> UTeK OMPUTER IN ustom FJr Title : V_PI_ROM Engineer: Frank Xu,, 00 ate: heet of 0.0

31 U_PN U_PP ON IE IE WTO_ON_P R R 0.UFV L +V UPN 00MhzUPP L00 00Mhz 0.UF0V UPN UPP 0.UF0V 0.0 UTeK OMPUTER IN ustom FJr Title : FINER PRINT Engineer: Frank Xu,, 00 ate: heet of.0

32 PLE E iodes near V port R0. ustom,, 00 UTeK OMPUTER IN RT.0 FJr Frank Xu ate: heet of Title : Engineer: RT_RE VYN_RT RT_LUE RT_REEN HYN_RT _T_ON HYN_RT +V_RT_ +V_RT T _LK_ON VYN_RT +V_RT LK RT_R_ON RT ON _T_ON VYN_ON _LK_ON VYN_ON RT ON HYN_ON HYN_ON +V +V +V +V +V +V +V +V +V +V +V +V ON _U_PR 0 PF0V c00 Q HN00 0PF0V c00 V RN.KOHM pf0v 00 0PF0V c00 PF0V c00 Q HN00 RN.KOHM L 00Mhz Q HN00 L Ohm00Mhz L Ohm00Mhz V RN.KOHM 0PF0V c00 V V L Ohm00Mhz pf0v 00 Q HN00 L 00Mhz V RN.KOHM 0 NW PF0V c00 00 pf0v 00 pf0v 00 RT_RE RT T RT_LUE RT_VYN RT_REEN RT_HYN RT LK

33 L acklight ontrol L_V_EN +V Q HN00 R0 00KOhm r00 R 00KOhm r00 +V L Power R 0KOhm r00 Q0 HN00 R NW 0 UFV 00 r00 0 Q IV +VL UFV c00 0.0UFV L 00Mhz 0 0.UFV c00 +V able Requirement: Impedence: 00 ohm +- 0% Length Mismatch <= 0 mils Twisted Pair(Not Ribbon) Maximum Length <= " 0 0 0UF0V UF0V c UFV c00 +V_L EI_LK EI_T +V_L L L L LV Interface ON TO_ON_0P LV_L0N LV_UN LV_L0P LV_UP LV_LN LV_U0N LV_LP 0 0 LV_U0P LV_LN LV_UN LV_LP LV_UP LV_LLKN 0 0 LV_ULKN LV_LLKP LV_ULKP 00Mhz L0 00Mhz +V 00Mhz 0 0 +V_L 0 0.UFV c PF0V 0 00PF0V INVERTER Interfacepeaker ONN. PNEL I = : WX+ 0x00 PNEL I = 0 : WX 0x00 PNEL I0 REERVE FOR VENOR,,,0, _T_Y U# LI_E# L_KLTEN_V L_KOFF# L 00Mhz TW +V_L TW +VIN_INV UFV c00_h R 0KOhm r00 L_EN INTMI_P INTMI_N +V L_EN L_ LI_E# R0. U_PN U_PP 0OHM 0OHM RN RN +VIN_INV LI_E#_ON L_EN_ON L ON +V_ON 0OHM 0OHM 0OHM 0OHM UPN UPP RN RN RN RN L_EN_ON L ON LI_E#_ON +V_ON 00PF0V 0.UFV c00 00PF0V 0.UFV c00 R0. L +V + 00Mhz E UF.V 0.UFV c00,, 00 ate: heet of ON R0. WTO_ON_0P UPN UPP amera UTeK OMPUTER IN Engineer: Frank Xu ustom FJr Title : LV & INVERTER.0

34 UTeK OMPUTER IN ustom FJr Title : chematic page name Engineer: Frank Xu,, 00 ate: heet of.0

35 TV OUT +V V +V V +V V TV_V TV_Y TV_ TV_V TV_Y TV_ R R R Ohm Ohm Ohm L 00Mhz V_ON L 00Mhz Y_ON L 00Mhz _ON 0.PF0V.PF0V.PF0V.PF0V.PF0V.PF0V c00 c00 c00 c00 c00 c00 V_ON Y_ON _ON ON V V Y N 0 MINI_IN_P -00 hange to 00 PLE E iodes near TV port R L HOKE_P R R R0. VI VI_TXP VI_TXN VI_TXP VI_TXN VI_TXP VI_TXN VI_TXP VI_TXN VI_TX0P VI_TX0N VI_TXP VI_TXN VI_LKP VI_LKN L0 HOKE_P R R L HOKE_P R R L0R0. HOKE_P R R L HOKE_P R R L0 R0. HOKE_P R R L HOKE_P R R. 0 0 ON TM_T_+ TM_T_- TM_T_+ TM_T_- TM_T_+ TM_T_- TM_T_+ TM_T_- TM_T_0+ TM_T_0- TM_T_+ TM_T_- TM_LK+ TM_LK- P_ P_ NP_N NP_N VI_ON_P HOT_PLU_ETET _K _T V_YN _for+v +V_POWER TM_LK_hield TM hield TM_T hield TM_T_0_hield +V +V_VI T RN.KOHM R HPE 0KOhm +V_VI 00PFV RN.KOHM Q HN00 +V Q HN00 RN.KOHM UTeK OMPUTER IN Engineer: Frank Xu ustom +V RN.KOHM VI LK VI T FJr Title : TV OUT & VI ON.,, 00 ate: heet of.0

36 UTeK OMPUTER IN ustom FJr Title : chematic page name Engineer: Frank Xu,, 00 ate: heet of.0

37 Thermal ensor Q HN00 M_LK M_THRM +V +V M_THRM M_THRM THRM_LERT# RN0 0KOhm RN0 0KOhm RN0 0KOhm RN0 0KOhm M_T M_THRM Q HN00 THRM_LERT# M_THRM M_THRM 00PF0V 00PF0V Max: m U LK V XP LERT# XN OVERT# MXM +V_THM R 0 0.UF0V +V 0 H_THERM H_THERM O#_O H_THERM H_THERM O#_O H_THERM H_THERM 000PF0V FN ontrol H H FJ- FJ- NI0M0- FN_PWM FN0_TH +V T R.KOhm +V R0. +V + E 00UF0V NW 00PF0V 0.UF0V +V_FN 00PF0V ON IE IE Wto_ UTeK OMPUTER IN. N ustom FJr Title : Engineer: THER ENOR & FN Frank Xu,, 00 ate: heet of.0

38 UTeK OMPUTER IN ustom FJr Title : chematic page name Engineer: Frank Xu,, 00 ate: heet of.0

39 Q HN00 PU_elect In Intel K-0M R schematics: HORT_PIN Q R, R use. Ohm and R R0. uses Ohm. HN00 IN_O#, TIM_NO Latched Input elect ITP_ENPILK_F0 0 = R Pair = PEREQ# ELPIE0_L#PI_LK 0 = L lock (MHz) = PU_ITP Pair = PI Express (00MHz) ITP_EN PI_LKREQ_EL 0 = PILK() REQ_EL +V LK_U L 00Mhz +V +V ELPIE0_L# R ELL_#PILK_F 0 = MHzMHz# Pair = L_LK Pair ELL_# XIN_LK FL FL +V_V R +V % R0. LK_EPI LK_PI LK_TPMPI LK_IHPI LK_PI R 0KOhm R 0 0UF0V 0PF0V 0KOhm 0PF0V, 0,0,,,,0,,, 0PF0V 0.UFV JP TIM_ LK_EPI LK_PI LK_TPMPI LK_PI LK_IHPI M_LK_ M_T_ 0PF0V R 0.UFV R0 R0 0PF0V Ohm.KOhm Ohm Ohm Ohm Ohm 0KOhm 0KOhm PF0V X.Mhz +-0ppm0PF 0.UFV 0.UFV R R0 Ohm 0PF0V KOhm XOUT_LK PF0V 0.UFV R R R R R R R0 00PF0V 00PF0V +V_LK XIN_LK XOUT_LK LK_# LK LK_M ELPIE0_L# _LK_PI _LK_TPMPI REQ_EL ELL_# ITP_EN R0 Ohm % R 0KOhm LK F EL EL EL0 PU_EL0 PU_EL PU_EL 0 U VPIEX VPIEX VPIEX PWRVE# VPU V X X FIXL_TPIEX0T L_PIEX0 FLU_MHz FLTET_MOE ELPIEX0_L#PILK PILK PILK PILKREQ_EL ELL_#PILK_F ITP_ENPILK_F0 LK T IREF I0LFT Pin,,,, : Internal Pull-Up Pin : Internal Pull-own L L L H R0. H H.V~.V Max: 00m Reserved for ebug & Expriment 0.UFV R KOhm +VP V VREF PIPIEX_TOP# PU_TOP# PULKT PULK PULKT0 PULK0 PULKT_ITPPIEXT PULK_ITPPIEX PEREQ#PIEXT PEREQ#PIEX PIEXT PIEX PIEXT PIEX PIEXT PIEX PIEXT PIEX PIEXT PIEX PIEXT PIEX TLKT TLK OTT_MHz OT_MHz PEREQ# PEREQ# Vtt_Pwrd#P REFFLTET_EL REF0 0.UFV R KOhm R KOhm +V_VPI +V_V LK_MH LK_MH# LK_PU LK_PU# LK_PIE LK_PIE# PEREQ# PEREQ# LK_PIE LK_PIE# LK_PIE LK_PIE# LK_PIE LK_PIE# LK_PIE LK_PIE# LK_PIE LK_PIE# LK_T LK_T# PEREQ# PEREQ# REF REF0 R0 KOhm L 00Mhz +V_VREF FL FL FL R R R R R R R R R R R R R R R R R R0 R0 R0 TPT TPT R R T T0 +V Ohm Ohm +V KOhm KOhm KOhm KOhm 0.UFV TP_PI# TP_PU# Ohm Ohm Ohm Ohm Ohm Ohm Ohm Ohm Ohm Ohm Ohm Ohm Ohm Ohm Ohm Ohm R0 0KOhm.KOhm Ohm 0PF0V RN RN RN RN FL 0.UFV LK_MH_LK LK_MH_LK# LK_PU_LK LK_PU_LK# R0. JP HORT_PIN JP HORT_PIN LK_PIE_NEWR LK_PIE_NEWR# LK_MINIR_REQ# LK_NEWR_REQ# LK_PIE_MINIR LK_PIE_MINIR# LK_PIE_MM LK_PIE_MM# LK_PIE_LN LK_PIE_LN# LK_MH_PLL LK_MH_PLL# LK_PIE_IH LK_PIE_IH# LK_T_IH LK_T_IH# LK_EN#,0 LK_IH MH_EL0 MH_EL MH_EL +V_VPI ustom LK_MH_LK LK_MH_LK# LK_PU_LK LK_PU_LK# LK_PIE_NEWR LK_PIE_NEWR# LK_PIE_MINIR LK_PIE_MINIR# LK_MH_PLL LK_MH_PLL# LK_PIE_IH LK_PIE_IH# LK_T_IH LK_T_IH# LK_PIE_MM LK_PIE_MM# LK_PIE_LN LK_PIE_LN# PEREQ# 0 = PIEX0 Not ontrolled = PIEX0 ontrolled PEREQ# PEREQ# 0 = PIEX Not ontrolled = PIEX ontrolled PEREQ# PEREQ# 0 = PIEX Not ontrolled = PIEX ontrolled () PEREQ# PEREQ# UTeK OMPUTER IN. N 0 = PIEX Not ontrolled = PIEX ontrolled () PEREQ# FJr R0.Ohm % R.Ohm % R.Ohm % R.Ohm % R.Ohm % R.Ohm % R.Ohm % R0.Ohm % R.Ohm % R.Ohm % R.Ohm % R.Ohm % R.Ohm % R.Ohm % R.Ohm % R0.Ohm % R.Ohm % R0.Ohm % R0 0KOhm R0 0KOhm R 0KOhm R 0KOhm Title : Engineer: +V +V LOK EN-I0 Frank Xu,, 00 ate: heet of.0

40 UTeK OMPUTER IN ustom FJr Title : chematic page name Engineer: Frank Xu,, 00 ate: heet of 0.0

41 PWRW# W TP_WITH_P MRTHON# ITP_W# OLOREN# INTERNET# INTNTON# W TP_WITH_P W TP_WITH_P W TP_WITH_P W TP_WITH_P W TP_WITH_P HUT_OWN# +V R 00KOhm 0.UFV FORE_OFF# W TP_WITH_P FORE_OFF#,,,0 ITP_W# OLOREN# INTERNET# MRTHON# INTNTON# PWRW# TPT 0 0.UFV 0.UFV 0.UFV 0.UFV 0.UFV 0.UFV T PWRW# R Ohm +V_E R 00KOhm 0 0.UFV PWR_W# UTeK OMPUTER IN Engineer: Frank Xu ustom FJr Title : Power on & Res Freq,, 00 ate: heet of.0

42 +V +V +.V +V +V R R R R, U_ON R0 00KOhm Q HN00 +V_IHR +V_IHR +.V_IHR +V_IHR Q Q0 Q Q HN00 HN00 HN00 HN00 +V +V +.V +.V +0.V +VRM +VP +V R R R R R R R,, U_ON R 00KOhm Q HN00 +V_IHR +V_IHR +.V_IHR +.V_IHR +0.V_IHR Q Q Q Q Q0 HN00 HN00 HN00 HN00 HN00 +VRM_IHR UTeK OMPUTER IN. N ustom Q HN00 FJr +VP_IHR Title : Engineer: IHRE & EMI P Frank Xu,, 00 ate: heet of Q HN00.0

43 UTeK OMPUTER IN ustom FJr Title : chematic page name Engineer: Frank Xu,, 00 ate: heet of.0

44 XOUT_LN XIN_LN X Mhz R EER0000 U 0.UFV 0.UFV c00 c00.v_tl +V_LN_ +.V_LN.KOhm % PF0V c00 PF0V c00 +.V_LN +V_LN EMI_PRIN_P U EMI_PRIN_P MIP0 MIN0 MIP MIN MIP MIN MIP MIN.V_TL U0 VTRL EEK V_ EEIUX MIP0 V_ MIN0 EEO V_ EE MIP V_ MIN N V_ V_ MIP N 0 0 MIN N V_ V_ MIP V_ MIN IOLTE V_ N V_ N V_ V_ R.KOhm r00 LN_EEK LN_EEI LN_EEO LN_EE R KOhm % R KOhm % U V K I OR O T +V +V_LN 0.UFV c00 RTL JP +.V_LN_E _LN HORT_PIN R0. +VU +V,, L0 PIE_WKE# L 00Mhz 00Mhz +V_LN 0 0UF0V c00.v_tl R.KOhm r00 0.UFV c00.v_tl R.KOhm r00 Pin : ap Pin : ap Pin & : hare ap 0 0.UFV c00 Q Q 0 0.UFV c00 0UF0V c UF0V c UFV c00 PIE_RXN_LN_ PIE_RXP_LN_ 0.UFV c UFV c00 Pin & : hare ap Pin & : hare ap.0v~.v +V_LN_ L0 Typ: 00Mhz 0m +.V_LN 0 0.UFV c UFV c UFV c00 0.UFV c00 0.UFV c00 LK_PIE_LN# LK_PIE_LN PIE_TXN_LN PIE_TXP_LN UF_PLT_RT#,,,,,,, 0.UFV c00 Pin & : hare ap 0.UFV c UFV c00 0.UFV c00.v~.v +.V_LN_E Typ: m L0 PIE_RXN_LN PIE_RXP_LN Pin & : hare ap.v~.v +.V_LN Typ: m Pin & : hare ap Pin & : hare ap 0.UFV Pin & & : hare ap c00 Pin & & : hare ap UTeK OMPUTER IN. N ustom FJr Title : Engineer: LN-RTL Frank Xu,, 00 ate: heet of.0

45 hange to N0M0 M ONN. H H LE_ LE_ Z_OUT_M Z_YN_M Z_IN Z_RT#_M R r00 Ohm ON0 0 0 JP L_JUMP JP L_JUMP R0. +V +VU Z_LK_M +V 0.UFV c00 TO_ON_P PF0V LN ONN. +.V_LN MIP0 MIN0 MIP MIN MIP MIN MIP MIN 0 0.0UFV ON IE IE WTO_ON_P R0. 0.0UFV RJ_TIP_ON R0. 0.0UFV L0 L0 0.0UFV 0 U KOhm00Mhz KOhm00Mhz T+ TT T+ TT T+ TT T+ TT M00 LTRLP0 LTRLM0 LTRLP LTRLP LTRLM LTRLM LTRLP LTRLM RJ_TIP 000PFKV 000PFKV 0 MX+ MT MX- MX- MX+ MT MX- MX+ MT T- T- T- T- MX- MX+ MT ON 0 0 P_ NP_N NP_N P_ MOULR_JK_P L_TRLP0 L_MT0 L_TRLM0 L_TRLP L_MT L_TRLM L_TRLP L_MT L_TRLM L_TRLP L_MT L_TRLM L_TRLP0 L_TRLM0 L_TRLP L_TRLM L_TRLM L_TRLP L_TRLM0 L_TRLP0 L_TRLM L_TRLP L_TRLM L_TRLP L_TRLP L_TRLM L_TRLP L_TRLM 0OHM 0OHM 0OHM 0OHM L0 ommon hoke IEEE L0 ommon hoke IEEE 0OHM 0OHM 0OHM 0OHM RN RN RN RN RN RN RN RN LTRLP0 LTRLM0 LTRLP LTRLM LTRLM LTRLP LTRLM0 LTRLP0 LTRLM LTRLP LTRLM LTRLP LTRLP LTRLM LTRLP LTRLM L_MT0 L_MT L_MT L_MT UTeK OMPUTER IN. N ustom RN Ohm RN Ohm RN Ohm RN Ohm FJr LN_ 0 00PF0V 00PF0V Title : M & RJ+ Engineer: Frank Xu,, 00 ate: heet of.0

46 UTeK OMPUTER IN ustom FJr Title : chematic page name Engineer: Frank Xu,, 00 ate: heet of.0

47 +V +.00V~+.V Max= 0 m 0.UFV 0UF0V +.V +.V~+.V Max= m T_HT T_HLK LK_MINIR_REQ# LK_PIE_MINIR# LK_PIE_MINIR WLN_WKE# ON WKE# T_T T_HLK LKREQ# REFLK- REFLK+.V_.V_ Reserved Reserved Reserved Reserved Reserved 0 0.UFV 0UF0V +VUX_OLN 0.UFV +.00V~+.V Max= 0 m R R +V +VU Reserved R to +VU for Wake on WLN function! PIE_RXN_MINIR PIE_RXP_MINIR PIE_TXN_MINIR PIE_TXP_MINIR H H 0M0_ 0M0_ OM change to 000 Reserved Reserved PERn0 PERp0 PETn0 PETp0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved0 MINI_R_LTH_P W_ILE# PERT#.Vaux.V_ Reserved Reserved 0 Reserved Reserved N LE_WLN# N.V_.V_ NP_N NP_N WLN_ON WLN_LE#, UF_PLT_RT#,,,,,,, M_LK_,0,,, M_T_,0,,, TPT T RF_ON_W#,, PIE_WKE# WLN_ON Q HN00 R +VUX_OLN Q HN00 Q HN00 WLN_WKE# UTeK OMPUTER IN. N ustom WLN_ON# FJr Title : MINIR Engineer: Frank Xu,, 00 ate: heet of.0

48 UTeK OMPUTER IN ustom FJr Title : chematic page name Engineer: Frank Xu,, 00 ate: heet of.0

49 Use EEPROM +V --> _RT# ms < T < 00ms R0. ustom,, 00 UTeK OMPUTER IN. N R-R().0 FJr Frank Xu ate: heet of Title : Engineer: PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI RET# M_EN X_EN _L HWPN# PI_ IEL_ IEL_ X_EN L _RET# M_EN +V +V +V +V +V +V +V RN 0KOhm R 0KOhm 0 0PF0V RN 0KOhm RN 0KOhm 0UF0V 0UF0V 0 0UF0V 0.0UFV R 0KOhm RN 0KOhm 0.0UFV U T0N 0 V WP L UF0V 0.0UFV U R UIO UIO0RIRQ# V_V INT# PME# E0# E# E# E# 0 HWPN# V_PIV_ V_PIV_ V_ROUT PR REQ# NT# ERR# PERR# TOP# EVEL# TRY# IEL IRY# FRME# LKRUN# PIRT# PILK RT# V_ROUT V_M INT# UIO UIO V_RIN TET UIO UIO MEN XEN V_PIV_ V_PIV_ V_PIV_ V_PIV_ V_ROUT V_ROUT V_ROUT 0 0 T R UFV 0.UFV 0.0UFV R 00KOhm 0.0UFV 0 UF0V PI_[:0], INT_ERIRQ,,, PI_E#0, PI_NT#0 PI_REQ#0 PI_E#, PI_E#, PI_E#, PI_PR, PI_FRME#, PI_IRY#, PI_TRY#, PI_EVEL#, PI_TOP#, PI_PERR#, PI_ERR#, PI_RT#, LK_PI, PI_INT#, PI_INT#, _#, PM_LKRUN#,,

50 +V U L 00Mhz V_PHYV_ V_PHYV_ V_PHYV_ V_PHYV_ UFV 0 0.UFV 0 UFV LTP0+ LTP0- LTP0+ LTP0-0 0PF0V XIN_ X.Mhz +-0ppmPF XOUT_ 0PF0V 0 _FILO 0 0.0UFV XI XO FIL0 TPI0 TPN0 TPP0 TPN0 TPP R0 Ohm R Ohm 0 0 TP0- TP0+ TP0- TP0+ 0.0UFV 0.UFV L ommon hoke IEEE LTP0- LTP0+ LTP0- LTP0+ ON IEEE REXT R 0KOhm % _VREF 0.0UFV uard 0 00 REXT VREF.KOhm 0PF0V R R Ohm R Ohm losed to R RN RN RN RN 0OHM 0OHM 0OHM 0OHM losed to onnector o-layout RV R TPT MIO TPT MIO TPT MIO TPT MIO MIO 0 MIO MIO MIO0 TPT MIO0 MIO0 TPT MIO TPT MIO TPT MIO0 MIO0 0 MIO00 MIO0 MIO0 MIO0 TPT T MIO0 MIO0 T T T T M_T M_T M_T M_M MLK M_T M_T T T T0 T M_T0 M_M WP # M# MLK M_PWR M_T0 M_T # M# WP M_PWR RN 0OHM RN 0OHM RN 0OHM RN 0OHM 0OHM 0OHM 0OHM 0OHM 0OHM 0OHM 0OHM 0OHM RN0 RN0 RN0 RN0 RN RN RN RN MT_ MT_ M_M_ MLK_ MT0_ MT_ #_ M#_ WP_ M_PWR_ UTeK OMPUTER IN. N ustom FJr Title : Engineer: R-R() Frank Xu,, 00 ate: heet of 0.0

51 +V RN 0KOhm Q I0_T_E +M_V Q HN00 M_T olve M uo daptor short problem _T Q 0 M_PWR Q HN00 0.UFV 0.UFV R 0KOhm M_T HN00 _T +V RN 0KOhm _ # Q HN00 +V +M_V R_REER_P IN RER ONNETOR PN hange to 0000 M_T M_T ON # +M_V NP_N NP_N _T _T 0 M_T 0 M_M MLK PF0V M_T 0 M_T 0 Write Protect : High active RN 0KOhm 0PF0V M# 0 M_T0 0 0PF0V 0PF0V # 0 WP 0 RN 0KOhm UTeK OMPUTER IN Engineer: Frank Xu ustom FJr Title : in R REER,, 00 ate: heet of.0

52 U_PP U_PN RN0 0OHM RN0 0OHM R0. U_P+ U_P- R. R. o-layout Neward Header,,,,,,,,,, U_ON VU_ON UF_PLT_RT# +VU +VU_PE +V +.V +VU 0.UF0V 0.UF0V PERT#.0V~.V ve= 00m Max= m U TY# O# 0 HN#.VOUT_ PERT#.VOUT_.VIN_.VIN_.VIN_.VIN_ UXIN YRT# R00 +V REFLK_EN.0V~.V +V_PE ve= 000m Max= 00 m PPE# PU# REFLK_EN NEWR_O# +.V_PE +VU_PE +V_PE +.V 0UF0V 0UF0V UXOUT.VOUT_.VOUT_ PPE# PU# RLKEN N 0 0.UF0V 0.UF0V Q HN00 LK_NEWR_REQ#.V~.V +.V_PE ve= 00 m Max= 0 m 0 UF0V 0UF0V 0.UF0V 0.UF0V,, PIE_WKE#!! Expressard tandard.0: hange Pin from REERVE to MLK hange Pin from MLK to MT hange Pin from MT to +.V +VU_PE Q HN00 R,0,,,,0,,, PIE_WKE#_ M_LK_ M_T_ +.V_PE +VU_PE LK_PIE_NEWR# LK_PIE_NEWR PIE_RXN_NEWR PIE_RXP_NEWR PIE_TXN_NEWR PIE_TXP_NEWR +V_PE U_P- U_P+ PU# PIE_WKE#_ PERT# PPE# PF0V PF0V ustom 0 0 ON EXPRE_R_P Neward Ejecter ON UTeK OMPUTER IN. N 0 0 P_ P_ P_ P_ P_ R_EJETOR_P FJr NP_N NP_N Title : NEWR Engineer: Frank Xu,, 00 ate: heet of.0

53 , +V m 0 0UF0V 0.UF0V 0.UF0V c00_h c00 c00 0.0UF0V +.V +V m V_RIN_ 0UF0V 0.UF0V 0.UF0V c00 c00 c00 V_ROUT_ R 0 0.UF0V 0.UF0V c00 c00 R r00 R 00KOhm, PI_[:0] PI_ PI_0 PI_ PI_ V_ROUT_ PI_ PI_ PI_ PI_ 0.UFV 0.UFV PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ Open rain : PI_ PI_ PME#, PI_ ERR#, PI_ INTn# PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0, PI_PR PI_E# PI_E# PI_E# PI_E#0 IEL_, PI_E#[:0] PI_REQ# PI_NT#, PI_FRME#, PI_IRY#, PI_TRY#, PI_EVEL#, PI_TOP#, PI_PERR#, PI_ERR# _RT#, PI_RT# R0 LK_PI,, PM_LKRUN# PI_PME# L.. V_V POWER : PME#, PKROUT, RI_OUT# HWUP#, RT#, IRQn #, #, V#, V# TET, VEN#, VEN# VPPEN0, VPPEN, M IF VPI POWER : PI U V_LOT POWER : R_U, UIO, TH PF0V c00 PF0V c00 L.. U W V_PIV_ R V_PIV_ R V_PIV_ R V_RIN_ E V_RIN_ L V_ROUT_ E V_ROUT_ R REEN# M M 0 N N N N P P R R R T 0 T U U V T V W R T V 0 W R V W T V W T V W 0 V PR P E# W E# W E# T E0# P IEL M REQ# M NT# V FRME# V IRY# W TRY# T EVEL# V TOP# W PERR# T ERR# RT# L PIRT# K PILK L LKRUN# RI_OUT#PME# R-P0Q PI_ IEL_ R 0 r00_h _RT# R 00KOhm r00 0.UFV c00 +V ==> _RT# ms < T < 00ms +V V_V_ V_V_ V_V_ V_V_ V_MV 0 TET HWPN# PKROUT UIO UIO UIO UIO UIO UIO0RIRQ# INT# INT# INT# N F J K J J K E R0 T0 V0 W0 L M F F F H H H H J J K K L R J R J N R K FRME# R L TRY# +V R L EVEL# N R0 M TOP#0 m R N LOK# R N RFU E R N R P 0.UF0V 000PF0V 000PF0V +V +M_V R L LK Ohm c00 c00 c00 R K IRY# 0UF0V r00_h HIEL N R N PERR# c00 R N PR PF0V R K E# L.. c00 N R R R0 U 0 R R E +V R N R P E# m R J R R H 0 E N R H 0.UF0V R c00 R 000PF0V 0UF0V R F c00 c00 R F R0 E 0 T U W T RFU T V T V T V T0 0 T 0 T T W T W W +V T T T T R 0 T RFU R T E 0KOhm T0 0 r00 T TPT E T _HWUP# MIO OE# OE# M T TPT WE# NT#WE# T 0.0UF0V MIO E# 0E# V PKR_ E# E0#E# F T TPT RE# E#RE# R 00KOhm H MIO REET RT#REET r00 T TPT T TPT MIO WIT# ERR#WIT# E PKR PULL OWN : UE ROM MIO WPIOI# LKRUN#IOI# T TPT M MIO RYIREQ# INT#IREQ# 0 MT_ MIO V F UIOPKR_IN#V TPT T 0 MT_ MIO V E THTH#V 0 MT_ E H MIO V# V 0 MT0_ R MIO0 V# V L.. # # _L_ 0 MLK_ MIO0 # T # R r00 INPK# REQ#INPK# TPT T 0 M_M_ R0 MIO0 TPT T HIEL r00 P MIO0 IOR# IOR# P T TPT MIO IOWR# IOWR# INT_ERIRQ,,, MIO0 0 ohm T TPT MIO0 UP V TPT T UM W TPT T 0 M_PWR_ MIO0 +V PI_INT#, 0 WP_ MIO0 r00 PI_INT#, T TPT R 00KOhm +V MIO0 PI_INT# W 0 M#_ MIO0 VPPEN VPP V VPPEN0 VPP0 T R 0 #_ MIO00 VEN# V_EN# RIOH R : R 00KOhm VEN# V_EN# r00 INT #--> RU INT #--> LKRUN#IOI# INT #--> R REER R 00KOhm r00 R-P0Q _HWUP# TW U RT# POWER EQ +V ==> (RT#_HWUP#) ==>PIRT# HW UPEN# POWER EQ : UPEN : _HWUP# LO=> PIRT# LO=> +V OFF REUME : +V ON => PIRT# HI=> _HWUP# HI R R UTeK OMPUTER IN ustom U#,,,0 _#, FJr Title : R Engineer: Frank Xu,, 00 ate: heet of.0

54 Layout: HIEL m PMI # # L L bit OTHER bit losed to onnector o-layout ustom,, 00 UTeK OMPUTER IN PMI OKET.0 FJr Frank Xu ate: heet of Title : Engineer: TPI0 P TP0+_ TP0+ REF_ V_PHY_ TP0-_ X REF_ V_PHY FIL TP0-_ X FIL X_ EVEL# INT#IREQ# PERR# TRY# THTH#V LOK# IRY# ERR#WIT# UIOPKR_IN#V TOP#0 REQ#INPK# LKRUN#IOI# TP0-_ TP0+_ TPI TPI0 TP0-_ TP0+_ X_ +V +V +V +V +VPP +V +V +VPP +V +VPP +V +VPP +V T TPT UFV c00_h 0.UFV c00 0.UFV c00 ON NP_N PTH_ PTH_ NP_N PTH_ PTH_ 0.0UF0V RN 0OHM R.KOhm r00_h L 00Mhz PFV R 0KOhm r00 T TPT T TPT 0.UFV c00 0PF0V U RV00 0 V_EN V_EN EN0 EN FL N N VPPOUT VOUT N VIN VOUT VIN VOUT VIN R 0KOhm r00 0.0UFV c00 R Ohm % T TPT 0 UFV c00_h 000PF0V c00 0 UFV c00_h T TPT UFV c00_h T TPT 0.UFV c00 0.UFV c00 000PF0V c00 R Ohm % X.Mhz U R-P0Q E0 E E V_PHY_ V_PHY_ V_PHY_ V_PHY_ TPI0 TPN0 TPP0 TPN0 TPP0 TPI TPN TPP TPN TPP P XI XO FIL0 REXT VREF N T TPT 0.UFV c00 0.UFV c00 T TPT 0.UFV c00 R Ohm % T0 TPT RN 0OHM 0 PFV U T0N 0 V WP L RN 0OHM T TPT T TPT R0 Ohm % 0.UFV T TPT 0PF0V c00 RN 0OHM 0.UFV c00 0.UFV c00 R 0KOhm T-IRM0FTN00<> r00_h R UFV c00_h ommon hoke L 0.0UF0V T TPT V_EN# VPP VPP0 V_EN# L_ LTP0-0 LTP0+ 0 LTP0-0 LTP0+ 0 E# IOR# 0E# EVEL# LOK# PR TRY# E#RE# 0 THTH#V REQ#INPK# RFU 0 E0#E# RFU FRME# TOP#0 IOWR# LK # 0 PERR# IRY# UIOPKR_IN#V 0 0 E# INT#IREQ# LKRUN#IOI# ERR#WIT# # V RT#REET V 0 0 RFU OE# NT#WE#

55 UTeK OMPUTER IN ustom FJr Title : FJ Engineer: Frank Xu,, 00 ate: heet of.0

56 Z_LK_OE R R.KOhm.KOhm INTMI_P MI_JK L0 L0 Ver :R00 change to 0K ohm % +V T00 _UIO RER_L RER_R R00 0KOhm UFV c00 PFV c00 L0 Ver EPOP# HP_J R0.KOhm LINE_J R00 0.UFV R R0 R0 R 0.UFV R ERPHONE_L ERPHONE_R PIFO 0.UFV _UIO +V_UIO _UIO 0 0PF0V Z_OUT_OE Z_LK_OE Z_IN0 Z_YN_OE, Z_RT#_OE +V_OE P_EEP EPOP# R. R.KOhm U MX HN# IN _UIO _UIO R.KOhm U0 0 L0 Ver EPOP# OUT ET MXTEUK L0-R UFV c00_h N V URR-L(PORT--L) JREF URR-R(PORT--R) V ENTER(PORT--L) LFE(PORT--R) N N N PIFO R R KOhm % FOR L0 Ver R 0KOhm R Ohm 000PF0V c00 R 00KOhm UFV c00 L 000PF0V _UIO +.V _UIO LINE-R(PORT--R) LINE-L(PORT--L) MI-R(PORT--R) MI-L(PORT--L) -R - -L MI-R(PORT-F-R) MI-L(PORT-F-L) LINE-R(PORT-E-R) LINE-L(PORT-E-L) ense 000Mhz Vout=.*(+(00KK)) +V_UIO _UIO 0 UFV c00_h EXTMI_J HP_J 0.UFV _UIO 0 _UIO 0.UFV c00 R 0KOhm R0. R.KOhm 0.UFV c00 R.KOhm UFV INTMI_P INTMI_P UFV UFV 0VXR 00 UFV0VXR 00MI_JK MI_JK UFV 0VXR 00 _R_ UFV 0VXR 00 UFV 0VXR 00 _L_ UF0V INTMI_P UF0V _UIO _UIO +V_UIO +V_UIO _UIO 0.UFV c00 R UF0V R.KOhm 000PF0V.KOhm ERPHONE_R_0 ERPHONE_L_0 INTMI_N For T00 INTMI_N INTMI_P L0 T00 L0 _JK 00Mhz JP JP JP JP JP JP R0. L_JUMP L_JUMP L_JUMP L_JUMP L_JUMP L_JUMP _UIO _PKR PKR_ +V 0.UFV L c00 0.UFV c00 _UIO Engineer: Frank Xu UTeK OMPUTER IN. N ustom R0 KOhm NW VREF_OE _UIO FJr 00Mhz 0UF.V c UFV c00 0.UFV c00 P_EEP R0 KOhm 0.UFV c00 0.UFV c00 +V_OE UFV c00_h Title : OE-L0,, 00 ate: heet of.0

57 To Internal peaker onnector XR XR XR ->- VV 0->NORML EXTERNL MI Microphone In Jack R0. R0. R0. ustom,, 00 UTeK OMPUTER IN. N UIO MP & JK.0 FJr Frank Xu ate: heet of Title : Engineer: ETL# ETL# INTPKL- MP_HN# INTPKL+ LY_OP_E# INTPKR- LY_OP_E# INTPKR- INTPKR+ INTPKL- INTPKL+ INTPKR+ FR ER_POP FL ER_POP FL FR JK_W# JK_W# JK_W# _UIO V_MP _UIO _UIO _UIO +V +V _UIO PV_MP V_MP _UIO +V PV_MP _UIO V_MP V_MP +V _UIO _UIO _UIO _JK V_MP _JK _JK _JK _JK _UIO _JK _UIO _JK _UIO V_MP V_MP +V V_PIF V_PIF _UIO _JK _JK V Vin M J PHONE_JK_P 0 L L 00Mhz R 00KOhm 000PF0V 0 00PF0V R Ohm L 00Mhz L Q HN00 KOhm 0 UFV c00 Q HN00 000PF0V 0 0.UFV Q HN00 R MOhm r00_h E 0UFV R0 00KOhm r00 R 0KOhm r00 L 00Mhz Q HN UFV 00PF0V E 00UF.V 0 0.0UFV c00 R L UIO JK J PHONE_JK_P 0 UF0V E0 00UF.V ON WTO_ON_P IE IE L 00Mhz T Q HN00 E Q PM0 0 0.UFV 0.UFV L 00Mhz 0.0UFV c00 L 00Mhz R.KOhm Q HN00 00PF0V L 0.UFV c00 R- K R- K E Q PTEK 0 UFV c UFV 0.UFV c00 TW U TP0PWPR 0 0 IN0 IN LOUT+ LLINEIN LHPIN PV RIN LOUT- LIN YP RLINEIN HUTOWN# ROUT+ RHPIN V PV HPLINE# ROUT- ETL# P-EEP L0 00Mhz R0 0KOhm E 0UFV R 0KOhm r00 R 0 0.UFV R0 0KOhm r00 L 00Mhz 000PF0V R 0KOhm R Ohm 000PF0V UFV Q HN00 Q HN00 R L0 R 0KOhm r00 E Q0 PM0 Q HN00 R 0KOhm RER_L IN_MP# RER_R Z_RT#_OE, ERPHONE_L ERPHONE_R EXTMI_J MI_JK EPOP# OP_# PIFO HP_J ERPHONE_R_0 ERPHONE_L_0

58 +V U_ON_E U OE# V Y U_ON,, LVV 0.UFV UTeK OMPUTER IN ustom FJr Title : ON & ON Engineer: Frank Xu,, 00 ate: heet of.0

59 +V_E +V UF0V PF0V X.Khz XIN_E XOUT_E 0.UFV,0, LP_0,0, LP_,0, LP_,0, LP_ LK_EPI,0, LP_FRME#,,,,,,, UF_PLT_RT#,,, INT_ERIRQ EXTMI# FR# FWR# F# F0 F F F F F F F F0 F F R0 F R F PPEN F HM F F F F F0 F F F F F F F F KI0 KI KI KI KI KI KI KI KO0 KO KO KO KO KO KO KO KO KO KO0 KO KO KO KO KO 0PF0V 0KOhm 0KOhm 0KOhm 0KOhm 0.UFV EXT_I# 0TE R_IN# E_RT# T T XIN_E XOUT_E RN RN RN RN TPT TPT PF0V +V_E JP U IT0TE HORT_PIN R0. +V_E L0 L L L LPLK LFRME# LPRT#WUIP ERIRQ EMI# EI#P 0P KRT#P WRT# PWUREQ# FR# FWR# F# F0 F F F F F F F F0 F FR0 FR FPPEN FHM F F F F F0 F F F F F FP0 FP FP FP KI0T# KIF# KIINIT# KILIN# KI KI KI KI KO0P0 KOP KOP KOP KOP KOP KOP KOP KOK# KOUY KO0PE KOERR# KOLT KO KO KO KK KKE PLK0PF0 PT0PF PLKPF PTPF +VPLL +VPLL +V 0.UFV +V +V 0.UFV JP +V_E MLK0P MT0P MLKP MTP 0 0 PWM0P0 PWMP PWMP PWMP PWMP PWMP PWMP PWMP RXP0 TXP P RIN#PWRFIL#LPRT#P LKOUTP0 P TMRI0WUIP P TMRIWUIP KKOUTP RI#WUI0P0 RI#WUIP P INTP TH0P THP PE0 PE PE PE PWRWPE WUIPE LPP#WUIPE LKRUN#WUIPE PLKPF PTPF PLKPF PTPF F0P FP LP0HLP LP0LLP PH0 PH PH PH PH PH PH PH PI0 PI PI PI PI PI PI HORT_PIN R0. E_ UF0V JP HORT_PIN R0. TPT TPT T TPT IN_MP#_K THRM_PU# TPT PMTHERM# _PR_U# VU_# PUPWR_# TPT T T T +V T0 0.UFV NUM_LE P_LE RL_LE THRO_PU _0 PM_RMRT# M0_LK M0_T M_LK M_T T KI0 0 KI 0 FN_PWM L_KOFF# U#,,,0 U# RF_ON_W#, TP_LK 0 TP_T 0,,,0 L_ TEL_P# H_LE_UP# PWR_LE_UP# IN_O#, OP_# T_IN_O# E_IE_RT# FN0_TH OLOREN# INTERNET# MRTHON# ITP_W# T_ON# INTNTON# VU_ON, PM_PWRTN# U_ON, U_ON_E PM_RMRT# IH_PWROK H_EN# PREH T_LL# T_LERN O#_O FORE_OFF# attery Thermal ensor for Keyboard I R. +V_E V 0 R 0KOhm R T r00 EXT_I# THRM_PU# PU_VRON 0 R_IN# t=0. * 0^ * (sec) =. ms IN_MP#_K 0TE PWR_W# LI_E# M_T M_LK M0_T M0_LK _PR_U# INTNTON# PUPWR_# VU_# LI_E# THRM_PU# T_IN_O# IN_O# +V +V UMKN PMTHERM# +V.UF.V Q R0 0KOhm +V Q Q UMKN +V HN00 U RTOUT N Q UMKN RNV 0 T VV.KOhm.KOhm.KOhm.KOhm 0KOhm 0KOhm 0KOhm 0KOhm Q HN00 E_RT# 0KOhm 0KOhm 0KOhm 0KOhm RN RN RN RN RN RN RN RN K_I# +V_E +V_E +V_E +V_E RN RN RN RN THRM_LERT# R 0 0.UFV PM_THERM# 0TE_IH R_IN#_IH IN_MP# UTeK OMPUTER IN. N ustom +V R_IN#_IH 0KOhm 0TE_IH0KOhm TP_LK TP_T KI KI0 U# U# U_ON_E U_ON ITP_W# MRTHON# INTERNET# OLOREN# _PR_U# VU_# PUPWR_# FJr JP MM_OPEN_MIL 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm.KOHM.KOHM.KOHM.KOHM Q UMKN Q UMKN R R0 R R RN0 RN0 RN0 RN0 RN RN RN RN +V_E +V +V +V_E Title : E-IT0E Engineer: Frank Xu,, 00 ate: heet of Q UMKN R R _PR_U V_V_PWR,0 VRM_PWR,0,0.0

60 For Touch-Pad For Keyboard +V +V_TP L 00Mhz 0.UFV LFET W TP_T TP_LK LFET RIHT +V_TP ON IE 0 0 IE FP_ON_P W RIHT ON0 IE 0 0 IE KO KO KO KO0 KO KO KO KO KO KO KO KI0 KI KO KI KI KO KI KI KO KI KI KO0 KO KI KI0 KO KO KO KO0 KO KO KO KO KO KO KO KI0 KI KO KI KI KO KI KI KO KI KI KO0 KO TP_WITH_P FP_ON_P TP_WITH_P UTeK OMPUTER IN. N ustom FJr Title : Touch Pad & K Engineer: Frank Xu,, 00 ate: heet of 0.0

61 UTeK OMPUTER IN ustom FJr Title : chematic page name Engineer: Frank Xu,, 00 ate: heet of.0

62 +V +V_U_ON F.V R0.KOhm L 00Mhz U_PP U_PN RN 0OHM RN 0OHM R0. U_P+ U_P- +V_U_ON 0 U_ON_O# R0.KOhm +V_U_ON +V_U_ON IP0Z E UF.V + 0.UFV U_P+ U_P- U_P+ U_P- ON 0P+ 0P- V P+ U_ON_XP P- V F.V L 00Mhz U_PN U_PP RN 0OHM RN 0OHM R0. U_P- U_P+ R0 U_ON_O0#.KOhm + E UF.V 0.UFV R0.KOhm U_PP0 U_PN0 U_PN U_PP RN 0OHM RN 0OHM R0. +V_U_ON RN 0OHM RN 0OHM R0. IP0Z U_P0+ U_P0- U_P- U_P+ +V_U_ON R0. + E 00UF0V + E UF.V 0.UFV 0 0.UFV U_P0- U_P0+ U_P- U_P+ ON IE_ V T0+ IE_ IE_ IE_ U_ON_XP ON IE_ V IE_ T0- T0- T0+ IE_ IE_ U_ON_XP UTeK OMPUTER IN ustom FJr Title : U ONN Engineer: Frank Xu,, 00 ate: heet of.0

63 UTeK OMPUTER IN ustom FJr Title : chematic page name Engineer: Frank Xu,, 00 ate: heet of.0

64 I ROM E Hardware trapping +V_E F R0 & F R 00: PNPN ccess Register Pair re 00Eh and 00Fh 0: PNPN ccess Register Pair re 00Eh and 00Fh 0: PNPN ccess Register Pair re etermined by E omain Registers WLR and WHR. : Reserved +V_E F R0 R0 R 0KOhm 0KOhm F R R R 0KOhm 0KOhm Note: ampled at VTY Power Up Reset F PPEN 0: Normal : K Interface Pins re witched to Parallel Port Interface for In-ystem Programming +V_E F HM F PPEN 0: isable hared Memory with Host IO : Enable hared Memory with Host IO R 0KOhm R 0KOhm F HM R 0KOhm R 0KOhm +V_E F F F F F F F F F HM F F PPEN F F R F F R0 0 OE# FR# F 0 F0 F0 0 E# F# F0 Q0 Q F F F U TVF00 UTeK OMPUTER IN. N ustom 0.UFV FJr FWR# F F F F F Title : Engineer: I ROM Frank Xu,, 00 ate: heet of.0

65 UTeK OMPUTER IN ustom FJr Title : chematic page name Engineer: Frank Xu,, 00 ate: heet of.0

66 For LE For POWER LE +VU LE R + PWR_LE# REEN +VU For TTERY LE +VLM LE R + ORNE H_LE# H_LE# for ap. Lock +V LE R + REEN P_LE# P_LE# for Num Lock +V LE R + NUM_LE# REEN NUM_LE# PWR_LE_UP# RN.KOHM PWR_LE# Q HN00 Q HN00 +VU H_LE_UP#.KOHM RN Q HN00 Q HN00 P_LE Q0 HN00 NUM_LE Q HN00 For TIE LE For WireLess LE for croll Lock T_LE# IE_LE# +V +V R +V.KOHM.KOHM TW LE + REEN RN RN H_LE# Q HN00 H_LE# Q HN00 +V WLN_LE_EN For T LE +V R0.KOHM.KOHM R TLE_ON LE + REEN RN RN LE + REEN.KOHM.KOHM WLNLE_EN# RN WLNLE_EN# T_LEON# RN Q HN00 T_LEON# Q HN00 +V for Touch Pad +V TP_LEON R R0 LE + REEN Q HN00 LE + REEN RL_LE# RL_LE# Q HN00 UTeK OMPUTER IN ustom TP_LEON# TP_LEON# RL_LE FJr Title : LE Engineer: Frank Xu,, 00 ate: heet of.0

67 UTeK OMPUTER IN ustom FJr Title : chematic page name Engineer: Frank Xu,, 00 ate: heet of.0

68 IN J P_ P_ NP_N _PWR_JK_P _JK_IN TPT T TPT T TPT T TPT T L 00Mhz 0.UFV TPT T TPT T TPT T TPT T UFV _OK_IN UFV 0.UFV _OK_IN daptor V,.0, R 0KOhm W % R KOhm R.KOhm % 0.UF0V V +V _ T T IN J P_ 0 P_ TT_ON_P T_ON TPT TPT TPT TPT TPT TPT TPT TPT 0.UFV T0 T0 T0 T0 T00 T0 T0 T0 TPT 0 00PF0V T TPT 00PF0V T TPT L L L 0.UFV T 00Mhz 00Mhz 00Mhz K K M0_LK M0_T T#,,0 R KOhm R.KOhm Without attery & Pull out dapter R KOhm 000PF0V U N V U VOUT PT0NR UFV _T_Y R0 00KOhm R 0KOhm V V When _T_Y<V ctive EN +V T_ FORE_OFF#,,,0 UTeK OMPUTER IN. N ustom FJr Title : Engineer: & T IN Frank Xu,, 00 ate: heet of.0

69 UTeK OMPUTER IN ustom FJr Title : chematic page name Engineer: Frank Xu,, 00 ate: heet of.0

70 For ebug +V ON,, LP_0,, LP_,, LP_,, LP_,, LP_FRME# LK_PI IE 0 0 IE 0PF0V FP_ON_P ottom ontact LP_FRME# LP_0 LP_ LP_ LP_ R 0 RN 0 RN 0 RN 0 RN 0 UTeK OMPUTER IN ustom FJr Title : ebug ONN. Engineer: Frank Xu,, 00 ate: heet of 0.0

71 UTeK OMPUTER IN ustom FJr Title : chematic page name Engineer: Frank Xu,, 00 ate: heet of.0

72 Normal type High: lave Low : Master T H O H_EL : Pull-own, H as Master ustom,, 00 UTeK OMPUTER IN. N T-H & O.0 FJr Frank Xu ate: heet of Title : Engineer: IE_PP# IE_I H_EL _EL IE_P0 IE_P IE_PIORY IE_PIOW# IE_P IE_P IE_P IE_P IE_P IE_PP# IE_PIOR# IE_PREQ _EL IERT# IE_I IE_P IE_P IE_P INT_IRQ IE_P IE_P IE_P IE_P IE_P0 IE_P IE_P0 IE_PK# IE_P# IE_P IE_P IE_P IE_P IE_P IE_P IE_P0 IE_P IE_P IE_P IE_P IE_P INT_IRQ IE_P IE_P IE_P IE_P IE_P IE_I IE_PIORY IE_P IE_P IE_PP# IE_P IE_P IE_P# IE_PIOR# IE_P IERT# IE_P IE_P IE_P IE_P# IERT# H_EL IE_PREQ IE_P IE_P IE_P IE_P0 IE_P IE_PIOW# IE_P IE_P0 IE_P IE_P0 IE_P0 IE_P IE_PK# +V +V +V +V +V +V +V +V +V +V +V +V 0UF0V 0.UFV ON H_ON_XP REET# KEY MRQ IOW# IOR# IORY EL MK# INTRQ IO# PI# 0 #0 # P# +V_L +V_M RV R0 + E UF.V ON T_ON_P NP_N NP_N NP_N NP_N Q UMKN R 0KOhm r00 0UF0V c00 R.KOhm R 0KOhm R R 0KOhm ON to_on_0p PF0V 0.UFV TW 000PF0V R R T0 TPT R 0KOhm r00 Q UMKN 0 0.UFV c00 R 0KOhm r00 _R_ IE_P[:0] IE_LE# IE_P IE_PIOR# IE_PK# IE_P# IE_PREQ E_IE_RT# UF_PLT_RT#,,,,,,, IE_P _L_ IE_PIOW# IE_P# IE_P0 IE_PIORY INT_IRQ T_RXN0 T_RXP0 T_TXN0 T_TXP0

73 UTeK OMPUTER IN ustom FJr Title : chematic page name Engineer: Frank Xu,, 00 ate: heet of.0

74 FOR V FOR PU FOR REW HOLE FOR LEFT UNER FOR RIHT UP FOR FN ustom,, 00 UTeK OMPUTER IN REW HOLE.0 FJr Frank Xu ate: heet of Title : Engineer: H T H N_N NP_N NP_N H TRXN NP_N H0 TN NP_N H N H N NP_N H N NP_N H T H I H N H T H NN NP_N NP_N H N NP_N H N NP_N H0 I H N NP_N H T H N NP_N H N NP_N H N NP_N H N NP_N H N NP_N H I

F7F CPU CLOCK GEN ICS NORTH DDR2 SO-DIMM0 BRIDGE DDR2 SO-DIMM1 SOUTH BRIDGE TPM 1.2 INFINEON SLB9635 AZALIA CODEC EC ITE IT8510E MDC NEWCARD

F7F CPU CLOCK GEN ICS NORTH DDR2 SO-DIMM0 BRIDGE DDR2 SO-DIMM1 SOUTH BRIDGE TPM 1.2 INFINEON SLB9635 AZALIA CODEC EC ITE IT8510E MDC NEWCARD 0_lock iagram 0_ystem etting 0_PU-YONH(HOT) 0_PU-YONH(PWR) 0_N-M(HOT) 0_N-M(MI & F) 0_N-M(RPHI) 0_N-M(R) _N-M(PWR) _N-M(PWR) _N-M() _-IHM() _-IHM() _-IHM() _-IHM(PWR) 0_R O-IMM0 _R O-IMM _R TERMINTION

More information

CPU MEROM 34W NORTH BRIDGE. Nvdia NB8 CRESTLINE PAGE 24,25,26,27,28,29,30,31. Debug Conn. PAGE 70 SOUTH BRIDGE ICH8M TPM 1.2 INFINEON SLB9635 PAGE 76

CPU MEROM 34W NORTH BRIDGE. Nvdia NB8 CRESTLINE PAGE 24,25,26,27,28,29,30,31. Debug Conn. PAGE 70 SOUTH BRIDGE ICH8M TPM 1.2 INFINEON SLB9635 PAGE 76 0 lock iagram * 0 0 0 0 ystem etting * 0_PU-Merom(HOT) 0_PU-Merom(PWR) U ONN * I ROM * Fv/c 0 * 0 0_RETLINE(HOT) 0 0_RETLINE(MI & F) 0 0_RETLINE(RPHI) 0 0_RETLINE(R) 0 _RETLINE(PWR) _RETLINE(PWR) _RETLINE()

More information

T53S Main BD. R1.2 Block Diagram

T53S Main BD. R1.2 Block Diagram T Main. R. lock iagram LV PE Merom PU LV / ULV PE, F F 00/ MHz LOK EN. ILPRLF-T PE FN Thermal sensor PE 0 RT HMI PE PE M Nvidia NP- M PE 0,,,,,, PE udio L PE,, 0 F PI-E X zalia LP restline PM PE 0,,,,,

More information

F8V L80V N80V N81 Montevina Block Diagram

F8V L80V N80V N81 Montevina Block Diagram FV L0V N0V N Montevina lock iagram _IN & T ON PE 0 Penryn W & LE PE HMI RT PE PE LV & INV PE INTERNL KEYOR TOUH P PE IR IO PI ROM MI IN HP&PIF OUT OPMP PE Internal MI ON PE PE PE 0 V aughter PE FVa: M

More information

W7J: YONAH/CALISTOGA-PM/G72M BLOCK DIAGRAM

W7J: YONAH/CALISTOGA-PM/G72M BLOCK DIAGRAM WJ: YONH/LITO-PM/M LOK IRM PE LOK EN. I0 PE 0 MI PREMP & INT MI PE 0, PE PE PE R VRM* F TV OUT ZLI M PE LV RT ZLI L0 UIO_MP & INT PK PE PE PE nvii M PE,,,0,, PIF JK zalia PIE LP T PE,, PE,,,,0,, Yonah

More information

E chematic Index Page ystem page Ref. 0 lock iagram 0 chematic Information 0-0 PU-Penryn 0-09 R II O-IMM 0- antiga 0- IH9M PI ROM 9 LK-I9LPRLF-T 0- E_

E chematic Index Page ystem page Ref. 0 lock iagram 0 chematic Information 0-0 PU-Penryn 0-09 R II O-IMM 0- antiga 0- IH9M PI ROM 9 LK-I9LPRLF-T 0- E_ : PENRYN/NTI/IH9-M/N9M- LOK IRM mall-oard ub-oard R VRM*(MX) RT MI PREMP & INT MI LZI M UIO OR L0 PE mall-oard LV HMI TouchPad PE IO PI ROM PE INTERNL KEYOR PE PE PE PE UIO_MP & INT PK PE PE PE PE nvii

More information

A8Jp/Jv/Je/Jn/Fm SCHEMATIC

A8Jp/Jv/Je/Jn/Fm SCHEMATIC Jp/Jv/Je/Jn/Fm HMTI P 0 0 0 0 ontent YTM P RF. Merom PU () Merom PU () PU P/THRML NOR LOK N. alistoga--pu alistoga--pi alistoga--r alistoga--powr alistoga--n alistoga--trap R O-IMM_0 R O-IMM_ R R TRMINTION

More information

F80Q SCHEMATIC Revision 2.00

F80Q SCHEMATIC Revision 2.00 F0Q HMTI Revision.00 P 0 0 0 0 ontent YTM P RF. PU-Penryn() PU-Penryn() PU P, Thermal enor LOK N._ILPRLF N_-0L ()--PU N_-0L ()--R/P N_-0L ()--R bus N_-0L ()--POWR N_-0L ()--POWR N_-0L ()--/trapping R O-IMM_0

More information

CPU T2060 4xx,5xx Series PAGE 2,3. FSB 533MHz. GMCH-M Calistoga 943GML B0:02G PAGE 6,7,8,9,10,11 DMI Interface PCIE *1 ICH7-M PCIE *1

CPU T2060 4xx,5xx Series PAGE 2,3. FSB 533MHz. GMCH-M Calistoga 943GML B0:02G PAGE 6,7,8,9,10,11 DMI Interface PCIE *1 ICH7-M PCIE *1 TERE lock iagram PE FN ENR M0RMZ PE, PU T00 xx,xx eries PE PE LK EN 0 HRER RUT F MHz Power n equence PE 0 TP PE PE LV & NV RT MH-M alistoga ML 0:00000 PE,,,,0, M nterface R-MHz ual hannel R PE,, -MM X

More information

4 4 IDT CV125PA G S 533/667MHz TPS PCI Express x16 ATI. 3D3V_S0 2D5V_S0 VRAM x4 11,12. 1D8V_S3 1D5V_S0 Codec. CARDBUS CardReader

4 4 IDT CV125PA G S 533/667MHz TPS PCI Express x16 ATI. 3D3V_S0 2D5V_S0 VRAM x4 11,12. 1D8V_S3 1D5V_S0 Codec. CARDBUS CardReader YTM / TP0 LW- lock iagram LK N. IT VP Yonah P TKUP YTM /.//. TP, TOP INPUT OUTPUT TVO 0V_0 HOT U 00//MHz TOUT LV "WX+ V_ R /MHz L TP00 0 MHz alistoga, PI xpress x V_ R_VRF_0 TI RT V M Ver.: MP / MP R Ver.:

More information

Z62Ha CPU. Card Reader TPM 1.2 GIGA LAN NEWCARD DDR2 SO-DIMM1 DDR2 SO-DIMM2 AZALIA CODEC CLOCK GEN MDC CONN. DDR2 32MX16M X4. Touch Pad.

Z62Ha CPU. Card Reader TPM 1.2 GIGA LAN NEWCARD DDR2 SO-DIMM1 DDR2 SO-DIMM2 AZALIA CODEC CLOCK GEN MDC CONN. DDR2 32MX16M X4. Touch Pad. lock iagram R MXM X L RT Internal K Touch Pad ynaptics TI PU M- ebug onnector TPM. INFINEON L PU MEROM ocket-p NORTH RIE I OUTH RIE R single hannel- R single hannel- MUTIOL MHz ITP ONN. LOK EN I LPR00

More information

Project Name :I36IAx Platform : Celeron GS40 + Park + ICH9M

Project Name :I36IAx Platform : Celeron GS40 + Park + ICH9M Project Name :IIx Platform : eleron + 0 + Park + IHM PE..... PU... 0_FF. 0...... -IHM.... 0.......... 0....... POWER... 0. ONTENT INEX YTEM LOK IRM POWER IRM & EQUENE Power on equence iagram PU Penryn

More information

Z96S CPU MEROM 34W P.3~5. DDR2 16Mx16 x4 CLOCK GEN ICS 9LPR364BGLF-T P.25. DDR2 16Mx16 x4 NORTH. nvidia DDR2 SO-DIMM0 BRIDGE

Z96S CPU MEROM 34W P.3~5. DDR2 16Mx16 x4 CLOCK GEN ICS 9LPR364BGLF-T P.25. DDR2 16Mx16 x4 NORTH. nvidia DDR2 SO-DIMM0 BRIDGE 0_lock iagram 0_ystem etting 0_Merom PU () 0_Merom PU () 0_PU P. 0_PM--PU () 0_PM--R/PE () 0_PM--R U () 0_PM--PWER () 0_PM--PWER () _PM--/TRPPIN () _IHM() _IHM() _IHM() _IHM--PEW/ () _R -IMM0 _R -IMM _R

More information

4 4 RTM865T B0W 3 Max , 5 G TV Out CRT LCD. 3D3V_S0 2D5V_S0(130 ma) 11,12. Line In 1D8V_S3 1D5V_S0(5A) Codec

4 4 RTM865T B0W 3 Max , 5 G TV Out CRT LCD. 3D3V_S0 2D5V_S0(130 ma) 11,12. Line In 1D8V_S3 1D5V_S0(5A) Codec YTM / MX lock iagram RTMT-.00.0W P TKUP YTM / Max.00.00, TV Out TOP INPUT OUTPUT R LK N. / MHz, R / MHz /MHz Mobile PU Yonah eleron M HOT U 00//MHz@.0V alistoga TL+ PU I/F R Memory I/F INTRT RHPI Project

More information

G792 C/Y LVDS. 0 Ohm resistor (Y40) RGB CRT S 6,7,8,9,10. RGB switch. To Port Replicator (Y41) ENE. CardReader LAN 88E8055. Mini Card 802.

G792 C/Y LVDS. 0 Ohm resistor (Y40) RGB CRT S 6,7,8,9,10. RGB switch. To Port Replicator (Y41) ENE. CardReader LAN 88E8055. Mini Card 802. Y lock iagram INPUT OUTPUT R LK N. IT V / MHz, R / MHz INT.PKR RJ MOM M ard H 0 ROM 0 Mobile PU Yonah eleron M, T PT HOT U 00//MHz alistoga,,, MINI U TXFM Phone lue-tooth OM LPT U x port U P RT PORT PORT

More information

L53II0 M/B and Daughter P/N LIST:

L53II0 M/B and Daughter P/N LIST: Model : LII0 P P/N:L00- P P/N:L00- Intel Merom PU + M + IH-M hipset LII0 M/ and aughter P/N LIT: LII0 M/ ffiliated FF/able P/N LIT: P0 INEX P0 YTEM LOK IRM P0 POWER IRM & EQUENE P0 PIO & POWER ONUMPTION

More information

CPU Yonah Single core Yonah Celeron Page 2. AGTL+ 133/166MHz DDR2 533/667 RC415ME. Page 5,6,7,8,9 PCIE X4 SB600. LPC 33MHz. Debug Conn.

CPU Yonah Single core Yonah Celeron Page 2. AGTL+ 133/166MHz DDR2 533/667 RC415ME. Page 5,6,7,8,9 PCIE X4 SB600. LPC 33MHz. Debug Conn. FR LOK IRM PU Yonah ingle core Yonah eleron Page TL+ MHz LV Page 0 RT Page PIE RME R ingle hannel UL R O-IMM Page,, Page,,,, PIE X MINIR Page 00 LN 000 TTNI L LP MHz ebug onn. Page NEWR Page Page,,,, H

More information

Model : M30EI0. Mobile Dothan with INTEL 915GM / ICH6-M Chipset

Model : M30EI0. Mobile Dothan with INTEL 915GM / ICH6-M Chipset Revision History / ORIINL RELEE Model : MEI Mobile othan with INTEL M / IH-M hipset P INEX P YTEM LOK IRM P POWER IRM & EQUENE P PIO & POWER ONUMPTION P PU anias/othan-/ P PU anias/othan-/ P LOK EN I P

More information

TV Out CRT LCD 13. Nvidia G72M-V 46 ~ 48, 51 ~ 55 PWR SW CP TI PCI ~ 25. Mini-PCI 30 LAN TXFM RJ45 RTL8111B DEBUG CONN 34

TV Out CRT LCD 13. Nvidia G72M-V 46 ~ 48, 51 ~ 55 PWR SW CP TI PCI ~ 25. Mini-PCI 30 LAN TXFM RJ45 RTL8111B DEBUG CONN 34 MYLL lock iagram a. Line In b. Mic In c. INT Mic d. Line Out e. INT.PKR R II O-IMM R II O-IMM P Layer tackup L: ignal L: V L: ignal L: ignal L: N L: ignal ~ LK N. IT V odec L OP MOM M ard ~ RM U / MHz

More information

CPU. Diamondville FCBGA437. FSB533/400MHz NORTH LVDS BRIDGE 945GSE RGB. x2 DMI SOUTH BRIDGE LPC ICH7-M. Touch Pad PCIE USB USB_P1/2/3 USB_P4 USB_P7

CPU. Diamondville FCBGA437. FSB533/400MHz NORTH LVDS BRIDGE 945GSE RGB. x2 DMI SOUTH BRIDGE LPC ICH7-M. Touch Pad PCIE USB USB_P1/2/3 USB_P4 USB_P7 0_lock iagram 0_ystem etting 0_Power equence 0_lock en_ilpr 0_iamondville_U 0_iamondville_PWR 0_N-M(HT) 0_N-M(MI) 0_N-M(RPHI) 0_N-M(R) _N-M(PWR) _N-M(PWR) _N-M() _-IHM(PWR) _-IHM() _-IHM() _-IHM() _R IMM

More information

C90S C90S CLOCK GEN ICS9LPR363AGLF-T P.03 CPU THERMAL CONTROL. MXM Interface NORTH DDR2 SO-DIMM0 BRIDGE DDR2 SO-DIMM1 SOUTH BRIDGE EC ITE IT8511EP.

C90S C90S CLOCK GEN ICS9LPR363AGLF-T P.03 CPU THERMAL CONTROL. MXM Interface NORTH DDR2 SO-DIMM0 BRIDGE DDR2 SO-DIMM1 SOUTH BRIDGE EC ITE IT8511EP. 0 00_00_000 LOK iagram HITORY Power equence LKEN-ILPRLF-T N-_ N-_ N-_ N-_ N-_ 0 L- L- L- L- RII_-IMMs RII_-Termination MXM Interface MXM Power & N NIO_-LV & Inverter NIO_-RT 0 NIO_-VIEO NIO_-HMI onnector

More information

X51C Main BD. R1.0 BLOCK DIAGRAM

X51C Main BD. R1.0 BLOCK DIAGRAM X Main. R.0 LOK IRM Merom PU LOK EN. ILPRLF-T PE ufp FN + Thermal sensor PE, PE 0 PE LV i0elv F 00 MHz PE TV PE RT im TE R MHz R-II O-IMM X PE,, PE PE 0,,,,,, MI * PIE * Miniard WLN onn. PE New ard onn

More information

R&D Division. Board name : Mother Board Schematic Project : Z11D (Santa Rosa) Version : 0.4 Initial Date : March 02, Inventec Corporation

R&D Division. Board name : Mother Board Schematic Project : Z11D (Santa Rosa) Version : 0.4 Initial Date : March 02, Inventec Corporation Inventec orporation R& ivision oard name : Mother oard chematic Project : Z (anta Rosa) Version : 0. Initial ate : March 0, 00 Inventec orporation F, No., ection, Zhongyang outh Road eitou istrict, Taipei

More information

P901 CPU CLOCK GEN ICS9LPR G NORTH SODIMM 200P BRIDGE. AZALIA CODEC Realtek ALC269 SOUTH BRIDGE MDC MINICARD. Card Reader Alcor AU6336

P901 CPU CLOCK GEN ICS9LPR G NORTH SODIMM 200P BRIDGE. AZALIA CODEC Realtek ALC269 SOUTH BRIDGE MDC MINICARD. Card Reader Alcor AU6336 0_lock iagram 0_ystem etting 0_Power equence 0_lock en_ilpr 0_iamondville_U 0_iamondville_PWR 0_N-M(HT) 0_N-M(MI) 0_N-M(RPHI) 0_N-M(R) _N-M(PWR) _N-M(PWR) _N-M() _-IHM(PWR) _-IHM() _-IHM() _-IHM() _R IMM

More information

立成网. 视频教程 LICHENGNB.COM

立成网. 视频教程 LICHENGNB.COM 本图纸版权属原厂家所有 仅在服务该产品使用者时使用 YTM / TP0 Project code: 9.Q0.00 INPUT OUTPUT LW- lock iagram LK N. IT VP Yonah P TKUP YTM /.//. TP, TOP INPUT OUTPUT TVO 0V_0 HOT U 00//MHz TOUT LV "WX+ V_ R /MHz L TP00 0 MHz

More information

C45/C46 Block Diagram

C45/C46 Block Diagram / lock iagram LK EN I LPR.00.00W Mobile PU Merom /., Project code:.u0.00 Project code:.v00.00 P Number : 0 Revision : - YTEM / TP0 INPUT TOUT OUTPUT V_() V_() YTEM / INPUT TOUT OUTPUT 0V_0(.) V_(.) R /

More information

Z62H CPU CLOCK GEN NORTH BRIDGE DDR2 SO-DIMM0 DDR2 SO-DIMM1 TPM 1.2 INFINEON SLB9635 SOUTH BRIDGE EC ENE3925 AZALIA CODEC.

Z62H CPU CLOCK GEN NORTH BRIDGE DDR2 SO-DIMM0 DDR2 SO-DIMM1 TPM 1.2 INFINEON SLB9635 SOUTH BRIDGE EC ENE3925 AZALIA CODEC. PU MERM ocket-p ITP NN. LK EN ZH L Internal K Touch Pad ynaptics E PI FLH LV i 0 ELV RT ebug onnector TPM. INFINEN L E ENE I - PI FLH HV us Vus R LP PI i F MHz/MHz NRTH RIE UTH RIE i MUTIL MHz R ingle

More information

Yonah/RC410MD/IXP450 BLOCK DIAGRAM

Yonah/RC410MD/IXP450 BLOCK DIAGRAM YonahR0MIXP0 LOK IRM, Yonah M ufp LOK EN. I Thermal ensor (MX) LV & INV. on 0 HOT U TL.0V,00MHZ IN Jack, FN on RT on R0M,,, -link UL R O-IMM, POWER ON KTs, U X U.0 IE U 0 PI_U RU RIOH R 0 RU LOT V, V VPP,

More information

2007/7/15. DDR2 x 1. DDR2 x 1 SATA1. 4 x SATA150,300 ports SATA2 SATA3 SATA4 IDE X1. USB2.0 8 ports WIFI. BIOS Flash ROM (SPI)

2007/7/15. DDR2 x 1. DDR2 x 1 SATA1. 4 x SATA150,300 ports SATA2 SATA3 SATA4 IDE X1. USB2.0 8 ports WIFI. BIOS Flash ROM (SPI) PI-EX x lot ch udio PI-EX x lot LN THERO RELTEK L PI lot PI lot V PKPL-VM/I PI-EX x PI-EX x PI-EX x zalia V PI U MHz Intel L Pentium (90/nm).Hz PU Intel MH earlake (North ridge) F 00/0/MHz MI U Intel IH

More information

Extreme/Meron 2M/4M SV FSB:667 or 800 MHz 4~7. Host BUS 667/800MHz. PCIe x16 8~14. DMI I/F 100MHz. USB 2.0 USB x 427 SATA PATA PCI/PCI BRIDGE 22~25

Extreme/Meron 2M/4M SV FSB:667 or 800 MHz 4~7. Host BUS 667/800MHz. PCIe x16 8~14. DMI I/F 100MHz. USB 2.0 USB x 427 SATA PATA PCI/PCI BRIDGE 22~25 LT- lock iagram YTEM / TP0 INPUT OUTPUT 0 /MM M/M Pro/x 0 RJ ONN EXT MI LK EN ILPR Thermal ensor/ Fan control MT RII / RII / lot lot Ricoh R ardreader OROM M0/M 0/00M/000M TLE RJ ML0 ONN RELTEK H UIO OE

More information

AMD CPU S1g1 ATI RS690M ATI SB600

AMD CPU S1g1 ATI RS690M ATI SB600 .'' active matrix color TFT.'' WX/WX ual hannel LV I/F PE PE PE RT TV OUT VI PE KEYP MTRIX PE PE LE ontrol, uage PE PE PE PE V VORE PE 0 PU VORE PE,, M Turion Mobile ual ore(taylor, pin,w,r,tl-0///0) M

More information

T76S: MEROM/965-PM/ICH8-M/NB8M-SE BLOCK DIAGRAM

T76S: MEROM/965-PM/ICH8-M/NB8M-SE BLOCK DIAGRAM TS: MEROM/-PM/IH-M/NM-SE LOK IRM LOK EN. ISLPRLF-T R VRM*(X) Merom PE ufp FN Thermal sensor F PE PE,, PE FS 00 MHz LVS nvii NM-SE PE RT PE POWER RESTLINE PM PIE * PE ~ R-II SO-IMM R MHz VORE PE 0 SYSTEM

More information

ACER_BAP31 MAIN BOARD INVENTEC ACER_JM31 CODE EE DATE POWER DATE DRAWER DESIGN CHECK RESPONSIBLE TITLE

ACER_BAP31 MAIN BOARD INVENTEC ACER_JM31 CODE EE DATE POWER DATE DRAWER DESIGN CHECK RESPONSIBLE TITLE ER_P MIN OR 00.. Tuesday, March 0, 00 TE HNE NO. X0 REV EE TE POWER TE RWER EIN HEK REPONILE IZE= VER: FILE NME: XXXX-XXXXXX-XX P/N XXXXXXXXXXXX INVENTE ER_JM OE IZE O.NUMER REV --00-L X0 X0 HEET . chematic

More information

Leopard2 Block Diagram

Leopard2 Block Diagram LK N I0 Leopard lock iagram Mobile PU othan V_UX onn PMI Power LOT witch TP0 /M in ard lost PI RU /M/MM/M lviso Host U 00/MHz V TI MP Mini-PI 0.a/b/g RJ ONN RJ ONN 0, 0/00 RTL00 MOM M ard, PI U -LINK,,,,,0,,,

More information

G HDMI 4, 5. DVI ATI M76-M PCI-EG. Page.44~50 LAN 10/100/1000 PCI-E6. INTEL 82566MM Page.23,24 PCI-E3 PCI-E4 /USB 2.

G HDMI 4, 5. DVI ATI M76-M PCI-EG. Page.44~50 LAN 10/100/1000 PCI-E6. INTEL 82566MM Page.23,24 PCI-E3 PCI-E4 /USB 2. R lock iagram LK EN. / MHz R MI In x I LPR / MHz odec L /MHz ZLI OP MP Q INT.PKR x OK E R PI-E PI-Express U.0 PORT/PORT Repeater/ PIEQX0 ock Port x Jack In x RJ- Ethernet Port x HMI x RT x U.0 x udio In

More information

G60J Schematics for Calpella Platform Rev. 1.5

G60J Schematics for Calpella Platform Rev. 1.5 YTEM PE REF. 0. lock iagram 0. ystem etting 0. PU()_MI,PE,FI,LK,MI 0. PU()_R 0. PU()_F,RV,N 0. PU()_PWR 0. PU()_XP. R()_O-IMM0. R()_O-IMM. R()_/Q Voltage. VI ontroller 0. PH()_T,IH,RT,LP. PH()_PIE,LK,M,PE.

More information

Model Name: 8I945AE-AE Revision 1.1

Model Name: 8I945AE-AE Revision 1.1 Model Name: IE-E Revision. HEET TITLE HEET TITLE 0 0 0 0 0 0 0 0 0 0 0 OVER HEET LOK IRM OM & P MOIFY HITORY P_L_ P_L_ P_L_ P_L_,E,F, MH-LKEPORT_HOT MH-LKEPORT_RII MH-LKEPORT_PI E, MI MH-LKEPORT_INT V

More information

PART for BOM only 02G GPU NB8M

PART for BOM only 02G GPU NB8M RT_TY P PRT for OM only Function U Partnumber RT TY 000 LOTION Temp Modify 0: elete E,,,, already have in location elete E, No space to add elete,,0,,,,,,, No space to add TT PU NM 00000 Title Revision

More information

CPU Diamondville N270 & N280 NORTH BRIDGE SOUTH BRIDGE. SATA FPC Conn

CPU Diamondville N270 & N280 NORTH BRIDGE SOUTH BRIDGE. SATA FPC Conn 0_lock iagram 0_ystem etting 0_Power equence 0_lock en_ipr 0_iamondville_U 0_iamondville_PWR 0_N-M(OT) 0_N-M(MI) 0_N-M(RPI) 0_N-M(R) _N-M(PWR) _N-M(PWR) _N-M() _-IM(PWR) _-IM() _-IM() _-IM() _R OIMM _R_Termination

More information

INTEL PINETRAIL Platform F10T. Notes: Version : A Drawing by :Wain

INTEL PINETRAIL Platform F10T. Notes: Version : A Drawing by :Wain over sheet LOK_IRM MU_&_IRQ_ROUTIN POWER_ON_EQUENE POWER_lock POWER_UET POWER_EQUENE LOK_EN PU PU N N N N N N R_OIMMO R_TEMINTION L_ON RT IHM IHN IHM IHM U_PORT H MINIR MOEM ON LN RIHO RIHO RU L OE UIO

More information

On Board Device: Main Memory: Dual-channel DDR-II * 4 (Max 8GB) Expansion Slots: PCI EXPRESS X16 SLOT *2 PCI EXPRESS X1 SLOT * 1 PCI SLOT * 2

On Board Device: Main Memory: Dual-channel DDR-II * 4 (Max 8GB) Expansion Slots: PCI EXPRESS X16 SLOT *2 PCI EXPRESS X1 SLOT * 1 PCI SLOT * 2 ONTENT over, lock diagram Intel L PU HEET - - TX Version:. NVII R IMM,,, R Terminations NVII R0 NVII MP PI lot & - - - - PU: Intel Pentium edar Mill / Prescott, Pentium mithfield / Presler and onroe /

More information

U35JC SCHEMATIC Revision 1.0

U35JC SCHEMATIC Revision 1.0 YTEM PE REF. PE ontent lock iagram ystem etting PU()_MI,PE,FI,LK,MI PU()_R PU()_F,RV, PU()_PWR PU()_XP R O-IMM_0 R O-IMM_ R _Q VOLTE 0 PH_IEX()T,IH,RT,LP PH_IEX()_PIE,LK,M,PE PH_IEX()_FI,MI,Y PWR PH_IEX()_P,LV,RT

More information

FOXCONN Title. Schematics Page Index (Title / Revision / Change Date) Project Code & Schematics Subject:

FOXCONN Title. Schematics Page Index (Title / Revision / Change Date)   Project Code & Schematics Subject: Page of chematics Page 0 chematics Page Index 0 lock iagram 0 Penryn(HOT U) / 0 Penryn(HOT U) / 0 Penryn (Power/nd) / 0 LOK N 0 antiga (HOT) / 0 antiga (MI) / 0 antiga (RPHI) / 0 antiga (RII) / antiga

More information

Canary2 Block Diagram

Canary2 Block Diagram anary lock iagram 0- V_0 0V_0 Line Out R II IN LK N. IT V RJ- RIL PORT, RT HOT U lviso-m MI I/F IH-M PT Port Replicator ( PIN) PRINTR MHz 00MHz ROM 0 P PI U LP U MI LIN IN LIN OUT TV OUT K TM R 00/MHz

More information

N61Jv SCHEMATIC Revision 2.0

N61Jv SCHEMATIC Revision 2.0 YTEM PE REF. PE ontent lock iagram ystem etting PU()_MI,PE,FI,LK,MI PU()_R PU()_F,RV, PU()_PWR PU()_XP R OIMM_0 R OIMM_ R _Q VOLTE VI controller 0 PH_IEX()T,IH,RT,LP PH_IEX()_PIE,LK,M,PE PH_IEX()_FI,MI,Y

More information

F3T Block Diagram. CPU S1g1 DDR2-667 PAGE 2,3,4. H.T 800 MHz C51MV PCIE *1 PCIE *1 PAGE 9,10,11,12,13 H.T MCP51 USB SATA USB 2.

F3T Block Diagram. CPU S1g1 DDR2-667 PAGE 2,3,4. H.T 800 MHz C51MV PCIE *1 PCIE *1 PAGE 9,10,11,12,13 H.T MCP51 USB SATA USB 2. FT lock iagram R M* R M* R M* R M* PE PU VORE PE,, PU g R- ual hannel R PE, O-IMM X bit H.T 00 MHz Power On equence PE LV & INV PE RT & TV OUT PE VI M PE,,,,,, PIE * MV PE,0,,, PIE * PIE * U PE MINI R

More information

G D8V_S3 667/8000MHz WXGA/SXGA+ LVDS. New card G577 USB 2.0. ACPI in 1 TRL8101E 23 PCI-E / USB 2.0 LPC BUS KBC.

G D8V_S3 667/8000MHz WXGA/SXGA+ LVDS. New card G577 USB 2.0. ACPI in 1 TRL8101E 23 PCI-E / USB 2.0 LPC BUS KBC. E YTEM / Project code: TP P0 lock iagram YTEM / Mobile PU PWQI LK EN. ILPRYLFT-P RTMT-0-V-RT HOT U Penryn, /00/0MHz@.0V Line Out odec H udio PI-E/U.0 L IHM New card PIe ports MI In PI/PI RIE M/M Pro/ U.0

More information

SWITCH BD ASSY R40II1 REV:02 PCB SW BD R40IIx REV *11.50*1.2 6L +*V_AUX +*V +*V_LDO +*V_DDR OFF. AC/DC S4/Moff (Suspend to Disk) OFF OFF OFF

SWITCH BD ASSY R40II1 REV:02 PCB SW BD R40IIx REV *11.50*1.2 6L +*V_AUX +*V +*V_LDO +*V_DDR OFF. AC/DC S4/Moff (Suspend to Disk) OFF OFF OFF Intel Penryn PU + antiga + IHM hipset R0IIx M/ / 0 VER PE 0 0 LK IRM MIELLNEU 0 PI 0 0 PU Penryn of PU Penryn of 0 N antiga of 0 N antiga of 0 N antiga of 0 N antiga of N antiga of N antiga of LK ENERTR

More information

SCHEMATIC REV. DRAWING NO RELAY CONTROL CHART A A DE N V C L O REVISIONS

SCHEMATIC REV. DRAWING NO RELAY CONTROL CHART A A DE N V C L O REVISIONS THI RWIN I THE PROPERTY OF NLO EVIE IN. IT I NOT TO E REPROUE OR OPIE, IN WHOLE OR IN PRT, OR UE IN FURNIHIN INFORMTN TO OTHER, OR FOR NY OTHER PURPOE ETRIMENTL TO THE INTERET OF NLO EVIE. THE EQUIPMENT

More information

ZC1 SYSTEM BLOCK DIAGRAM. Yonah/Merom 479 ufcpga

ZC1 SYSTEM BLOCK DIAGRAM. Yonah/Merom 479 ufcpga TVOUT TFT L Panel." WSXG+ X'TL M VI RT luetooth US US P P P P P amera Module(.M) P in ardreader (SMS ) P US US Port x US0~ P VI TVout LVS VG Media-ay O/nd H/nd attery P X'TL.MHZ lock Generator H IS0GLF

More information

Morar Block Diagram 2005/05/28

Morar Block Diagram 2005/05/28 Morar lock iagram 00/0/ LK N. Mobile PU Project ode:.0.00 YTM / TP0, P:00- R II 0 MHz R II 0 MHz IT V,, HOT U Intel 0ML MI I/F 0MHz 00MHz,,,,0 R_VRF V_ R_VRF_ Line In Int. MI In, odec L 0MHz 0MHz LINK

More information

S Note-3 Block Diagram

S Note-3 Block Diagram Jan. ' Keyboard Light Thermal ensor MX99 LM I us / M us TML TRFN LIN OUT Int. MI MI IN RJ ONN Mus UNUFFR On-oard R OIMM x,,,, H 9 -PIN R OIMM UNUFFR R OIMM ocket, OP MP MX9 9 O 9,, Modem/luetooth U U lock

More information

Alba Discrete ATI M92-LP gddr2 Schematics ufcpga Mobile Penryn Intel Cantiga-PM + ICH9M REV : SA

Alba Discrete ATI M92-LP gddr2 Schematics ufcpga Mobile Penryn Intel Cantiga-PM + ICH9M REV : SA lba iscrete TI M-LP gr chematics ufp Mobile Penryn Intel antiga-pm + IHM 00-0- REV : : Nopop omponent M : Pop when antiga is M PM : Pop when antiga is PM /P : OM control if antiga is PM Wistron

More information

Power supply, reset circuit, reference voltage and power indicator. Analogue and digital inputs with options for FET outputs

Power supply, reset circuit, reference voltage and power indicator. Analogue and digital inputs with options for FET outputs VR core and power 00v.0 Power supply, reset circuit, reference voltage and power indicator. Port 00v.0 nalogue and digital inputs with options for FET outputs Port 00v.0 igital inputs with optional FET

More information

CPU NORTH BRIDGE SOUTH BRIDGE

CPU NORTH BRIDGE SOUTH BRIDGE 0_lock iagram 0_System Setting 0_Power Sequence 0_lock Gen_ISLPR 0_iamondville_US 0_iamondville_PWR 0_N-GMS(HOST) 0_N-GMS(MI) 0_N-GMS(GRPHI) 0_N-GMS(R) _N-GMS(PWR) _N-GMS(PWR) _N-GMS() _S-IHM(PWR) _S-IHM()

More information

Pamirs UMA Block Diagram

Pamirs UMA Block Diagram RJ ONN /IO/MM M/M Pro/x LK N ILPRKLFT-P RII / lot 0 RII / Ricoh R ardreader 0/00 NI Marvell 0 lot, Pamirs UM lock iagram RII hannel R II hannel PI LI Intel PU Meron M/M V F: or 00 MHz,, Host U /MHz restline-m/ml

More information

Z96J DDR2 SO-DIMM1 DDR2 SO-DIMM0 AZALIA CODEC NEWCARD MINICARD CLOCK GEN MDC BRIDGE BRIDGE SOUTH NORTH CPU. Card Reader M56P TPM 1.2 ATI LAN AUDIO AMP

Z96J DDR2 SO-DIMM1 DDR2 SO-DIMM0 AZALIA CODEC NEWCARD MINICARD CLOCK GEN MDC BRIDGE BRIDGE SOUTH NORTH CPU. Card Reader M56P TPM 1.2 ATI LAN AUDIO AMP R Mx x Option P. YONAH W CPU MEROM P.~ W CLOCK EN IC 0 P. ZJ R Mx x P. PB MHz THERMAL CONTROL P. LC CRT P. P. TV-OUT P. ATI MP PCI-E X NORTH BRIE Intel PM P.~0 P.~ R R R O-IMM0 P.0~ R O-IMM IA ROM TPM.

More information

AG1(Alviso) Block Diagram 2005/11/01

AG1(Alviso) Block Diagram 2005/11/01 (lviso) lock iagram 00//0 LK N. Mobile PU Project ode:.0.00 P:0-0 Line Out R II 00 MHz R II 00 MHz Line In Int. MI In INT.PKR P Layer tackup L: ignal L:V L: ignal L: ignal L: N L: ignal IT V,, odec L OP

More information

A_SYNCOUT1_P A_SYNCOUT1_N A_SYNCOUT2_P A_SYNCOUT2_N A_SYNCOUT3_P A_SYNCOUT3_N

A_SYNCOUT1_P A_SYNCOUT1_N A_SYNCOUT2_P A_SYNCOUT2_N A_SYNCOUT3_P A_SYNCOUT3_N ate: //00 heet of File: :\User\..\MFO.choc rawn y: NIN_P NIN_N NOUT_P NOUT_N N_N N_P LE OLK_P OLK_N NTROUT_P NTROUT_N IN_P LK_P LK_N NV_P IN_N NV_N VO MFO.choc TK TI TO TK TI TO LK _IN ONE HWP INIT_ M

More information

AS1117M3 or LM1117MPX-ADJ ADJ. C20 0.1uF + C56. + C57 10uF. 10 uf R K 1% R18 GND 10.0K 1%

AS1117M3 or LM1117MPX-ADJ ADJ. C20 0.1uF + C56. + C57 10uF. 10 uf R K 1% R18 GND 10.0K 1% K POWER SW JP EXTERNL POWER FUSE 0. uf VT 0 uf R SM or LMMPX-J VIN VOUT U 0.0K % J R.K % 0uF REG_V 0 0.uF REG_V J PV PV_US_TGT V_M0X POWER_SELET R0 0Ohm V to V ENTER POSITIVE.

More information

M630/M640 Main Board.

M630/M640 Main Board. chematics Page Index ( / Revision / hange ate) Page of chematics Page Rev. ate Page 0 chematics Page Index 0 lock iagram 0 Merom(HOT U) / 0 Merom(HOT U) / 0 Merom(Power/nd) / 0 0 LOK N 0 restline (HOT)

More information

REVISION HISTORY DESCRIPTION INITIAL SCHEMATIC AIY REMOVED ANALOG SWITCHES CHANGED FEEDBACK

REVISION HISTORY DESCRIPTION INITIAL SCHEMATIC AIY REMOVED ANALOG SWITCHES CHANGED FEEDBACK REVISION HISTORY Notes - Unless otherwise noted. Resistances values in Ohms. apacitance values in micrarads (uf). ll 0.uF and 0.0uF capactors are decoupling and should be placed near the I they are shown

More information

KEIm Baseboard. PAGE DESCRIPTION 1 Block Diagram, History 2 SoM Connector. 3 LCD Connector. 4 Ethernet. 5 UART 6 Analog 7 Peripheral 8 Power

KEIm Baseboard. PAGE DESCRIPTION 1 Block Diagram, History 2 SoM Connector. 3 LCD Connector. 4 Ethernet. 5 UART 6 Analog 7 Peripheral 8 Power KEIm aseboard REV TE PGES ESRIPTION.0.0 Oct//0 ll INITIL REVISION RELESE..0 Feb//0 ll MP REVISION RELESE PGE ESRIPTION lock iagram, History SoM onnector L onnector Ethernet URT nalog Peripheral Power KONO

More information

ME3 Block Diagram HDD G792 ICH8-M. Project code : 91.4X PCB P/N : Revision : PCB LAYER LPC DEBUG CONN. TPM SLB9635TT KBC. Intel CPU.

ME3 Block Diagram HDD G792 ICH8-M. Project code : 91.4X PCB P/N : Revision : PCB LAYER LPC DEBUG CONN. TPM SLB9635TT KBC. Intel CPU. M lock iagram RII lot 0 RII lot Power witch RJ ONN Line In INT.PKR Line Out (PIF) RJ INT. MI rray igital HMI (PIF),, Mini ard_ Robson Mic In -T ONN RII hannel RII hannel MP MP MOM -T IL 0/00 ontroller

More information

Model Name: 965P-DQ6. Revision 1.01F

Model Name: 965P-DQ6. Revision 1.01F Model Name: P-Q HEET TITLE Revision.0F HEET TITLE 0 0 0 0 0 0 0 0 0 0 0 OVER HEET OM & P MOIFY HITORY LOK IRM POWER MP P_L_ P_L_ P_L_ P_L_ MH-ROWTER_HOT MH-ROWTER_RII MH-ROWTER_PI E, MI MH-ROWTER_T V MH-ROWTER_

More information

NV11,4Mx16 DDR, RGB, INTERNAL DVI-I, AGP.

NV11,4Mx16 DDR, RGB, INTERNAL DVI-I, AGP. . NV.V 00PF 00PF 00PF 0.UF 0.UF 0.UF 0.UF 0UF 0UF 0 0.UF 0.UF.V TO- -pin package Semtech Z, Unisem US0 00 NV O- RG-PWR-IN.V@ /- 0mV 0UF 00PF 00PF 0 00PF 0UF 00PF 0UF 0 0.UF 0 00PF 0.UF 0 O0 U POWR SNS

More information

HOSCO HOSCI AS M AS M C1 18P C2 18P C1 18P C2 18P GND VCC3 GPIOK7 R82 R82 10K A20 10K. #OffHook. FmHook #TRANSLED. VxBP 0.1U 0.

HOSCO HOSCI AS M AS M C1 18P C2 18P C1 18P C2 18P GND VCC3 GPIOK7 R82 R82 10K A20 10K. #OffHook. FmHook #TRANSLED. VxBP 0.1U 0. 0 #E0 GPIOK #MWR #MR #FWE HOSI KEYI0 GPIO0 HOSO V V VREFI KEYI GPIO GPIO_ V KEYO GPIO #E OUTR MIIN VMI GPIO_0 #LON V #HOL 0 0 #E KEYO GPIO 0 KEYO0 GPIO GPIO_ GPIO_0 #MR #MWR V V V V TSEL #E #E0 V HOSI

More information

J1B B1 B3 B5 B7 B9 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B35 B37 B39 B41 B43 B45 B47 B49 B51 B53 B55 B57 VCC VCC USB_DET

J1B B1 B3 B5 B7 B9 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B35 B37 B39 B41 B43 B45 B47 B49 B51 B53 B55 B57 VCC VCC USB_DET GP0 GP0 GP0 P0 GP0 GP GP GP GP GP GP GP P GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP00 UINO ONE PIN EFINE GP0 GP GP GP GP GP GP GP GP0 GP GP

More information

FOXCONN Title. Schematics Page Index (Title / Revision / Change Date) Rev M/B P/N:

FOXCONN Title. Schematics Page Index (Title / Revision / Change Date) Rev M/B P/N: Page 0 0 0 0 0 0 0 0 0 0 0 0 of chematics Page chematics Page Index lock iagram Merom(HOT U) / Merom(HOT U) / Merom(Power/nd) / LOK N restline (HOT) / restline (MI) / restline (RPHI) / restline (RII) /

More information

Beyonce UMA Schematics Document. ufcpga Mobile Merom Intel Crestline-GM + ICH8M REV : -2 (DELL:A00)

Beyonce UMA Schematics Document. ufcpga Mobile Merom Intel Crestline-GM + ICH8M REV : -2 (DELL:A00) eyonce UM chematics ocument ufp Mobile Merom Intel restline-m + IHM 00-0- REV : - (ELL:00) Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. eyonce UM ize ocument Number

More information

20-JUNE-14 SCHEMATIC HSC REV. DRAWING NO.

20-JUNE-14 SCHEMATIC HSC REV. DRAWING NO. THI RWING I THE PROPERTY OF NLOG EVIE IN. IT I NOT TO E REPROUE OR OPIE, IN WHOLE OR IN PRT, OR UE IN FURNIHING INFORMTION TO OTHER, OR FOR NY OTHER PURPOE ETRIMTL TO THE INTERET OF NLOG EVIE. THE EQUIPMT

More information

AS1117M3 or LM1117MPX-ADJ REG_VDD ADJ. C20 0.1uF U6. + C57 10uF R K 1% GND 3.92K 1%

AS1117M3 or LM1117MPX-ADJ REG_VDD ADJ. C20 0.1uF U6. + C57 10uF R K 1% GND 3.92K 1% K POWER SW JP EXTERNL POWER FUSE 0. uf VT + 0 uf SM or LMMPX-J REG_V VIN VOUT + 0uF 0 0.uF U R 0.0K % J R.K % REG_V J PV PV_US_TGT V_M0X POWER_SELET R0 0Ohm V to V ENTER POSITIVE.

More information

PCB NO. DM205A SOM-128-EX VER:0.6

PCB NO. DM205A SOM-128-EX VER:0.6 V. M0 M M M M M M M MQM0 MQS0N MQS0P M M M0 M M M M M MQM MQSN MQSP U RM R0 Q00 M0 U Q0 M T Q0 M R Q0 M U Q0 M U Q0 M T Q0 M T Q0 M T M0 M U QS0N M U QS0P M0 M W0 Q0 M W Q0 M V0 Q0 M U0 Q M W Q W Q 0 V

More information

Thurman UM chematics ocument ufp Mobile Merom Intel restline-m + IHM 00-0- REV : (ELL:X0) Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Thurman UM ize ocument Number

More information

Generated by Foxit PDF Creator Foxit Software For evaluation only.

Generated by Foxit PDF Creator Foxit Software   For evaluation only. I_ST I_SLK K_% R K_% R L_0 L_ L_ L_ KEY TON_STHL /F NN_ NN_ P M VS OUTL P OUTR VR MIIN VREF V HOSI LOSI R X pf LOSO.KHZ M_% pf HOSO X pf MHz HOSI 0 pf POWER Generated by Foxit PF reator Foxit Software

More information

CPU Intel Penryn (Socket P) 3,4. FSB 800/1067 MHz. Cantiga GM LVDS. Panel CRT VGA. x4 DMI. 34 x 34mm 1329 FCBGA HDMI 10~15 DMI X4.

CPU Intel Penryn (Socket P) 3,4. FSB 800/1067 MHz. Cantiga GM LVDS. Panel CRT VGA. x4 DMI. 34 x 34mm 1329 FCBGA HDMI 10~15 DMI X4. NOTE " UM lock iagram 00/0/ PU Intel Penryn (Socket P), FS 00/0 MHz Thermal Sensor G0 FN 0 0 LOK GEN. ISLPRSGLFT RII SOIMM, RII antiga GM x MI LVS VG Panel RT RII SOIMM, RII x mm FG HMI LEVEL SHIFTER PERIOM

More information

RSC CHIP VDD P05 P03 P01 P04 VDD GND PWM0 AVDD VDD AVDD P0-2 P0-5 P0-1 P0-6 P0-4 P0.3 GND P00. Y1 3.58MHz P00 P01 AGND P01 P00 P02 P02 P07 P0-0 P0-7

RSC CHIP VDD P05 P03 P01 P04 VDD GND PWM0 AVDD VDD AVDD P0-2 P0-5 P0-1 P0-6 P0-4 P0.3 GND P00. Y1 3.58MHz P00 P01 AGND P01 P00 P02 P02 P07 P0-0 P0-7 Place as close to pins of U as possible. RS HIP 0-00 RS-x emo/evaluation oard: RS-000 Thursday, ecember, 00 Size ocument Number Rev ate: Sheet of P XI P0 P0 P0 P0 P00 PN P0 P0 P0 P0 P0 P0 P0 P0 P XO -XM

More information

AMD REV.F ATI RS690M ATI SB600

AMD REV.F ATI RS690M ATI SB600 LV & INV PE PE PE PE PE PE KEYP MTRIX PE PE 0 LE PE 0 PE PE RT TV OUT VI IR IR INTNT KEY I ROM (M) MPLIFIER UPER I/O ITEITF_IX PE E ITE PE, M onn (RJ) PE zalia odec L 0 PE 0 PU VORE TI PIE * M-M LP MHz

More information

MS Last Schematic Update Date: 11/06/2002

MS Last Schematic Update Date: 11/06/2002 over heet lock iagram MIN LOK EN & IE ONNETOR mp- INTEL PU ockets INTEL rookdale- /L MH R LOT R TERMINTOR INTEL IH H00 & VI TV OUT PI LOT / FWH U PORT LP I/O(Ms LPM) OM & LPT & F & FN K / M ONNETOR / POV

More information

SHELBY-INTEGRATED CLOCKS ICS PG 17. sdvo SI1362 PG 18 USB2.0 (P5,P6) USB2.0 (P3,P4) USB2.0 (P7) 1394 CONN PG 25 USB2.

SHELBY-INTEGRATED CLOCKS ICS PG 17. sdvo SI1362 PG 18 USB2.0 (P5,P6) USB2.0 (P3,P4) USB2.0 (P7) 1394 CONN PG 25 USB2. IMVP- PU VR PG RUN POWER SW PG UIO ST00 PG, / +V_SR +VSUS PG /TT ONNETOR TT SELETOR TT HRGER POWER / R-SOIMM PG, R-SOIMM PG, ST - H PG Internal Media ay -ROM PG S/PIF to OK PG udio Jacks PG RJ to OK PG

More information

,. *â â > V>V. â ND * 828.

,. *â â > V>V. â ND * 828. BL D,. *â â > V>V Z V L. XX. J N R â J N, 828. LL BL D, D NB R H â ND T. D LL, TR ND, L ND N. * 828. n r t d n 20 2 2 0 : 0 T http: hdl.h ndl.n t 202 dp. 0 02802 68 Th N : l nd r.. N > R, L X. Fn r f,

More information

C107 C108 C uF/10V Ta. 10uF/10V Ta. 100nF. 100nF. 100nF C106 C111 C110 VCC VCC AVCC (AD0)PA0 (AD1)PA1 (AD2)PA2 (AD3)PA3 (AD4)PA4 (AD5)PA5

C107 C108 C uF/10V Ta. 10uF/10V Ta. 100nF. 100nF. 100nF C106 C111 C110 VCC VCC AVCC (AD0)PA0 (AD1)PA1 (AD2)PA2 (AD3)PA3 (AD4)PA4 (AD5)PA5 ate: may 0 Kiad.... ize: Id: / RPIVR alarm v. File: rpialarm.sch heet: / pittnerovi.com P0 P P 0 P0 PI VR_ IRQ IRQ VR_ V R0 00k RFM_IRQ PWM LOOP LOOP0 comm comm.sch 00uF/.V R0 00k V VR_ K VR_ V V RT P0

More information

MODEL REV CHANGE LIST ZL9. Preliminary Release

MODEL REV CHANGE LIST ZL9. Preliminary Release E MOEL REV HNGE LIST ZL Preliminary Release Page : dd.pf for Signal quanlity Page : dd R0 0om for UM. Page : seprate STLE# for IE interrupt. Page :add R 0ohm for M-T. Page : enlarge H,H to mm for VG sink

More information

A8E/A8S Merom/GM965/PM965 BLOCK DIAGRAM CPU ... MEROM. 3,4 HOST BUS CRESTLINE GM965/PM965 11~15 X4 DMI PCI EXPRESS X1 3 3 SYSTEM

A8E/A8S Merom/GM965/PM965 BLOCK DIAGRAM CPU ... MEROM.  3,4 HOST BUS CRESTLINE GM965/PM965 11~15 X4 DMI PCI EXPRESS X1 3 3 SYSTEM E/S Merom/GM/PM LOK IGRM E Sub block iagram / OM option VI ual H. HOST US RT & TV ON LVS & INV ON VORE R SRM /MHz SYSTEM.VS &.0VS R & VTT +VO & +.VS HRGER PI ETET PROTET LO SWITH FLOWHRT VG ON US x /T

More information

HF SuperPacker Pro 100W Amp Version 3

HF SuperPacker Pro 100W Amp Version 3 HF SuperPacker Pro 00W mp Version Revised 0 0 V Stamps KOOR This is the third generation HF SuperPacker Pro 00W Version home construction project offered by HF Projects. This is a group construction project

More information

Page 0 0 0 0 0 0 0 0 09 0 9 0 9 0 9 0 chematics Page Index ( / Revision / hange ate) of chematics Page chematics Page Index lock iagram R (MI,PE,FI) R (LK,MI,JT) R (R) R (POWER) R (RPHI POWER) R (N) R

More information

L13X DAUGHTER CARDS TABLE OF CONTENTS REV SL NO. TABLE OF CONTENTS VERSION VERSION HISTORY BLOCK DIAGRAM 4 UART-0 INTERFACE

L13X DAUGHTER CARDS TABLE OF CONTENTS REV SL NO. TABLE OF CONTENTS VERSION VERSION HISTORY BLOCK DIAGRAM 4 UART-0 INTERFACE LX UGHTER RS TLE OF ONTENTS SL NO. ONTENTS PGE NO REV TLE OF ONTENTS VERSION HISTORY VERSION.0.. LOK IGRM URT-0 INTERFE N US INTERFE URT INTERFE PROFI US & SOFT IR INTERFE SOFT URTS REV NO. NTURE OF HNGE

More information

core Tiny6410.sch DM9000 DM9000-etc.sch AC97 AC97-etc.sch USB HUB USB-HUB.sch Tiny6410SDK 1103

core Tiny6410.sch DM9000 DM9000-etc.sch AC97 AC97-etc.sch USB HUB USB-HUB.sch Tiny6410SDK 1103 core Tiny0.sch M000 M000-etc.sch -etc.sch US HU US-HU.sch Tiny0SK 0 M_ VV V V V V V V V V V VN VSYN VLK VUS OTGI OTGM OTGP IN0 S_LK S_n S_T0 S_T OUT0 INT INT INT RST ( 红色 ) Tiny0 Tiny0 P Power Supply S

More information

J400 C UF,50V,20% V-STBY 10.0K,1%,1/4W R63 R61 1M,5%,1/4W V-STBY R K,1%,1/4W AC-OK RY3A R11INT 1 NC NO COM 47K,5%,1/4W R11

J400 C UF,50V,20% V-STBY 10.0K,1%,1/4W R63 R61 1M,5%,1/4W V-STBY R K,1%,1/4W AC-OK RY3A R11INT 1 NC NO COM 47K,5%,1/4W R11 MNL-PIN J MNL-PIN J MNL-PIN J MNL-PIN J J00-00 MNL-PIN J MV J MNL-PIN PHS-REF (Sh. ) IN-RET (Sh.,) -OK (Sh. ) HOT-IN 0V(US) 00V(INT) MV LIN-XFER (Sh. ) +V OOST (Sh. ) TRIM (Sh. ) MNL-PIN MNL-PIN 0V(US)

More information

DR1 (Roberts) Schematics Document ufcpga Mobile Penryn Intel Cantiga-GM + ICH9M REV : A00

DR1 (Roberts) Schematics Document ufcpga Mobile Penryn Intel Cantiga-GM + ICH9M REV : A00 R () chematics ocument ufpg Mobile Penryn Intel antiga-gm + IHM 00-0-0 REV : 00 : Nopop omponent Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. over Page

More information

Scalar Diagram & C.B.A

Scalar Diagram & C.B.A XLFH LC C _0.U Z A A U I/O I/O VGA_PC_V V I/O I/O AZC-0 RAI L Z0 R F C 0.0U V RE RE VGA_CL VGA_A R F R F R F R F R F R _ F C _.P C R 0 C 0.0U V AI- RE-.V VGA_PC_V C C R 00 J R 00 J HY R R K J Q VGA_WP

More information

Reference Schematic for LAN9252-HBI-Multiplexed Mode

Reference Schematic for LAN9252-HBI-Multiplexed Mode Reference Schematic for LN-HI-Multiplexed Mode onfigurations HI Multiplexed mode EEPROM - F (High) Port mode Port0 & Port = opper Page No. Schematic Page Title Power Supply LN(Part) LN(Part), Strap & EEPROM

More information

R2 44.2K_1% 5DVCC 5DVCC GND COMP SS24 DW1. EC2 470uF/16V. 470uF/16V 内内内内内内 DW2; 去去 U103,L9 33V. 33V C15 NC/10uF 33V C17 D2 NC/UDZ33B-33V

R2 44.2K_1% 5DVCC 5DVCC GND COMP SS24 DW1. EC2 470uF/16V. 470uF/16V 内内内内内内 DW2; 去去 U103,L9 33V. 33V C15 NC/10uF 33V C17 D2 NC/UDZ33B-33V JK_P JP V V L 0u/N F FUSE() FUSE E 0uF/V E. V L 0u/N V 00nF 00nF V, R 00K 00nF U MP IN EN SS OMP 0nF S SW F 0.nF R K SW L u R.K_% R 0K_% V E 0uF/V V,,, ST-V V 00nF.uF 00P SS W ST-V E 0uF/V E 00nF TO U

More information

SYMETRIX INC th Avenue West Lynnwood, WA USA

SYMETRIX INC th Avenue West Lynnwood, WA USA ENE MI J XLR-FEMLE NOTE: ENE MI R K00 R K00 J (h ) isables phantom power for all mics. Remove R and/or R to disable phantom power for ense Mic and/or only. J XLR-FEMLE NP NP 0 NP R K00 R K00 NP R 0 NP

More information

YROTATE-IT-RX23T YROTATE-IT-RX23T_3-10.SCH YROTATE-IT-RX23T YROTATE-IT-RX23T_9-10.SCH. Date APR, 29, 2015 Sheet.0 OF

YROTATE-IT-RX23T YROTATE-IT-RX23T_3-10.SCH YROTATE-IT-RX23T YROTATE-IT-RX23T_9-10.SCH. Date APR, 29, 2015 Sheet.0 OF YROTTE-IT-RXT YROTTE-IT-RXT_-0.H YROTTE-IT-RXT YROTTE-IT-RXT_-0.H YROTTE-IT-RXT YROTTE-IT-RXT_-0.H YROTTE-IT-RXT YROTTE-IT-RXT_-0.H YROTTE-IT-RXT YROTTE-IT-RXT_-0.H YROTTE-IT-RXT YROTTE-IT-RXT_-0.H YROTTE-IT-RXT

More information

Reference Schematic for LAN9252-SPI/SQI+GPIO16 Mode

Reference Schematic for LAN9252-SPI/SQI+GPIO16 Mode Reference Schematic for LN-SPI/SQI+GPIO Mode onfigurations SPI/SQI+GPIO Mode EEPROM - F (High) Port mode Port0 & Port = opper Page No. Schematic Page Title Power Supply LN(Part) LN(Part), Strap & EEPROM

More information

Virtex 5 FF1136 DUT. Single Ended Socket Clocks 2X. Differential SMA MGT Clocks 2X D. Differential SMA Clocks 2X. Upstream Connector.

Virtex 5 FF1136 DUT. Single Ended Socket Clocks 2X. Differential SMA MGT Clocks 2X D. Differential SMA Clocks 2X. Upstream Connector. PGE System Monitor ux PGE System Monitor PGE System ce Upstream PGE Upstream onnector PGE Single Ended Socket locks X PGE ifferential SM locks X PGE ifferential SM MGT locks X PGE - Power us and Switches

More information

1101HA Block Diagram (Silverthorne / Poulsbo)

1101HA Block Diagram (Silverthorne / Poulsbo) 0_LK RM 0_H P etting 0_E Pin efine 0_Power equrnse 0_Power equence 0_Power equence escription 0_lock en_lpr 0_PU-LVERTHRNE () 0_PU-LVERTHRNE () 0_PU-LVERTHRNE () _H_Poulsbo_HT () _H_Poulsbo_R () _H_Poulsbo_LV/V

More information

PR D NT N n TR T F R 6 pr l 8 Th Pr d nt Th h t H h n t n, D D r r. Pr d nt: n J n r f th r d t r v th tr t d rn z t n pr r f th n t d t t. n

PR D NT N n TR T F R 6 pr l 8 Th Pr d nt Th h t H h n t n, D D r r. Pr d nt: n J n r f th r d t r v th tr t d rn z t n pr r f th n t d t t. n R P RT F TH PR D NT N N TR T F R N V R T F NN T V D 0 0 : R PR P R JT..P.. D 2 PR L 8 8 J PR D NT N n TR T F R 6 pr l 8 Th Pr d nt Th h t H h n t n, D.. 20 00 D r r. Pr d nt: n J n r f th r d t r v th

More information

CD-DET TP5_CS- LCDPWR RFPWR CHPD5 GP05 GP25 RST5 L13 D12 D11 D10 LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS- LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS-

CD-DET TP5_CS- LCDPWR RFPWR CHPD5 GP05 GP25 RST5 L13 D12 D11 D10 LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS- LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS- SPST SW L 0uH.uF TP HEER NO STUFF TP 0 HEER NO STUFF TP TP pf Y.uF.uF 0 HEER NO STUFF 0 HEER NO STUFF MHz, 0ppm pf.uf (OUT) (IN) R 0K /W % 0uF OUT OUT OUT OUT KLT L 0 L_MISO L_MOSI L_SK S_S- L_S- L_- L_

More information