CPU T2060 4xx,5xx Series PAGE 2,3. FSB 533MHz. GMCH-M Calistoga 943GML B0:02G PAGE 6,7,8,9,10,11 DMI Interface PCIE *1 ICH7-M PCIE *1

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1 TERE lock iagram PE FN ENR M0RMZ PE, PU T00 xx,xx eries PE PE LK EN 0 HRER RUT F MHz Power n equence PE 0 TP PE PE LV & NV RT MH-M alistoga ML 0:00000 PE,,,,0, M nterface R-MHz ual hannel R PE,, -MM X PE PE 0 PE TT N PU VRE YTEM PWR KEYP MTRX PE PE NTNT KEY LE ontrol PE 0, PE 0 PE,0 E TE RM LP MHz zalia PE,,,0 H-M 0:00000 T E U PE * PE * P MHz PE PE MN R WLN NEW R PE, T T 000 LN RTL00L PE T & HRER M PHNE JK PE HEPHNE JK PE PE zalia odec PE,, PE PE H (T) PE U.0 N X PE, ardus R T PE PM ME R LT PE T T PEKER U MP PE PE PE M T ULPHTeK MPUTER N. LK RM Horng hou ize Project Name Rev ustom TERE ate: Monday, February 0, 00 heet of.

2 H_#[..] H_REQ#[..0] H_#[..] T0 H_#[0..] H_T#0 H_T# H_0M# H_FERR# H_NNE# H_TPLK# H_NTR H_NM H_M# U0 H_# J H_# []# L H_# []# M H_# []# K H_# []# M H_# []# N H_# []# J H_#0 []# N H_# [0]# P H_# []# P H_# []# L H_# []# P H_# []# P H_# []# R H_T#0 []# L T[0]# H_REQ#0 H_REQ# H_REQ# H_REQ# H_REQ# H_0M# H_FERR# H_NNE# K REQ[0]# H REQ[]# K REQ[]# J REQ[]# L REQ[]# H_# Y H_# []# U H_# []# R H_#0 []# W H_# [0]# U H_# []# Y H_# []# U H_# []# R H_# []# T H_# []# T H_# []# W H_# []# W H_# []# Y H_#0 []# W H_# [0]# Y H_T# []# V T[]# 0M# FERR# NNE# H_TPLK# H_NTR TPLK# H_NM LNT0 H_M# LNT M# RV[] RV[] RV[] RV[] M RV[] N RV[] T RV[] V RV[] RV[] RV[0] RV[] R RUP 0 R RUP THERM HLK REERVE NTRL XPTP NL # H NR# E PR# EFER# H RY# F Y# E R0# (00)hange PU ocket into PN=00 F ERR# 0 NT# LK# H REET# R[0]# F R[]# F R[]# TRY# HT# HTM# E PM[0]# PM[]# PM[]# PM[]# PRY# PREQ# TK T T TM TRT# R# 0 PRHT# THERM THERM THERMTRP# LK[0] LK[] RV[] T RV[] RV[] RV[] F RV[] RV[] RV[] F RV[] RV[] RV[0] H_# H_NR# H_PR# H_EFER# H_RY# H_Y# H_R0# H_ERR# H_NT# H_LK# H_PURT# H_R#0 H_R# H_R# H_TRY# H_HT# H_HTM# VP_TL PRY# T0 H_PREQ# R0 hm H_TK R0 hm H_T R0 hm H_T R0 hm H_TM R0 hm H_TRT# R0 hm PU_R# T0 TPT H_PRHT_# PU_THRM_ PU_THRM_ PU_THRM_ PU_THRM_ PM_THRMTRP# LK_PU_LK LK_PU_LK# H_# H_NR# H_PR# H_EFER# H_RY# H_Y# H_R0# H_NT# H_LK# H_PURT# H_R#0 H_R# H_R# H_TRY# H_HT# H_HTM# T0 PM_THRMTRP#, LK_PU_LK LK_PU_LK# R0 hm R0.hm VP_TL VP_TL ± % pull-up to Vcc_0 f PRHT# is not used, then it must be terminated with a pull-up resistor to VP. f PRHT# is routed between PU, MVP and MH, pull-up resistor has to be hm ± % H_TN#0 H_TP#0 H_NV#0 H_# N H_# []# []# K H_# []# []# P H_# []# [0]# R H_#0 []# []# L H_# [0]# []# L H_# []# []# L H_# []# []# 0 M H_# []# []# E P H_# []# []# F P H_# []# []# P H_# []# []# E T VP_TL H_# []# []# R H_# []# [0]# E L H_#0 []# []# F T H_# [0]# []# F N R0 H_TN# []# []# F H_TN# M Khm H_TP# TN[]# TN[]# H_TP# N % H_NV# TP[]# TP[]# E H_NV# M NV[]# NV[]# 0 TL_REF TLREF MP[0] R <00 mil ( hm) M MP[] U T trace TET MP[] U 0 R R pace TET MP[] V 0.UF0V Khm Khm % R TET TET PRTP# E hm PLP# PU_EL0 PWR# PU_EL0 PU_EL EL[0] PWR PU_EL PU_EL EL[] LP# PU_EL EL[] P# E For eleron M (00)hange PU ocket into PN=00 LK F ELELEL0 MHz MHz L L H U0 H_#0 E H_# [0]# F H_# []# E H_# []# H H_# []# F H_# []# H_# []# E H_# []# E H_# []# K H_# []# H_#0 []# J H_# [0]# J H_# []# H H_# []# F H_# []# K H_# []# H H_TN#0 []# H H_TP#0 TN[0]# H_NV#0 TP[0]# J NV[0]# T RP 0 T RP []# []# []# V []# V []# W []# U []# U []# U [0]# []# W []# Y []# []# Y []# Y []# []# TN[]# W TP[]# Y NV[]# V T RP T RP H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_TN# H_TP# H_NV# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_TN# H_TP# H_NV# H_MP0 R0.hm % H_MP R.hm % H_MP R H_MP R.hm %.hm % H_PRTP# H_PLP# H_PWR# H_PWR H_PULP# PM_P# H_TN# H_TP# H_NV# H_TN# H_TP# H_NV# Layout Note: omp0, connect with Z0=. ohm, make trace length shorter than 0.". omp, connect with Z0=. ohm, make trace length shorter than 0.". omp[:0] at least mils away from any other toggling signal.. ohm connects with an ~mil wide trace to comp0.. ohm connect with mil-wide to comp H_PRTP#,0 H_PLP# H_PWR# H_PWR T0 H_PULP#, PM_P# 0 VP_TL JP0 HRT_PN. VP H_PRHT_# VP_TL R hm H_PRHT_# H_PWR VP_TL R hm VP VP_TL VP,,0, VP_TL,,, ULPHTeK MPUTER N. YNH PU () Horng hou ize Project Name Rev ustom TERE ate: Monday, February 0, 00 heet of.

3 eleron M F:MHz MN TYP MX V.0V.V.V 0.. h VRE (00)hange PU ocket into PN=00 VRE eleron M F:MHz MN TYP MX VP 0.V.0V.0V MN TYP MX P. Modity Table for eleron M U0 V[] V[] 0 V[] V[] 0 V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] 0 V[] V[] V[0] V[] V[] V[] 0 V[] V[] 0 V[] V[0] V[] V[] V[] V[] V[] V[] V.V V[] V[] 0 V[] V[] E JP0 V[] V[] E0 0 V[0] V[] E V[] V[] E MM_PEN_ML V[] V[] E V[] V[0] E V[] V[] E V[] V[] E0 V[] V[] F 0 V[] V[] F0 V[] V[] F V[] V[] F V[0] V[] F V[] V[] F VP_TL V[] V[] F E V[] V[00] F0 E V[] E0 V[] VP[] V E V[] VP[] RN0 E V[] VP[] J E V[] VP[] K E V[] VP[] M E V[0] VP[] J E0 V[] VP[] K F V V[] VP[] M 0m 0mil F V[] VP[] N F0 V[] VP[0] N lose to Pin F V[] VP[] R F V[] VP[] R F V[] VP[] T 0 F V[] VP[] T F V[] VP[] V 0UF0V 0.0UFV F0 V[0] VP[] W V[] checklist suggests V[] V 0uF PP 0 V[] V[] H_V0 RN0 V[] V[0] VR_V0 0 H_V RN0 V[] V[] F VR_V 0 H_V RN0 V[] V[] E VR_V 0 H_V RN0 V[] V[] F VR_V 0 0 H_V V[] V[] E RN0 VR_V 0 H_V V[0] V[] F RN0 VR_V 0 0 H_V RN0 V[] V[] E VR_V 0 0 V[] R0 V[] VENE V[] VENE F VRE V[] 0 V[] VENE 0 VENE V[] VENE E VENE 0 R0 0 U0 V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] E V[] E V[] E V[] E V[] E V[] E V[0] E V[] E V[] E V[] F V[] F V[] F V[] F V[] F V[] F V[] F V[0] F V[] F V[] V[] V[] V[] V[] H V[] H V[] H V[] H V[0] J V[] J V[] J V[] J V[] K V[] K V[] K V[] K V[] L V[] L V[0] L V[] L V[] M V[] M V[] M V[] M V[] N V[] N V[] N V[] N V[0] P V[] V[] P V[] P V[] P V[] R V[] R V[] R V[] R V[] T V[0] T V[] T V[] T V[] U V[] U V[] U V[] U V[] V V[] V V[] V V[00] V V[0] W V[0] W V[0] W V[0] W V[0] Y V[0] Y V[0] Y V[0] Y V[0] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] E V[] E V[] E V[] E V[] E V[0] E V[] E V[] E V[] E V[] F V[] F V[] F V[] F V[] F V[] F V[0] F V[] F V[] F (00)hange PU ocket into PN=00 VRE ---PWR comp Place the cap on North of econdary side E0 0UFV VP_TL VRE.V (00)hange UF into 0UF Place these upper side inside socket cavity on L Place these lower side inside socket cavity on L Place these upper side inside socket cavity on L 0UF0V Place these lower side inside socket cavity on L 0 0UF0V 0 0UF0V 0UF0V 0UF0V 0 0UF0V 0UF0V 0 0UF0V 0 0UF0V 0 0UF0V 0UF0V 0UF0V (0)hange into 0UF0V PN:0 0,0,0,,,,,0,, 0 0UF0V 0 0UF0V 0UF0V 0UF0V VP_TL,,, VRE 0.V,,0,0,,,, Vcc ore ecoupling aps Primary side => ottom side econdary side => Top side 0 0UF0V 0UF0V 0 0UF0V 0UF0V VP_TL.0V ecoupling apacitor Place near PU c00 c00 c00 c00 c00 c00 E0 0.UF0V 0.UF0V 0.UF0V 0.UF0V 0.UF0V 0.UF0V 00UF.V Layout Note: VENEVENE lines between the PU and the VR should have a trace width of mils on mils spacing, with trace impedance of Zo=. hm. The VENEVENE should be length matched to within mils. These resistors should be placed within inch of the PU. ULPHTeK MPUTER N. Yonah PU () Horng hou ize Project Name Rev ustom TERE ate: Monday, February 0, 00 heet of.

4 Fan peed ontrol V V V V,,0,,,,,0,,,,0, V,,,,,,,,,0,,,,,,,,0,,,0,,0,,0, V,,,,,0,,,, V K will issue a analog ( a voltage level ) signal. W: FN_ must be low during FN_PWM FN0_TH FN_PWM FN0_TH V R0 0Khm V R0 0Khm E0 00UF0V NW Unmount: E0 and 0 0UF0V New addition 0 00PF0V 0 0.UF0V Wto_N_P N N N0 (00)hange N0 into PN: PF0V T0 TPT V THERML PRTETN PLE UNER PU Route H_THERM and H_THERM on the same layer THER NL mils =============== 0 mils =========H_THERM(0 mils) 0 mils =========H_THERM(0 mils) 0 mils ========= mils THER NL void P,Power 0 THRM_PU# 0.0UF0V T0 TPT U0 N V U VUT PT0NR V_E R0 0Khm r00 R.Khm R TPT T0 V Q0 N00 R 00Khm 00Khm ( EREE ) FRE_FF#,,,,0 M_LK M_T V 0 ->, R need to be tuned (0)maybe R=.K hm(000) R R 00Khm 00Khm 00Khm V R0.Khm R (0)dd thermiters R0 r00 M_LK M_T MLERT# V_THM 0 0.UF0V c00 V_THM U0 LK V T LERT# - THERM# M0RMZ_REEL, PM_THRMTRP# MH_THRMTRP# (000)dd 0ohm resister tandby Mode: u(max. 0u) Full ctive: 0. m(max. m) (000) dd second sorce: 0000 PU_THRM_ PU_THRM_ R 0Khm R V_THM Q0 N00 R0 "-" 0 00PF0V "-" V Q0 TRP_R E PM0 E_RT_W#,,,,0 (000)dd R and Q0 to avoid error action R0 Mhm PU_THRM_ PU_THRM_ V VU_N_ 0 0.UF.V R0 0Khm r00 VU_N ULPHTeK MPUTER N. VU_N,, THER-ENR,FN ize Project Name Rev ustom Q0 N00 TERE Horng hou ate: Monday, February 0, 00 heet of.

5 VP_TL Request PE_REQ# PE_REQ# PE_REQ# PE_REQ# ontrol net PE0(#),PE(#) PE(#),PE(#) PE(#),PE(#) PE(#),PE(#), PE(#) Net name None None LK_PE_MNR(#) LK_MH_PLL(#) R0 Khm R0 Khm R0 Khm R0 Khm PU_EL0 PU_EL PU_EL R0 R0 R0 V MH_EL0 MH_EL MH_EL FL FL FL clk F EL EL L L L H EL0 H H V_LK VP_TL V VP_TL,,, V,,,,,,,,,0,,,,,,,,0,,,0,,0,,0, UF0V 0.UF0V Pin is PWRVE# L0 V_LK 00Mhz L0 00Mhz UF0V 0.UF0V 0.UF0V 0.UF0V 0.UF0V V_VP UF0V 0.UF0V 0UF0V Layout Note: Place termination close to source LK_MH_LK LK_MH_LK# LK_PU_LK LK_PU_LK# R0.hm r00 R0.hm r00 R0.hm r00 R.hm r00 ELPE0_L#: 0-->pin,pin=LLK(MHz) or MM_ ELL_#PLK_F: -->pin,pin=llk(mhz) PLKREQ_EL: -->pin0,pin=preq#,preq# TP_ENPLK_F0: -->PU_TP pair LK_PE_H R.hm R 0.UF0V 0UF0V r00.hm R LK_PE_H# R.hm V_LK U0 hm r00 LK_MH_PLL R.hm R r00 V_V LK_MH_PLL# -0ppm0PF V R VPEX.hm r00.hm VPEX V_VREF X0 VPEX VREF LK_L_ R.hm.Mhz 0UF0V 0.UF0V TP_P# r00 V PPEX_TP# 0.UF0V TP_P# LK_L_# R.hm (000)hange 0 TP_PU# VPU PU_TP# r00 TP_PU#,0 from PF to PF PF0V PF0V V_V LK_UM_M R V.hm LK_PU PULKT R hm r00 LK_PU_LK LK_PU# LK_UM_M# R LK_PU_LK#.hm PULK R hm r00 _X LK_MH LK_MH_LK PULKT0 R X hm LK_MH# LK_PE_MNR LK_MH_LK# _X PULK0 R hm R.hm r00 X LK_PE_MNR# L_ PULKT_TPPEXT R.hm R0 LK_L_ hm R 0Khm FXL_TPEX0T PULK_TPPEX r00 V R L_# PEREQ# LK_PE_NEWR LK_L_# hm L_PEX0 PEREQ#PEXT R R LK_NEWR_REQ#.hm PEREQ# F PEREQ#PEX 0 R 0Khm r00 R LK_PE_NEWR# LK_U hm R R PE PU_EL0.Khm FLU_MHz.hm PEXT R hm r00 LK_PE_NEWR PE# PU_EL FLTET_ME PEX R hm LK_PE_NEWR# LK_PE_T R.hm r00 PLK PEXT R LK_PE_T# R LK_LN_P hm.hm R0 0Khm ELPEX0_L#PLK PEX r00 R PLK PE LK_P hm PLK PEXT 0 R hm LK_MH_PLL PE# R hm LK_MH_PLL# R PLK LK_FWHP hm PEX PLK elete LK_TPMP(connect to pin) PE LK_PE_MNR PREQ# PLK PEXT R hm R PE# LK_EP hm PLKREQ_EL PEX R hm LK_PE_MNR# R V_LK 0Khm 0=PEX 0 Not ontrolled PE R hm LK_PE_H R0 PE# V_LK 0Khm PEXT ELL_#PLK_F PEX R hm LK_PE_H# =PEX 0 ontrolled R PLK_F0 LK_HP hm TP_ENPLK_F0 PEXT R V_LK 0Khm PEX 0 PREQ#,,,, M_LK_ LK LK_T TLKT R hm LK_PE_T 0=PEX Not ontrolled LK_T#,,,, M_T_ T TLK R hm LK_PE_T# =PEX ontrolled _REF T R hm REF TT_MHz LK_UM_M T# R hm T_MHz LK_UM_M# PREQ# R V_LK 0=PEX Not ontrolled hm =PEX ontrolled MH_LK_REQ# PEREQ# internal R0 pull high 0Khm LK_MNR_REQ# PEREQ# Remove 0ohm Vtt_Pwrd#P 0 LK_EN# 0 0PF0V 0PF0V 0 0PF0V 0PF0V 0PF0V 0PF0V Realtek:Mount R,Remove R0 R 0LFT VP VP nternal Pull-Up Resistor nternal Pull-own Resistor REFFLTET_EL REF0 0 REF REF0 R.Khm R hm PU_EL LK_H ULPHTeK MPUTER N. ize Project Name Rev ustom PREQ# 0=PEX Not ontrolled =PEX ontrolled TERE LK EN Horng hou ate: Monday, February 0, 00 heet of.

6 H_#[0..] H_#[..] LK_MH_LK LK_MH_LK# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_XRMP H_XMP H_XWN H_YRMP H_YMP H_YWN LK_MH_LK LK_MH_LK# U0 F H_#_0 J H_#_ H H_#_ J H_#_ H H_#_ K H_#_ H_#_ H_#_ K H_#_ K H_#_ K H_#_0 J H_#_ H H_#_ J H_#_ K H_#_ H_#_ T0 H_#_ W H_#_ T H_#_ U H_#_ U H_#_0 U H_#_ T H_#_ W H_#_ T H_#_ T H_#_ T H_#_ W H_#_ U H_#_ T H_#_ W H_#_0 T H_#_ H_#_ H_#_ W H_#_ W H_#_ Y H_#_ Y H_#_ W H_#_ Y0 H_#_ H_#_0 W H_#_ H_#_ H_#_ H_#_ H_#_ 0 H_#_ Y H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 0 H_#_ H_#_ H_#_ E E E Y U W H_XRMP H_XMP H_XWN H_YRMP H_YMP H_YWN H_LKN H_LKN# LT_Q H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_# H_T#_0 H_T#_ H_VREF H_NR# H_PR# H_REQ#0 H_PURT# H_Y# H_EFER# H_PWR# H_RY# H_VREF H_NV#_0 H_NV#_ H_NV#_ H_NV#_ H_TN#_0 H_TN#_ H_TN#_ H_TN#_ H_TP#_0 H_TP#_ H_TP#_ H_TP#_ H_HT# H_HTM# H_LK# H_REQ#_0 H_REQ#_ H_REQ#_ H_REQ#_ H_REQ#_ H_R#_0 H_R#_ H_R#_ H_LPPU# H_TRY# H E F F H J J H J F E F E J F J H K J W U 0 K T Y K T F E E E H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_T#0 H_T# H_VREF H_NR# H_PR# H_R0# H_PURT# H_Y# H_EFER# H_PWR# H_RY# H_NV#0 H_NV# H_NV# H_NV# H_TN#0 H_TN# H_TN# H_TN# H_TP#0 H_TP# H_TP# H_TP# H_HT# H_HTM# H_LK# H_REQ#0 H_REQ# H_REQ# H_REQ# H_REQ# H_R#0 H_R# H_R# N_PULP# H_TRY# H_# H_T#0 H_T# H_NR# H_PR# H_R0# H_PURT# H_Y# H_EFER# H_PWR# H_RY# H_NV#0 H_NV# H_NV# H_NV# H_TN#0 H_TN# H_TN# H_TN# H_TP#0 H_TP# H_TP# H_TP# H_HT# H_HTM# H_LK# R VP_TL H_REQ#[..0] H_R#[0..] H_PULP#, H_TRY# R0 0 % R0 0 % 0 0.UF0V Layout Note: 0.uF should be placed 00mils or less from MH pin. VP VP VP R0.hm % H_XMP H_XRMP R0.hm % R0 hm % R0 0 % R0 hm % R0 0 %.0 mils 00mils H_XWN 0 0.UF0V H_YWN 0 0.UF0V VP VP VP_TL H_YMP H_YRMP ignal voltage level = 0.*VP Trace should be 0 mil wide with 0 mil spacing ULPHTeK MPUTER N. VP,,0, VP_TL,,, alistoga MH () ize Project Name Rev ustom R0.hm % R0.hm % 00mils TERE Horng hou ate: Monday, February 0, 00 heet of.

7 V L_KLTTL R0 0Khm R0 0Khm R0 0Khm R0 0Khm L_KLTEN T0 Remove LV channel R0 R R R0.Khm % R0 00Khm % % % U0 L_KLTTL L_KLTEN L_KLTTL J0 L_TL_LK L_KLTEN H0 L_TL_T L_LK_TL H E_LK L_T_TL E_T L LK L_ L T L_V L_ L_VEN L_V F L_VREFH L_VEN L_VREFL L_VREFH L_VREFL LV_LLKN LV_LLKP L_LK# L_LK E L_LK# E L_LK LV_L0N LV_LN LV_LN LV_L0P LV_LP LV_LP RT_LUE RT_REEN RT_RE RT LK RT T RT LK _HYN_M RT T RT_HYN J _VYN_M RT_REF H RT_VYN R hm % RT_REF L_T#_0 L_T#_ L_T#_ L_T_0 L_T_ L_T_ 0 L_T#_0 0 L_T#_ F L_T#_ F0 L_T_0 L_T_ F L_T_.V TV UT TV UT TV UT J0 TV_REF TV_RTN TV_RTN TV_RTN TV UT disable way E RT_LUE RT_LUE# RT_REEN RT_REEN# RT_RE RT_RE# LT_Q EXP MP EXP MP EXP RXN_0 EXP RXN_ EXP RXN_ EXP RXN_ EXP RXN_ EXP RXN_ EXP RXN_ EXP RXN_ EXP RXN_ EXP RXN_ EXP RXN_0 EXP RXN_ EXP RXN_ EXP RXN_ EXP RXN_ EXP RXN_ EXP RXP_0 EXP RXP_ EXP RXP_ EXP RXP_ EXP RXP_ EXP RXP_ EXP RXP_ EXP RXP_ EXP RXP_ EXP RXP_ EXP RXP_0 EXP RXP_ EXP RXP_ EXP RXP_ EXP RXP_ EXP RXP_ EXP TXN_0 EXP TXN_ EXP TXN_ EXP TXN_ EXP TXN_ EXP TXN_ EXP TXN_ EXP TXN_ EXP TXN_ EXP TXN_ EXP TXN_0 EXP TXN_ EXP TXN_ EXP TXN_ EXP TXN_ EXP TXN_ EXP TXP_0 EXP TXP_ EXP TXP_ EXP TXP_ EXP TXP_ EXP TXP_ EXP TXP_ EXP TXP_ EXP TXP_ EXP TXP_ EXP TXP_0 EXP TXP_ EXP TXP_ EXP TXP_ EXP TXP_ EXP TXP_ R0 0 EXP MP F H J L M N P R T V W Y F H J L M N P R T V W Y F 0 H J0 L M0 N P0 R T0 V W0 Y 0 0 F0 H0 J L0 M N0 P R0 T V0 W Y0 0.hm %.V_PE V R0 0Khm R0 0Khm MH_EL0 MH_EL MH_EL MH_F_ MH_F_ MH_F_ MH_F_ MH_F_ MH_F_ MH_F_ MH_H_YN# MH_LK_REQ# PM_EXTT#0 PM_EXTT# MH_EL0 K MH_EL K MH_EL J T0 MH_F_ F T0 MH_F_ E MH_F_ F T0 MH_F_ E MH_F_ T0 MH_F_ MH_F_ T0 MH_F_0 E MH_F_ T0 MH_F_ T0 MH_F_ K T0 MH_F_ T0 MH_F_ H MH_F_ T MH_F_ H MH_F_ J MH_F_ K T MH_F_0 J MH_H_YN# MH_LK_REQ# U0 T RV_ R RV_ F RV_ F RV_ RV_ F RV_ H RV_ J RV_ K0 TV_NEL_0 J TV_NEL_ RV_ RV_ RV_ RV_ RV_ F_0 F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 PM_MUY# PM_MUY# PM_EXTT#0 PM_MUY# F R PM_EXTT# PM_EXTT#_0,0 PM_PRLPVR H PM_THRMTRP# PM_EXTT#_ MH_THRMTRP# H_PWRK PM_THRMTRP#, H_PWRK H PWRK H RT_N#_MH RTN#,,,,, PLT_RT# H V_TRLLK H V_TRLT K H_YN# H LK_REQ# N0 N N N 0 N N N N N N N0 Y N Y N W N W N 0 N N N N LT_Q V M_VREF_MH.V.V_PE.V M_K_0 M_K_ M_K_ M_K_ M_K#_0 M_K#_ M_K#_ M_K#_ M_KE_0 M_KE_ M_KE_ M_KE_ M_#_0 M_#_ M_#_ M_#_ M_MP_0 M_MP_ M_T_0 M_T_ M_T_ M_T_ M_RMP# M_RMP M_VREF_0 M_VREF LKN# _LKN _REFLKN# _REFLKN _REFLKN# _REFLKN M_RXN_0 M_RXN_ M_RXN_ M_RXN_ M_RXP_0 M_RXP_ M_RXP_ M_RXP_ M_TXN_0 M_TXN_ M_TXN_ M_TXN_ M_TXP_0 M_TXP_ M_TXP_ M_TXP_ V,,,,,,,,,0,,,,,,,,0,,,0,,0,,0, M_VREF_MH,,.V,0,0,,,,.V_PE.V 0,,,,, Y M_LK_R0 R M_LK_R W M_LK_R W0 M_LK_R W M_LK_R#0 T M_LK_R# Y M_LK_R# Y0 M_LK_R# U0 M_KE0 T0 M_KE M_KE Y M_KE W M_#0 W M_# Y M_# W M_# L0 F0 M_MP0 M_MP M_T0 M_T Y0 M_T U M_T V T K K M_RMP# M_RMP M_VREF_MH F LK_MH_PLL# LK_MH_PLL LK_UM_M# LK_UM_M 0 LK_L_# LK_L_ E M_TXN0 F M_TXN M_TXN H M_TXN M_TXP0 E M_TXP F M_TXP M_TXP E M_RXN0 F M_RXN M_RXN H M_RXN M_RXP0 E M_RXP F M_RXP M_RXP M_LK_R0 M_LK_R M_LK_R M_LK_R M_LK_R#0 M_LK_R# M_LK_R# M_LK_R# Layout Note: Route as short as possible R 0.hm R 0.hm.V R 0.hm % R 0.hm % LK_MH_PLL# LK_MH_PLL LK_UM_M# LK_UM_M LK_L_# LK_L_ M_TXN[0..] M_TXP[0..] M_RXN[0..] M_RXP[0..] M_KE[0..],, M_#[0..],, M_T[0..],, LV_L0N LV_LN LV_LN LV_L0P LV_LP LV_LP LV_L0N LV_LN LV_LN LV_L0P LV_LP LV_LP LV_LLKN LV_LLKP L_KLTEN E_LK E_T L_VEN LV_LLKN LV_LLKP L_KLTEN E_LK E_T L_VEN RT_RE RT_REEN RT_LUE _HYN_M _VYN_M RT LK RT T RT_RE RT_REEN RT_LUE RT LK RT T (00)dd ohm resisters R hm _VYN_M R hm _HYN_M _VYN_UF _HYN_UF ULPHTeK MPUTER N. alistoga P-E () Horng hou ize Project Name Rev ustom TERE ate: Monday, February 0, 00 heet of.

8 M Q M Q0 M M M Q M Q M Q# M Q M Q M Q M Q M Q0 M M Q M Q M Q M Q M Q M Q0 M Q M M M M Q M Q M Q M M M Q M M Q M M M0 M Q#0 M Q M Q M Q M Q M Q M M 0 M Q M M M WE# M M Q M Q M Q M Q M Q# M Q M Q# M Q M Q M M M Q M Q M Q M Q M Q0 M 0 M M M Q M M M Q M Q M M M Q M R# M Q# M Q M Q M Q M Q M Q M Q M Q M Q M Q# M Q M M Q M Q M Q M RVENUT# M M Q M Q# M M Q0 M Q0 M Q M Q M Q M Q M Q M Q# M Q M Q M Q M RVENN# M Q0 M M Q M # M #0 M # M # M M Q# M M M Q M Q M Q M Q M Q M Q M Q M Q M Q M M M M Q# M Q# M Q M Q M Q0 M Q M WE# M RVENN# M 0 M Q M M M Q M Q M Q M Q M Q0 M M Q# M Q M Q M Q M Q M Q M M M Q# M M0 M # M # M #0 M Q M Q M Q M RVENUT# M M Q# M Q M # M Q M Q M M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M M M Q0 M Q M Q M Q M 0 M Q M Q M Q M R# M M Q0 M Q M Q M Q M Q0 M Q# M Q M Q M Q M Q M Q M Q#0 M M M M M M M Q0 M Q M Q0 M Q M M Q M Q M M M M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M WE#, M M[0..] M R#, M R#, M #, M, M 0, M WE#, M, M, M 0, M, M #, M Q[0..] M Q[0..] M Q#[0..] M Q[0..] M Q[0..] M [0..], M M[0..] M Q#[0..] M [0..], ize Project Name Rev ate: heet of ustom Monday, February 0, 00 ULPHTeK MPUTER N. alistoga R (). TERE Horng hou ize Project Name Rev ate: heet of ustom Monday, February 0, 00 ULPHTeK MPUTER N. alistoga R (). TERE Horng hou ize Project Name Rev ate: heet of ustom Monday, February 0, 00 ULPHTeK MPUTER N. alistoga R (). TERE Horng hou _Q0 K _Q J _Q P _Q R _Q J _Q K _Q N _Q P _Q T0 _Q V _Q0 U _Q V _Q P _Q R0 _Q W _Q Y _Q _Q V _Q R _Q P _Q0 _Q U _Q P _Q P _Q Y _Q _Q T _Q U _Q U _Q W _Q0 V _Q W _Q M _Q L _Q P _Q N _Q N _Q M _Q P _Q L _Q0 J _Q H0 _Q J _Q N0 _Q K _Q H _Q K0 _Q J _Q 0 _Q W0 _Q0 _Q W _Q Y0 _Q Y _Q W _Q Y _Q V _Q R _Q K _Q K _Q0 T _Q K _Q J _Q J 0 T V Y _# R _M_0 K _M_ R _M_ T _M M_ L _M_ H _M M_ N _Q_0 M _Q_ T _Q_ U _Q_ R _Q_ R _Q_ R0 _Q_ R _Q_ N _Q#_0 M0 _Q#_ U _Q#_ T _Q#_ P _Q#_ P _Q#_ T0 _Q#_ T _Q#_ P _M_0 Y _M_ W _M_ Y _M_ R _M_ T _M_ T _M_ U _M_ V _M_ V _M_ W _M_0 V _M M_ Y _M_ R _R# U _RVENN# K _RVENUT# K _WE# R U0E LT_Q U0E LT_Q _Q0 J _Q J _Q M _Q M _Q J _Q K _Q J _Q H _Q N _Q P _Q0 R _Q P _Q N _Q M _Q M _Q N _Q K _Q L _Q M _Q N _Q0 K _Q L _Q M _Q P _Q P _Q L _Q P _Q N0 _Q L _Q P _Q0 P0 _Q T _Q R _Q R _Q P _Q P _Q T _Q T _Q L _Q L _Q0 K _Q N _Q K _Q K _Q P _Q N _Q T _Q L _Q Y _Q W _Q0 P _Q N _Q V _Q T _Q N _Q L _Q _Q F _Q _Q F _Q0 _Q H _Q F _Q F 0 U V 0 _# Y _M_0 J _M_ M _M_ L _M_ N _M_ M _M_ L _M_ R _M_ H _Q_0 K _Q_ T _Q_ N _Q_ M _Q_ N _Q_ N _Q_ P _Q Q#_0 K _Q#_ U _Q#_ N _Q#_ M _Q#_ M _Q#_ L _Q#_ N _Q#_ H _M_0 Y _M_ U _M_ W _M M M_ U _M_ V _M_ U _M_ W _M_ T _M_0 U _M_ T _M_ V0 _M_ V _R# W _RVENN# K _RVENUT# K _WE# Y U0 LT_Q U0 LT_Q T0 T0 T0 T0 T0 T0 T0 T0

9 Layout Note: Place filter components.v close to MH.V_PE Layout Note: L0 aps should be on Top layer 00Mhz E0 0 0 V 0UFV 0UF0V 0UF0V.V L0 00Mhz.V_VUX L0 00Mhz VUX (00) E m 0UF=>0UF 0UFV 0.UF0V L0 00Mhz L0 00Mhz L0 00Mhz L0 00Mhz V_YN Pin H VP_MH_R (00), :unmount 0.UF0V R0 0 m L0 00Mhz V_LV Pin 0 m V_RT Pin E F 0 0.UF0V E0 0UF.V E0 0UF.V UF.V UF.V 0 0.0UFV 0 0UF0V 0.UF0V 0.UF0V.V_PLL V_PLL.V_PLL V_PLL 0 m.v_pll V_PLL 0 m.v_hpll V_HPLL m.v_mpll V_MPLL 0.UF0V m 0.0UFV 0.UF0V 0.UF0V 0 T 0.UF0V V_ Pin m.v_rt 00 m VP_MH.V V_LV 0 m Pin.V V_TV Pin.V V_QTV H Layout Note: 0.uF caps in.v_xpll need to be located as edge caps within 00 mils. 0.UF0V Layout Note: These aps should be within 0 mils of edge of MH 0 0.UF0V 0UF0V MH VRE VP VP_MH.0V JP0 00 m VP HRT_PN JP0 0.0UFV 0.UF0V 0 0.0UFV 0.UF0V VTX_LV 0 m Pin m Layout Note: These aps should be within 0 mils of edge of MH 0.UF0V.UF0V.V_RT V V_HV 0 m Pin HRT_PN 0UF0V.V_VUX.V_PLL.V.V V.V.V_PLL.V_PLL.V_HPLL.V_MPLL.V.V_PE.V TV UT disable way.v.v.v Layout Note: These 0.uF caps should be placed within 00 mils of edge 0.UF0V.V U0H H VYN 0 V_TXLV0 0 V_TXLV 0 V_TXLV J V0 V Y V V V R V N V L V V_PLL V_ H V_ F V_RT0 E V_RT V_RT V_PLL V_PLL F V_HPLL V_LV V_LV F V_MPLL H0 V_TV 0 V_TV E V_TV0 F V_TV 0 V_TV0 0 V_TV E0 V_TV0 F0 V_TV H V_HMPLL0 H V_HMPLL V_LV0 V_LV V_LV V_TV V_HV0 V_HV V_HV H V_QTV K VUX0 F VUX E VUX VUX L0 VUX K0 VUX J0 VUX H0 VUX 0 VUX F0 VUX E0 VUX0 0 VUX 0 VUX VUX F VUX E VUX VUX VUX VUX F VUX E VUX0 H VUX J VUX H VUX J0 VUX H0 VUX H VUX P VUX P VUX H VUX P VUX0 H VUX VUX F VUX E VUX Y VUX F VUX E VUX F VUX E VUX VUX0 LT_Q VP_TL VP_MH.V_PE V.V.V VTT_0 VTT_ VTT_ W VTT_ V VTT_ T VTT_ R VTT_ P VTT_ N VTT_ M VTT_ L VTT_0 VTT_ VTT_ VTT_ VTT_ Y VTT_ W VTT_ V VTT_ U VTT_ T VTT_ R VTT_0 N VTT_ M VTT_ L VTT_ VTT_ VTT_ Y VTT_ W VTT_ V VTT_ U VTT_ T VTT_0 R VTT_ P VTT_ N VTT_ M VTT_ L VTT_ R VTT_ P VTT_ N VTT_ M VTT_ R0 VTT_0 P0 VTT_ N0 VTT_ M0 VTT_ P VTT_ N VTT_ M VTT_ R VTT_ P VTT_ N VTT_ M VTT_0 P VTT_ N VTT_ M VTT_ R VTT_ P VTT_ M VTT_ VTT_ R VTT_ P VTT_ N VTT_0 M VTT_ P VTT_ N VTT_ M VTT_ R VTT_ P VTT_ N VTT_ M VTT_ R VTT_ P VTT_0 M VTT_ VTT_ VTT_ R VTT_ P VTT_ N VTT_ M VP_TL VTTLF_P 0.UFV VTTLF_P VTTLF_P 0.UFV VP_TL,,, VP_MH 0.V_PE V,,,,,,,,,0,,,,,,,,0,,,0,,0,,0,.V,.V,0,0,,,, VP_TL Layout Note: Place in cavity NTE:0.UF P UE N.V,.V.V should be placed within 00 mils of edge. 00 m 0 0.UF0V.UF.V 0.UF.V 0 0.UF.V Remove TV UT Power ULPHTeK MPUTER N. alistoga Power () ize Project Name Rev ustom Layout Note: Place on the edge E0 00UF.V TERE (00) change into 00 Horng hou ate: Monday, February 0, 00 heet of.

10 V_M_ V_M_ V_M_ V_M_ V_M_ V_M_.V,,0,,,,.V,,,,, VP_MH.V.V VP_MH VP_MH.V.V VP_MH VP_MH.V ize Project Name Rev ate: heet of ustom 0 Monday, February 0, 00 ULPHTeK MPUTER N. listoga (). TERE Horng hou ize Project Name Rev ate: heet of ustom 0 Monday, February 0, 00 ULPHTeK MPUTER N. listoga (). TERE Horng hou ize Project Name Rev ate: heet of ustom 0 Monday, February 0, 00 ULPHTeK MPUTER N. listoga (). TERE Horng hou V(MH ore) 00 m.v (00 m) or.0v (00 m) Layout Note: Place in cavity 00 0.UFV 00 0.UFV 00 0UF0V 00 0UF0V 00 0.UFV 00 0.UFV V_0 T V_ N V_ M V_ H V_ V_ W V_ K V_ J V_ F V_ V_0 V_ K V_ V_ F V_ E V_ V_ V_ V_ V V_ R V_00 N V_0 L V_0 V_0 Y V_0 P V_0 K V_0 J V_0 H V_0 V_0 W0 V_0 R0 V_ M0 V_ 0 V_ K0 V_ 0 V_ 0 V_ N V_ V_ W V_ K V_0 V_ V_ H V_ P V_ H V_ V_ V_ Y V_ R V_ P V_0 M V_ K V_ V V_ N V_ L V_ J V_ F V_ V_ N V_ M V_0 K V_ N V_ M V_ L V_ V_ V_ V_ T V_ K V_ V_0 V_ U V_ K V_ H V_ E V_ V V_ R V_ N V_ M V_ L V_0 V_ P V_ F V_ V_ V_ Y V_ V_ K V_ H V_ E V_0 V_ V_ Y V_ J V_ V_ V_ V0 V_ P0 V_ L0 V_ J0 V_0 0 V_ 0 V_ W0 V_ U0 V_ V_ W V_ R V_ H V_ V_ Y V_0 R V_ V_ E V_ V_ V_ V_ V_ U V_ K V_ V_00 V_0 V V_0 P V_0 L V_0 J V_0 H V_0 F V_0 V_0 R V_0 V_0 V_ V_ V_ V_ Y V_ U V_ N V_ K V_ H V_ V_0 V V_ F V_ V_ Y V_ R V_ P V_ L V_ J V_ Y V_ U V_0 R V_ J V_ F V_ V_ Y V_ W V_ V V_ L V_ H V_ V_0 F V_ V_ V_ V_ V_ T V_ R V_ P V_ K V_ J V_0 V_ V_ Y V_ U V_ T V_ N V_ J V_ H V_ F V_ V_0 L U0J LT_Q U0J LT_Q 00 0.UFV 00 0.UFV 00 0UF0V 00 0UF0V E00 0uFV E00 0uFV V_NTF0 V_NTF V_NTF V_NTF V_NTF Y V_NTF W V_NTF V V_NTF U V_NTF T V_NTF R V_NTF0 V_NTF V_NTF V_NTF V_NTF Y V_NTF W V_NTF V V_NTF U V_NTF T V_NTF R V_NTF0 V_NTF V_NTF V_NTF V_NTF Y V_NTF W V_NTF V V_NTF U V_NTF T V_NTF R V_NTF0 V_NTF V_NTF V_NTF V_NTF Y V_NTF W V_NTF V V_NTF U V_NTF T V_NTF R V_NTF0 V_NTF V V_NTF U V_NTF T V_NTF R V_NTF V_NTF V V_NTF U V_NTF T V_NTF R V_NTF0 V_NTF V V_NTF U V_NTF T V_NTF R V_NTF 0 V_NTF V0 V_NTF U0 V_NTF T0 V_NTF R0 V_NTF0 V_NTF V V_NTF U V_NTF T V_NTF V_NTF V_NTF V_NTF V_NTF Y V_NTF W V_NTF0 V V_NTF U V_NTF T V_NTF0 E V_NTF E V_NTF E V_NTF E V_NTF E V_NTF E V_NTF E V_NTF E0 V_NTF E V_NTF E V_NTF0 V_NTF Y V_NTF U VUX_NTF0 VUX_NTF F VUX_NTF VUX_NTF F VUX_NTF VUX_NTF F VUX_NTF VUX_NTF F VUX_NTF VUX_NTF F VUX_NTF0 VUX_NTF F VUX_NTF VUX_NTF F VUX_NTF 0 VUX_NTF F0 VUX_NTF VUX_NTF F VUX_NTF R VUX_NTF VUX_NTF0 F VUX_NTF R VUX_NTF VUX_NTF F VUX_NTF E VUX_NTF VUX_NTF VUX_NTF VUX_NTF W VUX_NTF V VUX_NTF0 T VUX_NTF R VUX_NTF VUX_NTF F VUX_NTF E VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF Y VUX_NTF0 W VUX_NTF V VUX_NTF U VUX_NTF T VUX_NTF R VUX_NTF VUX_NTF F VUX_NTF E VUX_NTF VUX_NTF VUX_NTF0 VUX_NTF VUX_NTF Y VUX_NTF W VUX_NTF V VUX_NTF U VUX_NTF T VUX_NTF R U0 LT_Q U0 LT_Q E00 0uFV E00 0uFV 0 0.UFV 0 0.UFV 00 0UF0V 00 0UF0V 0 0.UF.V 0 0.UF.V 0 0.UFV 0 0.UFV E00 0UF.V E00 0UF.V 00 0.UFV 00 0.UFV 0 0UF0V 0 0UF0V E00 0UFV N E00 0UFV N 00 0.UF.V 00 0.UF.V V_0 V_ W V_ P V_ N V_ L V_ J V_ V_ Y V_ W V_ V V_0 P V_ N V_ M V_ L V_ J V_ V_ W V_ V V_ T V_ R V_0 P V_ N V_ M V_ 0 V_ Y0 V_ W0 V_ V0 V_ U0 V_ T0 V_ R0 V_0 P0 V_ N0 V_ M0 V_ L0 V_ V_ Y V_ W V_ V V_ U V_ R V_0 P V_ M V_ L V_ V_ V_ Y V_ V V_ U V_ T V_ R V_0 P V_ N V_ M V_ L V_ P V_ N V_ M V_ L V_ P V_ N V_0 L V_ N V_ M V_ L V_ P V_ N V_ M V_ V_ V_ Y V_0 P V_ N V_ M V_ L V_ V_ V_ Y V_ W V_ P V_ N V_0 M V_ L V_ V_ V_ W V_ N V_ M V_ L V_ 0 V_ 0 V_0 Y0 V_ W0 V_ P0 V_ N0 V_ M0 V_ L0 V_ V_ V_ Y V_ N V_00 M V_0 L V_0 N V_0 M V_0 L V_0 P V_0 N V_0 M V_0 N V_0 M V_0 L V_M_0 U V_M_ T V_M_ M V_M_ U0 V_M_ V_M_ Y V_M_ W V_M_ V V_M_ U V_M_ T V_M_0 R V_M_ 0 V_M_ Y0 V_M_ W0 V_M_ V0 V_M_ U0 V_M_ T0 V_M_ R0 V_M_ P0 V_M_ N0 V_M_0 M0 V_M_ M V_M_ L V_M_ K V_M_ J V_M_ H V_M_ J V_M_ H V_M_ J V_M_ H V_M_0 V_M_ Y V_M_ W V_M_ V V_M_ U V_M_ T V_M_ R V_M_ J V_M_ H V_M_ J V_M_0 H V_M_ J V_M_ H V_M_ V_M_ J V_M_ V_M_ Y V_M_ W V_M_ V V_M_ U V_M_0 T V_M_ R V_M_ P V_M_ K V_M_ J V_M_ K V_M_ K0 V_M_ V_M_ Y V_M_ W V_M_0 V V_M_ U V_M_ T V_M_ R V_M_ P V_M_ K V_M_ J V_M_ J V_M_ J V_M_ H V_M_0 J V_M_ H V_M_ V_M_ Y V_M_ W V_M_ V V_M_ U V_M_ T V_M_ R V_M_ J V_M_0 J V_M_ J V_M_ H V_M_ K V_M_ J V_M_ H V_M_ V_M_ K V_M_ V_M_ Y V_M_0 W V_M_ V V_M_ T V_M_ R V_M_ P V_M_ V_M_ Y V_M_ W V_M_ V V_M_ T V_M_00 R V_M_0 P V_M_0 N V_M_0 L V_M_0 K V_M_0 J V_M_0 V V_M_0 J U0F LT_Q U0F LT_Q 00 UF0V 00 UF0V V_0 V_ V_ W V_ T V_ P V_ M V_ J V_ F V_ V0 V_ P0 V_0 N0 V_ K0 V_ J0 V_ H0 V_ 0 V_ F0 V_ E0 V_ 0 V_ Y V_ W V_0 V V_ R V_ N V_ J V_ V_ V_ V_ Y V_ W V_ V V_0 T V_ R V_ P V_ N V_ M V_ L V_ J V_ H V_ V_ F V_0 V_ T V_ M V_ H V_ V_ F V_ E V_ V_ K V_ H V_0 V_ V_ Y V_ W V_ V V_ T V_ R V_ P V_ N V_ M V_0 L V_ J V_ H V_ V_ F V_ V_ Y V_ W V_ N V_ H V_0 V_ F V_ E V_ V_ V_ V_ V_ V V_ R V_ H V_0 V_ V_ Y V_ W V_ V V_ T V_ R V_ P V_ N V_ M V_0 L V_ J V_ H V_ V_ F V_ V_ N V_ K V_ V_ F V_00 E V_0 V_0 V_0 W V_0 V V_0 R V_0 E V_0 V_0 Y V_0 V V_0 T V_ R V_ M V_ H V_ V_ F V_ V_ V_ H V_ V_0 F V_ E V_ V_ V_ V_ V_ Y V_ V V_ N V_ J V_0 V_ V_ Y V_ 0 V_ E0 V_ T V_ N V_ V_ T V_ N V_0 K V_ V_ E V_ V_ V_ V_ V_ W V_ U V_ P V_0 M V_ V_ V_ W V_ J V_ E V_ P V_ M V_ K V_ J V_0 V_ F V_ V_ V_ N V_ M V_ K V_ F V_ V_ K V_0 P V_ K V_ H V_ E V_ V_ V_ V_ U V_ L V_ W U0 LT_Q U0 LT_Q 00 0.UF.V 00 0.UF.V E00 0UF.V E00 0UF.V

11 MH_F_ R0.Khm r00_h F : M X elect LW = M X HH = M X (efault) MH_F_ R0.Khm r00_h F : F YNM T LW = ynamic T isabled HH = ynamic T Enabled (efault) MH_F_ R0.Khm r00_h F : PU TRP LW = Reserved HH = Mobility PU (efault) MH_F_ V R0 Khm r00 F : MH ore Voltage Level LW =.0V HH =.V (default) F[..] have internal pullup resistors. F[..] have internal pulldown resistors. VRTL_T has internal pulldown resistors. MH_F_ MH_F_ R0.Khm r00_h R0.Khm r00_h F : PE RPH LNE LW = REVERE LNE HH = NRML PERTN (efault) F : Reserved but need to be pull low MH_F_ V R0 Khm r00 F : M LNE REVERL LW = NRML HH = LNE REVERE (0)Remove.V power supply F :0 : :0 : : ll are sampled with respect to the leading edge of the MH PWRK 00 = F F Freq select 0 = F M X elect PU trap PE raphics Lane Reversal XRLLZ F ynamic T V_ TRLT V Present V select M Lane Reversal VPE 0 concurrent 0 = M X = M X (efault) 0 = Reserved = Mobile PU (efault) 0 = Reverse Lanes = Normal (efault) 00 = Partial lock ating isable 0 = XR Mode Enabled 0 = ll-z Mode Enabled = Normal operation (efault) 0 = ynamic T isabled = ynamic T Enabled (efault) 0 = No V ard Present (efault) = V ard Present 0 =.0V (efault) =.V 0 = Normal (efault) = Reverse Lanes 0 = nly V or PE x is operational(efault) = V and PE x are operating simultaneously via the PE port ULPHTeK MPUTER N. alistoga trapping Horng hou ize Project Name Rev ustom TERE ate: Monday, February 0, 00 heet of.

12 L Panel Power ~.V Full ctive: 0 m(max. 00 m) ~.V 0- M: 0 m(max. 00 m) V Remove M amera(u) V V 0 0 L_VEN Q0 N00 Q0 N00 R0 00Khm R0 00Khm R0 khm VL_ 0 UFV Q0 V L0 00Mhz VL 0 0.UF0V R0 V_L VL_ 0.UF0V 0.0UFV 0 0UF0V 0 UF0V 0 0.UF0V Q0 N00 L acklight ontrol L_KFF# When user push "FnF" button active this pin to turn nff backlight Refer to VJ (00)Mount R0 and Q0 nverter oard built in.w L Panel E NVTER_: E output signal ( adjust voltage level) to adjust backlight V _T_Y V L_KFF#,, P_RT# L_KLTEN L_W# L_KLTTL NVTER_ RHT_PWM L_KFF# P_RT# L_KLTEN L_W# L0 00Mhz L 00Mhz L 00Mhz 0 RF 0 RF L 00Mhz L_EN_L R0 0Khm r00 000PF0V 000PF0V 0.UFV UFV L0 Khm L0 l00_h 00Mhz L0 l00_h 00Mhz _NV 0.UF0V 000PF0V L_W#_N J_L_N L_EN_N V_N L0 00Mhz ombine nverter interface into LV interface (00,EM) dd bead V L0 00Mhz V_L L LV & NVERTER nterface elete LV channel Rearrange pin location(00) 0 0.UF c00 V_LV N0 WT_N_0P E E (00)hange N0 into PN:0000 E_LK_L E_T_L V_L LV_L0N LV_L0P LV_LN LV_LP LV_LN LV_LP LV_LLKN LV_LLKP 0 PF0V N c00 L0 hm 0 PF0V N c00 L0 hm E_LK E_T ULPHTeK MPUTER N. LV & NVERTER Horng hou ize Project Name Rev ustom TERE ate: Monday, February 0, 00 heet of.

13 RT UT New addition for Teresa RT_RE RT_RE R0 r00 (00,EM) dd L0, L0, L0 0 0PF0V L0 0NH checklist suggests ohm00mhz RT_R_N 0 0PF0V L0 00Mhz (000) Remove 0om resister V_RT F0 V (000) hange fuse into RT_REEN RT_REEN R0 r00 0PF0V L0 0NH RT N L0 00Mhz 0 0PF0V 0.UF0V hange -U into PN:00M N0 RT_LUE RT_LUE R0 r00 0 0PF0V L0 0NH RT N L0 00Mhz 0PF0V RT_R_N RT N RT N 0 _T_N HYN_N VYN_N _LK_N RT_HYN Q0 N00 R0 hm HYN_ HYN_N 0PF0V _U_P 00M V 0 V RT_RE V (0)Modify into V RT_VYN VYN_ R0 hm VYN_N V 0 NW V_RT V 0 V RT_REEN N00 Q0 0PF0V (00) Mount 0PF V_RT R0.Khm _ Remove idirectional Port(00) V 0 V RT_LUE RT T Q0 N00 _ R _T_N PF0V c00 V R0.Khm _ V 0 HYN_ V (0)Modify into V R.Khm R.Khm RT T RT LK V V 0 VYN_ RT LK N00 Q0 _ R _LK_N PF0V c00 V ULPHTeK MPUTER N. RT & TV UT Horng hou ize Project Name Rev ustom TERE ate: Monday, February 0, 00 heet of.

14 (0)hange N0 into PN:0000R M_LK_R0, M [0..] 0 PLE NER -MM_ 0PF0V M_LK_R#0 M_LK_R 0 PLE NER -MM_ 0PF0V M_LK_R#, M Mus lave ddress:0h, M 0, M, M_#0, M_# M_LK_R0 M_LK_R#0 M_LK_R M_LK_R#, M_KE0, M_KE, M #, M R#, M WE#,,,, M_LK_,,,, M_T_, M_T0, M_T M M[0..] M Q[0..] M Q#[0..] (0)hange N0 into PN:0000R N0 M 0 0 M Q0 M 0 Q0 0 M Q M Q 00 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M 0 Q 0 M Q M 0P Q0 0 M Q0 M Q M Q M Q 0 M Q Q M Q Q M Q Q M Q _ Q M Q Q 0 M Q 0 Q 0 M Q Q 0 M Q0 0# Q0 M Q # Q 0 M Q K0 Q M Q K0# Q M Q K Q M Q K# Q M Q KE0 Q 0 M Q KE Q M Q # Q 0 M Q R# Q 0 M Q0 WE# Q0 M Q 0 Q 00 M Q Q M Q L Q M Q Q M Q Q M Q T0 Q M Q T Q M Q M M0 Q 0 M Q M M M0 Q M Q0 M M M Q0 M Q M M M Q M Q M M M Q 0 M Q M M M Q M Q M M M Q 0 0 M Q M M M Q M Q M Q M Q M Q0 Q M Q M Q Q0 Q M Q M Q Q Q M Q0 M Q Q Q0 0 M Q M Q Q Q M Q M Q Q Q M Q M Q Q Q 0 M Q M Q Q Q M Q M Q#0 Q Q M Q0 M Q# Q#0 Q M Q M Q# Q# Q M Q M Q# Q# Q M Q M Q# Q# Q M Q M Q# Q# Q0 0 M Q M Q# Q# Q M Q M Q# Q# Q M Q Q# Q R_MM_00P WP WP WP WP WP WP M Q[0..] Layout Note: Place these aps near MM 0.V V V V V V V V V V V V V 0 0.UFV 0.UFV 0.UFV V V 0.UFV V V V V 0 0 V0 V V V V 0 V V V VP V V0 0 N V 0 N V 0.UFV 0 N V M_VREF_MH N V NTET V V 0 VREF V 0 V 0.UF.V 0 0 V 0 V0 0.UFV V 0 NP_N V 0 NP_N V V V V V V.V.V V V V V V V V V0 V V V V E0 E0 V V 0UFV 0UFV V0 V 0 V V V V 0 V V V V R_MM_00P.V 0 UF.V UF.V UF.V UF.V UF.V.V Layout Note: Place these aps near MM 0 N0.UF.V 0.UF.V.UF.V.UF.V.UF.V -MM 0 is placed farther from the MH than -MM ULPHTeK MPUTER N. R -MM0 Horng hou ize Project Name Rev ustom TERE ate: Monday, February 0, 00 heet of.

15 Mus lave ddress:h M_LK_R, M [0..] 0 PLE NER -MM_0 0PF0V M_LK_R# M_LK_R 0 PLE NER -MM_0 0PF0V M_LK_R#, M, M 0, M, M_#, M_# M_LK_R M_LK_R# M_LK_R M_LK_R#, M_KE, M_KE V, M # R0, M R#, M WE# 0Khm,,,, M_LK_,,,, M_T_, M_T, M_T M M[0..] M Q[0..] M Q#[0..] V_ET M 0 M M M M M M M M M M 0 M M M M M0 M M M M M M M M M M M M M M M Q0 M Q M Q M Q M Q M Q M Q M Q M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M Q[0..] (0)Update P footprint PN:0000 N P 0 _ # # 0 K0 K0# K K# KE0 0 KE # 0 R# 0 WE# 0 00 L T0 T 0 M0 M M M 0 M M 0 M M Q0 Q Q 0 Q Q Q Q Q Q#0 Q# Q# Q# Q# Q# Q# Q# R_MM_00P Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q 0 Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 0 Q Q Q M Q[0..] M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q WP WP WP ddress reference.v, add four 0.uF decoupling P. 0 0.UFV c00.v.v.v V.V M_VREF_MH 0 0 UF.V 0.UFV Layout Note: Place these aps near MM UFV UFV 0.UFV 0.UFV c00 c00 c UFV Layout Note: Place these aps near MM 0 0.UFV Layout Note: Place these High-Freq decoupling aps near the MH 0.UFV Layout Note: Place these Ps near the MH.UF.V 0.UFV 0.UFV c00.uf.v (0)Update P footprint PN:0000 N0 V V V V V V V V V V0 V V V V V V V V 0 0 V0 V V V 0 V V V VP V V0 N V 0 N V 0 N V N V NTET V V 0 VREF V V 0 0 V 0 V0 V 0 NP_N V 0 NP_N V V V V V V V V V V V V V V0 V V V V V V V0 V 0 V V V V 0 V V V V 0.UF.V R_MM_00P 0.UFV 0.UFV 0.UFV c00 c00 c00.uf.v.uf.v ULPHTeK MPUTER N. R -MM Horng hou ize Project Name Rev ustom TERE ate: Monday, February 0, 00 heet of.

16 0.V M [0..], M_VREF_MH 0.V M_VREF_MH,, 0.V, M [0..], RN0 hm RN0 hm RN0 hm RN0 hm RN0E hm RN0F hm 0 RN0 hm RN0H hm RN0 hm RN0 hm RN0 hm RN0 hm RN0E hm RN0F hm 0 RN0 hm RN0H hm RN0 hm RN0 hm RN0 hm RN0 hm RN0E hm RN0F hm 0 RN0 hm RN0H hm RN0 hm RN0 hm RN0 hm RN0 hm RN0 hm RN0 hm RN0 hm RN0 hm RN0E hm RN0F hm 0 RN0 hm RN0H hm RN0 hm RN0 hm RN0 hm RN0 hm RN0E hm RN0F hm 0 RN0 hm RN0H hm RN0 hm RN0 hm RN0 hm RN0 hm RN0E hm RN0F hm 0 RN0 hm RN0H hm RN0 hm RN0 hm RN0 hm RN0 hm M_KE M_KE M M M M M M M M M M M M M 0 M WE# M M 0 M R# M 0 M M # M_T M_# M_# M_T M M M M M M_KE M_KE0 M M M M M 0 M M M 0 M M R# M 0 M M M # M WE# M_T0 M_#0 M_# M_T 0.V 0.V 0 c00 0.UF0V c00 0.UF0V M #, M R#, M WE#, M [0..], M [0..], M #, M R#, M WE#, M_#[0..],, M_T[0..],, M_KE[0..],, 0 c00 0.UF0V dd Voltage Follower Layout note: Place one cap close to every pull-up resistors terminated to 0.V c00 0.UF0V 0 c00 0.UF0V c00 0.UF0V 0 c00 0.UF0V c00 0.UF0V 0 c00 0.UF0V c00 0.UF0V 0.0UF0V 0 c00 0.UF0V c00 0.UF0V.V R0 0 c00 0.UF0V 0 c00 0.UF0V 0Khm R0 0Khm 0 c00 0.UF0V c00 0.UF0V V 0 c00 0.UF0V c00 0.UF0V U0 V - V- LMVVR 0.UFV c00 0.UF0V c00 0.UF0V T0 c00 0.UF0V M_VREF_MH c00 0.UF0V UF0V c00 0 c00 0.UF0V c00 0.UF0V c00 0.UF0V c00 0.UF0V ULPHTeK MPUTER N. R TERM Horng hou ize Project Name Rev ustom TERE ate: Monday, February 0, 00 heet of.

17 V_RT R0 RTRT# 0Khm 0 UFV JRT (0)hange reference from JRT0 to JRT 0 PF0V X0 E 0.KHZ PF0V RT_X R0 0Mhm RT_X.V_PE_H VP_H V_RT VP.V V V V.V_PE_H,0 VP_H 0 V_RT 0 VP,,,0,.V,,0,0,,,, V,,,0,,,,,0,,,,0, V,,,,,,,,,,0,,,,,,,,0,,,0,,0,,0, V,,,,,,0,,,, elete LP interface of TPM LP_0_H R LP H R0 LP H R LP H R LP_FRME#_H R close to H Z_LK_U Z_LK_M Z_YN_U Z_YN_M, Z_RT#_U Z_RT#_M Z_UT_U Z_UT_M hm hm hm hm R0 hm R hm R0 hm R hm R hm R hm R hm R0 hm hm LP_0 LP_ LP_ LP_ LP_FRME# Z_LK Z_YN Z_RT# Z_UT LP_0, LP_, LP_, LP_, LP_FRME#, 0 T_LE# RT_X RT_X RTRT# Z_LK Z_YN Z_RT# Z_N0 Z_N Z_N Z_UT T_RXN0 T_RXP0 T_TXN0_H T_TXN0 0 00PF0V T_TXP0_H T_TXP0 0 00PF0V hange to 00PF Remove 0 ohm T_R T0 T_TN T0 T_TP LK_PE_T# LK_PE_T V_RT R0 Mhm R0 0Khm Z_N0 Z_N T0 E_PR#_H E_PR# E_PW# E_PW# E_PK# E_PK# NT_RQ NT_RQ E_PRY E_PRY E_PREQ E_PREQ U0 RTX RTX NTRUNER# Y NTVRMEN W RTRT# NTRUER# NTVRMEN W EE_ Y EE_HLK Y EE_UT W EE_N V U LN_LK LN_RTYN U LN_RX0 V LN_RX T LN_RX U LN_TX0 V LN_TX V LN_TX U Z_LK R Z_YN R Z_RT# T Z_N0 T Z_N T Z_N T F Z_UT TLE# F T0RXN E T0RXP T0TXN H T0TXP F TRXN E TRXP TTXN H TTXP F T_LKN E T_LKP T_RH0 R.hm % TRN 0 TRP F R# H W# F K# H ERQ RY E REQ HM RT LN -ZL T E PU LP L0 L L L LRQ0# LRQ#P LFRME# 0TE 0M# PULP# TPPRTP# TPPLP# FERR# PPUPWR NNE# NT_V# NT# NTR RN# NM M# TPLK# THERMTRP# # # Y E H F H LP_0_H LP H LP H LP H LP_RQ#0 LP_RQ# LP_FRME#_H 0TE H_0M# _PULP# _PRTP# H_PLP# H_FERR# H_PWR H_NNE# NT_V# F H_NT# F H_NTR RN# H H_NM F H_M# H F E F E F F H H H E F E H_TPLK# _THRMTRP# E_P0 E_P_H E_P_H E_P E_P E_P E_P E_P E_P E_P_H E_P0_H E_P E_P E_P E_P E_P E_P0 E_P E_P E_P# E_P# LP_RQ#0 T0 0TE H_0M# R0 R0 H_PWR H_NNE# H_NT# H_NTR RN# H_NM H_M# H_TPLK# R.hm % E_P0 E_P E_P E_P E_P E_P E_P E_P E_P E_P E_P E_P E_P0 E_P E_P E_P# E_P# H_PULP#, H_PRTP#,0 H_PLP# T0 VP_H R hm E_P E_P E_P E_P0 VP_H R0 hm PM_THRMTRP#, H_FERR# PRTP# routing from ntel 0M to Yonah processor is required. Routing to VR must be done last and must have de-bounce filtering to handle daisy chain topology. ± % series termination resistor placed within " from ntel 0M, ± % pull-up resistor has to be within " from the series resistor heck with EM: remove 0 ohm =>E_PR#_H E_P_H E_P_H E_P_H E_P0_H Z_UT PWRK rising TP pull low: allow entrance to XR hain testing TP not pull low: sets bit of RP.P Z_YN PWRK rising sets bit 0 of RP.P P EE_ EE_UT NT# should not be pulled high should not be pulled low should not be pulled low P P PU PU P PRLPVR P NTVRMEN LNKLERT# REQ[:]# TLE# PKR RMRT# rising LWY PWRK rising PWRK rising should not be pulled high should not be pulled low high: Enable integrated Vccus_0 VRM REQURE an extenal pull-up R should not be pulled low high: "No reboot" mode P PU Need PU onditional PU P NT# NT#P# NT#P PWRK rising PWRK rising low: "top-block swap" mode NT# NT# 0 P 0 P LP PU PU TP PWRK rising should not be pulled low unless using XR hain testing ULPHTeK MPUTER N. PU H-M () Horng hou ize Project Name Rev ustom TERE ate: Monday, February 0, 00 heet of.

18 P evice, P_[:0] evice EL# REQ#NT# nterrupts ardus REQ#NT#,, LN REQ#NT#, P_NT#, P_NT#, P_NT#, P_NT# T0 T0 T0 T0 T U0 P_0 E P_ 0 REQ0# P P_ NT0# P_ REQ# F P_ NT# E P_ REQ# P_ NT# E P_ REQ# P_ NT# P_ REQ#P P_0 NT#P E P_ 0 PREQ# P_ PNT# P_ P_ E0# P_ E# P_ E# E P_ E# P_ P_ RY# P_0 PR 0 P_ 0 PRT# F P_ EVEL# F0 P_ PERR# E P_ PLK# P_ ERR# P_ TP# P_ TRY# P_ FRME# P_ P_0 PLTRT# E P_ 0 PLK PME# nterrupt F P_NT# P_NT# PRQ# PPRQE# P_NT# PRQ# PPRQF# P_NT# PRQ# PPRQ# PRQ# PPRQH# M _RV E _RV RV_ RV RV RV_ RV RV RV_ RV_ H _RV RV_ RV_ RV_ MH_YN# HM E E F E0 E 0 F F F F F E H F H0 P_REQ#0 P_NT#0 P_REQ# P_NT# P_REQ# P_NT# P_REQ# P_NT# P_REQ# P_NT# P_REQ# P_NT# P_E#0 P_E# P_E# P_E# P_RY# P_PR P_RT#_H P_EVEL# P_PERR# P_LK# P_ERR# P_TP# P_TRY# P_FRME# PLT_RT#_ LK_HP P_PME# P_NTE# P_NTF# P_NT# P_NTH# P_E#0, P_E#, P_E#, P_E#, P_EVEL#,, P_PERR#,, P_LK# P_ERR#,, P_TP#,, P_TRY#,, P_FRME#,, LK_HP P_PME#,, _RV T0 _RV T0 _RV T0 _RV T MH_H_YN# MH_H_YN# NT# NT# LP (default) P_REQ#0 T0 P 0 0 P 0 0 P_REQ#, P_NT# P_REQ#, P_NT# P_REQ# T0 R0 Khm P_REQ# P_REQ# P_RY#,, P_PR, P_NTE# P_NTF# P_NT# P_NTH# R0 Khm 0ohm replace N gates P_RT#_H PLT_RT#_ (0)dd N gates U0 V Y NUP0KR U0 V Y NUP0KR R0 R0 V V P_RT#,, PLT_RT#,,,,, VU RN0 00Khm RN0 00Khm RN0 00Khm RN0 00Khm RN0 0Khm RN0 RN0 RN0 0Khm 0Khm 0Khm PE_RXN_MNR PE_RXP_MNR PE_TXN_MNR PE_TXP_MNR PE_RXN_NEWR PE_RXP_NEWR PE_TXN_NEWR PE_TXP_NEWR U_N_0# U_N_# U # NEWR_# U # U # Y_RT# PM_R# Y_RT# PM_R# T T T T PE_RN PE_RP PE_TN PE_TP 0 0.UF0V 0 0.UF0V c00 T T T0 T T T T0 0 0.UF0V 0 0.UF0V c00 T T T T0 T T T T T T PE_RN PE_RP PE_TN PE_TP PE_RN PE_RP PE_TN PE_TP PE_RN PE_RP PE_TN PE_TP P_LK P_# P_R P_M P_M U0 F PERn F PERp E PETn E PETp H PERn H PE_TN PERp PE_TP PETn PETp K PERn K PE_TN PERp J PE_TP PETn J PETp M PERn M PERp L PETn L PETp P PERn P PERp N PETn N PETp T PERn T PERp R PETn R PETp R P_LK P P_# P P_R P P_M P P_M U_N_0# U_N_0# U # 0# onnect to # U_N_# # U_N_# # U # # E U # # NEWR_# #P NEWR_# U # #P0 #P HM P P-Express U irect Media nterface M0RXN M0RXP M0TXN M0TXP MRXN MRXP MTXN MTXP MRXN MRXP MTXN MTXP MRXN MRXP MTXN MTXP M_LKN M_LKP M_ZMP M_RMP UP0N UP0P UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UR# UR V V U U Y Y W W E E F F H H J J K K L L M M N N M_RXN0 M_RXP0 M_TXN0 M_TXP0 M_RXN M_RXP M_TXN M_TXP M_RXN M_RXP M_TXN M_TXP M_RXN M_RXP M_TXN M_TXP LK_PE_H# LK_PE_H U_PN0_ U_PP0_ T T U_PN_ U_PP_ U_PN_ U_PP_ T T T T U_PN_ U_PP_ T0 T R0 UR_PN M_RXN0 M_RXP0 M_TXN0 M_TXP0 M_RXN M_RXP M_TXN M_TXP M_RXN M_RXP M_TXN M_TXP M_RXN M_RXP M_TXN M_TXP LK_PE_H# LK_PE_H R0.hm % M_MP.V_PE_H U_PN0 U_PP0 U_PN U_PP U_PN U_PP dd test points.hm % U_PN U_PP (00)RT HVYN buffer circuit move to page- Layout Note: Pull-ups must be placed within 00 mils from ntel 0M pins ULPHTeK MPUTER N. ize Project Name Rev ustom TERE Modify U evice table U evices Port 0 Port Port Port Port Port Port Port N0 Unused N0 N0 Unused Unused Neward Unused H-M () Horng hou ate: Monday, February 0, 00 heet of.

19 U0 PRLPVR contains same information M_LK P M_T MLK PT0P F R0 0 as PRTP#. P T0 P_TRY# LNKLERT# MT PTP H PRLPVR is preferred over PRTP# RP0,, P_TRY# M_LNK0 LNKLERT# PTP H.KHM T0 if only one signal will be used. 0 P_0 P_LK# M_LNK MLNK0 PTP E RP0 P_LK#.KHM MLNK 0 LK_H P_ERR# RP0 PM_R# LK LK_H,, P_ERR#.KHM LK_U PM_R# R# LK LK_U 0 P_PERR# RP0,, P_PERR# _PKR LK_H _PKR 0 PKR ULK 0.KHM 0 T T 0PF0V P_REQ# RP0E P_REQ# Y_RT# U_TT#.KHM LP_# Y_RT# R0 Y_RT# LP_# PM_U# 0 LP_# P_REQ#0 PM_U#, P_REQ#0 PM_MUY# LP_# R0 0 RP0F.KHM LP_# PM_MUY# P0M_UY# LP_# F 0PF0V 0 T0 P_RY# RP0,, P_RY#.KHM M_LERT# H_PWRK MLERT#P PWRK H_PWRK, 0 P_EVEL# RP0H,, P_EVEL#.KHM TP_P# PM_PRLPVR TP_P# 0 PM_PRLPVR,0 TP_PU# PTPP# PPRLPVR 0,0 TP_PU# F R0 P0TPPU# PM_TLW# TP0TLW# 0Khm T P_NT# RP0 P, P_NT#.KHM (0)efine T devices PM_PWRTN# PM_PWRTN# T_EV0 PWRTN# 0 P_NT# RP0, P_NT# NEWR_FF# P.KHM NEWR_FF# E P 0 PLT_RT# P_NT# RP0 PLT_RT#,,,,,, P_NT# (00)dd PM_LKRUN# LN_RT#.KHM, PM_LKRUN# PLKRUN# 0 PM_RMRT# P_NT# NEWR_FF# pin PM_RMRT#, P_NT# T_EV RMRT# Y RP0.KHM (0)efine T devices T_EV PZ_K_EN# 0 U T_ET#0 f HM embedded Lan P_NT# RP0E PZ_K_RT# P E0 P_NT#.KHM WLN_W#_H controller was used 0 PE_WKE# P0 0 R0 K_# P_NTF#, PE_WKE# F0 K_# "LN_RT#" should be P_NTF# NT_ERRQ WKE# P F 0Khm RP0F.KHM NEWR_ET#, NT_ERRQ H NEWR_ET# connected to "RMRT#" PM_THERM#_H ERRQ P E 0 F0 T_LL#_H P_NTH# THRM# P R RP0 P_NTH#.KHM (0)Rename into PM_THERM#_H WLN_LE# WLN_LE# 0 VRMPWR P E 0 P_NTE# RP0H 0 MVPK P_NTE#.KHM R0 VRMPWR P R _# _# 0 T P 0 P T0 PM_THERM#_P P P P P_ T VU EXTM# P P 0 P_ P_REQ# EXTM# E nternal pull high (0)dd 00K pull-up resister RP0 P P E0 P_REQ#.KHM 0 HM, P_REQ# P_REQ# RP0.KHM 0 PM_THERM# R0 (0)dd T_LL & T_PT function P_REQ# RP0, P_REQ#.KHM PM_THERM#_P NEWR_ET# R 00Khm 0 P_REQ# RP0 P_REQ#.KHM 0 T_LL#_H R 00Khm 0 PM_THERM#_H PM_TLW# PM_LKRUN# RP0E T_LL#.KHM R (0)Rename into PM_THERM#_H 0 NW PM_THERM#_H RP0F.KHM 0 (0) P_FRME# RP0,, P_FRME#.KHM K_# R0 0Khm 0 0 P_TP# RP0H,, P_TP#.KHM T_LL#_H 0 P NW checklist suggests M_LERT# R0 0Khm M_LK_ R.Khm P Power Plane Vsus M_T_ R.Khm,,,, M_LK_,,,, M_T_ P_0 P_ P_ PU Vcore V ore.v ore.v Resume V V R.Khm r00_h R.Khm r00_h P[] P[:] P[0][:][:][:][] P[:][:] V R0.Khm r00_h R.Khm r00_h Q0 N00 Q0 N00 R.Khm r00_h R.Khm r00_h V M_LK M_T (0)efine P P_ : PRJET E P_ M V.0 M V. M V M Y P Power MT locks T P (0) WLN_W#_H R T_EV0 T_EV T_EV H_PWRK (00)efine T devices V Q0 N00 VRMPWR VU V V R 0Khm R 0Khm R 0Khm R 0Khm R 0Khm WLN_W#,,0 R 0Khm R 0Khm T EVE T_EV0: NEWR T_EV: PM T_EV: ME R (0:Existence : Nonexistence) PM_TLW# T_ET#0 Remove pull-up resister of P_LE# & T_ET# (P,: default P) WLN_LE# M_LK M_T PE_WKE#,, P_PME# R.Khm R.Khm R.Khm R.Khm R.Khm R Khm Pull-up to VU for NEWR_FF# NEWR_FF# M_LNK LNKLERT# M_LNK0 (0)Remove pull-up resistor R (connect to U_TT#) P_PME# R 0Khm nternal pull up RN0 0Khm RN0 0Khm RN0 0Khm RN0 0Khm LP_RQ#0 VU NT_ERRQ TP_P# TP_PU# P LP_RQ#0 R.Khm nternal pull up PM_RMRT# PM_PRLPVR R 00Khm nternal pull down ULPHTeK MPUTER N. V ize Project Name Rev ustom TERE R 0Khm R 0Khm R0 0Khm R.Khm R 0Khm H-M () Horng hou ate: Monday, February 0, 00 heet of.

20 VP_H VP JP00 U0E V Vss Vss P 00 HRT_PN Vss Vss R Vss Vss00 R Vss Vss0 R JP00 V Vss Vss0 R Vss Vss0 R R00 T U0F Vss Vss0 R 0 m HRT_PN 0 VREF Vss Vss0 R m 0 VREF_ Vcc_0_ L Vss Vss0 R Vcc_0_ L Vss0 Vss0 R 00 VREF_ Vcc_0_ L Vss Vss0 T 0.UF0V Vcc_0_ L E00 Vss Vss0 T 0 m F VREF_us Vcc_0_ L 0.UF0V UF0V 0UFV Vss Vss0 T VU Vcc_0_ L cd_h 0 Vss Vss T f H embedded Lan Vcc Vcc_0_ M Vss Vss T Vcc Vcc_0_ M controller was used, these R00 Vss Vss T 00 Vcc Vcc_0_ P pins should connect to Vss Vss T Vcc Vcc_0_0 P V Vss Vss U VU for - wake up. VU Vcc Vcc_0_ T E R00 Vss Vss U Vcc Vcc_0_ T E Vss0 Vss U Vcc Vcc_0_ U VU E Vss Vss U R00 T VREF_U Vcc Vcc_0_ U E Vcc Vcc_0_ V 00 Vss Vss U E Vss Vss0 U Layout Note: 00 Vcc 0 Vcc_0_ V F V Vcc Vcc_0_ V 0.UF0V Vss Vss U Place within 00 mils of H-M F Vss Vss U Layout Note: 0.UF0V Vcc Vcc_0_ V F on the ottom side or 0 mils Vss Vss U Place above aps within 00 mils of Vcc Vcc_0_ V F Vss Vss U on the Top near pin H-M on the ottom side or 0 mils Vcc Vcc_0_0 V F E VPUX Vss Vss V 0 m 00 on the Top near pin, T & Vcc F Vss Vss V E Vcc Vccus_VccLN V Vss0 Vss V E Vcc Vccus_VccLN V 0.UF0V Vss Vss V F Vcc Vccus_VccLN W Vss Vss V F.V.V_PE_H Vcc Vccus_VccLN W m Vss Vss0 V Vcc 0 Vcc Vcc_VccH 0 m Vss Vss W Vss Vss W L00 H Vcc 0 m H VP_H Vcc Vccus_VccusH R Vss Vss W VU Vss Vss W J Vcc 00 Vss Vss Y 00Mhz J Vcc V_PU_ E m (0)hange into PN:0 Vss Vss Y E00 K Vcc V_PU_ E 0.UF0V Vss0 Vss Y 0UFV 0.UF0V 0.UF0V K Vcc V_PU_ H 00 0 H Vss Vss Y cd_h L 0 Vcc Layout Note: H Vss Vss L Vcc Vcc 0.UF0V 0.UF0V.UF0V Place within 00 mils of H-M H Vss Vss0 M Vcc 0 Vcc H M on the ottom side or 0 mils Vss Vss V Vcc Vcc 0 H Vss Vss N Vcc Vcc 0 m V on the Top near pin H N Vss Vss Vcc Vcc J Vss Vss P Vcc Vcc 0 J Vss Vss Layout Note: P Vcc Vcc J 0 Vss Vss Place within 00 mils of H-M R Vcc Vcc 0 0.UF0V J Vss0 Vss R on the ottom side or 0 mils Vcc Vcc J 0.UF0V R V Vss Vss Vcc J on the Top R Vss Vss Vcc Vcc Layout Note: K Vss Vss0 R Vcc 0 Vcc istribute in P section K Vss Vss T Vcc Vcc K Vss Vss T.V.V_MPLL Vcc Vcc L Vss Vss T Vcc Vcc L Vss Vss T Vcc Vcc L Vss Vss R00 L00 T.V_MPLL_L Vcc Vcc F 0.UF0V 0.UF0V 0.UF0V L V_RT Vss Vss 0 m U Vcc Vcc L Vss0 Vss U Vcc Vcc 0 M Vss Vss hm 00Mhz 0 0 V Vcc Vcc M V Vss Vss Vcc M W Vcc 0 VccRT W Vss Vss0 0UF0V 0.0UF0V 00 0 M Vss Vss W Vcc M Vss Vss Layout Note: Y m VU Vcc Vccus P 0.UF0V 0.UF0V M Vss Vss Place within 00 mils of H-M Y Vcc M on the ottom side or 0 mils Vccus 0 Vss Vss 0 M Vss Vss Vcc Vccus (00,Power) Modify for RT charge circuit M on the Top near pin.v Vccus 0.UF0V Vss Vss E 0.UF0V M Vss0 Vss E VccMPLL Vccus M Vss Vss E Vccus M RT_PWR Vss Vss E 0 m Vcc N VU Vss Vss0 E.V Vcc Vccus K N Vss Vss E 0 Vcc Vccus K N Vss Vss E Layout Note: Vcc Vccus K N V_RT Vss Vss E 0.UF0V Place within 00 mils of 0 m E Vcc Vccus 0 K 00 N F H-M on the ottom side or Vcc Vccus L T00 Vss Vss E T00 N Vss Vss F 0 F 0 mils on the Top Vcc Vccus L 0 0 N Vss Vss F Vcc Vccus L N H RT_T Vss0 Vss F 0.UF0V Vcc Vccus L 0.UF0V 0.UF0V N Vss Vss F XR V Vccus L N Vss Vss F VccTPLL Vccus M R00 N Vss Vss0 F Vccus M.Khm 0 N H Vcc Vccus N TT_P Vss Vss N.V T UF.V Vss Vss Layout Note: N VU.V Vss Vss 0 Place within 00 mils of 0 Vcc 0 Vcc N Vss Vss H-M on the ottom side or Vcc Vcc 0 P 0 VP_H Vss Vss 0.UF0V Vcc P 0 mils on the Top 0 Vss Vss Vcc Vcc T 00 P Vss0 Vss 0 0 E0 Vcc Vcc F P Vss Vss 0 F0 Vcc Vcc 0.UF0V (0)hange battery into rechargeable type (PN:0000) P Vss Vss H 0.UF0V UF0V F R00 Vcc PNN ML0-FE 0000 P Vss Vss0 H Vcc Vcc P H MXELL ML0T Vss Vss H.V Layout Note: Vcc Vcc P Vss Vss H P VLN Vss Vss H Place within 00 mils of H-M E Vccus Vccus_0_ K P Vss Vss H m on the ottom side or 0 mils 0 m VccUPLL Vccus_0_ HM.V on the Top near pin VLN Vccus_0_ 0 0 c00 Vccus_0VccLN_0_ 0 m Y Vccus_0VccLN_0_ Vcc 0.UF0V Vcc H Layout Note: Vcc H 0 Place within 00 mils of Vcc J H-M on the ottom side H-M () Vcc 0 J 0.UF0V or 0 mils on the Top ULPHTeK MPUTER N. Horng hou HM ize Project Name Rev ustom. VP RX TX U RE RE E P U VU TERE ate: Monday, February 0, 00 heet 0 of

21 V_U HEPHNE_L HEPHNE_R FRNT_L FRNT_R 0 UFV c00_h 0 0.UFV c00 EPP V_E _U Z_LK_U Z_UT_U Z_LK_U Z_N0 Z_YN_U, Z_RT#_U PFV c00 Z_LK_U R0 hm R 0Khm Z_N0_E P_EEP U0 PF_UT V K P V T_UT T_LK V T_N V 0 YN REET# PEEP EP V LNE_UT_R V LNE_UT_L V HEPHNE_R V 0 HEPHNE_L V MN_UT PHNE_N UX_L UX_R JK_ENE_ JK_ENE L R M_ M_ LNE_N_L LNE_N_R JPZ URR_UT_R URR_UT_L V VREF_UTLFE LFE_UT ENTER_UT V 0 VREF_UTLNE_N VREF_UTM_ VREF_FLT V V Remove nternal M _U T0 M_VREFUT_R VREF_E _U TPT V_U 0 (0,)dd 0.uf cap to 0.UFV _U and close to pin c00 0 UFV c00_h 0 0.UFV c00 V_U V_U 0 _U _U _U R0.Khm R.Khm Remove 0 0 UFV UFV 0VXR 00 R Khm M_JK_R T_LW_EEP M_ET# HP_ET# 0.UFV _PKR _PKR_ c00 0 R0 Khm N0K 0.UFV _PKR _PKR_ (00,) 0 c00 Remove R0,R0 (00) Mount R0, R0 R0 Khm NW 0.UFV c00 R Khm R 0Khm % R 0.Khm P_EEP_ R0 Khm 0.UFV c00 P_EEP hange into circuit V ET#_E V 0.0UFV (00,) dd 0.0UF for noise filiter L0 0.UF0V 0UF0V V _U New addition(refer to VJ) UFV 00Mhz U0 HN# N Vref=.V (00).Kohm=>.Kohm _U V_E 0.UFV 0.UFV UFV c00 c00 c00_h ET UT F 00PF0V R0 00Khm R0.KHM 0 0.UF0V (0,)dd Kohm resister V_U 0.UFV 0UF0V c00 ULPHTeK MPUTER N. _U _U ize Project Name Rev ustom (00,EM)dd three 0ohm resisters R, R, R R ottom side (00,EM)Mount R0, R, R, R R0 R0 R R Top side R R R R TERE JPZ Horng hou ate: Monday, February 0, 00 heet of.

22 R0 Khm (00) hange R0, R0, R0, R0 into k ohm 0 PF0V R0 Khm 0 PF0V Remove Woofer circuit FRNT_R 0 0.UFV 0 UF0V R0 0Khm R0 0Khm 0 UF0V XR U0 RLNEN 0 RHPN RYP RUT RUT- RV NTPKR NTPKR- V_MP L0 00Mhz V FRNT_L _U UF0V 0.UFV R 0Khm R 0Khm TJ MUTE N ETL# MUTE UT HPLNE# HUTWN LV LYP N N LHPN LUT LLNEN LUT- 0 0FUF H H THERML H H T R0 0Khm ETL# UF0V 0.UFV UFV UFV c00_h c00_h _U _U _U _U NTPKL NTPKL- HP_ET# V _U PF0V R0 Khm PF0V R0 Khm (000)modify JK_N circuit JK_N R 00Khm N00 ETL# Q0 _U Q0 N00, Z_RT#_U P_# EPP TW R 00Khm 0 V V R0 00Khm Q0 N00 Q0 N00 V R 0Mhm Q0 N00 R To nternal peaker onnector NTPKL R 00Mhz NTPKL- R 00Mhz NTPKR R 00Mhz NTPKR- R 00Mhz 00Khm r00 0.UFV c00 Q0 NTPKR R N00 R HEPHNE_R (0,) Placing Q0, Q0 Q0 on the other side of E0, E0 N00 E0 0UF.V R hm ER_R UTR_ JK_R ER_L Q0 N00 HEPHNE_L NTPKL (000,EM)dd Varistors(0~0) E0 0UF.V R R UTL_ R hm JK_L 00-00E0NP-LF 00-00E0NP-LF E0NP-LF 00-00E0NP-LF (00) change into 0000F N0 E E Wto_N_P c00 c00 000PF0V 000PF0V c00 c00 000PF0V 000PF0V R Khm _U L0 L0 R Khm Khm00Mhz Khm00Mhz L L _U HP_JK_R HP_JK_L 0 JK_N 00PF0V 00PF0V L0 Khm00Mhz 00PF0V use change _JK R0 R hange for Layout _JK 00Mhz 00Mhz _JK (00,EM) dd one 0ohm resister _JK 00PF0V (00,EM)hange 0ohm resisters into beads HP JK PHNE_JK_P 0 NP_N NP_N P_ P_ N0 _JK (00)hange Phone Jack into PN:0000M (0,)_JK connect to _U directly U MP ULPHTeK MPUTER N. Horng hou ize Project Name Rev ustom TERE ate: Monday, February 0, 00 heet of.