G60J Schematics for Calpella Platform Rev. 1.5

Transcription

1 YTEM PE REF. 0. lock iagram 0. ystem etting 0. PU()_MI,PE,FI,LK,MI 0. PU()_R 0. PU()_F,RV,N 0. PU()_PWR 0. PU()_XP. R()_O-IMM0. R()_O-IMM. R()_/Q Voltage. VI ontroller 0. PH()_T,IH,RT,LP. PH()_PIE,LK,M,PE. PH()_FI,MI,Y PWR. PH()_P,LV,RT. PH()_PI,NVRM,U. PH()_PU,PIO,MI. PH()_POWER,N. PH()_POWER,N. PH()_PI,M. LK_ILPR 0. E_IT(). E_IT()K,TP,FP. RT_Reset ircuit. LN_R. LN_RJ. U()_LV. U()_MP,JK. U()_FM00 0. ()_RU0. ()_Neward. U_ebug. RT()_LV. RT()_-ub. RT()_isplay Port. TV()_HMI 0. FN_Fan,ensor. X_H,O. U_U Port. MINIR_WLN. LE_Indicator. _ischarge 0. _/T ONN. T_luetooth. TUN_TV Tuner. ME_ONN,kew Hole. E_ET. OTH_ME-LE 0. V()_MXM lot. V()_LV witch 0_PWR()_VORE _PWR()_YTEM_+VU _PWR()_VTT_PU &.0V _PWR()_I/O_R & VTT _PWR()_**** _PWR()_+.V _PWR()_**** _PWR()_HRER 0_PWR()_ETET _PWR()_LO WITH _PWR()_PROTET _PWR()_INL _PWR()_FLOWHRT. ystem History. Power On equence. Power On Timing HMI RT L Panel Page RT Page Page Touchpad Keyboard Page udio mp peaker Page udio Jack Page rray Mic Page MXM nvii N0E-T ebug onn. E ITE ITE PI ROM Page 0 s u M Page 0 Page Page 0 Thermal ensor PWM Fan zalia odec Realtek L Page 0 ardreader+ Ricoh RU0 Page 0~ Page rray Mic.P Fortemedia FM00 Page ischarge ircuit Page Reset ircuit Page PIE x 0J chematics for alpella Platform Rev.. HMI LV LOK IRM LP PI ROM Page PIEx zalia PU LRKFIEL/UURNLE (&Q) x I F & TT. onn. PH Ibex Peak-M s u M Page 0 T kew Holes Page 0 x I M Page ~ Page 0~ O H() PIEx U Page H() Page Page et Page lock enerator I ILPR R MHz Page 0 R O-IMM Miniard WLN hirley Peak/ Echo Peak Miniard TV Tuner igaln R Expressard U Port() U Port() U Port() Page ~ Page Page Page ~ Page Page Page Page U Port() Page luetooth Page MO amera Page RJ Page Power PU_VORE ystem VTT R +.V FX_ORE harger etect Load witch Power Protect Page 0 Page Page Page Page Page Page Page 0 Page Page U/R lock iagram 0J Friday, July, 00 ate: heet of.

2 PH_IEX PIO PH_IEX PIO Use s ignal Name PIO 00 PO PH_PIO0_R PIO PIO [:] Native PI_INT[E:H]# PIO 0 PI PU_PWR_EN PIO PIO 0 PI EXT_MI# PIO 0 Native U_O# PIO 0 Native U_O# PIO PI EXT_I# PIO Native PM_LNPHY_EN PIO - - PIO PO _# PIO PO WLN_ON PIO PO PU_HOL_RT# PIO PO PU_PWROK PIO Native LKREQ_TV# PIO PI T_ET#_R PIO 0 Native LKREQ_WLN# PIO PI T_ET#0_R PIO PO WLN_LE PIO - - PIO PO O_LN_RT# PIO Native LKREQ_NEWR# PIO Native LKREQ_ET# PIO - - PIO PO T_LE/PI_# PIO Native ME_PM_LP_LN# PIO 0 Native ME_UPWRNK / RTLN_M# PIO Native ME PREENT PIO Native PM_LKRUN# PIO - - PIO Native TP_PI# PIO Native T_LK_REQ# PIO PO PU_PWR_EN# PIO PI PU_PRNT# PIO PI P_I0 PIO PI P_I PIO 0 Native U_O# PIO Native U_O# PIO Native U_O# PIO Native U_O# PIO - - PIO - - PIO PIO PIO PIO PIO 0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO 0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO - - Native LKREQ_PE# - - PU_RT# / PO RIT_TEMP_REP#_R - - Native PI_NT# PO PU_ELET# Native PI_NT# Native LKREQ_LN# PO T_ON Native ML_LK Native U_O0# PO RTLN_M_EN Native LK_OUT0 Native LK_OUT Native ML_T INT PU Internal & External Power Pull-up/down - +V INT T +V EXT PU +V INT T +V INT T +V EXT PU & INT PU +VU EXT PU +VU EXT PU +VU EXT PU +VU EXT PU +VU - +VU EXT PU(IOE NI) +VU INT P +VU - +V EXT P & INT T +V EXT PU(NI)/P +V - +V EXT PU(NI)/P +V - +V EXT P +V - +V EXT PU +VU EXT PU(NI)/P +VU EXT PU(Not used) +VU INT WEK PU +VU EXT P +VU EXT PU(NI)/P(NI) +VU EXT PU +VU EXT PU EXT PU +VU +V - +V EXT PU +V EXT PU/P(NI) +V EXT PU +V EXT PU +V EXT P +V EXT P +V EXT PU (Not used) +VU EXT PU (Not used) +VU EXT PU (Not used) +VU EXT PU (Not used) +VU EXT PU (Not used) +VU EXT PU (Not used) +VU EXT PU (Not used) +VU EXT P +VU - +V - EXT PU (Not used) EXT PU INT PU - INT PU EXT PU(NI)/P EXT PU(IOE) EXT PU EXT PU (Not used) EXT PU INT T INT T INT T INT T - EXT PU (Not used) EXT PU (Not used) EXT PU +V +V +V +V +V +V +V +VU +VU +VU +VU +VU +VU +VU +VU +V +V +V +V +VU +VU +VU +VU E IT E PIO Use s ignal Name P0 O PWR_LE# P O H_LE# P - P O ME_LE_E# P O L_L_PWM P O FN_PWM P - P - P0 O U_E# P O U_E# P - P IO M0_LK P IO M0_T P O 0TE P O RIN# P O PM_RMRT# P0 - P IO M_LK P IO M_T P O PM_PWRTN# P I _IN_O# P O OP_# P I T_IN_O# P I RFON_W# P0 I PWRLIMIT# P I PM_U# P I UF_PLT_RT# P O EXT_I# P O EXT_MI# P O L_KOFF# P I FN0_TH P - PE0 O VU_ON PE O E (IT0 ddress/ata connect) PE O E# (IT0 ycle tart connect) PE O ELK (IT0 lock connect) PE I PWR_W# PE - PE I LI_W# PE I P_K# PF0 - PF - PF I EXP_TE# PF - PF I TP_LK PF IO TP_T PF O THRO_PU PF IO H_PEI P0 - P I PM_U# P - P - PH0 IO PM_LKRUN# PH - PH O FX_VR_ON PH O T_LERN PH O HK PH O NUM_LE# PH O P_LE# PI0 - PI I U_PWR PI I LL_YTEM_PWR PI I VRM_PWR PI I FX_VR PI I L_ PI - PI - PJ0 O PU_VRON PJ O PM_PWROK PJ O VET_E PJ O IET_E PJ O TP_LE PJ - E IT0 E PIO PIO0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO0 PIO PIO PIO PIO PIO PIO PIO Use s I I M_U RE : M-us evice lock enerator O-IMM 0 O-IMM PU Thermal I(0) V Thermal I(-) PIE PIE PIE PIE PIE PIE PIE PIE T0 T T T Minicard TV Tuner Minicard WLN Newcard LN T H() T O N/ N/ U/R ystem etting ignal Name ME_PM_LP_M# ME_UPWRNK - - ME_+VM_PWR ME_PM_LP_LN# ME PREENT ME_PWROK - ME_LP_M_E# V Thermal ensor(ne-e) U 0 U U U U U U U U U U 0 U U U 0J M-us ddress 000x ( h ) 00000x ( 0h ) 0000x ( h ) 0000x ( h ) 000x ( h ) VI ontroller M 000x ( h ) P FM00 T T N/ PIE to T (R) N/ N/ T H() et I I O O O 00x ( Eh ) U Port () U Port () U Port () U Port () MO amera Newcard Minicard TV Tuner N/ OLE WLN N/ U Port () luetooth Finger Print Friday, July, 00 ate: heet of.

3 <> MI_TXN0 <> MI_TXN <> MI_TXN <> MI_TXN <> MI_TXP0 <> MI_TXP <> MI_TXP <> MI_TXP <> MI_RXN0 <> MI_RXN <> MI_RXN <> MI_RXN <> MI_RXP0 <> MI_RXP <> MI_RXP <> MI_RXP FI_FYN0 FI_FYN FI_INT FI_LYN0 FI_LYN For Intel FX display U00 MI_RX#[0] MI_RX#[] MI_RX#[] MI_RX#[] MI_RX[0] MI_RX[] MI_RX[] MI_RX[] MI_TX#[0] MI_TX#[] F MI_TX#[] H MI_TX#[] MI_TX[0] F MI_TX[] E MI_TX[] MI_TX[] E FI_TX#[0] FI_TX#[] FI_TX#[] FI_TX#[] FI_TX#[] E FI_TX#[] F FI_TX#[] FI_TX#[] FI_TX[0] FI_TX[] 0 FI_TX[] FI_TX[] FI_TX[] E0 FI_TX[] F0 FI_TX[] FI_TX[] F FI_FYN[0] E FI_FYN[] FI_INT F FI_LYN[0] FI_LYN[] MI Intel(R) FI PI EXPRE -- RPHI PE_IOMPI PE_IOMPO PE_ROMPO PE_RI PE_RX#[0] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[0] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX[0] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[0] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_TX#[0] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[0] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX[0] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[0] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_IROMP_R R00 %.Ohm EXP_RI R00 % 0OHM PIEN_RXN[:0] <0> K PIEN_RXN0 J PIEN_RXN J PIEN_RXN PIEN_RXN PIEN_RXN F PIEN_RXN F PIEN_RXN PIEN_RXN E PIEN_RXN PIEN_RXN PIEN_RXN0 PIEN_RXN PIEN_RXN PIEN_RXN 0 PIEN_RXN PIEN_RXN PIEN_RXP[:0] <0> J PIEN_RXP0 H PIEN_RXP H PIEN_RXP F PIEN_RXP PIEN_RXP E PIEN_RXP F PIEN_RXP PIEN_RXP F PIEN_RXP PIEN_RXP PIEN_RXP0 PIEN_RXP 0 PIEN_RXP PIEN_RXP PIEN_RXP 0 PIEN_RXP L PIEN_TXN0 X00 0.UF/0V PIE_RXN0 M PIEN_TXN X00 0.UF/0V PIE_RXN M PIEN_TXN X00 0.UF/0V PIE_RXN M0 PIEN_TXN X00 0.UF/0V PIE_RXN L PIEN_TXN X00 0.UF/0V PIE_RXN K PIEN_TXN X00 0.UF/0V PIE_RXN M PIEN_TXN X00 0.UF/0V PIE_RXN J PIEN_TXN X00 0.UF/0V PIE_RXN K PIEN_TXN X00 0.UF/0V PIE_RXN H0 PIEN_TXN X00 0.UF/0V PIE_RXN H PIEN_TXN0 X0 0.UF/0V PIE_RXN0 F PIEN_TXN X0 0.UF/0V PIE_RXN E PIEN_TXN X0 0.UF/0V PIE_RXN PIEN_TXN X0 0.UF/0V PIE_RXN PIEN_TXN X0 0.UF/0V PIE_RXN PIEN_TXN X0 0.UF/0V PIE_RXN L PIEN_TXP0 X0 0.UF/0V PIE_RXP0 M PIEN_TXP X0 0.UF/0V PIE_RXP M PIEN_TXP X0 0.UF/0V PIE_RXP L0 PIEN_TXP X00 0.UF/0V PIE_RXP M PIEN_TXP X0 0.UF/0V PIE_RXP K PIEN_TXP X0 0.UF/0V PIE_RXP M PIEN_TXP X0 0.UF/0V PIE_RXP H PIEN_TXP X0 0.UF/0V PIE_RXP K PIEN_TXP X0 0.UF/0V PIE_RXP 0 PIEN_TXP X0 0.UF/0V PIE_RXP PIEN_TXP0 X0 0.UF/0V PIE_RXP0 F PIEN_TXP X0 0.UF/0V PIE_RXP E PIEN_TXP X0 0.UF/0V PIE_RXP PIEN_TXP X00 0.UF/0V PIE_RXP PIEN_TXP X0 0.UF/0V PIE_RXP PIEN_TXP X0 0.UF/0V PIE_RXP PIE_RXN[:0] <0> PIE_RXP[:0] <0> <,,0,,,,0,,,,0> <,> <,> <> <> <> <,0> <> <> H_PEI H_THRMTRIP# H_PURT# PM_YN# H_PUPWR H_RM_PWR H_VTTPWR H_PWR_XP UF_PLT_RT# +VTT_PU THRO_PU +VTT_PU % R00 % R00.Ohm % R00.Ohm % R00 H_PROHOT_# H_OMP H_OMP H_OMP H_OMP0 T00 TP_KTO#.Ohm % R00 H_TERR# R0 00 L0 H_PEI_IO H_THRMTRIP#_R 00 L0 PM_YN#_R 00 L0 VPWROO R 00 L0 VPWROO_0_R 00 L0 VPWROO_R 00 L R.-- PLT_RT#_R R0 0OHM T T T H K T 00 L0 R0 Ohm H_PROHOT_#_RN R0.KOHM K P L N N K M M L KTO#:pulled to ground on processor. may use to determine if PU is present U00 OMP OMP OMP OMP0 KTO# TERR# PEI PROHOT# THERMTRIP# REET_O# PM_YN VPWROO_ VPWROO_0 M_RMPWROK VTTPWROO TPPWROO RTIN# OKET MI THERML PWR MNEMENT LOK R MI JT & PM M_RMRT# M_ROMP[0] M_ROMP[] M_ROMP[] +VTT_PU LK LK# LK_ITP LK_ITP# PE_LK PE_LK# PLL_REF_LK PLL_REF_LK# PM_EXT_T#[0] PM_EXT_T#[] PRY# PREQ# TK TM TRT# TI TO TI_M TO_M R# PM#[0] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] +.V R0 T0 E F L M N N P +VTT_PU T P N P T T R R P N J K K J J H K H LK_PU_LK LK_PU_LK# LK_ITP_LK_R LK_ITP_LK#_R LK_EXP_P LK_EXP_N LKREF LKREF# M_ROMP0 M_ROMP M_ROMP PM_EXTT# RN00 RN00 XP_TI_R XP_TO_R XP_TI_M XP_TO_M H_R#_R XP_O0_R XP_O_R XP_O_R XP_O_R XP_O_R XP_O_R XP_O_R XP_O_R +VTT_PU <,,,,,,,,> +.V <,,,,> R0 R0 R0 R0 R0 % % % 0KOHM 0KOHM R0 RX0 RX0 RX0 RX00 RX0 RX0 RX0 RX0 00 L 00 L F F LK selection 0.Ohm KOhm KOhm M_RMRT# <,> XP_PRY# <> XP_PREQ# <> XP_TLK <> XP_TM <> XP_TRT# <> XP_O0 XP_O XP_O XP_O XP_O XP_O XP_O XP_O LK_ITP_LK <> LK_ITP_LK# <> 0MHz from PH. IF NOT UE, PULL-LOW FOR POWER VIN. PM_EXTT#0 <,> XP_REET# <,> XP_O[:0] <> OKET +VTT_PU H_PROHOT_# <> LK_PU_P_PH <> LK_PU_N_PH <> LK_MI_PH <> LK_MI#_PH 00 L0 00 L0 00 L0 00 L0 LK_PU_LK LK_PU_LK# LK_EXP_P LK_EXP_N R.-- H_PURT# XP_TM XP_TI_R XP_PREQ# XP_TLK R0 R0 R0 R0 R0 Ohm OHM OHM OHM OHM <0,0> PWRLIMIT# 00 RV-0 Q00 HN00 THRO_PU THRO_PU <0> FI disable: (For discrete graphic). N: FI_TX#[0:],FI_TX[0:],FI_RX#[0:],FI_RX[0:] V_XENE,V_XENE. Pull-down to N via KΩ ± % resistor: FI_FYN[0:],FI_LYN[0:],FI_INT,FX_IMON ~mw power saving.( R0. P.0). onnected to N: VX,PLL_REF_LK,PLL_REF_LK#. an be connected to N directly: PLL_REF_LK,PLL_REF_LK# FI_FYN0 FI_FYN FI_LYN0 FI_LYN FI_INT 00 L 00 L 00 L KOhm R0 KOhm R0 RMPWROK: (WW MoW) hoose either one solution: -->hoose solution. This pin should have an external pull-up of K Ohms to 0K Ohms to a rail of.0/.v which is ON in 0-. onnect this pin through a voltage divider circuit; recommend.k Ohms pull-up to R Power Rail (VQ) of +V.U and a K Ohms pull-down to ground to convert to processor s VTT level. VPWROO_R +.V R00.KOhm.0KOHM R0 R.-- JT MPPIN XP_TI_R XP_TO_M XP_TI_M XP_TO_R R0 R00 R0 00 L PU_XP PU_XP 00 L XP_TI <> XP_TO <> XP_TRT# R0 OHM. onnect to +V.0 rail: VFIPLL WW_00_WOM U/R PU()_MI,PE,FI,LK,MI 0J Friday, July, 00 ate: heet of.

4 M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M M M M M M M M M M0 M M M M M M M Q M Q M Q0 M Q M Q M Q M Q M Q M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M M M M M M M 0 M M M M M 0 M M M M M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M M M M M M M M M M M M0 M M M M M Q M Q0 M Q M Q M Q M Q M Q M Q M Q# M Q# M Q# M Q# M Q#0 M Q# M Q# M Q# M M M M M M M M M M 0 M M M 0 M M M M Q[:0] <> M 0 <> M <> M <> M # <> M R# <> M WE# <> M M[:0] <> M Q[:0] <> M Q#[:0] <> M [:0] <> M_LK_R0 <> M_LK_R#0 <> M_KE0 <> M_#0 <> M_# <> M_OT0 <> M_OT <> M_LK_R <> M_LK_R# <> M_KE <> M Q[:0] <> M # <> M R# <> M WE# <> M 0 <> M <> M <> M M[:0] <> M Q[:0] <> M Q#[:0] <> M [:0] <> M_LK_R <> M_LK_R# <> M_KE <> M_LK_R <> M_LK_R# <> M_KE <> M_# <> M_# <> M_OT <> M_OT <> ate: heet of Friday, July, 00 U/R PU()_R. 0J ate: heet of Friday, July, 00 U/R PU()_R. 0J ate: heet of Friday, July, 00 U/R PU()_R. 0J R YTEM MEMORY - U00 OKET R YTEM MEMORY - U00 OKET _[0] _[] W _[] R _# _R# Y _WE# _K[0] W _K[] V _K#[0] W _K#[] V _KE[0] M _KE[] M _#[0] _#[] _OT[0] _OT[] _M[0] _M[] E _M[] H _M[] K _M[] H _M[] L _M[] R _M[] T _Q[] _Q#[] H _Q[] L _Q#[] L _Q[] P _Q#[] R _Q[] R _Q#[] R _Q[0] _Q#[0] _Q[] E _Q#[] F _Q[] H _Q#[] J _Q[] M _Q#[] L _M[0] U _M[] V _M[] T _M[] V _M[] R _M[] T _M[] R _M[] R _M[] R _M[] R _M[0] _M[] P _M[] R _M[] F _M[] P _M[] N _Q[0] _Q[] _Q[] _Q[] _Q[] E _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] F _Q[] F _Q[] _Q[] F _Q[] F _Q[] _Q[] H _Q[] _Q[] J _Q[] J _Q[0] _Q[] _Q[] J _Q[] J _Q[] J _Q[] K _Q[] L _Q[] M _Q[] K _Q[] K _Q[0] M _Q[] N _Q[] F _Q[] _Q[] J _Q[] K _Q[] _Q[] _Q[] J _Q[] H _Q[0] K _Q[] K _Q[] M _Q[] N _Q[] K _Q[] K _Q[] M _Q[] M _Q[] P _Q[] N _Q[0] T _Q[] N _Q[] N _Q[] N _Q[] T _Q[] T _Q[] N _Q[] P _Q[] P _Q[] T _Q[0] T _Q[] P _Q[] R0 _Q[] T0 R YTEM MEMORY U00 OKET R YTEM MEMORY U00 OKET _[0] _[] _[] U _# E _R# _WE# E _K[0] _K[] Y _K#[0] _K#[] Y _KE[0] P _KE[] P _#[0] E _#[] E _OT[0] _OT[] F _M[0] _M[] _M[] H _M[] M _M[] _M[] M _M[] N0 _M[] N _Q[0] _Q#[0] _Q[] F _Q#[] F _Q[] H _Q#[] J _Q[] M _Q#[] N _Q[] H _Q#[] H _Q[] K0 _Q#[] K _Q[] N _Q#[] P _Q[] R _Q#[] T _M[0] Y _M[] W _M[] _M[] _M[] V _M[] _M[] V _M[] T _M[] Y _M[] U _M[0] _M[] T _M[] U _M[] _M[] T _M[] V _Q[0] 0 _Q[] 0 _Q[] _Q[] _Q[] 0 _Q[] 0 _Q[] E0 _Q[] _Q[] _Q[] F0 _Q[0] E _Q[] F _Q[] E _Q[] _Q[] E _Q[] _Q[] H0 _Q[] _Q[] K _Q[] J _Q[0] _Q[] 0 _Q[] J _Q[] J0 _Q[] L _Q[] M _Q[] M _Q[] L _Q[] L _Q[] K _Q[0] N _Q[] P _Q[] H _Q[] F _Q[] K _Q[] K _Q[] F _Q[] _Q[] J _Q[] J _Q[0] J0 _Q[] J _Q[] L0 _Q[] K _Q[] K _Q[] L _Q[] K _Q[] L _Q[] N _Q[] M0 _Q[0] R _Q[] L _Q[] M _Q[] N _Q[] T _Q[] P _Q[] M _Q[] N _Q[] M _Q[] T _Q[0] T _Q[] L _Q[] R _Q[] P

5 U00E U00H U00I P L L L J M L 0mil trace <> IMM0_VREF_Q J 0mil trace <> IMM_VREF_Q H E E0 T0 F0 M0 T0 F M T0 F P T0 F L T0 F L0 T0 F M T0 F N T0 F M T0 F K T00 F K T0 F0 K T0 F J T0 F N0 T0 F N T0 F J T0 F J T00 F J0 T0 F K0 T0 F H L000 H_RV_R 0 L0 00 H_RV_R 0 00 R.0-- U T T0 T00 J J T0 T0 T0 T0 RV RV RV RV RV RV RV RV RV RV0 RV RV RV RV F[0] F[] F[] F[] F[] F[] F[] F[] F[] F[] F[0] F[] F[] F[] F[] F[] F[] F[] F[] RV RV RV RV RV RV0 RV RV RV RV RV RV RV RV RV0 RV REERVE RV RV RV RV RV RV RV RV RV0 RV RV RV RV RV RV RV RV RV0 RV RV RV RV RV RV RV RV RV RV0 RV RV RV RV RV RV RV RV RV RV0 RV RV RV RV RV RV RV RV RV RV0 RV RV RV RV RV RV J J H K L R J J P T T R L L P0 P L T T P R T T P R R E F J H R R E V V N W W N E P RV_R RV_R T00 T00 T00 T00 T00 T00 T00 T00 T00 L0 00 L0 00 R.0-- T0 T R R R R R R0 R R R R R R P0 P P P0 P P P N N N N0 N M M M M0 M M M M M M L L L L0 L L L L L K K K K0 K J J J0 J J J J J J H H H H H H0 H H H H H0 H H H H H 0 F F F E V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V V0 V V V V V V V V V V00 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 E E E E E0 E E E E E Y Y Y W W W W W W0 W W W W W V0 U U U T T T T T T0 T T T T T R0 P P P N N N N N N0 N N N N N M0 L L L L L L K K K0 K K K K J J0 J J H H H H H H H H H H H H H 0 F0 F F F F F E E E E E E E E E E E 0 0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V00 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF T TP_MP_V_NTF T TP_MP_V_NTF R TP_MP_V_NTF TP_MP_V_NTF T0 T0 T0 T0 OKET OKET OKET F strapping information: F[:0]: PI Express Port ifurcation:(larksfield Only) - = x PE (efault) - 0 = x PE F[]: PIE tatic Numbering Lane Reversal.(uburndale Only) - :Normal Operation (efault) - 0:Lane Numbers Reversed -> 0, ->,... F[]: Embedded isplayport etection.(uburndale Only) - :isabled - No Physical isplay Port attached to Embedded isplayport - 0:Enabled - n external isplay Port device is connected to the Embedded isplay Port F[]: Fixed for PI Express.0 jitter specifications.(larksfield) larksfield (only for early samples pre-e) - onnect to N with.0k Ohm/% resistor For a common motherboard design (for U and F), the pull-down resistor should be used. oes not impact U functionality. Unmount if Intel has fixed this issue. Note: (uburndale)hardware traps are sampled on the asserting edge of VPWROO_0 and VPWROO_ and latched inside the processor. F0 F F F R0 R0 R0 R0 % % % %.0KOHM.0KOHM.0KOHM.0KOHM Note: (larksfield)hardware traps are sampled after RTIN# de-assertion. U/R PU()_F,RV,N 0J Friday, July, 00 ate: heet of.

6 U00F +VTT_PU +.V +VTT_PU <,,,,,,,,> +.V <,,,,> +VORE +VORE <,,0> +VORE +VTT_PU +.V +.V <,,,0,> 0 F F F F F F0 F F F F Y Y Y Y Y Y0 Y Y Y Y V V V V V V0 V V V V U U U U U U0 U U U U R R R R R R0 R R R R P P P P P P0 P P P P V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V00 PU ORE UPPLY POWER ENE LINE PU VI.V RIL POWER VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 VTT VTT VTT VTT PI# VI[0] VI[] VI[] VI[] VI[] VI[] VI[] PRO_PRLPVR VTT_ELET IENE V_ENE V_ENE VTT_ENE V_ENE_VTT H H H H0 J J H H F F F F E E F0 E0 0 0 Y0 W0 U0 T0 J J J J N K K K L L M M M PU_VI0 PU_VI PU_VI PU_VI PU_VI PU_VI PU_VI PM_PRLPVR_R VENE VENE VTT_ENE TP_V_ENE_VTT Intel use u H_VTTVI <> VTT_TET T N J J 0UF/.V 00 UF/.V 0 0UF/.V 00 R.0-- R.0-- I_MON <0> 0UF/.V 00 0UF/.V 0 0UF/.V 00 +VTT_PU UF/.V 0 0UF/.V 0 T0 T0 0UF/.V 00 0UF/.V 0 +VORE 0UF/.V 0 0UF/.V 0 +VTT_PU R00 0 % R00 0 % 0 0UF/.V 0 0UF/.V R.-- PM_PI# <0> PU_VI[0:] <> PM_PRLPVR <0> VENE <0> VENE <0> R00 F +VTT_PU +VORE R0.,P +VTT_PU UF/.V 0 UF/.V 0 Intel use u Intel use u UF/.V 0 UF/.V 0 +VFX_ORE T T T T R R R R P P P P N N N N M M M M L L L L K K K K J J J J H H H H J J H K J J J H F E E ecoupling guide from Intel U00 VX VX VX VX VX VX VX VX VX VX0 VX VX VX VX VX VX VX VX VX VX0 VX VX VX VX VX VX VX VX VX VX0 VX VX VX VX VX VX VTT VTT VTT VTT VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT OKET VORE uf * pcs 0uF * pcs 0uF * pcs ( no stuff) 0 UF/.V 0 UF/.V UF/.V 0 0 UF/.V 0 UF/.V 0 FI PE & MI UF/.V +VFX_ORE RPHI POWER 0 UF/.V ENE LINE RPHI VIs R -.V RIL.V.V 0 VX_ENE VX_ENE FX_VI[0] FX_VI[] FX_VI[] FX_VI[] FX_VI[] FX_VI[] FX_VI[] FX_VR_EN FX_PRLPVR FX_IMON UF/.V VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VPLL VPLL VPLL 0 UF/.V R T M P N P M P N R T M J F E E Y W W U T T P N N L H P0 N0 L0 K0 J J0 J H H0 H L L M R0 FX_VRON_EN FXVR_PRLPVR_R L R.0-- R0 KOhm F 0 UF/.V 0 0 UF/.V UF/0V 0 Intel use u UF/0V 0 R00 0UF/.V UF/0V 0.UF/0V 0 F UF/0V 0.UF/.V 0 UF/0V 0 0 0UF/.V 0 UF/.V UF/.V 0 UF/0V 0.KOhm UF/0V 0 +VTT_PU +VTT_PU +.V R00 UF/.V 0 FX_VR <0> UF/.V 0 E00 0UF/V Intel.V P. u: /.u: /.u: / 0u:/.KOhm +.V R0.,P xbuck tuffing option + PNONI/EEFX0XE ER=mOhm/Ir= OKET 00 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 0UF/.V 00 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V 00 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V PU()_PWR U/R 0J. Friday, July, 00 ate: heet of

7 +VTT_PU +VTT_PU <,,,,,,,,> +VTT_PU <,> <> <> H_PUPWR PM_PWRTN#_R H_PWR_XP <,,,,,,,> <,,,,,,,> <> <> <> <> <> <> <> <> <> <> <> J00 XP_O XP_PREQ# T00 XP_O XP_PRY# T0 XP_O XP_O0 0 T00 0 XP_O XP_O T00 XP_O0 XP_O T00 XP_O XP_O T00 0 T0 XP_O 0 XP_O T0 T0 XP_O0 XP_O T0 XP_O XP_O T00 XP_O T00 XP_O 0 0 XP_O XP_O T00 XP_O XP_O T00 PUPWR_XP KOhm R00 0 LK_ITP_LK_XP R00 PM_PWRTN#_XP 0 R0 LK_ITP_LK#_XP R0 PIE_LK_XP_P R00 XP_RT#_R R00 KOhm PIE_LK_XP_N T M_T_ M_LK_ XP_TRT# <> XP_TI <> XP_TLK XP_TM <> 0 0 NP_N NP_N LK_ITP_LK <> LK_ITP_LK# <> H_PURT# <> +VTT_PU R0 Ohm XP_REET# <,> XP_TO <> to_on_0p XP_RT#_R R0 UF_PLT_RT# <,,0,,,,0,,,,0> PU_XP PU XP connector U/R PU()_XP 0J Friday, July, 00 ate: heet of.

8 U/R N()_**** ustom 0J ate: Friday, July, 00 heet of.

9 U/R N()_**** ustom 0J ate: Friday, July, 00 heet of.

10 U/R N()_**** ustom 0J ate: Friday, July, 00 heet 0 of.

11 U/R N()_**** ustom 0J ate: Friday, July, 00 heet of.

12 U/R N()_**** ustom 0J ate: Friday, July, 00 heet of.

13 U/R N()_**** ustom 0J ate: Friday, July, 00 heet of.

14 U/R N()_**** 0J ate: Friday, July, 00 heet of.

15 U/R N()_**** 0J ate: Friday, July, 00 heet of.

16 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q0 M Q M M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M M M M M M M M M M M M M M M M0 M Q M Q# M Q M Q M Q M Q# M Q M Q# M Q# M Q M Q# M Q#0 M Q M Q# M Q0 M Q# M M M M M M M 0 M M M M M 0 M M M M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M_LK_R0 M_LK_R M_LK_R# M_LK_R#0 M [:0] <> M Q[:0] <> M_LK_R0 <> M_KE0 <> M_LK_R# <> M_LK_R <> M_KE <> M # <> M_LK_R#0 <> M <> M 0 <> M <> M M[:0] <> M Q#[:0] <> M Q[:0] <> M_T_ <,,,,,,,> M_LK_ <,,,,,,,> M WE# <> PM_EXTT#0 <,> M_# <> M R# <> M_#0 <> M_OT0 <> M_OT <> M_RMRT# <,> +V <,,0,,> +.V_R <,> M_VREF_IMM0 <> +0.V <,,> M_VREFQ_IMM0 <> +.V <,,,,> +V +.V_R +0.V M_VREF_IMM0 M_VREFQ_IMM0 +0.V +.V_R +.V_R +.V_R +.V +V +.V_R M_VREF_IMM0 +0.V M_VREFQ_IMM0 +.V ate: heet of Friday, July, 00 U/R R()_O-IMM0. 0J ate: heet of Friday, July, 00 U/R R()_O-IMM0. 0J ate: heet of Friday, July, 00 U/R R()_O-IMM0. 0J H:.mm Mus lave ddress: 0H Layout Note: Place these caps near O IMM 0 Layout Note: Place these caps near O IMM 0 0 PLE LOE TO OIMM R.0-- R.0-- R.0-- R.0-- R.0-- 0PF/0V 0PF/0V 0 0UF/.V 0 0UF/.V UF/.V UF/.V 0 0UF/.V 0 0UF/.V R0 0KOhm R0 0KOhm.UF/0V.UF/0V.UF/0V.UF/0V 0.UF/0V 0.UF/0V J0 R_IMM_0P J0 R_IMM_0P EVENT# N 0 N 0 N N NP_N 0 NP_N 0 OT0 OT 0 R# 0 REET# 0 #0 # 0 0 L 0 00 TET V V0 00 V 0 V 0 V V V V V V V V V V V V V V VP VREF VREFQ V V 0 V V V V V0 0 V V V V V V V V V V V0 V V V V V V 0 V V V V V0 V V V V V V V V V V 0 V0 V V V V V V V V V V V0 V VTT 0 VTT 0 WE# 0.UF/0V 0.UF/0V 0 0.UF/0V 0 0.UF/0V UF/.V UF/.V R0 R0 0.UF/0V 0.UF/0V JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL R0 % R0 % 0UF/.V 0UF/.V UF/.V UF/.V.UF/0V.UF/0V UF/.V UF/.V 0 0UF/.V 0 0UF/.V J0 R_IMM_0P J0 R_IMM_0P 0 0/P 0 /# # K#0 0 K# 0 K0 0 K 0 KE0 KE M0 M M M M M M 0 M Q0 Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q Q0 Q Q Q Q Q Q Q 0 Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q Q Q Q Q#0 0 Q# Q# Q# Q# Q# Q# Q# Q0 Q Q Q Q Q Q Q 0PF/0V 0PF/0V + E0 0UF/V ER=0mOhm/Ir=. + E0 0UF/V ER=0mOhm/Ir=. 0 0.UF/0V 0 0.UF/0V 0UF/.V 0UF/.V 0UF/.V 0UF/.V R0 % R0 % R0 0KOhm R0 0KOhm 0 0.UF/0V 0 0.UF/0V 0 0.UF/0V 0 0.UF/0V

17 M Q M Q M Q0 M M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q0 M Q0 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q# M Q M M M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q# M Q M Q M Q M Q M M M Q M Q M Q M Q M M M Q M M M M M M M M M M0 M Q M Q# M Q M Q M Q M Q M Q# M Q# M Q#0 M Q M Q# M Q0 M Q# M Q M M M M M M M 0 M M M M M 0 M M M M Q0 M Q M Q M Q M Q0 M Q M Q M Q M_LK_R M_LK_R# M_LK_R M_LK_R# M WE# <> M_# <> M_LK_R <> M_KE <> M_LK_R# <> M_LK_R <> M_KE <> M # <> M R# <> M_LK_R# <> M_# <> M_OT <> M_OT <> M_T_ <,,,,,,,> M_LK_ <,,,,,,,> M M[:0] <> M Q#[:0] <> M Q[:0] <> M <> M 0 <> M <> M_RMRT# <,> M [:0] <> M Q[:0] <> PM_EXTT#0 <,> +V <,,0,,> +.V_R <,> M_VREF_IMM <> +0.V <,,> M_VREFQ_IMM <> +.V <,,,,,> +0.V +0.V +.V_R +.V_R M_VREF_IMM M_VREFQ_IMM +.V_R +V +V +V +.V_R M_VREF_IMM +0.V M_VREFQ_IMM +.V ate: heet of Friday, July, 00 U/R R()_O-IMM. 0J ate: heet of Friday, July, 00 U/R R()_O-IMM. 0J ate: heet of Friday, July, 00 U/R R()_O-IMM. 0J Mus lave ddress: H Layout Note: Place these caps near O IMM Layout Note: Place these caps near O IMM H:.mm 0 PLE LOE TO OIMM R.0-- R.0-- R.0-- R.0-- R.0-- R.0-- RX0 RX0 0 0.UF/0V 0 0.UF/0V UF/.V UF/.V 0UF/.V 0UF/.V 0UF/.V 0UF/.V 0 0.UF/0V 0 0.UF/0V.UF/0V.UF/0V UF/.V UF/.V.UF/0V.UF/0V UF/.V UF/.V J0 R_IMM_0P J0 R_IMM_0P 0 0/P 0 /# # K#0 0 K# 0 K0 0 K 0 KE0 KE M0 M M M M M M 0 M Q0 Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q Q0 Q Q Q Q Q Q Q 0 Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q Q Q Q Q#0 0 Q# Q# Q# Q# Q# Q# Q# Q0 Q Q Q Q Q Q Q 0 0.UF/0V 0 0.UF/0V R0 0KOhm R0 0KOhm.UF/0V.UF/0V 0.UF/0V 0.UF/0V 0UF/.V 0UF/.V 0.UF/0V 0.UF/0V R0 % R0 % + E0 0UF/V ER=0mOhm/Ir=. + E0 0UF/V ER=0mOhm/Ir=. 0 0UF/.V 0 0UF/.V 0UF/.V 0UF/.V 0PF/0V 0PF/0V 0 0PF/0V 0 0PF/0V 0 0UF/.V 0 0UF/.V UF/.V UF/.V J0 R_IMM_0P J0 R_IMM_0P EVENT# N 0 N 0 N N NP_N 0 NP_N 0 OT0 OT 0 R# 0 REET# 0 #0 # 0 0 L 0 00 TET V V0 00 V 0 V 0 V V V V V V V V V V V V V V VP VREF VREFQ V V 0 V V V V V0 0 V V V V V V V V V V V0 V V V V V V 0 V V V V V0 V V V V V V V V V V 0 V0 V V V V V V V V V V V0 V VTT 0 VTT 0 WE# 0.UF/0V 0.UF/0V R0 % R0 % R0 0KOhm R0 0KOhm 0 0.UF/0V 0 0.UF/0V

18 +.V_R +.V_R <,> M_VREF_IMM0 M_VREF_IMM0 <> R Vref M_VREFQ_IMM0 M_VREF_IMM M_VREFQ_IMM M_VREFQ_IMM0 <> M_VREF_IMM <> M_VREFQ_IMM <> Intel ocument Number: 00 alpella larksfield R O-IMM VREFQ Platform esign uide hange etails +V +VU +V +V <,,,,,,,,> +VU <,,,> +V <,,,,> efault M M_VREF M_VREF_R R.0-- M_VREF_IMM0 <> M_VREF R0 M: Fixed O-IMM VREF_Q (efault tuffing) *Option: Mount=R0,R0,R0,R0,R0 Unmount=R0,R0,R0,R0,0 P00 M_VREF_IMM R00 P0 R00 For R_VREF command & address. R0,R0 are always mount. +.V_R R0 KOHM M_VREFQ_IMM0 R.0-- M_VREFQ_IMM P0 R00 P0 R UF/0V R0 KOHM <> IMM0_VREF_Q R0 <> IMM_VREF_Q R0 M M: Programmable O-IMM VREFQ on motherboard New Requirement *Option: Mount=R0,R0,R0,R0,R0,R0,0 Unmount=R0,R0,R0 *Range from 00 to 00 mv *efault startup value needs to adhere to JEE spec. (power sequencing and +/-% of Vdd/) M M: Processor enerated O-IMM VREFQ New Requirement Option: Mount=R0,R0,R0,R0 Unmount=R0,R0,R0,R0,R0,0 Note: Use voltage divider instead of I solution. R.-- U/R R()_/Q Voltage 0J Friday, July, 00 ate: heet of.

19 lock iagram M_LK_ M_T_ PU PU_VI0~ M VR_I0~ Voltage Regulator O U LK en. O/U pin Internal Pull own Reserved 0 ohm R to bypass +VTT_PU +V +VTT_PU <,,,,,,,,,> +V <,,0,,> <> <> <> <> <> <> <> PU_VI PU_VI PU_VI PU_VI PU_VI PU_VI PU_VI0 PU_VI PU_VI PU_VI PU_VI PU_VI PU_VI PU_VI0 L00 VR_VI 00 L0 VR_VI 00 L0 VR_VI 00 L0 VR_VI 00 L0 VR_VI 00 L0 VR_VI 00 L0 VR_VI0 00 VR_VI <0> VR_VI <0> VR_VI <0> VR_VI <0> VR_VI <0> VR_VI <0> VR_VI0 <0> R.-- U/R VI ontroller 0J Friday, July, 00 ate: heet of.

20 RT battery J00 IE IE +RTT +V 00 R00 KOhm +RT_T T +V_RT 00 UF/0V +.0V +V_RT +V +.0VM_OR +.0V <,,,,> +V_RT <> +V <,,0,,> +.0VM_OR <> Wto_ON_P N -00K000 N N +VTT_PH_VIO +VM_PI +VTT_PH_VIO <,> +VM_PI <> +V_RT RTRT# R delay should be ms~ms R00 0KOhm % 00 UF/0V JRT00 L_JUMP Request by for MO clear function MO ettings lear MO Keep MO JRT00 hunt Open (efault) N 00 PF/0V X00.Khz R00 0MOhm U00 R00 0KOhm % R00 MOhm N N TPM ettings 00 UF/0V lear ME RT Registers Keep ME RT Registers N N <> Z_LK_U <> Z_YN_U <,> Z_RT#_U <> Z_OUT_U <0> Z_LK_V <0> Z_YN_V <0> Z_RT#_V <0> Z_OUT_V JRT00 hunt JRT00 L_JUMP Open (efault) OHM OHM OHM OHM OHM OHM OHM OHM R.0-- RNX000 RNX000 RNX000 RNX000 RNX00 RNX00 RNX00 RNX00 Z_LK Z_YN Z_RT# Z_OUT <0> PH_PI_OV <> +VM_PI _PKR H_YN: elect VVRM.V or.v +V N <> <> <> <> N +V R00 0KOhm Q00 PI_LK PI_#0 PI_# PI_I 00 PF/0V R00 KOhm N00ET R0 KOhm +V_RT T00 T00 T00 T00 T00 <> <0> Z_IN0_U Z_IN_V T00 T00 <> R00 R.0-- H_OK_EN# PU_PWR_EN_R PH_JT_TK_UF Ohm PI_O T00 Ohm X_RT X_RT RTRT# RTRT# M_INTRUER# Z_LK Z_YN Z_RT# Z_IN_M Z_OUT _PILK RN00 RN00 0KOhm PI_MOI _PI0# _PI# RTX RTX RTRT# RTRT# INTRUER# INTVRMEN 0 H_LK H_YN P PKR 0 H_RT# 0 H_IN0 F0 H_IN E H_IN F H_IN H_O RT IH H H_OK_EN#/PIO J0 H_OK_RT#/PIO M JT_TK K JT_TM K JT_TI J JT_TO J JT_RT# PI_LK V PI_0# Y PI_# Y PI_MOI V PI_MIO IEXPEK-M PI JT LP T FWH0/L0 FWH/L FWH/L FWH/L FWH/LFRME# LRQ0# LRQ#/PIO ERIRQ T0RXN T0RXP T0TXN T0TXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TIOMPO TIOMPI TLE# T0P/PIO TP/PIO F K K K K H H H H F F F F H H F F F F T Y V LP_0 <0,> LP_ <0,> LP_ <0,> LP_ <0,> LP_FRME# <0,> PH_RQ#0 T00 LP_RQ# T00 INT_ERIRQ <0> T_RXN0 <> T_RXP0 <> T_TXN0 <> H T_TXP0 <> T_RXN <> T_RXP <> T_TXN <> O T_TXP <> E.0: T port,port may not be available in all PH KUs. T_RXN <> T_RXP <> T_TXN <> H T_TXP <> T_RXN <> T_RXP <> T_TXN <> ET T_TXP <> +VTT_PH_VIO T_OMP.Ohm % R00 +V 0KOhm R0 T_LE# <> T0P TP H_OK_EN# R.0 R0 KOhm +V MoW_WW0_0' N INT_ERIRQ 0KOhm R0 trap information: T0P 0KOhm R0 H_PKR: No reboot strap Low: isable. High:Enable TP 0KOhm R0 H_OK_EN#:.Flash descriptor security: ampled low: override ampled high: in effect..pio low on the rising edge of PWROK, Will also disable Intel ME. PI_MOI: itpm strap. Mount R0: Enable Unmount R0: isable(default) U/R PH()_T,IH,RT,LP 0J Friday, July, 00 ate: heet of 0.

21 PIE: PIE--> +VU +V +VTT_PH_OR +VU <,0,,,,,,,> +V <,,0,,> +VTT_PH_OR <,,> U00 +VU_OR +VU_OR <,,,> <> <> <> <> <> <> <> <> PIE_RXN_TV PIE_RXP_TV PIE_TXN_ PIE_TXP_ PIE_RXN_WLN PIE_RXP_WLN <> PIE_TXN_ <> PIE_TXP_ PIE_RXN_NEWR PIE_RXP_NEWR <> PIE_TXN_ <> PIE_TXP_ 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V X0 X0 X0 X0 X0 X0 PIE_TXN_TV PIE_TXP_TV PIE_TXN_WLN PIE_TXP_WLN PIE_TXN_NEWR PIE_TXP_NEWR 0 J0 F H W U0 T0 U V E PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP Mus MLERT#/PIO MLK MT ML0LERT#/PIO0 ML0LK ML0T MLLERT#/PIO MLLK/PIO MLT/PIO H J M E0 EXT_I# L ML0LERT# ML0_LK ML0_T MLLERT# ML_LK ML_T T0 T0 T0 T0 EXT_I# <0> L_ <> _ <> ML_LK <> ML_T <> To E R.-- <> <> <> <> <,> <> <> <> PIE_RXN_LN <> PIE_RXP_LN <> PIE_TXN_ <> PIE_TXP_ LK_PIE_TV#_PH LK_PIE_TV_PH <> LKREQ_TV# LK_PIE_WLN#_PH LK_PIE_WLN_PH <> <0> PIE_RXN_R <0> PIE_RXP_R <0> PIE_TXN_ <0> PIE_TXP_ LKREQ_WLN# LK_PIE_NEWR#_PH LK_PIE_NEWR_PH LKREQ_NEWR# R.-- <0> <0> <0> LK_PIE_R# LK_PIE_R LK_REQ#_ R.-- <> LK_PIE_LN# <> LK_PIE_LN <> LK_REQ_LN# 0.UF/V 0.UF/V 0.UF/0V 0.UF/0V X X LKREQ_R# LK_REQ_LN# PIE_TXN_R PIE_TXP_R PIE_TXN_LN PIE_TXP_LN E.0: PIE, may not be availiable in all PH KUs. T0 T0 X X LK_REQ0# LK_PH_R_N LK_PH_R_P LK_PH_R_N LK_PH_R_P LK_PH_R_N LK_PH_R_P LK_PH_R_N LK_PH_R_P LK_PH_R_N LK_PH_R_P LKREQ_LN#_R F H J W T U U V J J K K P M M U M M N H H M M M J0 J H K K P PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP LKOUT_PIE0N LKOUT_PIE0P PI-E* PIELKRQ0#/PIO LKOUT_PIEN LKOUT_PIEP PIELKRQ#/PIO LKOUT_PIEN LKOUT_PIEP PIELKRQ#/PIO0 LKOUT_PIEN LKOUT_PIEP PIELKRQ#/PIO LKOUT_PIEN LKOUT_PIEP PIELKRQ#/PIO LKOUT_PIEN LKOUT_PIEP PIELKRQ#/PIO LKOUT_PE N LKOUT_PE P PE LKRQ#/PIO From LK UFFER lock Flex ontroller PE Link L_LK L_T L_RT# PE LKRQ#/PIO LKOUT_PE N LKOUT_PE P LKOUT_MI_N LKOUT_MI_P LKOUT_P_N/LKOUT_LK_N LKOUT_P_P/LKOUT_LK_P LKIN_MI_N LKIN_MI_P LKIN_LK_N LKIN_LK_P LKIN_OT_N LKIN_OT_P LKIN_T_N/K_N LKIN_T_P/K_P REFLKIN LKIN_PILOOPK XTL_IN XTL_OUT XLK_ROMP LKOUTFLEX0/PIO LKOUTFLEX/PIO LKOUTFLEX/PIO LKOUTFLEX/PIO T T T H N N T T W P P F E H H P J H H F XLK_OMP T LK_OUT0 P LK_OUT T LK_OUT N0 LK_OUT R 0.Ohm % R T T0 T0 Ohm R.0 L_LK <> L_T <> L_RT# <> LKREQ_PE# <0> LK_PIE_PE#_PH <0> LK_PIE_PE_PH <0> LK_MI#_PH <> LK_MI_PH <> LK_MI# <> LK_MI <> LK_PH_LK# <> LK_PH_LK <> LK_OT# <> LK_OT <> LK_T# <> LK_T <> LK_IH <> LK_PI_F <> +VTT_PH_OR LK_ <> U 0 PF/0V X0 MOhm Mhz R U U U 0 PF/0V N EXT_I# L MLLERT# ML0_LK ML0_T ML_LK ML_T MLLERT# PH LKREQ etting: Not connected to device. LK_REQ0# LKREQ_LN#_R R R 0KOhm.KOhm.KOhm 0KOhm.KOhm.KOhm.KOhm.KOhm 0KOhm +VU_OR R0 R R R R0 R R R R R. -- +VU_OR 0KOhm 0KOhm R.-- IEXPEK-M onnected to device. efault : lock free run. (P 0K). Reserver 0K PU for power saving purpose. +V LKREQ_TV# LKREQ_WLN# R 0KOhm R 0KOhm +VU_OR LKREQ_NEWR# R 0KOhm LK_REQ#_ LK_REQ_LN# LKREQ_TV# LKREQ_WLN# LKREQ_NEWR# LK_REQ_LN# LK_REQ#_ LKREQ_PE# R R R R R R R R 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm R.-- N U/R PH()_PIE,LK,M,PE 0J Friday, July, 00 ate: heet of.

22 pre-e not support Reversal Feature PM_LKRUN# PM_PWROK R.KOhm R 0KOhm +V N R. -- <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP J W0 J0 0 0 E F 0 E H 0 U00 MI0RXN MIRXN MIRXN MIRXN MI0RXP MIRXP MIRXP MIRXP MI0TXN MITXN MITXN MITXN MI0TXP MITXP MITXP MITXP FI_RXN0 FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXP0 FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_INT H J E F W J +VU_OR +VTT_PH_OR <,> +V XP_REET# R KOhm 0 R0.Ohm % R MI_OMP +V R. -- KOhm R Y_REET# H F T MI_ZOMP MI_IROMP Y_REET# MI FI FI_FYN0 FI_FYN FI_LYN0 FI_LYN WKE# F H J J PIE_WKE# <,,> PM_RI# PM_TLOW# PIE_WKE# ME_PM_LP_M# ME_UPWRNK ME PREENT R 0KOhm R.KOhm R KOhm R IMT 0KOhm R 0KOhm R 0KOhm R.-- <0,> LL_YTEM_PWR <> <0> <0> PM_PWROK H_RM_PWR <0> ME_PWROK PM_RMRT# ME_UPWRNK <> PM_PWRTN#_R <0> PM_PWRTN# <0> ME PREENT N R 00 L0 L00 00 R R R.0-- MPWROK_R UXPWROK_R 0KOhm L0 00 L0 00 L0 00 T0 PM_RMRT#_R R.-- R.0-- ME PREENT PM_TLOW# M K 0 M P P Y_PWROK PWROK MEPWROK LN_RT# RMPWROK RMRT# U_PWR_K/PIO0 PWRTN# PREENT/PIO TLOW#/PIO ystem Power Management LKRUN#/PIO U_TT#/PIO ULK/PIO LP_#/PIO LP_# LP_# LP_M# TP PMYNH Y P F E H P K N J0 PM_U_TT# U_LK LP_# LP_#_R LP_#_R LP_M#_R PM_LP_W# L0 00 L0 00 L0 00 R.0-- T0 T0 T0 T0 PM_LKRUN# <0> PM_U# <0> PM_U# <0> ME_PM_LP_M# PM_YN# <> R ME_PM_LP_LN# IMT 0KOhm TUFF for IMT T0 PM_RI# F RI# IEXPEK-M LP_LN# F ME_PM_LP_LN# ME_PM_LP_LN# <,> +VU_OR +V +VTT_PH_OR +VU_OR <,,,> +V <,,0,,> +VTT_PH_OR <,,> U/R PH()_FI,MI,Y PWR 0J Friday, July, 00 ate: heet of.

23 +V +V <,,0,,> R.0-- U00 +V T0 T0 L_TRL_LK L_TRL_T T T Y Y V L_KLTEN L_V_EN L_KLTTL L LK L T L_TRL_LK L_TRL_T VO_TVLKINN VO_TVLKINP VO_TLLN VO_TLLP VO_INTN VO_INTP J J F H L_TRL_LK L_TRL_T R 0KOhm R 0KOhm P P T T V V Y V 0 Y V P P Y T U T Y T U0 T LV_I LV_V LV_VREFH LV_VREFL LV_LK# LV_LK LV_T#0 LV_T# LV_T# LV_T# LV_T0 LV_T LV_T LV_T LV_LK# LV_LK LV_T#0 LV_T# LV_T# LV_T# LV_T0 LV_T LV_T LV_T LV igital isplay Interface VO_TRLLK VO_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P T T J U J 0 0 W Y E V0 E0 0 F H isplay Port isplay Port VO RT_LUE RT_REEN RT_RE P_TRLLK P_TRLT U0 U R N KOHM 0.% V RT LK V RT T Y RT_HYN Y RT_VYN _IREF RT_IRTN IEXPEK-M RT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P T J0 0 J F H E R.-- isplay Port N R R0., R0.: K+/-0.% Intel checklist recommand:.0k P resistor to 0.% isplay Port isable: (For discrete graphic). N: LL LV isable: (For discrete graphic). N: LV_T [:0], LV_T# [:0], LV_LK, LV_LK#, LV_T [:0], LV_T# [:0], LV_LK, LV_LK# L_V_EN, L_KLTEN, L_KLTTL, LV_VREFH LV_VREFL, LV_I, LV_V. onnected to N: VccLV,VccTX_LV RT isable: (For discrete graphic). N: RT_RE,RT_REEN,RT_LUE RT_HYN,RT_VYN. -kω ±0.% pull-down to N: _IREF. onnected to N: RT_ITRN. onnect to +V.: V U/R PH()_P,LV,RT 0J Friday, July, 00 ate: heet of.

24 +VU +V +VU <,0,,,,,,,> +V <,,0,,> change to PI_LK to sync I <> LK_PPI <> LK_PI_F <0> LK_KPI_PH <> LK_EU <> LK_PI T R. -- H0 N J 0 E H E0 0 M M F M0 M J K F0 K M J K L F J0 F M H U00E PI NVRM R.-- +V_NVRM_VQ J0 Y /E0# NV_WR#0_RE# Y /E# NV_WR#_RE# H /E# V /E# NV_WE#_K0 F PI_INT# NV_WE#_K PI_INT# PIRQ# H PI_INT# PIRQ# PI_INT# PIRQ# UP0N H U_PN0 <> U_PP0 <> U port(io/) PIRQ# UP0P J PI_REQ0# UPN U_PN <> F U_PP <> U port(io/) PI_REQ# REQ0# UPP PU_ELET#_R REQ#/PIO0 UPN N0 U_PN <> PI_REQ# REQ#/PIO UPP P0 U_PP <> U port M REQ#/PIO UPN J0 U_PN <> U_PP <> PI_NT0# UPP L0 U port F U_PN <> PI_NT# NT0# UPN F0 K U_PP <> TV turner T0 PI_NT# NT#/PIO UPP 0 F U_PN <> PI_NT# NT#/PIO UPN 0 H U_PP <> Newcard NT#/PIO UPP 0 R.-- T0 PI_INTE# UPN M T PI_INTF# PIRQE#/PIO UPP N K U_PN T0 PI_INT# PIRQF#/PIO UPN U_PP T0 PI_INTH# PIRQ#/PIO UPP U_PN UPN H T0 PIRQH#/PIO U_PP T0 UPP J K PIRT# UPN E U_PN <> U_PP <> WiFi/WiMax PI_ERR# UPP F E U_PN0 T0 PI_PERR# ERR# UP0N E0 U_PP0 T0 PERR# UP0P U_PN UPN T0 U_PP PI_IRY# UPP H T0 IRY# UPN L U_PN <> H U_PP <> T PI_EVEL# PR UPP M F U_PN <> PI_FRME# EVEL# UPN FRME# UPP U_PP <> amera R.--0 PI_LOK# PLOK# PI_TOP# URI# PI_TRY# TOP# URI_PN TRY# URI R N.Ohm % Place within 00 mils of PH M PME# N 0KOHM RN0 PLT_RT# O0#/PIO J PLTRT# O#/PIO0 0KOHM RN0 F Ohm RX0 LK_PPI_R O#/PIO Ohm RX0 LK_PI_F_R 0KOHM RN0 N L LKOUT_PI0 O#/PIO 0KOHM RN0 LK_KPI_PH_R 0KOHM RN0 P E Ohm RX0 LKOUT_PI O#/PIO P Ohm RX0 LK_EU_R LKOUT_PI O#/PIO P F LK_PI_R LKOUT_PI O#/PIO0 0KOHM RN0 P T LKOUT_PI O#/PIO 0KOHM R.0 0KOHM RN0 Ohm RX0 RN0 U NV_E#0 NV_E# NV_E# NV_E# NV_Q0 NV_Q NV_Q0/NV_IO0 NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q0/NV_IO0 NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_LE NV_LE NV_ROMP NV_R# Y P V P P T T V E J J Y U V +V +VU_OR +V <,,,,,,,> +V_NVRM_VQ <> +VU_OR <,,,> +VU_OR PI_INT# PI_INT# PI_INT# PI_TOP# PI_PERR# PI_LOK# PI_EVEL# PI_ERR# PI_INTE# PI_IRY# PI_INT# PI_REQ0# PI_INT# PI_INTF# PI_REQ# PI_REQ# PI_FRME# PI_TRY# PI_INTH# PU_ELET#_R.KOHM RN0.KOHM RN0.KOHM RN0.KOHM RN0.KOHM RN0.KOHM RN0.KOHM RN0.KOHM RN0.KOHM RN0.KOHM RN0.KOHM RN0.KOHM RN0.KOHM RN0.KOHM RN0.KOHM RN0.KOHM RN0.KOHM RN0.KOHM RN0.KOHM RN0.KOHM RN0 R0 0KOhm +V IEXPEK-M 0PF/0V 0 0PF/0V 0 0PF/0V 0 0PF/0V 0 0PF/0V 0 N N N NN NT0#,NT#: oot IO trap. oot IO trap PI_NT# PI_NT0# oot IO Location 0 0 LP 0 PI 0 Reserved PI (PH) NT#: swap override trap/ Top-lock swap override jumper Low=Enabled swap override/ Top-lock swap override High=efault +V ampled on rising edge of PWROK. PI_NT0# R0 KOhm PI_NT# R KOhm N PI_NT# R KOhm N PLT_RT# PLT_RT# N U0 V N Y NZ0PX_NL UF_PLT_RT# <,,0,,,,0,,,,0> R U/R PH()_PI,NVRM,U 0J Friday, July, 00 ate: heet of.

25 +V R 0KOhm +V R 0KOhm I0 I KU F_Non-IMT 0 F_IMT 0 U_Non-IMT U_IMT R.-- T T0 T0 TPT T <0> EXT_MI# R.-- T OKIN_ET# PU_PWR_EN XIE_Y_IN# PM_LNPHY_EN Y J F0 K U00F MUY#/PIO0 TH/PIO TH/PIO TH/PIO PIO MI LN_PHY_PWR_TRL/PIO LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP 0TE H H F F U 0TE <0> R R 0KOhm 0KOhm R.-- N N P_I0 P_I PIO :Enable VVRM,Low=disable. efault internal pull up. <> <> R.-- <> R.-- <> <> T_LE WLN_LE WLN_ON TP_PI# T_LK_REQ# R.-- T T T00 PU_HOL_RT# PU_PWROK O_LN_RT# VRM_EN TP_PI# L0 T_LK_REQ#_R 00 PU_PWR_EN# PU_PRNT# T F Y H0 V M V PIO TP/PIO TH0/PIO LOK/PIO MEM_LE/PIO PIO PIO TP_PI#/PIO PIO TLKREQ#/PIO TP/PIO TP/PIO PU LKOUT_LK0_N/LKOUT_PIEN LKOUT_LK0_P/LKOUT_PIEP PEI RIN# PROPWR THRMTRIP# TP TP M M 0 T E0 0 W PEI L00 00 R.0-- PM_THRMTRIP# T T LK_PU_N_PH <> LK_PU_P_PH <> H_PEI <,0> RIN# <0> H_PUPWR <,> Ohm R0 Ohm R close to U00.0 +VTT_PU H_THRMTRIP# <,> P_I0 V LO/PIO TP T P_I P TOUT0/PIO TP Y T T LK_REQ# H PIELKRQ#/PIO TP Y T T LK_REQ# F PIELKRQ#/PIO TP V T R.-- <> T T00 T_ON TPT EMIL_LE TEMP_LERT# F TOUT/PIO TP/PIO PIO TP TP TP V F M TP_PH T T T TP0 N TP0_PH T EXT_MI# +VU_OR 0KOhm R +V T T T T T T T T T0 T T T T T T T0 T T T T T T T T T T0 T T TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF0 TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF0 TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF TP_V_NTF0 TP_V_NTF 0 E E F F H H H H J J J J J J0 J J E E V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ IEXPEK-M NTF RV TP TP TP TP TP TP TP TP TP N_ N_ N_ N_ N_ INIT_V# TP J K K M N M0 N0 H T P 0 TP_PH TP_PH TP_PH TP_PH TP_PH TP_PH TP_PH TP_PH_N TP_PH_N TP_PH_N TP_PH_N TP_PH_N INT_V# TP_PH_T T T0 T T T T T T0 T T T T T T T T PU_PWR_EN R.-- 0KOhm R PU_HOL_RT# 0KOhm R0 PU_PRNT# R.-- 0KOhm R +V +VU +VTT_PU +V <,,0,,> +VU <,0,,,,,,,> +VTT_PU <,,,,,,,,> R.-- +VU_OR +VU_OR <,,,> R0 PWR_OK_V <> PU_PWROK R 0KOhm T_LK_REQ# R 0KOhm R.-- 0'WW0 MoW N U/R PH()_PU,PIO,MI 0J Friday, July, 00 ate: heet of.

26 +.0V <,,,> +VTT_PH_VIO <0,> +VTT_PH_OR <,,> +.V <,,,0,> +.V <,,,,> +V <,,0,,> +VTT_PU <,,,,,,,,> +V_NVRM_VQ +VTT_PH_VPLL_EXP +VTT_PH_VPLL_FI +VTT_PH_VPLL_EXP +VTT_PH_V +VTT_PH_VPLL_FI +VTT_PH_VIO N +VTT_PH_VIO N +V_V N +VTT_PH_VIO +VTT_PH_OR +VTT_PH_OR N +VFI_VRM N +.V +VTT_PH_.V_.V +.V +VTT_PH_OR +V_V_IO +V N +VTT_PU +V +VM_VPEP N N N +VTT_PU_V_MI +VTT_PH_OR N N +.V_VMI_VRM N N +V N N N +V N N +.0V +VTT_PH_V +VTT_PH_OR +VTT_PH_OR +VTT_PH_VIO +V +VFI_VRM +.V_VMI_VRM +.V_VT_LV +V_V_LV N +V +V_NVRM_VPNN +V_NVRM_VQ +.0V +VTT_PH_VIO +VTT_PH_OR +.V +.V +V +VTT_PU +V_NVRM_VQ +.V +.V +V_NVRM_VQ +VM +VM ate: heet of Friday, July, 00 U/R PH()_POWER,N. 0J ate: heet of Friday, July, 00 U/R PH()_POWER,N. 0J ate: heet of Friday, July, 00 U/R PH()_POWER,N. 0J. 0 max m 0 idle 00m 0 max m 0 max m 0 max m 0 max m 0 max m 0 max m 0 max +VTT_PH_VPLL_EXP.. 0 max +VTT_PH_V_EXP.0 0 max R.-- R.-- R.0-- R.0-- R.0-- R.0-- R.0-- R.0-- R.0-- R.0-- R.0-- R.0-- R.0-- P0 R00 P0 R00 0.UF/0V 0.UF/0V P0 R00 F P0 R00 F L0 KOhm/00Mhz L0 KOhm/00Mhz R R 0 UF/.V 0 UF/.V 0 0UF/.V 0 0UF/.V P0 R00 F P0 R00 F JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL P0 R00 P0 R00 JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL 0 UF/.V 0 UF/.V UF/.V UF/.V 0 0UF/.V 0 0UF/.V 0.UF/0V 0.UF/0V 0 UF/.V 0 UF/.V POWER V ORE MI PI E* RT LV FI NN / PI HVMO U00 IEXPEK-M POWER V ORE MI PI E* RT LV FI NN / PI HVMO U00 IEXPEK-M VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] F VORE[] F VORE[] F0 VORE[] F VORE[0] H VORE[] H VORE[] H0 VORE[] H VORE[] J0 VORE[] J VPNN[] K VPNN[] K0 VIO[] N VIO[] N VIO[] N VIO[0] N VIO[] N0 VIO[] N VIO[] T VIO[] T VIO[] U VIO[] U VIO[] V VIO[] V VIO[] W VIO[0] W VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] E VIO[0] E VIO[] VIO[] VIO[] H VIO[] J VIO[] J V[] E0 V[] E VTX_LV[] P VTX_LV[] P VLV H VVRM[] T VVRM[] T VPLLEXP J VFIPLL J VPNN[] K VPNN[] K VPNN[] M VPNN[] M VIO[] K VTX_LV[] T VTX_LV[] T V_[] F V_LV H V_[] F VIO[] M V_[] V_[] V_[] V_[] N VME_[] M VME_[] M VME_[] P VME_[] P VPNN[] K VPNN[] M VPNN[] M VMI[] T VMI[] U VIO[] N0 VIO[] N 0 0UF/.V 0 0UF/.V R R JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL P R00 P R00 R R P0 R00 P0 R00 R R R R L0 KOhm/00Mhz L0 KOhm/00Mhz R R 0 0UF/.V 0 0UF/.V P0 R00 P0 R00 0.UF/0V 0.UF/0V P R00 P R00 P R00 P R00 0 0UF/.V 0 0UF/.V 0 UF/.V 0 UF/.V 0 0.0UF/V 0 0.0UF/V P0 R00 P0 R00 0 UF/.V 0 UF/.V L0 KOhm/00Mhz L0 KOhm/00Mhz U00H IEXPEK-M U00H IEXPEK-M V[] V[] 0 V[] V[] V[] V[] V[] 0 V[] V[0] V[] V[] V[] V[] 0 V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] 0 V[] V[0] V[] V[] V[] V[] V[] V[] E V[] E V[] F V[] F V[] P V[] F V[] F V[] F V[] F V[0] F V[] V[] V[] H V[] H V[] H V[] H V[] H V[] H V[0] H V[] H V[] J V[] J V[] J0 V[] J V[] J V[] J V[] J V[] J V[0] J V[] T V[] J V[] K V[] K V[] K V[] K V[] K V[0] K0 V[] K V[] K V[] K V[] K V[] K V[] K V[] K V[] K V[] K V[0] K V[] L V[] L V[] M V[] M0 V[] M V[] M V[] M V[00] M V[0] M0 V[0] M V[0] M V[0] M V[0] M V[0] M V[0] M V[0] M V[0] U0 V[] M V[] V V[] M V[] M V[] 0 V[] N V[] N0 V[] N V[0] P V[] P V[] P V[] P V[] P V[] P V[] R V[] R V[] T V[] T V[] T V[] T V[] T V[] T V[] V V[] V V[] V0 V[] V V[0] V0 V[] V V[] V V[] V V[] V V[] V V[] V V[] V V[] W V[] W V[0] W V[] F V[] W V[] W V[] W0 V[] W V[] Y V[] Y V[] Y V[0] Y V[] U V[] N V[] 0 V[0] V[] V V[] U V[] M V[] M V[] N V[] H V[] V[0] H V[0] V[] V[] P0 R00 P0 R00 0.UF/0V 0.UF/0V P R00 P R00 P0 R00 P0 R00 P00 R00 P00 R00

27 TP_PH_VW +V.0_INT_VU +VT PRT +.0VM_OR_R +.0VM_OR_R +.0VM_OR_R +.0VM_OR_R +VTT_PH_V PL +VTT_PH_V PL +V <,,0,,> +.0V <,,,> +VTT_PU <,,,,,,,,> +VTT_PH_VIO <0,> +VTT_PH_OR <,,> +VU <0,,,,,,,> +V_RT <0> +VU <,,> +V <0,,,,,,0,,,,0,0,> +.0VM_OR +VU_OR <,,,> +VU_OR +.0VM <,,,> +V_VPU +.0VM_OR +VTT_PH_V_LK +.0VM_VUX +VTT_PU_VPPU N N N +V_RT +VTT_PH_VIO N N N N N +V_V_ +.0VM_OR N N N N +VTT_PU +VTT_PH_.V_.V +VU_OR N N N N N N N N +VTT_PH_V PL +VTT_PH_V PL N +VTT_PH_VPLL +V_PH_VREF +VU_VPU +VTT_PH_VIO N +VTT_PH_VIO N +VTT_PH_OR +V N N +VU_OR N N N N +.0VM_OR N +VU_OR +V_V_ N +VU_OR +VTT_PH_VIO +V_V_ +V N +VPLLVRM +VU_PH_VREFU +VTT_PH_OR N N +VTT_PH_V PL +VTT_PH_V PL N N +VTT_PH_OR N N +VTT_PH_.V_.V +VPLLVRM +.0V +.0VM_OR +V +V_V_ +VU_H +VU_OR +V +.0V +VTT_PU +VTT_PH_VIO +VTT_PH_OR +VU +V_RT +VU +V +.0VM_OR +VU +VU_OR +VU +VU_OR +VU_OR +VU_OR +.0VM +.0VM ate: heet of Friday, July, 00 U/R PH()_POWER,N. 0J ate: heet of Friday, July, 00 U/R PH()_POWER,N. 0J ate: heet of Friday, July, 00 U/R PH()_POWER,N. 0J m 0 max m 0 max 0 max m 0 max m 0 max?? +.VM_VEPW >m 0 max m 0 max +VTT_PH_V.+m 0 max m 0 max +VTT_PH_VUORE m 0 max +VTT_PH_V_T +V_VPPI +V_VPORE 0mil trace R.0-- R.0-- R.0-- R.0-- R.0-- R.0-- R.0-- R.0-- R.0-- R R UF/.V UF/.V 0 0.UF/0V 0 0.UF/0V UF/.V UF/.V 0.UF/0V 0.UF/0V UF/.V UF/.V R0 R0 P0 R00 P0 R00 0.UF/0V 0.UF/0V 0UF/.V 0UF/.V UF/.V UF/.V 0 0.UF/0V 0 0.UF/0V 0.UF/0V 0.UF/0V P0 R00 P0 R00 0.UF/0V 0.UF/0V R R + E0 0UF/V ER=0mOhm/Ir=. + E0 0UF/V ER=0mOhm/Ir=. P0 R00 P0 R00 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL 0 T 0 T 00 0UF/.V 00 0UF/.V UF/.V UF/.V JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL 0.UF/0V 0.UF/0V UF/.V UF/.V UF/.V UF/.V UF/.V UF/.V.UF/.V.UF/.V 0.UF/0V 0.UF/0V L0 KOhm/00Mhz L0 KOhm/00Mhz 0UF/.V 0UF/.V L0 KOhm/00Mhz L0 KOhm/00Mhz UF/.V UF/.V + E0 0UF/V ER=0mOhm/Ir=. + E0 0UF/V ER=0mOhm/Ir=. 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V P00 R00 P00 R00 UF/.V UF/.V R0 R0 P0 R00 P0 R00 0 UF/.V 0 UF/.V JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL P0 R00 P0 R00 UF/.V UF/.V UF/.V UF/.V JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL L0 KOhm/00Mhz L0 KOhm/00Mhz POWER T U lock and Miscellaneous H PU PI/PIO/LP RT PI/PIO/LP U00J IEXPEK-M POWER T U lock and Miscellaneous H PU PI/PIO/LP RT PI/PIO/LP U00J IEXPEK-M PUYP Y0 VME[] VME[] VME[] VME[] F VME[] F VUH L0 VU_[] U VIO[] V VIO[] VIO[] F0 VIO[] F VME[] V VME[] V VME[] V VME[0] Y VME[] Y VME[] Y VREF K V_[] J V_[] L V_[0] M V_[] N V_[] P V_[] U VRT VU_[] VU_[] VU_[] VU_[] VU_[] VU_[] E VU_[] E VU_[0] F VU_[] F VU_[] VU_[] VU_[] H VU_[] H VU_[] J VU_[] J VU_[] L VU_[] L VU_[0] M VU_[] M VU_[] N VU_[] N VU_[] P VU_[] P VU_[] U VU_[] U VU_[] U VU_[] V VIO[] 0 VIO[0] VIO[0] H VPLL[] VPLL[] VIO[] J VREF_U F VIO[] H0 VIO[] VIO[] 0 VIO[] VIO[] F V_[] VIO[] H VVRM[] T0 PU Y VIO[] F VIO[] H VLN[] F VLN[] F VPLL[] VPLL[] VVRM[] U VLK[] P VLK[] P PRT V VIO[] F VME[] F VIO[] H VIO[] H PT V VTPLL[] K VTPLL[] K VME[] VME[] Y VME[] Y VME[] V_[] V V_[] V V_[] Y VU_[] P VU_[0] U VU_[] U0 VU_[] U VIO[] V VIO[] V VIO[] Y VIO[] Y V_PU_IO[] T V_PU_IO[] U P0 R00 P0 R00 0.UF/0V 0.UF/0V 0 T 0 T JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL 0 UF/.V 0 UF/.V R 0 R 0 U00I IEXPEK-M U00I IEXPEK-M V[] Y V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] 0 V[] V[] 0 V[] V[] V[] V[] V[0] V[] 0 V[] V[] V[] V[] V[] V[] V[] 0 V[] V[0] V[] H V[] V[] V[] V[] E V[] E V[] E0 V[] E V[] E0 V[00] E V[0] E V[0] E V[0] E V[0] E V[0] E0 V[0] E V[0] E V[0] F V[0] F V[0] F V[] V[] V[] V[] 0 V[] H V[] H V[] H V[] H V[] H V[0] H V[] H V[] H V[] H V[] H V[] V[] 0 V[] V[] E V[] E V[0] E0 V[] E V[] E0 V[] E V[] E V[] E V[] E V[] E V[] K V[] K V[] L V[] L V[] L V[] L V[0] L V[] L V[] L0 V[] L V[] M V[] M V[] M0 V[] N V[] M V[] M V[0] M V[] M V[] M V[] M V[] M V[] N V[] P V[] P V[] P0 V[0] P V[] P V[] P V[] P V[] P V[] R V[] R V[] T V[] T V[] T V[00] T V[0] T V[0] T V[0] U0 V[0] U V[0] U V[0] U V[0] P V[0] V V[0] P V[0] V V[] V0 V[] V V[] V0 V[] V V[] V V[] V V[] E V[] E V[0] F V[] F V[] 0 V[] V[] V[] V[] V[] V[] V[] 0 V[0] V[] V[] V V[] V V[] V V[0] V V[] V V[] V V[] V V[] V V[] V V[] V V[] W V[] W V[] Y V[0] Y V[] Y V[] Y V[] Y V[] Y V[] Y0 V[] Y V[] Y V[] Y V[] Y V[0] Y V[] Y V[] Y V[] Y V[] P V[] P V[] V[] F V[] H V[] H0 V[] H0 V[] H V[] H V[] H V[] T V[] V[] T V[] V[0] Y V[] T V[] M V[] T V[] M V[] K V[] K V[] V V[] K V[] K V[] H V[0] H V[] J 0.UF/0V 0.UF/0V P0 R00 P0 R00 P0 R00 P0 R00 0UF/.V 0UF/.V L0 KOhm/00Mhz L0 KOhm/00Mhz

28 PH PI ROM +VM_PI R.KOhm U0 +VM_PI R.KOhm 0 0.UF/V L +V 00 +VM R R.0-- +VM_PI 0 T R R.0-- +V +V +VU +VM +VM_PI +V <,,0,,,,,,,,,0,,,,0,,,,,,0,,,,,,,,,0,0,,> +V <,> +VU <,> +VM <,,,,> +VM_PI <0> <0> <0> PI_#0 PI_O R Ohm +VM_PI_0 E# V O HOL# WP# K V I +VM_PI_00 PILK PII PI_LK <0> PI_I <0> TVF00-0- PIO (Mb) <0> PI FROM E For E request. +VM_PI R.KOhm PI_# R +VM_PI_ Ohm U0 E# V O HOL# WP# K V I TVF0 (Mb) +VM_PI R.KOhm 0 0.UF/V +VM_PI_ R.0-- PH <> L_ Q0 UMKN +V +V.KOhm R0.KOhm R0 MU Link device P LKEN EU WLN PU XP PH XP VI ONTROLLER P FM00 ME LE M_LK_ <,,,,,,,> <> _ M_T_ <,,,,,,,> Q0 UMKN +VU PI FLH ON <0,> M_LK ML_LK <> PI_# PI_#0 Ohm Ohm R R +VM_PI J0 PI_#_ON PILK PIO PII HEER_XP_K Put near U0,U0 E <0,> M_T Q0 UMKN Q0 UMKN PH ML_T <> +V +V PI etting for layout: PH U00 ranch as short as possible. Q0 UMKN.KOhm R0.KOhm R0 M_LK_ <0,0> PU,V Thermal M_T_ <0,0> Flash ON J0 PH PI U0 U0 Q0 UMKN E U00 U/R PH()_PI,M 0J Friday, July, 00 ate: heet of.

29 Reserved for new LK EN. +V L0 +VIO_ 00 L0 +VIO_ 00 R.0-- +VTT_PU R R +V 0UF/0V L0 /00Mhz +V_VPIEX 0.UF/V R.0-- +V 0UF/0V 0 0.UF/V 0 0.UF/V 0 0.UF/V 0 0.UF/V U0 VPIEX VPIEX VPIEX PWRVE#* 0 VPU VPI VPI 0UF/0V V VREF PI/PIEX_TOP# PU_TOP# L0 /00Mhz +V_VPI 0.UF/V +V_V +V_VREF TP_PI#_R TP_PU# 0.UF/V R +V 0.UF/V TP_PI# <> 0UF/0V 0 0UF/0V +V_VPI 0.UF/V 0.UF/V Latched Input elect Pin desides pin/: 0 : Pin / = L_ : Pin / = PIe_L0 R0 0KOhm PI R0 0KOhm Pin desides pin/: 0 : Pin / = R LK : Pin / = PU_ITP LK +V +V L UF/V 0 0UF/0V 0 0.UF/V 0 PF/0V +V_V X_LK V N X PUT_LF PU_LF R.-- PIF R R0 0KOhm 0KOhm 0 PF/0V X0.Mhz X_LK X PUT_L0 PU_L0 PUITPT_L/PIeT_L PUITP_L/PIe_L LKPHLK RX Ohm LKPHLK# RX Ohm LK_PH_LK <> LK_PH_LK# <> Pin desides pin/,/: 0 : Pin / = PIe_L Pin / = FIX/ : Pin / = OT_MHz R.-- FIX/L_T/PIeT_L0 /L_/PIe_L0 PEREQ#/PIeT_L PEREQ#/PIe_L PIeT_L PIe_L 0 T_LK_REQ# <> PEREQ# ontrol:(yte,r/w) TLK[bit]: 0=Not controlled,=controlled. PIEX [bit]: 0=Not controlled,=controlled. PIEX0 [bit0]: 0=Not controlled,=controlled. Pin / = L_/PIe_L0 R 0KOhm PIF R0 0KOhm +V FL R0.KOhm FL FL/U_MHz FL/TET_MOE PIeT_L PIe_L PIeT_L PIe_L 0 LKMI LKMI# RX0 Ohm RX Ohm LK_MI <> LK_MI# <> Pin desides pin0/: 0 : Pin 0/ = PIe_L : Pin 0/ = PEREQ#,PEREQ# +V PIeT_L R 0KOhm PI *ELPIEX0_L#PILK PIe_L PIeT_L PI0 R 0KOhm PIe_L K-0 recommend ohm PILK PIeT_L PIe_L 0 R.-- TP_PI#_R RX 0KOhm +V PILK TLKT_L TLK_L TLK TLK# RX Ohm RX Ohm LK_T <> LK_T# <> TP_PU# RX 0KOhm PI0 PILK0/REQ_EL** PIeT_L/OTT_MHzL PIe_L/OT_MHzL LK_PIE RX0 Ohm LK_PIE# RX Ohm LK_OT <> LK_OT# <> +V Reserved for R.0 ebug LK F FL FL FL 0 0 PIF *ELL_#/PILK_F *PEREQ# PEREQ#* VttPWR_/P# 0 LK_PWR R0 0KOhm PIF ITP_EN/PILK_F <,,,,,,,> M_LK_ LK REF RX0 0KOhm FL REF/FL/TET_EL <,,,,,,,> M_T_ 0 REF0 RX0 Ohm T REF0 LK_IH <> +V VREF % KOhm R0 N N K0_VREF N N N N R0 N ILPRLF-T % Q0 N00 LK_EN# <0> FL FL FL R KOhm R KOhm +VTT_PU R R KOhm KOhm R R KOhm KOhm ILPRLF-T:000 +V +VTT_PU +V <,,0,,,,,,,,,0,,,,0,,,,,,0,,,,,,,,,0,0,,> +VTT_PU <,,,,,,,,> :VREF :TURO :NO TURO R0 R0 R K 0 0K 0 U/R LK_ILPR ary Tsai 0J Friday, July, 00 ate: heet of.