Winery13 CALPELLA DIS N11M-GE1 Schematics ufcpga Mobile Arrandale Intel Ibex Peak-M REV : A00

Transcription

1 Winery LPELL I NM-GE chematics ufpg Mobile rrandale Intel Ibex Peak-M REV : 00 : Nopop omponent UM : Pop when schematic is UM I : Pop when schematic is I <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. over Page ize ocument Number Rev ustom Winery M I ate: Wednesday, January, 00 heet of 00

2 P LYER L: Top L: GN L: ignal L: ignal L: V L: ignal L: GN L: ottom VRM(gR) Mbxx (M), RT H PEKER ( in ) /MM/MM+ MI IN HP OUT L (ingle hanel) MER igital Mic rray 0 VRM RG RT LV lock Generator LGP ardreader RELTEK RT zalia OE OP MP IT 9HU Winery LPELL lock iagram Nvidia PIe x NM-GE(0nm) LV 0,,, 0 RG RT witchable U.0 x 00MHz/.Gbps andwidth :G RG RT LV RG RT LV U.0 0Mbps ZLI MHz T,U U,ET Multi-Port x Intel PU rrandale T Gbps O H,9,0,,,, MIx FI(UM). GT/s. GT/s Intel PH U.0/. ports ETHERNET (0/00/000Mb) High efinition udio T ports () PIE ports () LP I/F PI. PI/PI RIGE 0,,,,,,,, 9 PI Flash ROM M PI Flash ROM k RIII 0 hannel 00/0MHz R III 0 hannel 00/0MHz 00MHz.Gbps PIE U.0 0Mbps M us 00KHz LP us MHz K NUVOTON NPE0X Touch P Thermal & Fan EM0 9, Int. K Project code : 9.EX0.00 Part Number :.EX0.00 P P/N : 09 Revision : 00 RIII 0 RIII 0 Free fall sensor 0 M us lot 0 lot 9 PIE x & U.0 x U.0 x U.0 x PIE x U.0 x U.0 x U.0 x New ard (FP able to onnect) PIE x U.0 x apacity oard Power W TPR PIE x 0/00/000LOM RJ RTLL (On daughter board) st amsung ONN Mini-ard WWN/ WiMX? Left ide: U x Mini-ard WLN 0.a/b/g/n Right ide: U x luetooth iometric ize ocument Number Rev ustom ate: Wednesday, January, 00 heet of INPUT +PWR_R Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. lock iagram Winery M I PU / IL INPUT +PWR_R +PWR_R OUTPUT +.0V_VTT, OUTPUT +V_ORE YTEM / RT0 INPUT OUTPUT +V_LW +.V_RT_LO +V_LW +.V_LW YTEM / TP INPUT OUTPUT +PWR_R INPUT +PWR_R INPUT +_IN +PTT 0 +.V_U +0.V_R_VTT +V_R_REF YTEM / P YTEM / TP INPUT +PWR_R OUTPUT +PU_GFXORE OUTPUT HRGER Q OUTPUT +PWR_R +V_GFX_ORE YTEM / TP INPUT +.V_LW INPUT +.V_LW LO PL90 LO RT90 OUTPUT +.V_RUN OUTPUT 9 +.V_RUN_GPU 00

3 dapter +PWR_R TPPWPRG 0 O0 harger IL P TP TPR 9 +V_R_REF +0.V_R_VTT +.V_U attery Q +PTT +V_ORE +PU_GFXORE For Intel GPU +V_GFX_ORE For NVII GPU +.0V_VTT rrandale :.0V F0 +V_LW +V_LW +.V_LW_ RT0 F0 +.0V_GFX_PIE +.V_RUN_GPU O0 O +V_LW +.V_LW +.V_PU +V_LW +.V_RT_LO +.V_RUN TP0 I/O O TP0 O0 I/O TPR O PL90 RT90 O TPR +V_U For U +V_RUN +V_U For U & ET +.V_LN +.V_RUX +.V_RUN +.V_RUN +.V_RUN_GPU +.V_RUN_GPU +.V_R RTLL I/O IV TPR +.V_LOM +LV +.V_R Power hape Regulator LO witch st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Power lock iagram ize ocument Number Rev ustom 00 Winery M I ate: Wednesday, January, 00 heet of

4 PH Mus lock iagram +.V_LW +.V_RUN PH MLK MT PT PLK L K NPE GPIO/L GPIO/ M_LK M_T TPT TPLK +.V_RT_LO T_L T_ K_L K_ RNKJ--GP +.V_RT_LO RNKJ--GP M_LK M_T +V_RUN RNKJ--GP RN0KJ--GP N00PT Express ard M_LK M_T TPT TPLK RN00J--GP +.V_RUN TPT TPLK PT_MLK PT_MT RNKJ--GP PH_MLK PH_MT PH_MLK PH_MT PH_MLK PH_MT PH_MLK PH_MT PH_MLK PH_MT L Minicard WWN M_LK M_T TouchPad onn. LK_M T_M L IMM Mus ddress:0 IMM L Mus ddress: lock Generator MLK MT Mus address: Minicard WLN K Mus lock iagram N00W--GP PH_MLK PH_MT +.V_RUN RNKJ--GP +.V_RUN M_LK M_T Q Mus address: I/O Free fall sensor L/P /I/O Mus address: 0 attery onn. THERM_L THERM_ MLK MT Thermal Mus address: apacity oard witchable Graphic Mus lock iagram PH L LK L T RT LK RT T NM-GE I_L I_ I_L I_ IFP_UX_IW_L IFP_UX_IW_# RNKJ--GP L LK L_LK L T L_T RNKJ--GP +.V_RUN +.V_RUN L_LK_ON L_T_ON RNKJ--GP THERM_L L THERM_ (On daughter board) Mus address:0 GMH_LK RT_LK_ +.V_RUN GMH_T RT_T_ RNKJ--GP 0 GN V NPX-GP 0 GN +.V_RUN V NPX-GP 0 GN V NPX-GP 0 GN V NPX-GP +.V_RUN +.V_RUN +.V_RUN +.V_RUN RNKJ--GP _LK_ON _T_ON +.V_RUN +.V_RUN Remove HMI L onn. N00W--GP +.V_RUN_GPU _LK_ON _T_ON st amsung +V_RT_RUN RNKJ--GP RT ONN Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. MU lock iagram Winery M I ize ocument Number Rev 00 Wednesday, January, 00 ate: heet of

5 E Thermal lock iagram udio lock iagram N EM0_N HP_PORT L U_HP_JK_L HP_PORT R U_HP_JK_R Thermal EM0 P P N EM0_P VG_THERM VG_THERM 0P0VJN-GP 0P0VJN-GP PLU MINU Q90 GPU MMT90--GP lose to PH I 0 PKR_PORT L+ odec 9H HP0_PORT L HP0_PORT R VREFOUT OR_F U_EXT_MI_L U_EXT_MI_R U_VREFOUT_ U_PK_L-_ U_PK_L+_ 0R-0-U-V-GP PEKER HP OUT MI IN 0 0 P N 9 T_THERM T_THERM 0P0VJN-GP Q90 MMT90--GP HW T sensor MI_LK/GPIO MI0/GPIO 0 U_MI_LK U_MI_IN0 RJ--GP RJ--GP U_MI_LK_G U_MI_IN0_R igital MI rray st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. U_PK_L- U_PK_L+ PKR_PORT L Thermal/udio lock iagram ize ocument Number Rev ustom Winery M I ate: Wednesday, January, 00 heet of E 00

6 PH trapping Name PKR INIT_V# E alpella chematic hecklist Rev. chematics Notes GNT#/ GPIO INTVRMEN Reboot option at power-up efault Mode: Internal weak Pull-down. No Reboot Mode with TO isabled: onnect to Vcc_ with.-k - 0-k weak pull-up resistor. Intel suggest K resistor (Fonseca) Internal pull-up. Leave as "No onnect" efault Mode: Internal pull-up. Low (0) = Top lock wap Mode Note: onnect to ground with.-k weak pull-down resistor. R uses a k ; do not stuff resistor. High () = Integrated VRM is enabled Low (0) = Integrated VRM is disabled Note: R uses a 0-k resistor. Processor trapping Pin Name FG[] FG[] FG[0] trap escription Embedded isplayport Presence PI-Express tatic Lane Reversal PI-Express onfiguration elect alpella chematic hecklist Rev. onfiguration (efault value for each bit is unless specified otherwise) : isabled - No Physical isplay Port attached to Embedded isplayport. 0: Enabled - n external isplay Port device is connected to the Embedded isplay Port. : Normal Operation. 0: Lane Numbers Reversed -> 0, ->,... : ingle PI-Express Graphics 0: ifurcation enabled efault Value GNT0#, GNT# GNT#/ GPIO efault (PI): Leave both GNT0# and GNT# floating. No pull up required. oot from PI: oot from LP: onnect both GNT0# and GNT# to ground with -k pull-down resistor. onnect GNT# to ground with -k pull-down resistor. Leave GNT0# Floating. efault - Internal pull-up. Low (0) = onfigures MI for EI compatible operation (for servers only. Not for mobile/desktops). PI_MOI NV_LE N_LE H_OK_EN# /GPIO[] PIE Routing LNE LNE LNE LNE LNE ard reader Miniard WLN LN Miniard WWN New ard U Table There is an internal pull-up of 0 k for H_OK_EN# which is only H_O H_YN GPIO Enable Intel nti-theft Technology: onnect to Vcc_ with.-k weak pull-up resistor. isable Intel nti-theft Technology: Left floating, no pull-down required. Low (0)- Flash escriptor ecurity will be overridden. lso, when this signals is sampled on the rising edge of PWROK then it will also disable Intel ME and its features. High ()-: ecurity measure defined in the Flash escriptor will be enabled. Platform design should provide appropriate pull-up or pull-down depending on the desired settings. If a jumper option is used to tie this signal to GN as required by the functional strap, the signal should be pulled low through a weak pull-down in order to avoid asserting H_OK_EN# inadvertently. Note: R recommends -k pull-down for F Override. Weak internal pull-down. o not pull high. ampled at rising edge of RMRT#. Weak internal pull-down. o not pull high. ampled at rising edge of RMRT#. Low (0)-Intel ME rypto Transport Layer ecurity (TL) cipher suite with no confidentiality High ()-: Intel ME rypto Transport Layer ecurity (TL) cipher suite with confidentiality Note: This is an unmuxed signal. This signal has a weak internal pull-down of 0 K which is enabled when PWROK is low. ampled at rising edge of RMRT#. R has a -k pull-up on this signal to +.V rail. st amsung GPIO GPIO Enable Intel nti-theft Technology: onnect to +NVRM_Vccq with.-k weak pull-up resistor.[r has it pulled up with -k no-stuff resistor] isable Intel nti-theft Technology: Leave floating (internal pull-down) MI termination voltage. Weak internal pull-up. o not pull low. enabled at boot/reset for strapping functions. Weak internal pull-up. o not pull low. ampled at rising edge of RMRT#. efault = o not connect (floating). Internal pull-up. High() = Enables the internal VccVRM to have a clean supply for analog rails. No need to use on-board filter circuit. Low (0) = isables the VccVRM. Need to use on-board filter circuits for analog rails. Pair evice U U for ET U REERVE WLN WWN U REERVE (Not available for HM) REERVE (Not available for HM) luetooth ard Reader iometric MER New ard REERVE Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Table of ontent ize ocument Number Rev ustom Winery M I ate: Wednesday, January, 00 heet of 00

7 I = lock GEN 0 P0VN-GP +.V_RUN R0 0R00-P--GP change 0 to.pf for RF 0 0U0VZY-GP 0 U0VKX-GP 0 U0VKX-GP 0 U0VKX-GP +.V_RUN_L 0 U0VKX-GP 0 U0VKX-GP +.0V_VTT R09 0R00-P--GP UVKX-GP 0 0U0VZY-GP U0VKX-GP +.0V_RUN_L_IO U0VKX-GP +.V_RUN_L +.0V_RUN_L_IO [] REFLK# [] REFLK [] LKIN_MI# [] LKIN_MI [] LK_PIE_T# [] LK_PIE_T [] LK_PU_LK# [] LK_PU_LK RN0 0RPR-P RN0 0RPR-P RN0 0RPR-P RN0 0RPR-P TP-GP TP-GP RN TP0 TP0 RN RN LK_MH_REFLK# LK_MH_REFLK LK_IN_MI# LK_IN_MI LK_PIE_T# LK_PIE_T LK_PU_LK# LK_PU_LK TP_PU_# TP_PU_ U0 OT_9# OT_9 R_# R_ R_/T# 0 R_/T PU_0# PU_0 9 PU_# 0 PU_ V_PU V_R 9 V_REF V_OT V_ V_R_IO V_PU_IO MHZ MHZ_ PU_TOP# KPWRG/P# REF_0/PU_EL 0 XTL_IN XTL_OUT L LK_M LK_M_ PU_TOP# K_PWRG F LK_XTL_IN LK_XTL_OUT VG M R0 R0 Mount NON- Mount R0 R0 R0 R0 RJ--GP RJ--GP +.V_RUN KRJ--GP RJ--GP PH_MT [,9,,0,,] PH_MLK [,9,,0,,] LK_VG_M [] LK_PH_M [] E0 P0VN-GP K_PWRG +.V_RUN_L R0 0KRJ--GP G Q0 N00--GP T:.N0.E N:.N0. VR_LKEN# [] LGPVTR-GP GN _REF _PU _R _OT T 9 X0 LK_XTL_IN LK_XTL_OUT st ilego.0.00 nd I R0 0KRJ--GP +.0V_VTT R0 KRJ--GP F X-M-GP P0VJN-GP st: HRMONY nd: ITTI.000. rd: TX.000. F 0 PEE MHz (efault) P0VJN-GP 00MHz LK_VG_M R9 0RJ--GP LK_VG_M_R P0VN-GP st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. lock Generator LGP ize ocument Number Rev Winery M I ate: Wednesday, January, 00 heet of 00

8 I = PU alpella Platform esign Guide Revision. [] MI_PTX_RXN0 [] MI_PTX_RXN [] MI_PTX_RXN [] MI_PTX_RXN [] MI_PTX_RXP0 [] MI_PTX_RXP [] MI_PTX_RXP [] MI_PTX_RXP [] MI_TX_PRXN0 [] MI_TX_PRXN [] MI_TX_PRXN [] MI_TX_PRXN [] MI_TX_PRXP0 [] MI_TX_PRXP [] MI_TX_PRXP [] MI_TX_PRXP [] FI_TXN0 [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXP0 [] FI_TXP [] FI_TXP [] FI_TXP [] FI_TXP [] FI_TXP [] FI_TXP [] FI_TXP [] FI_FYN0 [] FI_FYN [] FI_INT [] FI_LYN0 [] FI_LYN Page 9 FI_TXN0 FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXP0 FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP. rrandale Graphics isable Guideline It applies to rrandale and larksfield discrete graphic designs. FI_TX[:0] and FI_TX#[:0] can be left floating on the rrandale. The GFX_IMON, FI_FYN[0], FI_FYN[], FI_LYN[0], FI_LYN[], and FI_INT signals on the rrandale side should be tied to GN (through -k ±% resistors). MI_RX#0 MI_RX# MI_RX# MI_RX# MI_RX0 MI_RX MI_RX MI_RX MI_TX#0 G MI_TX# F MI_TX# H MI_TX# MI_TX0 F MI_TX E MI_TX G MI_TX E FI_TX#0 FI_TX# 9 FI_TX# FI_TX# G FI_TX# E9 FI_TX# F FI_TX# G FI_TX# FI_TX0 FI_TX 0 FI_TX FI_TX G FI_TX E0 FI_TX F0 FI_TX G9 FI_TX F FI_FYN0 E FI_FYN PU FI_INT F FI_LYN0 FI_LYN LRKFIEL PI EXPRE -- GRPHI MI PEG_IOMPI PEG_IOMPO PEG_ROMPO PEG_RI PEG_RX#0 PEG_RX# PEG_RX# PEG_RX# PEG_RX# PEG_RX# PEG_RX# PEG_RX# PEG_RX# PEG_RX#9 PEG_RX#0 PEG_RX# PEG_RX# PEG_RX# PEG_RX# PEG_RX# Intel(R) FI OF 9 PEG_RX0 PEG_RX PEG_RX PEG_RX PEG_RX PEG_RX PEG_RX PEG_RX PEG_RX PEG_RX9 PEG_RX0 PEG_RX PEG_RX PEG_RX PEG_RX PEG_RX PEG_TX#0 PEG_TX# PEG_TX# PEG_TX# PEG_TX# PEG_TX# PEG_TX# PEG_TX# PEG_TX# PEG_TX#9 PEG_TX#0 PEG_TX# PEG_TX# PEG_TX# PEG_TX# PEG_TX# PEG_TX0 PEG_TX PEG_TX PEG_TX PEG_TX PEG_TX PEG_TX PEG_TX PEG_TX PEG_TX9 PEG_TX0 PEG_TX PEG_TX PEG_TX PEG_TX PEG_TX K J J G G F F E 0 J H H F G E F F L M M M0 L K M9 J K9 H0 H9 F9 E 9 L M M L0 M K M H K G0 G9 F E PEG_IROMP_R EXP_RI PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N0 PIE_MRX_GTX_N9 PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N0 PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P0 PIE_MRX_GTX_P9 PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P0 R0 99RF-GP R0 0RF-GP PIE_MRX_GTX_N[0..] PIE_MRX_GTX_P[0..] PIE_MRX_GTX_N[0..] [0] PIE_MRX_GTX_P[0..] [0] PIE_MTX_GRX N 9 U0VKX-GP PIE_MTX_GRX_N PIE_MTX_GRX N U0VKX-GP PIE_MTX_GRX_N PIE_MTX_GRX N U0VKX-GP PIE_MTX_GRX_N PIE_MTX_GRX N U0VKX-GP PIE_MTX_GRX_N PIE_MTX_GRX N 0 U0VKX-GP PIE_MTX_GRX_N PIE_MTX_GRX N0 U0VKX-GP PIE_MTX_GRX_N0 PIE_MTX_GRX N9 PIE_MTX_GRX N 0 U0VKX-GP U0VKX-GP PIE_MTX_GRX_N9 PIE_MTX_GRX_N PIE_MTX_GRX N PIE_MTX_GRX N PIE_MTX_GRX N 0 U0VKX-GP U0VKX-GP U0VKX-GP PIE_MTX_GRX_N PIE_MTX_GRX_N PIE_MTX_GRX_N PIE_MTX_GRX N U0VKX-GP PIE_MTX_GRX_N PIE_MTX_GRX N U0VKX-GP PIE_MTX_GRX_N PIE_MTX_GRX N U0VKX-GP PIE_MTX_GRX_N PIE_MTX_GRX N 0 U0VKX-GP PIE_MTX_GRX_N PIE_MTX_GRX N0 U0VKX-GP PIE_MTX_GRX_N0 PIE_MTX_GRX P PIE_MTX_GRX P U0VKX-GP U0VKX-GP PIE_MTX_GRX_P PIE_MTX_GRX_P PIE_MTX_GRX P U0VKX-GP PIE_MTX_GRX_P PIE_MTX_GRX P U0VKX-GP PIE_MTX_GRX_P PIE_MTX_GRX P 0 U0VKX-GP PIE_MTX_GRX_P PIE_MTX_GRX P0 0 U0VKX-GP PIE_MTX_GRX_P0 PIE_MTX_GRX P9 PIE_MTX_GRX P PIE_MTX_GRX P PIE_MTX_GRX P PIE_MTX_GRX P PIE_MTX_GRX P U0VKX-GP U0VKX-GP U0VKX-GP U0VKX-GP U0VKX-GP U0VKX-GP PIE_MTX_GRX_P9 PIE_MTX_GRX_P PIE_MTX_GRX_P PIE_MTX_GRX_P PIE_MTX_GRX_P PIE_MTX_GRX_P PIE_MTX_GRX P 0 U0VKX-GP PIE_MTX_GRX_P PIE_MTX_GRX P 09 U0VKX-GP PIE_MTX_GRX_P PIE_MTX_GRX P 0 U0VKX-GP PIE_MTX_GRX_P PIE_MTX_GRX P0 9 U0VKX-GP PIE_MTX_GRX_P0 PIE_MTX_GRX_N[0..] PIE_MTX_GRX_P[0..] PIE_MTX_GRX_N[0..] [0] PIE_MTX_GRX_P[0..] [0] LRKUNF st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PU (PIE/MI/FI) ize ocument Number Rev Winery M I ate: Wednesday, January, 00 heet of 00

9 +.0V_VTT Processor Pullups R90 99RF-GP R9 R-GP H_TERR# I = PU H_PROHOT_R# [] PM_RM_PWRG [,,,,,0,,0] [] H_PROHOT# [,] H_PWRGOO [9] H_VTTPWRG PLT_RT# Processor ompensation ignals H_OMP R90 0RF-GP H_OMP R90 0RF-GP H_OMP R90 99RF-GP H_OMP0 R90 99RF-GP TP-GP TP90 [,,] H_THRMTRIP# KTO#_R H_TERR# [] H_PEI R9 0RJ--GP H_PROHOT_R# -0. remove K ohm for remove XP TP90 TP_REET_O# TP-GP [] H_PM_YN TP-GP TP90 R9 KRF-GP H_PWRGOO TP_TPPWRGOO PLT_RT#_R R9 0RF-GP PU T OMP T G T H K T N K P L N N K M M L OMP OMP OMP0 KTO# TERR# PEI PROHOT# THERMTRIP# REET_O# PM_YN VPWRGOO_ VPWRGOO_0 M_RMPWROK VTTPWRGOO TPPWRGOO RTIN# LRKUNF heck LRKFIEL MI THERML LOK R MI PWR MNGEMENT JTG & PM OF 9 LK LK# LK_ITP R0 LK_ITP# T0 PEG_LK E PEG_LK# PLL_REF_LK PLL_REF_LK# M_RMRT# F M_ROMP0 L M_ROMP M M_ROMP N PM_EXT_T#0 N PM_EXT_T# P PR# T PREQ# P TK N TM P TRT# T TI T9 TO R TI_M R9 TO_M P9 R# heck N PM#0 J PM# K PM# K PM# J PM# J PM# H PM# K PM# H LK_PU_P_R LK_PU_N_R heck PEG_LK_R PEG_LK#_R PLL_REF_LK_R PLL_REF_LK#_R M_RMRT# M_ROMP_0 M_ROMP_ M_ROMP_ PM_EXTT#0_ PM_EXTT#_ XP_TRT# XP_TO_R TI_M TO_M R9 RJ--GP R90 0R00-P--GP H_R#_R R909 0R00-P--GP 0/0 heck.assign GPIO E_GPIO9?? -0 RN90 change to ohm RN RN90 RNJ--GP RN90 0RPR-P RNKJ--GP RN90 LK_PU_P [] LK_PU_N [] LK_EXP_P [] LK_EXP_N [] M_ROMP_ M_ROMP_ XP_TO_R +.V_U +.0V_VTT RN90 Vgs(th)<=.V T:.00.E N: R9 RN0KJ--GP PM_EXTT#0 [] PM_EXTT# [9] 0RJ--GP RN90 0RPR-P alpella Platform Power Reduction Platform Power Reduction R Implementation esign etails Revision 0. RN XP_REET# [] -00- R9, POP 9,R9, Q90 G R_RT_GTE# [] 9 0U0VKX-GP +.0V_VTT R_RT_GTE# R9 0KRJ--GP R_RMRT# [,9] R ompensation ignals M_ROMP_0 R90 00RF-L-GP-U R90 9RF-L-GP Q90 --F-GP R9 RJ--GP R9 KRJ--GP R9 0RF--GP M_RMRT# +.V_LW -0 change Q90 to.00.f R9 00KRJ--GP -0 pop R9 for reduce function Normal [,9,] VTT_PWRG R99 0KRJ--GP U9_ U9 GN V Y T:.0G0.L0 N: LVG0GW--GP +.V_LW VTT_PWRG_R R9 KRF-GP R99 KRF-L-GP PM_RM_PWRG +.V_PU R90 0RF-GP R99 R90 U.k k F.k k Power Reduction circuit R99 R90 U.k() 0.k F.k() 0.k R9.k().k() R9.k.k -00- POP R9 for redution R99, change R90 to 0.K Remove XP function for layout concern st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PU (THERML/LOK/PM ) ize ocument Number Rev 00 Winery M I ate: Wednesday, January, 00 heet 9 of

10 I = PU PU OF 9 PU OF 9 [] M Q[..0] M Q[..0] [] M 0 [] M [] M [] M # [] M R# [] M WE# M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q E0 F0 E F E9 E H0 G K J G G0 J J0 L M M L9 L K N P9 H F K K F G J J J0 J9 L0 K K L K L N M0 R L M9 N9 T P M N M T T L R P U E E9 _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q9 _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q9 _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q9 _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q9 _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q9 _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q9 _Q0 _Q _Q _Q _0 _# _R# _WE# LRKFIEL R YTEM MEMORY _K0 _K#0 _KE0 _K _K# _KE _#0 _# _OT0 _OT _M0 _M _M _M _M _M _M _M _Q#0 _Q# _Q# _Q# _Q# _Q# _Q# _Q# _Q0 _Q _Q _Q _Q _Q _Q _Q _M0 _M _M _M _M _M _M _M _M _M9 _M0 _M _M _M _M _M P Y Y P E E F9 9 H M G M N0 N 9 F J9 N9 H K9 P T F9 H9 M9 H K0 N R Y W V 9 V T Y9 U T U G T V9 M M0 M M M M M M M M M M M M M M M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M Q0 M Q M Q M Q M Q M Q M Q M Q M 0 M M M M M M M M M 9 M 0 M M M M M M_LK_R0 [] M_LK_R#0 [] M_KE0 [] M_LK_R [] M_LK_R# [] M_KE [] M_0# [] M_# [] M_OT0 [] M_OT [] [9] M Q[..0] M M[..0] [] M Q#[..0] [] M Q[..0] [] M [..0] [] M Q[..0] [9] M 0 [9] M [9] M [9] M # [9] M R# [9] M WE# M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q E F F F F G H G J J G G J J J K L M K K M N F G J K G G J H K K M N K K M M P N T N N N T T N P P T9 T P9 R0 T0 W R Y _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q9 _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q9 _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q9 _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q9 _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q9 _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q9 _Q0 _Q _Q _Q _0 _# _R# _WE# LRKFIEL R YTEM MEMORY - _K0 _K#0 _KE0 _K _K# _KE _#0 _# _OT0 _OT _M0 _M _M _M _M _M _M _M _Q#0 _Q# _Q# _Q# _Q# _Q# _Q# _Q# _Q0 _Q _Q _Q _Q _Q _Q _Q _M0 _M _M _M _M _M _M _M _M _M9 _M0 _M _M _M _M _M W W9 M V V M E H K H L R T F J L H L R R E H M G L P R U V T V R T R R R R P R F P N M M0 M M M M M M M M M M M M M M M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M Q0 M Q M Q M Q M Q M Q M Q M Q M 0 M M M M M M M M M 9 M 0 M M M M M M_LK_R [9] M_LK_R# [9] M_KE [9] M_LK_R [9] M_LK_R# [9] M_KE [9] M_# [9] M_# [9] M_OT [9] M_OT [9] M M[..0] [9] M Q#[..0] [9] M Q[..0] [9] M [..0] [9] LRKUNF LRKUNF st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PU (R) ize ocument Number Rev Winery M I ate: Wednesday, January, 00 heet 0 of 00

11 I = PU PUE OF 9 RV#J RV#J J J FG0 R0 KRF-GP PI-Express onfiguration elect FG0 :ingle PEG 0:ifurcation enabled TP TP _IMM_VREF# _IMM_VREF# P L L L J G9 M L J H G G E E0 RV#P RV#L RV#L RV#L RV#J RV#G9 RV#M RV#L _IMM_VREF _IMM_VREF RV#G RV#G RV#E RV#E0 LRKFIEL RV#H RV#K RV#L RV_NTF_ RV#J RV#J H K L R J J FG FG IÁ% R0 KRF-GP W FG - PI-Express tatic Lane Reversal FG 0/0 Reversal.PI-Express tatic Lane Reversal R0 KRF-GP FG - isplay Port Presence FG :Normal Operation 0 :Lane Numbers Reversed -> 0, ->,... :isabled; No Physical isplay Port attached to Embedded isplay Port 0:Enabled; n external isplay Port device is connected to the Embedded isplay Port alpella Platform esign Guide Revision.... LV witching witchable GFX, just like integrated GFX only, to enable LV it is required that the OEM set the LV (L T) strap to present (pulled up) and the ep strap (FG[]) to disabled (not pulled down).... ep witching ep for witchable GFX can only be driven out of Port of PH. To configure Port for embedded P it is required to set the P_TRLT strap high to.v ore rail through. k ±% resistor, LV (L T) strap as no connect and the ep strap FG[] as no connect. Page, TP-GP TP-GP TP9 TP0 FG0 M0 FG0 M FG P FG FG L FG FG L0 FG M FG N9 FG M FG K FG K FG9 K FG0 J FG N0 FG N FG J FG J9 FG J0 FG K0 FG H RV_TP_ 9 RV#9 9 RV#9 TP_H_RV_R 0 TP_H_RV_R RV#0 0 RV#0 U9 RV#U9 T9 RV#T9 9 RV#9 9 RV#9 J9 RV#J9 J RV#J LRKUNF REERVE RV#L RV#L9 RV#P0 RV#P RV#L RV#T RV#T RV#P RV#R RV#R RV_TP#E RV_TP#F KEY RV# RV# RV#J RV#H _K _K# _KE _# _OT _K _K# _KE _# _OT _K _K# _KE _# _OT _K _K# _KE _# _OT L L9 P0 P L T T P R R E F J H R R9 G E V V N W W N E 9 P TP_RV_R TP_RV_R TP TP-GP TP TP-GP FG(Reserved) - Temporarily used for early larksfield samples. W 0/0 dded.dded display witchable strap commentariat FG larksfield (only for early samples pre-e) - onnect to GN with.0k Ohm/% resistor. W0 Only support rrandale, FG no need pull down Note: Only temporary for early F sample (rpg/g) [For details please refer to the WW MoW and sighting report]. For a common M/ design (for U and F), the pull-down resistor shouble be used. oes not impact U functionality. st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PU (REERVE) ize ocument Number Rev 00 Winery M I Wednesday, January, 00 ate: heet of

12 +V_ORE 0 0UVKX-GP 0UVKX-GP UVMX-GP 0UVMX-GP U0VKX-GP I = PU 0 0UVKX-GP 0UVKX-GP 0UVKX-GP 0UVMX-GP -0- pop and change size to 00 for EMI 0 0UVKX-GP 0UVKX-GP UVMX-GP 0UVKX-GP 09 0UVKX-GP 0UVKX-GP 0UVKX-GP UVMX-GP 0 UVMX-GP UVMX-GP 9 0UVKX-GP 9 0UVKX-GP PROEOR ORE POWER 0 0UVKX-GP 0UVKX-GP 0 0UVKX-GP 0 0UVKX-GP (rburdale) 0UVKX-GP UVMX-GP 0UVKX-GP UVMX-GP +V_ORE PUF G V G V G V G V G V G0 V G9 V G V G V G V F V F V F V F V F V F0 V F9 V F V F V F V V V V V V 0 V 9 V V V V V V V V V 0 V 9 V V V V V V V V V 0 V 9 V V V V Y V Y V Y V Y V Y V Y0 V Y9 V Y V Y V Y V V V V V V V V V V V V0 V V9 V V V V V V V U V U V U V U V U V U0 V U9 V U V U V U V R V R V R V R V R V R0 V R9 V R V R V R V P V P V P V P V P V P0 V P9 V P V P V P V LRKFIEL PU ORE UPPLY POWER ENE LINE PU VI.V RIL POWER OF 9 PI# VI VI VI VI VI VI VI PRO_PRLPVR VTT_ELET IENE V_ENE _ENE VTT_ENE _ENE_VTT H H H H0 J J H H G G G G F F F F E E F0 E0 0 0 Y0 W0 U0 T0 J J J J N K K K L L M M M G N J J PU_VI0 PU_VI PU_VI PU_VI PU_VI PU_VI PU_VI TP_H_VTTVI V_ENE _ENE 0 0UVKX-GP TP ENE_VTT 0 0UVKX-GP PI# [] PU_VI[..0] [] PM_PRLPVR [] TP0 0 0UVMX-GP 0UVKX-GP TP-GP IMVP_IMON [] VTT_ENE [9] TP0 TP-GP 0UVKX-GP 0UVKX-GP 0UVMX-GP 0UVKX-GP +V_ORE 0UVKX-GP 0UVKX-GP UVMX-GP +.0V_VTT 0/0 heck.prlpvr?? R0 00RF-L-GP-U R0 00RF-L-GP-U 9 0UVKX-GP +.0V_VTT 0 UVMX-GP 0 UVKX-GP V_ENE [] _ENE [] +.0V_VTT The decoupling capacitors, filter recommendations and sense resistors on the PU/PH Rails are specific to the R Implementation. ustomers need to follow the recommendations in the alpella Platform esign Guide. Please note that the VTT Rail Values are rrandale VTT=.0V; larksfield VTT=.V H_VTTVI = Low,.V H_VTTVI = High,.0V st amsung LRKUNF Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev Winery M I ate: Wednesday, January, 00 heet of PU (V_ORE) 00

13 +PU_GFXORE UVMX-GP UVMX-GP +.0V_VTT +.0V_VTT I = PU T0 9 0 E0UVM-L-GP 0UVMX-GP 0 0UVMX-GP 0UVMX-GP 0UVKX-GP 0UVMX-GP UVKX-GP 0UVMX-GP 0UVKX-GP 0UVMX-GP UVKX-GP 09 0UVKX-GP 0UVKX-GP PUG T VXG T9 VXG T VXG T VXG R VXG R9 VXG R VXG R VXG P VXG P9 VXG P VXG P VXG N VXG N9 VXG N VXG N VXG M VXG M9 VXG M VXG M VXG L VXG L9 VXG L VXG L VXG K VXG K9 VXG K VXG K VXG J VXG J9 VXG J VXG J VXG H VXG H9 VXG H VXG H VXG J VTT J VTT H VTT K VTT J VTT J VTT J VTT H VTT G VTT G VTT G VTT F VTT E VTT E VTT LRKUNF GRPHI LRKFIEL POWER FI PEG & MI ENE LINE GRPHI VIs R -.V RIL.V.V OF 9 VXG_ENE XG_ENE GFX_VI GFX_VI GFX_VI GFX_VI GFX_VI GFX_VI GFX_VI GFX_VR_EN GFX_PRLPVR GFX_IMON VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VTT VTT VTT VTT VTT VTT VPLL VPLL VPLL R T M P N P M P N R T M J F E E Y W W U T T P N N L H P0 N0 L0 K0 J J0 J H H0 H9 L L M +.V_PU +.V_U V_XG_ENE [] _XG_ENE [] GFX_VI0 [] GFX_VI [] GFX_VI [] GFX_VI [] GFX_VI [] GFX_VI [] GFX_VI [] GFX_VR_EN [] TP_GFX_PRLPVR TP0TP-GP 0 U0VKX-GP 0 0UVMX-GP 0UVKX-GP U0VKX-GP +.V_PU +.V_U GFX_IMON [] +.0V_VTT +.0V_VTT. +.V_PU +.V_U +.V_PU +.V_RUN +.V_PU +.V_U Follow Intel "0_alpella_PowerReduction_WhitePaper_Rev0.9.pdf" document. 0 UVKX-GP UVKX-GP 0 U0VKX-GP 9 For no use switch graphic function 0UVKX-GP 0UVMX-GP UVKX-GP 0 UVKX-GP 0 UVKX-GP U0VKX-GP 0 U0VKX-GP UVKX-GP 0 0UVKX-GP 0 T0 E0UVM-GP 0UVKX-GP U0VKX-GP 0UVMX-GP 9 U0VKX-GP st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PU (V_GFXORE) ize ocument Number Rev Winery M I ate: Wednesday, January, 00 heet of 00

14 I = PU PUH T0 T R R R R R R0 R R R R9 R R P0 P P P0 P P P N N N N0 N M9 M M M0 M M M M M M L L L L0 L L L9 L L K9 K K K0 K J J J0 J J J J J J H H H H H H0 H9 H H H H0 H H H9 H H G0 F F F E LRKFIEL OF 9 E E E E E0 E9 E E E E Y Y Y W W W W W W0 W9 W W W W V0 U U U T T T T T T0 T9 T T T T R0 P P P N N N N N N0 N9 N N N N M0 L L L9 L L L K K K0 PUI K K9 K K J J0 J J9 H H H H H H H H H H H H H G G G0 G9 G G F0 F F F F9 F E E E9 E E E E E E E E LRKFIEL NYF TET PIN:,T,T,,,,, P,P,R,R,T,T, T,T,,, NTF 9 OF 9 _NTF _NTF _NTF _NTF# _NTF#T _NTF#T _NTF# RV_NTF# RV_NTF# RV_NTF# RV_NTF#P RV_NTF#P RV_NTF#R RV_NTF#R RV_NTF#T RV_NTF#T RV_NTF#T RV_NTF#T RV_NTF# RV_NTF# RV_NTF# R T T P P R R T T T T TP_MP NTF TP_MP NTF TP_MP NTF TP_MP NTF TP0 TP0 TP0 TP0 For layout request LRKUNF LRKUNF st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PU () ize ocument Number Rev Winery M I ate: Wednesday, January, 00 heet of 00

15 (lanking) st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Reserved ize ocument Number Rev Winery M I ate: Wednesday, January, 00 heet of 00

16 (lanking) st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Reserved ize ocument Number Rev Winery M I ate: Wednesday, January, 00 heet of 00

17 (lank) st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. (Reserve) ize ocument Number Rev ustom Winery M I ate: Wednesday, January, 00 heet of 00

18 I = MEMORY +.V_U 0 0UVKX-GP +.V_U 0 0UVKX-GP [0] [0] [0] [0] [0] M Q#[..0] M Q[..0] M M[..0] M Q[..0] M [..0] Layout Note: Place near M Layout Note: Put close to VTT,VTT. +0.V_R_VTT 0 UVKX-GP 0 0UVKX-GP UVKX-GP G: uf* (per O-IMM) 0uF* (two close to VR and one between the two O-IMM) U0VKX-GP U0VKX-GP U0VKX-GP 0UVKX-GP UVKX-GP U0VKX-GP 0UVKX-GP UVKX-GP Follow Intel "0_alpella_PowerReduction_WhitePaper_Rev0.9. pdf" document. 0 U0VKX-GP +V_R_REF 0UVKX-GP U0VKX-GP Layout Note: Put between two O-IMM 0UVMX-GP T0 T0UVM--GP 09 UVKX-GP M 0 M M M M M M M M M 9 M 0 M M M M M M [0] M M 0 [0] M 0 M [0] M M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M Q0 M Q M Q M Q M Q M Q M Q M Q [0] M_OT0 M_OT0 [0] M_OT M_OT +0.V_R_VTT [9,9] R_RMRT# M 0 9 0/P / 0 Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q Q0# Q# Q# Q# Q# Q# Q# Q# Q0 Q Q Q Q Q Q Q OT0 OT VREF_ VREF_Q REET# VTT VTT Height.mm NP NP NP NP R# 0 WE# # 0# # KE0 KE 0 K0 K0# 0 K 0 K# 0 M0 M M M M M M 0 M 00 0 L EVENT# 9 VP 99 0 N# N# N#/TET V V V V V V V V V9 V0 V V V V V V V V M_LK_R0 M_LK_R#0 M_LK_R M_LK_R# M M0 M M M M M M M M M M M M M M PH_MT PH_MLK 0_M _M +.V_U M R# [0] M WE# [0] M # [0] M_0# [0] M_# [0] M_KE0 [0] M_KE [0] M_LK_R0 [0] M_LK_R#0 [0] M_LK_R [0] M_LK_R# [0] PH_MT [,9,,0,,] PH_MLK [,9,,0,,] PM_EXTT#0 [9] +.V_RUN 0 U0VKX-GP 0_M _M put near connector M_LK_R0 M_LK_R#0 M_LK_R M_LK_R# UMMY- 9 UMMY- MU address:0 W 0/0 Reserve.dded 0_M pull-up resistor 0/0.Reserve pull-hi,lo resistor 0 UVKX-GP 0 UMMY- R0 R0 0KRJ--GP 0KRJ--GP UMMY- st amsung R-0P--GP Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RIII-OIMM LOT ize ocument Number Rev ustom Winery M I ate: Wednesday, January, 00 heet of 00

19 I = MEMORY +.V_U +0.V_R_VTT +.V_U [0] [0] [0] [0] [0] 90 0UVKX-GP 90 UVKX-GP M Q#[..0] M Q[..0] M M[..0] M Q[..0] M [..0] 9 0UVKX-GP Layout Note: Place near M Layout Note: Put close to VTT,VTT. G: uf* (per O-IMM) 0uF* (two close to VR and one between the two O-IMM) 9 U0VKX-GP 9 0UVKX-GP 9 UVKX-GP 9 U0VKX-GP 9 U0VKX-GP Follow Intel "0_alpella_PowerReduction_WhitePaper_Rev0.9. pdf" document. +V_R_REF 9 0UVMX-GP 9 UVKX-GP 99 U0VKX-GP 90 U0VKX-GP 99 0UVKX-GP 909 UVKX-GP 90 0UVKX-GP 90 U0VKX-GP T90 T0UVM--GP 9 UVKX-GP [9,] [0] [0] [0] [0] [0] M M 0 M M_OT M_OT R_RMRT# M 0 M M M M M M M M M 9 M 0 M M M M M M M 0 M M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M Q0 M Q M Q M Q M Q M Q M Q M Q M_OT M_OT +0.V_R_VTT M 0 9 0/P / 0 Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q Q0# Q# Q# Q# Q# Q# Q# Q# Q0 Q Q Q Q Q Q Q OT0 OT VREF_ VREF_Q REET# VTT VTT Height 9.mm R-0P--GP NP NP R# WE# # 0# # KE0 KE K0 K0# K K# M0 M M M M M M M NP NP L EVENT# VP 99 0 N# N# N#/TET V V V V V V V V V9 V0 V V V V V V V V M_LK_R M_LK_R# M_LK_R M_LK_R# M M0 M M M M M M M M M M M M M M PH_MT PH_MLK 0_M _M ize ocument Number Rev Winery M I ustom ate: Wednesday, January, 00 heet 9 of +.V_U hange ONN 009/0/0 M R# [0] M WE# [0] M # [0] M_# [0] M_# [0] M_KE [0] M_KE [0] M_LK_R [0] M_LK_R# [0] M_LK_R [0] M_LK_R# [0] PH_MT [,,,0,,] PH_MLK [,,,0,,] PM_EXTT# [9] M_LK_R M_LK_R# M_LK_R M_LK_R# 90 U0VKX-GP 90 UMMY- +.V_RUN put near connector 90 UMMY- 90 UMMY- st amsung _M 0_M R90 0KRJ--GP 9 UVKX-GP +.V_RUN +.V_RUN MU address: Note: If 0_IM0 = 0, _IM0 = 0 O-IMM P ddress is 0x0 If 0_IM0 =, _IM0 = 0 O-IMM P ddress is 0x If 0_IM0 = 0, _IM0 = O-IMM P ddress is 0x 90 UMMY- R90 0KRJ--GP E90 R90 UVKX-GP 0KRJ--GP R90 0KRJ--GP Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RIII-OIMM LOT 00

20 I = PH [] MH_LUE [] MH_GREEN [] MH_RE W 0/0. L brightness control are separated by GPU,PH,E. L Power Enable control are separated by GPU,PH,E. L acklight On/Off tatus are separated by GPU,PH,E 0/0. ummy R00 R00 KRF-GP 0 ohm trace to filter MH_LUE MH_GREEN MH_RE Place near PH [] PNEL_KEN_PH [] LV_EN_PH [] LKLT_TL_PH [] L LK [] L T +.V_RUN [] MH_LV_LK# [] MH_LV_LK [] MH_LV_T0# [] MH_LV_T# [] MH_LV_T# [] MH_LV_T0 [] MH_LV_T [] MH_LV_T LV_EN_PH R0 0R00-P--GP U00 PNEL_KEN_PHR T LV_EN_PH L_KLTEN T L_V_EN RN00 RN0KJ--GP TP-GP TP00 LIG TP_LV_VG. ohm trace to 0R resistor Y LTL_LK LTL_T V R00 00KRJ--GP L_KLTTL L LK Y L T L_TRL_LK L_TRL_T P9 LV_IG P LV_VG T LV_VREFH T LV_VREFL V LV_LK# V LV_LK LV_T#0 LV_T# Y LV_T# V LV_T# LV_T0 0 LV_T Y9 LV_T V LV_T P LV_LK# P LV_LK Y LV_T#0 T9 LV_T# U LV_T# T LV_T# Y LV_T0 T LV_T U0 LV_T T LV_T RT_LUE RT_GREEN RT_RE LV igital isplay Interface OF 0 VO_TVLKINN VO_TVLKINP VO_TLLN VO_TLLP VO_INTN VO_INTP VO_TRLLK VO_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT J G J G F H T T G J U J G 0 0 W Y9 9 E V0 E0 0 F H U0 U R00 0RF--GP R00 0RF--GP Place near PH R00 0RF--GP [] GMH_LK [] GMH_T [] GMH_HYN [] GMH_VYN R00 KRJ--GP RT_IREF V RT LK V RT T Y RT_HYN Y RT_VYN _IREF RT_IRTN RT IEXPEK-M-GP-NF P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P T J0 G0 J G F H E -0 change R00 from 0.% to %. st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PH (LV/RT/I) ize ocument Number Rev Winery M I ate: Wednesday, January, 00 heet 0 of 00

21 +.V_RUN +.V_RUN PI_PERR# PI_REQ0# PI_REQ# PI_FRME# RN0 PI_EVEL# 0 PI_IR# 9 GPU_ELET# PI_ERR# INT_PIRQ# INT_PIRQ# PI_TOP# INT_PIRQ# +.V_RUN [,] EI_ELET# OOT IO trap PI_GNT#0 PI_GNT# RNKJ--GP-U RN0 0 9 RNKJ--GP-U 0 +.V_RUN 0 0 LP INT_PIRQ# PI_PLOK# PI_REQ# PI_TR# GPU_PWM_ELET# EI_ELET_R# PH_GPIO INT_PIRQE# RN0 RN0KJ-GP OOT IO Location 0 Reserved PI PI(efault) swap override trap/top-lock wap Override jumper U0 V Y +.V_RUN +.V_RUN [9,,,,,0,,0] -0 U0; POP R0 GN LVG0GW--GP R0 0RJ--GP 0P0VKX-GP EI_ELET_R# 0 U0VKX-GP PLT_RT# W -0 U0; POP R0 [0] PLK_FWH [] LK_PI_F [] PLK_K [] PLK_TPM 0/0 dded. using the single buffers for device with equivalent capability..rename PI_PLTRT# +.V_RUN [,,] GPU_ELET# [] GPU_PWM_ELET# [0] H_FLL_INT [] WWN_RF_EN U0 V Y TP-GPTP TP GN LVG0GW--GP R0 0RJ--GP TP-GPTP0 TP0 R0 RJ--GP R0 RJ--GP R RJ--GP R RJ--GP alpella Platform esign Guide Revision. TP-GPTP TP PLTRT#_PH INT_PIRQ# INT_PIRQ# INT_PIRQ# INT_PIRQ# PI_REQ0# PI_REQ# GPU_ELET# PI_REQ# PI_ERR# PI_PERR# PI_IR# PI_EVEL# PI_FRME# PI_PLOK# PI_TOP# PI_TR# PH_PME# PLTRT#_PH U00E H0 0 N J 0 E H 9 E0 0 0 M M F M0 M J K F0 9 0 K M J K L F J0 G F 9 M 0 H J0 /E0# G /E# H /E# G /E# G PIRQ# H PIRQ# PIRQ# PIRQ# F REQ0# REQ#/GPIO0 REQ#/GPIO M REQ#/GPIO PI_GNT0# F GNT0# K GPU_PWM_ELET# GNT#/GPIO F R PI_GNT# GNT#/GPIO H 0RJ--GP GNT#/GPIO INT_PIRQE# WWN_RF_EN PIRQE#/GPIO K PH_GPIO PIRQF#/GPIO EI_ELET_R# PIRQG#/GPIO PIRQH#/GPIO PIRT# K PIRT# E ERR# E0 PERR# IR# H PR F EVEL# FRME# 9 M PLK_FWH_R N LK_PI_F_R P PLK_K_R P PLK_TPM_R P P PLOK# TOP# TR# PME# PLTRT# LKOUT_PI0 LKOUT_PI LKOUT_PI LKOUT_PI LKOUT_PI IEXPEK-M-GP-NF PI NVRM U OF 0 NV_E#0 NV_E# NV_E# NV_E# NV_Q0 NV_Q NV_Q0/NV_IO0 NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q9/NV_IO9 NV_Q0/NV_IO0 NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_LE NV_LE NV_ROMP NV_R# NV_WR#0_RE# NV_WR#_RE# NV_WE#_K0 NV_WE#_K UP0N UP0P UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UP9N UP9P UP0N UP0P UPN UPP UPN UPP UPN UPP URI# URI O0#/GPIO9 O#/GPIO0 O#/GPIO O#/GPIO O#/GPIO O#/GPIO9 O#/GPIO0 O#/GPIO Y9 P V9 G P P T T9 V E J J G Y U V Y Y V F H J N0 P0 J0 L0 F0 G0 0 0 M N H J E F G H L M N J F L E G F T TP_NV_LE TP_NV_LE TP_NV_ROMP TP0 TP-GP Port 0 for debug port TP_U_PN TP_U_PP TP_U_PN TP_U_PP TP_U_PN TP_U_PP TP_U_PN TP_U_PP U_RI_PN U_O#0_ U_O#_ U_O#_ U_O#_ U_O#_9 U_O#0_ U_O#_ PH_O# TP TP-GP TP TP-GP U_PN0 [] U_PP0 [] U_PN [] U_PP [] U_PN [] U_PP [] TP TP U_PN [] U_PP [] U_PN [] U_PP [] TP TP9 TP0 TP U_PN [] U_PP [] U_PN9 [] U_PP9 [] U_PN0 [] U_PP0 [] U_PN [] U_PP [] U_PN [] U_PP [] TP TP9 I = PH MI Termination Voltage NV_LE et to Vss when low. et to Vcc when high. Low = efault unused NV_LE strap R0 RF-L-GP Pair U_O#0_ [,] U_O#_ [] U_O#_ [] U evice U U for ET U REERVE WLN WWN REERVE (Not available for HM) REERVE (Not available for HM) luetooth ard Reader iometric MER New ard REERVE Pull up in page for layout convenience swap net for layout Pull up in page for layout convenience PI_GNT# Low = swap override/top-lock wap Override enabled High = efault Table. Overcurrent Pin Example onfiguration Page These O# pins are not used for U overcurrent protection and should be configured as GPIOs. The unused U ports can be left as no connect. PI_GNT# R09 KRJ--GP +.V_LW PH_O# U_O#_ U_O#_ U_O#_ RP0 0 9 PM_RI# U_O#_9 PEG LKRQ# U_O#0_ RN0KJ-L-GP +.V_LW PM_RI# [] PEG LKRQ# [] swap net for layout st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PH (PI/U/NVRM) ize ocument Number Rev Winery M I ate: Wednesday, January, 00 heet of 00

22 I = PH +.0V_VTT [] MI_TX_PRXN0 [] MI_TX_PRXN [] MI_TX_PRXN [] MI_TX_PRXN [] MI_TX_PRXP0 [] MI_TX_PRXP [] MI_TX_PRXP [] MI_TX_PRXP [] MI_PTX_RXN0 [] MI_PTX_RXN [] MI_PTX_RXN [] MI_PTX_RXN [] MI_PTX_RXP0 [] MI_PTX_RXP [] MI_PTX_RXP [] MI_PTX_RXP R0 MI_IROMP_R 99RF-GP +.V_RUN U00 MI0RXN J MIRXN W0 MIRXN J0 MIRXN MI0RXP G MIRXP 0 MIRXP G0 MIRXP E MI0TXN F MITXN 0 MITXN E MITXN MI0TXP H MITXP 0 MITXP MITXP H MI_ZOMP F MI_IROMP MI FI OF 0 FI_RXN0 FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXP0 FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_INT FI_FYN0 FI_FYN FI_LYN0 FI_LYN H J E F G W J F H J G FI_TXN0 FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXP0 FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_INT FI_FYN0 FI_FYN FI_LYN0 FI_LYN FI_TXN0 [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXP0 [] FI_TXP [] FI_TXP [] FI_TXP [] FI_TXP [] FI_TXP [] FI_TXP [] FI_TXP [] FI_INT [] FI_FYN0 [] FI_FYN [] FI_LYN0 [] FI_LYN [] [,] U_O#0_ U_O#0_ U_PWR_K PM_TLOW#_R R0 0KRJ--GP PIE_WKE# R0 KRJ--GP _PREENT_E R 0KRJ--GP +.V_RUN +.V_LW Option to " isable " clkrun. Pulling it down will keep the clks running. RN0 RN0KJ--GP R 0KRJ--GP [9] XP_REET# [] PM_PWROK [9] PM_RM_PWRG XP_REET# PM_PWRG LN_RT# PM_RM_PWRG [] RMRT#_K PM_RMRT#_R PM_LP_#_R PM_LP_# [,,0] R0 0RJ--GP RMRT# LP_# H R 0R00-P--GP [] U_PWR_N_K U_PWR_K M PM_LP_#_R U_PWR_N_K/GPIO0 LP_# P PM_LP_# [,,,0,,] R 0R00-P--GP R 0R00-P--GP [] PM_PWRTN# PM_PWRTN#_R P IO_LP_M#_R PWRTN# LP_M# K R 0R00-P--GP TP0TP-GP [] _PREENT_E Remove XP pull-up? R0 0R00-P--GP R0 0KRJ--GP R09 0KRJ--GP _PREENT_E _PREENT R 0R00-P--GP R0 0KRJ--GP T M K 0 9 P Y_REET# Y_PWROK PWROK MEPWROK LN_RT# RMPWROK PREENT/GPIO ystem Power Management WKE# LKRUN#/GPIO U_TT#/GPIO ULK/GPIO LP_#/GPIO TP J Y P F E N PM_LKRUN# TP_U_TT# PH_ULK PH_LP_# PM_LP_W# TP0TP-GP TP0TP-GP TP0TP-GP PIE_WKE# [,] PM_LKRUN# [] lose to PH R9 0R00-P--GP R0 0R00-P--GP PH_ULK_0 [9] PH_ULK_K [] PM_LKRUN# R 0KRJ--GP PM_TLOW#_R TLOW#/GPIO PMYNH J0 H_PM_YN H_PM_YN [9] [] PM_RI# PM_RI# F RI# LP_LN#/GPIO9 F IEXPEK-M-GP-NF Pull up in page for layout convenience K_PWR R 0KRJ--GP - U U_ PM_RMRT#_R V_V_POK [,] MN0LW--GP st amsung PM_RMRT#_R R0 0KRJ--GP Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PH (M I/FI/PM) ize ocument Number Rev Winery M I ate: Wednesday, January, 00 heet of 00

23 I = PH U00 OF 0 ML0LERT# MLLERT# RN0 RN0KJ--GP +.V_LW +.V_LW +.V_LW -00 [] PIE_IRXN_MTXN [] PIE_IRXP_MTXP [] PIE_ITXN_MRXN [] PIE_ITXP_MRXP [] PIE_IRXN_LRTXN [] PIE_IRXP_LRTXP [] PIE_ITXN_LRXN [] PIE_ITXP_LRXP [] PIE_IRXN_MTXN [] PIE_IRXP_MTXP [] PIE_ITXN_MRXN [] PIE_ITXP_MRXP U0VKX-GP U0VKX-GP U0VKX-GP U0VKX-GP U0VKX-GP U0VKX-GP G0 J0 F9 H9 W0 0 PIE_ITXN_MRXN_0 PIE_ITXP_MRXP_ 0 U0 T0 PIE_ITXN_LRXN_ U PIE_ITXP_LRXP_ V PIE_ITXN_MRXN_ PIE_ITXP_MRXP_ E PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP WLN LN WWN Mus MLERT#/GPIO MLK MT ML0LERT#/GPIO0 ML0LK ML0T MLLERT#/GPIO MLLK/GPIO MLT/GPIO 9 H J G M E0 G MLERT# PH_M_LK PH_M_T ML0LERT# ML0_LK ML0_T MLLERT# K_L K_ R0 0KRJ--GP +.V_LW Remove XP pull-up PH_M_LK [] PH_M_T [] K_L [] K_ [] -00 RN RNKJ--GP +.V_RUN PH_M_LK PH_M_T RN0 RNKJ--GP [] PIE_IRXN_NTXN [] PIE_IRXP_NTXP [] PIE_ITXN_NRXN [] PIE_ITXP_NRXP [] LK_PIE_NEW# [] LK_PIE_NEW [] NEWR_LKREQ# [] LK_PIE_MINI# [] LK_PIE_MINI [] MINI_LKREQ# 0 0 F H U0VKX-GP PIE_ITXN_NRXN_G U0VKX-GP PIE_ITXP_NRXP_ J PIELKRQ{0,,,,,}# should have a 0K pull-up to +.V_LW. PIELKRQ{,} should have a 0K pull-up to +._RUN RN 0RPR-P RN0 0RPR-P RN RN RN LK_PIE_NEW# LK_PIE_NEW NEWR_LKREQ# U LK_PIE_MINI_# LK_PIE_MINI_ MINI_LKREQ# W T U U V G J G J K K P9 M M M M N PERN PERP PETN PETP New ard PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP LKOUT_PIE0N LKOUT_PIE0P PI-E* PIELKRQ0#/GPIO LKOUT_PIEN LKOUT_PIEP PIELKRQ#/GPIO LKOUT_PIEN LKOUT_PIEP PIELKRQ#/GPIO0 From LK UFFER ontroller PEG Link L_LK L_T L_RT# PEG LKRQ#/GPIO LKOUT_PEG N LKOUT_PEG P LKOUT_MI_N LKOUT_MI_P LKOUT_P_N/LKOUT_LK_N LKOUT_P_P/LKOUT_LK_P LKIN_MI_N LKIN_MI_P LKIN_LK_N LKIN_LK_P LKIN_OT_9N LKIN_OT_9P LKIN_T_N/K_N LKIN_T_P/K_P T T T9 H N N T T W P P F E H H L_LK L_T L_RT# PEG_LKREQ# LK_PIE_VG# LK_PIE_VG LK_EXP_N LK_EXP_P LKIN_MI# LKIN_MI LK_PU_LK# LK_PU_LK REFLK# REFLK LK_PIE_T# LK_PIE_T TP0 TP-GP TP0 TP-GP TP0 TP-GP RN 0RPR-P +.V_LW RN LK_EXP_N [9] LK_EXP_P [9] LKIN_MI# [] LKIN_MI [] LK_PU_LK# [] LK_PU_LK [] REFLK# [] REFLK [] R0 0KRJ--GP LK_PIE_VG# [0] LK_PIE_VG [0] LK_PIE_T# [] LK_PIE_T [] PH_M_T PH_M_LK [,] GPU_V_PGOO RN0 RNKJ--GP Q0 MN0LW--GP G PEG_LKREQ# Q0 N00--GP PH_MT [,,9,0,,] T:.MN.0F N:.00.FF PH_MLK [,,9,0,,] T:.N0.E N:.N0. [] LK_PIE_LN# [] LK_PIE_LN [] LKREQ#_LN [] LK_PIE_MINI# [] LK_PIE_MINI [] MINI_LKREQ_R# RN0 0RPR-P RN09 0RPR-P [] PEG LKRQ# +.V_RUN LK_PIE_LN# LK_PIE_LN LKREQ#_LN LK_PIE_MINI_# LK_PIE_MINI_ Q0_ MINI_LKREQ# PIELKRQ# PEG LKRQ# IEXPEK-M-GP-NF Pull up in page for layout convenience T:.090.H N:.090.L0 RN R 0KRJ--GP Q0 MMT90--F-GP MINI_LKREQ# R09 0RJ--GP H LKOUT_PIEN H LKOUT_PIEP PIELKRQ#/GPIO M LKOUT_PIEN M LKOUT_PIEP M9 PIELKRQ#/GPIO J0 LKOUT_PIEN J LKOUT_PIEP H P PIELKRQ#/GPIO K LKOUT_PEG N K LKOUT_PEG P PEG LKRQ#/GPIO +.V_LW +.V_RUN RN0 RN0KJ-GP RN0 lock Flex PIELKRQ# U_O#_ LKREQ#_LN MINI_LKREQ# REFLKIN LKIN_PILOOPK P J XTL_IN H XTL_OUT H XLK_ROMP LKOUTFLEX0/GPIO LKOUTFLEX/GPIO LKOUTFLEX/GPIO LKOUTFLEX/GPIO F T P T N0 U_O#_ [] LK_PH_M LK_PI_F XTL_IN XTL_OUT -0 swap net for layout NEWR_LKREQ# K_ET_R# K_ET_R# [] GPO_M GPO_M [,] MINI_LKREQ# -0 RN0 change to * size XLK_ROMP TP_LK_OUTFLEX0 TP_LK_PI_LP swap net for layout TP_LK_PH_REF LKM/EI_EL R0 0R00-P--GP LK_PH_M [] LK_PI_F [] R0 909RF--GP TP0 TP-GP TP0 TP-GP TP0 TP-GP +.0V_VTT -00 move EI_ELET# from GPIO to GPIO LK_PH_M [] RN0KJ--GP un-stuff M X'tal without HMI/eP/P XTL_IN XTL_OUT -0 pop for MHz st amsung -- pop 0 ohm if no use MHz XTL R0 MRJ--GP X0 XTL-MHZ-GP Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PH (PI-E/MU/LOK/L) ize ocument Number Rev Winery M I 00 ate: Wednesday, January, 00 heet of 0RJ--GP 0 P0VJN--GP

24 PH_RTX R0 0MRJ-L-GP X0 PH_RTX +RT_ELL R0 0KRJ-L-GP 0 UVKX-GP INTVRMEN- Integrated U.V VRM Enable High - Enable internal VRs I = PH 0 P0VJN-GP 0 P0VJN-GP U00 OF 0 LP_L[0..] LP_L[0..] [,,0] - W 0/ dded.dded "ME in Manufacturing Mode" strap.dded ardreader_wake# to sent ard detect signal for PH. ( Only For JM0 ) ME_UNLOK# +.V_RUN NO REOOT TRP _PKR R0 KRJ--GP W st: EPON.000. nd: QURTEH.000. rd: K Flash escriptor ecurity Override/ ME ebug Mode 0/0 hange.hange R0 to dummy This strap should only be asserted low via external pull down in manufacturing/debug environments ONLY. R9 KRJ--GP X-KHZ-GP ME_UNLOK_R# No Reboot trap R Low = efault H_PKR High = No Reboot -0. remove R pull high INT_ERIRQ to RN0. +RT_ELL R0 0KRJ-L-GP 0 UVKX-GP [0] PH_Z_OE_ITLK [0] PH_Z_OE_YN [0] _PKR [0] PH_Z_OE_RT# [0] PH_IN_OE [0] PH_OUT_OE [] ME_UNLOK# [] PH_PI_LK [] PH_PI_0# [] PH_PI_O G0 GP-OPEN +RT_ELL R 0R00-P--GP PH_RTX PH_RTX PH_RTRT# RTRT# M_INTRUER# R0 MRJ--GP PH_INTVRMEN R0 0KRF-L-GP R0 RJ--GP R0 RJ--GP R0 RJ--GP Z_IT_LK Z_YN_R Z_RT#_R ME_UNLOK_R# PH_JTG_TK PH_JTG_TM PH_JTG_TI PH_JTG_TO PH_JTG_RT# RTX RTX INTVRMEN [] PH_PI_I V PI_MIO -0- change R,R,R from ohm to 0 ohm IEXPEK-M-GP-NF G0 F0 E F R09 RJ--GP Z_TOUT_R 9 TP0 TP0 TP0 TP0 TP0 R 0RJ--GP PI_LK_R R 0RJ--GP PI_#0_R R 0RJ--GP PI_MOI_R P H J0 M K K J J V Y Y RTRT# RTRT# INTRUER# H_LK H_YN PKR H_RT# H_IN0 H_IN H_IN H_IN H_O H_OK_EN#/GPIO H_OK_RT#/GPIO JTG_TK JTG_TM JTG_TI JTG_TO TRT# PI_LK PI_0# PI_# PI_MOI RT IH PI JTG LP T FWH0/L0 FWH/L FWH/L FWH/L FWH/LFRME# LRQ0# LRQ#/GPIO ERIRQ T0RXN T0RXP T0TXN T0TXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TIOMPO TIOMPI TLE# T0GP/GPIO TGP/GPIO9 F 9 K K K K9 H H H9 H F F9 F F H H F F 9 F F T Y9 V T_ITXN0_HRXN0_ T_ITXP0_HRXP0_ T_ITXN_ORXN_ T_ITXP_ORXP_ TIOMP GPO_M PH_GPIO9 W LP_L0 LP_L LP_L LP_L LP_LFRME# [,,0] INT_ERIRQ [,,] 0 0UVKX-GP 0 0UVKX-GP 0 0UVKX-GP 0 0UVKX-GP R RF-GP 0/0 assign GPIO.assign GPIO GPIO_M,Felic_ETET# T_LE# [] GPO_M [,] PH_GPIO9 [] +.0V_VTT H T_IRXN0_HTXN0_ [9] T_IRXP0_HTXP0_ [9] T_ITXN0_HRXN0 [9] T_ITXP0_HRXP0 [9] O T_IRXN_OTXN_ [9] T_IRXP_OTXP_ [9] T_ITXN_ORXN [9] T_ITXP_ORXP [9] ET ET_IRX_TX_N_ [] ET_IRX_TX_P_ [] ET_ITX_RX_N [] ET_ITX_RX_P [] st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PH (PI/RT/LP/T/IH) ize ocument Number Rev 00 Winery M I ate: Wednesday, January, 00 heet of

25 [] EEPILE_WKE_INT_R# +.V_RUN R0 0KRJ--GP GPU_PWROK R 0KRJ--GP PH_GPIO [] PH_GPIO9 PH_GPIO PH_GPIO PIELKRQ# EMI# PH_GPIO L_L_ET_R# R0 TP_PI# +.V_RUN_GPU +.V_RUN_GPU +.V_RUN R 0KRJ--GP [] EWI# 0 P0VJN-GP [] GFX_ORE_PGOO [,] GPU_V_PGOO [] L_L_ET# W Q_ GPU_HOL_RT# R 0KRJ--GP RN0KJ--GP PH_GPIO9 PH_GPIO RN0 0/0 hange.hange LK_T_OE# to pull-down +.V_LW +.V_LW +.V_RUN +.V_RUN [] EMI# PH_GPIO [] EI# [0] GPU_HOL_RT# R0 0R00-P--GP R0 0R00-P--GP R9 00RJ--GP [] K_ET# [] K_ET_R# [,,] INT_ERIRQ [] IO_ET# [] IO_ET# [] GPU_PWR_EN# EWI# EI# EEP_ILE# EI# IO_ET# EWI# EMI# PH_GPIO GPU_HOL_RT# L_L_ET_R# PH_GPIO PH_GPIO TP_PI# GPU_PWR_EN# GPU_PRNT# PH_GPIO R 00RJ--GP K_ET_R# [9] R_RT_GTE# [0] FF_INT_R [] TURO_OOT_LERT# 0/0 dded.hanged PH GPIO R_RT_GTE from GPIO to GPIO, ason on design guide 0/ dded.dded Finger Printer etect Pin, control by PH.hange K_ET signal from E to PH control.hange L_L_ET signal from E to PH control swap net for layout RN0 RN0KJ--GP -0-0 swap net for layout Q MMT90--F-GP - R0 0KRJ--GP R KRJ--GP R 0KRJ--GP R 0KRJ--GP 0KRJ--GP R 0KRJ--GP R KRJ--GP R0 0KRJ--GP TP-GP TP0 PIELKRQ# R_RT_GTE# FF_INT_R PH_GPIO For layout request TP-GP TP TP-GP TP TP-GP TP0 TP-GP TP09 PH_NTF_ PH_NTF_ GPU_PWROK J F0 H0 V +.V_RUN +.V_RUN K9 F F TH/GPIO TH/GPIO LN_PHY_PWR_TRL/GPIO TH0/GPIO LOK/GPIO GPIO GPIO GPIO TGP/GPIO TURO_OOT_LERT# TGP/GPIO9 PH_NTF_ PH_NTF_ RN0KJ--GP RN0 Y T Y M V V P H F U00F MUY#/GPIO0 TH/GPIO GPIO GPIO TGP/GPIO TP_PI#/GPIO TLKREQ#/GPIO TGP/GPIO LO/GPIO TOUT0/GPIO9 PIELKRQ#/GPIO PIELKRQ#/GPIO TOUT/GPIO GPIO _NTF_ 9 _NTF NTF_ 0 _NTF NTF NTF NTF NTF NTF_9 _NTF_0 E _NTF_ E _NTF_ F _NTF_ F _NTF_ H _NTF_ H _NTF_ H _NTF_ H _NTF_ J _NTF_9 J _NTF_0 J _NTF_ J9 _NTF_ J _NTF_ J0 _NTF_ J _NTF_ J _NTF NTF NTF NTF_9 E _NTF_0 E _NTF_ IEXPEK-M-GP-NF GPIO NTF RV GPU_PRNT# MI PU +.V_RUN LKOUT_PIEN H LKOUT_PIEP H LKOUT_PIEN F LKOUT_PIEP F PH_THERMTRIP_R R RN0 0KRJ--GP INT_ERIRQ FF_INT_R GPU_PWR_EN# IO_ET# -0 RN0KJ--GP RN0 change to * size OF 0 0GTE LKOUT_LK0_N/LKOUT_PIEN LKOUT_LK0_P/LKOUT_PIEP R 0KRJ--GP PEI RIN# PROPWRG THRMTRIP# TP TP TP TP TP TP TP TP TP9 TP0 TP TP TP TP TP TP TP TP TP9 N_ N_ N_ N_ N_ INIT_V# TP U M M G0 T E0 0 W Y Y V V F M N J K K M N M0 N0 H T9 P 0 INIT_V# K0GTE [] LK_PU_N [9] LK_PU_P [9] H_PEI [9] H_PWRGOO [9,] TP0TP-GP I = PH R RJ--GP KRIN# [] st amsung +.0V_VTT R09 RJ--GP Placed Within " from PH H_THRMTRIP# [9,,] Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PH (GPIO/PU) Winery M I ize ocument Number Rev ate: Wednesday, January, 00 heet of 00

26 I = PH +.0V_VTT.0 +.0V_VTT +.0V_VTT 0UVKX-GP. 0 0UVKX-GP U0VKX-GP U0VKX-GP U0VKX-GP +.V_RUN U0VKX-GP +.V_RUN -0 m R0 +V_VRM 0R00-P--GP TP0 VFIPLL TP-GP 0 UVKX-GP +.0V_VTT TP0 TP-GP VPLLEXP U0VKX-GP U00G VORE VORE VORE VORE VORE. F VORE F VORE F0 VORE F VORE H VORE H VORE H0 VORE H VORE J0 VORE J VORE K VIO J VPLLEXP N0 VIO N VIO N VIO N VIO N VIO N VIO.0 J VIO J VIO T VIO T VIO U VIO U VIO V VIO V VIO W VIO W VIO VIO VIO VIO VIO VIO VIO VIO VIO E VIO E VIO G VIO G VIO H VIO N0 VIO N VIO N V_ T VVRM[] J VFIPLL M VIO POWER V ORE PI E* IEXPEK-M-GP-NF FI RT LV HVMO MI NN / PI OF 0 V V <m VLV _LV VTX_LV VTX_LV 9m VTX_LV VTX_LV V_ m V_ V_ VVRM VMI VMI VPNN VPNN VPNN m VPNN VPNN VPNN VPNN VPNN VPNN VME_ VME_ m VME_ VME_ E0 E F F H H9 P P T T T T U M K K0 K9 K K M M M M M9 P P9 +V +V_V_LV 0UVKX-GP m 0 +V_VRM m +.0V_V_MI m m +.V_RUN R09 0R00-P--GP m R0 0R00-P--GP V_RUN V_RUN R0 0R00-P--GP <m U0VKX-GP +.V_VTX_LV L0 IN-UH--GP 0UVMX-GP 0UVKX-GP 0UVKX-GP 9m +.V_RT_LO +.V_RUN +.V_RUN 0 U0VKX-GP 0UVMX-GP N# U0VKX-GP U0VKX-GP PH_VME_ U0VKX-GP 0 U0VKX-GP L0 LMPGN-GP 0 0UVMX-GP 9m R0 0R00-P--GP V_RT_LO U0 OUT IN GN HN# MXEXK-T-GP +.0V_VTT +.V_RUN +V_RUN 9 U0VKX-GP st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PH (POWER) ize ocument Number Rev Winery M I ate: Wednesday, January, 00 heet of 00

27 +.0V_VTT I = PH - L0 +.0V_V PL IN-0UH--GP 0UVMX-GP L0 +.0V_V PL IN-0UH--GP 0UVMX-GP U0VKX-GP +.0V_VTT 0UVKX-GP +.0V_VTT UVKX-GP +.V_LW UVKX-GP 0 0UVKX-GP m <m U0VKX-GP +RT_ELL m TP0 VLK TP-GP P VLK P VLK 0 U0VKX-GP 9 0 UVKX-GP UVKX-GP U0VKX-GP 0 UVKX-GP U0VKX-GP U0VKX-GP 0 UVKX-GP PUYP Y0 PUYP F VLN F VLN VME 9 VME VME m 0m F VME F VME.9 F VME V9 VME V VME V VME Y9 VME Y VME Y VME UVKX-GP +VRTEXT V9 PRT +V_VRM U0VKX-GP U VVRM UVKX-GP m +.0V_V PL VPLL VPLL m 9m +.0V_V PL VPLL VPLL 9m +.0V_VTT H VIO J VIO H VIO 9 0 UVKX-GP UVKX-GP F VIO H VIO F VIO U00J +VT V PT +.0VLW_INT_VU Y PU U0VKX-GP P VU_ U9 VU_ U0 VU_ U VU_ +.V_RUN V V_ V V_ Y V_ T V_PU_IO <m U V_PU_IO VRT m IEXPEK-M-GP-NF POWER lock and Miscellaneous RT PU PI/GPIO/LP T PI/GPIO/LP U 0 OF 0 +.0V_VTT VIO V VIO V 0 VIO Y U0VKX-GP VIO Y VU_ V +.V_LW VU_ U VU_ U VU_ U VU_ P VU_ P 0 VU_ N U0VKX-GP VU_ N VU_ M VU_ M VU_ L VU_ L VU_ J VU_ J VU_ H m VU_ H VU_ G VU_ G +.V_LW VU_ F VU_ F +.V_LW W VU_ E 0/0 hange resistor Value VU_ E.R0,R0 value corrected to 00 Ohms following PG doc VU_ 0 VU_ +V_LW VU_ HH-0PT-GP 09 VU_ U0VKX-GP VU_ +.V_RUN VU_ U +.0V_VTT VIO V R0 00RJ--GP +VLW_PH_VREFU +V_RUN <m 0 VREF_U F HH-0PT-GP UVKX-GP <m VREF K9 +V_PH_VREF R0 +.V_RUN V_ J 00RJ--GP V_ L UVKX-GP V_ M +.V_RUN V_ N U0VKX-GP V_ P V_ U U0VKX-GP V_ VTPLL TP0 VTPLL K TP-GP VTPLL K - +.0V_VTT VIO H +V_VRM 9m VVRM T0 UVKX-GP VIO H9 VIO 0 VIO F VIO 9 VIO F0 VIO F9 VIO H0 VIO 9 VIO 0 VIO VIO +.0V_VTT VME VME Y VME Y VME R st amsung m VUH m +.V_LW 0R00-P--GP F,, ec., Hsin Tai Wu Rd., Hsichih, UVKX-GP Taipei Hsien, Taiwan, R.O.. H +V_+.V_H_IO Wistron orporation PH (POWER) ize ocument Number Rev Winery M I ate: Wednesday, January, 00 heet of 00

28 I = PH U00H 9 0 M U 9 E E F Y H9 U F P N F F F9 F F G G H H H H H V H H H J9 J J0 J J J J J J T J K M N9 K K K K IEXPEK-M-GP-NF OF 0 K0 K K K K K K K K9 K K L L M M0 M M M M M0 M M M M M M9 M U0 M V M9 M 0 0 N N0 N P P P P9 P P R R T H T T T T T V V V0 V V0 V V V V V9 V V W W W F9 W W W0 W Y Y Y U00I Y 9 9 G H9 9 E E E0 E E0 E E E E E E0 E E F F9 F G G G G0 H H H9 H H H H9 H H H 0 E E E0 E E0 E E E E E E E F9 F G0 G G G G G G G0 G G F9 H H0 H0 H H H 9 OF 0 H9 H J K K K K L L L L L L L0 L M M M0 N M M M M M9 M M N P P P0 P P P P P R R T T T T9 T T U0 U U U P V P V9 V0 V V0 V V V V V V V V V V9 V V V W W Y Y Y Y9 Y Y Y0 Y Y Y Y Y P9 Y Y Y P T T Y T M T M K K9 V st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IEXPEK-M-GP-NF PH () ize ocument Number Rev Winery M I ate: Wednesday, January, 00 heet of 00

29 (lank) st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. (Reserve) ize ocument Number Rev ustom Winery M I ate: Wednesday, January, 00 heet 9 of 00

30 I = UIO +.V_RUN +.V_RUN [] U_MI_LK_G R00-P--GP R0 0 U0VKX-GP PH_Z_OE_ITLK 0 P0VN-GP R00 0KRJ--GP MP_MUTE# +.V_RUN Internal pull up 0K check external pull up?? E00 P0VJN-GP [] PH_Z_OE_ITLK [] PH_IN_OE [] PH_OUT_OE [] PH_Z_OE_YN [] PH_Z_OE_RT# U_MI_LK_Y lose to codec 009 UVKX-GP [] U_MI_IN0 +.V_RUN U00 V Y R0 RJ--GP OE# GN LVG-GP [] MP_MUTE# U_MI_LK lose to codec U_VORE 0 0UVMX-GP VIO PH_Z_OE_ITLK PH_IN_OE_0 PH_OUT_OE PH_Z_OE_YN PH_Z_OE_RT# U_MI_LK U_MI_IN0 MP_MUTE# PUMP_PN PUMP_PP U00 V_ORE 9 V V_IO H_ITLK H_I H_O 0 H_YN H_RT# V V PV 9 PV ENE_ ENE_ HP0_PORT L HP0_PORT R 9 VREFOUT OR_F HP_PORT L HP_PORT R U_PK_L+ U_PK_L- PORT L 9 PORT R 0 VREFOUT_ MI_LK/GPIO MI0/GPIO PKR_PORT L+ 0 PKR_PORT L- MI/GPIO0/PIF_OUT_ PKR_PORT R- PIF_OUT_0 PKR_PORT R+ EP PORT_E_L PORT_E_R PORT_F_L P- PORT_F_R P+ P_EEP MONO_OUT P 0 VREFFILT P V- 9 GN VREG 9H9NLGXTX-GP U_ENE_ U_ENE_ U_EXT_MI_L U_EXT_MI_R U_VREFOUT_ U_HP_JK_L_ U_HP_JK_R_ U_P U_VREFFLT U_V_ U_VREG U_P_EEP +V U_EXT_MI_L [0] U_EXT_MI_R [0] U_PK_L+ [0] U_PK_L- [0] U_P_EEP Trace width> mils V_RUN 0 U0VKX-GP U_HP_JK_L U_HP_JK_R +PV U_VREFOUT_ [0] R0 00 _PKR_R U0VKX-GP 0KRF-L-GP K_EEP_R U0VKX-GP R0 0 99KRF--GP U_HP_JK_L [0] U_HP_JK_R [0] -0- connect U00 pin, pin to pin net and change R0 to 0K for vendor request From _PKR [] K_EEP [] From E V_RUN L00 0R00-P--GP L00 0R00-P--GP lose to codec PH_OUT_OE 0 0UVMX-GP +V R0 K9RF-GP Place this block close to udio odec Pin +V R0 RJ--GP U_ENE_ PH_Z_OE_OUT 0 KP0VKX-GP U_ENE_ R0 0KRF-L-GP R0 9KRF-L-GP st amsung 0RJ--GP R0 R0 RJ--GP 09 U0VKX-GP 0 UVKX-GP 0 U0VKX-GP 0 UVKX-GP L00 0R00-P--GP 0 U0VKX-GP 0 U0VKX-GP R0 0RF-GP R09 0RF-GP 0 0UVMX-GP 0 0UVMX-GP 0 UVKX-GP R0 00KRJ--GP 00 U0VKX-GP EXT_MI_J# [0] lose to Pin U_HP_J# [0] Revised HP/MI detect circuit 009/0/0 Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. UIO OE_9H ize ocument Number Rev Winery M I ate: Wednesday, January, 00 heet 0 of 00

31 (lank) st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. (Reserve) ize ocument Number Rev ustom Winery M I ate: Wednesday, January, 00 heet of 00

32 I = IO [] LK_PH_M PH GPIO(M) confirm with W _ [] _ [] +.V_RUN_R +.V_RUN_R trace = 0mil 0 U0VKX-GP 0 0UVMX-GP 0 U0VKX-GP +.V_RUN V_RUN_R RREF trace =mils UVKX-GP [] U_PN9 [] U_PP9 V RREF RREF M P V_IN R_V V GN LK_IN X_ P P P 0 P 9 X_# P P P P P P0 GPIO0 P9 P P P U0 RT-GR-GP _M _LK _# _M [] _LK [] _# [] lose to chip P0VJN-GP R0 KRF-GP 0 U0VKX-GP V trace =mils _0 WP _0 [] _ [] _WP [] st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ardreader/rt ize ocument Number Rev ustom Winery M I ate: Wednesday, January, 00 heet of 00

33 I = IO /MM/MM+ ard Reader +.V_RUN_R R +.V_RUN_R lose to +.V_RUN_R _0_R R R 9 V T0 T T 0 /T /WP/GN WP LK M EMPTY R _LK_R _M_R _# [] _WP [] UVKX-GP UVKX-GP 0UVKX-GP U0VKX-GP 0 0UVMX-GP NP NP NP NP GN T: 0.I00.00 N: R-PUH-9P--GP-U lose to R [] _0 [] _ [] _ [] _ [] _LK [] _M _0 _ R0 RJ--GP R0 RJ--GP R0 RJ--GP R0 RJ--GP _LK R0 _M R0 RJ--GP RJ--GP _0_R R R R _WP _LK_R _# _M_R E0 P0VN-GP E0 E0 E0 E0 E0 E0 E0 P0VN-GP P0VN-GP 0P0VKX-GP P0VN-GP P0VN-GP P0VN-GP P0VN-GP -0- pop E0,E0,E0,E0,E0,E0,E0 and change from 00p to.p for EMI I = 9 Remove 9 st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. R REER ONN ize ocument Number Rev Winery M I ate: Wednesday, January, 00 heet of 00

34 I = Expressard +.V_R Max. 0m, verage 00m. +.V_R Max. 00m, verage 000m +.V_RUX Max. m - NEW For nd ource V_RUN +.V_R +.V_R +.V_RUN U0 +.V_RUX +.V_LW +.V_R GN N# N# N# N# N# NEWR_O# +.V_RUN +.V_R +.V_RUN TP0 PM_LP_# [,,,0,,] PERT# PU# PPE# NRT +.V_R Max. 0m, verage 00m. +.V_R Max. 00m, verage 000m +.V_RUX Max. m Lay out close to hip UXOUT UXIN.VOUT.VIN.VOUT.VIN THERML_P O# 9 RLKEN TY# T:.0.0 N: V_LW PM_LP_# [,,0] PLT_RT# [9,,,,,0,,0] [] U_PN [] PH_M_LK [] PH_M_T +.V_R [,] PIE_WKE# +.V_RUX +.V_R [] NEWR_LKREQ# [] PIE_IRXN_NTXN [] PIE_IRXP_NTXP [] PIE_ITXN_NRXN [] PIE_ITXP_NRXP [] LK_PIE_NEW# [] LK_PIE_NEW -0 pop and change L0 to 0 ohm; R0, R0 for EMI remove R0, R0 for no co-lay after X U_N U_N U_P PU# PIE_IRXN_NTXN PIE_IRXP_NTXP PH_M_LK PH_M_T PIE_WKE# PERT# PIE_ITXN_NRXN PIE_ITXP_NRXP NEWR_LKREQ# PPE# LK_PIE_NEW# LK_PIE_NEW PTWO-ON--GP T: 0.K00.0 N: 0.K0.0 +.V_LW +.V_RUN +.V_R +.V_RUX T: N: [] U_PP U_P +.V_RUN +.V_R 0 dd commom choke L0 LWHNQL-GP 0 U0VKX-GP HN# 0 PERT# PU# 9 PPE# 0 YRT# TPRGP-GP-U R0 0 RN0 RN00KJ--GP 0RJ--GP P0VJN-GP U0VKX-GP U0VKX-GP 0UVMX-GP U0VKX-GP U0VKX-GP UVKX-GP 0UVMX-GP U0VKX-GP st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Expressard ize ocument Number Rev Winery M I ate: Wednesday, January, 00 heet of 00

35 (lank) st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. (Reserve) ize ocument Number Rev Winery M I ate: Wednesday, January, 00 heet of 00

36 I = User.Interface TPM board ONN +.V_RUN TPM [9,,,,,0,,0] PLT_RT# PLT_RT# [,,0] LP_L0 [,,0] LP_L [,,0] LP_L [,,0] LP_L R0 0RJ--GP [,,0] LP_LFRME# [,,] INT_ERIRQ [] PLK_TPM -0 dd R0 LP_L0 LP_L LP_L LP_L LP_LFRME# PLT_RT#_TPM INT_ERIRQ PLK_TPM 9 0 E-ON0--GP -- remove TPM FTP st amsung TPM Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev ustom Winery M I ate: Wednesday, January, 00 heet of 00

37 V_RUN_GPU +.V_RUN_GPU K_PWR K_PWR R change power rail to K_PWR R I = K +.V_RT_LO P_VER0 P_VER K_PWR +.V_RUN K_PWR E_Tx [] THERMTRIP_VG# _I_K []._GFX_ON [] P_I_E [] TURO_OOT_LERT# 0/. dded R 00 Ohm damping resistor. dded R 00 Ohm damping resistor. dded R 00 Ohm damping resistor PLK_K_R PLK_K GN _I_K 9._GFX_ON 9 THERMTRIP_VG_R# TURO_OOT_LERT# 0 K_THERMTRIP# 9 [] U_PWR_N_K U_PWR_N_K 0 [] K_L_ET# R 00RJ--GP K_L_ET_R# 0 GPU_PWR_EN# K_PWR [] GPU_PWR_EN# 0 P_INT_R# 0 Pull High : iscrete internal Pull Low for UM I R [,,,0,,] PM_LP_# KRJ--GP - K_PWRTN_E# 9 _IN_L# R 00RJ--GP _IN_R# 9 [9] LI_LOE# LI_LOE# 9 P_VER0 9 W_UM_I [] V_VG_ON V_VG_ON 09 P_VER 0 PWRLE# [] PWRLE# UM R9 [] PWR_TN_LE# PWR_TN_LE# KRJ--GP [] K_L_TRL K_L_TRL [] _OFF _OFF [] RMRT#_K RMRT#_K 0 [,,0] PM_LP_# PM_LP_# [] NUM_LOK_LE# NUM_LOK_LE# [,] V_V_POK V_V_POK [] PM_PWROK R0 PM_PWROK_R Remove [] E_PI_WP#_R 0R00-P--GP E_PI_WP#_R H_FLL_INT E_PWR_HN# [] LON_OUT LON_OUT [] IMVP_VR_ON R9 IMVP_VR_ON_R [] PI_ILE# 0R00-P--GP PI_ILE# [] GFX_ORE_EN GFX_ORE_EN [] ME_UNLOK# ME_UNLOK# [,] U_PWR_EN# U_PWR_EN# R0 0KRJ--GP R0 0KRJ--GP W 0/0 ummy.ummy R 0 UVKX-GP R R00-P--GP R KRJ--GP U0VKX-GP W 0KRJ--GP R 0KRJ--GP R L0 LMG0N-GP T:.000. N: U0VKX-GP [] [] VT P_INT# Q_ Q MMT90--F-GP W Put 0.uf close to V-GN pin pair. U0VKX-GP 0 U0VKX-GP W 0/0 assign GPIO.assign GPIO TUHPNEL_TP# 0 U0VKX-GP R 0RJ--GP 0 UVKX-GP 0 P0VN-GP R 0KRJ--GP U0VKX-GP 0 T:.090.H N:.090.L0 U0 VREF GPI90/0 GPI9/ GPI9/ GPI9/ GPIO0 GPIO0 GPI9 GPI9 GPI9 GPI9 R KRJ--GP GPIO0/T GPIO0 GPIO0 GPIO0 GPIO GPIO GPIO0 GPIO GPIO/_PWM GPIO/H_PWM GPIO0/F_PWM GPIO/TK GPIO/TM GPIO/TI GPIO/E_PWM GPIO/TRT# GPIO GPIO0/TO GPIO GPIO/R# GPIO GPIO0 GPIO GPIO GPO/TRI# V V V V V 9 / / GPIO THERMTRIP_VG_R# 0/0 dded.dded circuit, For prevent electric leakage GN GN GN GN GN GN 9 R 0KRJ--GP V 0 V LP M P PI Q09 MMT90--F-GP GN 0 T:.090.H N:.090.L0 +.V_RUN GN Q09_ +.0V_VTT 0 GPIO R0 0R00-P--GP R KRJ--GP 0 U0VKX-GP GPIO0/LPP# LREET# LLK LFRME# L0 L L L ERIRQ GPIO/LKRUN# KRT# G0 EI#/GPIO 9 GPIO/MI# 9 GPIO/PWUREQ# GPIO/ GPIO/L GPIO/ GPIO/L GPIO/G_PWM GPIO GPIO/HM GPIO GPIO 9 GPO/OUT_R/R GPIO/IN_R GPO/R0 ER/IR OF GPIO GPIO GPIO VORF NPE0X-GP R KRJ--GP THERMTRIP_GTE K_PWR V_RUN P_LOK_LE# PLT_RT#_ LP_L0 LP_L LP_L LP_L EI#_K PNEL_KEN EWI#_K K_ K_L TT_WHITE_LE EMI#_K E_Tx E_Rx VTT_PWRG_G K_VORF P_INT_R# R KRJ--GP U0VKX-GP T_IN# [] [] P_LOK_LE# [] PLK_K [] LP_LFRME# [,,0] INT_ERIRQ [,,] PM_LKRUN# [] KRIN# [] K0GTE [] K_ [] K_L [] T_ [,] T_L [,] LUETOOTH_EN [] WIFI_RF_EN [] WIRELE_ON#/OFF [] E_PWR_HN# LP_L[0..] [,,0] TT_WHITE_LE [] E_Tx [] E_Rx [] _PREENT_E [] K_PWRTN# W_UNW_I 0KRJ--GP _IN_L# EWI#_K.V_RUN_GPU_EN.0V_GFX_ON R_LOK_LE# L_TT_R TPT TPLK ERT# [9,] PURE_HW_HUTOWN# ERT#_ U0VKX-GP E K_THERMTRIP# Q0 [9,,] H_THRMTRIP# H90PT-GP Q0 T:.090.P dd reset I U0 to prevent PI ROM data lost H90PT-GP N:.090.T T:.090.H R0 0RJ--GP N:.090.R K_PWR [] E_PI_I [] PI_IO [] E_PI_# [] E_PI_LK K_PWR PM_LN_ENLE [] VTT_PWRG [9,9,] _ENLE [] R R00-P--GP 0 U0VKX-GP 0 need place near pin. Pull High : witch oard Pull Low : Unwitch oard K_PWR R -00 R KRJ--GP R KRJ--GP G [].V_RUN_GPU_EN [].0V_GFX_ON [] R_LOK_LE# [] L_TT [] TPT [] TPLK E_PI_I E_PI_# E_PI_LK K_PWRTN_E# 0R00-P--GP Q0 N00--GP [,,] [] - K_PWRTN# 0 T-U-GP R 0R00-P--GP K_ON# PLT_RT#_ PNEL_KEN GPU_ELET# T:.0.0F N: PH_ULK_K [0] - MP_MUTE# +.V_RUN 00KRJ--GP +.V_RT_LO EI#_K EMI#_K [] IMVP_VR_PWRG [] PM_PWRTN# [] HM_LTT_EN [0] K_EEP [] TT_ORNGE_LE [] LKLT_TL_E R0 0R00-P--GP R 0 T-U-GP K_ON# K_XI W_UNW_I MP_MUTE# HM_LTT_EN E_PI_O E_PI_LK_ K_PWR _IN# [] G +.V_RT_LO K_PWR PLT_RT# [9,,,,,0,,0] - PNEL_KEN_GPU [] PNEL_KEN_PH [0] EWI# [] EI# [] EMI# [] [9,] -- add U0 mux for panel backlight enable signal select U0 GN R REET# R0 0RJ--GP V G90L9TUF-GP 0R00-P--GP 0P0VKX-GP R 0KRJ--GP R 0RJ--GP 0RJ--GP V U0 0 GN NPX-GP 0 K R 0KRJ--GP XVTG-GP-U 0 K 0 K T--F-GP XVTG-GP-U XVTG-GP-U U0 PNEL_KEN_GPU [] PNEL_KEN_PH [0] T:.0.0H N:.0.E0J KX/KLKIN KX GPIO/LKOUT GPIO/T GPIO0/T GPIO/T GPIO/_PWM GPIO/_PWM GPIO/_PWM GPIO/PT GPIO/PLK GPIO/PT GPIO/PLK GPIO/PT GPIO/PLK F_I F_O F_0# F_K E I0-T-GE-GP Q0 P/ FIU 0 U0VKX-GP THERM_ OF KIN0 KIN KIN KIN KIN KIN KIN KIN V_POR# K_L KOUT0/JENK# KOUT/TK KOUT/TM 0 KOUT/TI 9 KOUT/JEN0# KOUT/TO KOUT/R# KOUT K KOUT KOUT9 0 KOUT0 9 KOUT KOUT/GPIO KOUT/GPIO KOUT/GPIO KOUT/GPIO/XOR_OUT GPIO0/KOUT GPIO/KOUT NPE0X-GP E_Rx K_L K_ T_ T_L K_THERMTRIP# R09 TURO_OOT_LERT# R WIRELE_ON#/OFF R0 K_L_ET# R0 K0GTE R KRIN# R 9 0 _ENLE R KOL0 R HM_LTT_EN R LUETOOTH_EN R PNEL_KEN R9 st amsung KOL0 KOL KOL KOL KOL KOL KOL KOL KOL KOL9 KOL0 KOL KOL KOL KOL KOL KOL TP_KOL TP0 KROW0 KROW KROW KROW KROW KROW KROW KROW ERT# U0 R RN0 RN0 +.V_RUN RNKJ--GP K_PWRTN# R 00KRJ--GP MN0LW--GP RNKJ--GP K_ 0KRJ--GP 00KRJ--GP +.V_RUN +.V_LW K_PWR +.V_RT_LO 0KRJ--GP 00KRJ--GP 0KRJ--GP 0KRJ--GP 0KRJ--GP 0KRJ--GP 0KRJ--GP 0KRJ--GP 0KRJ--GP 00KRJ--GP KOL[0..] [] KROW[0..] [] THERM_L [9,] +.V_RUN W Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. K Nuvoton NPE0X 0/0 hange.hange Power rail E0 UVKX-GP ize ocument Number Rev ustom Winery M I 00 Wednesday, January, 00 ate: heet of

38 (lank) st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. (Reserve) ize ocument Number Rev ustom Winery M I ate: Wednesday, January, 00 heet of 00

39 I = Thermal +V_RUN mil +.V_RUN R90 0KRJ--GP UVKX-GP 909 U0VKX-GP EM0_FN_TH_ EM0_FN_TH_ []. WWN T:.090.P N:.090.T H90PT-GP Q90 [] VG_THERM [] VG_THERM E. GPU ensor Q90 must be near WWN 9 must be near Q90 Layout notice: H_THERM, H_THERM routing together, Trace width / pacing = 0 / 0 mil W 0/ Removed.Removed YTEM ensor ritical. PU ensor Layout notice : oth VG_THERM and THERM routing 0 mil trace width and 0 mil spacing. 90 must be near Q90 E H90PT-GP Q P0VJN-GP T:.090.P N:.090.T.HW T sensor ( PU ) 9 0P0VJN-GP Layout notice : oth N and P routing 0 mil trace width and 0 mil spacing. W 90 must be near EM0 +.V_RUN 9 0P0VJN-GP 9 must be near EM0 90 0P0VJN-GP 90 must be near EM0 0/0 el. Not reserve power source rail for EM0?? 90 0P0VJN-GP EM0_V_ R90 99RF-GP 90 UVKX-GP EM0_N EM0_P VG_THERM VG_THERM T_THERM T_THERM +.V_RUN R9 0RJ--GP R9 0KRJ--GP V_V EM0_HN EM0_FN_mode GN = Fan is OFF OPEN = Fan is at 0% full-scale +.V = Fan is at % full-scale GN 9 U90 GN = hannel OPEN = hannel +.V = isabled R90 0KRJ--GP N P N P N P TH N# V_Va HN_EL 9 FNa FN_MOE 0 FNb TRIP_ET EM0_FN_RIVE V_Vb EM0 Y_HN# Y_HN# MLK THERMTRIP# MT POWER_OK# EM0_PWROK EM0_THERMTRIP# +.V_RUN HN#_G G RN90 R90 0KRJ--GP RNKJ--GP N# GN 0 LERT# LK_IN LK_EL REET# N# TP_LERT# LK_K +.V_RUN THERM_L [,] THERM_ [,] 9 EM0-ZK-GP Q90 N00--GP T:.N0.E N:.N0. EM0_LK_EL TP_EM0_REET# T:.00. N:.09.0 RN90 RN0KJ--GP K_PWR R9 0KRJ--GP mil TP90 TP-GP R90 0KRJ--GP TP90 TP-GP V_EGREE +.V_RUN +.V_RUN PURE_HW_HUTOWN# [,] EM0_FN_RIVE [] GN = Internal Oscillator elected +.V = External.kHz lock elected 90 U0VKX-GP 90 U0VKX-GP +.V_RUN R90 0KRF--GP TRIP_ET Pin Voltage V_EGREE=(((egree-)/) T shutdown is set deg R90 KRF-GP K suspend clock output T:.N0.E N:.N0. W 0/ Removed. Removed U90 N gate. [] PH_ULK_0 Q90 N00--GP LK_K_R R9 LK_K st amsung G 0RJ--GP 9 P0VN-GP Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RUN_POWER_ON [,] Thermal/Fan ontrollor EM0 ize ocument Number Rev ustom Winery M I ate: Wednesday, January, 00 heet 9 of 00

40 I = User.Interface Free Fall ensor +.V_RUN Note - no via, trace, under the sensor (keep out area around mm) - stay away from the screw hole or metal shield soldering joints - design P pad based on our sensor LG pad size (add 0.mm) - solder stencil opening to 90% of the P pad size - mount the sensor near the center of mass of the N as possible as you can 00 0UVMX-GP +.V_RUN +.V_RUN [,,9,,,] [,,9,,,] PH_MLK PH_MT H_FLL_O R00 0RJ--GP 00 U0VKX-GP U00 L/P /I/O O V REERVE# REERVE# V_IO INT INT 9 GN GN GN GN 0 R00 00KRJ--GP H_FLL_INT FF_INT_R 0/ heck.h_fll_int [ GPIO Table ]?? H_FLL_INT [] +.V_RUN G T:.N0.E N:.N V_RUN R00 00KRJ--GP ELTR-GP FF_INT_L K FF_INT [9] 09/0 (#) Just pull +.V_RUN ~ Ref. Rothschild (#) FE/ is ok, chip internal pull-up resistors (#) From spec, lave dress() is 000xb Pull HIGH is 000b Pull GN is 0000b Q00 N00--GP FF_INT_R [] M0U0--GP T:.R00.0M N: -0 Note () Keep all signals are the same trace width. (included V, GN). () No VI under I bottom. st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Free Fall ensor ize ocument Number Rev ustom Winery M I ate: Wednesday, January, 00 heet 0 of 00

41 (lank) st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. (Reserve) ize ocument Number Rev ustom Winery M I ate: Wednesday, January, 00 heet of 00

42 I = Reset.uspend Remove +.V_ELY power rail 009/0/ H_THRMTRIP# [9,,] [9,] H_PWRGOO R KRJ--GP H_PWRG_R 0 U0VKX-GP E Q0 HTPT-GP [] V_V_EN T:.0.0F N: 0 K PURE_HW_HUTOWN# [,9] XVTG-GP-U R09 00KRJ-L-GP R0 KRJ--GP _ENLE [] +.V_RT_LO +V_RUN Peak current:. esign current:. +V_LW [] P_NTRL P_NTRL R0 00KRJ--GP +V_LW RUN_POWER_ON R0 0KRJ--GP RUN_ON_V 0 00PVKX-GP U0 G O-GP. Rds=m ohm T:.0.0 N:.0.0 Q0 MN0LW--GP [,,,0,,] PM_LP_# RUN_POWER_ON [9,] R0 00KRJ--GP +.V_RUN R 0KRJ--GP RUN_ON_V 0 0UVKX-GP R KRF-L-GP 0 0UVKX-GP G +.V_RUN U0 RUN_ON_VR G +.V_LW U0 O-GP Peak current: 9m esign current:.m. Rds=m ohm -0 Peak current: 0m esign current: m O-GP. Rds=m ohm T:.0.0 N:.0.0 T:.0.0 N: V_U st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Power Plane Enable Winery M I ize ocument Number Rev ustom ate: Wednesday, January, 00 heet of 00

43 I = IN +V_LW PR0 KRJ--GP PI_PRO PR09 00KRJ--GP E PQ0 H90PT-GP G PR0 0KRJ--GP PI_ILE#_R PQ0 FV0N-NL-GP PR0 P_I P0 V99--GP PR0 PI_ILE# [] +.V_LW +.V_LW P_I_E [] RJ--GP [] P_I_R P_I_R PR0 RJ--GP This cap should be used only as last resort for EMI suppression. -0- pop P0 for RF P0 P0VN-GP +_IN P0 PR0 UVKX-GP 0KR-GP P0 0UVKX-GP [] _OFF PQ0 R IN R OUT GN TEU-F-GP _OFF_L PQ0 R R E PTEU--GP _OFF_R 0RJ--GP P0 V99--GP PR0 KRJ--GP +_IN_ PU0 G O0-GP P0 0UVKX-GP P0 0UVKX-GP P0 0UVKX-GP PR0 KRJ-L-GP Id=- Qg=-n Rdson=0~mohm st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IN ize ocument Number Rev ustom Winery M I ate: Wednesday, January, 00 heet of 00

44 I = TT att onnecter TT GN GN 0 GN 9 GN T_LERT Y_PRE# TT_PR# T_M LK_M TT+ TT+ FOX-ON9--GP PT_LRM# PT_PRE# PT_MT PT_MLK FTP0 FTP0 PR0 P0 U0VKX-GP 00RJ--GP T: N: PT_PRE# PT_MT PT_MLK +PTT FTP0 FTP0 FTP0 FTP0 T_IN# T_ T_L P0 00P0VKX-GP PR0 K_PWR PRN0 0KRJ--GP RN00J--GP T_IN# [] T_ [,] T_L [,] +PTT TT_ENE [] PG0 GP-LOE-PWR--GP P0 V99--GP P0 V99--GP P0 V99--GP +.V_RT_LO st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. att onnecter ize ocument Number Rev Winery M I ate: Wednesday, January, 00 heet of 00

45 I = harger +_IN PU0 +PTT O0-GP +_IN_ G +PWR_R PU0 +_IN_ PR0 G 0RF--GP O0-GP PG09 PG0 GP-LOE-PWR--GP GP-LOE-PWR--GP PR_0 PR 00KRJ--GP Id=- Qg=-n Rdson=0~mohm PR 0KRJ--GP Id=- Qg=-n Rdson=0~mohm PR 0KRJ--GP GP-LOE-PWR--GP PG PR_0 +_IN_ GP-LOE-PWR--GP GP-LOE-PWR--GP PG0 GP-LOE-PWR--GP PG0 PG0 PR 0KRF--GP PR_0 PR 0RJ--GP PQ0_0 PQ0 PQ0_0 PR 0R00-P--GP PR 0R00-P--GP Q_OK HGER_R KRF--GP PR0 MN0LW--GP HGER_R P U0VKX-GP P9 U0VKX-GP HG_GN PR 0R00-P--GP E0 UVZY-GP P UVKX-GP P0 Q_P Q_IN P U0VKX-GP Q_IN U0VKX-GP Q_REF IN +.V_RT_LO Q_N HG_GN Q_LO N Q_IOUT VM IOUT PR P0 0R00-P--GP HG_GN Q_OOT_ Q_T PR OOT K Q_LO harger urrent=.~. 0R00-P--GP Q_OK VP P 0W--GP U0VKX-GP OK P U0VKX-GP P 0UVKX-GP P 0UVKX-GP P IREF IN E0 00P0VKX-GP G PU0 I00-T-GP PR0 RJ--GP -0. change PL0 to.r0.0 P U0VKX-GP PR 0KRF--GP PR 0KRF--GP Q_HRGER_UGTE PR 0R00-P--GP HG_GN V_IN +PTT PL0 P 00P0VKX-GP Q_LX P U0VKX-GP UGTE L 0 T_L_ PG0 GP-LOE-PWR--GP T_L [,] P 0U0VKX-GP PR0 KRF--GP +VHGR PR9 0RF--GP PHE 009/0/0 Q_PHE_GN Q_LGTE_ T P 0UVKX-GP P0 0UVKX-GP L-UH-GP T_ [,] HG_GN 009/0/ PR0 KRF-GP P0 MTG-GP P U0VKX-GP K PG0 GP-LOE-PWR--GP 9 P 0UVKX-GP P 0UVKX-GP PG0 GP-LOE-PWR--GP P 0P0VJN-GP 0 LGTE PG0 GP-LOE-PWR--GP PU0 I00-T-GP G PGN 9 N# PR0 0R00-P--GP _I_K [] Q_OP_ OP HG_GN Q_VIM ON Q_FO VIM Q_PR0-0 PR0 0R00-P--GP PR 00KRF-L-GP HG_GN Q_OP Q_EI FO P0 Q_EO EI N# PR PR 00P0VKX-GP Q_REF EO 0R00-P--GP PR_0 KRF--GP Q_E VREF P PR0 E Q_ON GN VF PR 0P0VJN-GP 0R00-P--GP 0R00-P--GP T_ENE P PU0 TT_ENE [] P0VJN-GP QRHR-GP PR09 P U0VKX-GP KRJ--GP U0VKX-GP P GN Q_FO PR9 P 0P0VJN-GP PR0 KRF--GP P U0VKX-GP P U0VKX-GP 9 0R00-P--GP P UVKX-GP P9 0U0VKX-GP P U0VKX-GP HG_GN PR KRJ-GP HG_GN HG_GN P UVZY-GP P 0U0VKX-GP HG_GN This Resistor must be % tolerance. +.V_RT_LO PR 00KRJ--GP [] _IN# PQ0 st amsung N00--GP Wistron orporation G V_IN P UVKX-GP F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. 009//9 HRGER Q Winery M I 00 ize ocument Number Rev ustom ate: Wednesday, January, 00 heet of

46 G G E PQ0 +PWR_R +PWR_R_V N00--GP _ENTIP +.V_LW +V_PWR PG0 GP-LOE-PWR PG0 GP-LOE-PWR PG0 GP-LOE-PWR PG0 GP-LOE-PWR PG I = PWR.Plane.Regulator_V/V I(uburndale) esign urrent =.0.9<OP< +PWR_R_V 009/0/0 GP-LOE-PWR P0 P P TP:0RJ/ L TP:0RJ/ L PG +V_PWR RT0 :R/.R0.L RT0 :R/.R0.L +V_LW I(uburndale) PG P P P GP-LOE-PWR 009/0/ esign urrent =. PG PU0 PU0 +PWR_R 0.<OP<. +PWR_R_V GP-LOE-PWR IN-T-GE-GP IN-T-GE-GP PG PU0 GP-LOE-PWR 009/0/ PG PG P PR0 PR0 GP-LOE-PWR UVKX-GP RF-L-GP RF-L-GP UVKX-GP PG P G 00-- GP-LOE-PWR GP-LOE-PWR G _VT VT 9 _VT _VT_ changepl0 from.u to.u by power PG OOT OOT PG0 +V_PWR 009/0/0 GP-LOE-PWR -0 PL0 _RVH 0 _RVH +V_PWR PL0-0 PG UGTE UGTE +V_LW GP-LOE-PWR GP-LOE-PWR _LL 0 _LL PG PHE PHE PG IN-UH--GP IN-UH-GP GP-LOE-PWR P9 PT0 PT0 _RVL 9 _RVL PG9 LGTE LGTE GP-LOE-PWR GP-LOE-PWR PG PR0 PG RF--GP PU0 _VO _VO PU0 PR0 PG0 PT0 PT0 P0 GP-LOE-PWR VOUT VOUT 009/0/0 RF--GP PG0 _F _F GP-LOE-PWR F F PG9 GP-LOE-PWR _EN V_V_POK PG PR0 0KRF-GP EN PGOO G GP-LOE-PWR P0 G _ENTIP _ENTIP PG 0P0VKX-GP _VREF ENTRIP ENTRIP GP-LOE-PWR P 0P0V-GP PG REF PGN GP-LOE-PWR _TONEL PG TONEL GN GP-LOE-PWR PR PG _VLK 0RJ--GP -0- GP-LOE-PWR PR0 KIPEL LG_P 009/0/ X0 _KIPEL change P0 pull up to +V_LW for layout. PR09 0RJ--GP PR GP-LOE-PWR KRF-GP TP: RT0GQW-GP KRF-GP RT0 :M _F_R _F_R P +V_LW +.V_RT_LO P P0VJN--GP P0VJN--GP +.V_LW_ PG PR 0R00-P--GP PR PR PR _VREF GP-LOE-PWR--GP 00KRJ--GP KRF-GP 0KRF--GP PR lose to VF Pin (pin) +.V_LW_ 009/0/ X0 V_V_POK [,] 0RJ--GP U0VKX-GP T00UVM-GP T0UVM-GP GP-LOE-PWR--GP 0U0VKX-GP lose to VF Pin (pin) 0UVKX-GP GP-LOE-PWR PG09 GP-LOE-PWR PG GP-LOE-PWR _LL_R _VREF +.V_LW_ [] V_V_EN PR 0RJ--GP 00-- pop PR9; dummy PR by power to improve +V_Pump Power on issue I/P cap: 0U V K0 XR/.0.L Inductor:.UH PM0T-RM yntec.mohm Isat =rms.r0.0 O/P cap: 0U.V PLV0JM() mohm.rms NE_TOKIN/..00L O/P cap: 00U.V TEPL0J0M()R mohm.rms NE_TOKIN/.0.0 H/: in mohm/0mohm@.vgs/.00.0 L/: in.mohm/.mohm@.vgs/.090.e TONEL H H GN 00kHz khz VREF khz 0kHz 0UVKX-GP PG0 GP-LOE-PWR PG0 GP-LOE-PWR PG0 G G IN-T-GE-GP _ENTRIP +PWR_R PR _EN 009/0/ X0 0KRF-GP P P 009/0/ X0 U0VKX-GP PR 0RJ--GP PR9 0R00-P--GP VREG VREG PR G 009/0/ X0 P TP TP:M RT0 : 00kHz khz khz 0kHz RT0 M V_UX P U0VKX-GP VREG P0 P0VJN--GP VIN +.V_LW ENTIP +.V_LW_ +.V_RT_LO PR0 0R00-P--GP KIPEL VREG or VREG VREF(V) Operating OO uto kip uto kip Mode EN0 VREG P 0U0VKX-GP 0UVKX-GP 009/0/ 0U0VKX-GP UVMX-GP P Open PR0 0KRF-GP PQ0 MN0LW--GP PR0 00KRJ--GP P0 P0VJN--GP 0k to GN Operating Mode enable both enable both LOs, disable all LOs, VLK on VLK off and circuit and ready to ready to turn on turn on switcher channels switcher st amsung channels GN PWM only GN PR0 0KRF-GP 009/0/ IN-T-GE-GP 0UVKX-GP _LL_R _VLK +V_LW +PWR_R_V 0UVKX-GP GP-LOE-PWR--GP P0 KP0VKX-GP P0 T--GP PG0 GP-LOE-PWR--GP 0U0VKX-GP P90_ P90_ P0 UVKX-GP P09 UVKX--GP P90_0 P90_ P0 UVKX-GP P0 T--GP +V_PWR P0 UVKX-GP I/P cap: 0U V K0 XR/.0.L Inductor:.uH PM0T-RMN yntec 0 mohm Isat =rms.r0.0 O/P cap: 0U.V PLV0JM() mohm.rms NE_TOKIN/..00L O/P cap: 00U.V TEPL0J0M()R mohm.rms NE_TOKIN/.0.0 H/: in mohm/0mohm@.vgs/.00.0 L/: in.mohm/.mohm@.vgs/.090.e T0UVM-GP T00UVM-GP P0 UVKX-GP U0VKX-GP Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RT0_V/V ize ocument Number Winery M I Rev 00 ustom Wednesday, January, 00 ate: heet of E

47 I = PWR.Plane.Regulator_PU ore _GN NT 0K close to H/ MOFET of Phase [9] H_PROHOT# _NT_R PR _GN PR NT-0K--GP K0RF-GP _GN 0UVKX-GP P9 PR K0RF-GP _GN IEN P P0VJN-GP [] IEN [] IEN [] IEN +PWR_R -0- remove T0 for layout PR 0RJ--GP +.0V_VTT _OMP_R P PR 0P0VJN-GP KRF-GP IEN IEN IEN T0 PR R-GP E00UVM-0GP [] IMVP_VR_PWRG [] PI# +.V_RUN PR9 K9RF--GP 009/0/9 P0 000P0VJN-GP-U P P0VJN-GP [] V_ENE [] _ENE UVKX-GP _NT _VW _OMP _F IEN _F_VEN [] VR_LKEN# 009/0/9 +.V_RUN P PR9 PR9 RF-GP 90P0VKX-GP 0R00-P--GP V_ENE_L PR0 K9RF--GP 009/0/9 PR K9RF--GP _PGOO PR 0R00-P--GP PGOO _PI# PR 0R00-P--GP PI# _RI PR KRF-GP RI VR_TT# UVKX-GP IEN _LK_EN# PR 0R00-P--GP _PRLPVR _VR_ON ILHRTZ-T-GP _GN P9 UVKX-GP 9 PU0 NT VW OMP F IEN/F IEN 0 P IEN P GN P 0P0VKX-GP P9 0P0VKX-GP _GN 0 LK_EN# IEN PR 0R00-P--GP PRLPVR 9 VEN P0 000P0VJN-GP-U PR 0R00-P--GP VR_ON RTN PM_PRLPVR [] PU_VI _VI PR 0R00-P--GP VI IEN PR KRF-L-GP VUM+ PR9 KRF-GP VUM- PR0 RF-GP IEN PR KRF-L-GP IEN PR KRF-L-GP VUM- IUM- PU_VI _VI VUM+ VUM_R _GN IMVP_VR_ON [] PR 0R00-P--GP VI IUM+ PU_VI _VI _V PR9 0R00-P--GP VI V PU_VI _VI PR0 0R00-P--GP VI VIN _VIN PU_VI _VI PR 0R00-P--GP P U0VKX-GP VI IMON PU_VI _VI PU_VI0 _VI0 _GN _GN PR RF--GP PR 0R00-P--GP VI OOT 9 PR 0R00-P--GP VI0 UGTE 0 PR9 K0RF-GP UGTE PU_VI[..0] [] OOT UGTE PHE LGTE _VP _PWM LGTE PHE _OOT PR IMVP_IMON RJ--GP +PWR_R PR 0R00-P--GP +V_LW RF-GP P PR9 UVKX-GP P 0UVKX-GP OOT UGTE PHE P LGTE VP PWM/LGTE# LGTE P PHE KRF-GP 009/0/9 0 9 P P UVKX-GP PR 0UVKX--GP OOT [] UGTE [] PHE [] OOT_PHE VUM_RR _GN 0_PWM LGTE [] LGTE [] 0_FM P UVKX--GP PR KRF-L-GP PR 0R00-P--GP U0VKX-GP P PHE [] _ENE [] PR KRF--GP PWM FM PU0 +V_LW +V_LW PR 0RJ--GP PR9 00KRF-L-GP P0 U0VKX-GP PR9 NT-0K--GP V PR0 0R00-P--GP GN GN P U0VKX-GP OOT VUM+ [] _GN 9 OOT PHE UGTE LGTE IL0RZ-TGP-U PR 0RJ-0-U-GP P U0VKX-GP UGTE [] IMVP_IMON [] +.0V_VTT 0_PHE PR RJ--GP PHE UGTE LGTE 009/0/9 P UVKX--GP UGTE PHE -0. change PR to.0.l. change PR9 to.0.l. change P to.0.l. change P to..fl PR9 GP-LOE-PWR--GP LGTE I0N-T-GE-GP G I0N-T-GE-GP G PU0 PU0 PU_VI0 PU_VI PU_VI PU_VI PU_VI PU_VI PU_VI PM_PRLPVR PI# P NUER 0UVKX-GP VUM- _IUM- VUM- VUM- [] NT 0K close to hoke of Phase P UVKX-GP -0- change P to 00 size VUM- 009/0/9 +.0V_VTT +PWR_R P 0UVKX-GP PR0 RF--GP 009/0/9 st amsung PHE_R L0 IN-UH--GP-U Intel support PO (power on current). PR PR PR PR PR9 PR90 PR9 PR9 PR9 KRJ--GP PG GP-LOE-PWR--GP PR0 PR PR PR PR PR PR PR PR KRJ--GP KRJ--GP KRJ--GP P0 0P0V-GP KRJ--GP P KRJ--GP 0UVKX-GP KRJ--GP KRJ--GP P U0VKX-GP KRJ--GP KRJ--GP ate: Wednesday, January, 00 heet of KRJ--GP KRJ--GP +V_ORE_PHE PG GP-LOE-PWR--GP PT0 +V_ORE _GN Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IL_PU_ORE_/ ize ocument Number Rev ustom 00 KRJ--GP KRJ--GP KRJ--GP KRJ--GP Winery M I T0UVM--GP PT0 KRJ--GP KRJ--GP T0UVM--GP

48 I = PWR.Plane.Regulator_PU ore +PWR_R P P P P UGTE [] UGTE PHE [] PHE OOT 00T_R [] OOT PR P RJ--GP UVKX--GP [] LGTE IEN [] IEN VUM+ [] VUM+ VUM- [] VUM- IEN [] IEN IEN [] IEN LGTE I0N-T-GE-GP G I0N-T-GE-GP G PU0 PU0 0UVKX-GP NUER PR0 KRF-L-GP PR0 KRF-GP PR0 RF-GP PR0 KRF-L-GP PR0 KRF-L-GP 0UVKX-GP PR RF--GP 009/0/ P0 0P0V-GP 009/0/ 0UVKX-GP U0VKX-GP L0 IN-UH--GP-U PG0 GP-LOE-PWR--GP PHE_R +V_ORE_PHE PG0 GP-LOE-PWR--GP PT0 T0UVM--GP +V_ORE PT0 T0UVM--GP I(uburndale) esign urrent = Peak urrent=.<op<. +PWR_R P P9 P0 P [] UGTE [] PHE [] LGTE PHE LGTE UGTE I0N-T-GE-GP G I0N-T-GE-GP G PU0 PU0 0UVKX-GP NUER 0UVKX-GP PR RF--GP 009/0/ P0 0P0V-GP 0UVKX-GP U0VKX-GP PG0 GP-LOE-PWR--GP L0 IN-UH--GP-U PG0 GP-LOE-PWR--GP PT0 T0UVM--GP +V_ORE PT0 E0UVM-GP I/P cap: 0U V K0 XR/.0.L Inductor: 0.UH ETQPLRWF PNONI.mohm/.R0.0 O/P cap: 0U V EEFX0E mohm.0rms Panasonic/9.9.0L O/P cap: 0U V EEFX0XE mohm.rms Panasonic/9.9.90L H/: irp/ POWERPK-/ L/: i0p/ POWERPK-/.mOhm/.mohm@.Vgs/.00.0 Freq=00KHz@PER PHE [] IEN [] VUM+ [] VUM- [] IEN [] IEN 009/0/ IEN VUM+ VUM- IEN IEN PR0 KRF-L-GP PR0 KRF-GP PR09 RF-GP PR0 KRF-L-GP PR KRF-L-GP 009/0/ PHE_R +V_ORE_PHE st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev ustom Winery M I ate: Wednesday, January, 00 heet of IL_PU_ORE_/ 00

49 G G G G I = PWR.Plane.Regulator_0V_VTT +PWR_R +PWR_R_0V TP for +.0V_VTT PG90 GP-LOE-PWR PG90 GP-LOE-PWR PG90 +PWR_R_0V GP-LOE-PWR PG90 GP-LOE-PWR PG90 GP-LOE-PWR 009/0/ [0,] RUNPWROK VTT_PWRG P9 UVKX-GP +.V_RUN [9,,] PR90 0KRF-GP PR9 0R00-P--GP PR90 0KRJ--GP VTT_PWRG P90 KP0VKX-GP _VTT_TRIP _VTT_EN _VTT_VF _VTT_M PR90 0KRF-GP PQ90 MN0LW--GP PU90 PGOO TRIP EN VF M H_VTTPWRG_R GN VT 0 RVH 9 W VIN RVL TPR-GP-U +.V_LW PR90 00KRJ--GP +.0V_VTT PR909 KRJ--GP P90 PR90 UVKX-GP RJ--GP _VT_VTT _VT_VTT _RVH_VTT _W_VTT _RVL_VTT +V_LW P90 U0VKX-GP PU90 I0N-T-GE-GP PU90 I0N-T-GE-GP PU90 I0N-T-GE-GP PU90 I0N-T-GE-GP 0UVKX-GP PR90 _VTT_VF P9 P9 0UVKX-GP _W_GN_VTT P909 RJ--GP 0P0VKX-GP 0UVKX-GP - P90 PL90 IN-UH--GP -0 0UVKX-GP GP-LOE-PWR--GP +.0V_VTT_VOUT PR90 9KRF-GP PR90 0KRF--GP P90 R R U0VKX-GP PG9 P90 UVKX-GP UVKX-GP PR9 0RJ--GP P90 P90 U0VKX-GP I(rrandale.0V_VTT) esign urrent =..<OP<.9 P90 VTT_ENE [] 009/0/ PT90 +.0V_VTT_P 009/0/0 Vout=0.0V*(R+R)/R E0UVM-L-GP PT90 E0UVM-L-GP - PT90 E0UVM-L-GP +.0V_VTT_P PG90 GP-LOE-PWR PG90 GP-LOE-PWR PG9 GP-LOE-PWR PG9 +.0V_VTT GP-LOE-PWR--GP PG9 GP-LOE-PWR--GP PG9 GP-LOE-PWR--GP PG9 GP-LOE-PWR--GP PG9 GP-LOE-PWR--GP PG99 GP-LOE-PWR PG9 GP-LOE-PWR PG9 GP-LOE-PWR PG99 GP-LOE-PWR +.0V_VTT_P PG909 GP-LOE-PWR PG90 GP-LOE-PWR PG9 +.0V_VTT GP-LOE-PWR--GP PG9 GP-LOE-PWR--GP PG9 GP-LOE-PWR--GP PG9 GP-LOE-PWR--GP PG90 GP-LOE-PWR PG9 GP-LOE-PWR PG9 GP-LOE-PWR PG9 GP-LOE-PWR PG9 GP-LOE-PWR PG90 GP-LOE-PWR -0 H_VTTPWRG H_VTTPWRG [9] Frequency setting 0K -->90KHz 00K -->0KHz 00K -->0KHz 9K -->0KHz I/P cap: 0U V K0 XR/.0.L Inductor: 0.uH PM0T-RMN yntec R:.mohm Isat=rms.R0.0 O/P cap: 0U.V EEFX0ER 9mOhm rms PNONI/ 9.9.L0 H/: i0n/ L/: i0n/ POWERPK-/.mOhm/mohm@.Vgs/ st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. TP_+.0V_VTT ize ocument Number Rev ustom 00 Winery M I Wednesday, January, 00 ate: heet of 9

50 G G G G I = PWR.Plane.Regulator_V/0V -00- PR0-0 +V_LW PR00 RJ-GP +V_LW [,,,,,] PM_LP_# PR0 0RJ--GP 0V_EN 0V_EN [] 009/0/0 +PWR_R_V [9,] RT: Non_M TI: M +0V_R_P P00 U0VKX-GP RUNPWROK P009 0UVMX-GP PR0 +V_LW +.V_LW +.V_U_P PR00 +0V_R_P PR00 +.V_U_P 0R00-P--GP esign urrent = 0. P00 0UVMX-GP PR00 0KRF-L-GP P0 0UVMX-GP PR00 KRF-GP P00 KP0VKX-GP 0KRF-GP TP_V TP_V_R P00 U0VKX-GP MRJ-GP P0 KP0VKX-GP TP_N# V_EN 0V_EN TP_TON +0V_R_P PG0 GP-LOE-PWR PG0 GP-LOE-PWR tate VR VTTREF VTT 0 Hi Hi On On On Lo Hi On On Off(Hi-Z) / Lo Lo Off Off Off 0 ILIM PG N# EN/PV VTTEN VTTIN N# VTT VTT +0.V_R_VTT VP TP_REF VP REF T H LX L F 0 9 TPRGER-GP-U PGN PGN PGN TON VQ GN U0VKX-GP P0 PU00 V 9 +V_R_REF PR0 0R00-P TP_UGT TP_LGT P09 U0VKX-GP TP_VT TP_UGT TP_PH TP_LGT P0 0UVKX-GP TP_VT TP_VQN TP_VQET P0 UVKX-GP TP_VT +V_LW PR00 0RJ-0-U-GP PR00 0RJ--GP P00 U0VKX-GP +V_LW P00 HH-0PT-GP 009/0/0 +PWR_R_V PU00 I0N-T-GE-GP TP_PH PU00 I0N-T-GE-GP GP-LOE-PWR PG00 GP-LOE-PWR W 0/0 el. Not reserve.v_run_en?? 009/0/0 +PWR_R +PWR_R_V PG00 [,,] GP-LOE-PWR PG00 GP-LOE-PWR PG00 PU009 I0N-T-GE-GP PU00 I0N-T-GE-GP PM_LP_# P0 0UVKX-GP P00 0UVKX-GP PR00 RF--GP PR0 0R00-P--GP TP_PH_ET PL00 IN-UH--GP P00 0UVKX-GP P0 0P0VKX-GP TP_VQN -0 PR009 0K9RF-GP P00 U0VKX-GP PG0 GP-LOE-PWR--GP V_EN P0 U0VKX-GP P00 UVKX-GP P00 U0VKX-GP P0 UVKX-GP P0 P0VJN--GP I(uburndale) esign urrent =..<OP<.9 P0 U0VKX-GP +.V_U_P PT00 E0UVM-GP PT00 E0UVM-GP 009/0/ +.V_U_P +.V_U PG00 GP-LOE-PWR PG00 GP-LOE-PWR PG00 GP-LOE-PWR PG00 GP-LOE-PWR PG009 GP-LOE-PWR PG0 GP-LOE-PWR PG0 GP-LOE-PWR PG0 GP-LOE-PWR PG09 GP-LOE-PWR PG00 GP-LOE-PWR PG0 GP-LOE-PWR PG0 GP-LOE-PWR TP_VQET VQET GN VIN F Resistors VQ (V).. djustable VTTREF and VTT VVQN/ VVQN/ VVQN/ NOTE R R. V < VVQ < V I/P cap: 0U V K0 XR/.0.L Inductor: 0.uH PM0T-RMN yntec R:.mohm Isat=rms.R0.0 O/P cap: 0U.V EEFX0ER 9mOhm rms PNONI/ 9.9.L0 H/: i0n/ L/: i0n/ POWERPK-/.mOhm/mohm@.Vgs/ witching freq-->00khz PR00 0KRF-GP lose to VF Pin (pin) st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. TP_+.V_U ize ocument Number Rev ustom 00 Winery M I Wednesday, January, 00 ate: heet of 0

51 I = PWR.Plane.Regulator_V PL90 for +.V_RUN +.V_LW PG0 [,,,,0,] PM_LP_# [9,0] RUNPWROK R0 V_RUN_EN 0R00-P--GP +V_LW change R0 to short pad, P0 to 0K for power's suggestion To prevent PM_LP_# signal rebound U0VKX-GP P0 PU0 POK EN PL90KI-TRG-GP P0 0KRJ--GP VNTL GN VIN# VIN#9 9 VOUT# VOUT# F P0 O--P V_VIN 9_.V_RUN_F P0 KRF-GP PR0 P0VJN-GP GP-LOE-PWR PG0 GP-LOE-PWR P0 PR0 KRF-L-GP UVMX-GP 009/0/9 +.V_RUN_P I(rrandale) esign urrent =0. 009/0/9 Vout=0.V*(R+R)/R RT90 for +.V_RUN_GPU +.V_LW +V LO I: Peak current:00m esign current:0m +.V_PWR PG0 +.V_RUN_GPU [,] GPU_V_PGOO []._GFX_ON +V_LW GPU_V_PGOO RT90_EN P U0VKX-GP 0UVMX-GP 0UVMX-GP P0 UVMX-GP P0 +.V_RUN_P +.V_RUN PG0 GP-LOE-PWR PG0 GP-LOE-PWR PG09 P 0U0VKX-GP P09 0U0VKX-GP GP-LOE-PWR PG0 GP-LOE-PWR PU0 PR0 0R00-P--GP PGOO GN EN J VIN VOUT V N# GN RT90-PP-GP 9 PR0 KRF-GP RT90_F PR0 KRF-L-GP P 00P0VJN-GP P 0U0VKX-GP P0 0U0VKX-GP GP-LOE-PWR PG0 GP-LOE-PWR P UVKX-GP Vo=0.*(+(R/R)) st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev ustom Winery M I ate: Wednesday, January, 00 heet of PL90/RT90 00

52 I = PWR.Plane.witch_V PU -00- R, R, R; POP R, 0, R, R0, Q0, R. +0.V_R_VTT [9,,9] VTT_PWRG R0 00KRJ--GP 0V_EN 0V_EN [0] Q0_ [] P_NTRL P_NTRLG T:.N0.E N:.N0. P_NTRL G T:.N0.E N:.N0. +.V_PU: +.V_U MX urrent 000 m esign urrent 00 m +.V_PU alpella Platform Power Reduction Platform Power Reduction R Implementation esign etails Revision 0. W 0/0 dded.dded discharge circuit +.V_PU 00-- remove R, R, R for cost down Q0_ [9,] RUN_POWER_ON RUN_POWER_ON R 0KRJ--GP T: N:.V_PU_ENLE Rds(on) =. mohm (Max) Q0 G IR0P-T-GE-GP 00-- change Q0 from.00.0 to P_NTRL T:.N0.E N:.N0. R RJ--GP Q0 N00--GP Q0 N00--GP R RF--GP 0 0UVKX-GP G Q0 N00--GP 00-- change R to 0K; remove R for cost down 09 0U0VKX-GP W 0/0 corrected. Removed. RemovedQ0,R,R0 to save more part counts st amsung to V Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev ustom Winery M I ate: Wednesday, January, 00 heet of 00

53 9 G G I = PU.GFX.Regulator +PWR_R +PWR_R_PU_GFXORE -0- change PR from K to 0R +V_LW KP0VKX-GP P GN I 0P0VJN-GP _F_ PG0 GP-LOE-PWR PG0 GP-LOE-PWR PG0 GP-LOE-PWR PG0 GP-LOE-PWR PG09 GP-LOE-PWR [] GFX_IMON [] [] [] [] [] [] [] [] GFX_VI GFX_VI GFX_VI GFX_VI GFX_VI GFX_VI GFX_VI0 +.0V_VTT GFX_VR_EN PR KRF-GP 00-- change PR from.9k to.k by power P09 PR KRF--GP P0VJN-GP P 0KRF-L-GP _P 0P0VKX-GP PR9 +PWR_R_PU_GFXORE PR _VENE PR0 009/0/ P PR0 PR0 PR0 GN I PR0 PR0 PR0 PR09 PG9 PR0 +.0V_VTT P0 0U0VKX-GP +V_LW _OMP 0R00-P--GP PR 0KRJ--GP +.V_LW PR0 PR PR PR KRF--GP 0R00-P--GP 0R00-P--GP 0R00-P--GP 0R00-P--GP 0R00-P--GP 0R00-P--GP 0KRJ--GP 0R00-P--GP _PWRG _FRTN _F _OMP _ILIM PR 009/0/0 _RMP_ GN I +PU_GFXORE 0KRF-GP KRF-GP _GFX_VR_EN GN I PR 0KRJ--GP 9K09RF-GP 0KRF--GP _IREF _RPM _RT _VI _VI _VI _VI _VI _VI _VI0 PR 0RJ--GP PU0 PR KRF--GP P 000P00VKX-GP PWRG IMON LKEN# FRTN F OMP GPU ILIM PMNRG-GP 0KRF-L-GP EN VI0 0 VI 9 VI VI VI VI VI IREF RPM RT RMP LLINE REF F OMP 0 _RMP _LLINE _REF _F _OMP PR9 P 0P0VKX-GP V T RVH W PV 0 9 RVL PGN GN GN P9 KP0VKX-GP -0 _V _T PR _RVH _W _RVL GN I PR0 0RJ--GP PR 0KRF-GP PR0 U0VKX-GP NT-0K--GP P0 GN I RJ-L-GP _T_ U0VKX-GP P0 _RVL PR _OMP_ P0 UVKX--GP +V_LW KRF-GP PR 0KRF-GP -0 PU0 IP-T-GP _RVH PU0 IR0P-T-GE-GP +PWR_R_PU_GFXORE 009/0/0 _W_L 0P0VKX-GP RJ--GP _W_GN P0 0UVKX-GP PR P PG P0 0UVKX-GP GP-LOE-PWR--GP P0 0UVKX-GP PL0 IN-UH--GP PG P0 0UVKX-GP GP-LOE-PWR--GP UM Thermal esign urrent = Max. urrent =.<OP<. +PU_GFXORE PT0 E0UVM-L-GP PT0 E0UVM-L-GP P 0UVKX-GP P U0VKX-GP 00RF-L-GP-U GP-LOE-PWR--GP PR 0R00-P--GP PR 0R00-P--GP PR 0R00-P--GP V_XG_ENE [] _XG_ENE [] PG0 _OMP P0 KP0VKX-GP PR GN 00RF-L-GP-U GP-LOE-PWR--GP GN I I/P cap: 0U V K0 XR/.0.L Inductor: 0.uH PM0T-RMN yntec R:.mohm Isat=rms.R0.0 O/P cap: 0U.V EEFX0ER 9mOhm rms PNONI/ 9.9.L0 H/: IP/ POWERPK-/mOhm/mOhm@.Vgs/.0.0 L/: ir0p/ POWERPK-/.9mOhm/.mohm@.Vgs/ st amsung PG Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. GN I GP-LOE-PWR--GP 009/0/0 P PU_GFXORE Winery M I ize ocument Number Rev ustom 00 Wednesday, January, 00 ate: heet of

54 I = VIEO lose PH RN0 RNKJ--GP +.V_RUN lose GPU RN09 RNKJ--GP +.V_RUN_GPU W 0/0 dded.dded LV LK/T Pull Hi I = Inverter H=> -igpu PH (UM) L=>0 -dgpu GPU (I) LV ONNETOR JE-ON0--GP-U L NP NP T: 0.F.00 N: +PWR_R_L [,] EI_ELET# +.V_EEPROM L_RIGHTNE LON_OUT_R L_TT_L L_LK_ON L_T_ON L_ET_G L_L_ET# VG_TXOUT- VG_TXOUT+ VG_TXOUT0- VG_TXOUT0+ VG_TXLK- VG_TXLK+ VG_TXOUT- VG_TXOUT+ [] L_T [0] L T [] L_LK [0] L LK E0 U0VKX-GP [0] L T [0] L LK +LV EI_ELET# +.V_RUN R0 RJ--GP R0 R L_L_ET# [] VG_TXOUT0- [] VG_TXOUT0+ [] VG_TXOUT- [] VG_TXOUT+ [] VG_TXOUT- [] VG_TXOUT+ [] VG_TXLK- [] VG_TXLK+ [] +.V_RUN [] LKLT_TL_E [] LKLT_TL_GPU [0] LKLT_TL_PH [] L_T [] L_LK UM/I LV LK/T select circuit -0 0 U0VKX-GP 00RJ--GP 00RJ--GP R0 00RJ--GP 0 GN +.V_RUN U V NPX-GP 0 GN L_RIGHTNE L_T_ON EI_ELET# +.V_RUN U V NPX-GP R0 0KRJ--GP T:.0.0H N:.0.E0J L_LK_ON LON_OUT [] L_TT [] L_T_ON L_LK_ON EI_ELET# P0VJN-GP T:.0.0H N:.0.E0J UM/I LV PWM select circuit R 0RJ--GP U 0 GN V NPX-GP H=> -igpu PH (UM) L=>0 -dgpu GPU (I) +.V_RUN P0VJN-GP L_RIGHTNE T:.0.0H N:.0.E0J LV side GPU_PWM_ELET# [] ENV_M [] HM_LTT_EN I = VIEO [] LV_EN_GPU [0] LV_EN_PH L POWER -- add mux U to select LV enable signal 00-- modify L power schematic remove 0 09 T--F-GP T:.000.X N:.T.0 GPU_ELET# : H=> -igpu PH (UM) L=>0 -dgpu GPU (I) ENV_ U 0 GN +PWR_R_L V NPX-GP INVERTER POWER 0 KP0VKX-GP R09 0RJ--GP R 9K9RF-L-GP +.V_RUN ENV_M ENV T:.0.0H N:.0.E0J +LV T: N: F0 POLYW-V--GP 0 UVKX-GP +LV U0 OUT GN EN GTU-GP 0 UVKX-GP T:.0.0F N: GPU_ELET# [,,] +PWR_R 0 0UVKX-GP IN# IN# -0- pop E0 for EMI E0 UVZY-GP 0 U0VKX-GP +.V_RUN 0 U0VKX-GP -0 L_RIGHTNE LON_OUT_R L_TT E0 P0VJN-GP E0 P0VJN-GP R0 0KRJ--GP For EMI request st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. L/Inverter onnector ize ocument Number Rev ustom Winery M I ate: Wednesday, January, 00 heet of 00

55 I = VIEO [] M_RE [] M_GREEN [] M_LUE 00-- change R0, R0, R0 from 0R to R by EMI R0 M_RE_ RJ--GP R0 M_GREEN_ RJ--GP R0 M_LUE_ RJ--GP 00-- change L0, L0, L0 to 0R L0 0RJ-0-U-GP L0 0RJ-0-U-GP L0 0RJ-0-U-GP RT_R RT_G RT_ +V_RT_RUN +V_RUN 0 00W--F-GP K 0 0UVKX-GP +V_RT_RUN RT_R RT_G RT_ FTP change RT from to RT 9 0 VIEO---GP-U _T_ON JVG_H JVG_V _LK_ON JVG_H [] JVG_V [] RT_R RT_G RT_ Layout Note: *Pi-filter & 0 Ohm pull-down resistors should be as close as to RT ONN. * RG signal will hit Ohm first, then pi-filter, finally RT ONN. FTP0 FTP0 FTP09 FTP0 FTP0 FTP0 FTP0 FTP0 +V_RT_RUN _T_ON _LK_ON RT_R RT_G RT_ JVG_H JVG_V T: N: W 0 P0VJN-GP 0/ hange.hange RT ONN PN from to base on ME emm files. +.V_RUN_GPU +.V_RUN_GPU +.V_RUN_GPU lose PH +.V_RUN R0 0RF--GP R0 R0 0RF--GP 0RF--GP 0 V99--GP 0 P0VJN-GP lose GPU +.V_RUN_GPU 09 P0V-GP 0 V99--GP 0 P0V-GP P0V-GP 0 V99--GP 0 P0V-GP W 0/0 hange.hange RT LK/T ircuit +V_RT_RUN 0 P0V-GP 0 P0V-GP RN0 RNKJ--GP RN RNKJ--GP RN RNKJ--GP [0] GMH_T [0] GMH_LK [] RT_T_ [0] GMH_T [] RT_T_ [] RT_LK_ UM/I RT LK/T select circuit 0 GN V NPX-GP +.V_RUN U _T_ON EI_ELET# 9 P0VJN-GP +.V_RUN _T_ON _LK_ON RT side 0 0P0VJN-GP 00-- change 0 from p to 0p by EMI [,] EI_ELET# [] RT_LK_ [0] GMH_LK EI_ELET# H=> -igpu PH (UM) L=>0 -dgpu GPU (I) 0 GN V NPX-GP +.V_RUN U _LK_ON EI_ELET# _T_ON _LK_ON Q MN0LW--GP _T_ON _LK_ON <ore esign> RT onnector Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev Winery M I ate: Wednesday, January, 00 heet of 00

56 (lank) st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. (Reserve) ize ocument Number Rev ustom Winery M I ate: Wednesday, January, 00 heet of 00

57 (lank) st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. HMI onnector ize ocument Number Rev ustom 00 Winery M I Wednesday, January, 00 ate: heet of

58 I = Thermal FTP0 EM0_FN_TH_ Fan onnector FTP0 EM0_FN_RIVE FN [9] EM0_FN_TH_ EM0_FN_TH_ [9] EM0_FN_RIVE *Layout* mil EM0_FN_RIVE K 0 UVMX-GP FTP0 0 MK00L--F-GP FOX-ON--GP-U T: N: 0.F0.00 st amsung FN Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev Winery M I ate: Wednesday, January, 00 heet of 00

59 [] T_ITXN0_HRXN0 [] T_IRXN0_HTXN0_ I = T T H onnector T_IRXN0_HTXN0 9 0UVKX-GP +.V_RUN +V_RUN P P P P P0 P P H P P P P P9 P P P KT-TP+P--GP-U T:.000. N: T_IRXP0_HTXP0 +.V_RUN +V_RUN FF_INT lose to ONN V power pin +V_RUN 9 0UVKX-GP T_ITXP0_HRXP0 [] T_IRXP0_HTXP0_ [] FF_INT [0] lose to ONN.V power pin +.V_RUN T H Interface comment ****************************** :GN :RX+ :RX- :GN :TX- :TX+ :GN ****************************** P V P V P V P:GN P:GN / ell etected Pin P:GN P V P V P V P0--- GN P:ell: FF_INT for supported H P:GN P V P V P V ****************************** 90 0UVMX-GP 90 U0VKX-GP 90 0UVMX-GP 90 U0VKX-GP I = T O onnector O [] T_ITXP_ORXP [] T_ITXN_ORXN [] T_IRXN_OTXN_ [] T_IRXP_OTXP_ 9 9 T_RX- and T_RX+ Trace Length match within 0 mil 0UVKX-GP 0UVKX-GP +V_RUN 9 0UVMX-GP T_IRXN_OTXN T_IRXP_OTXP 90 U0VKX-GP P P P P P P NP NP GN + - GN - + GN P +V +V M GN GN GN GN NP NP KT-TP+P--GP-U st amsung T:.00. N:.00. Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. H/O onnector ize ocument Number Rev Winery M I ate: Wednesday, January, 00 heet 9 of 00

60 I = UIO I = UIO peaker onnector U_PK_L- [0] U_PK_L- U_PK_L+ [0] U_PK_L+ E00 MLVG000NV0-GP E00 MLVG000NV0-GP R00 0R00-P--GP R00 0R00-P--GP FTP00 FTP00 U_PK_L-_ U_PK_L+_ U_PK_L-_ U_PK_L+_ check cable pin define T: 0.F09.00 N: 0.F.00 FTP00 PK MLX-ON--GP-U MI IN [0] U_VREFOUT_ [0] U_EXT_MI_L [0] U_EXT_MI_R 0 UVKX-GP 0 UVKX-GP -0 R00 KRJ--GP R00 KRJ--GP U_VREFOUT_ 00 UVKX-GP [0] EXT_MI_J# MI_IN_L_ L00 LM0N-GP MI_IN_R_ L00 LM0N-GP 00ohm 00MHz 00m 0.ohm EXT_MI_J# MI_IN_L_ MI_IN_R_ E00 00P0VJN-GP E00 00P0VJN-GP T:.0.0 N: LIN UIO-JK-GP -0- pop E00 and E00 for EMI FTP009 FTP00 FTP0 FTP09 EXT_MI_J# GN MI_IN_L_ MI_IN_R_ elete udio e-pop ircuit 009/0/ I = UIO Head Phone [0] U_HP_J# [0] U_HP_JK_L [0] U_HP_JK_R 009/0/0 U_HP_J# U_HP_JK_L U_HP_JK_R L00 L00 00ohm 00MHz 00m 0.ohm LM0N-GP LM0N-GP U_HP_JK_L_ U_HP_JK_R_ T:.0.0 N: LOUT UIO-JK-GP P0VJN-GP-U P0VJN-GP-U E00 0UVKX-GP E00 0UVKX-GP -0- change E00,E00 from 0.U to 0.0U FTP0 FTP0 FTP0 FTP0 U_HP_J# GN U_HP_JK_L_ U_HP_JK_R_ dded HP circuit 009/0/ st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PEKER/MI/UIO JK ize ocument Number Rev Winery M I ate: Wednesday, January, 00 heet 0 of 00

61 (lank) st amsung (Reserve) Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev ustom Winery M I ate: Wednesday, January, 00 heet of 00

62 I = Flash.ROM I = RTT PI FLH ROM (M bits) for K K_PWR RN0 RN00KJ--GP E_PI_# E_PI_HOL# K_PWR RT onnector +.V_RT_LO U0VKX-GP UVKX-GP UVKX-GP U0 K_PWR +RT_ELL 0 +.V_RT_LO RT_PWR R change RT from to RT_V [] E_PI_# [] E_PI_I [] E_PI_WP#_R R0 R0 0RJ--GP 0RJ--GP E_PI_# PI_O E_PI_WP# # O WP# GN V HOL# K I E_PI_HOL# PI_IO E_PI_LK [] PI_IO [] 0 TW--GP KRJ--GP U0VKX-GP st.t. nd.t. Width=0mils TF0-H-T-GP st.0.00 nd.0.0 E0 P0VN-GP FTP0 st nd 0.F0.00 +RT_V PI FLH ROM (M bits) for PH +.V_RUN RN0 RNKJ--GP PH_PI_WP# PH_PI_HOL_0# +.V_RUN +.V_RUN R0 00KRJ--GP RT FTP0 FOX-ON--GP E0 P0VN-GP E0 P0VN-GP 0 UVKX-GP 0 U0VKX-GP -0- change R0 from ohm to 0 ohm R0 KRJ--GP U0 +.V_RUN [] PH_PI_0# [] PH_PI_I R0 0RJ--GP E0 P0VN-GP PH_PI_I_R PH_PI_WP# # O WP# GN V HOL# K I TF-U-GP st..00 nd..0 PH_PI_HOL_0# E0 E0 P0VN-GP P0VN-GP PH_PI_LK [] PH_PI_O [] st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. EEPROM/RT onnector ize ocument Number Rev Winery M I ate: Wednesday, January, 00 heet of 00

63 I = U U & ET Power W +V_LW U0 U_O#0_ [,] +V_U -0. pop and change TR0 to 90 ohm for EMI; R0, R0 [,] U_PWR_EN# 0 U0VKX-GP at least 0 mil -0- change 0 to U for EMI GN IN EN# EN# O# OUT OUT O# TP0-GP T:.00. N:.00.0 at least 0 mil R0 00KRJ--GP 0 U0VKX-GP -0- pop R0 for EMI 0 U0VKX-GP T0 T00UVMLGP [] U_PN0 T:.000. N:.00.0 LWHN900QLGP-U TR0 U_P0- U_P0+ U_P0- +V_U U [] U_PP0 U_P0+ KT-U--GP-U remove R0, R0 for no co-lay after X Remove E diode, confirmed with EMI T:.0.00 N:.0. FTP FTP FTP FTP0 U_P0- U_P0+ +V_U GN I = ET 00 ET Power [] U_PN R0 0R00-P--GP U_P- hare one power W with U port [] U_PP R0 0R00-P--GP U_P remove TR0 for no co-lay after X Remove E diode, confirmed with EMI +V_U ET VU +.V_RUN +.V_RUN R R KRF-GP KRF-GP R R 0RJ--GP 0RJ--GP 0 +.V_RUN U0VKX-GP U0VKX-GP 9 0U0VKX-GP RN0 0RPR-P M M ET_ITX_RX_PU_ ET_ITX_RX_NU_ R0 0R00-P--GP R0 0R00-P--GP ET_ITX_RX_PU ET_ITX_RX_NU ET_ITX_RX_PU ET_ITX_RX_NU ET_IRX_TX_PU ET_IRX_TX_NU U_P+ U_P- FTP0 FTP09 FTP0 0 9 T:.0.F N: V_U U_P- U_P+ GN GN GN GN GN GN GN GN KT-U-ET--GP FTP0 [] [] ET_ITX_RX_P ET_ITX_RX_N ET_IRX_TX_PU_L 0U0VKX-GP ET_IRX_TX_NU_L 0U0VKX-GP P LOE TO ET +.V_RUN 09 0U0VKX-GP ET_ITX_RX_P_R ET_ITX_RX_N_R 0 0U0VKX-GP ET_IRX_TX_P_L ET_IRX_TX_P R0 0RJ--GP ET_IRX_TX_N ET_IRX_TX_N_L R 0RJ--GP RN R U0_REPETER_EN 0RJ--GP U0 9 V V V V RX_0P RX_0N RX_P RX_N 0 EN TX_0P TX_0N TX_P TX_N GN GN GN GN GN 9 GN NLVPRTJR-GP ET_ITX_RX_PU_L R 0RJ--GP ET_ITX_RX_NU_L R9 0RJ--GP ET_IRX_TX_P L ET_IRX_TX_N L P LOE TO ET ET_ITX_RX_PU_R ET_ITX_RX_PU_ 0U0VKX-GP ET_ITX_RX_NU_R ET_ITX_RX_NU_ 0U0VKX-GP ET_IRX_TX_P_ [] 0UVKX-GP ET_IRX_TX_N_ [] 0UVKX-GP ET_IRX_TX_PU_L ET_IRX_TX_NU_L R 0R00-P--GP R 0R00-P--GP ET_IRX_TX_PU ET_IRX_TX_NU remove TR0, TR0 for no co-lay after X RN0 0RPR-P RN st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. U/ET Port ize ocument Number Rev ustom 00 Winery M I Wednesday, January, 00 ate: heet of

64 I = Wireless Mini ard onnector(0.a/b/g/n) +.V_RUN +.V_RUN WLN NP +V_LW 0 UVKX-GP +.V_RUN 0 U0VKX-GP [] WLN_T [] T_T [] MINI_LKREQ# [] LK_PIE_MINI# [] LK_PIE_MINI UVMX-GP +.V_RUN 0 UVKX-GP WLN_T 0 0UVMX-GP +.V_RUN 0 U0VKX-GP E0 0P0VKX-GP [] E_RX [] E_TX R0 0RJ--GP R0 0RJ--GP [] PIE_IRXN_MTXN [] PIE_IRXP_MTXP E_RX_R E_TX_R [] PIE_ITXN_MRXN [] PIE_ITXP_MRXP +.V_RUN R0 +V_LW +V_MINI_EUG 0RJ-0-U-GP NP PLT_RT# PH_MLK PH_MT U_P- U_P+ WIFI_RF_EN [] PLT_RT# [9,,,,,0,,0] +.V_RUN PH_MLK [,,9,,0,] PH_MT [,,9,,0,] LE_WLN_WIMX_OUT# [,] U_P- U_P+ R0 0R00-P--GP R0 0R00-P--GP U_PN [] U_PP [] KT-MINIP--GP T:.00. N: 0.F remove L0 for no co-lay after X FTP0 FTP0 E_RX E_TX V_RUN T: N:.00. ON OFF W NP NP W-LIE-GP TP0 TP-GP R0 WIRELE_ON#/OFF_R 0RJ--GP R0 KRJ--GP 0 UVKX-GP WIRELE_ON#/OFF [] st amsung TP0 TP-GP WIRELE_ON#/OFF_R Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. MINIR(WLN)/ITP ONN ize ocument Number Rev Winery M I ate: Wednesday, January, 00 heet of 00

65 (lank) st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. WWN onnector ize ocument Number Rev Winery M I ate: Wednesday, January, 00 heet of 00

66 I = LE PWR TN LE For LE & apacity board: [] PWR_TN_LE# PWR_TN_LE# R PWR_TN_LE_R# 0KRJ-L-GP PWR_TN_LE_R# [] LE Type olor Power rail RLK LE TTERY LE mber(multi-color) LW [] R_LOK_LE# R_LOK_LE# R0 RL_LE_R# 0KRJ-L-GP RL_LE_R# [] RL LE P LE White White LW LW P LE NUM LE White LW [] P_LOK_LE# P_LOK_LE# R P_LE_R# 0KRJ-L-GP P_LE_R# [] PWR TN LE T T LE T T LE WLN/WWN T LE White White White White LW RUN RUN RUN NUM LE [] NUM_LOK_LE# luetooth LE NUM_LOK_LE# R NUM_LE_R# 0KRJ-L-GP NUM_LE_R# [] [] T_TIVE_K# T_TIVE_K# R LE_T_T_K_R# 0KRJ-L-GP LE_T_T_K_R# [] WWN LE -0 [,] LE_WWN_OUT# WLN WIMX_LE [,] LE_WLN_WIMX_OUT# WLN_WIMX_LE_R# [] R 0KRJ-L-GP For LE&apacity board: LE Location from left to right POWER TTERY +V_LW LE0 [] TT_ORNGE_LE [] TT_WHITE_LE Orange Q0 R0 T_O_LE T_O_LE_R R E 0R00-P--GP R PTEU--GP T:.00.HK N:.00.K White Q09 R T_W_LE T_W_LE_R R E 0R00-P--GP R PTEU--GP T:.00.HK N:.00.K R 0R00-P--GP R9 0R00-P--GP TT_LE_ORNGE TT_LE_WHITE R TT_LE_ORNGE TT_LE_ORNGE_R 0RJ--GP TT_LE_WHITE PWR_LE R TT_LE_WHITE_R 0RJ--GP E09 U0VKX-GP R0 PWR_LE_R 0RJ--GP E0 U0VKX-GP E0 U0VKX-GP LE-OW--GP -0 LE0 K LE-Y--GP TTERY Pin(+) and Pin(-)= orange Pin(+) and Pin(-)= white T:.00.G0 N:.0.K0 RETH POWER LE white T:.000.J0 N:.0.R0 [] PWRLE# R 0KRJ-L-GP POWER_LE_R# white Q0 R R +V_LW E R9 POWER_LE_L PWR_LE Remove H LE TE--F-GP T:.00.K N: -0 0R00-P--GP [] T_LE# H LE R 0KRJ-L-GP T_T_# white Q0 R R TE--F-GP T:.00.K N: +V_RUN E H_LE R 0RJ--GP T_T_LE T_T_LE [] For LE & apacity board st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. LE ize ocument Number Rev 00 Winery M I Wednesday, January, 00 ate: heet of

67 (lank) st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. (Reserve) ize ocument Number Rev ustom Winery M I ate: Wednesday, January, 00 heet of 00

68 I = K I = Touch.Pad Internal Keyoard onnector TouchPad onnector K K_ET# FTP K_ET# [] +V_RUN +V_RUN E-ON0--GP T: 0.K0.00 N: 0.K09.00 KROW KROW KROW KROW KROW KROW KROW KROW0 KOL KOL KOL KOL KOL KOL KOL KOL KOL0 KOL KOL KOL KOL KOL KOL9 KOL KOL0 FTP FTP FTP9 FTP FTP FTP0 FTP FTP FTP FTP FTP FTP FTP9 FTP FTP FTP0 FTP FTP FTP FTP FTP FTP FTP9 FTP FTP0 KROW[0..] [] KOL[0..] [] [] TPLK [] TPT 0 P0VJN-GP FTP FTP FTP +V_RUN TPLK TPT 0 P0VJN-GP 0 U0VKX-GP +V_RUN TPLK TPT FTP E0 UVZY-GP E0 UVZY-GP TP E-ON-0-GP-U T: 0.K00.00 N: 0.K0.00 K acklight ONN +V_RUN KL [] K_L_ET# R KRJ--GP N_P K_L_ET# K_L_TRL# FTP FTP FTP FTP +V_RUN N_P K_L_ET# K_L_TRL# [] K_L_TRL Q0 G E-ON-0-GP-U T: 0.K00.00 N: 0.K0.00 +V_RUN +V_RUN R0 00KRJ--GP O0-GP T:.00. N: change hange Q0 to.00. U0VKX-GP For EMI RN0 RN0KJ--GP E0 UVZY-GP +V_RUN E0 UVZY-GP N_P K_L_ET# E0 UVZY-GP E0 UVZY-GP K_L_TRL# E0 UVZY-GP Place near ON 9 U0VKX-GP st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Keyboard/Touch Pad ize ocument Number Rev ustom Winery M I ate: Wednesday, January, 00 heet of 00

69 I = User.Interface Hall ensor onnector +.V_LW R90 009/0/ +.V_LW 90 U0VKX-GP [] LI_LOE# R90 00KRJ--GP LI_LOE# LI_LOE#_ R90 0RJ--GP 90 0U0VKX-GP HLL V OUTPUT EM--T0-GP T:.0.0 N:.09. st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Hall sensor ize ocument Number Rev ustom Winery M I ate: Wednesday, January, 00 heet 9 of 00

70 I = EUG PORT GOLEN FINGER FOR EUG OR [9,,,,,,,0] PLT_RT# [,,] LP_L0 [,,] LP_L [,,] LP_L G00 [,,] LP_L [,,] PLT_RT#_GP LP_LFRME# GP-OPEN [] PLK_FWH -0 T and add G00 +.V_RUN T 9 0 MLX-ON0--GP st amsung ebug port Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev ustom Winery M I ate: Wednesday, January, 00 heet 0 of 00

71 (lank) st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. (Reserve) ize ocument Number Rev ustom Winery M I ate: Wednesday, January, 00 heet of 00

72 (lank) st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. raidwood ize ocument Number Rev ustom Winery M I ate: Wednesday, January, 00 heet of 00

73 I = User.Interface For EMI amera onnector U_PP [] amera Power +.V_RUN +.V_MER R0 0RJ-0-U-GP E0 UVKX-GP 0 UVKX-GP MER 9 0 E-ON--GP-U U_MI_IN0_R U_MI_LK_G FTP0 +.V_MER MER_U+ MER_U- R00 RJ--GP U_MI_IN0 [0] U_MI_LK_G [0] L0 LWHN900QLGP-U T:.00.0G N: U_PN [] T: 0.F09.00 N: 0.F.00 FTP0 FTP0 FTP0 FTP0 FTP0 U_MI_LK_G U_MI_IN0_R +.V_MER MER_U- MER_U+ MLVG000NV0-GP E0 MLVG000NV0-GP E0-0- pop L0 for EMI remove R0, R0 for no co-lay after X For E I = User.Interface luetooth cable conn. LUETOOTH_ET# T NP T_T [] U_PP [] U_PN [] T_T [] LUETOOTH_EN [] WLN_T ssign T_ET# GPIO 009/0/09 R0 00KRJ--GP E0 0P0VKX-GP U_PP U_PN T_T LUETOOTH_EN WLN_T R0 0KRJ--GP FTP0 FTP0 FTP0 FTP0 FTP0 FTP0 FTP0 FTP0 LUETOOTH_ET# WLN_T LUETOOTH_EN T_LE T_T +.V_RUN U_PP U_PN WLN_T LUETOOTH_EN T_LE 9 E-ONN-GP 0 NP T: 0.F00.0 N: 0.F09.0 U_PP U_PN FTP09 +.V_RUN 0 U0VKX-GP pin define check T LE control signal 009/0/ lose to T +V_RUN +.V_RUN [] T_TIVE_K# Remove R0 009/0/09 R09 00KRJ--GP T_TIVE_K# Q0 MMT90--F-GP T_LE T:.090.H N:.090.L0 0 UVKX-GP 0 U0VKX-GP - st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. amera ONN ize ocument Number Rev Winery M I ate: Wednesday, January, 00 heet of 00

74 I = VIEO UM/I LV signal select circuit U +.V_RUN -0 modify GPU EL circuit [] VG_LV_T [] VG_LV_T# [] VG_LV_T [] VG_LV_T# [] VG_LV_T0 [] VG_LV_T0# [] VG_LV_LK [] VG_LV_LK# [0] MH_LV_T [0] MH_LV_T# [0] MH_LV_T [0] MH_LV_T# [0] MH_LV_T0 [0] MH_LV_T0# [0] MH_LV_LK [0] MH_LV_LK# GPU_V_EL# 9 H=>TM -igpu PH (UM) L=>TM -dgpu GPU (I) 9 TM+ TM- TM+ TM+ TM- TM- TM+ TM0+ TM- TM0- TM0+ TMLK+ TM0- TMLK- TMLK+ TMLK- TM+ TM- TM+ TM- TM0+ TM0- TMLK+ TMLK- V V V V V 0 V 0 V 0 V EL GN U0VKX-GP VG_TXOUT+ [] VG_TXOUT- [] VG_TXOUT+ [] VG_TXOUT- [] VG_TXOUT0+ [] VG_TXOUT0- [] VG_TXLK+ [] VG_TXLK- [] 0 U0VKX-GP +V_RT_RUN 0 U0VKX-GP 0 U0VKX-GP TVRUR-GP.0.0G +.V_RUN UM/I RT Hsync/Vsync select circuit Hsync & Vsync level shift GPU_ELET GPU_ELET# +V_RT_RUN UM/I RT signal select circuit E0 UVZY-GP +.V_RUN GPU_ELET -0 modify GPU EL circuit R 0KRF-L-GP +.V_RUN [0] GMH_VYN [] VG_VYN GPU_ELET# H=> -igpu PH (UM) L=> -dgpu GPU (I) +V_RT_RUN GPU_ELET GPU_ELET# U0 HTPWR-GP VYN_ VYN_ U0 HTPWR-GP RN VYN_ HYN_ +V_RT_RUN 0 U0 HTPWR-GP RNJ--GP-U JVG_V [] JVG_H [] 0 U0VKX-GP +V_RT_RUN U GPU_ELET# V [] VG_LUE I0 [0] MH_LUE I [] VG_GREEN I0 [0] MH_GREEN I [] VG_RE I0 [0] MH_RE 0 I I0 I GN Y Y Y 9 Y OE# PIQE-GP N =.0.0 M_LUE [] M_GREEN [] M_RE [] H=>I -igpu PH (UM) L=>I0 -dgpu GPU (I) [,,] Q0 MN0LW--GP GPU_ELET# [0] GMH_HYN 9 HYN_ R +V_RT_RUN 0KRF-L-GP [] VG_HYN HYN_ GPU_V_EL# U0 HTPWR-GP st amsung Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PX with- ize ocument Number Rev ustom Winery M I ate: Wednesday, January, 00 heet of 00