Size Document Number Rev A3. Date: Monday, November 15,

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1 ize ocument Number Rev ate: Monday, November, 00 heet of 0

2 [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP FI_TXN0 FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXP0 FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP [] FI_FYN0 [] FI_FYN [] FI_INT [] FI_LYN0 [] FI_LYN ep_omp andy ridge Processor (MI,PE,FI) INT_eP_HP_Q U MI_RX#[0] MI_RX#[] MI_RX#[] MI_RX#[] MI_RX[0] MI_RX[] MI_RX[] MI_RX[] MI_TX#[0] E MI_TX#[] F MI_TX#[] MI_TX#[] MI_TX[0] MI_TX[] F0 MI_TX[] MI_TX[] FI0_TX#[0] H FI0_TX#[] E FI0_TX#[] F FI0_TX#[] FI_TX#[0] 0 FI_TX#[] FI_TX#[] E FI_TX#[] FI0_TX[0] FI0_TX[] E0 FI0_TX[] FI0_TX[] 0 FI_TX[0] FI_TX[] FI_TX[] F FI_TX[] J FI0_FYN J FI_FYN H0 FI_INT J FI0_LYN H FI_LYN ep_ompio ep_iompo ep_hp ep_ux ep_ux# ep_tx[0] F ep_tx[] ep_tx[] ep_tx[] ep_tx#[0] E ep_tx#[] ep_tx#[] F ep_tx#[] MI Intel(R) FI ep PI EXPRE* - RPHI andy ridge_rp_rev0p rpga--socket ^0000 I OKET RP P(P.0,M/H.0) ep_omp connect to PIN W:mils/:mils/L: 00mils. ep_omp connect to PIN W:mils/:mils/L: 00mils. PE_IOMPI J PE_IOMPO J PE_ROMPO H PE_RX#[0] K PE_RX#[] M PE_RX#[] L PE_RX#[] J PE_RX#[] J PE_RX#[] H PE_RX#[] H PE_RX#[] PE_RX#[] 0 PE_RX#[] F PE_RX#[0] E PE_RX#[] E PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX[0] J PE_RX[] L PE_RX[] K PE_RX[] H PE_RX[] H PE_RX[] PE_RX[] PE_RX[] F PE_RX[] F0 PE_RX[] E PE_RX[0] E PE_RX[] F PE_RX[] PE_RX[] E PE_RX[] PE_RX[] PE_TX#[0] M PE_TX#[] M PE_TX#[] M PE_TX#[] L PE_TX#[] L PE_TX#[] K PE_TX#[] K PE_TX#[] J0 PE_TX#[] J PE_TX#[] H PE_TX#[0] PE_TX#[] E PE_TX#[] F PE_TX#[] PE_TX#[] F PE_TX#[] E PE_TX[0] M PE_TX[] M PE_TX[] M0 PE_TX[] L PE_TX[] L PE_TX[] K0 PE_TX[] K PE_TX[] J PE_TX[] J PE_TX[] H PE_TX[0] PE_TX[] E PE_TX[] F PE_TX[] PE_TX[] E PE_TX[] PE_RX#0 PE_RX# PE_RX# PE_RX# PE_RX# PE_RX# PE_RX# PE_RX# PE_RX# PE_RX# PE_RX#0 PE_RX# PE_RX# PE_RX# PE_RX# PE_RX# PE_RX0 PE_RX PE_RX PE_RX PE_RX PE_RX PE_RX PE_RX PE_RX PE_RX PE_RX0 PE_RX PE_RX PE_RX PE_RX PE_RX PE_OMP _PE_TX#0 _PE_TX# _PE_TX# _PE_TX# _PE_TX# _PE_TX# _PE_TX# _PE_TX# _PE_TX# _PE_TX# _PE_TX#0 _PE_TX# _PE_TX# _PE_TX# _PE_TX# _PE_TX# _PE_TX0 _PE_TX _PE_TX _PE_TX _PE_TX _PE_TX _PE_TX _PE_TX _PE_TX _PE_TX _PE_TX0 _PE_TX _PE_TX _PE_TX _PE_TX _PE_TX PE_OMP connect to PIN H&J W:mils/:mils/L: 00mils. PE_OMP connect to PIN J W:mils/:mils/L: 00mils. [,,,,,] PE_RX#[0..] [] PE_RX[0..] [] PU REET# PLTRT# M_RMPWROK Processor Input. [] [] [] H_N_IV# N_IV# N. at N E # 0.v / del for update. E_PEI [,] H_PROHOT# [,] PM_THRMTRIP# V PM_YN / reserved for "boot hang " issue / change to 0 ohm [] H_PWROO N V / --> modify *LV0W / del for update. PM_RM_PWR_PU Placement close to E. R / short R _ KTO# TP_TERR# H_PEI./F_ H_PROHOT#_R PM_THRMTRIP#_R H_PWROO_R PU_PLTRT#_R PM_RM_PWR_ NOUT R *LV0W 0/ change PM_RM_PWR [] / add for P update R 0_ R 0_.0V_VTT R0 *_ U NOUT PU_PLTRT# R0 *_ IN V 0 / --> modify R.K/F_ R *0K_ R *0_ R 0_ 0 P/0V_ *0.U/0V_ R TP 0K_ U N V IN V PM_RM_PWR_ R0 *K/F_ TP R *0_/ PM_YN_R short00 00 *0.U/0V_ / --> modify.v_pu MIN_ON [,] 0/F_ PM_RM_PWR_R andy ridge Processor (LK,MI,JT) / --> modify _ N L N L N M P U R Q N00 / add TERR# PEI PROHOT# THERMTRIP# PM_RM_PWR_R V M_RMPWROK R 0/F_ *0.U/0V_ R N_IV# KTO# PM_YN UNOREPWROO REET# / --> modify MI THERML PWR MNEMENT andy ridge_rp_rev0p rpga--socket ^0000 I OKET RP P(P.0,M/H.0) R 00/F_ LOK R MI JT & PM LK LK# PLL_REF_LK PLL_REF_LK# M_RMRT# R M_ROMP[0] K M_ROMP[] M_ROMP[] PRY# P PREQ# P TK TM TRT# TI TO R# PM#[0] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[].VU [,] R_RMRT# [] RMRT_NTRL_PH / for H/W modify. LK_PLL_LKP_R LK_PLL_LKN_R PU_RMRT# M_ROMP_0 R M_ROMP_ R M_ROMP_ R XP_PRY# XP_PREQ# XP_RT# LK_PU_LKP [] LK_PU_LKN [] M_ROMP[0] W:0mils/:0mils/L: 00mils, M_ROMP[] W:0mils/:0mils/L: 00mils, M_ROMP[] W:mils/:0mils/L: 00mils, R XP_TLK R XP_TM P0 XP_TRT# R XP_TI_R P XP_TO L T XP_PM0 R R0 T0 P XP_PM XP_PM XP_PM XP_PM R XP_PM T XP_PM R XP_PM PU_RMRT#_R TP TP 0/F_./F_ 00/F_ TP TP TP TP TP TP0 TP TP TP TP TP TP0 TP PU XP V XP_RT# [] R RM REET R R R K_ K_ *K_ R R *0_/ short00 / short 0.0U/0V_ PU_RMRT# R0.K/F_ [,,,,0,,,,,,,,,,,,,,,,] V [,,,,0,,,,,,,,] V [,0,].V_PU [,,,,,].0V_VTT *0_ Q N00 FI disable (I only stuff) R R R0 R R *0_ *0_ *0_ *K_ *K_ FI_INT FI_FYN0 FI_FYN FI_LYN0 FI_LYN FI_FYN can gang all these signals together and tie them with only one K resistor to N ( V0. h..). PE x disable (UM only remove) _PE_TX0 _PE_TX _PE_TX _PE_TX _PE_TX _PE_TX _PE_TX _PE_TX _PE_TX _PE_TX _PE_TX0 _PE_TX _PE_TX _PE_TX _PE_TX _PE_TX [] PE_TX[0..] [] PE_TX#[0..] U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ PE_TX0 PE_TX PE_TX PE_TX PE_TX _PE_TX#0 _PE_TX# _PE_TX# _PE_TX# _PE_TX# U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ PE_TX PE_TX PE_TX PE_TX PE_TX PE_TX0 _PE_TX# _PE_TX# _PE_TX# _PE_TX# _PE_TX# _PE_TX#0 0 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0 0.U/0V_ PE_TX _PE_TX# 0.U/0V_ 0.U/0V_ PE_TX _PE_TX# 0.U/0V_ 0.U/0V_ PE_TX _PE_TX# 0.U/0V_ 0.U/0V_ PE_TX _PE_TX# 0.U/0V_ 0.U/0V_ PE_TX _PE_TX# 0.U/0V_ 0.uF coupling aps for PIE EN// PE_TX#0 PE_TX# PE_TX# PE_TX# PE_TX# PE_TX# PE_TX# PE_TX# PE_TX# PE_TX# PE_TX#0 PE_TX# PE_TX# PE_TX# PE_TX# PE_TX# 0.uF coupling aps for PIE EN// Embedded isplay PLL lock LK_PLL_LKP_R LK_PLL_LKN_R LK_PLL_LKP_R LK_PLL_LKN_R I /UM N Ra RP Rb R Rc R Ra Rb Rc tuff 0_PR_0 tuff N / change Part reference. *0_ *0_ tuff N LK_PLL_LKP [] LK_PLL_LKN [] P & PE ompensation.0v_vtt.0v_vtt.0v_vtt R R0 INT_eP_HP_Q./F_ ep_omp ep_ompio and IOMPO signals should be shorted near balls and routed with typical impedance < mohms R 0K_./F_ PE_OMP PE_IOMPI and ROMPO signals should be routed within 00 mils typical impedance = mohms PE_IOMPO signals should be routed within 00 mils typical impedance =. mohms Processor pull-up (PU) H_PROHOT# XP_TO XP_TM XP_TI_R XP_PREQ# XP_TLK XP_TRT# R _ R _ R _ R _ R *_ R _ R _.0V_VTT ize ocument Number Rev ustom ate: Monday, November, 00 heet of 0

3 andy ridge Processor (R) U U [] M Q[:0] [] M #0 [] M # [] M # [] M # [] M R# [] M WE# M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q F0 F 0 F F K K K J J J J K M N0 N N M0 M N M K K H H J J J K J K H H L L P N L M M L P N J H L K L K J H E0 F0 V E F _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _[0] _[] _[] _# _R# _WE# R YTEM MEMORY _LK[0] _LK#[0] _KE[0] _LK[] _LK#[] _KE[] _LK[] _LK#[] _KE[] _LK[] _LK#[] _KE[] _#[0] _#[] _#[] _#[] _OT[0] _OT[] _OT[] _OT[] _Q#[0] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _M[0] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _M[0] _M[] _M[] _M[] _M[] _M[] V V0 W W0 K L H H H J M L M R M F K N L M R M 0 W W W V V W W V W V W F V V M QN0 M QN M QN M QN M QN M QN M QN M QN M QP0 M QP M QP M QP M QP M QP M QP M QP M 0 M M M M M M M M M M 0 M M M M M M LKP0 [] M LKN0 [] M KE0 [] M LKP [] M LKN [] M KE [] M #0 [] M # [] M OT0 [] M OT [] M QN[:0] [] M QP[:0] [] M [:0] [] [] M Q[:0] [] M #0 [] M # [] M # [] M # [] M R# [] M WE# M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q 0 F F F F J J K0 K J J0 K K M N N N M N M M M M R P N N N P P N T T P N R R R J T T H R J H T N R T T N R T R 0 _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _[0] _[] _[] _# _R# _WE# R YTEM MEMORY _LK[0] E _LK#[0] _KE[0] R _LK[] E _LK#[] _KE[] R0 _LK[] _LK#[] _KE[] T _LK[] _LK#[] _KE[] T0 _#[0] _#[] E _#[] _#[] E _OT[0] E _OT[] _OT[] _OT[] E _Q#[0] _Q#[] F _Q#[] K _Q#[] N _Q#[] N _Q#[] P _Q#[] K _Q#[] P _Q[0] _Q[] _Q[] J _Q[] M _Q[] N _Q[] P _Q[] K _Q[] P _M[0] _M[] T _M[] R _M[] T _M[] T _M[] T _M[] T _M[] R _M[] T _M[] R _M[0] _M[] R _M[] T _M[] 0 _M[] R _M[] R M QN0 M QN M QN M QN M QN M QN M QN M QN M QP0 M QP M QP M QP M QP M QP M QP M QP M 0 M M M M M M M M M M 0 M M M M M M LKP0 [] M LKN0 [] M KE0 [] M LKP [] M LKN [] M KE [] M #0 [] M # [] M OT0 [] M OT [] M QN[:0] [] M QP[:0] [] M [:0] [] andy ridge_rp_rev0p rpga--socket ^0000 I OKET RP P(P.0,M/H.0) andy ridge_rp_rev0p rpga--socket ^0000 I OKET RP P(P.0,M/H.0) ize ocument Number Rev ustom ate: Monday, November, 00 heet of 0

4 / all of these uf/.v capacitors are repleaced by 0uF/.V in OM U/.V_ 0 U/.V_ U/.V_ 0 U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ N: uf_ x ocket TOP cavity uf_ x0 ocket OT cavity uf_ x ocket TOP edge 0uF_ x / change 0U FP to 00. U/.V_ U/.V_ U/.V_ U/.V_ *U/.V_ U/.V_ 0 U/.V_ U/.V_ U/.V_ 0 *U/.V_ *U/.V_ U/.V_ U/.V_ andy ridge Processor (POWER) V_ORE *U/.V_ UF V V V V V 0 V V V V V0 F V F V F V F V F V F0 V F V F V F V F V0 V V V V V 0 V V V V V0 V V V V V 0 V V V V V0 V V V V V 0 V V V V V0 Y V Y V Y V Y V Y V Y0 V Y V Y V Y V Y V0 V V V V V V V V V V V0 V V V V V V V V V0 U V U V U V U V U V U0 V U V U V U V U V0 R V R V R V R V R V R0 V R V R V R V R V0 P V P V P V P V P V P0 V P V P V P V P V00 ORE UPPLY ENE LINE VI andy ridge_rp_rev0p rpga--socket ^0000 I OKET RP P(P.0,M/H.0) PE N R VIO H VIO H0 VIO 0 VIO 0 VIO Y0 VIO U0 VIO P0 VIO L0 VIO J VIO0 J VIO J VIO J VIO H VIO H VIO H VIO VIO VIO VIO F VIO0 F VIO F VIO F VIO E VIO E VIO E VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO VIO VIO VIO VILERT# J VILK J0 VIOUT J V_ENE J V_ENE J VIO_ENE 0 VIO_ENE 0 VIO0 J.0V_VTT_0 H_PU_VILRT# H_PU_VILK H_PU_VIT / Modify. / all of these uf/.v capacitors are repleaced by 0uF/.V in OM U/.V_ U/.V_ *U/.V_ N:. / modify 0 U/.V_ *U/.V_ VP_ENE U/.V_ U/.V_.0V_VTT.0V_VTT V_ORE V_ENE [] V_ENE [] VP_ENE [] Trace Route to Power I area. [,0,,,,,].VU [,0,].V_PU [,,,,,].0V_VTT [] V [,0] V_FX [,0] V_ORE.V N:. V_FX uf_ x ocket TOP cavity uf_ x ocket OT cavity /: add 0/ uf_ x ocket TOP cavity (no stuff) uf_ x ocket OT cavity (no stuff) 0uF_ x R U/.V_ *0_/ R 00_ TP 0 U/.V_ U/.V_ 0 *U/.V_ *U/.V_ *U/.V_ *U/.V_ U/.V_ 0 *U/.V_ U/.V_ R 00_ 0 U/.V_ *U/.V_ *U/.V_ 0 U/.V_ Ra H_PU_VILK H_PU_VIT.0V_VTT H_PU_VILRT#.0V_VTT.0V_VTT andy ridge Processor (RPHI POWER) uf_ x ocket TOP cavity uf_ x ocket OT cavity uf_ x ocket TOP edge uf_ x ocket OT edge 0uF_ x U/.V_ U/.V_ U/.V_ 0 U/.V_ U/.V_ U/.V_ 0U/.V_ U/.V_ N:. Ra R I tuff /UM N 0uF x, 0uF_ x, uf_ x ocket OT edge. / change 0U FP to 00. Layout note: need routing together and LERT need between LK and T. Place PU resistor close to PU U/.V_ 0 U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ *0_ / Modify. R 0/F_ Place PU resistor close to PU Place PU resistor close to VR R *./F_ Place PU resistor R close to VR *0/F_ / Modify. /: modify R _ R _ U T VX T VX T VX T0 VX T VX T VX R VX R VX R VX R0 VX0 R VX R VX P VX P VX P VX P0 VX P VX P VX N VX N VX0 N VX N0 VX N VX N VX M VX M VX M VX M0 VX M VX M VX0 L VX L VX L VX L0 VX L VX L VX K VX K VX K VX K0 VX0 K VX K VX J VX J VX J VX J0 VX J VX J VX H VX H VX0 H VX H0 VX H VX H VX VPLL VPLL VPLL U/.V_ 0U/V_ / Modify. RPHI.V RIL andy ridge_rp_rev0p rpga--socket ^0000 I OKET RP P(P.0,M/H.0) VI LK.0V_VTT ENE LINE RIL R -.V RIL VREF MI VR_VI_LK [] VI T VR_VI_T [] VI LERT VR_VI_LERT# [] VX_ENE K VX_ENE K M_VREF.VU L VQ F VQ F VQ F VQ VQ VQ VQ Y VQ Y VQ Y VQ0 U VQ U VQ U VQ P VQ P VQ P V M V M V L V J V J V J V H V H MIN / Modify. VR_REF_PU R 00K_ VU_ENE_R V_ENE H R / short R H_F_ F_ V_VI / delete JP R Q0 ON0 MIN.V_PU V_FX V_X_ENE [] V_X_ENE [] Note: VR_REF_PU should have 0 mil trace width N: R_VTTREF [,,] MIN [] V 0uF x, 0uF_ x ocket OT edge, 0uF_ x ocket OT cavity. / change 0U FP to 00. VU_ENE [] V_EL [].VU MIN_ON [,] /: modify / mount for black screen issue / modify.v_pu N: 0U/.V_ /: layout modify 0uF x, 0uF_ x ocket OT edge. 0U/.V_ / FP changed from 0U_.V_.0x.ER0m to 0U/.V_x.ER / change 0U FP to 00. *0P/0V_ R 00_ R 00_ *0_ Q N00 0U/.V_ 0U/.V_ 0U/.V_ R 0 0U/.V_ 0U/.V_ 0U/.V_X.ER 0U/.V_ *0_/ short00 0K_ 0U/.V_ *0U/.V_ /: dd for intel R R0 0_ 0K_ Q0 N00 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ / add for Intel. Placement close to PU. PU VQ ize ocument Number Rev ustom ate: Monday, November, 00 heet of 0

5 UH andy ridge Processor (N) UI andy ridge Processor (REERVE, F) UE T T T T T T T T T T0 T T T R R R R R R0 R R R P P P P P P P P P0 P P P N0 N N N N N N N0 N N M M M M M M M0 M M M M M L L L L L L L L L0 L L L K K0 K K K K K K K0 K K J V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V V0 V V V V V V V V V V00 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 J J J J J0 J J J J J H H H H0 H H H H H H H H H F F F F E E E E E E0 E E E E E 0 Y Y Y Y Y Y W W W W W W0 W W W W U U U U U U T T T T T T0 T T T T P P P P P P N N N N N N0 N N N N M L L0 L L L L L L L L L K K K K J J H H0 H H H H H H H0 H H H H H H H H H 0 F F F V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V00 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V F F E0 E E E E E E E0 E E E E E E E E E [] MR_VREF_Q0_M [] MR_VREF_Q_M [] H_VTTVI For PU debug. TP0 TP TP R *K_ R / short F0 F F F F F R *K_ *0_/ short00 K F[0] K F[] L F[] L F[] K F[] L F[] L0 F[] M F[] M F[] M0 F[] M F[0] M F[] N F[] N F[] N F[] M F[] K F[] N F[] J RV H RV J RV H RV J RV RV F RV F RV F RV0 RV RV RV E RV RV 0 RV RV 0 RV RV 0 RV0 RV 0 RV RV J0 RV RV RV J RV RV REERVE andy ridge_rp_rev0p rpga--socket ^0000 I OKET RP P(P.0,M/H.0) RV RV RV0 RV RV RV RV RV RV RV RV RV0 RV RV RV RV RV RV RV RV RV RV0 RV RV RV RV RV RV RV RV KEY L E K W T M J T J H R T T P R J K H N M T T R TP TP # N E0.v no function. For rp socket, RV pin should be left N. andy ridge_rp_rev0p rpga--socket ^0000 I OKET RP P(P.0,M/H.0) andy ridge_rp_rev0p rpga--socket ^0000 I OKET RP P(P.0,M/H.0) Processor trapping F (PE tatic Lane Reversal) Normal Operation The F signals have a default value of '' if not terminated on the board. 0 Lane Reversed (hh) TWH PE bus is Lane Reversed F R K_ F[:] (PIE Port ifurcation traps) : (efault) x - evice functions and disabled 0: x, x - evice function enabled ; function disabled 0: Reserved - (evice function disabled ; function enabled) 00: x,x,x - evice functions and enabled F (P Presence trap) F (PE efer Training) isable; No physical P attached to ep PE train immediately following xxreet de assertion Enable; n ext P device is connected to ep PE wait for IO training F F F F R R R R *K_ *K_ *K_ *K_ ize ocument Number Rev ustom ate: Monday, November, 00 heet of 0

6 [] [] U_PWR_K_R [] UK# Y_PWROK E_PWROK_R [] PM_RM_PWR [] RMRT# [] NWON# [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] XP_RT# E_PWROK.0V 0/ add / short [] U_PWR_K [] _PREENT MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP R R / short R R0 00./F_ MI_OMP 0/F_ MI_RI *0_/ short00 *0_ UK#_R XP_RT# R0 *0_/ Y_PWROK_R short00 R *0_ R 0_ E_PWROK_R R 0_ R R0 R U/0V_ / --> modify PWROK_R PM_RM_PWR RMRT# *0_/ U_PWR_K_R short00 *0_/ NWON#_R short00 *0 PREENT_R PM_TLOW# PM_RI# ougar Point (MI,FI,PM) U MI0RXN E0 MIRXN MIRXN 0 MIRXN E MI0RXP 0 MIRXP J MIRXP J0 MIRXP W MI0TXN W0 MITXN MITXN V MITXN Y MI0TXP Y0 MITXP Y MITXP U MITXP J H K P L L0 MI_ZOMP MI_IROMP Y_REET# Y_PWROK E0 PWRTN# (W) H0 PREENT / PIO (V) E0 TLOW# / PIO 0 MIRI UK# PWROK PWROK RMPWROK RMRT# RI# MI ystem Power Management FI (V) K UWRN#/UPWRNK/PIO0 FI_RXN0 J FI_RXN Y FI_RXN E FI_RXN H FI_RXN FI_RXN J FI_RXN 0 FI_RXN FI_RXP0 FI_RXP FI_RXP F FI_RXP FI_RXP E FI_RXP FI_RXP J0 FI_RXP H FI_INT FI_FYN0 FI_FYN FI_LYN0 FI_LYN WVRMEN PWROK WKE# LP_# LP_# LP_U# W V 0 V 0 E (V) LKRUN# / PIO N (V) U_TT# / PIO (V) ULK / PIO N (V) LP_# / PIO 0 LP_# H F 0 PMYNH P (V) LP_LN# / PIO K WVREN R 0_ PIE_WKE# LKRUN# PH_ULK_L R R0 0_ R0 0_ R0 R LP_LN# *0_ *0_ FI_TXN0 [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXP0 [] FI_TXP [] FI_TXP [] FI_TXP [] FI_TXP [] FI_TXP [] FI_TXP [] FI_TXP [] FI_INT [] FI_FYN0 [] FI_FYN [] FI_LYN0 [] FI_LYN [] R 0_ PWROK PM_YN [] RMRT# PIE_WKE# [,,] LKRUN# [] TP *0_/ short00 LP_ [] U# [] U# [] LP_# [] / remove in OM LP_U# [] /: modify / short TP PH_ULK [] [] PH_LV_LON [] PH_IP_ON [] PH_PT_PWM [] PH_EILK [] PH_EIT / change net name. [] PH_L_LK# [] PH_L_LK [] PH_L_TN0 [] PH_L_TN [] PH_L_TN [] PH_L_TP0 [] PH_L_TP [] PH_L_TP [] PH_L_LK# [] PH_L_LK [] PH_L_TN0 [] PH_L_TN [] PH_L_TN [] PH_L_TP0 [] PH_L_TP [] PH_L_TP [] PH_RT_ [] PH_RT_ [] PH_RT_R [] PH_LK [] PH_T *.P/0V_ *.P/0V_ *.P/0V_ PH_EILK PH_EIT TRL_LK TRL_T LV_I PH_L_LK# PH_L_LK PH_L_TN0 PH_L_TN PH_L_TN PH_L_TP0 PH_L_TP PH_L_TP PH_L_LK# PH_L_LK PH_L_TN0 PH_L_TN PH_L_TN PH_L_TP0 PH_L_TP PH_L_TP R0 0_ PH_RT_ R 0_ PH_RT_ R 0_ PH_RT_R R 0_ R 0_ PH_HYN_R PH_VYN_R PH_RT_ PH_RT_ PH_RT_R / EMI(near PH) TP R 0_ R 0 IREF R K/F_ ougar Point (LV,I) U J L_KLTEN M L_V_EN P L_KLTTL T0 L LK K L T T L_TRL_LK P L_TRL_T F LV_I F LV_V E LV_VREFH E LV_VREFL K LV_LK# K0 LV_LK N LV_T#0 M LV_T# K LV_T# J LV_T# N LV_T0 M LV_T K LV_T J LV_T F0 LV_LK# F LV_LK H LV_T#0 H LV_T# F LV_T# F LV_T# H LV_T0 H LV_T F LV_T F LV_T N RT_LUE P RT_REEN T RT_RE T RT LK M0 RT T M RT_HYN M RT_VYN T _IREF T RT_IRTN LV RT igital isplay Interface ougarpoint_rev_0p fcbga-intel-cougarpoint J0QMVY0T0 I TRL(P)OURPOINT QMVY TOP / VO_TVLKINN P VO_TVLKINP P VO_TLLN M VO_TLLP M0 VO_INTN P VO_INTP P0 VO_TRLLK P VO_TRLT M P_UXN T P_UXP T P_HP T0 P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P P_TRLT P P_UXN P P_UXP P P_HP T P_0N Y P_0P Y P_N Y P_P Y P_N P_P P_N P_P P_TRLLK M P_TRLT M P_UXN T P_UXP T P_HP H P_0N P_0P P_N F P_P E P_N F P_P E P_N J P_P P_HP_Q V P_LNE0_N V0 V V P_LNE0_P P_LNE_N P_LNE_P U U P_LNE_N P_LNE_P V P_LNE_N V P_LNE_P VO_LK [] VO_T [] INT. HMI PH Pull-high/low(L) PM_RI# PM_TLOW# PIE_WKE# LP_LN# U_PWR_K _PREENT_R LKRUN# XP_RT# RMRT# Y_PWROK V R0 0K_ R0 *.K_ R 0K_ R *0K_ R 0K_ R0 0K_ V R.K_ R 0K_ R *K_ R 0K_ R *00K_ /0 change from 0K to 00K / change to N INT LV & RT disable (I only remove) V [] PH_HYN [] PH_VYN R0 R P Res place close to PH ougarpoint_rev_0p fcbga-intel-cougarpoint J0QMVY0T0 I TRL(P)OURPOINT QMVY TOP / R / change net name. TRL_LK TRL_T LV_I PH_HYN_R PH_VYN_R / modify PH to Res routeing 0 ohm Impedance. Res to connector filter routeing.ohm Impedance. R0 R0 R00.K_.K_.K/F_ R0 _ R0 _ 0/F_ 0/F_ 0/F_ PH_RT_ PH_RT_ PH_RT_R INT HMI disable (I only remove) P_HP_Q P_LNE0_N P_LNE0_P P_LNE_N P_LNE_P P_LNE_N P_LNE_P P_LNE_N P_LNE_P INT HMI etect Function R *00K_ R0 0_ V Q *N00 R *00K_ IN_# [] IN_ [] IN_# [] IN_ [] IN_0# [] IN_0 [] IN_LK# [] IN_LK [] HMI_HP_ON [] ystem PWR_OK(L) Y_PWROK V_RT U *TH0FU R V / --> modify R0 0_ 0K_ E_PWROK WVREN *0.U/0V_ R 00K_ On ie W VR Enable High = Enable (efault) Low = isable ** IMVP_PWR [] / delete a short net in"e_pwrok" R *0K_ V VPU [,0,,,,,,] V [,,,,0,,,,,,,,,,,,,,,,] V [,,,,0,,,,,,,,] V [,,,,,0,] VPU [,0] V_W [,0,] V_RT PWROK FOR W /: modify *R00V-0 0 V_W *R00V-0 Q *PTEU VPU R *0K_ VPU R *0K_ Q *N00 PWROK *0.U/0V_ add cap to timing tune ize ocument Number Rev ustom ate: Monday, November, 00 heet of 0

7 V_RT VPU [] [] [] PKR Z_IN0 / delete net "Z_IN" [] PH_PI_LK [] PH_PI_0# [] U_MI# PH_PI_I [] PH_PI_O PH trap Table PKR PIO NT# / PIO NV_LE NV_LE RT_X RT_X RT_RT# RT_RT# M_INTRUER# PH_INVRMEN Z_LK Z_YN PKR Z_RT# Z_OUT PIO PH_JT_TK_R PH_JT_TM PH_JT_TI_R PH_JT_TO_R PH_PI_LK PH_PI_0# PH_PI_# PH_PI_I PH_PI_O ougar Point (H,JT,T) Pin Name trap description ampled onfiguration NT# / PIO NT# / PIO PIO ifferent from alpella No reboot mode setting Top-lock wap Override oot IO election [bit-] oot IO election 0 [bit-0] EI strap (erver only) Intel nti-theft H protection Only for Interposer MI Termination voltage PWROK PWROK PWROK PWROK PWROK PWROK PWROK NT# 0 NT0# 0 PH_RQ#0 PH_RQ# ERIRQ T_RXN0_ T_RXP0_ T_TXN0_ T_TXP0_ T_RXN_ T_RXP_ T_TXN_ T_TXP_ T_OMP T_OMP T_RI _IT0 0 efault (weak pull-down 0K) = etting to No-Reboot mode 0 "top-block swap" mode = efault (weak pull-up 0K) INTVRMEN Integrated.0V VRM enable LWY hould be always pull-up H_OK_EN#/PIO H_O PIO R TP00 0/ mount / short R TP TP0 TP TP M_ *0K_ ifferent from alpella ifferent from alpella R *0_/ Flash escriptor ecurity Only for Interposer Flash escriptor ecurity PWROK PWROK 0 Override = efault (weak pull-up 0K) hould not be pull-down (weak pull-up 0K) weak pull-down 0kohm oot Location PI LP 0 = isable (Internal pull-down 0kohm) H_YN On-ie PLL VR Voltage elect RMRT 0 = upport by.v (weak pull-down) = upport by.v / change net name. L0 [,] L [,] L [,] L [,] LFRME# [,] V PKR PH_INVRMEN PIO.V 0 Override / --> modify = efault (weak pull-up 0K) [] Integrated lock hip Enable RMRT# hould be pull-down (weak pull-up 0K) On-die PLL Voltage Regulator RMRT# PI_MOI itpm function isable PWROK K N L T0 K E U RTX RTX INTRUER# INTVRMEN H_LK H_YN H_RT# H_IN0 H_IN H_IN RT IH H_O (V) H_OK_EN# / PIO (V) N H_OK_RT# / PIO J H K H T Y T V U RTRT# RTRT# PKR H_IN JT_TK JT_TM JT_TI JT_TO PI_LK PI_0# PI_# PI_MOI PI_MIO PI JT T LP T ougarpoint_rev_0p fcbga-intel-cougarpoint J0QMVY0T0 I TRL(P)OURPOINT QMVY TOP / FWH0 / L0 FWH / L FWH / L FWH / L FWH / LFRME# LRQ0# E LRQ# / PIO K (V) ERIRQ V T0RXN M T0RXP M T0TXN P T0TXP P TRXN M0 TRXP M TTXN P TTXP P0 TRXN TRXP TTXN H TTXP H TRXN TRXP 0 TTXN F TTXP F TRXN Y TRXP Y TTXN TTXP TRXN Y TRXP Y TTXN TTXP TIOMPO TIOMPI TROMPO TOMPI Y Y0 TRI H TLE# P (V) T0P / PIO V (V) TP / PIO P 0 isable = Enable (efault) 0 efault (weak pull-down 0K) = Enable / change net name. R.V V PH_PI_I PIO_E T_RXN0 [] T_RXP0 [] T_TXN0 [] T_TXP0 [] V ERIRQ [] T_RXN [] T_RXP [] T_TXN [] T_TXP [] recommended that coupling capacitors should be close to the connector (<00 mils) for optimal signal quality. / modify for placement. / modify / --> modify / delete excess coupling,,0,0 0,0,, R0 R0 R0 R0 R TP TP.K_./F_./F_ 0/F_ 0K_ 0K_ R R V.0V ircuit *K_ 0K_ UE PIO PIN T_LE# [] [Need external pull-down for LP IO] efault weak pull-up on NT0/# R R R R0 R0 R R0.K_ R R R0 R H0 (T.0b/s) O (T.b/s) Vender *K_ V EON PI_NT# [] ios request, for can't boot apella /. Winbond ocket 0K_ V_RT *K_ *K_ *K_ *K_ R0 Z_OUT R *K_ *K_ K_ K_ [] IT_LK_UIO [] Z_YN_UIO / --> modify PIO_E [].K IT0 _IT [] NV_LE [] Z_YN / reserve. I_EN# [] V *K_ PLL_OVR_EN [] 0/ add for EMI R0 _ 0/ Intel P 00 0P/0V_ R00 M_ NV_LE [] N. at PT E 0. H_N_IV# [] V._._H_IO V RT ircuitry(rt) /: modify V_W V_RT_0 R [] Z_RT#_UIO [] Z_OUT_UIO PH_PI_0# PH_PI_LK PH_PI_I PH_PI_O VPU N T_ONN R _ Z_LK V FOR W V_RT_ V_RT_ RT Power trace width 0mils. R0 R R ize M M / short 0K_ P/N Z_YN Z_RT# Z_OUT PH_PI_LK_R PH_PI_I_R PH_PI_O_R 0mils V_RT H us(l) / delete M function support "Z_LK"-R-"IT_LK_M" "Z_YN"-R-"Z_YN_M" "Z_RT#"-R-"Z_RT#_M" "Z_OUT"-R-"Z_OUT_M" R0 R R *0_ *0_/ K_ R _ R _ KEP0N00 (WQVI) RT lock.khz KEFN0Q00 (ENF-00HIP) *0_ *0_ *0_ R 0 0 Q N00K 0P/0V_ *P/0V_ P/0V_ P/0V_ 0 T *.K_ /0 add. R 0K/F_ R 0K/F_ U/.V_ RT_RT# V RT_X RT_X U/.V_ *0_ RT_RT# RT_RT# RT_RT# PH JT ebug(l) / : modify /: modify PH_JT_TM PH_JT_TI_R PH_JT_TO_R PH_JT_TK_R PH PI ROM(L) [0] V._._H_IO [,,,,0,,,,,,,,,,,,,,,,] V [,,,,,0,] VPU [,0] V_W [,0,] V_RT [,0,,].V ize ocument Number Rev ustom ate: Monday, November, 00 heet of 0 V J *OLERJUMPER- 0/ remove all R (Intel confirmed) U E# V K I O HOL# WP# Y.KHZ R0 V *PI Flash ocket R 0M_ 0 U/.V_ R R R *0/F_ *0/F_ *0/F_ R R *00/F_ *00/F_ R R *00/F_ J *OLERJUMPER- R *_ *.K_ *0.U/0V_

8 [] PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# MP_PWR_TRL# L_K [] PI_PLTRT# U_O# U_O# U_O# U_O# MP_PWR_TRL# [] [] [] [] PU_ILE_INT# LK_M_EU [] PI/UO# Pull-up(L) LK_M_K PLTRT# V MP witch ontrol MP_PWR_TRL# PLTRT#(L) T_OMO_EN# _IT PI_NT# L_K ios swap PIO /. / remove R in OM R 0_ / change net name to "PH_PIO" delete "PU_ILE_INT#" pull-hi R R R R TP TP LK_PI_F V.K_.K_.K_.K_ 0K_0PR_ V / change V Part reference. RP 0 PH_PIO T_OMO_EN# 0 P/0V_ RP 0 0K_0PR_ / change Part reference. U_O# U_O0# U_O# U_O# Low = MP ON High = MP OFF (efault) R R 0 PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# T_OMO_EN# _IT PI_NT# MP_PWR_TRL# L_K PH_PIO PU_ILE_INT# / delete R00 0 P/0V_ U *TH0FU PI_PLTRT# LK_PI_TPM_R LK_PI_R_R R0 _ LK_PI_F_R PI_PME# *_LK_PI_LP_R / EMI(near PH) TP *K_ R _ *0.U/0V_ PLTRT# [,,,,,] LK_PI_E_R ougar Point-M (PI,U,NVRM) J H J H H K K N0 H H M M Y K L M0 Y E 0 E J E0 F V U Y0 U Y V W0 K0 K H E0 E F 0 K0 H H J K H0 /0 modify [,,] [,,] UE TP TP TP TP TP TP TP TP TP TP0 TP TP TP TP TP TP TP TP TP TP0 TP TP TP TP TP TP TP TP TP TP0 TP TP TP TP TP TP TP TP TP TP0 PLTRT# / modify M_PH_T R 00K_ M_PH_LK PIRQ# PIRQ# PIRQ# PIRQ# REQ# / PIO0 (V) REQ# / PIO (V) REQ# / PIO (V) NT# / PIO (V) NT# / PIO (V) NT# / PIO (V) PIRQE# / PIO (V) PIRQF# / PIO (V) PIRQ# / PIO (V) PIRQH# / PIO (V) PME# PLTRT# LKOUT_PI0 LKOUT_PI LKOUT_PI LKOUT_PI LKOUT_PI MLK MT Mus/Pull-up(L) V RV PI V NVRM U ougarpoint_rev_0p fcbga-intel-cougarpoint J0QMVY0T0 I TRL(P)OURPOINT QMVY TOP / Q N00 N00 Q0 Q N00 NV_E#0 NV_E# NV_E# NV_E# NV_Q0 NV_Q NV_Q0 / NV_IO0 NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q0 / NV_IO0 NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_LE NV_LE NV_ROMP NV_R# NV_RE#_WR0 NV_RE#_WR NV_WE#_K0 NV_WE#_K UP0N UP0P UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UP0N UP0P UPN UPP UPN UPP UPN UPP URI# URI (V) O0# / PIO (V) O# / PIO0 (V) O# / PIO (V) O# / PIO (V) O# / PIO (V) O# / PIO (V) O# / PIO0 (V) O# / PIO R R Q N00 M_ME_LK V M_ME_T M_RUN_T [,].K_.K_ R R M_RUN_LK [,].K_.K_ Y V U T0 U T T T Y T V V E F V Y V0 T Y T F K H E N M L0 K0 0 E0 0 0 L K E K0 L NV_LE NV_LE U_I WLN LN UP- [] UP [] UP- [] UP [] UP- [] UP [] TP00 TP00 UP- [] UP [] UP0- [] UP0 [] UP- [] UP [] [] [] [] [] [] [] [] [] [] [] [] [] NV_LE [] NV_LE [] / --> modify HM Port & Port are disable PIE_RXN PIE_RXP PIE_TXN PIE_TXP PIE_RXN_LN PIE_RXP_LN PIE_TXN_LN PIE_TXP_LN PIE_RXN_U PIE_RXP_U PIE_TXN_U PIE_TXP_U U.0 U.0 U.0 luetooth amera WLN ard Reader EXTERNL U.0 / --> modify U.0/U.0 OMO U.0/U.0 OMO / delete T function (U) delete net "U/-" 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ PIE_TXN_ PIE_TXP_ ougar Point-M (PI-E,MU,LK) PIE_TXN_LN_ PIE_TXP_LN_ PIE_TXN_U_ PIE_TXP_U_ LK_PH_R0N LK_PH_R0P LK_PIE_REQ0# LK_PH_RN LK_PH_RP LK_PIE_REQ# LK_PIE_REQ# LK_PIE_REQ# LK_PIE_REQ# J V U E F Y J V U F E Y H Y J U V 0 J0 Y0 0 E W Y Y0 Y J M V0 Y Y Y Y L U PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP LKOUT_PIE0N LKOUT_PIE0P (V) LKOUT_PIEN LKOUT_PIEP (V) LKOUT_PIEN LKOUT_PIEP (V) LKOUT_PIEN LKOUT_PIEP (V) LKOUT_PIEN LKOUT_PIEP PI-E* PIELKRQ0# / PIO PIELKRQ# / PIO PIELKRQ# / PIO0 PIELKRQ# / PIO PIELKRQ# / PIO MLERT# M_PH_LK M_PH_T RMRT_NTRL_PH M_ME0_LK M_ME0_T MLLERT#_R M_ME_LK M_ME_T R (V) LK_PH_M./F_ REFLKIN K V LKOUT_PIEN ios swap PIO /. V LKOUT_PIEP H LK_PI_F U_O0# LKIN_PILOOPK [] OR_I0 L U_O# PIELKRQ# / PIO P/0V_ U_O# (V) U_O# LK_PH_PEN R0 Y U_O# LK_PH_PEP LKOUT_PE N / --> modify change FP 0 XTL_IN U_O# XTL_IN V M_ LKOUT_PE P MHZ V XTL_OUT U_O# LK_PE_REQ# XTL_OUT E U_O# PE LKRQ# / PIO P/0V_ (V) / hange net name [] INT_T_OMO_EN# V0 LKOUT_PIEN XLK_ROMP "OR_I" to V Y R0 0./F_ LKOUT_PIEP XLK_ROMP.0V "INT_T_OMO_EN#" [] OR_I T PIELKRQ# / PIO (V) (V) V K LK_FLEX0 R _ LKOUT_PIEN LKOUTFLEX0 / PIO LK_M_R [] V LKOUT_PIEP (V) F LK_FLEX R0 _ LKOUTFLEX / PIO LK_M_U.0 [] K LK_REQ/trap Pin(L) V PIELKRQ# / PIO (V) LK_FLEX (V) H LKOUTFLEX / PIO 0/0 R mount K LK_PIE_REQ# (V) Rb R0 *_ 00 TP R 0K_ LKOUT_ITPXP_N LK_FLEX TP K K LK_PIE_REQ# LKOUT_ITPXP_P LKOUTFLEX / PIO TP00 0P/0V_ R 0K_ 0/ add for EMI LK_PH_ITPN Remove Ra, Rb for UM &. V LK_PH_ITPP ougarpoint_rev_0p J0QMVY0T0 MHz support I only. / add R0, exchange M net fcbga-intel-cougarpoint I TRL(P)OURPOINT QMVY TOP / 0/ remove M circuit LK_PIE_REQ0# R 0K_ LK_PIE_REQ# R 0K_ LK_PIE_REQ# PIE lock / change Part reference. R 0K_ [] LK_PIE_WLNN RP LK_PH_R0N [] LK_PIE_WLNP LK_PH_R0P V Mus/Pull-up(L) WLN 0_PR_0 LK_PE_REQ# R0 *0K_ [] PIE_LKREQ_WLN# R 0_ LK_PIE_REQ0# LK_PE_REQ# Ra R *0K_ R K_ RMRT_NTRL_PH : Rb ; UM : Ra / change Part reference. LK_PE_REQ# Rb R *0K_ [] LK_PIE_LNN RP LK_PH_RN R 0K_ MLERT# LK_PE_REQ# R 0K_ LN [] LK_PIE_LNP 0_PR_0 LK_PH_RP R.K_ M_PH_LK [] PIE_LKREQ_LN# R 0_ LK_PIE_REQ# R.K_ M_PH_T LK_UF_LK_N R 0K_ R.K_ M_ME0_LK LK_UF_LK_P R 0K_ / change Part reference. R.K_ M_ME0_T [] LK_PIE_V# RP LK_PH_PEN R 0K_ MLLERT#_R LK_UF_PIE_PLL# R 0K_ PU [] LK_PIE_V 0_PR_0 LK_PH_PEP LK_UF_PIE_PLL R 0K_ [] PIE_LKREQ_V# R 0_ LK_PE_REQ# LK_UF_REFLK# R 0K_ LK_UF_REFLK R 0K_ LK_UF_REFLK# R 0K_ [] LK_PIE_UN RP LK_PH_PEN LK_UF_REFLK U.0 [] LK_PIE_UP 0_PR_0 R 0K_ LK_PH_PEP LK_PH_M R 0K_ / delete R ize ocument Number Rev LOK TERMINTION for FIM [,,,,0,,,,,,,,,,,,,,,,] V ustom [,,,,0,,,,,,,,] V Monday, November, 00 ate: heet of 0 MU (V) (V) (V) MLLERT# / PHHOT# / PIO (V) MLLK / PIO (V) MLT / PIO ontroller Link LOK FLEX LOK MLERT# / PIO MLK MT ML0LERT# / PIO0 ML0LK ML0T L_LK L_T L_RT# (V) PE LKRQ# / PIO LKOUT_PE N LKOUT_PE P LKOUT_MI_N LKOUT_MI_P LKOUT_P_N LKOUT_P_P LKIN_MI_N LKIN_MI_P LKIN_N_N LKIN_N_P LKIN_OT_N LKIN_OT_P LKIN_T_N LKIN_T_P E H E M M T P0 M0 V U M M F E J0 0 E K K L_LK_R L_T_R L_RT#_R LK_PE_REQ# LK_PH_PEN LK_PH_PEP LK_UF_PIE_PLL# LK_UF_PIE_PLL LK_UF_LK_N LK_UF_LK_P LK_UF_REFLK# LK_UF_REFLK LK_UF_REFLK# LK_UF_REFLK RMRT_NTRL_PH [] TP0 TP TP TP LK_PU_LKN [] LK_PU_LKP [] LK_PLL_LKN [] LK_PLL_LKP [] / del external clock generator.

9 Reserve / --> modify [] IO_EXT_MI# [] IO_EXT_I# / delete net "T_OFF#" [] [] I_EN# RF_OFF# [] O_PRNT# [,,] PU_PWROK [,] PU_HOL_RT# [] PLL_OVR_EN [,,] PU_PWR_EN [] TP _PIO OPTIMU POWER control pin PU_PWROK PIO PU_HOL_RT# PIO PU_PWR_EN PIO / modify TP00 R 00_ R *0_ R 0_ R 0_ R 0_ R 0_ IO_EXT_MI# IO_EXT_I# T_OFF# I_EN# LN_ILE#_R RF_OFF# O_PRNT#_R IO_RE OR_I PIO PLL_OVR_EN_R OR_I OR_I PU_PWR_EN_R FI_OVRVLT MF_MOE PU_PRNT# TET_ET_UP TP V_ET UF T MUY# / PIO0 (V) TH / PIO (V) H TH / PIO (V) E TH / PIO 0 (V) PIO (V) LN_PHY_PWR_TRL / PIO (V) PIO (V) U TP / PIO (V) 0 TH0 / PIO T (V) LOK / PIO E (V) PIO / MEM_LE (V) E PIO (W) P PIO K (V) TP_PI# / PIO K (V) PIO V (V) TP / PIO (V) M TP / PIO (V) N LO / PIO M (V) TOUT0 / PIO V (V) TOUT / PIO V (V) TP / PIO (V) PIO (V) E E F F V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ PIO NTF PU/MI TH / PIO 0 (V) TH / PIO (V) TH / PIO0 (V) TH / PIO 0 (V) 0TE PEI RIN# PROPWR THRMTRIP# INIT_V# N_ N_ N_ N_ N_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ ougarpoint_rev_0p I TRL(P)OURPOINT QMVY TOP / fcbga-intel-cougarpoint J0QMVY0T0 P U P Y Y0 T H K H0 K0 P H H J J J J J J E E F F PIO PIO PIO E_RIN# PH_THRMTRIP# R R R PU_OPT_I# RF_PWR_OFF# [] / add "RF_PWR_OFF#" control from PH.K/F_ *.K/F_ R 0_ V V E_0TE [] E_RIN# [] H_PWROO [] / stuff R PM_THRMTRIP# [,] 000 modify: MF_MOE. elete TH0.. PIO0 connect PU optimus / discrete setting. R0 0_ *0K_ rev0. suggest to T_V connect to N /. lock en Power OK (L) _PIO RF_OFF# Low = isable (efault) High = Enable TET_ET_UP / del external clock generator. / modify elete net "PIO0",connect PU optimus / discrete circuit R MF-TET ios swap PIO /. R Intel ME rypto Transport Layer ecurity (TL) cipher suite *0_ R V_ET_UP High = trong (efault) R R0 R R K_ 0K_ 0K_ *0_ 0K_ *0_ V V V V PU_OPT_I#: High : Optimus. Low: iscrete. LN_ILE#_R IO_EXT_I# IO_EXT_MI# T_OFF# E_0TE E_RIN# TP PIO O_PRNT#_R PU_PWROK PU_PWROK PIO IO REOVERY IO_RE V_ET PU_OPT_I# V PIO Pull-up/Pull-down(L) R R R R R R0 R R / update net name from / modify "PU_V_EN" to "PU_PWROK" R R *0_ 00K_ R R0 R R V V High = isable (efault) Low = Enable TET ETET Low = efault R0 *0K/F_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_.K/F_ 0K_ *0K_ / delete "PIO0" and R 0/0 double pull high *0K_ 0K_ R R R0 0K/F_ 0K_ 0K_ *0K_ V V OR I ETTIN x 0 x 0 x [] OR_I0 OR_I0 / delete net "OR_I" OR_I [] OR_I R R R R R R *0K_ OR_I0 *0K_ OR_I 0K_ OR_I *0K_ OR_I 0K_ OR_I *0K_ OR_I R 0K_ R *0K_ R0 *0K_ R *0K_ R *0K_ R *0K_ / modify 0/ correct board I V V V 0/ no need pull high MI TERMINTION VOLTE OVERRIE Rb R00 PU_PWR_EN_R tuff N Low = Tx, Rx terminated to same voltage ( oupling Mode) (EFULT) FX Present Ra *00K_ PU_PRNT# R Ra Rb R0 UM Rb Ra *00K/F_ 0K_ V V V R 00K_ FI TERMINTION VOLTE OVERRIE FI_OVRVLT R *K_ LOW - Tx, Rx terminated to same voltage [,,,,0,,,,,,,,,,,,,,,,] V [,,,,0,,,,,,,,] V ize ocument Number Rev ustom ate: Monday, November, 00 heet of 0

10 .0V V.0V.0V / short.0v.0v.0v.0v R 0.00/F_0 R.0V R V_PRO_IO=m (0mils) V_RT VRT<m (0mils).0V_VEPW 0 U/.V_ U/.V_ U/.V_ *0_ 0 *0U/.V_ U/.V_ U/.V_.0 (0mils) U/.V_ VLK V_W R *0_ VPW m (0mils) T VW_ 0 /: modify PH_VW 0.U/0V_ V PUYP *0.U/0V_ 0/ remove for leakage V_U_LKF T V_[] /: modify.0v VPLL_PY_PH H VPLLMI L0 VPLL_PY L VIO[] R R0 R *0_ R 0_ *0uH/00m_ R R0 *0_/ *0_/ *0_/ *0_/ *U/.V_ *0_/ short00 0 U/.V_ VU *U/.V_ VFI_VRM 0m (0mils).0V_V PL m (0mils).0V_V PL m (0mils) VIFFLK VIFFLKN m (0mils) V.0V_V m (0mils) VT 0.U/0V_ V.0M_VU VTT_VPPU U/.V_.U/.V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ U/.V_ 0.U/0V_ [,,,].V [,,,,,,].VU [,,,].0V ougar Point-M (POWER) L W W W W W W W Y F UJ VW[] VW[] VW[] VW[] VW[] VW[] VW[] VW[] VW[0] VW[] VW[] VPLL lock and Miscellaneous F VIO[] F VIFFLKN[] F VIFFLKN[] VIFFLKN[] VLK VRTEXT N 0.U/0V_ PRT V T PU[] V PU[] J PU[] VW[] VW[] VW[] VW[] VW[] VW[] VW[] VW[] VW[0] VVRM[] VPLL V PT V_PRO_IO VRT PU RT T PI/PIO/LP U MI H ougarpoint_rev_0p fcbga-intel-cougarpoint J0QMVY0T0 I TRL(P)OURPOINT QMVY TOP / VIO[] VIO[0] VIO[] VIO[] VIO[] VU_[] VU_[] VU_[] VU_[0] VU_[] VIO[] VREF_U PU[] VU_[] VREF VU_[] VU_[] VU_[] VU_[] V_[] V_[] V_[] V_[] VIO[] VIO[] VIO[] VIO[] VPLLT VVRM[] VIO[] VIO[] VIO[] VW[] VW[] VW[] VUH N P P T T T T V V P T M N N P N0 N P0 P W T J F H H F K F T V T P V_VPU V_VU VUPLL V_PH_VREFU V_UU V_VPU V_PH_VREF m (mils) V_VPU m (0mils) V_VPORE V V.0_T V.LN_VPLL VFI_VRM.0V_VIO.0 (0mils).0V_VEPW.0V_VUORE 00 0.U/0V_ 0m (0mils) R V._._H_IO 0 0.U/0V_ [,,,,,,,] V [,,,,,,,,,,,,0] V [,,,,,,,,,,,,,,,,,,,,] V [,,,,,,,,,,,,] V [,] V_W [,,] V_RT V.0V U/.V_ m (0mils) 0.U/0V_ R0 R 0 0.U/0V_ R R R0 U/.V_ R 0 0.U/0V_ 0.U/0V_ R 0 U/.V_ U/.V_ R 0_ *U/.V_ *0_/ *U/.V_ L *0uH/00m_ *0U/.V_ R *0_/ *0_/ *0_/ *0_/ *0_/ *0_/ *0_/ *0_ V.0V V / short V.0V.0V.0V.VU V.V_PU.0V.0V.0V.0V.0V V (Mobile.V).0V V. (0mils).0V_PH_V R0 0.00/F_0.0V_PH_VPLL_EXP R *0_/.0V_VPLL_EXP L *uh/m_.0v_vio R. (0mils) 0.00/F_0 0U/.V_ R 0_ R0 R 0m (mils) R00 0_.0V.0V 0 U/.V_ U/.V_ V_V_EXP VFI_VRM *0_ L 0uH/00M_ L 0uH/00M_ R *0_ 0 U/.V_ VFI_VRM.0V_VPLL_FI R *0_ R0 0_.0V_VPLL_FI m (0mils).0V_V PL m (0mils).0V_V PL 0m (0mils) V_U_LKF U/.V_ U/.V_ /F_ V_U_LKF_R L 0uH/00M_ 0m (0mils).0V V_MI_I.V_V_MI_I R */F_ R 0_ 0 0U/.V_ 0 *0U/.V_ U/.V_ U/.V_ 00 0.U/0V_ L *0uH/00m_ OUR POINT (POWER) 0 U VORE[] VORE[] VORE[] VORE[] F VORE[] F VORE[] VORE[] VORE[] VORE[] VORE[0] VORE[] VORE[] J VORE[] J VORE[] J VORE[] J VORE[] J VORE[] N J N N N N N P P P P T N N H P P U0 VIO[] VPLLEXP VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] V_[] VVRM[] VccFIPLL VIO[] VMI[] U/.V_ U/.V_ / modify *0U/.V_ *0U/.V_ V ORE VIO FI U/.V_ 0U/.V_ RT LV NN / PI MI HVMO / add for RT wave noise ougarpoint_rev_0p fcbga-intel-cougarpoint J0QMVY0T0 I TRL(P)OURPOINT QMVY TOP / V_PH_VREF U00 V *0TU V_LO Vin Vout 00 *U/.V_ V V_LO V V U m (0mils) L H0KF-T/._ V U VLV VLV VTX_LV[] VTX_LV[] VTX_LV[] VTX_LV[] V_[] V_[] VVRM[] VMI[] VLKMI VPNN[] VPNN[] VPNN[] VPNN[] VPI m (0mils) K K M M P P & UM : Ra I : Rb V V T T0 J J V VREF= m VFI_VRM V_PH_VREFU VLV V Ra R 0_ Rb R *0_ 0m (0mils) Ra V_TX_LV L 0.uH/0m_ V_V_IO VREFU=m R.V_V_MI_I U/.V_ 0 m (mils) VP_NN Rb R 0m (0mils) V_VME_PI N R 0.U/0V_ R 0 0.U/0V_ R U/.V_ 0.U/0V_ 0U/.V_ 0.U/0V_ 0.0U/V_ 0.0U/V_ V m (0mils).V_V_MI *0U/.V_ U/.V_ *0_ *0_ U/.V_ 0.0U/V_ *0_/ R U/.V_.V *0_/ *0_/ V R 0_ R0 0_.V R00V-0 R00V-0.0V *0_/ / short V V V V ize ocument Number Rev ustom ate: Monday, November, 00 heet 0 of 0

11 ize ocument Number Rev ate: heet of ustom 0 Monday, November, 00 ize ocument Number Rev ate: heet of ustom 0 Monday, November, 00 ize ocument Number Rev ate: heet of ustom 0 Monday, November, 00 IEX PEK-M (N) IEX PEK-M (N) UI ougarpoint_rev_0p UI ougarpoint_rev_0p V[] Y V[0] Y V[] Y V[] Y V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] 0 V[] V[] V[] V[] 0 V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] 0 V[] V[] V[] V[] V[] E V[] E V[] E0 V[] F0 V[00] F V[0] F V[0] F0 V[0] F V[0] F V[0] F V[0] F V[0] V[0] F0 V[0] F V[0] F0 V[] F V[] V[] V[] V[] V[] V[] H V[] H V[] H V[0] H V[] H V[] H V[] H V[] H V[] H V[] H V[] H V[] V[0] V[] V[] V[] V[] V[] V[] 0 V[] V[] K V[] L V[] L V[] L0 V[] L V[] L V[0] L V[] L V[] M V[] P V[] M V[] M V[] M V[] M0 V[] M V[] M V[0] M V[] M V[] M V[] M V[] M V[] N V[] P0 V[] P V[] P V[0] T V[] P0 V[] P V[] P V[] P V[] R V[] R V[] T V[] T V[] T V[00] T V[0] W V[0] T V[0] T V[0] T V[0] V V[0] V V[0] V V[0] V V[0] V V[0] V V[] V V[] V V[] V V[] V V[] W V[] W V[] V[] V[0] V[] V[] E V[] E V[] V[] 0 V[] V[] V[] V[] V[0] H V[] H V[] W V[] W V[] W V[0] Y V[] Y V[] Y V[] Y V[] Y V[] Y V[] V[] N V[0] J V[] N V[] H V[] H V[] H V[] H0 V[] H V[] H V[] F V[] K V[] K V[] H V[0] K V[] K V[] V[] V[] E0 V[] V[] V[] H V[0] T V[] V[] V[] V[] P V[] F V[] H0 V[] M V[] P V[] P V[] E V[0] V[] V[] J UH ougarpoint_rev_0p UH ougarpoint_rev_0p V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] 0 V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] 0 V[] V[] V[] V[] V[] F0 V[] F V[] V[] F V[] F V[] F V[0] F V[] F V[] F V[] F V[] F V[] F V[] F V[] F V[] F V[0] F V[] V[] V[] V[] V[] H V[] H V[] H V[] H V[] H0 V[0] H V[] H V[] H V[] J V[] J V[] J V[] K V[] K V[0] K V[] K V[] K V[] K V[] K V[] L V[] L V[] L V[] L V[] L V[0] L V[] L V[] L V[] L V[] L V[] M V[] M V[] M V[00] M V[0] M V[0] M V[0] M V[0] N V[0] N V[0] N V[0] N V[0] P V[0] P V[] P V[] P0 V[] P V[] P V[] P V[] P V[] P V[] R V[0] R V[] T V[] T V[] T V[] T V[] T V[] T V[] T0 V[] T V[] T V[] T V[] T V[] U V[] U0 V[] V V[] V0 V[] V V[] V0 V[0] V V[] V V[] V V[] V V[] W V[] W V[] W V[] W V[] W V[] W V[0] W V[] W V[] W V[] W0 V[] W V[] V V[] Y V[] Y V[] Y V[0] V[] E V[] V[] P V[0] H V[] F V[] V[] V[] J V[] J V[] E V[] T V[0] T V[0] M V[] L V[] L

12 M 0 M M M M M M 0 M M M M M M M M M M_RUN_LK M_RUN_T M M M M M QP0 M QP M QP M QP M QP M QP M QP M QP M QN0 M QN M QN M QN M QN M QN M QN M QN M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q IMM0_0 IMM0_ MR_VREF_IMM PM_EXTT#0 MR_VREF_Q0 MR_VREF_Q0_M MR_VREF_Q0_M MR_VREF_IMM R_VTTREF MR_VREF_Q0_M M Q M Q M Q M Q M Q M Q0 M [:0] [] M #0 [] M # [] M # [] M #0 [] M # [] M LKP0 [] M LKN0 [] M LKP [] M LKN [] M KE0 [] M KE [] M # [] M R# [] M WE# [] M QP[:0] [] M QN[:0] [] M OT0 [] M OT [] M Q[:0] [] M_RUN_LK [,] M_RUN_T [,] R_RMRT# [,] MR_VREF_Q0_M [] R_VTTREF [,,] PM_EXTT#0 [] V [,,,,,0,,,,,,,,,,,,,,,].VU [,,0,,,,] 0.V_R_VTT [,,] VPU [,,,,,,0,].VU V 0.V_R_VTT V.VU.VU MR_VREF_IMM V.VU 0.V_R_VTT MR_VREF_Q0 ize ocument Number Rev ate: heet of ustom 0 Monday, November, 00 ize ocument Number Rev ate: heet of ustom 0 Monday, November, 00 ize ocument Number Rev ate: heet of ustom 0 Monday, November, 00. VREF Q0 M olution Place these aps near o-imm0. /: layout modify / FP changed from 0U_.V_.0x.ER0m to 0U/.V_x.ER / delete.u/.v_.u/.v_ *0U/.V_ *0U/.V_ P00 R RM O-IMM (0P) JIM R-IMM0_H=._RV R--00-RV-0P MK000 I OKET RIII O-IMM(0P,H.,RV) P00 R RM O-IMM (0P) JIM R-IMM0_H=._RV R--00-RV-0P MK000 I OKET RIII O-IMM(0P,H.,RV) V V V V V V V V V V0 00 V 0 V 0 V V V V V V VP N N NTET EVENT# REET# 0 VREF_Q VREF_ V V V V V V V V 0 V V0 V V V V V V V V V V0 V 0 V V V V V V V V V0 V V V V V 0 V V V V V0 V V V V V V V V V V0 0 V V VTT 0 VTT 0 N 0 N 0 R0 0K_ R0 0K_ 0 0P/0V_ 0 0P/0V_ P00 R RM O-IMM (0P) JIM R-IMM0_H=._RV R--00-RV-0P MK000 I OKET RIII O-IMM(0P,H.,RV) P00 R RM O-IMM (0P) JIM R-IMM0_H=._RV R--00-RV-0P MK000 I OKET RIII O-IMM(0P,H.,RV) 0 0 0/P 0 /# # # K0 0 K0# 0 K 0 K# 0 KE0 KE # R# 0 WE# 0 0 L 0 00 OT0 OT 0 M0 M M M M M M 0 M Q0 Q Q Q Q Q Q Q Q#0 0 Q# Q# Q# Q# Q# Q# Q# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q0 Q Q Q Q Q Q Q 0 Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q U/.V_ U/.V_ R *0_ R *0_ U/.V_ U/.V_ 0.U/0V_ 0.U/0V_ R 0K_ R 0K_.U/.V_.U/.V_ 0U/.V_ 0U/.V_ U/.V_ U/.V_ *0U/.V_ *0U/.V_ U/.V_ U/.V_ 0U/.V_ 0U/.V_ 0.U/0V_ 0.U/0V_ R 0_ R 0_ U/.V_ U/.V_ 0U/.V_ 0U/.V_ U/.V_ U/.V_ R *0_ R *0_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ R 0K_ R 0K_ 0 0U/.V_ 0 0U/.V_ R *0_ R *0_ U/.V_ U/.V_ R 0K_ R 0K_ R 0K_ R 0K_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ R K/F_ R K/F_ U/.V_ U/.V_.U/.V_.U/.V_ 0.U/0V_ 0.U/0V_ R K/F_ R K/F_

13 M 0 M M M M M M 0 M M M M M M M M M M M M M M QP0 M QP M QP M QP M QP M QP M QP M QP M QN0 M QN M QN M QN M QN M QN M QN M QN M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q IMM_0 IMM_ PM_EXTT#0 MR_VREF_Q MR_VREF_Q_M MR_VREF_Q_M MR_VREF_Q_M M Q0 M Q M Q0 M Q R_THERM MLK MT PM_EXTT#0 R_THERM PM_EXTT#0_E M [:0] [] M #0 [] M # [] M # [] M #0 [] M # [] M LKP0 [] M LKN0 [] M LKP [] M LKN [] M KE0 [] M KE [] M # [] M R# [] M WE# [] M QP[:0] [] M QN[:0] [] M OT0 [] M OT [] M Q[:0] [] R_RMRT# [,] M_RUN_LK [,] M_RUN_T [,] MR_VREF_Q_M [] R_VTTREF [,,] MT [,,] PM_EXTT#0 [] MLK [,,] V [,,,,,0,,,,,,,,,,,,,,,].VU [,,0,,,,] 0.V_R_VTT [,,] VPU [,,,,,,0,].VU V 0.V_R_VTT MR_VREF_IMM V V MR_VREF_IMM MR_VREF_Q.VU V V V.VU 0.V_R_VTT ize ocument Number Rev ate: heet of ustom 0 Monday, November, 00 ize ocument Number Rev ate: heet of ustom 0 Monday, November, 00 ize ocument Number Rev ate: heet of ustom 0 Monday, November, 00 Place these aps near o-imm.. VREF Q M olution R Thermal ensor 0/0 double pull high 0/ remove 0U/.V_ 0U/.V_ R 0_ R 0_ R *0K_ R *0K_ R K/F_ R K/F_ U/.V_ U/.V_ 0U/.V_ 0U/.V_ U/.V_ U/.V_ *00P/0V_ *00P/0V_ 0 0.U/0V_ 0 0.U/0V_ R0 *0_ R0 *0_ *0U/.V_ *0U/.V_ 00 0.U/0V_ 00 0.U/0V_.U/.V_.U/.V_ R 0K_ R 0K_ P00 R RM O-IMM (0P) JIM R-IMM_H=._RV R-0-URN-F-0P MK000 I OKET RIII O-IMM(0P,H.,RV) P00 R RM O-IMM (0P) JIM R-IMM_H=._RV R-0-URN-F-0P MK000 I OKET RIII O-IMM(0P,H.,RV) 0 0 0/P 0 /# # # K0 0 K0# 0 K 0 K# 0 KE0 KE # R# 0 WE# 0 0 L 0 00 OT0 OT 0 M0 M M M M M M 0 M Q0 Q Q Q Q Q Q Q Q#0 0 Q# Q# Q# Q# Q# Q# Q# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q0 Q Q Q Q Q Q Q 0 Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q.U/.V_.U/.V_ 0 0U/.V_ 0 0U/.V_ 0U/.V_ 0U/.V_ *0.0U/V_ *0.0U/V_ 0U/.V_ 0U/.V_.U/.V_.U/.V_ R 0K_ R 0K_ Q *MMT0--F Q *MMT0--F 0 0U/.V_ 0 0U/.V_ 0 U/.V_ 0 U/.V_ 0U/.V_ 0U/.V_ R *0_ R *0_ U/.V_ U/.V_ 0U/.V_ 0U/.V_ R *0K_ R *0K_ 0 U/.V_ 0 U/.V_ U *0PU U *0PU V XP XN N LK LERT# OVERT# U/.V_ U/.V_ U/.V_ U/.V_ P00 R RM O-IMM (0P) JIM R-IMM_H=._RV R-0-URN-F-0P MK000 I OKET RIII O-IMM(0P,H.,RV) P00 R RM O-IMM (0P) JIM R-IMM_H=._RV R-0-URN-F-0P MK000 I OKET RIII O-IMM(0P,H.,RV) V V V V V V V V V V0 00 V 0 V 0 V V V V V V VP N N NTET EVENT# REET# 0 VREF_Q VREF_ V V V V V V V V 0 V V0 V V V V V V V V V V0 V 0 V V V V V V V V V0 V V V V V 0 V V V V V0 V V V V V V V V V V0 0 V V VTT 0 VTT 0 N 0 N 0 R K/F_ R K/F_ 0.U/0V_ 0.U/0V_ *0U/.V_ *0U/.V_ 0 0U/.V_ 0 0U/.V_ U/.V_ U/.V_

14 .0V_FX.0V_FX V_FX V_FX U/.V_ 0U/.V_ 0.U/.V_ U/.V_ 0 U/.V_ 0.U/0V_ 0.U/0V_ U/.V_ 0U/.V_.U/.V_ U/.V_ U/.V_ 00 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0 0.U/0V_.U/.V_ U/.V_ 0.U/0V_ 0 0.U/0V_ 0.U/0V_ L0 0_.U/.V_ 0.U/0V_ 0.0U/V_ U K PEX_IOV_ K PEX_IOV_ K PEX_IOV_ K PEX_IOV_ K PEX_IOV_ PEX_IOVQ_ PEX_IOVQ_ PEX_IOVQ_ PEX_IOVQ_ PEX_IOVQ_ PEX_IOVQ_ PEX_IOVQ_ PEX_IOVQ_ PEX_IOVQ_ PEX_IOVQ_0 PEX_IOVQ_ PEX_IOVQ_ J PEX_IOVQ_ J PEX_IOVQ_ J PEX_IOVQ_ J PEX_IOVQ_ J PEX_IOVQ_ J PEX_IOVQ_ J PEX_IOVQ_ J PEX_IOVQ_0 K PEX_IOVQ_ K0 PEX_IOVQ_ K PEX_IOVQ_ K PEX_IOVQ_ L PEX_IOVQ_ J V_ J0 V_ J V_ J V_ J V_ PEX_V_V_ F PEX_V_V_N N_ N_ N_ N_ N_ N_ N_ N_ N_ N_0 E N_ F N_ N_ N_ H N_ H N_ H N_ H N_ H N_ J N_0 K N_ L N_ N_ N_ E N_ N_ N_ N_ N_ N_0 N_ N_ N_ H0 N_ H N_ H N_ H N_ H N_ H N_ H N_0 H N_ H N_ J N_ J N_ L N_ L N_ M N_ P N_ P N_ R N_0 R N_ U N_ V N_ Y N_ Nx NP J0NP0T0 PEX_RX0 P PEX_RX0_N N PEX_RX N PEX_RX_N P PEX_RX R PEX_RX_N R0 PEX_RX P0 PEX_RX_N N0 PEX_RX N PEX_RX_N P PEX_RX R PEX_RX_N R PEX_RX P PEX_RX_N N PEX_RX N PEX_RX_N P PEX_RX R PEX_RX_N R PEX_RX P PEX_RX_N N PEX_RX0 N PEX_RX0_N P PEX_RX R PEX_RX_N R PEX_RX P PEX_RX_N N PEX_RX N PEX_RX_N P PEX_RX R PEX_RX_N R PEX_RX R PEX_RX_N P PEX_TX0 L PEX_TX0_N M PEX_TX M PEX_TX_N M PEX_TX L PEX_TX_N K PEX_TX L0 PEX_TX_N M0 PEX_TX M PEX_TX_N M PEX_TX L PEX_TX_N K PEX_TX L PEX_TX_N M PEX_TX M PEX_TX_N M PEX_TX L PEX_TX_N K PEX_TX L PEX_TX_N M PEX_TX0 M PEX_TX0_N M PEX_TX L PEX_TX_N K PEX_TX K PEX_TX_N L PEX_TX M PEX_TX_N M0 PEX_TX M PEX_TX_N M PEX_TX N PEX_TX_N P PEX_REFLK R PEX_REFLK_N R PEX_TTLK_OUT J PEX_TTLK_OUT_N J PEX_RT_N PEX_LKREQ_N M R PE_TX PE_TX# PE_TX PE_TX# PE_TX PE_TX# PE_TX PE_TX# PE_TX PE_TX# PE_TX0 PE_TX#0 PE_TX PE_TX# PE_TX PE_TX# PE_TX PE_TX# PE_TX PE_TX# PE_TX PE_TX# PE_TX PE_TX# PE_TX PE_TX# PE_TX PE_TX# PE_TX PE_TX# PE_TX0 PE_TX#0 _PE_RX _PE_RX# _PE_RX _PE_RX# _PE_RX _PE_RX# _PE_RX _PE_RX# _PE_RX _PE_RX# _PE_RX0 _PE_RX#0 _PE_RX _PE_RX# _PE_RX _PE_RX# _PE_RX _PE_RX# _PE_RX _PE_RX# _PE_RX _PE_RX# _PE_RX _PE_RX# _PE_RX _PE_RX# _PE_RX _PE_RX# _PE_RX _PE_RX# _PE_RX0 _PE_RX#0 LK_PIE_V LK_PIE_V# PEX_TTLK PEX_TTLK# V_RT# PEX_LKREQ# R PE_TX [] PE_TX# [] PE_TX [] PE_TX# [] PE_TX [] PE_TX# [] PE_TX [] PE_TX# [] PE_TX [] PE_TX# [] PE_TX0 [] PE_TX#0 [] PE_TX [] PE_TX# [] PE_TX [] PE_TX# [] PE_TX [] PE_TX# [] PE_TX [] PE_TX# [] PE_TX [] PE_TX# [] PE_TX [] PE_TX# [] PE_TX [] PE_TX# [] PE_TX [] PE_TX# [] PE_TX [] PE_TX# [] PE_TX0 [] PE_TX#0 [] 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0 0.U/0V_ 0 0.U/0V_ 0.U/0V_ 0 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ LK_PIE_V [] LK_PIE_V# [] 0K/F_ PE_RX [] PE_RX# [] PE_RX [] PE_RX# [] PE_RX [] PE_RX# [] PE_RX [] PE_RX# [] PE_RX [] PE_RX# [] PE_RX0 [] PE_RX#0 [] PE_RX [] PE_RX# [] PE_RX [] PE_RX# [] PE_RX [] PE_RX# [] PE_RX [] PE_RX# [] PE_RX [] PE_RX# [] PE_RX [] PE_RX# [] PE_RX [] PE_RX# [] PE_RX [] PE_RX# [] PE_RX [] PE_RX# [] PE_RX0 [] PE_RX#0 [] PEX_RT# V_FX V_PU_ENE [] For iscrete /0 add [,,] PU_PWROK [,,,,,] PEX_TERMP PEX_TERMP R0.K/F_ (N) PEX_TERMP H R0 *0_/ TETMOE P TETMOE R 0K/F_ / short PEX_PLLV L PY00T-0Y-N_.0V_FX R *0_/ PEX_PLLV (N) H 0.U/.V_ PEX_PLL_HV_N 0 U/.V_ 0 0.U/0V_ 0/ for NE V_ENE_ 0 V_ENE_ V_ENE_ P VPU_ORE_ENE [] N_ENE_ N_ENE_ E N_ENE_ R R0 *00_ R0 0_ PLTRT# R0 0K/F_ V_FX PEX_LKREQ# For iscrete R 0_ R 0_ [,] PU_HOL_RT# R *0K/F_ U MVH0FT V_FX R *0_ V [,,,].0V_FX [,,,,] V_FX Q *TEU R Q TEU 0.U/0V_ 0K/F_ PIE_LKREQ_V# [] PEX_RT# R0 00K/F_ V I/O.V PEX_RT Power equence ize ocument Number Rev ate: Monday, November, 00 heet of 0 NVV ettling Time Trise >= u Tfail <=00n

15 U U F_M0 VM_Q0 F_M0 VM_Q0 [] F_M[0:0] U0 F_M F_M0 (F_M) F_00 L [0] F_M[0:0] F VM_Q F_M F_M0 (F_M) F_00 V0 VM_Q F_M F_M (F_M) F_0 N E VM_Q F_M F_M (F_M) F_0 U VM_Q F_M F_M F_M F_0 L VM_Q F_M F_M F_0 V VM_Q F_M F_M (F_M0) F_0 N VM_Q F_M F_M (F_M0) F_0 T VM_Q F_M F_M F_M (F_M0) F_0 N F VM_Q F_M F_M (F_M0) F_0 U VM_Q F_M F_M (F_M) F_0 P VM_Q F_M F_M (F_M) F_0 W VM_Q F_M F_M F_M (F_M) F_0 P VM_Q F_M F_M (F_M) F_0 W VM_Q F_M F_M F_0 P E0 VM_Q F_M F_M F_0 W VM_Q F_M F_M F_M (F_M) F_0 K VM_Q F_M F_M (F_M) F_0 W VM_Q F_M0 F_M (F_M) F_0 K 0 VM_Q0 F_M0 F_M (F_M) F_0 U VM_Q0 F_M F_M F_M0 (F_M0) F_0 K VM_Q F_M F_M0 (F_M0) F_0 U VM_Q F_M F_M (F_M) F_ H VM_Q F_M F_M (F_M) F_ U VM_Q F_M F_M F_M (F_M) F_ 0 VM_Q F_M F_M (F_M) F_ 0 T VM_Q F_M F_M (F_M) F_ F0 VM_Q F_M F_M (F_M) F_ T VM_Q F_M F_M F_M (F_M) F_ E 0 VM_Q F_M F_M (F_M) F_ W0 VM_Q F_M F_M (F_M) F_ E VM_Q F_M F_M (F_M) F_ 0 VM_Q F_M F_M F_M (F_M) F_ F VM_Q F_M F_M (F_M) F_ E 0 VM_Q F_M F_M (F_M) F_ F0 F VM_Q F_M F_M (F_M) F_ F VM_Q F_M F_M F_M (F_M) F_ 0 F VM_Q F_M F_M (F_M) F_ F0 VM_Q F_M0 F_M (F_M) F_ VM_Q0 F_M0 F_M (F_M) F_ F VM_Q0 F_M F_M F_M0 (F_M) F_0 K0 VM_Q F_M F_M0 (F_M) F_0 F Y VM_Q F_M F_M (F_M) F_ K F VM_Q F_M F_M (F_M) F_ Y VM_Q F_M F_M (F_M) F_ H0 E VM_Q F_M F_M (F_M) F_ VM_Q F_M F_M (F_M) F_ K VM_Q F_M F_M (F_M) F_ E VM_Q F_M F_M (F_M) F_ L VM_Q F_M F_M(F_M) F_ Y VM_Q F_M F_M (F_M) F_ L0 VM_Q F_M F_M (F_M) F_ E W VM_Q VM_Q[:0] F_M F_M (F_M) F_ M VM_Q F_M F_M (F_M) F_ F Y VM_Q F_M F_M (F_M) F_ N0 VM_Q F_M F_M (F_M) F_ F Y VM_Q VM_Q[:0] F_M F_M (F_M) F_ M0 VM_Q F_M F_M (F_M) F_ F Y0 VM_Q F_M0 F_M (F_M) F_ P VM_Q0 F_M0 F_M (F_M) F_ E W VM_Q0 F_M0 F_0 R 0 VM_Q F_M0 F_0 F Y VM_Q F_M (N) F_ R0 0 VM_Q F_M (N) F_ F VM_Q F_ 0 VM_Q F_ VM_Q VM_M0 F_ VM_Q VM_M0 F_ F VM_Q [] VM_M[:0] P [0] VM_M[:0] VM_M F_QM0 F_ H VM_Q VM_M F_QM0 F_ F H VM_Q VM_M F_QM F_ F 0 VM_Q VM_M F_QM F_ E J0 VM_Q VM_M F_QM F_ F0 F VM_Q VM_M F_QM F_ P0 VM_Q VM_M F_QM F_ E0 VM_Q VM_M F_QM F_ F F VM_Q VM_M F_QM F_ VM_Q VM_M F_QM F_ L VM_Q VM_M F_QM F_ 0 VM_Q0 VM_M F_QM F_ E L VM_Q0 VM_M F_QM F_0 N VM_Q VM_M F_QM F_0 E F VM_Q F_QM F_ L VM_Q F_QM F_ F VM_Q F_ M VM_Q F_ VM_Q VM_WQ0 F_ L VM_Q VM_WQ0 F_ E VM_Q [] VM_WQ[:0] L [0] VM_WQ[:0] VM_WQ F_Q_WP0 F_ K0 H VM_Q VM_WQ F_Q_WP0 F_ VM_Q VM_WQ F_Q_WP F_ K 0 J VM_Q VM_WQ F_Q_WP F_ F VM_Q VM_WQ F_Q_WP F_ J0 E0 N VM_Q VM_WQ F_Q_WP F_ 0 VM_Q VM_WQ F_Q_WP F_ H0 E VM_Q VM_WQ F_Q_WP F_ E VM_Q VM_WQ F_Q_WP F_ H E J VM_Q VM_WQ F_Q_WP F_ VM_Q VM_WQ F_Q_WP F_ H J VM_Q0 VM_WQ F_Q_WP F_ VM_Q0 VM_WQ F_Q_WP F_0 H VM_Q VM_WQ F_Q_WP F_0 VM_Q F_Q_WP F_ H VM_Q F_Q_WP F_ VM_Q F_ J VM_Q F_ VM_Q VM_RQ0 F_ L VM_Q VM_RQ0 F_ VM_Q [] VM_RQ[:0] L [0] VM_RQ[:0] VM_RQ F_Q_RN0 F_ M VM_Q VM_RQ F_Q_RN0 F_ VM_Q VM_RQ F_Q_RN F_ M 0 H VM_Q VM_RQ F_Q_RN F_ VM_Q VM_RQ F_Q_RN F_ F N VM_Q VM_RQ F_Q_RN F_ VM_Q VM_RQ F_Q_RN F_ E E VM_Q VM_RQ F_Q_RN F_ VM_Q VM_RQ F_Q_RN F_ F F J VM_Q VM_RQ F_Q_RN F_ VM_Q VM_RQ F_Q_RN F_ E J VM_Q0 VM_RQ F_Q_RN F_ VM_Q0 VM_RQ F_Q_RN F_0 E VM_Q VM_RQ F_Q_RN F_0 VM_Q F_Q_RN F_ E VM_Q F_Q_RN F_ VM_Q F_ VM_Q F_ VM_Q F_ F_.V_FX FVQ_.V_FX J FVQ_0 FVQ_ J VM_LK0 FVQ_ VM_LK0 [] VM_LK0 FVQ_ F_LK0 T J0 VM_LK0 [0] VM_LK0# VM_LK0# [] VM_LK0# FVQ_ F_LK0_N T FVQ_ F_LK0 E J VM_LK0# [0] VM_LK FVQ_ F_LK0_N VM_LK [] VM_LK FVQ_ F_LK J VM_LK [0] VM_LK# VM_LK# [] VM_LK# FVQ_ F_LK_N 0 FVQ_ F_LK J FVQ_ F_LK_N VM_LK# [0] FVQ_ mils width E J.U/.V_ FVQ_ E.U/.V_ FVQ_ J J F_EU.V_FX F_EU R *0K/F_ FVQ_ (F_EU) F_EU0 T0 R *0K/F_ FVQ_ N 0 U/.V_ F_EU.V_FX F_EU FVQ_0 (N) F_EU T R *0K/F_ FVQ_ (F_EU) F_EU0 P R *0K/F_ 0 U/.V_ E F_VREF 0.U/0V_ FVQ_ F_VREF_N J (N) F_EU TP FVQ_ R FVQ_0 FVQ_ mils width T 0.U/0V_ FVQ_ F_L_P_VQ R 0./F_ 0.U/0V_ FVQ_ U F_LLV FVQ_ F_LLV L PY00T-0Y-N_ FVQ_ F_L_P_VQ K.0V_FX U R *0_/ 0.U/0V_ F_L_PU_N FVQ_ (N) F_LLV F R *0_/ FVQ_ (N) F_L_P_VQ K V R0 0./F_ 0.U/0V_ FVQ_ (N) F_LLV J R *0_/ 0 0U/.V_ FVQ_ F_L_PU_N L V R *0_/ 0.U/0V_ H U/.V_ FVQ_ (N) F_L_PU_N L 0.U/0V_ FVQ_ V J F_PLLV FVQ_ F_PLLV F 0.U/0V_ FVQ_ W 0.U/0V_ J F_L_TERM_N FVQ_ (N) F_PLLV E R *0_/ 0 0.U/0V_ FVQ_ Y R 0./F_ F_L_TERM_N M (N) F_PLLV J R *0_/ 0.U/0V_ FVQ_ R *0_/ (N) F_L_TERM_N M Nx NP J0NP0T0 Nx 0/ for NE 0/ for NE NP J0NP0T0 / short / short R 0K/F_ R 0K/F_ R 0K/F_ R 0K/F_ R 0K/F_ R 0K/F_ R 0K/F_ R0 0K/F_ R0 0K/F_ R 0K/F_ VM_Q[:0] [] VM_Q[:0] [0].V_FX.V_FX.V_FX [,,,].0V_FX [,0,,].V_FX ize ocument Number Rev ate: Monday, November, 00 heet of 0