BAD50_HC DIS/UMA/Muxless Schematics Document IVY/SNB Bridge Panther Point

Transcription

1 0_H I/UM/Muxless chematics ocument IVY/N ridge Panther Point :None Installed I:I installed I_Muxless :OTH I or Muxless installed I_PX:OTH I or PX installed :I or PX or Muxless installed. Muxless: Muxless installed.(px.0) PX:MUX installed.(px.0) PX_Muxless:OTH PX or Muxless installed. UM:UM installed UM_Muxless:OTH UM or Muxless installed UM_PX_Muxless:UM or PX or Muxless installed NNIE: ONLY FOR NNIE solution. PL: K PL circuit for 0mW solution installed. 0mW: External circuit for 0mW solution installed. W: for W adaptor installed. 90W: for 90W adaptor installed. <ore esign> bios.ru over Page Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev 0-H - ate: Friday, March 0, 0 heet of 09

2 uttom ocking VG/HMI(VI)/P HP OUT/PIF/MI IN/LINE IN/ U.0/U.0/ JK/ LN/ERIL PORT/PRLLEL PORT HMI ep L RT WITH P MUX 9 TV0EQTR WITH 9 WITH 9 PIVEPZLE PIVEPZLE Right ide: U x MUX PIVEP 0 ##OnMainoard VRM G/G/M HP MI IN H PEKER,9,90,9 U HRGER U x 0 MER 9 FingerPrinter 9 mart ard Internal digital MI MHz R 900MHz U.0 x U.0 x U.0 x U.0 x ep Nvidia NP -G/GLP isplay Port X0 0-H lock iagram (iscrete/um/co-lay).,,, iscreet/um/px o-lay H OE RG RT 9 LV(single hannel) H PIe x (iscrete only) PI Flash ROM0 FIxx (UM only) QM/HM PI Flash ROM M+M 0 Intel PU,,,,,9,0,,, MIx Intel PH Panther Point 0 U.0 ports U.0 ports ETHERNET (0/00/000Mb) High efinition udio T G ports () T G ports () PIE ports () LP I/F PI.0a,,9,0,,,,,, LP us Mus LP debug port K Fan NUVOTON NPE Mus Touch P IVY/N ridge 9 Thermal Int. NTW K ENE P9 9 RIII 00 hannel RIII 00 hannel G sensor MHz 9. KHz U.0 x T.0 x T.0 x T.0 x TPM/TM RIII 00 RIII 00 PIE x PIE x U x PIE x PIE x Project ode: 9.UP0.00 Project Name: 0_H P No: P Version: - lot 0 Express ard intel 9 ardreader RT09 0 Mini-ard PIE x,u.0 x H O mt lot Mini-ard 0.a/b/g M G Right ide: U x non vpro vpro U.0 x WITH MHz /MM+/M/ M Pro/x IM RJ ONN 9 TI HRGER Q0 INPUT OUTPUT T+ IL9HRTZ ~ INPUT TOUT YTEM / TP TOUT V_UX_ V_UX_ V_HRGER V_ PU / V_ VG VTMFQX 0V_0 V_PWR VG_ORE P LYER 0 YTEM / RT9GQW INPUT OUTPUT OUTPUT INPUT OUTPUT TOUT YTEM / TP 0V_LN YTEM / RT0LGQW INPUT V_HRGER 9 OUTPUT witches INPUT OUTPUT V_ V_VG_0 V_0 V_ORE GFX / IL9HRTZ INPUT OUTPUT INPUT OUTPUT +V_GFXORE V_ 0V_0 YTEM / PW INPUT OUTPUT INPUT OUTPUT INPUT OUTPUT TOUT TOUT witches TOUT V_ V_0 V_ V_VG_0 L:Top L:Power L:GN L:ignal L:ignal L:GN L:ignal L:ottom <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. bios.ru lock iagram ize ocument Number Rev ustom 0-H - Friday, March 0, 0 ate: heet of 09

3 PH trapping Name PKR INIT_V# GNT#/GPIO GNT#/GPIO GNT#/GPIO hief River chematic hecklist Rev. hief River chematic hecklist Rev. E chematics Notes Reversal INTVRMEN F_TV TGP/ GPIO9 TGP/ GPIO TGP/ GPIO V_0.V V_0.V H_O H_YN GPIO WVRMEN Reboot option at power-up efault Mode: Internal weak Pull-down. No Reboot Mode with TO isabled: If the signal is sampled high. Weak internal pull-up. This signal should not be pulled low. This ignal has a weak internal pull-up. Note: the internal pull-up is disabled after PLTRT# deasserts. This signal has a weak internal pull-down. NOTE: The internal pull-down is disabled after PLTRT# deasserts. NOTE: This signal should not be pulled high when strap is sampled. This signal has a weak internal pull-down. NOTE: The internal pull-down is disabled after PLTRT# deasserts. NOTE: This signal should not be pulled high when strap is sampled. Weak internal pull-down. This signal has a 0k internal pull down resistor. On ie PLL VR is supplied by. V from VVRM when sampled high,. V from VVRM when sampled low. Needs to be pulled High for hief River platform. If strap is sampled high, the Integrated eep / Well (W) On-ie VR mode is enabled. If not used,.-kω to 0-kΩ pull-up to +V. power-rail. GPIO signal also needs to be pulled up to.v_u with.k resistor to ensure proper strap setting when use as the chipset test interface. GPIO9/ LP_LN# GNT[:0]# functionality is not available on Mobile. Used as GPIO only. Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc_ power rail. Integrated.0 V VRM Enable / isable. Integrated.0 V VRMs is enabled when high. NOTE: This signal should always be pulled high. External.0 V VRM Enable / isable. Integrated.0 V VRMs is enabled when Low. NOTE: This signal should be pulled down to GN through 0 kohms resistor. This signal has a weak internal pull-down. NOTE: strong pull-up may be needed for GPIO functionality. L T When ''- LV is detected; When '0'- LV is not detected. This signal has a weak internal pull-down VO_TRLT P_TRLT When ''- Port is detected; When '0'- Port is not detected P_TRLT This signal has a weak internal pull-down GPIO PIE Routing LNE LNE LNE strap for selecting MI and FI termination voltage. F_TV needs to be pulled up to VccFTERM power rail through. kohms ±% resistor. If Intel LN is implemented on the platform, LP_LN# must be used to control the power to the PHY LN. If integrated Intel LN is not supported on the platform, GPIO9 can be used as a normal GPIO. ard Reader LNE Mini ard(wln) Pair evice P HMI level shifter 0x9 & 0X9 ML_LK/ML_T X NTW 0x9 or 0x99 ML_LK/ML_T <ore esign> LNE X 0 H Mini ard (WWN) E Mus M_LK/M_T NT0Y-0 0x0 M_LK/M_T M-T 9 U port(et ),on M/ NT0Y- 0x M_LK/M_T Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, LNE Intel GE LN PH Mus LNE LNE X Mini ard(wwn) bios.ru New ard X T Table N/ N/ O ET T U Table Pair 0 0 U port (usb charger) smart card G ard Mini ard (WLN) New ard evice U port U port ock X Fingerprint MER Processor trapping Pin Name trap escription onfiguration (efault value for each bit is unless specified otherwise) FG[0] FG[] FG[] FG[:] FG[:] POWER PLNE V_0 V_0 0V_VTT 0V_0 0V_0 V_ORE V_GFXORE V_VG_0 V_VG_0 V_VG_0 0V_VG_0 V_UX_ V_ R_VREF_ T+ TOUT V_ V_HRGER V_UX_ V_ V_UX_ V_LN_ V_UX_K V_UX_ O-IMM O-IMM Intel LN 9 G-ensor MINI WWN INTEL LN9 PIe tatic x Lane Numbering isplay Port Presence strap PI-Express Port ifurcation traps configuration lands. test point may be placed on the board for these lands. VOLTGE V.V.0V V 0.V 0.V to.v 0. to.v.v.v.v.0v V.V 0.V V-9.V V-9.V V V V.V.V.V.V.V Mus REE I / Mus ddresses evice E Mus attery 0 HRGER P(HMI witch) (ottom ock) U.0 redriver P0 (ottom ock) E Mus attery PH iscrete VG Thermal onnect a series kohms resistor on the critical FG[0] trace in a manner which does not introduce any stubs to FG[0] trace. : Normal Operation; Lane # definition matches socket pin map definition 0:Lane Reversed : isabled - No Physical isplay Port attached to Embedded isplayport. 0: Enabled - n external isplay Port device is connectd to the EMEE display Port 00 = x, x PI Express 0 = reserved 0 = x PI Express = x PI Express Voltage Rails TIVE IN 0 ll states WOL_EN W, x G, x ddress 0x 0x 0x9E 0x0 0x 0x9 & 0x9 0x9 or 0x9E HIEF RIVER OR ERIPTION PU ore Rail Graphics ore Rail rick Mode only Legacy WOL ON for supporting eep leep states Powered by Li oin ell in G and +VLW in x us T_L/T_ T_L/T_ T_L/T_ T_L/T_ ML_LK/ML_T ML_LK/ML_T ML_LK/ML_T PH_MT/PH_MLK PH_MT/PH_MLK PH_MT/PH_MLK PH_MT/PH_MLK PH_MT/PH_MLK PH_MT/PH_MLK efault Value Taipei Hsien, Taiwan, R.O.. Table of ontent ize ocument Number Rev 0-H - ate: Friday, March 0, 0 heet of 09

4 I = PU ignal Routing Guideline: PEG_IOMPO keep W/=/ mils and routing length less than 00 mils. PEG_IOMPI & PEG_ROMPO keep W/=/ mils and routing length less than 00 mils. FI_LYN0 FI_FYN0 FI_FYN FI_LYN FI_INT Note: Intel MI supports both Lane Reversal and polarity inversion but only at PH side. This is enabled via a soft strap. Note: Intel FI supports both Lane Reversal and polarity inversion but only at PH side. This is enabled via a soft strap. Note: Lane reversal does not apply to FI sideband signals. bios.ru 0V_VTT ignal Routing Guideline: EP_IOMPO keep W/=/ mils and routing length less than 00 mils. EP_OMPIO keep W/=/ mils and routing length less than 00 mils. NOTE. Processor strap FG[] should be pulled low to enable Embedded isplayport. tuff to disable internal graphics function for power saving. R0 KRJ--GP I RN0 RNKJ--GP I 9 MI_TXN[:0] 9 MI_TXP[:0] 9 MI_RXN[:0] 9 MI_RXP[:0] 9 FI_TXN[:0] 9 FI_TXP[:0] MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP FI_TXN0 FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXP0 FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP 9 FI_FYN0 9 FI_FYN 9 FI_INT 0 ep_uxp_pu 0 ep_uxn_pu 9 FI_LYN0 9 FI_LYN R0 9RF-L-GP 0 ep_txp0_pu 0 ep_txp_pu 0 ep_txn0_pu 0 ep_txn_pu P_OMP ep_hp IVY-RIGE MI_RX#0 MI_RX# MI_RX# MI_RX# MI_RX0 MI_RX MI_RX MI_RX G MI_TX#0 E MI_TX# F MI_TX# MI_TX# G MI_TX0 MI_TX F0 MI_TX MI_TX FI0_TX#0 H9 FI0_TX# E9 FI0_TX# F FI0_TX# FI_TX#0 0 FI_TX# FI_TX# E FI_TX# FI0_TX0 G9 FI0_TX E0 FI0_TX G FI0_TX 0 FI_TX0 9 FI_TX 9 FI_TX F FI_TX J FI0_FYN J FI_FYN H0 PU FI_INT J9 FI0_LYN H FI_LYN EP_OMPIO EP_IOMPO EP_HP EP_UX EP_UX# EP_TX0 F EP_TX EP_TX G EP_TX EP_TX#0 E EP_TX# EP_TX# F EP_TX# MI Intel(R) FI ep NOTE: elect a Fast FET similar to N00E whose rise/ fall time is less than ns. If HP on ep interface is disabled, connect it to PU VIO via a 0-kΩ pull-up resistor on the motherboard. PI EXPRE* - GRPHI OF 9 PEG_IOMPI J PEG_IOMPO J PEG_ROMPO H PEG_RX#0 K PEG_RX# M PEG_RX# L PEG_RX# J PEG_RX# J PEG_RX# H PEG_RX# H PEG_RX# G PEG_RX# G0 PEG_RX#9 F PEG_RX#0 E PEG_RX# E PEG_RX# PEG_RX# PEG_RX# PEG_RX# 0 ep_hp_r PEG_RX0 J PEG_RX L PEG_RX K PEG_RX H PEG_RX H PEG_RX G PEG_RX G PEG_RX F PEG_RX F0 PEG_RX9 E PEG_RX0 E PEG_RX F PEG_RX PEG_RX E PEG_RX PEG_RX PEG_TX#0 M9 PEG_TX# M PEG_TX# M PEG_TX# L PEG_TX# L9 PEG_TX# K PEG_TX# K PEG_TX# J0 PEG_TX# J PEG_TX#9 H9 PEG_TX#0 G PEG_TX# E9 PEG_TX# F PEG_TX# PEG_TX# F PEG_TX# E.00. PEG_TX0 M PEG_TX M PEG_TX M0 PEG_TX L PEG_TX L PEG_TX K0 PEG_TX K PEG_TX J9 PEG_TX J PEG_TX9 H PEG_TX0 G PEG_TX E PEG_TX F PEG_TX PEG_TX E PEG_TX PEG_IROMP_R PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN0 PEG_RXN9 PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN0 PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP0 PEG_RXP9 PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP0 PEG TXN PEG TXN PEG TXN PEG TXN PEG TXN PEG TXN0 PEG TXN9 PEG TXN PEG TXN PEG TXN PEG TXN PEG TXN PEG TXN PEG TXN PEG TXN PEG TXN0 PEG TXP PEG TXP PEG TXP PEG TXP PEG TXP PEG TXP0 PEG TXP9 PEG TXP PEG TXP PEG TXP PEG TXP PEG TXP PEG TXP PEG TXP PEG TXP PEG TXP0 NOTE: elect a Fast FET similar to N00E whose rise/ fall time is less than ns. If HP on ep interface is disabled, connect it to PU VIO via a 0-kΩ pull-up resistor on the motherboard. N00K--GP UM_PX_EP R0 00KRJ--GP R0 9RF-L-GP 0V_VTT PEG_RXN[0..] PEG_RXP[0..] NOTE. If PEG is not implemented, the RX&TX pairs can be left as No onnect PEG tatic Lane Reversal 0 U0VKX-GP 0 U0VKX-GP 0 U0VKX-GP 0 U0VKX-GP 0 U0VKX-GP 0 U0VKX-GP 0 U0VKX-GP 0 U0VKX-GP 09 U0VKX-GP 0 U0VKX-GP U0VKX-GP U0VKX-GP U0VKX-GP U0VKX-GP U0VKX-GP U0VKX-GP U0VKX-GP U0VKX-GP 9 U0VKX-GP 0 U0VKX-GP U0VKX-GP U0VKX-GP U0VKX-GP U0VKX-GP U0VKX-GP U0VKX-GP U0VKX-GP U0VKX-GP 9 U0VKX-GP 0 U0VKX-GP U0VKX-GP U0VKX-GP G Q0 全全 MUX 000 V. UM_PX_EP.N0.J 0V_VTT R0 0KRJ--GP ep_hp 09 UM_PX_EP <ore esign> PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN0 PEG_TXN9 PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN0 PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP0 PEG_TXP9 PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP0 PEG_TXN[0..] PEG_TXP[0..] Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PU (PIE/MI/FI) ize ocument Number Rev 0-H - ate: Thursday, March 9, 0 heet of 09

5 I = PU 0V_VTT H_PROHOT# R0 RJ-GP 0 P0VJN-GP H_N_IV# JE0 modify TERR# this signal should have an exposed test point for JE0 modify easy debug access. PU PRO_ELET# N KTO# L TERR# IVY-RIGE MI LOK OF 9 LK LK# PLL_REF_LK PLL_REF_LK# LK_EXP_P 0 LK_EXP_N 0 LK_P_P_R 0 LK_P_N_R 0 LK_P_N_R LK_P_P_R isabling Guidelines: If motherboard only supports external graphics: onnect PLL_REF_LK on Processor to GN through K +/- % resistor. onnect PLL_REF_LK# on Processor to VP through K +/- % resistorpower (~ mw) may be wasted. RN0 0V_VTT I.0.0L RNKJ--GP 0: pf@r pf@eklt, H_PROHOT#,,9 H_PUPWRG 9, PM_RM_PWRG VPWRGOO, H_PEI R H_PROHOT#_R RJ--GP onnect E to PROHOT# through inverting O buffer. PROHOT# with Two VR topology: Requires a series-resistor of 00 ±% close to the processor followed by a ±% pull-up to VTT power-rail towards the VR. pull up to VP(.0 V) hrough 00 ±% resistor close to the IMVP, H_THERMTRIP# 9 H_PM_YN R0 0KRJ--GP R0 0RJ--GP UF_PU_RT# N L N M P V R PEI PROHOT# THERMTRIP# PM_YN UNOREPWRGOO M_RMPWROK REET# THERML PWR MNGEMENT R MI JTG & PM M_RMRT# M_ROMP0 M_ROMP M_ROMP PR# PREQ# TK TM TRT# TI TO R# PM#0 PM# PM# PM# PM# PM# PM# PM# R K M_ROMP_0 M_ROMP_ M_ROMP_ JE0 modify XP_TRT# XP_TO XP_REET# JE0 modify M_RMRT# ignal Routing Guideline: M_ROMP keep routing length less than 00 mils. P9 P R R P0 R P L T R9 R0 T0 P R T R R0 K99RF-L-GP R0 0RF-GP R0 RF-GP R0 00RF-L-GP XP_TO XP_TRT# RN0 RNJ-GP 0V_VTT,,,,,,,,,,,9,0 PLT_RT# XP_REET# V_0 RN0 RNKJ--GP UF_PU_RT# PH Reset# output levels are 0 V and. V, processor Reset input levels are 0 V and.0 V..00. <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PU (THERML/LOK/PM ) ize ocument Number Rev ustom 0-H - ate: aturday, March 0, 0 heet of 09 bios.ru

6 I = PU PU OF 9 PU OF 9 IVY-RIGE M Q[:0] _K0 M IM0_LK_R0 M Q[:0] M Q0 _LK#0 M IM0_LK_R#0 M Q[:0] M Q _Q0 _KE0 V9 M IM0_KE0 M Q _Q M Q _Q M Q _Q M Q _Q _K M IM0_LK_R M Q _Q _LK# M IM0_LK_R# M Q _Q _KE V0 M IM0_KE M Q _Q F0 M Q9 _Q F M Q0 _Q9 G0 M Q _Q0 _K G9 M Q _Q _LK# F9 M Q _Q _KE W9 F M Q _Q G M Q _Q G M Q _Q K M Q _Q _K K M Q _Q _LK# K M Q9 _Q _KE W0 J M Q0 _Q9 J M Q _Q0 J M Q _Q J M Q _Q _#0 K M IM0_#0 K M Q _Q _# L M IM0_# M M Q _Q _# G N0 M Q _Q _# H N M Q _Q N M Q _Q M0 M Q9 _Q M9 M Q0 _Q9 _OT0 H M IM0_OT0 N9 M Q _Q0 _OT G M IM0_OT M M Q _Q _OT G G M Q _Q _OT H G M Q _Q K M Q _Q K M Q _Q H M Q#[:0] M Q _Q H M Q#0 M Q _Q _Q#0 J M Q# M Q9 _Q _Q# G J M Q# M Q0 _Q9 _Q# J J M Q# M Q _Q0 _Q# M K M Q# M Q _Q _Q# L J9 M Q# M Q _Q _Q# M K9 M Q# M Q _Q _Q# R H M Q# M Q _Q _Q# M H9 M Q _Q L9 M Q _Q L M Q _Q P M Q[:0] M Q9 _Q N M Q0 M Q0 _Q9 _Q0 L M Q M Q _Q0 _Q F M M Q M Q _Q _Q K M M Q M Q _Q _Q N L M Q M Q _Q _Q L P M Q M Q _Q _Q M9 N M Q M Q _Q _Q R J M Q M Q _Q _Q M H M Q _Q L M Q9 _Q K M Q0 _Q9 L M Q _Q0 M 0 M [:0] K M Q _Q _M0 0 J M M Q _Q _M W H M Q _M W M M W M M V M M V M M W M 0 E0 M 0 _M W M F0 M _M V M V M 9 M9 W M 0 _M0 M M V M M W M # E M # _M F M R# 9 M R# _M V M WE# F9 M WE# _M V R YTEM MEMORY M Q[:0] M 0 M M M # M R# M WE# M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q G F F G G F F G J J K0 K9 J9 J0 K K M N N N M N M M M M R P N N N P P N9 T T P N R R R9 J T T9 H R J H T N R T T N R T 9 R 0 9 _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q9 _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q9 _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q9 _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q9 _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q9 _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q9 _Q0 _Q _Q _Q _0 _# _R# _WE# IVY-RIGE R YTEM MEMORY _K0 _LK#0 _KE0 _K _LK# _KE _K _LK# _KE _K _LK# _KE _#0 _# _# _# _OT0 _OT _OT _OT _Q#0 _Q# _Q# _Q# _Q# _Q# _Q# _Q# _Q0 _Q _Q _Q _Q _Q _Q _Q _M0 _M _M _M _M _M _M _M _M _M9 _M0 _M _M _M _M _M E R9 E R0 T9 T0 E E E E M Q#0 F M Q# K M Q# N M Q# N M Q# P9 M Q# K M Q# P M Q# G J M N P K P T R T T T T R T R R T 0 R R M Q0 M Q M Q M Q M Q M Q M Q M Q M 0 M M M M M M M M M 9 M 0 M M M M M M IM0_LK_R0 M IM0_LK_R#0 M IM0_KE0 M IM0_LK_R M IM0_LK_R# M IM0_KE M IM0_#0 M IM0_# M IM0_OT0 M IM0_OT M Q#[:0] M Q[:0] M [:0] bios.ru <ore esign> PU (R) Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev 0-H - ate: Friday, March 0, 0 heet of 09

7 FG FG UM_PX_EP I = PU R0 KRJ--GP R0 KRJ--GP PUE OF 9 IVY-RIGE PEG tatic Lane Reversal FG : Normal Operation; Lane # definition matches socket pin map definition 0:Lane Reversed PIE Port ifurcation traps TP-OP-GPTP0 TP0 TP-OP-GPTP0 TP0 TP-OP-GPTP0 TP0 9/ FG0 FG FG FG FG FG FG FG K K9 L L K L9 L0 M M M0 M M N N N M K N9 FG0 FG FG FG FG FG FG FG FG FG9 FG0 FG FG FG FG FG FG FG FG V_IE_ENE _IE_ENE RV#L RV#G RV#E RV#K RV#W RV#T RV#M RV#J H H L G E K W T M J FG[:] : x - evice functions and disabled 0: x, x - evice function enabled ; function disabled 0: Reserved - (evice function disabled ; function enabled) 00: x,x,x - evice functions and enabled J H J H VXG_VL_ENE XG_VL_ENE V_VL_ENE _VL_ENE RV#T RV#J RV#H RV#G T J H G PEG EFER TRINING : PEG Train immediately following xxreet de assertion FG 0: PEG Wait for IO for training FG FG R0 KRJ--GP R0 KRJ--GP FG R0 KRJ--GP J F F F G G E RV#J RV#F RV#F RV#F RV# RV#G RV#G RV#E RV# RV#0 RV# RV#0 RV#9 RV#0 RV# RV#0 RV#9 REERVE RV_NTF#R RV_NTF#T RV_NTF#T RV_NTF#P RV_NTF#R RV_NTF# RV_NTF# RV_NTF# RV_NTF# RV_NTF# RV#J RV#K R T T P R J K J0 RV#J0 RV# LK_ITP LK_ITP# N M J RV#J RV_NTF#T RV_NTF#T RV_NTF#R T T R.00. bios.ru <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PU (REERVE) ize ocument Number Rev 0-H - ate: Friday, March 0, 0 heet of 09

8 I = PU PROEOR ORE POWER V_ORE 0V_VTT 0V_VTT to PU 0RF--GP PR0 PU VR_VI_LERT# R0,R0 close to PU R0 00RF-L-GP-U VENE ENE R0 00RF-L-GP-U <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. V_ORE G V G V VIO H G V VIO H0 G V VIO G0 G V VIO 0 G0 V VIO Y0 G9 V VIO U0 G V VIO P0 G V9 VIO L0 G V0 VIO9 J F V VIO0 J F V VIO J F V VIO J F V VIO H F V VIO H F0 V VIO H F9 V VIO G F V VIO G No-stuff sites outside the socket may be removed. F V9 VIO G No-stuff sites inside the socket cavity need to remain. F V0 VIO9 F V VIO0 F V VIO F V VIO F V VIO E 0V_VTT V VIO E 0 V 9 V VIO E V VIO V9 VIO V0 VIO V VIO9 V VIO0 V VIO V VIO V VIO 0 V VIO 9 V VIO V VIO V9 VIO V0 VIO V VIO9 V V VIO0 J V V 0 V 9 V V V9 V0 Y V close Y V Y V Y V H_PU_VIT R0 Y V Y0 V Y9 V Y V Y V9 Y V0 V V V V VILERT# J9 H_PU_VILRT# R0 RJ-GP V V VILK J0 H_PU_VILK V V VIOUT J H_PU_VIT V V V0 V V9 V V V V V9 V V0 U V U V U V U V U V U0 V U9 V U V U V9 U V0 R V V_ORE R V R V R V R V R0 V R9 V R V R V9 V_ENE J R V90 _ENE J P V9 P V9 P V9 P V9 VIO_ENE 0 VIO_ENE P V9 _ENE_VIO 0 IO_ENE P0 V9 P9 V9 P V9 P V99 P V00 bios.ru V Output ecoupling Recommendation: x 0 uf at ottom ocket Edge x uf at Top ocket avity x uf at Top ocket Edge x uf at ottom ocket avity PUF POWER IVY-RIGE OF 9 VIO Output ecoupling Recommendation: x 0 uf ( x 0 uf for 0 capable designs) x uf & x 00 no-stuff at ottom x uf & x 00 no-stuff at Top PU (V_ORE) ize ocument Number Rev ustom 0-H - ate: aturday, March 0, 0 heet of 09 ENE LINE VI ORE UPPLY 0UVMX-GP 0UVMX-GP 0UVMX-GP 0UVMX-GP 0UVMX-GP 0UVMX-GP 0UVMX-GP 0UVMX-GP 0UVMX-GP 0UVMX-GP 0UVMX-GP 0UVMX-GP 0UVMX-GP 0UVMX-GP 0UVMX-GP 0UVMX-GP 0UVMX-GP 0UVMX-GP 9 0UVMX-GP 0 0UVMX-GP 0UVMX-GP 0UVMX-GP 0UVMX-GP 0 0UVMX-GP 9 0UVMX-GP 0UVMX-GP 0UVMX-GP 0UVMX-GP PEG N R 0 0UVMX-GP 0 0UVMX-GP 0 0UVMX-GP 0 0UVMX-GP 0UVMX-GP 0 0UVMX-GP 0 0UVMX-GP 0 0UVMX-GP 09 0UVMX-GP 0 0UVMX-GP 0UVMX-GP 9 0UVMX-GP 0 0UVMX-GP 0UVMX-GP.00.

9 I = PU V_GFXORE V_0 isabling Guidelines for External Graphics esigns: an connect to GN if motherboard only supports external graphics and if GFX VR is not stuffed. an be left floating (Gfx VR keeps VXG rail from floating) if the VR is stuffed 0UVMX-GP VXG Output ecoupling Recommendation: x 0 uf at ottom ocket Edge x uf at Top ocket avity x uf at Top ocket Edge x uf at ottom ocket avity x uf at ottom ocket Edge 0UVMX-GP 90 UM_PX_Muxless UM_PX_Muxless UM_PX_Muxless UM_PX_Muxless UM_PX_Muxless UM_PX_Muxless 0UVMX-GP UVMX-GP 0UVMX-GP UVMX-GP 9 0UVMX-GP 90 0UVMX-GP PROEOR VPLL: U0VKX-GP 0UVMX-GP 90 UM_PX_Muxless UM_PX_Muxless UM_PX_Muxless UM_PX_Muxless UM_PX_Muxless UM_PX_Muxless 0UVMX-GP 9 0UVMX-GP 99 0UVMX-GP 90 T T T T0 T T R R R R0 R R P P P P0 P P N N N N0 N N M M M M0 M M L L L L0 L L K K K K0 K K J J J J0 J J H H H H0 H H PUG VXG VXG VXG VXG VXG VXG VXG VXG VXG9 VXG0 VXG VXG VXG VXG VXG VXG VXG VXG VXG9 VXG0 VXG VXG VXG VXG VXG VXG VXG VXG VXG9 VXG0 VXG VXG VXG VXG VXG VXG VXG VXG VXG9 VXG0 VXG VXG VXG VXG VXG VXG VXG VXG VXG9 VXG0 VXG VXG VXG VXG VPLL VPLL VPLL.00. GRPHI.V RIL POWER IVY-RIGE ENE LINE RIL R -.V RIL VREF MI OF 9 VXG_ENE XG_ENE M_VREF _IMM_VREFQ _IMM_VREFQ VQ VQ VQ VQ VQ VQ VQ VQ VQ9 VQ0 VQ VQ VQ VQ VQ V V V V V V V V V_ENE V_VI0 V_VI VIO_EL K K PROEOR V: V_ENE V_VI0 V_VI H_N_IV#_PWRTRL R90,R90 close to PU V_XG_ENE _XG_ENE Refer to the latest Huron River Mainstream PG (oc# ) for more details on power reduction implementation. +V_M_VREF_NT should have 0 mil trace width L F F F Y Y Y U U U P P P M M L J J J H H H 9.0V PIn 9 H 0UVMX-GP 909 0UVMX-GP 9 +V_M_VREF_NT hief River PROEOR VQ: 0 0UVMX-GP 90 0UVMX-GP 9 0UVMX-GP 9 0UVMX-GP 9 0V_0 V_ENE V_ V_GFXORE UM_PX_Muxless V_XG_ENE _XG_ENE V_0 V_VI0 V_VI M_VREF_Q_IMM0_ M_VREF_Q_IMM_ VQ Output ecoupling Recommendation: x 0 uf x 0 uf V Output ecoupling Recommendation: x 0 uf x 0 uf at ottom ocket avity x 0 uf at ottom ocket Edge R90 R90 need be close to pin H. 00RF-L-GP-U 0UVMX-GP R9 00KRJ--GP 9 9/9 EL IV 0UVMX-GP 9 R90 00RF-L-GP-U R90 00RF-L-GP-U UM_PX_Muxless 9/0 00-->00 RN90 RNKJ--GP 0V_VTT R90 0KRJ--GP R9 0KRJ--GP 0V_VTT R9 0KRJ--GP R9 0KRJ--GP V_VI0 V_VI VPLL Output ecoupling Recommendation: x 0 uf x uf x 0 uf V L V_GFXORE R90 0RJ-0-U-GP I R90 0RJ-0-U-GP I R90 0RJ-0-U-GP I R90 0RJ-0-U-GP I bios.ru <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PU (V_GFXORE) ize ocument Number Rev ustom 0-H - Thursday, March 9, 0 ate: heet of 9 09

10 I = PU PUH OF 9 PUI 9 OF 9 T T T9 T T T T9 T T T0 T T T R R R9 R R R0 R R R P P P P P P9 P P P0 P P P N0 N N N N9 N N N0 N N M9 M M M9 M M M0 M M M M M L L L L L L9 L L L0 L L L K K0 K K K K9 K K K0 K K J IVY-RIGE J J9 J J J0 J J J J J H H H H0 H9 H H H H9 H H H G9 G G F F F F E E E E E E0 E9 E E E E Y9 Y Y Y Y Y W W W W W W0 W9 W W W U9 U U U U U T T T T T T0 T9 T T T P9 P P P P P N N N N N N0 N9 N N N M L L0 L L9 L L L L L L L K K K9 K J J H H0 H H H H H H H0 H9 H H H H H H H H G G G9 G G G0 G G F F F IVY-RIGE F F9 E0 E E E E E E E0 E9 E E E E E E E E bios.ru <ore esign> PU () Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev 0-H - ate: Friday, March 0, 0 heet 0 of 09

11 JE0 delete XP function bios.ru <ore esign> XP Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev 0-H - ate: Friday, March 0, 0 heet of 09

12 (lanking) <ore esign> bios.ru Reserved Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev 0-H - ate: Friday, March 0, 0 heet of 09

13 (lanking) <ore esign> bios.ru Reserved Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev 0-H - ate: Friday, March 0, 0 heet of 09

14 I = MEMORY R_VREF_ U0VKX-GP 0V_0 9 UVKX-GP M R0 0RJ-0-U-GP M_VREF_Q_IMM0 Place these caps close to VTT and VTT. bios.ru, 9/9 EL IV add M M M 0 M M Q[:0] M IM0_OT0 M IM0_OT R_RMRT# M [:0] R_WR_VREF0_ Tracew should be at least 0 mils wide U0VKX-GP 0 UVKX-GP UVKX-GP R0 0RJ-0-U-GP UVKX-GP 0UVKX-GP M Q#[:0] M Q[:0] M 0 M M M M M M M M M 9 M 0 M M M M M M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M Q0 M Q M Q M Q M Q M Q M Q M Q R_VREF_ M_VREF_Q_IMM0 0V_0 H =mm M 0 9 0/P / 0 Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q Q0# Q# Q# Q# Q# Q# Q# Q# Q0 Q Q Q Q Q Q Q OT0 OT VREF_ VREF_Q REET# VTT VTT R-0P--GP.00.F NP NP R# WE# # 0# # KE0 KE K0 K0# K K# M0 M M M M M M M L EVENT# NP NP VP 99 0 N# N# N#/TET 9 0 V V V V V V V 9 V 9 V 99 V 00 V 0 V 0 V V V V V V N =.00.M V_ M R# M WE# M # M IM0_#0 M IM0_# M IM0_KE0 M IM0_KE M IM0_LK_R0 M IM0_LK_R#0 M IM0_LK_R M IM0_LK_R# PH_MT,0,,9 PH_MLK,0,,9 T#_IMM0_ U0VKX-GP 0 Layout Note: Place these aps near O-IMM. V_0 V_ 0 0UVKX-GP U0VKX-GP OIMM EOUPLING 0 0UVKX-GP U0VKX-GP 0 0U0VZY-GP <ore esign> Thermal EVENT T#_IMM0_ 0 0UVKX-GP 0 0UVKX-GP 0 0U0VZY-GP Note: If 0 IM0 = 0, _IM0 = 0 O-IMM P ddress is 0x0 O-IMM T ddress is 0x0 If 0 IM0 =, _IM0 = 0 O-IMM P ddress is 0x O-IMM T ddress is 0x V_0 R0 0KRJ--GP 09 0UVKX-GP Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. R-OIMM ize ocument Number Rev ustom 0-H - Thursday, March 9, 0 ate: heet of UVKX-GP

15 I = MEMORY M_VREF_Q_IMM M NP 0 M [:0] M Q[:0] M Q#[:0] M Q[:0] M 0 M M M M M M M M M 9 M 0 M M M M M M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M Q0 M Q M Q M Q M Q M Q M Q M Q Note: O-IMM P ddress is 0x O-IMM T ddress is 0x O-IMM is placed farther from the Processor than O-IMM V_ Layout Note: Place these aps near O-IMM. R_VREF_ U0VKX-GP 0V_0 UVKX-GP OIMM EOUPLING 0 0U0VZY-GP U0VKX-GP 0 0U0VZY-GP 9/9 EL IV add M_VREF_Q_IMM M Place these caps close to VTT and VTT. 9 UVKX-GP 0 0UVKX-GP M R0 0RJ-0-U-GP 0 UVKX-GP U0VKX-GP 0 0UVKX-GP U0VKX-GP UVKX-GP 0 0UVKX-GP 0 0U0VZY-GP 09 0UVKX-GP 0 0UVKX-GP R0 R_WR_VREF0_ 0RJ-0-U-GP V_0 0 U0VKX-GP M Q0 M Q M Q M Q 9 0 M Q#0 M Q0 M Q M Q M Q 9 M Q M Q 0 M Q9 M Q M Q M Q# M Q 9 0 M Q0 R_RMRT#, M Q M Q M Q M Q 9 M Q 0 M Q0 M Q M Q# M Q 9 M Q 0 M Q M Q9 M Q M Q M Q M Q 9 M Q9 0 M Q# M Q M Q M Q 9 M Q0 0 M Q V_ V_ M IM0_KE0 M IM0_KE 9 M M 0 M M M 9 M M M 9 M 9 90 M 9 9 M M 9 9 M 9 9 M 99 9 M 0 M IM0_LK_R M IM0_LK_R#0 0 0 M IM0_LK_R 0 0 M IM0_LK_R# M M 0 M 0 M R# M WE# M # M IM0_#0 M M IM0_OT0 9 M IM0_# 0 M IM0_OT R_VREF_ M Q 9 M Q 0 M Q M Q M Q# M Q 9 M Q 0 M Q M Q M Q9 M Q0 M Q M Q 9 M Q 0 M Q# M Q M Q M Q 9 M Q 0 M Q M Q M Q9 M Q M Q M Q# 9 M Q 0 M Q0 M Q M Q M Q 9 M Q 0 M Q0 M Q M Q M Q# 9 M Q M Q 9 90 M Q9 9 9 M Q 9 9 M Q T#_IMM0 IM 0 00 PH_MT,0,,9 R0 0V_0 0 0 PH_MLK,0,,9 0KRJ--GP 0 0V_0 NP 0 R-0P--GP.00.F0 N =.00.M bios.ru <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. R-OIMM ize ocument Number Rev 0-H - Thursday, March 9, 0 ate: heet of 09

16 (lanking) <ore esign> bios.ru Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. R-OIMM ize ocument Number Rev 0-H - ate: Friday, March 0, 0 heet of 09

17 V_0 UM_PX_Muxless RN0 RNKJ--GP RN0 RN00KJ--GP UM_PX_Muxless L_TRL_LK L_TRL_T L_KLT_EN LV_V_EN L T(PGE): This signal is on the LV interface. This signal needs to be left N if ep is used for the local flat panel display UM_PX_Muxless Place near PH V_0 R0 KRF-GP RN0 RNKJ--GP UM_PX_Muxless 9 L_KLT_EN 9 LV_V_EN 9 L_KLT_TRL 9 LV LK_R 9 LV T_R UM_PX_Muxless 9 LV_LK# 9 LV_LK 9 LV_T0# 9 LV_T# 9 LV_T# 9 LV_T0 9 LV_T 9 LV_T 9 RT_LUE 9 RT_GREEN 9 RT_RE RN0 RN0J--GP L_TRL_LK L_TRL_T LV_IG JE0 modify LV_VREFH LV_VREFL PH J L_KLTEN M L_V_EN P L_KLTTL T0 L LK K L T T L_TRL_LK P9 L_TRL_T F LV_IG F LV_VG E LV_VREFH E LV_VREFL K9 LV_LK# K0 LV_LK N LV_T#0 M LV_T# K LV_T# J LV_T# N LV_T0 M9 LV_T K9 LV_T J LV_T F0 LV_LK# F9 LV_LK H LV_T#0 H LV_T# F9 LV_T# F LV_T# H LV_T0 H9 LV_T F LV_T F LV_T N RT_LUE P9 RT_GREEN T9 RT_RE LV igital isplay Interface OF 0 VO_TVLKINN VO_TVLKINP VO_TLLN VO_TLLP VO_INTN VO_INTP VO_TRLLK VO_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT P P M M0 P9 P0 P M9 T9 T T0 V V0 V V U U V V9 P P P P9 T Y Y9 Y Y 9 M M UM_PX_Muxless HMI P_T# P_T P_T# P_T P_T0# P_T0 P_T# P_T P_UX# P_UX P_T0# P_T0 P_T# P_T P_T# P_T P_T# P_T P_TRLLK P_TRLT V_0 lose to PH side RN0 RNKJ--GP PH_HMI_LK PH_HMI_T PH_P_HP V_0 P_T# P_T P_T# P_T P_T0# P_T0 UM_PX_Muxless P_T# KRJ--GP KRJ--GP P_T R0 R0 P_UX# P_UX P_T0# P_T0 P_T# P_T P_T# P_T P_T# P_T I Port etect:(vo_trl_ T) : Port detected 0: Port not detected P PH_P_HP 9 RT LK 9 RT T T9 M0 RT LK RT T RT P_UXN P_UXP P_HP T T H lose to PH side RT_LUE RT_GREEN RT_RE 9 RT_HYN 9 RT_VYN R0 KR--GP _IREF_R M RT_HYN M9 RT_VYN T _IREF T RT_IRTN PNTHER-GP-NF.PNTH.00U P_0N P_0P P_N P_P P_N P_P P_N P_P F E F E J G RN0 RN0F--GP UM_PX_Muxless bios.ru <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PH (LV/RT/I) ize ocument Number Rev 0-H - ate: Thursday, March 9, 0 heet of 09

18 I = PH V_0 GNT#/GPIO RN0 RNKJ--GP-U GENOR_INT 0 INT_PIRQ# 9 INT_PIRQ# INT_PIRQF# INT_PIRQE# INT_PIRQ# INT_PIRQ# INT_PIRQG# swap override trap/top-lock wap Override jumper PI_GNT# GPU_HOL_RT# OOT IO trap TGP/GPIO9 0 Low = swap override/top-lock wap Override enabled High = efault R 0KRJ--GP 9/ OOT IO Location 0 0 LP 0 Reserved Reserved PI(efault) V_0 9/ 9/ del U RERIVER U0_TXN U0_TXN U0_TXN 0 U0_TXN U0_TXP U0_TXP U0_TXP 0 U0_TXP GPU_HOL_RT# 9,9,0 GPU_ELET# 9 GPU_PWR_EN# T_O_# 9 GENOR_INT V_0 9 GPU_PWM_ELET# 0KRJ--GP R GPU_PWR_EN# R 0KRJ--GP U0_RXN U0_RXN U0_RXN 0 U0_RXN U0_RXP U0_RXP U0_RXP 0 U0_RXP U0VKX-GP 0 U0_TXN_ U0VKX-GP 0 U0_TXN_ U0VKX-GP 0 U0_TXN_ U0VKX-GP 0 U0_TXN_ U0VKX-GP 0 U0_TXP_ U0VKX-GP 0 U0_TXP_ U0VKX-GP 0 U0_TXP_ U0VKX-GP 0 U0_TXP_ V_0 R KRJ--GP INT_PIRQ# INT_PIRQ# INT_PIRQ# INT_PIRQ# R 0R00-P INT_PIRQE# INT_PIRQF# INT_PIRQG# R GENOR_INT_R 0R00-P G TP J TP H TP J TP G TP H TP H TP K TP K TP9 TP0 N0 TP H TP H TP M TP M TP Y TP K TP L TP TP9 TP0 TP M0 TP Y TP G TP E URN 0 URN E URN J URN URP E0 URP F URP G URP V UTN UTN U UTN Y0 UTN U UTP Y UTP V UTP W0 UTP K0 PIRQ# K PIRQ# H PIRQ# G PIRQ# REQ#/GPIO0 REQ#/GPIO E0 REQ#/GPIO GNT#/GPIO E GNT#/GPIO F GNT#/GPIO G PIRQE#/GPIO G0 PIRQF#/GPIO PIRQG#/GPIO PIRQH#/GPIO K0 PHE PME# RV PI U OF 0 RV Y RV V RV U RV G RV T0 RV RV U RV T RV9 T RV0 T RV Y RV T RV V RV V RV RV RV RV RV9 RV0 E RV RV F RV V RV V0 RV T RV Y RV RV T RV9 F UP0N UP0P UPN UPP UPN UPP UPN K UPP H UPN E UPP UPN UPP UPN 9 UPP 9 UPN N UPP M UPN L0 UPP K0 UP9N G0 UP9P E0 UP0N 0 UP0P 0 UPN L UPP K UPN G UPP E UPN UPP URI# URI U Ext. port (H) External debug port use on Huron river platform U_RI V_ U_PN0 U_PP0 U_PN U_PP U_PN U_PP U_PN 0 U_PP 0 0 U_PN 9 U_PP 9 U_PN U_PP U_PN U_PP U_PN9 U_PP9 U_PN0 U_PP0 U_PN U_PP U_PN 9 U_PP 9 U_PN U_PP R RF-L-GP U Table Pair U port U port (usb charger) ock X X U port(et ),on M/ Mini ard (WLN) New ard evice U port Fingerprint smart card Mini ard (WWN) G ard MER -_00 LK_PI_LP 0 LK_PI_F, LK_PI_K P0VN-GP 9/ E0 P0VN-GP E0,,,,,,,,,,,9,0 P0VN-GP R0 RJ--GP R0 RJ--GP R0 RJ--GP E0 PLT_RT# LK_PI_LP_R LK_PI_F_R LK_PI_K_R PLTRT# H9 LKOUT_PI0 H LKOUT_PI J LKOUT_PI K LKOUT_PI H0 LKOUT_PI PNTHER-GP-NF O[:0]# for evice 9 (Ports 0-) O[:]# for evice (Ports -) O0#/GPIO9 O#/GPIO0 O#/GPIO O#/GPIO O#/GPIO O#/GPIO9 O#/GPIO0 O#/GPIO K0 L U_O R0 0KRJ--GP bios.ru EMI request 0009 <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PH (PI/U/NVRM) ize ocument Number Rev 0-H - ate: aturday, March 0, 0 heet of 09

19 I = PH MI_RXN[:0] MI_RXP[:0] MI_TXN[:0] MI_TXP[:0] PH OF 0 FI_TXN[:0] FI_TXP[:0] ignal Routing Guideline: MI_ZOMP keep W= mils and routing length less than 00 mils. MI_IROMP keep W= mils and routing length less than 00 mils. R9 0KRJ--GP R90 00KRJ--GP Y_PWROK 0V_VTT RI_PY Y_PWROK 0 Modify: PWROK hange R90 to 00K 00 from 0K and default stuff. V_0 R9 0R00-P, 0_PWR_GOO Non _imt_ R90 0RJ--GP PM_MPWROK R99 0RJ--GP imt_, PM_RM_PWRG U_PWR_K,9 PM_PWRTN# _PREENT MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP R90 99RF-GP MI_OMP_R R90 0RF-GP R90 0KRJ--GP JE0 modify U_PWR_K Y_REET# PWROK For 00 0_PWR_GOO after PM_LP_# delay 00 ms PWROK TLOW# PM_RMRT# E0 G G0 E 0 J J0 W W0 V Y Y0 Y U J G H K P L L0 K E0 H0 E0 MI0RXN MIRXN MIRXN MIRXN MI0RXP MIRXP MIRXP MIRXP MI0TXN MITXN MITXN MITXN MI0TXP MITXP MITXP MITXP MI_ZOMP MI_IROMP MIRI UK# Y_REET# Y_PWROK PWROK PWROK RMPWROK RMRT# PWRTN# PREENT/GPIO TLOW#/GPIO MI ystem Power Management FI UWRN#/UPWRNK/GPIO0 FI_RXN0 FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXP0 FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_INT FI_FYN0 FI_FYN FI_LYN0 FI_LYN WVRMEN PWROK WKE# LKRUN#/GPIO U_TT#/GPIO ULK/GPIO LP_#/GPIO LP_# LP_# LP_# LP_U# PMYNH J Y E H J G0 G9 G F G E G J0 H9 W V 0 V 0 E 9 N G N 0 H F G0 G P WOVREN PH_PWROK PM_LP_# PIE_WKE#,,, PM_LKRUN#, PH_ULK_K PM_LP_#, R9 0RJ--GP LP_# R9 0RJ--GP imt_ PM_LP_U# TP90 TP-OP-GP H_PM_YN FI_TXN0 FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXP0 FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_INT FI_FYN0 FI_FYN FI_LYN0 FI_LYN R90 0R00-P R9 0KRJ--GP U_TT# TP90 TP-OP-GP For platforms not supporting eep /.VccU_ and VccW_ will rise at the same time (connected on board).pwrok and RMRT# will rise at the same time (connected on board).lp_u# and UK# are left as no connect.uwrn# used as UPWRNK/GPIO0 PM_RMRT# PM_LP_#,9,,,,, For 00 PM_LP_#, RT_UX_ WOVREN - On ie W VR Enable HIGH Enabled (EFULT) LOW isabled WOVREN R9 0KRJ-L-GP R9 0KRJ-L-GP RT_UX_ PM_RI# 0 RI# LP_LN#/GPIO9 K PM_LP_LN#,, PNTHER-GP-NF R99 KRJ--GP V_0 V_ RN90 RN0KJ--GP R9 0KRJ--GP Non_ imt_ TLOW# PM_RI# _PREENT U_PWR_K PM_LP_LN# For 00 PIE_WKE# R : K EKLT: 0K V_UX_ R909 00KRJ--GP PM_LKRUN# bios.ru R9 R90 00KRJ--GP 0KRJ--GP PM_RMRT# PIE_WKE# PWRTN# This signal has an internal pull-up resistor PM_RMRT# R : PL 0K NNIE : PL 00K R9 0KRJ--GP V_V_POK_# PM_RMRT# R9 KRJ--GP Q90 N00KW-GP.N0.F nd =.N0.FF V_V_POK RMRT#_K <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PH (M I/FI/PM) ize ocument Number Rev 0-H - ate: aturday, March 0, 0 heet 9 of 09

20 I = PH PIE_RXN PIE_RXP PIE_TXN PIE_TXP PIE_RXN PIE_RXP PIE_TXN PIE_TXP PIE_RXN PIE_RXP PIE_TXN PIE_TXP 9/ PORT-->PORT,0 PIE_RXN,0 PIE_RXP,0 PIE_TXN,0 PIE_TXP PIE_RXN PIE_RXP PIE_TXN PIE_TXP GLN LK ard Reader WLN LK U.0 LK LK_PIE_WWN# LK_PIE_WWN PIE_LK_WWN_REQ# LK_PIE_R# LK_PIE_R PIE_LK_R_REQ# LK_PIE_WLN# LK_PIE_WLN PIE_LK_WLN_REQ# 9/ LN-->WLN,0 LK_PIE_INTEL_LN#,0 LK_PIE_INTEL_LN INTEL LN LK / WLN-->GLN,0 PIE_LK_INTEL_LN_REQ# U0VKX-GP U0VKX-GP U0VKX-GP U0VKX-GP U0VKX-GP U0VKX-GP U0VKX-GP U0VKX-GP U0VKX-GP U0VKX-GP 0RPR-P RN0 PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ LK_PH_R_N LK_PH_R_P PIE_REQ# R0 0R00-P PIE_REQ# R09 0R00-P PIE_REQ# PIE_REQ0# LK_PH_R_N LK_PH_R_P PIE_REQ# R0 0R00-P G PERN J PERP V PETN U PETP E PERN F PERP PETN Y PETP G PERN J PERP V PETN U PETP F PERN E PERP Y PETN PETP G PERN H PERP Y PETN PETP J PERN G PERP U PETN V PETP G0 PERN J0 PERP Y0 PETN 0 PETP E PERN PERP W PETN Y PETP GLN ard Reader WLN U.0 INTEL/M LN NEW R Y0 LKOUT_PIE0N Y9 LKOUT_PIE0P J PIELKRQ0#/GPIO 9 LKOUT_PIEN LKOUT_PIEP PIE_REQ# R0 0R00-P M PIELKRQ#/GPIO 0RPR-P RN0 LK_PH_R_N LK_PH_R_P LKOUT_PIEN LKOUT_PIEP RN RN RN0 0RPR-P 0RPR-P RN0 RN RN V0 PIELKRQ#/GPIO0 LK_PH_R_N Y LK_PH_R_P LKOUT_PIEN Y LKOUT_PIEP PIELKRQ#/GPIO Y LKOUT_PIEN Y LKOUT_PIEP L PIELKRQ#/GPIO V LKOUT_PIEN V LKOUT_PIEP L PH PIELKRQ#/GPIO PI-E* LOK MU ontroller MLERT#/GPIO MLK MT ML0LERT#/GPIO0 ML0LK ML0T MLLERT#/PHHOT#/GPIO Link OF 0 MLLK/GPIO MLT/GPIO L_LK L_T L_RT# PEG LKRQ#/GPIO LKOUT_PEG N LKOUT_PEG P LKOUT_MI_N LKOUT_MI_P LKOUT_P_N LKOUT_P_P LKIN_MI_N LKIN_MI_P LKIN_GN_N LKIN_GN_P LKIN_OT_9N LKIN_OT_9P LKIN_T_N LKIN_T_P REFLKIN LKIN_PILOOPK E H 9 G E M M T P0 PH_GPIO M0 PEG_LKREQ#_R F E J0 G0 G E K K K H RN00 LK_UF_EXP_N LK_UF_EXP_P LK_UF_PYLK_N LK_UF_PYLK_P LK_UF_OT9_N LK_UF_OT9_P LK_UF_K_N LK_UF_K_P LK_UF_REF L_LK L_T L_RT# E_WI# M_LK, M_T, RMRT_NTRL_PH ML0_LK 0 ML0_T 0 ML_LK ML_T LKOUT_PEG N LKOUT_PEG P RN0 RN0J--GP V U M LKOUT_P_N M LKOUT_P_P R00 0RJ--GP RN 0RPR-P RN00 RN0KJ--GP LK_PI_F PEG_LKREQ#_R LK_P_N_R LK_P_P_R M_T M_LK PEG_LKREQ# LK_PIE_VG# LK_PIE_VG LK_EXP_N LK_EXP_P V_0 R00 0KRJ--GP V_0 Q00 N00KW-GP.N0.F nd =.N0.FF R00 0KRJ--GP V_0 0KRJ--GP 0KRJ--GP R0 XTL_IN XTL_OUT UM_Muxless R00 I_PX RN00 RNKJ--GP V_0 M_LK M_T ML0_T ML0_LK ML_LK ML_T PH_GPIO PIE_REQ0# R009 RMRT_NTRL_PH KRJ--GP R00 and 00 O-LY 0KRJ--GP R00 MRJ-GP GPU_PRNT# PH_MT,,,9 PH_MLK,,,9 9/0 X00 XTL-MHZ-9-GP.000. nd =.000.I0 00 P0VJN-GP R0 I_UM 0KRJ--GP R0 PX_Muxless UM_I# 00 P0VJN-GP V_ RN00 RNKJ--GP RN00 RNKJ--GP RN00 RNKJ--GP RN0KJ--GP RN00 R009: K@R 0K@EKLT UM_IRETE# (UM_I#, GPU_PRNT#)=(, ) => UM (UM_I#, GPU_PRNT#)=(0, ) => I (UM_I#, GPU_PRNT#)=(0, 0) => PX (UM_I#, GPU_PRNT#)=(, 0) => Optimus(Muxless) LK_PIE_NEW# LK_PIE_NEW PIE_LK_NEW_REQ# PEG LKRQ# LK_PH_R_N LK_PH_R_P RN09 0RPR-P PIE_REQ# R00 0R00-P RN PIE_REQ# Reserved for RL 0 E V0 V T V V K K K LKOUT_PEG N LKOUT_PEG P PEG LKRQ#/GPIO LKOUT_PIEN LKOUT_PIEP PIELKRQ#/GPIO LKOUT_PIEN LKOUT_PIEP PIELKRQ#/GPIO LKOUT_ITPXP_N LKOUT_ITPXP_P FLEX LOK XTL_IN XTL_OUT XLK_ROMP LKOUTFLEX0/GPIO LKOUTFLEX/GPIO LKOUTFLEX/GPIO LKOUTFLEX/GPIO V V9 XTL_IN XTL_OUT Y XLK_ROMP 0V_VTT R00 909RF--GP K F H K9 GPU_PRNT# NEWR_PWR_EN LK_UF_REF LK_UF_K_P LK_UF_K_N RN009 RN0KJ-L-GP 0 9 LK_UF_EXP_P LK_UF_EXP_N LK_UF_OT9_N LK_UF_OT9_P need very close to PH V_ RN00 RN0KJ--GP PIE_REQ# PIE_LK_WLN_REQ# PIE_LK_INTEL_LN_REQ# PIE_REQ# RN00 RN0KJ--GP PEG LKRQ# PIE_LK_NEW_REQ# E_WI# 9/ V_0 bios.ru RN0 RN0KJ--GP PIE_LK_R_REQ# PIE_LK_WWN_REQ# 9/ PIELKRQ# and PIELKRQ# upport 0 power only PNTHER-GP-NF Prioritize ////-MHz FLEX on FLEX and FLEX o not configure ////-MHz FLEX clock on FLEX0 and FLEX if more than PI clocks + PI loopback are routed. <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PH (PI-E/MU/LOK/L) ize ocument Number Rev ustom 0-H - ate: Thursday, March 9, 0 heet 0 of 09

21 I = PH P0VN-GP 0 9 H_OE_YN 9 H_OE_OUT 9 H_OE_RT# 9 H_OE_ITLK +V_+.V_H_IO +V_+.V_H_IO H_YN V_0 H_OE_YN R0 0MRJ-L-GP X0 X-KHZ-GPU.000. nd =.000. R0 KRJ--GP PLL OVR VOLTGE Low =.V (efault) High =.V bios.ru RT_X RT_X H_OUT H_YN H_YN_R RT_UX_ EIKO suggest modify to P EPON suggest modify to P H_OUT H_PKR H_YN H_OUT H_RT# H_ITLK Flash escriptor ecurity Overide Low = efault High = Enable No Reboot trap This signal has a weak internal pull down. On ie PLL VR is supplied by.v when sampled high,. V when sampled low. Needs to be pulled High for Huron River platform. co-operate with R0 G R0 KRJ--GP Q0 N00K--GP.N0.J 0 P0VN-GP R RJ--GP R RJ--GP RN0 RNJ--GP-U Low = efault High = No Reboot R RJ--GP H_YN R 0KRF-L-GP R0 0KRF-L-GP 0 PI_LK_R ME_UNLOK 0 0 RT_UX_ INTVRMEN- Integrated U.0V VRM Enable High - Enable internal VRs Low - Enable external VRs 0 PI_0#_R 0 PI_#_R 0 PI_I_R 0 PI_O_R E0 0 PI_LK_ PI_I_ PI_O_ RT Reset 9 H_PKR 9 H_IN0 R0 KRJ--GP /9 RT_X RT_X RT_RT# RT_RT# M_INTRUER# PH_INTVRMEN H_ITLK H_YN H_RT# H_OUT MRTR_ET PH_JTG_TK_UF JE0 modify R09 PH_PI_0# 0RJ--GP R PH_PI_# 0RJ--GP / R0 UL ROM H_YN: This strap is sampled on rising edge of RMRT# and is used to sample.v VccVRM supply mode. K external pull-up resistor is required on this signal on the board. ignal may have leakage paths via powered off devices (udio odec) and hence contend with the external pull-up. blocking FET is recommended in such a case to isolate H_YN from the udio odec device until after the trap sampling is complete. UVKX-GP 0 P0VN-GP UVKX-GP 0 G0 GP-OPEN MRJ-GP R0 R0 0KRF-L-GP UL ROM 0RJ--GP R0 UL ROM 0RJ--GP R UL ROM 0RJ--GP Q0 N00K--GP.N0.J G K N L T0 K E G N J H K H T Y T V U G PH R RT_RT#_ RTX RTX RTRT# RTRT# INTRUER# INTVRMEN H_LK H_YN PKR H_RT# H_IN0 H_IN H_IN H_IN H_O H_OK_EN#/GPIO H_OK_RT#/GPIO JTG_TK JTG_TM JTG_TI JTG_TO PI_LK PI_0# PI_# PI_MOI PI_MIO PNTHER-GP-NF KRJ--GP RT IH JTG PI PH_JTG_TK_UF R 00KRJ--GP MRTR_ET RTRT_ON /0 RT Reset T LP T G OF 0 FWH0/L0 FWH/L FWH/L FWH/L FWH/LFRME# LRQ0# E LRQ#/GPIO K ERIRQ TLE# T0RXN M T0RXP M T0TXN P T0TXP P TRXN M0 TRXP M TTXN P TTXP P0 TRXN TRXP TTXN H TTXP H TRXN TRXP 0 TTXN F TTXP F TRXN Y TRXP Y TTXN TTXP TRXN Y TRXP Y TTXN TTXP TIOMPO TIOMPI TROMPO TOMPI TRI T0GP/GPIO TGP/GPIO9 V Y Y0 H P V P R KRJ--GP LP_0 LP_ LP_ LP_ V_0 T_ET#0 T_OMP R KRJ--GP R KRJ--GP LP_[0..] LP_FRME#,, INT_ERIRQ, T_RXN0 T_RXP0 T_TXN0 T_TXP0 T_RXN T_RXP T_TXN T_TXP T_RXN T_RXP T_TXN T_TXP T_RXN T_RXP T_TXN T_TXP PW_LR# H->mart ard <ore esign> T_LE# L->Non mart ard LP_[0..],, H M-T O ET R RF-GP T_OMP R 99RF-GP RI_T R 0RF-GP T_LE# INT_ERIRQ T_ET#0 0V_VTT 0V_VTT RN0 RN0KJ--GP V_0 Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PH (PI/RT/LP/T/IH) ize ocument Number Rev 0-H - ate: aturday, March 0, 0 heet of 09

22 V_ V_0 PH_GPIO GPU_HP_INTR# E_I# PH_TEMP_LERT# MFG_MOE _GPIO U_PWR_ON LN_I# PH_GPIO H_RIN# H_0GTE RN0KJ--GP GPIO has a weak[0k] internal pull up. To enable on-die PLL Voltage regurator, should not place external pull down. R0 0KRJ--GP Reserved for RL INTERNL GFX EXTERNL GFX R0 0K R0 00K EP#_LV R0 00KRJ--GP RN0 H LV L ep RN0 RN0KJ--GP RN0 V_0 RN0KJ--GP V_ RN0 9/ RN0KJ--GP R0 KRJ--GP T_O_PRNT# V_0 V_0 Note: For PH debug with XP, need to NO TUFF R PW_LR# JE0 delete FP function PassWord lear et_et# R09 0KRJ--GP ET R0 00KRF-L-GP R 0KRJ--GP NON_ET I = PH E_VP_MI# 0 E_I# Reserved for RL LN_I# 9,9 GPU_PWROK 00 delete TP0, TP0 G0 GP-OPEN TP-OP-GPTP0 TP0 9 TP-OP-GPTP TP TP-OP-GPTP0 TP0 TP-OP-GPTP0 TP0 TP-OP-GPTP0 TP0 TP-OP-GPTP0 TP0 TP-OP-GPTP09 TP09 _GPIO EP#_LV GPU_HP_INTR# I_EN# PH_GPIO T_O_PRNT# PH_GPIO PH_GPIO PH_GPIO PLL_OVR_EN MI_OVRVLTG FI_OVRVLTG MFG_MOE PH_TEMP_LERT# PH_NTF_ PH_NTF_ PH_NTF_ PH_NTF_ 9/ 9/ et_et# U_PWR_ON T H E 0 G U 0 T E E P K K V M N M V V 9 E E9 F F9 PHF MUY#/GPIO0 TH/GPIO TH/GPIO TH/GPIO GPIO LN_PHY_PWR_TRL/GPIO GPIO TGP/GPIO TH0/GPIO LOK/GPIO GPIO GPIO GPIO TP_PI#/GPIO GPIO TGP/GPIO TGP/GPIO LO/GPIO TOUT0/GPIO9 TOUT/GPIO TGP/GPIO9/TEMP_LERT# GPIO _NTF_# _NTF_# _NTF_# _NTF_# _NTF_# _NTF_# _NTF_# _NTF_# _NTF_9# _NTF_0#9 _NTF_#E _NTF_#E9 _NTF_#F _NTF_#F9 GPIO NTF NTF TET PIN:,,,,,,,,,9,E,E9,F,F9, G,G,H,H,J,J, J,J,J,J,,,, 9,E,E9,F,F9 PU/MI OF 0 TH/GPIO TH/GPIO9 TH/GPIO0 TH/GPIO 0GTE PEI RIN# PROPWRG THRMTRIP# INIT_V# F_TV T_ T_ T_ T_ N NTF_#G _NTF_#G _NTF_#H _NTF_#H _NTF_9#J _NTF_0#J _NTF_#J _NTF_#J _NTF_#J _NTF_#J _NTF_# _NTF_# _NTF_# _NTF_#9 _NTF_9#E _NTF_0#E9 _NTF_#F _NTF_#F9 0 VRM_IZE 0 P U P Y Y0 T Y H K H0 K0 P G G H H J J J J J J 9 E E9 F F9 VRM_IZE H_PEI_R PH_THERMTRIP_R NV_LE FI_OVRVLTG T_O_PWRGT UM_I# 0 MI_OVRVLTG H_0GTE R0 0RJ--GP R0 0KRJ--GP R0 0KRJ--GP H_RIN# H_PUPWRG,,9 GPIO (FI_OVRVLTG) GPIO (MI_OVRVLTG) H_PEI, HR:P NV_LE FI TERMINTION VOLTGE OVERRIE MI TERMINTION VOLTGE OVERRIE V_0 H_N_IV# 0V_VTT LOW - Tx, Rx terminated to same voltage ( oupling Model EFULT) Integrated lock Enable functionality is achieved via soft-strap. The default is integrated clock enable. Integrated lock hip Enable R KRJ--GP RN0 RNJ--GP PH_THERMTRIP_R H_THERMTRIP#, R0 公公 check different, 90RJ--GP check need modify or not 9/ check list 90 check intel, R0 eries-resistor of 90 ±% T ignal isable Guideline: T_, T_, T_ and T_ should not float on the motherboard. They should be tied to GN directly. LOW - Tx, Rx terminated to same voltage ( oupling Model EFULT) R KRJ--GP V_0 VRM Frequency PH_GPIO= : 00MHZ PH_GPIO=0 : 900MHZ R 0KRJ--GP UM_VRM00MHZ PH_GPIO bios.ru R9 0KRJ--GP VRM900MHZ VRM ize V_0 G 0KRJ--GP G_M 0KRJ--GP R R 0KRJ--GP 0KRJ--GP R G R G_M VRM_IZE VRM_IZE V_ 0KRJ--GP R 0909 I_EN# R KRJ--GP PNTHER-GP-NF PLL ON IE VR ENLE NOTE:This signal has a weak internal pull-up 0K ENLE -- HIGH (R UNTUFFE) EFULT ILE -- LOW (R TUFFE) PLL_OVR_EN R KRJ--GP I_EN# HIGH (R )- ILE [EFULT] LOW (R)- ENLE GPIO has a weak[0k] internal pull up. Integrated lock Enable functionality is achieved via soft-strap. The default is integrated clock enable. <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PH (GPIO/PU) ize ocument Number Rev 0-H - ate: aturday, March 0, 0 heet of 09

23 I = PH V_0 V_0 0V_VTT (ufx) (0uFx_00) 0V_VTT 0.9(Totally current of VVRM) R R 0UVKX-GP VVRM. V_0 0V_VTT.9(Total current of VIO) 0 UVKX-GP (uf x) 0. (Totally V_ current) 0RJ-0-U-GP 0RJ-0-U-GP 0 (0.uF x) UVKX-GP UVKX-GP (Totally current of VMI) UVKX-GP UVKX-GP U0VKX-GP 0 0 UVKX-GP UVKX-GP 0 VVRM 0V_VTT 0 JE0 modify 09 JE0 modify VORE VORE VORE VORE F VORE F VORE G VORE G VORE G VORE9 G VORE0 G VORE G9 VORE J VORE J VORE J VORE J9 VORE J VORE N9 J N N N N N P P P P T N N H9 P VIO VPLLEXP VIO VIO VIO VIO VIO9 VIO0 VIO VIO VIO VIO VIO VIO V VVRM G VFIPLL 00 check VFIPLL 0V_VTT P VIO U0 PHG VMI PNTHER-GP-NF POWER V ORE VIO FI.PNTH.00U RT LV FT / PI MI HVMO OF 0 V VLV LV VTX_LV VTX_LV VTX_LV VTX_LV V V VVRM VMI VLKMI VFTERM VFTERM VFTERM VFTERM VPI U U K K M M P P V V T T0 G G J J U0VKX-GP V +V +V_V_LV +.V_VTX_LV VVRM +.0V_V_MI_I (0.uF/0.0uF x) (0uF x_00) UM_PX_Muxless 0UVKX-GP I R0 0RJ--GP 0.0 V_0 0V_VTT 0V_VTT V_0 V_ V_0 V_0 V_0 UM_PX_Muxless UM_PX_Muxless UM_PX_Muxless R09 (0.0uF x) I 0RJ--GP (uf x) UVKX-GP 0 UVKX-GP 0UVKX-GP 0.0 0UVKX-GP (0.uFx) U0VKX-GP UM_PX_Muxless U0VKX-GP JE0 modify 0.9 0UVKX-GP 9 U0VKX-GP UVKX-GP 0UVKX-GP 0.0 (ufx) 0.00 UVKX--GP (uf x) L0 IN-0UH--GP.000.0Y nd = JE0 modify R0 0RJ--GP I R V 0 0RJ--GP UM_PX_Muxless R0 0RJ-0-U-GP UM_PX_Muxless R0 0RJ--GP (ufx) (0uFx) V_0 U0VKX-GP U0 for NNIE flicker issue R for don't flicker solution.v RT LO U0 IN GN EN OUT N# MEEEV0Z-GP.0.F N =.0.0F UVKX-GP V 0 0UVMX-GP bios.ru <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PH (POWER) ize ocument Number Rev 0-H - ate: Thursday, March 9, 0 heet of 09

24 I = PH 0V_VTT bios.ru 0.0 (ufx) (0uFx) (0uFx) (ufx) +.0V_V PL IN-0UH--GP L Y 09 nd = UVKX-GP 0.0 (ufx) (0uFx) +.0V_V PL IN-0UH--GP L Y 0 nd = UVKX-GP U0VKX-GP 0V_M (ufx) UVKX-GP 0V_VTT V_0 0V_VTT V_ (0.uFx) 0V_M +VRTEXT (0.uFx) 0.0 0V_VTT (0.uFx) (.ufx_00) UVKX-GP RT_UX_ u (0.uFx) (ufx) 0 0 0UVKX-GP 0UVKX-GP JE0 modify 0/ R 0RJ--GP (Total current of VW) 0V_VTT (ufx_00) (ufx) 0. (Totally current of VVRM 0 UVKX-GP VVRM TP +.0V_V PL +.0V_V PL UVKX-GP JE0 modify (ufx) 0.09 UVKX-GP JE0 modify (ufx) U0VKX-GP 0 UVKX-GP UVKX-GP PHJ TP-OP-GP VK 9 VLK U0VKX-GP 9 T V T L W W W W W9 W W N Y9 F PUYP 0 TP9 TP-OP-GP U0VKX-GP VPLLMI H VPLLMI 0V_VTT (0uFx) L9 VIO 0 UVKX-GP 0 UVKX-GP VW VW VW VW VW VW VW VW9 VW0 VW VW VPLL F VIO F VIFFLKN F VIFFLKN G VIFFLKN G VW PRT VVRM VPLL +T V PT (0.uFx) U0VKX-GP T 0V_M_PU PU V9 PU J VW_ V PU VW VW VW VW VW VW VW9 VW0 V_PRO_IO VRT PNTHER-GP-NF POWER lock and Miscellaneous PU RT.PNTH.00U T PI/GPIO/LP U MI H 0 OF 0 VIO9 VIO0 VIO VIO VIO VU VU VU 9 VU 0 VU VIO VREF_U PU VU VREF VU VU VU VU V V V V VIO VIO VIO VIO VPLLT VVRM VIO VIO VIO VW VW VW VUH N P P T V_ V_ T9 V_ 0.09 (Totally current of VU_) T (0.uFx) T V V P T 0V_VTT M +V_PH_VREFU N N P N0 N P0 P TP TP-OP-GP PU V_ +V_PH_VREF 0V_M T V T9 P V_ JE0 modify (ufx) JE0 modify 0/ 0V_VTT JE0 modify (ufx) +V_+.V_H_IO <ore esign> (0.uFx).R00.F 0 nd =.R00.F HH-0--GP V_ (0.uFx) U0VKX-GP U0VKX-GP K V_0 V_0 V_0 R W 909RF-GP (0.uFx) T V_ V_ 0 U0VKX-GP U0VKX-GP R0 V_0 0RF-GP J (0.uFx) F 9 U0VKX-GP V_ U0 V_ H 0V_VTT H (ufx) VIN VOUT GN EN N# 0 F UVKX-GP G9090-0TU-GP K VPLLT TP-OP-GP TP F F VVRM U0VKX-GP UVKX-GP UVKX-GP 0V_VTT (ufx) UVKX-GP U0VKX-GP 0.00 U0VZY-GP K 0 HH-0--GP R0 (ufx) 0RJ--GP U0VKX-GP +V_+.V_H_IO R09 0RJ-0-U-GP R0 0RJ--GP (0.uFx) R 0RJ-0-U-GP R 0RJ-0-U-GP V_ V_0 V_ Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PH (POWER) ize ocument Number Rev 0-H - ate: Thursday, March 9, 0 heet of 09 U0VZY-GP 0UVKX-GP

25 I = PH PHI 9 OF 0 bios.ru PHH H E E F0 F F F9 F 9 F 0 F F9 F F F F F F F 9 F 0 G9 G G G H H H H9 H0 9 H 0 H H J9 J J J J K K 9 PNTHER-GP-NF OF K K K K K L L L9 L L L L L L L L L M M M M9 M M M M N N9 N N P P9 P P0 P P P P P P R R T T T T T T T0 T T T9 T T T U U0 V V0 V V0 V V V V W W W W W W W W W W0 W V Y Y Y Y 9 Y 0 Y Y F E 9 E 9 E0 9 F0 99 F 00 F 0 F0 0 F 0 F 0 F 0 F 0 0 F0 0 F 09 F0 0 F G G G G G H H H 9 H9 0 H0 H H H H H9 H H E E G G0 G G G G 9 H 0 H H H H H0 H H F PNTHER-GP-NF H K K K9 K K L L L0 L L L L M P M M M M0 M M M M M M M N P0 N P P T P0 P P P R R T T T T W T T T V V V V V9 V V V9 V V W W9 W W W Y Y Y Y Y Y G9 N J E0 G G H T G G P M P P E G J <ore esign> PH () Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev 0-H - ate: Friday, March 0, 0 heet of 09

26 <ore esign> bios.ru lock(colay) Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev 0-H - ate: Friday, March 0, 0 heet of 09

27 E V_UX_K 9/ 9/ 0 0 U0VKX-GP 0 U0VKX-GP GPUHOT _IN# dgpu_lrm 0 0 LI_LOE# TP-OP-GP _I 0RT rest 9 T_EL_/# TP-OP-GP TP0 9 U_PWR_K 0 IN# V_HRGER_EN _OFF,9,0 _ENLE HMI_IN 9 T IN# 9 9, 9 HMI_VI_IN RMRT#_K PM_LP_# ME_UNLOK T IN# 9,, PM_LP_LN# 9, 0_PWR_GOO 0 PI_WP#,0 U_PWR_EN# 9 _PREENT RTRT_ON P_VER_ T_TYPE O_EN K_GPIO 9 R0 9 0R00-P MOEL_I 0 E_GPIO 9 9 RT_UX K E_ENLE VKUP 9 0 E_GPIO9 0 K_VORF V_UX_ V_ I = K V_UX_K P VERION /(PIN9) PULL-LOW REITOR PULL-HIGH REITOR VOLTGE RN RNKJ--GP 00.0K 0.0K.0V R V_0 KRJ--GP R 00.0K 0.0K.V 00.0K.0K.V 0 Modify: ML_LK_ Move R to closed V_UX_K power K.0K.V rail base on layout placement. P_VER_ 0 R -M 00.0K.9K.0V U0VKX-GP 00P0VKX-GP N00KW-GP R.N0.F K..V 00KRF-L-GP K 00.0K.V 0P0VKX-GP ML_T_ U0 OF V_HRGER Vad=.*(R/(R+R)) 0 U0VKX-GP 0 U0VKX-GP 00 Modify: RN0 pull-low 0K Resistor to on LUETOOTH_EN. 0 U0VKX-GP 0 00P0VKX-GP TP-OP-GPTP TP TP0 09 U0VKX-GP U0VKX-GP 0 U0VKX-GP 9/ VREF GPIO90/0 GPIO9/ GPIO9/ GPIO9/ GPIO9/0 GPIO9/ GPIO9/ GPIO GPIO/ GPIO/ GPIO/ PL_IN#_GPIO GPIO/ GPIO GPIO GPIO0 GPIO/IRRXL GPIO GPIO GPIO/TK GPIO/TM GPIO/TI GPIO/IRRXM/TRT# GPIO PL_IN_GPIO0 PL_OUT_GPIO VKUP GPIO GPO/HM GPIO GPIO GPO/IOX_LH/TET# GPIO/IOX_LK/XORTR# GPIO9 VORF V 9 V V V V V 0 V LREET# LLK LFRME# L L L L0 ERIRQ GPIO/LKRUN# 9 GPIO/MI# 9 EI#/GPIO GPIO0/LPP# GPIO/PWUREQ# GPIO/G0 KRT#/GPIO GPIO/PT/R# GPIO0/PLK/TO GPIO/PT 0 GPIO/PLK GPIO/PT GPIO/PLK GPIO/L GPIO/ GPIO/L GPIO/ GPIO/L GPIO/ GPIO/L GPIO/ F_0# F_K F_I/F_IO F_IO/F_IO LP_ LP_ LP_ LP_0 EI#_K / NT0Y_WKE# ML_LK_ ML_T_ M_LK M_T PROHOT_E EWI#_K INT_ERIRQ, PM_LKRUN# 9, PNEL_LEN 9 H_0GTE H_RIN# ILIM_EL TPT 9 TPLK 9 PLT_RT#,,,,,,,,,,,9,0 LK_PI_K, LP_FRME#,, LP_[0..],, _HMI_IN 0 LON_OUT 9 T_L 9,0,0 T_ 9,0,0 ML_LK_ 9,,9, ML_T_ 9,,9, _VI_IN 0 PI# 0 PILK 0 PII 0 PIO 0 / < TP F P0VN-GP 9/9 FOR RF < TTERY / HRGER <------PH / EP ILIM_EL H_PEI 0V_VTT FN_TH 9,9 PM_PWRTN# INTNT_VIEW_TN# 9,9,,,,, PM_LP_# HRGE_LE 9 K_EEP U_HRGER_TL U_HRGER_TL FN_PWM MUTE_LE TY_LE, PWRLE 9 9 MP_MUTE# PH_ULK_K, R0 0KRJ--GP,, R E_Rx E_Tx ERT# 0 RJ-GP PEI U0 OF GPIO/T KOUT0/JENK# GPIO0/T KOUT/TK GPIO/T KOUT/TM 0 GPIO0/T KOUT/TI 9 KOUT/JEN0# GPIO/_PWM KOUT/TO GPIO/_PWM KOUT/R# GPIO/_PWM KOUT GPIO/_PWM KOUT GPIO/G_PWM KOUT9/P_VI# 0 GPIO/H_PWM KOUT0/P0_LK 9 GPIO/E_PWM KOUT/P0_T GPIO0/F_PWM KOUT/GPIO KOUT/GPIO KOUT/GPIO V_POR# KOUT/GPIO/XOR_OUT GPIO0/KOUT GPIO/KOUT GPIO/IRRXM/IN_R GPIO/OUT_R/TRIT# KIN0 KIN GPIO/LKOUT/IOX_IN_IO KIN GPIO00/EXTLK KIN KIN 9 KIN 0 PEI KIN VTT KIN KOL0 KOL KOL KOL KOL KOL KOL KOL KOL KOL9 KOL0 KOL KOL KOL KOL KOL KOL KOL KROW0 KROW KROW KROW KROW KROW KROW KROW KOL[0..] 9 KOL 9 KROW[0..] 9 V_UX_ 0 TP0 TP-OP-GP Q0 E_I# V_UX_K E_WI# R 0R00-P R0 0RJ--GP 009 VKUP R EWI#_K 0RJ--GP EI#_K R9 0R00-P ML_LK 0 ML_T 0 K_PWRTN# 0 T--GP.T.P nd =.T.N G0 GP-OPEN V_UX_K V_UX_ R V_UX_ 0R00-P R0 0KRJ-L-GP E_GPIO R 0RJ--GP 0P0VKX-GP V_0 RN0 RN0KJ--GP 9/ PowermartTN# E_VP_MI# FN_TH U0VZY-GP NPE9P0X-GP-U T =.00.0G NPE GN GN GN GN GN GN 9 GN 0 NOTE: Locate resistors R9 and R close to the NPE9L. V_UX_ V_ R9 0KRJ--GP E_Rx UVKX-GP NPE9P0X-GP-U T =.00.0G V_UX_K LI_LOE# can not pull high, because push pull suggest RN0 Pin change FN_TH NOTE: onnect GN and GN planes via either 0R resistor or one point layout connection. R9 0KRJ--GP _IN# E_GPIO High ctive PROHOT_E G 00KRJ--GP RN0 RN00KJ--GP TOP_HG# R PM_LP_# 0KRF--GP R0 KRJ--GP _OFF R Q0 N00K--GP.N0.J H_PROHOT#, PowermartLE 0 _PWR_LE 0 _U_Power_EN PII RN RN00KJ--GP RMRT#_K _VI_IN _HMI_IN HMI_VI_IN _P_IN R 00KRJ--GP,, PURE_HW_HUTOWN# 00 Modify: dd Pull down 00k ohm at F_I for Power consumption concern. RN RN00KJ--GP RN RN00KJ--GP NT0Y-0 (ddr: 0x) M_T M_LK V_0 9/ V_UX_K RN0 RN0KJ--GP V_UX_ RN09 RN0KJ--GP PURE_HW_HUTOWN#_R MP_MUTE# WIRELE_W# RN0 RN0KJ--GP MUTE_TN# KUP_TN# RT_UX_ Q0 MMT90--GP nd =.090.F.T RT_UX K R 0R00-P UVKX-GP ERT# 0 Reserved _U_HRGER_EN# U_HRGER_PORT_EN# PURE_HW_HUTOWN# Reserved.9K 00.0K VP_EN_K M_T M_LK V_UX_ T_TYPE /(PIN99) PULL-LOW REITOR PULL-HIGH REITOR VOLTGE W 90W 0W 0W Prevent IO data loss N/ 00.0K 0.0K 0.0K.0K 00.0K 00.0K.V 0V 0.V 0.V 0W.0K 00.0K 0.V FTP9 U0 GN REET# V G90L9TUF-GP N/ 00.0K 00.0K.0V.V R0 00KRF-L-GP T_TYPE IRETE# R0 00KRF-L-GP 90W V_UX_K V_UX_K W UM R0 0KRF--GP R9 0KRF--GP W_90W# High: W / Low 90W IRETE# High: UM / Low: iscrete V_UX_K 0KRJ--GP R MOEL_I R 00KRF-L-GP V_UX_K 0 _PWNTN# V_UX_ R0 0KRJ-L-GP E_GPIO9 R 0RJ--GP LUETOOTH_EN 0P0VKX-GP bios.ru WLN_TET_LE LE/GP V 0 9 V_UX_K_RT# RT# V_UX_K_INT# PowermartTN# V_UX_K MUTE_TN# MUTE_TN#_R GP0 INT# 9 R0 0KRF--GP GP 0/GP HG_ON# 0 9 OE_EP_MUTE# R0 0 0R00-P GP /GP 009-9, PM_LP_#,0 _P_IN NT0Y_WKE# LE/GP LE/GP LE0/GP0 T LK GP GP GP EEP/GP /GP U0 NT0Y-GP-U NUMLOK_LE P_LE G_LE U0VKX-GP 9 U0VKX-GP V_UX_K R 0KRF--GP UVKX-GP NT0Y-0 (ddr: 0x0) _TFULL LE/GP WIRELE_W# GP0 0 TOP_HG# 9 IRETE# GP 0 GP 9,,9,0,0 _IN# K_GPIO R09 0R00-P LE/GP LE/GP LE0/GP0 T LK GP GP GP EEP/GP /GP KUP_TN# NT0Y_WKE# U0 NT0Y-GP-U V 0 9 V_UX_K_RT#_R RT# V_UX_K_INT#_R INT# V_UX_K R 0KRF--GP 0/GP /GP G_EN LUETOOTH_EN WIRELE_EN KUP_LE 0 U0VKX-GP U0VKX-GP V_UX_K R 0KRF--GP UVKX-GP T_ T_L M_LK M_T RN0 RNKJ-0-GP HG_ON# R90 0KRJ--GP LI_LOE# R 0KRJ--GP INTNT_VIEW_TN# NT0Y_WKE# RN0 RN0KJ--GP _ENLE ERT# IN# V_HRGER_EN RN0 RN0KJ--GP R 0KRJ--GP 00 Modify: RN0 pull-low 0K Resistor to on LUETOOTH_EN. <ore esign> ize ocument Number Rev ustom aturday, March 0, 0 ate: heet of 09 Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. K Nuvoton NPE 0-H -

28 I = Thermal V_0 Fan controller P9 *Layout* mil V_0 NT-00K--GP 00UVKX-GP.090.L0 rd =.090.X R0 Q0 PM90--GP 0U0VKX-GP Layout notice : oth XN and XP routing 0 mil trace width and 0 mil spacing. P00_XP 0 0P0VJN-GP P00_XN.ystem ensor, Put on palm rest 0 00P0VKX-GP LERT# V_0 THERM_Y_HN# V_0 U0 R V L + - LERT# T_RIT# GN NTW-GP R KR-GP.H/W T hutdown TM_L_ TM LERT# FN_TH check? TM_L_ TM R0 0RJ--GP 0 K HH-0GP-GP V_0 R0 0KRJ--GP.R00.JF nd =.R00.HH FN_TH_ FN_PWM K 0 HH-0GP-GP.R00.JF nd =.R00.HH V_0 FN_TH_ U0VKX-GP 09 U0VKX-GP 0U0VKX-GP E-ON-9-GP FN 0.F.00 nd = 0.F0.00 rd = 0.F9.00 R V_0 V_UX_ R09 KRF--GP,, PURE_HW_HUTOWN# 0 TPT-GP.000.T N =.T. rd =.T. 0 THERM_Y_HN# R0 0RJ--GP V_0 0KRJ--GP R U0VKX-GP G Q0 N00K--GP.N0.J IMVP_PWRG_G 0 0RJ--GP R <ore esign> IMVP_PWRG, Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Thermal NTW/Fan ize ocument Number Rev ustom 0-H - ate: Thursday, March 9, 0 heet of 09 bios.ru

29 9,,,,,,,,9,0,0 V_0 90 0UVMX-GP _IN#_OE 90 _IN# U0VKX-GP 9 MP_MUTE# PM_LP_# U0VKX-GP V_0 R90 V_0 0KRJ--GP R9 R9 0KRJ--GP U0VKX-GP V_V 9 90 W--GP.000.Q nd =.000.K 0R00-P 9 Q90 N00KW-GP.N0.F 0UVMX-GP _IN#_JT V_0 X0_MUTE# R9 0KRJ--GP 9 R9 9 0RJ--GP V_0 V_V V_0 V_0 0UVMX-GP U0VKX-GP 99 0U0VZY-GP R90 0KRJ--GP GPIO/PK_MUTE# EXT_MUTE# H_OE_ITLK H_OE_OUT H_IN0 90 U0VKX-GP R90 0RJ--GP R90 0RJ--GP H_OE_RT# 0UVMX-GP UVMX-GP 0UVMX-GP R RJ--GP 9 U0VKX-GP OE_YN U0VKX-GP LO_OUT_V U0VKX-GP OE_EP_MUTE# V_0 9 U0VKX-GP R9 UVKX-GP 9 U0VKX-GP R90 U_GN X0_RPWR X0_ITLK RJ--GP X0_T RJ--GP GPIO/PK_MUTE# _IN#_OE VEE FILT_. 9 0UVMX-GP 9 P0VJN-GP 9 0P0VJN-GP 9 0P0VJN-GP 90 X0_FLYP X0_FLYN UVKX-GP L REF 0 9 U0VKX-GP 9 U90 YN IT_LK T_OUT T_IN REET# GPIO0/EP# VEE V_HP V_IO VUX_. V_. FILT_. V_V V_.V RPWR_.0 LPWR_.0 L REF GN PIF/EEPGIN P_EEP MI_/ MI_LK0 MI_/ LEFT- LEFT+ RIGHT- GPIO/PK_MUTE# RIGHT+ GPIO/PIF EXT_MUTE# FLY_P FIY_N X0-Z-GP GP-LOE G90 9 PORT_L PORT_R PORT_L PORT_R 9 PORT_L PORT_R 0 PORT_L PORT_R PORTE_L PORTE_R PORTF_L PORTF_R _I _I ENE ENE FILT_. GP-LOE G90 U_GN UIO_P_EEP MI MI_LK_ U_PK_L- U_PK_L+ U_PK_R- U_PK_R+ EXT_MUTE# X0 L X0 R X0 L X0 R X0 L X0 R ENE_ ENE_ FILT_.V 9 _I U0VKX-GP U_GN 9 UVKX-GP UIO_P_EEP R9 R90 OK_PIF 0 R90 0R00-P R9 0R00-P R9 0R00-P R9 0R00-P 9 UVKX-GP 9 UVKX-GP 9 UVKX-GP 9 UVKX-GP R9 KRF-GP KRF-GP R9 U0VKX-GP 90 0R00-P 0R00-P UIO_EEP X0 L_ X0 R_ X0 L_ X0 R_ M_MIIN_L M_MIIN_R R9 R9 R9 R9 R9 R9 R9 0KRJ--GP MI_ MI_LK U_PK_L- U_PK_L+ U_PK_R- U_PK_R+ 9RJ-L-GP 9RJ-L-GP 00RF-L-GP-U 00RF-L-GP-U 00RF-L-GP-U 00RF-L-GP-U TGP-GP 90.R00.H K_EEP_ PKR nd =.R00.Q rd =.T.0 RN90 RN0J--GP ock 9/ RN90 ock 0R00-P R90 RNJ--GP-U 0R00-P R90 OK_LINEOUT_L 0 OK_LINEOUT_R 0 M_HP_L M_HP_R OK_MI_IN_L 0 OK_MI_IN_R 0 M_MIIN_L M_MIIN_R OK_LINEIN_L 0 OK_LINEIN_R 0 K_EEP H_PKR MI 99 00P0VJN-GP MI_LK_ 90 00P0VJN-GP EMI request 0009 V_0 V_V V_V R9 KRF-GP YN_TL R9 KRF--GP R9 KRF--GP H_OE_YN 9 P0VJN-GP N00K--GP G Q90 R9 OE_YN ENE_ R99 R99 0KRF--GP 9KRF-L-GP EXT_MI_J# ENE_PORT_ U_HP_J# ENE_PORT_ ENE_ R9 9KRF-L-GP OK_LINEIN_J# 0 <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. bios.ru 0RJ--GP udio odec ize ocument Number Rev ustom 0-H - Thursday, March 9, 0 ate: heet of 9 09

30 UIO OP MPLIFIER JE0 delete MP function <ore esign> bios.ru udio MP Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev 0-H - ate: Friday, March 0, 0 heet 0 of 09

31 V_ V_LN_ V_LN_ V_LN_ R0 0RJ-0-U-GP M M L0 V_LN_ GK00T-0Y-GP.00.0 nd =.00. M L0 GK00T-0Y-GP.00.0 nd =.00. M L0 GK00T-0Y-GP.00.0 nd =.00. M UVKX-GP M M U0VKX-GP U0VKX-GP VL_G UVKX-GP 9 UVKX-GP M PIE_PLLV M M M M GPHY_PLLV 0 UVKX-GP M M 0 M UVKX-GP 0 U0VKX-GP U0VKX-GP 0 U0VKX-GP U0VKX-GP 0 U0VKX-GP V_LN_ U0 VO V_LN_ V V VL_G VL_G VL VL_G VL 9 VL GPHY_PLLV GPHY_PLLVL PIE_PLLV PIE_PLLVL PIE_PLLVL M mm x mm -Pin QFN IVH XTLVH VH 0 VH TR_N TR_P TR_N TR_P TR_N TR_P TR0_N 9 TR0_P O#_LINKLE# P00LE# LK_P000LE# TRFFILE# IV_G XTLV_G LN_V LN_V M U0VKX-GP 0 M M LN_MIN_M 0 LN_MIP_M 0 LN_MIN_M 0 LN_MIP_M 0 LN_MIN_M 0 LN_MIP_M 0 LN_MI0N_M 0 LN_MI0P_M 0 0M/00M/G_LE#_M_ P00LE# ROM_LK LN_T_LE#_M 0 V_0 R0 L0 GK00T-0Y-GP 0RJ-0-U-GP M 0 M U0VKX-GP L0 GK00T-0Y-GP M 09 U0VKX-GP L09 GK00T-0Y-GP M U0VKX-GP M Mode ( PEE 0/00 LE MOE) 0M/00M/G_LE#_M W--GP 0 M V_LN_0 U0VKX-GP 0M/00M/G_LE#_M 0 0,0 PIE_RXP 0,0 PIE_RXN 0,0 PIE_TXP 0,0 PIE_TXN 9,,, PIE_WKE#,,,,,,,,,,,9,0 PLT_RT# 0,0 LK_PIE_INTEL_LN 0,0 LK_PIE_INTEL_LN# WP 0- RN0 M M M RN0J--GP M RN0 RN0J--GP V_LN_0 U0VKX-GP PIE_RXP_ U0VKX-GP PIE_RXN_ PIE_TXP_M PIE_TXN_M LK_PIE_M_LN LK_PIE_M_LN# 0 9 PIE_TX_P PIE_TX_N PIE_RX_P PIE_RX_N WKE# PERT# PIE_REFLK_P PIE_REFLK_N GPIO0 M_LK/TET_ M_T/TET_ #_EELK I#_EET M_LK_M R0 M_T_M R EELK EET M M 0RJ--GP 0RJ--GP V_LN_ M_LK 0, M_T 0, M R0 KRJ--GP 0M/00M/G_LE#_M_ ROM_LK EELK U0 I K REET# # O GN V WP# EET V_LN_ P0VJN--GP LN_XO_R LN_XI M X0 XTL-MHZ-0-GP M M 0,0 PIE_LK_INTEL_LN_REQ# 0RJ-0-U-GP M 0KRJ--GP R M_PRNT M M_LOW_PWR 0RJ-0-U-GP R0 R 00RF-L-GP M P0VJN--GP LN_XO_M LN_R 0 VMIN_PRNT LOW_PWR XTLO XTLI R M PIE_LK_M_LN_REQ# R0 LK_REQ# R9 KRF--GP M R_LX R_VF R_VP 0 R_V 9 THERML_P 9 V_LN R V_LN_ IN-UH-9-GP M V_LN_ M UVKX-GP L0 M U0VKX-GP M U0VKX-GP V_LN_ M 0 0UVKX-GP EET M R0 KRJ--GP T0-H-T-GP EELK M R0 KRJ--GP M U0VKX-GP Package ody <ore esign> M..00 st =..M0 Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. bios.ru M ize ocument Number Rev ustom 0-H - Thursday, March 9, 0 ate: heet of 09

32 RT9 clcok setting lock Mode 0(R) Mode (R) TP0 EEI TP-OP-GP,,,,,,,,,,,9,0 PLT_RT# 0 PIE_LK_R_REQ# R0 0R00-P PLT_RT#_R EEK EEI R 0KRJ--GP V_0 External Mhz X'tal Mhz or Mhz X sutff X stuff RT09==>PI-E Interface V_0 R 0RJ-0-U-GP V_0_R R0 KRF-GP UVZY-GP U0 R_RREF RREF V_IN LK_REQ# PERT# EEO EE EEK GPIO/EEI M_IN# 0 _# 9 P P M_IN# _# X_/_WP X_/M_LK 0 0 R0 PIE_TXN_HIP 0 PIE_TXP 0R00-P R0 0R00-P PIE_TXN_HIN 0 PIE_TXN 0 LK_PIE_R 0 LK_PIE_R# V PIE_RXP PIE_RXP 0 UVZY-GP PIE_RXN PIE_RXN 0 UVZY-GP V 9 V_R_0 R R_V 0 V_0 0R00-P R_V TP TP-OP-GP HIP HIN REFLKP REFLKN V HOP HON G GN V Output 90m R_V. V_IN Output 0m R_V P P P P0 P9 P P 0 P 9 P V_ GN _ V V R R 0R00-P X_ X_/M_ X_ X_/M_ X_/M_0 X_0 X_WP#/M_ X_LE X_LE/M R V_ 0KRJ--GP R V_ 0R00-P EMI request P0VJN-GP LK_PIE_R# E0 P0VJN-GP LK_PIE_R E0 V V U0VKX-GP UVZY-GP X_# RT09-GR-GP 0 U0VKX-GP X_# V_ GN P P P P 0 _LK _M _ 9 0 V_ UVKX-GP R _M_R _LK_R _0_R R losed to chip pin R R R R09 R0 X_WE# X_E# X_RE# X_R 0R00-P 0R00-P 0R00-P 0R00-P 0R00-P M _0 _ P0V-GP _LK 0 U0VKX-GP 0 UVZY-GP V_R_0 0 closed R Pin V_0 0 closed R Pin bios.ru 0 U0VKX-GP 0 U0VKX-GP 0 09 U0VKX-GP U0VKX-GP 0 closed to RPin 0 UVZY-GP 0UVKX-GP losed Pin <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RT09(R REER) ize ocument Number Rev 0-H - ate: Thursday, March 9, 0 heet of 09

33 E (lanking) <ore esign> F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. bios.ru ate: Friday, March 0, 0 heet of 09 E Reserved Wistron orporation ize ocument Number Rev 0-H -

34 bios.ru <ore esign> Reserved Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev 0-H - ate: Friday, March 0, 0 heet of 09

35 reserve bios.ru <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. U.0 ontroller ize ocument Number Rev - 0-H Friday, March 0, 0 ate: heet of 09

36 E Power equence, IMVP_PWRG R Y_PWROK 9 0R00-P 9,,9,,,, PM_LP_# 0 --GP.000.K N =.000.M R R : K NNIE Run Power U0 O-GP V_0.0.0 nd =.0.0 V_HRGER V_ RUN_ENLE 0 UVKX-GP R0 00KRJ--GP P_NTRL E 0U0VKX-GP G 9,,9,,,, PM_LP_# U09 G9TLU-GP.09.09P V_ /09 RUN_ENLE U0 O-GP.0.0 V_0 nd =.0.0 V_ G 9,,9,,,, PM_LP_# G Q0 N00K--GP.N0.J V_0 V_0 EN V GN HV U0 O-GP.0.0 V_0 nd =.0.0 V_ G 0U0VKX-GP,,9,,,,,,,,,,,9,0 H_PUPWRG PLT_RT# V/V_EN bios.ru 0V_VTT R0 00KRJ-L-GP R R0 H_PWRG_R KRJ--GP KRJ--GP R KRJ--GP KRF--GP R R0 0 RJ--GP U0VKX-GP 0 --GP.000.K N =.000.M MMTH-GP Q0 H_THERMTRIP#,.M.0 nd =.0.V PURE_HW_HUTOWN#,, _ENLE,9,0 9, PM_LP_# 9,, PM_LP_LN# U imt_ N00KW-GP.N0.F imt_ V_ PM_LP_#_JT V_ PM_V R PM_LP_#_JT change U, U, U to.n0.f 0 imt U R 00KRJ--GP N00KW-GP imt_ R 00KRJ--GP V_ imt R.N0.F N =.N0.FF R imt_ 0KRJ-L-GP imt_ V_ KRJ--GP imt PM_LP_LN#_JT V_M_R G 0V_M PM_V RR U N00K--GP PM_LP_LN#_JT_R R KRJ--GP 0UVKX-GP imt_.n0.j For imt nd =.000.I G Q0 MP0U--GP R imt,,, 00RJ--GP imt U0 QM00-GP.000. G imt_ RUNPWROK V_M 0V_LN 0V_M imt 0UVKX-GP imt_ U N00KW-GP imt_.n0.f V_ V_ 0V_VTT 0V_LN 0V_VTT R 00KRJ--GP RUNPWROK_JT RUNPWROK_JT_ KRF-L-GP imt_ imt_ imt_ U0VKX-GP imt_ R 0UVKX-GP 0V_LN imt_ U0 QM00-GP.000. G R imt_ 0V_LN_MO imt_ 0KRJ-L-GP U N00K--GP imt_.n0.j nd =.000.I V_ V_ 0V_LN_PWRG V_ 00KRJ--GP.M.0 nd =.0.V R 0V_M_R G R9 KRJ--GP imt_ 0V_M_ 0V_M_JT imt_ Q0 MMTH-GP G R0 0KRJ--GP imt_ Q0 N00K--GP.N0.J nd =.000.I.R00.F V imt_ Y GN nd =.R00.F R PM_LP_#_R 9, PM_LP_# K 0RJ--GP 0 HH-0--GP imt_ <ore esign> imt_ R9 0RJ--GP Non_ imt_ R0 0RJ--GP Non_ imt_ R 0RJ--GP Non _imt_ R 0RJ--GP Non_ imt_ 0V_LN 0V_M R 0RJ--GP Non _imt_ R 0RJ--GP Non_ imt_ 0V_VTT 0V_0 R 0RJ-0-U-GP R 0RJ-0-U-GP R 0RJ-0-U-GP PM_MPWROK 9 V_ V_M _NONiMT R 0RJ--GP R 0RJ--GP _NONiMT Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Power Plane Enable ize ocument Number Rev ustom 0-H - Thursday, March 9, 0 ate: heet of 09 U0 LVG0GW--GP.0G0.L0 N =.Z0.H

37 R 0RJ--GP lose to PU Power Reduction ircuit Processor VREF_Q Implementation R_VREF_ R0 0RJ--GP lose to IMM Power Reduction ircuit M_RMPWROK 0V_0 R0 RJ--GP R_WR_VREF0_ Q0 G M_VREF_Q_IMM0_ 9 RMRT_NTRL_PH 0 P_NTRL G Q0 Q0 N00K--GP.N0.J G R0 00KRJ--GP +V_M_VREF_NT 9 PM_LP_# 9,,9,,,, Q0 N00K--GP.N0.J G P_NTRL_MO N00K--GP.N0.J R 0RJ--GP 0V_EN P_NTRL Q09 N00K--GP.N0.J lose to PU Power Reduction ircuit M_RMPWROK V_ R_WR_VREF0_ G N00K--GP.N0.J M_VREF_Q_IMM_ 9 RMRT_NTRL_PH 0 0V_VTT_PWRG, V_ R09 0RJ--GP R0 KRJ--GP 9/ V_0 R KRJ--GP.V_RUN_PU_EN R KRJ--GP R 00KRJ--GP.V_RUN_PU_EN# Q0 PM90--GP.090.L0 Q0 N00K--GP.N0.J G 0V_EN_L 9,,9,,,, PM_LP_# V_0 R 0KRJ--GP R 0R00-P R 0RJ--GP R0 0R00-P 0V_EN 0 U0VKX-GP M_RMRT# 0 RMRT_NTRL_PH G Q0 0.N0.J 0UVKX--GP N00K--GP Power Reduction ircuit M_RMRT# M_RMRT#_ R 0 KRJ--GP 00P0VJN-GP R_RMRT#,,9 PM_RM_PWRG, LL_PWR_OK, 0V_VTT_PWRG R 00RF-L-GP R0 0RJ--GP V_ 0 U0VKX-GP V_ R 00RF-L-GP IN IN V GNOUT Y lose to PU Power Reduction ircuit M_RMPWROK V_ U0 VHG09FTG-GP.0G09.H V_0 VPWRGOO_R EKLT V.0: PH to K,UP to 00R R0 00RF-L-GP R9 0RF--GP R0 0RJ--GP VPWRGOO For U0 not O N gate R9 to.0.l R0 to.00.l R0 to V_ P_0_R Q0 MMTH-GP imt_ KRF-L-GP imt_ 0 U0VZY-GP 9/ E R KRJ--GP imt_.m.0 nd =.0.V P_0_R_JT 0V_VTT R V_ Q0 G N00K--GP.N0.J nd =.000.I imt_,,, RUNPWROK R 0KRJ--GP imt_ 0V_VTT_ V_ U0 V imt_ Y GN LVG0GW--GP.0G0.L0 N =.Z0.H 0V_VTT_PWRG <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PTER ize ocument Number Rev ustom 0-H - aturday, March 0, 0 ate: heet of 09 bios.ru

38 NNIE solution Pin= E-ON--GP IN NP NP _JK_IN daptor in to generate TOUT 0 _JK P00--GP-U.000.0M U0VKX-GP P0 K K 0 PMJGP-GP.PM.EG 0 PMJGP-GP P0 U0VZY--GP.PM.EG PR0 00KRF-L-GP PWR_+_ P0 U0VZY--GP PU0 G QM00-GP + PWR_JK_EN R R E _OFF NPN R/R =>K/K R R PQ0 LT0EU-F-GP PNP R/R =>K/K PQ0 PTEU--GP PR0 00KRJ--GP _OK PR09 0KRJ--GP 0 P00--GP-U _JK.000.0M bios.ru <ore esign> IN JK Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev 0-H - ate: Thursday, March 9, 0 heet of 09

39 T+ MIN TTERY ONNETOR T+ nd TTERY ONNETOR - 0 FOR RF T IN#,0,0 T_L,0,0 T_ P90 U0VKX-GP P90 00P0VKX-GP F9 00P0VKX-GP 9/9 FOR RF RN90 RNJ--GP T IN#_ T_L_ T I T 9 0 LP-ON--GP-U T IN#,,9, ML_LK_,,9, ML_T_ P90 U0VKX-GP P90 00P0VKX-GP F9 00P0VKX-GP RN90 RNJ--GP T IN#_ T_L_ T T_ 0 9 T LP-ON--GP K P90 MMPZGP-GP.R0.RF PR9 0RJ-0-U-GP N = R = K P90 MMPZGP-GP.R0.RF PR9 0RJ-0-U-GP T+ TTERY WITH P90 9/ UVKX-GP P90 T+ delete net 0- HG T+ HG + PR9 00KRJ--GP T+ V_UX_ T IN# HG I OM T_EL_/# MX_ET PR90KRF--GP MX_TOMP P9 U0VKX-GP PR909 0KRJ--GP PR9 00KRJ--GP M_EXTL MX_P PR90 0KRJ--GP MX_MINV PR90 MX_V P90 P9 UVKX-GP UVKX-GP PU90 T THM HG I OM TEL 0 ET TOMP EXTL 9 P MINV PR90 MXEUP-GP MX_P 0 P90 UVKX-GP PRE# TTT V_UX_ UVKX-GP P9 UVKX-GP T 0 THM 9 HG I OM GN V T IN# HG I OM T_TT PR9 00KRJ--GP T+ -_00 PR90 00KRJ--GP P909 U0VZY-GP daptor IN etection PR90 0KRJ--GP MX_V V_UX_ T+ OM T+ OM P9 UVKX-GP P90 0UVKX-GP G G O--GP PQ90 O--GP PQ90 G G HG_PWR HG_PWR O--GP PQ90 TOUT G G I I K P90 HG-0GP-GP bios.ru.r00.qf PR90 0KRJ--GP PR90 00KRJ--GP KRF-GP K9RF-GP MX_V M_EXTL G90 GP-LOE-PWR TOUT <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. TT_ONN ize ocument Number Rev 0-H - ate: Thursday, March 9, 0 heet 9 of 09

40 + V_UX_ + PR0 9K9RF-L-GP HG_GN PR09 0KRF--GP PR0 KRF-GP PR0 00KRJ--GP PQ00 N00--GP G _IN_ PWR_HG_OK PWR_HG_IOUT R P0 0U0VKX-GP PR0 00KRF-L-GP PU00 G R QM00-GP N =.P0. PQ00 PR00 00KRF-L-GP HG_GN,9,0 T_L,9,0 T_ HG_ON# add nd source (.P0. ) +_G_ PR0 0RF-GP PWR_HG_REGN PR00 0KRF--GP N00KW-GP.N0.F nd =.N0.FF PR0 0RF-GP PR00 0KRF-GP +_G_ V_UX_ TOP_HG PR00 00KRJ--GP PG00 PG0 V_UX_ PR0 0KRF--GP PR0 0R00-P PWR_HG_V PR0 HG_GN MRJ-GP PWR_HG_MPIN PWR_HG_ILIM PWR_HG OFF PR09 00KRJ--GP +_TO_Y MX_P 9 PG00 GP-LOE-PWR--GP P00 UVKX--GP U0VKX-GP P00 HG_GN HG_GN P00 UVKX--GP 0 0 V PR0 0KRF--GPPWR_HG_ET ET PWR_HG_T_L 9 GP-LOE-PWR--GP L PWR_HG_T_ GP-LOE-PWR--GP PR00 0RF--GP P00 UVKX-GP PWR_HG_P HG_GN V_UX_ PWR_HG_N TOUT HG_GN change to..0 PU00 MPOUT MPIN ILIM N# OK# PR009 0RJ--GP P GN QRGRR-GP N..0 GN PR00 00KRJ--GP PG00 GP-LOE-PWR--GP TT IOUT P00 U0VKX-GP REGN HIRV PHE LORV RP 9 RN PG0 GP-LOE-PWR--GP HG_GN + total power R R PR00 P00 P00 0RJ-0-U-GP 0W--GP UVKX--GP HG_TT K PWR_HG_TT PWR_HG_HIRV PWR_HG_PHE PWR_HG_LORV PWR_HG_IOUT I = harger PWR_HG_RP PWR_HG_RN KRF--GP PR0 HG_GN ( NNIE/TRO) PR0,PR0 w 0w 90w 0w PR0 0R00-P 0P0VJN-GP P0 P0 0UVKX-GP.K.k 0.k k PWR_HG_REGN PR0 0RF-L-GP PR0 RF-GP _I P0 UVKX-GP 00K 00K 00K 00K P09 UVKX-GP HG_GN HG_GN P0 UVKX-GP G P0 00P0VKX-GP G V_UX_ I-T-GE-GP PU00 I-T-GE-GP PU00 PWR_HG_OP_ ER00 R--U-GP E00 0P-GP TOUT PWR_HG_PHE_L 0UVKX-GP P00 0- EMI EMI requist TT_ENE_ PL00 0UVKX-GP P00 L-UH-GP-U 0UVKX-GP P009 00P0VKX-GP E00 PR0 0RF--GP T+_R PG00 GP-LOE-PWR--GP PG009 GP-LOE-PWR--GP UVZY-GP E00 delete net T+ P0 EUVM--GP 9..GL N = 9..FL P0 0UVKX-GP P0 add nd source ( 9..FL ) P00 U0VKX-GP PR0 KRF--GP V_UX_ bios.ru PR0 KRF--GP PWR_HG_T_L PWR_HG_T_ 0.00.wayler _IN# PWR_HG_OK PQ00 N00--GP G _IN# TOP_HG# PR0 00KRJ--GP PQ009 N00--GP G TOP_HG 9/ <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. HRGER Q ize ocument Number Rev ustom 0-H - ate: Thursday, March 9, 0 heet 0 of 09

41 G G E V/V_EN PWR_VV_ENTRIP V_HRGER_EN V_HRGER_EN_R PR 0KRJ--GP PR0 00KRJ-L-GP PWR_V_ENTRIP PR0 PWR_V_ENTRIP_R PQ0 MN0LW--GP V_PWR V_HRGER V_PWR.MN.0F PG PG0 et in 9. 9/ N =.N0.F chnge to 0k GP-LOE-PWR GP-LOE-PWR PR0 9 PG PG V_EN V_ V_PWR TOUT PG0 ask power team to check this issue 0KRF-L-GP GP-LOE-PWR GP-LOE-PWR P09 PG0 PG P0VJN--GP GP-LOE-PWR PG0 P0 GP-LOE-PWR GP-LOE-PWR OP setting EUVM--GP PG PG 9..GL GP-LOE-PWR change to 0K N = 9..FL PG0 GP-LOE-PWR GP-LOE-PWR et in 9. PG9 PG GP-LOE-PWR PG0 GP-LOE-PWR GP-LOE-PWR PG PG GP-LOE-PWR PG GP-LOE-PWR GP-LOE-PWR PG PG GP-LOE-PWR PG TOUT GP-LOE-PWR GP-LOE-PWR dd P, P PG PG GP-LOE-PWR TOUT P0 TOUT PG TOUT GP-LOE-PWR GP-LOE-PWR P GP-LOE-PWR P P change to close gaps 9 PG P P V_UX_ PR KRF-L-GP change to close gaps 9 GP-LOE-PWR PU0 I-T-GE-GP PU0 P PR0 change design current change to close gaps 0UVMX-GP PWR_VV_ENLO PU0 ENLO 00KRF-L-GP TP0-H-GP LO Iomax=. change H mosfet OP>9. Iomax= PR0 P9 P VIN OP> PWR_V_VOOT_ PWR_V_OOT 9 PWR_V_OOT PR09 PWR_V_VOOT_ change choke V_PWR OOT OOT UVKX-GP RJ-GP PWR_V_UGTE PWR_V_UGTE RJ-GP UVKX-GP V_PWR PL0 UGTE UGTE PL0 P0 PWR_VV_ENM/EF P V_ EF UVKX-GP V_V_POK PGOO V_EN PR PR ENTRIP V_UX_ KRF-GP PR 00KRJ--GP PWR_VV_TON add P0 PWR_V_ENTRIP TON ENTRIP PR 00KRJ--GP PR V_UX_ 9 V_V_POK KRF-GP KRF-L-GP et in.v PR9 Vout = * ( + PR/ PR9 0KRF--GP ) U0VKX-GP P0 T0UVM-GP PWR_V_VOUT PG GP-LOE-PWR--GP 0U0VKX-GP IN-UH--GP G PU0 I-T-GE-GP V_UX_ PWR_V_PHE PWR_V_LGTE PWR_V_F P0 P0VJN--GP 9 0 PHE LGTE F LO KRF--GP RT9ZQW-GP-U st =.09. GN PHE LGTE F YP 0 V_EN_L PWR_V_PHE PWR_V_LGTE PWR_V_F PWR_V_VOUT PR 00KRJ--GP 0UVKX-GP U0VKX-GP change L mosfet PU0 TP0-H-GP 0U0VKX-GP UVKX-GP IN-UH--GP PWR_V_VOUT et in V PR 0KRF--GP UVKX-GP PG GP-LOE-PWR--GP U0VKX-GP P P0 Vout = * ( + PR/ PR ) T0UVM-GP P0 T0UVM-GP TOUT K G PR0 0KRJ--GP PR0 00KRJ-L-GP Vz=.V TOUT PR PU0 0KRJ--GP PR0 PWR_VV_ENLO 0KRF-GP PU0_ UVKX-GP bios.ru F0 PU0_ 09 Modify PR 0KRF-GP N00KW-GP.N0.F nd =.N0.FF 09 Modify PU0 P0 MMPZ-GP.R90.F PR <ore esign> 00KRF-L-GP Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. V/V(RT9) ize ocument Number Rev 0-H - Thursday, March 9, 0 ate: heet of 09 E

42 TP-OP-GP TP0 PWR_GFXORE_IMON bios.ru _XG_ENE H_PU_VIT PWR_GFXORE_VW 0V_VTT P0 VR_VI_LERT# PR TP-OP-GP 0R00-P TP PGOOG PWR_VORE_ PWR_VORE_LERT# PWR_VORE_LK H_PU_VILK PR 0RJ--GP PR 0R00-P PWR_VORE_VRON, LL_PWR_OK PR IMVP_PWRG 9, 0_PWR_GOO 0RJ--GP PR K9RF--GP V_0 PWR_VORE_IMON TP0, IMVP_PWRG PWR_VORE_NT TP-OP-GP PR P0 PWR_VORE_VW 0V_VTT PR9 RF--GP ENE Place near high side MOFET of Phase, H_PROHOT# PR0 PR PWR_VORE_VW_L P PR PWR_VORE_IEN PR KRF-GP 0P0VJN-GP P PWR_VORE_IEN_R KRF-GP 0P0VKX-GP PR V_ORE PR0 0RJ--GP KRF-GP VENE ENE PR0 K0RF-GP P0 9P0VJN-GP PR0 KRF-GP 0U0VKX-GP Parallel KRF-GP P0 0UVKX-GP PR0 0R00-P P0 000P0VJN-GP-U P0 PR0 PWR_GFXORE_F_ 0P0VKX-GP PR K0RF-GP KRF-GP PR K0RF-GP PR0 P0 PWR_GFXORE_F_N RF--GP PR0 PR09 0RF--GP U0VKX-GP RF--GP P09 P0VJN-GP Place close to PU socket lose to PU P0 P0VJN-GP NT-0K--GP PR 9RF-L-GP PR KRF-GP P0 PR0 KRF--GP 000P0VJN-GP-U P P0VJN-GP V_0 PR P PWR_VORE_F_ 99RF--GP 0RF-L-GP PR9 0RF-L-GP 0P0V--GP 0P0VKX-GP PR K9RF--GP PR PWR_GFXORE_F_L PWR_VORE_OMP PWR_VORE_F KRF--GP P 0P0VKX-GP PU0 VWG IMONG PGOOG LERT# LK VR_ON PGOO 9 IMON 0 VR_HOT# NT VW P PWR_VORE_VUM- PWR_GFXORE_OMP PWR_GFXORE_F _XG_ENE PWR_GFXORE_IP PWR_GFXORE_IN PWR_GFXORE_NT PWR_GFXORE_PROG PWR_VORE_IEN PWR_VORE_IEN PWR_VORE_IEN PR9 PWR_VORE_F_L P KRF--GP 0P0VKX-GP P9 000P0VJN-GP-U GN 9 OMPG FG IL9HRTZ-T-GP P P P U0VKX-GP U0VKX-GP U0VKX-GP 0P0VKX-GP VENG RTNG -_00 IPG ING NTG PROG OOTG 0 PR K9RF-L-GP OMP F IEN/F IEN IEN VEN RTN IUMN IUMP V VIN PROG 9 0 P0 0P0VKX-GP PWR_VORE_VUM-_ UGG 9 PHG LGG PWR_VORE_V PWR_GFXORE_OOT PWR_GFXORE_HG PWR_GFXORE_PH PWR_GFXORE_LG PWR_VORE_VIN PWR_VORE_VUM+ Place close to PU socket P 000P0VJN-GP-U PR PWR_VORE_VUM-_L PWR_VORE_VP PWR_VORE_PWR_R PWR_VORE_PRG PR KRF-GP P 0P0VKX-GP P 0U0VKX-GP OOT UG PH P LG VP PWM 0 LG 9 P PH UG OOT P 0U0VKX-GP P U0VKX-GP P9 PWR_GFXORE_IP PWR_GFXORE_IN PR9 KRF-GP PR0 TOUT 0R00-P U0VKX-GP P0 U0VKX-GP PR V_PWR RF-GP P 9RF-GP UVKX-GP V_GFXORE PWR_GFXORE_OOT PWR_GFXORE_HG PWR_GFXORE_PH PWR_GFXORE_LG PR0 0RF-L-GP PR 0RF-L-GP PR KRF-L-GP PWR_VORE_OOT PWR_VORE_HG PWR_VORE_PH PWR_VORE_LG PWR_VORE_LG PWR_VORE_PH PWR_VORE_HG PWR_VORE_OOT PR KRF--GP PWR_VORE_VUM PR NT-0K--GP Parallel PWR_VORE_VUM+ PWR_VORE_VUM- <ore esign> V_XG_ENE 9 _XG_ENE 9 NT place near high side MOFET of Phase Place near choke of Phase P U0VKX-GP P 000P0VJN-GP-U PR PR NTG_R NT-0K--GP PR KRF-GP PR 0R00-P P KRF-GP U0VKX-GP V_PWR PWR_VORE_IEN PWR_VORE_IEN PWR_VORE_IEN PR 0R00-P P U0VKX-GP PWR_VORE_IEN PWR_VORE_IEN PWR_VORE_IEN ize ocument Number Rev ate: Thursday, March 9, 0 heet of 09 PWR_GFXORE_IN PR 0RJ--GP For iscrete only, UM need to UMMY Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PU ore-(il9) 0-H -

43 TOUT change to Net Name PWR_VORE_OOT PR PWR_VORE_OOT_ R--U-GP P PU0 UVKX-GP FM0-GP G Q PU09 FM0-GP G Q PL0 P UVKX-GP P UVKX-GP V_ORE P UVKX-GP P UVKX-GP PWR_VORE_HG PWR_VORE_PH PWR_VORE_LG 9 / G PHE Q 9 / G PHE Q PWR_VORE_VUM+_ OIL-UH--GP-U GP-LOE-PWR--GP PG PG PWR_VORE_VUM-_ GP-LOE-PWR--GP PR RF-GP PR RF-GP PR RF-GP PR 0KRF--GP PR9 KRF--GP P0 T0UVM--GP-U P0 PWR_VORE_IEN PWR_VORE_IEN PWR_VORE_VUM- PWR_VORE_IEN PWR_VORE_VUM+ T0UVM--GP-U TOUT change to Net Name TOUT P09 P0 PWR_VORE_OOT PWR_VORE_HG PWR_VORE_PH PWR_VORE_LG P PU0 FM0-GP PWR_VORE_HG PWR_VORE_PH 9 / PWR_VORE_LG UVKX-GP G Q G PHE PU FM0-GP Q 9 / G Q G PHE Q PWR_VORE_VUM+_ PL0 OIL-UH--GP-U PG0 GP-LOE-PWR--GP PG0 PWR_VORE_VUM-_ GP-LOE-PWR--GP P0 T0UVM--GP-U P0 UVKX-GP T0UVM--GP-U V_ORE P9 PR09 RF-GP PWR_VORE_IEN PR0 RF-GP PWR_VORE_IEN PR PWR_VORE_VUM- T0UVM--GP-U UVKX-GP elete gap 00 elete gap bios.ru PWR_VORE_IEN PWR_VORE_VUM+ P UVKX-GP P T0UVM--GP-U P0 P0 P P0 EUVM--GP PR0 PWR_VORE_OOT_ R--U-GP UVKX-GP RF-GP PR UVKX-GP UVKX-GP 0KRF--GP PR KRF--GP <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PU ore-(il9) ize ocument Number Rev ustom 0-H - ate: Thursday, March 9, 0 heet of 09

44 change to Net Name TOUT PWR_GFXORE_OOT PR0 PWR_GFXORE_OOT_ RJ-L-GP P0 UVKX-GP PU0 FM0-GP G Q PU0 FM0-GP G Q P UVKX-GP P0 UVKX-GP P0 UVKX-GP P0 UVKX-GP P0 UVKX-GP V_GFXORE PWR_GFXORE_HG PWR_GFXORE_PH PWR_GFXORE_LG 9 / G PHE Q PWR_GFXORE_IP_R PWR_GFXORE_IN_R Place near choke PR0 0KRF--GP KRF--GP PR0 P09 0UVKX-GP 9RF-GP U0VKX-GP PR0 PWR_GFXORE_IN_PR NT-0K--GP PR0 PWR_GFXORE_IP_PR PR0 0UVKX-GP T0UVM--GP-U P0 PR0 PWR_GFXORE_IN_PR 0RF-GP P0 P UVKX-GP PWR_GFXORE_IN PWR_GFXORE_IP TOUT P0 UVKX-GP 9 / G PHE Q PL0 OIL-UH--GP-U PG0 PG0 GP-LOE-PWR--GP GP-LOE-PWR--GP PR0 RF-GP KRF-L-GP P0 P T0UVM--GP-U P EUVM--GP delete gap bios.ru <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PU ore-(il9) ize ocument Number Rev 0-H - ate: Thursday, March 9, 0 heet of 09

45 TOUT PWR_TOUT_0V 0V_LN 0V_PWR 0V_LN 9 PG0 GP-LOE-PWR PG0 GP-LOE-PWR PG0 GP-LOE-PWR PG0 GP-LOE-PWR P09 EUVM--GP 9..GL N = 9..FL,,, RUNPWROK 9,, PM_LP_LN# change to close gaps9, 0V_VTT_PWRG 0V_LN_PWRG Non_iMT_ PR0 0RJ--GP PR 0RJ--GP imt_ V_ Non_iMT_ PR 0RJ--GP PWR_0V_PGOO imt_ PR 0RJ--GP 9/ PU0 PR0 KRF-GP PWR_0V_TRIP PGOO PWR_0V_EN TRIP PWR_0V_VF EN PWR_0V_M VF RF KP0VKX-GP PR P0 TP for 0V PR0 0RJ-0-U-GP PWR_0V_VT PWR_0V_VT_R PWR_0V_RVH PWR_0V_W PWR_0V_RVL V_PWR PWR_TOUT_0V PU0 FM9-GP G G - 0 PU0 FM00-GP P0 UVKX-GP P0 UVKX-GP Mag. 0.uH 0*0* R=.~.mohm Idc=, Isat=0 VTT_ENE_L IN-UH--GP PR0 0RF-L-GP Iomax= OP> 0V_PWR PG0 PG GP-LOE-PWR GP-LOE-PWR PG0 PG GP-LOE-PWR GP-LOE-PWR PG0 PG GP-LOE-PWR GP-LOE-PWR PG0 PG GP-LOE-PWR GP-LOE-PWR PG0 PG GP-LOE-PWR GP-LOE-PWR PG09 PG9 GP-LOE-PWR GP-LOE-PWR PG PG0 GP-LOE-PWR GP-LOE-PWR PG PG GP-LOE-PWR GP-LOE-PWR PG PG GP-LOE-PWR GP-LOE-PWR change to close gaps9 PWR_0V_VF Matsuki cap 90uF.V, ER=0mohm Vout=0.0V*(R+R)/R _ENE_L VTT_ENE_L VIO_ENE _ENE_L GN VT 0 RVH 9 W VIN RVL TPR-GP-U P0 UVKX-GP PL0 PR0 0KRF--GP P0 U0VKX-GP P E0UVM-GP 0KRJ--GP PR0 0KRF-GP P0 U0VKX-GP P0 UVKX-GP P0 UVKX-GP PR0 0KRF-L-GP PR09 PR0 0RF-L-GP 0RJ--GP P0 000P0VJN-GP-U PR0 0RJ--GP IO_ENE bios.ru <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. to _0V(TP) ize ocument Number Rev ustom 0-H - ate: Thursday, March 9, 0 heet of 09

46 TOUT PWR_TOUT_V V_PWR V_ PG0 GP-LOE-PWR PG0 PG0 GP-LOE-PWR PG GP-LOE-PWR PG0 GP-LOE-PWR PG GP-LOE-PWR PG0 9, PM_LP_# PWR_V_EN P U0VKX-GP V_ KP0VKX-GP RT0L for V PWR_V_V P0 9/ PWR_V_ PR0 9KRF-GP PWR_V_VP V_ P0 U0VKX-GP V_ PWR_TOUT_V PU0 FM9-GP G - 0 P0 UVKX-GP change to close gaps9 P UVKX-GP,,, RUNPWROK PWR_TOUT_V lose to pin PR09 PWR_V_TON 0KRF-GP PWR_V_EN PWR_V_OOT PWR_V_UGTE PWR_V_PHE_L G Iomax= OP>. V_PWR GP-LOE-PWR PG GP-LOE-PWR PG GP-LOE-PWR PG Iomax= OP>. V_PWR GP-LOE-PWR PG0 V_PWR GP-LOE-PWR R_VREF_PWR lose to output cap pin, not inside of the output cap change toclose gaps P0 0UVMX-GP PWR_0V_EN PWR_V_VTTIN PWR_V_VQ lose to pin PWR_V_VTTREF PR0 0R00-P PWR_V_PHE PWR_V_LGTE PWR_V_VQ PWR_V_F V_ R_VREF_ R R PR0 0KRF-GP G GP-LOE-PWR PG PR0 0R00-P PR0 RF-GP P0 U0VKX-GP PR0 0R00-P P UVKX-GP GP-LOE-PWR P TUVM--GP GP-LOE-PWR PG GP-LOE-PWR PG GP-LOE-PWR PG GP-LOE-PWR PG GP-LOE-PWR PG GP-LOE-PWR PG9 GP-LOE-PWR PG0 GP-LOE-PWR PG PR0 0KRF--GP PGOO TON V VP PU0 OOT UGTE PR0 R--U-GP P0 UVKX-GP PL0 PG0 GP-LOE-PWR PG0 0 VLOIN N# VTTGN MOE VTT VTTN GN GN R0 KRF-GP P09 P0VJN--GP G PU0 FM00-GP 00 Vout=0.*(+R/R) Vout=0.*(+0K/0K) =.V P UVKX-GP P E0UVM-GP P E0UVM-GP GP-LOE-PWR PG GP-LOE-PWR PG GP-LOE-PWR P0 0UVKX-GP change to chose gaps 0.V Iomax=. 0V_0 R_VREF_PWR VTTREF PHE LGTE VQ F 0 9 PGN N# 9 EM RT0LZQW-GP.00. IN-UH--GP-U PG0 0V_EN PR 0R00-P PWR_0V_EN GP-LOE-PWR PG09 bios.ru GP-LOE-PWR P0 0UVMX-GP P0 0UVMX-GP <ore esign> RT0L Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev ustom 0-H - Thursday, March 9, 0 ate: heet of 09

47 PW for V_0 V_PWR PR0 0KRF--GP,,, confirm with cherry RUNPWROK V_ P0 0UVMX-GP P0 0UVMX-GP PWR_V_OMP0 OMP P0 PR0 PR0 PWR_V_OMP_R 0KRF-L-GP 00P0VJN-GP P0 MRF-GP PU0 PV PGN V LX# POK LX# PWR_V_F 9 F GN GN HN/RT PWQI-TRG-GP.0. PWR_V_LX PWR_V_RT PL0 IN-UH-GP PWR_V_F et at 0.V PR0 0KRF-GP PR0 0KRF-L-GP 00P0VJN-GP change to close gaps 9 P0VJN-GP - 00 Vo=0.*(+(R/R)) PM_LP_#_MO 9,,9,,,, PM_LP_# PR0 KRF-GP V_PWR P0 P0 UVMX-GP V_0 PG0 GP-LOE-PWR P0 PG0 UVMX-GP GP-LOE-PWR PG0 GP-LOE-PWR PQ0 G P0 U0VKX-GP N00K--GP - 0.N0.J nd =.000.I bios.ru <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. LO_V(PW) ize ocument Number Rev 0-H - ate: aturday, March 0, 0 heet of 09

48 TP for V V_ V_ PG0 GP-LOE-PWR PG0 GP-LOE-PWR PWR_V_VIN change to close gaps9 P0 UVKX-GP PR0 RF-GP P UVKX-GP P UVKX-GP V_ P U0VKX-GP P U0VKX-GP PWR_V_VRV 9 PGN 0 PGN PGN VIN VIN VIN GN PWR_V_PGOO VRV VFILT PGOO VI VI0 EN GN VREF OMP LEW VOUT MOE PWR_V_OMP PWR_V_VREF PR09 00KRJ--GP PR0 0R00-P PWR_V_VI PWR_V_VI0 PWR_V_EN T W# W#0 0 W#9 9 W# W# PWR_V_VOUT PWR_V_LEW LL_PWR_OK, PR0 0R00-P PR0 0R00-P PWR_V_T PWR_V_W PR KRF--GP PR0 0RJ-0-U-GP PR 00RF-L-GP-U PR 0RJ--GP P0 0U0VKX-GP V_VI 9 V_VI0 9 0V_VTT_PWRG, PWR_V_T_R 0V_PWR NETNME ME 0 V_ENE 9 P 0UVMX-GP esign urrent =.<OP<. 0V_PWR VI0 L L H VI L H L V 0.9V 0.V 0.V PWR_V_OMP_ PR0 K99RF-L-GP 0 - change to close gaps9 H H 0.V U0 P0 TPRGER-GP UVKX-GP..0 PR0 0R00-P P0 UVKX-GP PL0 IN-UH--GP.R0.0M UVMX-GP P0 UVMX-GP P09 P0 0UVMX-GP P0 0UVMX-GP P0 0UVMX-GP P UVKX-GP 0V_0 PG0 GP-LOE-PWR PG0 GP-LOE-PWR PG0 GP-LOE-PWR PG0 GP-LOE-PWR PG0 GP-LOE-PWR PG0 GP-LOE-PWR P 00P0VKX-GP 0 - P0 U0VKX-GP bios.ru <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. LO_V(TP) ize ocument Number Rev 0-H - ate: Thursday, March 9, 0 heet of 09

49 I = VIEO LV ONNETOR LV ONNETOR L NP NP P-ON0-GP 0.F.00 TOUT_L TOUT_L _EN_ 0 LON_OUT_ L_RIGHTNE LKLT_TL 9 R90 RJ-L-GP U_MER# U_PN U_MER R90 0R00-P U_PP R909 0R00-P F9 F9 9/9 FOR RF P0VJN-GP P0VJN-GP UVKX-GP V_0 90 U0VKX-GP L POWER for NNIE INVERTER POWER 90 EP#_LV_R KP0VKX-GP U0VKX-GP ep decet. LV T 9 LV LK 9 LV UVKX-GP I = VIEO 90 F9 P0VJN-GP amera GN F90 POLYW-V-GP-U V_MER_0 LV_LK_R 9 LV_LK_R# 9 LV_T_R 9 LV_T_R# 9 LV_T_R 9 LV_T_R# 9 LV_T0_R 9 LV_T0_R# 9 P_T_R 0 P_T_R# 0 P_UX 0 P_UX# 0 P_T0_R 0 P_T0_R# 0 lvds connect to GN nd = _EN_ TOUT R90 0KRJ--GP _EN R90 RJ--GP R90 0KRJ--GP V_0 V_0 TP90 9/ amera Power F90 FUE-V-GP-U V_MER_ N = V_0 0UVMX-GP 90 0 P_UX# 0 P_UX V_0 EP#_LV_ R99 Q90 0R00-P MMT90--GP.T90. N =.090.P rd =.090.L0 V_0 Note: Place pull up resistor within inch of PU R99 0KRJ-L-GP EP#_LV_R EP#_LV_ R9 0KRJ-L-GP E R9 0KRJ-L-GP R9 00KRJ--GP R9 00KRJ--GP 00 - R9 00KRJ--GP R9 00KRJ--GP EP#_LV LV U90 Layout 0 mil 9 LV_EN EN IN# GN OUT IN# 00KRJ--GP R9 UVKX-GP 909 bios.ru UVKX-GP 90 GTU-GP.0.0F nd =.09.09F V_0 UVKX-GP 90 F9 P0VJN-GP 9/9 FOR RF LON_OUT KRJ--GP LON_OUT_ R90 00KRJ--GP R9 00P0VJN-GP 90 LV_LK_R LV_LK_R# LV_T_R LV_T_R# LV_T_R LV_T_R# LV_T0_R LV_T0_R# LV T LV LK F90 P0VN-GP F90 P0VN-GP F90 P0VN-GP F90 P0VN-GP F90 P0VN-GP F90 P0VN-GP F90 P0VN-GP F90 P0VN-GP F909 P0VN-GP F90 P0VN-GP <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. L onnector ize ocument Number Rev 0-H - ate: Thursday, March 9, 0 heet 9 of 09

50 V_RT_0 RT Pull High V esign on RT oard RT T & LK level shift V_0 V_0 0UVKX-GP 0 9 RT_VYN_ON_M 9 RT_HYN_ON_M RT_T_ON RT_LK_ON RT_R RT_G RT_ 9 V_RT T_I LK_I RT_RE RT_GREEN RT_LUE VYN HYN -U---GP-U nd = N# N# GN GN GN GN GN 0 GN GN RT_IN#_R FTP00 9 T_M V_RT_0 F00 FUE-V-GP-U nd = V_0 V_RT_0_R RT_T_ON K 00m 00 HH-0GP-GP.R00.JF nd =.R00.HH rd =.R00.0F RN00 RN0KJ--GP RT_IN#_R 9 LK_M RT_LK_ON Q00 N00KW-GP.N0.F nd =.N0.FF 9 RT_RE_R_M 9 RT_GREEN_R_M 9 RT_LUE_R_M RN00 RN0F--GP bios.ru RT RG 00 check RN00 擺擺擺擺 P0V-GP 00 P0V-GP 00 L00 FM0F-0T0-GP.00.0 nd = L00 FM0F-0T0-GP.00.0 L00 FM0F-0T0-GP.00.0 P0V-GP P0VJN-GP 00 0P0VJN-GP RT_R RT_G RT_ 00 0P0VJN-GP 00P0VJN-GP 00 P0VJN--GP <ore esign> 009 P0VJN--GP RT_T_ON RT_HYN_ON_M RT_VYN_ON_M 00RT_LK_ON 0 00P0VJN-GP Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RT onnector ize ocument Number Rev 0-H - ate: aturday, March 0, 0 heet 0 of 09

51 9 HMI 0 TM_TX+_M TM_TX-_M TM_TX+_M TM_TX-_M TM_TX0+_M 9 TM_TX0-_M 0 TM_TX+_M TM_TX-_M HMI_E TP0 TP-OP-GP TM_L TM_ 9 HMI_IN_ R0 KRJ--GP KT-HMI-0-GP.09. N =.09. R =.09.0 R0 00KRJ--GP V_HMI_0 V_0 F0 FUE-V-GP-U nd = HMI_IN U0VZY-GP TM_L_ TM RN0J--GP RN0 V_0 TM_L_ TM TM_TX-_M TM_TX+_M 0 U0VKX-GP EXT TM_TX0+_ TM_TX0-_ TM_TX+_ TM_TX-_ TM_TX+_ TM_TX-_ P_HP_ REXT R 99RF--GP VI_P TM_TX+_ TM_TX-_ U0 INP INN V INP INN GN INP INN L_R _R HP_R REXT GN V_0 INN INP VI EXT OUTP OUTN GN 0 OUTP 9 OUTN V OUTP OUTN W/_TL OE#/L_TL I_TL_EN HP _UXN L_UXP V OUTN OUTP GN OUTN OUTP TM_TX0+_M TM_TX0-_M TM_TX+_M TM_TX-_M OUTP OUTN GN L_UXP _UXN 0 9 HP MOE/I_R OUTP OUTN V OUTP OUTN TM_TX+_M TM_TX-_M I_R V_0 TM_L TM_ HMI_IN 0 W--GP.000.Q nd =.000.K TM_L_R TM R TM_TX+_OK 0 TM_TX-_OK 0 TM_TX0+_OK 0 TM_TX0-_OK 0 RN0 RNKJ--GP VI_P V_0 V_0 R0 0RJ--GP I_TL_EN LOW or N MOE / I_R LOW PinMode HMI/VI LOW or N HIGH PinMode P I_R I_TL R 0RJ--GP PinMode/I 9E9F HIGH LOW I I addresses addresses 9E/9F E/F R KRJ--GP I EF V_0 HIGH HIGH R KRJ--GP I R KRJ--GP PinMode PQFNG-GP 0 R0 0RJ--GP TM TM_L I_TL TM_TX+_OK 0 TM_TX-_OK 0 UM 0 U0VKX-GP TM_TX0-_ TM_TX+_OK 0 P_T0# UM 0 U0VKX-GP HMI_VI_IN TM_TX0+_ TM_TX-_OK 0 P_T0 0 OK_ UM 0 U0VKX-GP TM_TX-_ V_0 P_T# UM U0VKX-GP 0 OK_L TM_TX+_ P_T UM U0VKX-GP TM_TX-_ P_T# UM 0 U0VKX-GP TM_TX+_ P_T UM 0 U0VKX-GP TM_TX-_ P_T# UM 09 U0VKX-GP TM_TX+_ P_T GPU_P_T GPU_P_T# GPU_P_T GPU_P_T# GPU_P_T GPU_P_T# GPU_P_T0 GPU_P_T0# I_PX_Muless U0VKX-GP I_PX_Muless U0VKX-GP I_PX_Muless U0VKX-GP I_PX_Muless U0VKX-GP I_PX_Muless U0VKX-GP I_PX_Muless U0VKX-GP I_PX_Muless 0 U0VKX-GP I_PX_Muless 9 U0VKX-GP,9,9,0,0 _IN# U0VKX-GP PinMode R9 TM 0RJ--GP VI V INPUT FOR HMI/VI /09 GN INPUT For HMI/VI V_0 N00KW-GP V_ RNKJ--GP R0 TM RN 0RJ--GP I P_HP_ R KRJ--GP P_HP P_HP_E V_0 R0 0RJ--GP.090.L0 nd =.090.X Q0 PM90--GP P_HP_Q 0RJ--GP UM R V Tolerance GPU_P_L GPU_P_ PH_HMI_LK PH_HMI_T RN0 RNKJ--GP PH_P_HP PX V_VG_0 RN0 RN0J--GP PX UM RN RN0J--GP W HMI_LK_ HMI_T_ H OUT L OUT V_VG_0 R 0RJ--GP PX HMI_MU_V Q0 N00KW-GP.N0.F nd =.N0.FF V_0 R 0RJ--GP UM TM_L_ TM R,9,9,,9,9, ML_T_ ML_LK_ V_0 pin mode R 0KRJ--GP 0909 TM_L.N0.F nd =.N0.FF HMI_VI_IN_R HMI_IN HMI_IN_R HMI_VI_IN pin mode 0RJ--GP pin mode pin mode 0RJ--GP Q0 N00KW-GP.N0.F nd =.N0.FF 0 R 9/ Q0 TM TM_L_ I R TM_L 0RJ--GP R9 0KRJ--GP 0RJ--GP PX R GPU_P_HP bios.ru <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. HMI Level hifter/onnector ize ocument Number Rev 0-H - Thursday, March 9, 0 ate: heet of 09

52 P V_0 R0 0RJ--GP _P_IN_E ock,0 _P_IN R0 KRJ--GP ock _P_IN_ Q0 PM90--GP _P_IN_Q ock_um 0RJ--GP R0 PH_P_HP.090.L0 nd =.090.X OK R0 0KRJ--GP ock 0RJ--GP ock_px R0 GPU_P_HP P_UX# P_UX P_T0# P_T0 P_T# P_T P_T# P_T P_T# P_T ock_um 09 U0VKX-GP ock_um 0 U0VKX-GP ock_um 0 U0VKX-GP ock_um 0 U0VKX-GP ock_um 0 U0VKX-GP ock_um 0 U0VKX-GP ock_um 0 U0VKX-GP ock_um 0 U0VKX-GP ock_um 0 U0VKX-GP ock_um 0 U0VKX-GP OK_P_UX# 0 OK_P_UX 0 OK_P_T0# 0 OK_P_T0 0 OK_P_T# 0 OK_P_T 0 OK_P_T# 0 OK_P_T 0 OK_P_T# 0 OK_P_T 0 GPU_EP_UX# GPU_EP_UX ock_px U0VKX-GP ock_px U0VKX-GP GPU_EP_T0# GPU_EP_T0 GPU_EP_T# GPU_EP_T GPU_EP_T# GPU_EP_T GPU_EP_T# GPU_EP_T bios.ru ock_px 0 U0VKX-GP ock_px 9 U0VKX-GP ock_px U0VKX-GP ock_px U0VKX-GP ock_px U0VKX-GP ock_px U0VKX-GP ock_px U0VKX-GP ock_px U0VKX-GP <ore esign> isplay Port Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev 0-H - ate: aturday, March 0, 0 heet of 09

53 (lanking) <ore esign> bios.ru -VIEO Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev 0-H - ate: Friday, March 0, 0 heet of 09

54 (lanking) <ore esign> bios.ru Reserved Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev 0-H - ate: Friday, March 0, 0 heet of 09

55 I = User.Interface ITP onnector H_PURT# use pull-up Resistor close ITP connector 00 mil ( max ), others place near PU side. PU TK(PIN ) ITP onnector TK(PIN ) FO(PIN ) <ore esign> bios.ru ITP Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev 0-H - ate: Friday, March 0, 0 heet of 09

56 I = T T H onnector H NP V_0 T_RXP0 T_RXN0 T_TXN0 T_TXP0 0U0VZY-GP 0 9 H_UNLO U0VKX-GP 0 0UVKX-GP 0 0UVKX-GP 0 T_RXP0_ T_RXN0_ 0UVKX-GP 0 T_TXN0_ 0UVKX-GP 0 T_TXP0_ FOX-ON0--GP-U NP 0.F.00 N = 0.F.00 O onnector T_TXP T_TXN T_RXN T_RXP T_O_PRNT# nd source.00. and.00.. T V_0 T_O_# 0UVKX-GP 0UVKX-GP 0UVKX-GP 0UVKX-GP 0 T_TXP_ T_TXN_ T_RXN_ T_RXP_ R0 O O_PWR_V R0 T_O_#_ 0RJ--GP 0RJ--GP Y 9 NP P P P P P P NP 0 KT-TP-P--GP.00.9 nd =.00. Zero Power O T_O_PWRGT V_0 ZPO T0 0U0VZY-GP EN/EN# IN# IN# GN urrent limit ctive High MIN =>.0 00 mil U0 Y-GP.0.09 ZPO O# OUT# OUT# OUT# O_PWR_V T0 ZPO 0U0VZY-GP T Zero Power O V_0 bios.ru V_0 RN0 RN0KJ--GP ZPO T_O_PWRGT T_O_# Q0 ZPO R0 0KRJ--GP O_PWRGT# T_O_#_ T_O_PWRGT T_O_# 00 Modify: hange Q0 to UL N00 for isolate M/ signal between PH and O. N00KW-GP.N0.F nd =.N0.FF <ore esign> H/O Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev 0-H - ate: aturday, March 0, 0 heet of 09

57 ET Power V_,0 U_PWR_EN# 0 U0VKX-GP 09 U0VZY-GP at least 0 mil P0MPG--GP ET FLG EN# OUT# IN# OUT# IN# N# GN GN 9 U N R =.0.9 V_U0_ at least 0 mil 0 U0VKX-GP ET 0 U0VZY-GP ET T0 T00UVM-GP.0.0 ET nd =.0.L rd =.0.0L 0 ET ET ypass T redriver path 9/0 9/ U_PN9 U_PP9 V_U0_ NP NP 9 ET 0 KT-U+ET--GP-U T_RXP_ 0UVKX-GP 0 T_RXN_ 0UVKX-GP 0 T_TXN_ T_TXP_ 0UVKX-GP 0UVKX-GP ET ET 0 0 ET ET -_00 I-T-->ET 0 T_RXP T_RXN T_TXN T_TXP 0 bios.ru <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. E-T/U HRGER ize ocument Number Rev 0-H - ate: aturday, March 0, 0 heet of 09

58 I = UIO peaker onnector 9 9 M_HP_L M_HP_R L0 HP_L_ K00T-0Y-N-GP L0 HP_R_ K00T-0Y-N-GP 9 U_HP_J# LINE OUT NP NP LOUT 9 U_PK_L- -_00 PK 0 OK_LINEOUT_J# GP-LOE G0 E MLV00M0-GP-U UIO-JK9-GP-U TP TP-OP-GP.0. N =.0. 9 U_PK_L+ 000P0VJN-GP-U 0 000P0VJN-GP-U 0 E-ON-0-GP 0.F9.00 nd = 0.F0.00 U_GN E U0VKX-GP E R0 0RJ--GP 9 9 M_MIIN_L M_MIIN_R MI IN L0 K00T-0Y-N-GP L0 K00T-0Y-N-GP 9 EXT_MI_J# GP-LOE 0 OK_MI_J# G0 MI_IN_L_ MI_IN_R_ E MLV00M0-GP-U NP NP MIIN UIO-JK9-GP-U.0. N =.0. TP TP-OP-GP U0VKX-GP E U0VKX-GP E U0VKX-GP U_GN R 0RJ--GP R 0RJ--GP E U0VKX-GP E U0VKX-GP U_GN U_GN Internal Microphone bios.ru 9 MI_ 9 MI_LK L0 MLV00M0-GP-U V_0 ER0 RJ--GP MI R ER0 MI_LK_R RJ--GP L0 MLV00M0-GP-U _00 (Varistor) Need confirm with EMI : or ? MI E-ON-9-GP 0.F9.00 N = 0.F0.00 U_PK_L- U_PK_L+ E0 P0VJN-GP M_MIIN_L E0 P0VJN-GP M_MIIN_R E0 P0VJN-GP MI_ E0 P0VJN-GP MI_LK M_HP_L M_HP_R E0 TVL GP <ore esign> E0 TVL GP E09 udio Jack Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev 0-H - ate: aturday, March 0, 0 heet of 09 P0VJN-GP E0 P0VJN-GP

59 I = LOM GIG Lan Transformer LN MI Off-Page ONN_PWR ONN_PWR E90 000P0VJN-GP-U E90 000P0VJN-GP-U 000P0VJN-GP-U E90 LN_T_LE#_Y 000P0VJN-GP-U E90 0M/00M/G_LE#_Y LE OLOR 0(+) 9(-)::GREEN (+) (-):ORNGE 0 LN_T_LE#_Y 0 0M/00M/G_LE#_Y ONN_PWR ONN_PWR RJ_ RJ_ RJ_ RJ_ RJ_ RJ_ RJ_ RJ_ LN -_ E-ON--GP 0.F.0 nd = 0.F0.0 XF90 0 MI+_Y T:T RJ_ 90 U0VKX-GP 90 U0VKX-GP 90 U0VKX-GP XRF_T 0 MI-_Y 0 MI+_Y XRF_T 0 MI-_Y 0 MI+_Y XRF_T 0 MI-_Y 90 U0VKX-GP 0 MI0+_Y XRF_T 0 MI0-_Y T:T 0 9 T:T 9 T:T 0 XFORM-P-9-GP MT RJ_ RJ_ MT RJ_ RJ_ MT RJ_ RJ_ MT RJ_ For EMI 0 MI+_Y 0 MI-_Y V_ V_ U90 U90 TVLT00-GP.00.0E 0 MI0+_Y 0 MI0-_Y V_ V_ U90 U90 TVLT00-GP.00.0E V_M - 0 RN90 RN0J--GP-U ONN_PWR ONN_PWR TVLT00-GP.00.0E TVLT00-GP.00.0E 0 MI+_Y 0 MI+_Y 0 MI-_Y 0 MI-_Y MT MT MT MT MT MT MT MT 09X9T0-GP GT 09X9T0-GP GT 09X9T0-GP GT 09X9T0-GP GT RJ-L-GP R90 RJ-L-GP R90 RJ-L-GP R90 RJ-L-GP MT_R R90 90 KPKVKX-GP bios.ru <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. LN ONNETOR ize ocument Number Rev ustom 0-H - aturday, March 0, 0 ate: heet of 9 09

60 PI FLH ROM (M byte) for PH I = Flash.ROM V_ V_ 09 PI ROM Equal length need to less than 00mil M:.0.0,.Q.0 M:.Q.0,.0.0 RN00 RNKJ-0-GP YTEM PI ROM 0UVKX-GP 00 U0VKX-GP 00 U0VKX-GP 00 PI_HOL_0# V_ U00 U00 PI_0#_R PI_O_R R00 RJ--GP vpro NON vpro.q PI_O PI_WP# # V O/IO HOL# WP# LK GN I/IO0 MXL0EMI-G-GP.0.0 PI_LK_R_0 R0 PI_LK_R PI_I_R_0 RJ--GP PI_I_R R0 RJ--GP E00 E00 P0VN-GP P0VN-GP U00.Q V_ V_ V_ R00 KRJ--GP UL ROM R009 KRJ--GP UL ROM V_ R00 KRJ--GP UL ROM U00 PI_#_R PI_O_ R00 RJ--GP UL ROM PI_O R PI_WP#_ # V O/IO HOL# WP# LK GN I/IO0 MXL0EMI-G-GP UL ROM.0.0 PI_HOL_# R0 RJ--GP PI_LK_R_ PI_I_R_ UL ROM RJ--GP R0 UL ROM PI_LK_ PI_I_ V_UX_ 00 --GP.000.K nd =.000.M +RT_PWR_R I = RTT RT_UX_ R00 KRJ--GP 0.F9.00 nd = 0.F0.00 Q00 HFGP-GP-U RT_PWR +RT_PWR R00 0RJ--GP RT Width=0mils.R00. nd =.R00.G E-ON-0-GP V_UX_ E IO Flash ROM K V_UX_ PILK_ PI_O PII for ENE FE suggest,pi# is push-pull pin, don't need to pull high bios.ru PI# PII PI_WP# PI_HOL# R00 R00 0KRJ--GP 0KRJ--GP 0RF--GP ER00 R00 0KRJ--GP PI_I PI_WP# U00 E# V O HOL# WP# K GN IO PML00-E-GP.00.E0 nd = PI_V_V PI_HOL# PILK_ PI_O ER00 0R00-P 00 UVKX-GP 0RF--GP ER00 0RF--GP ER00 PILK PIO E00 P0VN-GP E00 P0VN-GP <ore esign> E00 P0VN-GP Flash/RT Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev ustom 0-H - Thursday, March 9, 0 ate: heet of 0 09

61 I = U <ore esign> bios.ru Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. U Power W ize ocument Number Rev 0-H - ate: Friday, March 0, 0 heet of 09

62 bios.ru <ore esign> U.0 Port Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev 0-H - ate: Friday, March 0, 0 heet of 09

63 I = User.Interface luetooth Module conn. 0 del NNIE luetooth Module E0 put near LUE / all U put one choke near connector by EMI request <ore esign> bios.ru luetooth Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev 0-H - ate: Friday, March 0, 0 heet of 09

64 Finger printer JE0 delete FP function F/P <ore esign> bios.ru REERVE Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev 0-H - ate: Friday, March 0, 0 heet of 09

65 I = Wireless Mini ard onnector(0.a/b/g/n) V_0 V_MINI_0 _NONiMT imt_o R 0RJ--GP R 0RJ--GP V_MINI_0 G mt_o R 0RJ--GP R 0RJ--GP V_ V_MINI_0 V_0 V_MINI_0 WLN 0 0 0, E_RX, E_TX L_LK L_T L_RT# TP0 TP-OP-GP V_0 R0 0RJ--GP E_RX_R R0 0RJ--GP E_TX_R MINI_EN V_MINI_0 imt imt - 00 R0 0RJ--GP L_LK_R R0 imt 0RJ--GP L_T_R R0 0RJ--GP L_RT#_R +V_MINI_EUG R 0KRJ--GP R WLN_LE#_ 0RJ--GP WLN_LE#.V.V +.V +.V +.V +.VUX REERVE# REERVE# REERVE# 0 REERVE#0 REERVE# REERVE# REERVE# REERVE# 9 REERVE#9 0 REERVE#0 REERVE# 9 REERVE#9 REERVE# REERVE# REERVE# REERVE# 9 REERVE#9 REERVE# LE_WWN# LE_WLN# LE_WPN# KT-MINIP--GP-U PERN0 PERP0 PETN0 PETP0 REFLK+ REFLK- U_- U_+ M_LK 0 M_T NP NP WKE# LKREQ# PERT# GN GN 9 GN GN GN GN GN GN 9 GN GN GN 0 GN 0 GN GN hange WLN Main/nd source - 0 EUG_ET# PIE_WKE#_R LK_PIE_WLN 0 LK_PIE_WLN# 0 PIE_RXN 0 PIE_RXP 0 PIE_TXN 0 PIE_TXP 0 U_PN U_PP O 0RJ--GP R PIE_WKE# 9,,, PIE_LK_WLN_REQ# 0 PLT_RT#,,,,,,,,,,,9,0 WIRELE_EN MINI_EN LUETOOTH_EN LUETOOTH_EN_ nd =.N0.FF.N0.F N00KW-GP Q0 _NONiMT imt R R imt 0KRJ--GP 0KRJ--GP MINI_EN_R V_MINI_0 imt V_ V_MINI_0 +V_MINI_EUG 0 F0 EMI request V_0 0UVKX-GP bios.ru LK_PIE_WLN LK_PIE_WLN# EUG_ET# Q0 N00K--GP G LUETOOTH_EN_ +V_MINI_EUG uto detect ebug card 000 Q0 MP0L--GP G G.00.0 N =.0. R0 00KRJ--GP UVKX-GP P0VJN-GP P0VJN-GP E0 G NP NP.00. nd =.00.G9 R 0RJ--GP _NONiMT IMT R R0 0KRJ--GP 0KRJ--GP nd =.N0.FF.N0.F N00KW-GP Q0 LUETOOTH_EN_R R 0RJ-0-U-GP IMT 0 0 UVKX-GP 0 0 0UVKX-GP UVKX-GP UVKX-GP F0 0 P0VJN-GP P0VJN-GP E0.N0.J nd =.000.I <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. MINIR(WLN)/ITP ONN ize ocument Number Rev 0-H - ate: Thursday, March 9, 0 heet of 09

66 I = Wireless 000 V. Place near MINI ard ONN Mini ard onnector(wwn) V_MINI_0 0 UVKX-GP 0 UVKX-GP V_0 09 F0 UVKX-GP 0 UVKX-GP UVKX-GP 0 P0VJN-GP.N0.F N00KW-GP Q0 F0 F0 P0VJN-GP P0VJN-GP 9/9 FOR RF V_MINI_0 9/9 FOR RF F0 P0VJN-GP R G 0KRJ--GP, E_RX, E_TX TP TP-OP-GP V_ V_0 G_LE# V_0 V_MINI_0.V.V +.V +.V G_MT GLN +.V +.VUX REERVE# UIM_PWR REERVE# UIM_T REERVE# 0 UIM_LK REERVE#0 UIM_REET REERVE# 0RJ--GPUIM_VPP REERVE# E_RX_MINI REERVE# E_TX_MINI REERVE# R0 R0 9 0RJ--GP MINI_EN REERVE#9 0 REERVE#0 REERVE# V_MINI_0 9 REERVE#9 REERVE# REERVE# REERVE# 0RJ--GP REERVE# 9 MINI_V_R REERVE#9 R0 REERVE# R0 0KRJ--GP LE_WWN# LE_WLN# LE_WPN# KT-MINIP--GP-U PERN0 PERP0 PETN0 PETP0 REFLK+ REFLK- U_- U_+ M_LK 0 M_T NP NP NP NP.00. nd =.00.G9 WKE# LKREQ# PERT# GN GN 9 GN GN GN GN GN GN 9 GN GN GN 0 GN 0 GN GN LK_PIE_WWN 0 LK_PIE_WWN# 0 PIE_RXN_R PIE_RXP_R PIE_TXN_R PIE_TXP_R PH_MLK_MINI PH_MT_MIN O R0 PIE_WKE#_ 0RJ--GP PIE_LK_WWN_REQ# 0 L0 FILTER--GP R09 0RJ--GP R 0RJ--GP PIE_WKE# 9,,, PLT_RT#,,,,,,,,,,,9,0 mt 0UVKX-GP T_RXP 0UVKX-GP T_RXN mt RN0J--GP PIE_RXN 0 PIE_RXP 0 G RN0 G 9/ PORT-->PORT RN0J--GP PIE_TXN 0 PIE_TXP 0 RN0 mt 0UVKX-GP 0UVKX-GP mt 9/9 FOR RF U_PN U_PP 9/ PH_MLK,,0,9 hange GLN Main/nd source - 0 PH_MT,,0,9 T_TXP T_TXN G_EN V_MINI_0_R MINI_EN R 0RJ--GP G R V_MINI_0 0KRJ--GP -_00 G IM EMI request UIM_LK E0 P0VJN-GP P0VJN-GP bios.ru G 0 UVKX-GP TP-OP-GPTP0 TP0 UIM_PWR UIM_VPP UIM_REET UIM_LK UIM_T V NP NP NP NP VPP REERVE# REERVE# RT LK I/O GN 9 GN 0 GN RU9P--GP 0.I0.00 nd = 0.I0.00 U_PP0 U_PN0 9/ <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. WWN onnector ize ocument Number Rev 0-H - ate: Monday, pril 0, 0 heet of 09

67 (lanking) <ore esign> bios.ru Reserved Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev 0-H - ate: Friday, March 0, 0 heet of 09

68 I = User.Interface LE-O--GP Power button LE TY_LE#_Q FRONT_PWRLE#_Q R0 R0 0RF-GP TY_LE#_R 0RF-GPFRONT_PWRLE#_R V_, PWRLE -_00 Q0 FRONT_PWRLE#_Q R R LT0ZU-F-GP nd =.0.0 rd =.00.EK HRGE_LE#_Q _TFULL#_Q R0 R0 0RF-GP 0RF-GP HRGE_LE#_R _TFULL#_R PLE.009.Z0.009.Z0 LE-O--GP V_HRGER _TFULL#_Q TY_LE#_Q HRGE_LE#_Q FRONT_PWRLE#_Q HLE Power TY_LE hange for LE E aps Lock LE E0 E0 E0 E0 U0VKX-GP U0VKX-GP U0VKX-GP U0VKX-GP Q0 TY_LE#_Q TY_LE R R P_LE LT0ZU-F-GP nd =.0.0 rd =.00.EK attery LE(_TFULL) Q0 R0 P_LE# R 0RF-GP R LT0ZU-F-GP nd =.0.0 rd =.00.EK T H LE LE ZENER IOI P_LE#_R K - + LE IE LE--9-GP.009.N0 V_0 hange for LE E Q0 _TFULL#_Q _TFULL R R LT0ZU-F-GP nd =.0.0 rd =.00.EK attery LE(HRGE) V_0 T_LE# LT0ZU-F-GP R Q09 R T_LE#_ MEI_LE#_R R0 0RF-GP nd =.0.0 rd =.00.EK HLE ZENER IOI K - + LE IE LE--9-GP.009.N0 V_0 HRGE_LE Q0 HRGE_LE#_Q R R LT0ZU-F-GP nd =.0.0 rd =.00.EK for factory test <ore esign> el PWRTN For P Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. LE ard/power utton ize ocument Number Rev ustom 0-H - ate: aturday, March 0, 0 heet of 09 bios.ru

69 I = K TOUH P V_0 V 0 -_00 Internal Keyoard onnector K PTWO-ON--GP 0.K09.0 nd = 0.K0.0 RN90 RN0KJ--GP TPLK TPT UVKX-GP RN90 90 RNJ--GP-U 9/ TP_LK TP_T U_PN U_PP V_0 TP_LEFT TP_RIGHT KROW0 KROW KROW KROW KROW KROW KROW KROW TP E-ON--GP 0.K0.0 nd = 0.K0.0 rd = 0.K0.0 KOL0 KOL KOL KOL KOL KOL KOL KOL KOL KOL9 KOL0 KOL KOL KOL KOL KOL KOL KOL KOL KROW[0..] Rubber ome M PIN EFINE K PIN EFINE KOL[0..] K/ TP_LEFT TP_RIGHT FP ETY-ON--GP 0.K0.00 nd = 0.K0.00 -_00 <ore esign> bios.ru Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Key oard/touch Pad ize ocument Number Rev 0-H - ate: aturday, March 0, 0 heet 9 of 09

70 V_UX_K 00 U0VKX-GP LI PX9HI-TRG-GP LI_LOE# LI_LOE#_ V GN VOUT R00 00RJ--GP 00 0UVKX--GP.09. nd =.0.0 <ore esign> bios.ru Hall ensor Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev 0-H - ate: aturday, March 0, 0 heet 0 of 09

71 modify to test pad V_0,, LP_0,, LP_,, LP_,, LP_,, LP_FRME#,,,,,,,,,,,9,0 PLT_RT# LK_PI_LP 9 0 MLX-ON0--GP <ore esign> bios.ru Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ubug connector ize ocument Number Rev 0-H - ate: aturday, March 0, 0 heet of 09

72 (lanking) <ore esign> bios.ru Reserved Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev 0-H - ate: Friday, March 0, 0 heet of 09

73 (lanking) <ore esign> bios.ru Reserved Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev 0-H - ate: Friday, March 0, 0 heet of 09

74 I = IO /X/M ard Reader X_# 0 _LK _M _# M_IN# X_R X_RE# X_E# X_WE# X_LE/M_ X_LE X_WP#/M_ X_0 X_/M_0 X_/M_ P(N0 _) P(NO _) P(NO ) P(No _) P P P P(NO M_) P9 P0 X_ X_/M_ X_ X_/M_LK X_/_WP P(M_) P P P P 000 R X_/M_LK R0 0R00-P V_R_0 0 P0V-GP _0 # X_/_WP _LK _M X_/M_0 X_WP#/M_ X_/M_ X_/M_ X_LE/M_ M_IN# X_/M_LK_R P P _V M_V X_V P _T0 P _T P _T P9 _T P _ P _WP P _LK P _M P0 M_T0 P9 M_T P M_T P M_T P M_ P M_IN P M_LK NP NP NP NP R-PUH-P--GP 0.I0.00 X_ X_R/ X_RE X_E X_LE X_LE X_WE X_WP_IN X_0 0 X_ X_ X_ X_ X_ X_ X_ M_GN P M_GN P0 X_GN 9 X_GN 9 _GN P _GN P _/WP_OM/IO_GN P _/WP_OM/IO_GN P el nd source X_# X_R X_RE# X_E# X_LE/M_ X_LE X_WE# X_WP#/M_ X_0 X_/M_0 X_/M_ X_ X_/M_ X_ X_/M_LK X_/_WP bios.ru <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. R Reader ONN ize ocument Number Rev 0-H - ate: aturday, March 0, 0 heet of 09

75 I = Expressard For Expresscard socket EXP EXPRER-P--GP-U Neward +.V_R Max. 0m, verage 00m. +.V_R Max. 00m, verage 000m +.V_RUX Max. m EXPRER-P--GP-U NP 0 PIE_TXP 0 PIE_TXN 0 PIE_RXP 0 PIE_RXN 0 V_NEW_0 0 LK_PIE_NEW 9 0 LK_PIE_NEW# PPE# 0 PIE_LK_NEW_REQ# V_NEW_LN_ PERT# 9,,, PIE_WKE# O PIE_WKE#_NEW R0 0RJ--GP V_NEW_0 0 RN0 9 M_T_NEW 0, M_T M_LK_NEW 0, M_LK RNJ--GP-U ONN_TP TP-OP-GPTP TP ONN_TP TP-OP-GPTP TP PUT# U_PP U_PN 9/ for add usb port NP EXP Neward U0 V_0 V_NEW_0 V_0 V_NEW_0 _VIN UXIN _VIN UXOUT _VOUT _VOUT PU# 9 PPE# 0 _VIN _VIN TY# YRT# _VOUT PERT# _VOUT O# 9 HN# 0 RLKEN GN N# GN GR9U-GP V_ V_NEW_LN_ PERT# PUT# PPE# RN0 RN00KJ--GP V_ 0 00P0VJN-GP NEWR_PWR_EN 0 PM_LP_# 9,,9,,,, PLT_RT#,,,,,,,,,,,9,0 Neward Place them Near to hip Place them Near to onnector For EMI V_0 V_NEW_0 V_NEW_0 V_NEW_LN_ 0 UVZY-GP Neward bios.ru 0 U0VZY-GP Neward Neward 0 UVZY-GP 0 U0VZY-GP Neward Neward 0 UVZY-GP 0 UVZY-GP Neward <ore esign> New ard Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev 0-H - ate: aturday, March 0, 0 heet of 09

76 MRT U_PP U_PN V_0 / swap E-ON--GP 9/ for addport 0.K0.00 nd = 0.K09.00 <ore esign> bios.ru Reserved Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev 0-H - ate: aturday, March 0, 0 heet of 09

77 bios.ru <ore esign> Reserved Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev 0-H - ate: Friday, March 0, 0 heet of 09

78 (lanking) <ore esign> bios.ru Reserved Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev 0-H - ate: Friday, March 0, 0 heet of 09

79 I = User.Interface Free Fall ensor Note - no via, trace, under the sensor (keep out area around mm) - stay away from the screw hole or metal shield soldering joints - design P pad based on our sensor LG pad size (add 0.mm) - solder stencil opening to 90% of the P pad size - mount the sensor near the center of mass of the N as possible as you can,9,, ML_LK_,9,, ML_T_ R909 0RJ--GP R90 0RJ--GP ML_LK_G ML_T_G V_0 0 dvs-->v_0,,0, PH_MLK,,0, PH_MT /09 GENOR_INT R9 0R00-P R9 0R00-P ML_LK_G ML_T_G V_0 R90 0KRJ--GP 90 K GENOR_INT_L M0U0--GP FF_INT 0 9 GN INT RE INT V O/0 /I/O U90 V_IO N# N# L/P GN 90 ML_LK_G U0VKX-GP 90 U0VKX-GP V_0 V_0 LIHTR-GP 0?????0ohm R90 0RJ--GP G_ R90 0KRJ--GP R90 0KRJ--GP G_0 R90 0KRJ--GP V_0 R90 0KRJ--GP V_0 G Q90 G_ G_0 ML_T_G FF_INT_L 90 K V_0 00KRF-L-GP R90 H_UNLO bios.ru O="H"; address="h" *O="L"; address="h" *="H"; mode="i" ="L"; mode="pi" R90 0RJ--GP GENOR_INT N00K--GP FTP0.N0.J N =.000.I M0U0--GP <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Free Fall ensor ize ocument Number Rev 0-H - ate: Thursday, March 9, 0 heet 9 of 09

80 (lanking) <ore esign> bios.ru Reserved Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev 0-H - ate: Friday, March 0, 0 heet 0 of 09

81 (lanking) <ore esign> bios.ru Reserved Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev 0-H - ate: Friday, March 0, 0 heet of 09

82 PWRN FF 異異 TNN V_0 V_ 9 0 E-ON--GP 0.K0.0 nd = 0.K0.0 rd = 0.K0.0 hange TNN main source 0 - KUP_TN# INTNT_VIEW_TN# MUTE_TN# K_PWRTN# PowermartTN# NUMLOK_LE PWRLE, -_00 PowermartLE MUTE_LE KUP_LE 0 U0_TXP U0_TXN U0_TXN U0_TXP U0_RXP U0_RXN U0_RXP U0_RXN U0_TXP U0_TXN U0_RXP U0_RXN E-ON0-9-GP UN 0.K0.00,,,,,,,,,,,9,0 PLT_RT# 9, PM_LKRUN# bios.ru V_ V_0 TPMN 9 FOX-ONN-GP 0 0.F90.0 nd = 0.F0.0 dd N ource 0 V_ R0 0KRJ--GP INT_ERIRQ, R0 LPP# LP_0,, 0RJ--GP LP_,, LP_FRME#,, LK_PI_K, LP_,, LP_,, U_TT# 9 / / V_U_ 00 V_HRGER V_0 U_PP0 U_PN0 U_PP U_PN U_PP U_PN U_HRGER_PORT_EN# WIRELE_W# WLN_TET_LE G_LE ILIM_EL 9,,9,,,, PM_LP_# U_HRGER_TL U_HRGER_TL 9 U_PK_R- 9 U_PK_R+ E-ON0-9-GP-U 0.K00.00 nd = 0.K00.00 Main source change to E 0.K UN <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IO oard onnector ize ocument Number Rev 0-H - ate: aturday, March 0, 0 heet of 09

83 V_VG_0 0V_VG_0 V_VG_0 Vendor ask to change property GPU_HOL_RT#,,,,,,,,,,,9,0 PLT_RT# GPU_HOL_RT# PLT_RT# dgpu reset N00K--GP G 0 PEG_LKREQ# Q0.N0.J nd =.000.I VG_RT# PEG_LKREQ#_ 0 LK_PIE_VG 0 LK_PIE_VG# PEG_RXP0 0 U0VKX-GP PEG RXP0 PEG_RXN0 0 U0VKX-GP PEG RXN0 PEG_TXP0 PEG_TXN0 PEG_RXP 0 U0VKX-GP PEG RXP PEG_RXN 0 U0VKX-GP PEG RXN PEG_TXP PEG_TXN PEG_RXP 0 U0VKX-GP PEG RXP R VG_RT# PEG_RXN 0 U0VKX-GP PEG RXN 00RJ--GP R0 PEG_TXP PEG_TXN 00RJ--GP R0 00KRJ--GP PEG_RXP 0 U0VKX-GP PEG RXP PEG_RXN 0 U0VKX-GP PEG RXN U0 V_VG_0 PEG_TXP PEG_TXN V VG_RT# PEG_RXP 09 U0VKX-GP PEG RXP Y PEG_RXN 0 U0VKX-GP PEG RXN GN LVG0GW--GP PEG_TXP.0G0.L0 PEG_TXN PX_Muxless PEG_RXP U0VKX-GP PEG RXP PEG_RXN U0VKX-GP PEG RXN PEG_TXP PEG_TXN PEG_RXP U0VKX-GP PEG RXP PEG_RXN U0VKX-GP PEG RXN PEG_TXP PEG_TXN PEG_RXP U0VKX-GP PEG RXP PEG_RXN U0VKX-GP PEG RXN PEG_TXP PEG_TXN PEG_RXP U0VKX-GP PEG RXP PEG_RXN U0VKX-GP PEG RXN PEG_TXP PEG_TXN PEG_RXP9 9 U0VKX-GP PEG RXP9 PEG_RXN9 0 U0VKX-GP PEG RXN9 PEG_TXP9 PEG_TXN9 R0 0KRJ--GP VG / PI_EXPRE J PEX_WKE# J PEX_RT# K PEX_LKREQ# L PEX_REFLK K PEX_REFLK# K PEX_TX0 J PEX_TX0# N PEX_RX0 M PEX_RX0# H PEX_TX G PEX_TX# N PEX_RX M PEX_RX# K PEX_TX J PEX_TX# P PEX_RX P PEX_RX# L PEX_TX K PEX_TX# N PEX_RX M PEX_RX# K PEX_TX J PEX_TX# N PEX_RX M PEX_RX# H PEX_TX G PEX_TX# P PEX_RX P PEX_RX# K PEX_TX J PEX_TX# N PEX_RX M PEX_RX# L9 PEX_TX K9 PEX_TX# N0 PEX_RX M0 PEX_RX# K0 PEX_TX J0 PEX_TX# P0 PEX_RX P PEX_RX# H0 PEX_TX9 G0 PEX_TX9# N PEX_RX9 M PEX_RX9# OF PEX_IOV_ PEX_IOV_ PEX_IOV_ PEX_IOV_ PEX_IOV_ PEX_IOV_ PEX_IOVQ_ PEX_IOVQ_ PEX_IOVQ_ PEX_IOVQ_ PEX_IOVQ_ PEX_IOVQ_ PEX_IOVQ_ PEX_IOVQ_ PEX_IOVQ_9 PEX_IOVQ_0 PEX_IOVQ_ PEX_IOVQ_ PEX_IOVQ_ PEX_IOVQ_ PEX_PLL_HV PEX_V_V V_ENE GN_ENE G9 G G G H H 0UVKX-GP 0UVMX-GP 0UVKX-GP U0VKX-GP UVKX-GP UVKX-GP 0UVMX-GP UVMX-GP V_VG_0 Near GPU. VGORE_V_ENE 9 VGORE_GN_ENE 9 U Under GPU U0VKX-GP.U NER TO GPU 0U mid TO GPU 0V_VG_0 G G G G G H H 0 H H J K L M N H G L L 0UVMX-GP UVKX-GP U0VKX-GP 0UVMX-GP UVMX-GP 0UVMX-GP 0UVMX-GP.V +/- % 0m (ee NV G) U Under GPU.U NER TO GPU 0U mid TO GPU PEG_RXP0 U0VKX-GP PEG RXP0 K PEG_RXN0 U0VKX-GP PEG RXN0 J PEG_TXP0 N PEG_TXN0 M PEX_TX0 PEX_TX0# PEX_RX0 PEX_RX0# N_VUX P PEG_TXP[0..] PEG_TXN[0..] PEG_RXP[0..] PEG_RXN[0..] PEG_RXP U0VKX-GP PEG RXP L PEG_RXN U0VKX-GP PEG RXN K PEG_TXP P PEG_TXN P PEG_RXP U0VKX-GP PEG RXP K PEG_RXN U0VKX-GP PEG RXN J PEG_TXP N PEG_TXN M PEG_RXP U0VKX-GP PEG RXP H PEG_RXN U0VKX-GP PEG RXN G PEG_TXP N PEG_TXN M PEG_RXP 9 U0VKX-GP PEG RXP K PEG_RXN 0 U0VKX-GP PEG RXN J PEG_TXP P PEG_TXN P PEX_TX PEX_TX# PEX_RX PEX_RX# PEX_TX PEX_TX# PEX_RX PEX_RX# PEX_TX PEX_TX# PEX_RX PEX_RX# PEX_TX PEX_TX# PEX_RX PEX_RX# PEX_TTLK_OUT PEX_TTLK_OUT# PEX_PLLV TETMOE J K G VR0VIEO_PEX_PLLV R0 9 0 TETMOE UVKX-GP K 0KRJ--GP U0VKX-GP U0VKX-GP.0V +/- % 0m (ee NV G) 0V_VG_0 L0 LM-GP HIP E LMGN PEG_RXP U0VKX-GP PEG RXP L PEG_RXN U0VKX-GP PEG RXN PEX_TX K PEX_TX# PEG_TXP N PEG_TXN PEX_RX M PEX_RX# NP-G--GP PEX_TERMP P9 R0 PEX_TERMP K9RF-GP U Under GPU U,.U NER TO GPU bios.ru.0np.00u <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. GPU_PIE/TRPPING(/) ize ocument Number Rev 0-H - Thursday, March 9, 0 ate: heet of 09

84 VGK / IFP OF V_VG_0.0V +/- % 0m (ee NV G) 0V_VG_0 0ohm@00MHz R=0.0 L0 LMPGN-GP I_PX.V +/- % I_PX 0m (ee NV G) Near GPU 0ohm@00MHz ER=0. R=0.09 I_PX L0 LMPGN-GP I_PX UVKX-GP 0 0 I_PX UVKX-GP 0 Near GPU U0VKX-GP U0VKX-GP UVKX-GP I_PX 0 Under GPU IFP_RET IFP_IOV Missed x 0.uF R0 KRF--GP IFP_PLLV J H G G9 R0 0KRJ--GP VGJ / IFP LL PIN N FOR GF IFP_RET IFP_PLLV IFP_IOV IFP_IOV IFP NP-G--GP.0NP.00U LV 0 OF IFP_TX# IFP_TX IFP_TX0# IFP_TX0 IFP_TX# IFP_TX IFP_TX# IFP_TX IFP_TX# IFP_TX IFP_TX# IFP_TX IFP_TX# IFP_TX IFP_TX# IFP_TX IFP_TX# IFP_TX IFP_TX# IFP_TX GPIO N M N P M N K L H J H9 J9 P P L M M N L K N GPU_LV_TX# 9 GPU_LV_TX 9 GPU_LV_TX0# 9 GPU_LV_TX0 9 GPU_LV_TX# 9 GPU_LV_TX 9 GPU_LV_TX# 9 GPU_LV_TX 9 IFPE_PLLV_PWR R0 IFP_RET KRF--GP I_PX I_PX IFP_IOV_PWR I_PX U0VKX-GP Under GPU. IFPE_PLLV_PWR R0 IFP_RET KRF--GP I_PX I_PX U0VKX-GP U0VKX-GP IFP_IOV_PWR 0 I_PX Under GPU. 0 I_PX U0VKX-GP U0VKX-GP Under GPU. LL PIN N FOR GF F IFP_RET VI/HMI F IFP_PLLV IW_ IW_L TX TX IFP IFP TX0 HMI TX0 TX TX TX TX F IFP_IOV NP-G--GP VGL / IFP LL PIN N FOR GF N IFP_RET VI/HMI G IFP_PLLV IX_ IX_L TX TX TX0 ep TX0 TX TX TX TX P G IFP_UX_IW_# G IFP_UX_IW_L G IFP_L# G IFP_L H IFP_L# H IFP_L J IFP_L# J IFP_L J IFP_L0# K IFP_L0 P GPIO OF P K IFP_UX_IX_# K IFP_UX_IX_L K IFP_L# K IFP_L L IFP_L# L IFP_L M IFP_L# M IFP_L M IFP_L0# M IFP_L0 GPU_P_ GPU_P_L GPU_P_T# GPU_P_T# GPU_P_T GPU_P_T GPU_P_T0# GPU_P_T0# GPU_P_T0 GPU_P_T0 GPU_P_T# GPU_P_T# GPU_P_T GPU_P_T GPU_P_T# GPU_P_T# GPU_P_T GPU_P_T GPU_P_HP GPU_eP_UX# 0 GPU_eP_UX 0 GPU_eP_T# 0 I_PX GPU_eP_T 0 GPU_eP_T0# 0 GPU_eP_T0 0 GPU_eP_UX GPU_eP_UX# R 00KRJ--GP I_PX R9 00KRJ--GP V_VG_0 IFPE_PLLV_PWR VGM OF / IFPEF LL PIN N FOR GF VI-L VI-L/HMI P IY_ IY_ IFPE_UX_IY_# IY_L IY_L IFPE_UX_IY_L IFPEF_PLLV GPU_EP_UX# GPU_EP_UX GPU_EP_UX# GPU_EP_UX I_PX 0 U0VKX-GP Under GPU. G IFP_IOV NP-G--GP.0NP.00U GPIO M 0 GPU_eP_HP_ GPU_eP_HP PX_EP R 0KRJ--GP PX_EP Q0 N00KW-GP.N0.F V_VG_0_ R PX_EP 0KRJ--GP V_VG_0 I_PX U0VKX-GP I_PX U0VKX-GP R0 IFPEF_RET KRF--GP I_PX 0 Under GPU. IFP_IOV_PWR IFPEF_RET IFPE TX TX TX0 TX0 TX TX TX TX HP_E P TX TX TX0 TX0 TX TX TX TX HP_E IFPE_L# IFPE_L IFPE_L# IFPE_L IFPE_L# IFPE_L IFPE_L0# IFPE_L0 GPIO R GPU_EP_T# GPU_EP_T GPU_EP_T# GPU_EP_T GPU_EP_T# GPU_EP_T GPU_EP_T0# GPU_EP_T0 GPU_EP_T# GPU_EP_T GPU_EP_T# GPU_EP_T GPU_EP_T# GPU_EP_T GPU_EP_T0# GPU_EP_T0 GPU_P_HP.0V +/- % m (ee NV G) 0V_VG_0 0ohm@00MHz ER=0.0 L0 IFP_IOV_PWR.V +/- % 0m (0m each, max links) (ee NV G) V_VG_0 00ohm@00MHz ER=0. L0 IFPE_PLLV_PWR I_PX 9 U0VKX-GP Under GPU. IFPE_IOV IFPF_IOV IFPF TX TX TX TX TX TX IZ_ IZ_L TX TX TX0 TX0 TX TX TX TX IFPF_UX_IZ_# IFPF_UX_IZ_L IFPF_L# IFPF_L IFPF_L# IFPF_L IFPF_L# IFPF_L IFPF_L0# IFPF_L0 F F F G F F E E GPU_EP_UX# I_PX R 00KRJ--GP GPU_EP_UX R 00KRJ--GP I_PX M00-R0-GP I_PX UVKX-GP I_PX U0VKX-GP Near GPU. 9 I_PX M00-R0-GP I_PX UVKX-GP I_PX U0VKX-GP Near GPU. I_PX U0VKX-GP 0 U0VKX-GP U0VKX-GP I_PX I_PX I_PX Under GPU. HP_F GPIO9 P NP-G--GP bios.ru.0np.00u <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. GPU Memory(/) ize ocument Number Rev 0-H - Thursday, March 9, 0 ate: heet of 09

85 EP 0 VG / F OF VG / F OF OF VG / FVQ tolerance +/- mv tolerance +/- 0mV < 00MHz V_VG_0 For RF - 0,9 M[..0] QM0 QM QM QM 9 QM 9 QM 9 QM 9 QM QP_0 QP_ QP_ QP_ 9 QP_ 9 QP_ 9 QP_ 9 QP_ M0 M M M M M M M M M9 M0 M M M M M M M M M9 M0 M M M M M M M M M9 M0 M M M M M M M M M9 M0 M M M M M M M M M9 M0 M M M M M M M M M9 M0 M M M L F_0 M9 F_ L9 F_ M F_ N F_ P9 F_ R9 F_ P F_ J F_ H9 F_9 J9 F_0 H F_ G9 F_ E F_ E F_ F0 F_ F_ F_ F_ F_9 F F_0 F F_ H F_ H F_ P F_ P F_ P F_ P F_ L F_ L F_9 L F_0 L F_ G F_ F9 F_ G9 F_ F F_ 0 F_ 9 F_ 9 F_ F_9 J9 F_0 K9 F_ J0 F_ K F_ M9 F_ M F_ N9 F_ M0 F_ N F_ N F_9 P0 F_0 P F_ M F_ L F_ K F_ K F_ F_ F_ 0 F_ F_9 F F_0 G F_ G F_ G F_ P0 F_QM0 F F_QM F F_QM M F_QM F_QM L9 F_QM M F_QM F F_QM M F_Q_WP0 G F_Q_WP E F_Q_WP M F_Q_WP E F_Q_WP K0 F_Q_WP N F_Q_WP F F_Q_WP F_LMP F_LL_V F_M0 F_M F_M F_M F_M F_M F_M F_M F_M F_M9 F_M0 F_M F_M F_M F_M F_M F_M F_M F_M F_M9 F_M0 F_M F_M F_M F_M F_M F_M F_M F_M F_M9 F_M0 F_M F_M_RFU0 F_M_RFU F_EUG0 F_EUG F_LK0 F_LK0# F_LK F_LK# 90,9 M[..0] E M0 G9 M F_0 E9 M F_ G M F_ F9 M F_ F F_PLLV_mil M F_ K G M F_ F M F_ G M F_ G M9 F_ F M0 F_9 E M F_0 F M F_ F M F_ G M F_ E M F_ F M F_ Place close to all M F_ M F_ M9 F_ M0 F_9 M F_0 M F_ M F_ M F_ M F_ M F_ M F_ M F_ M9 F_ M0 F_9 M F_0 M F_ F M F_ U0 -F_0 0 NV G M F_ F_M0 -F_0 90 T E E M F_ F_M 0 NV U9 G F F_OT0 M F_ F_M F_OT0 90 R F_KE0 M F_ F_M F_KE0 90 R E F_,9 M F_ F_M F_ 90,9 U G F_RT,9 M9 F_ F_M F_RT 90,9 U F F_9,9 M0 F_9 F_M F_9 90,9 U G G F_,9 M F_0 F_M F_ 90,9 V F F_,9 M F_ F_M F_ 90,9 V9 G E F_0,9 M F_ F_M9 F_0 90,9 V0 E F_,9 M F_ F_M0 F_ 90,9 U E9 F_,9 M F_ F_M F_ 90,9 U F9 F_0,9 V_VG_0 M F_ F_M F_0 90,9 V E0 -F_WE,9 M F_ F_M -F_WE 90,9 V 0 M F_ F_M Y -F_,9 M9 F_ F_M -F_ 90,9 R0 -F_ 9 M0 F_9 F_M -F_ 9 9 E F_L_P_VQ M F_0 F_M F 0RF-GP F_OT 9 M F_ F_M F_OT F_KE 9 M F_ F_M9 F_KE F_L_PU_GN F_,9 M F_ F_M0 F_ 90,9 9 F_,9 M F_ F_M F_ 90,9 9 F_,9 M F_ F_M F_ 90,9 Y G F_L_TERM_GN F_,9 M F_ F_M F_ 90,9 Y9 G F_,9 M F_ F_M F_ 90,9 W F F_,9 M9 F_ F_M F_ 90,9 Y0 F_,9 M0 F_9 F_M F_ 90,9 F_,9 M F_0 F_M F_ 90,9 Y F_,9 M F_ F_M F_ 90,9 Y F_0,9 M F_ F_M9 F_0 90,9 Y R0 -F_R,9 F_ F_M0 -F_R 90,9 V E F_M R0 R 90 QM0 E F_QM0 F_M_RFU0 90 QM E 0 F_QM F_M_RFU V_VG_0 90 QM F_QM 90 QM 9 F_QM V_VG_0 9 QM F F_QM 9 QM F F_QM 9 QM 0 F_EUG0 F_QM R R 9 QM G F_EUG0 R0 F_EUG R9 F_QM F_EUG0 0RF-GP G0 F_EUG R 0RF-GP 0RF-GP F_EUG 0RF-GP 90 QP_0 0 F_Q_WP0 90 QP_ F_Q_WP R0 LK0 90 QP_ F_Q_WP F_LK0 LK0 90 R LK0# 90 QP_ 9 E F_Q_WP F_LK0# LK0# 90 LK 9 9 QP_ E E0 F_Q_WP F_LK LK 9 LK# 9 9 QP_ E F0 F_Q_WP F_LK# LK# 9 9 QP_ 0 F_Q_WP 9 QP_ F_Q_WP U0VKX-GP 0RF-GP 0RF-GP FVQ_ 0 FVQ_ FVQ_ FVQ_ FVQ_ FVQ_ E FVQ_ F FVQ_ G FVQ_9 FVQ_0 FVQ_ 9 FVQ_ E FVQ_ E FVQ_ E9 FVQ_ H0 FVQ_ H FVQ_ H FVQ_ H FVQ_9 H FVQ_0 H FVQ_ H FVQ_ H FVQ_ H9 FVQ_ H0 FVQ_ H FVQ_ H FVQ_ H FVQ_ H FVQ_9 H FVQ_0 H9 FVQ_ L FVQ_ M FVQ_ N FVQ_ P FVQ_ R FVQ_ T FVQ_ T0 FVQ_ T FVQ_9 V FVQ_0 W FVQ_ W0 FVQ_ W FVQ_ Y FVQ_ F F_VQ_ENE F F_GN_ENE J F_L_P_VQ H F_L_PU_GN H F_L_TERM_GN NP-G--GP.0NP.00U U0VKX-GP U0VKX-GP U0VKX-GP UVKX-GP s Under GPU. U0VKX-GP U0VKX-GP U0VKX-GP 0UVKX-GP U0VKX-GP U0VKX-GP UVKX-GP 0UVKX-GP 0UVKX-GP UVKX-GP UVKX-GP UVKX-GP F0 F0 P0VJN-GP UVKX-GP QN_0 QN_ QN_ QN_ QN_ QN_ QN_ QN_ M0 F_Q_RN0 H0 F_Q_RN E F_Q_RN M F_Q_RN F0 F_Q_RN K F_Q_RN M F_Q_RN F F_Q_RN THE F_WKxx PIN RE UE ONLY ON GK0 THEY RE N FOR GF0 N FOR GF K F_WK L0 F_WK# H F_WK J F_WK# G0 F_WK G F_WK# J F_WK K F_WK# J0 F_WK J F_WK# J F_WK J F_WK# H F_WK J F_WK# J F_WK J F_WK# 0ohm@00MHz R=0.0 L0.0V +/- % 00m (ee NV G) 0V_VG_ QN_0 QN_ QN_ QN_ QN_ QN_ QN_ QN_ 9 F_Q_RN0 E F_Q_RN F_Q_RN 9 F_Q_RN F_Q_RN F_Q_RN 0 F_Q_RN F_Q_RN THE F_WKxx PIN RE UE ONLY ON GK0 THEY RE N FOR GF0 N FOR GF F F_WK E F_WK# F_WK F_WK# F_WK F_WK# F_WK F_WK# F_WK F_WK# F_WK F_WK# F F_WK E F_WK# F_WK F_WK# H F_VREF NP-G--GP.0NP.00U U F_PLL_V U0VKX-GP F_PLLV_mil H0KF-00T0-GP U0VKX-GP UVKX-GP 0UVMX-GP NP-G--GP.0NP.00U H F_PLL_V F_PLLV_mil U0VKX-GP Place close to all Under GPU. Near GPU. LK LK0 Group LK LK0 LK# R0 RF-GP LK0# R0 RF-GP Group R0 RF-GP R0 RF-GP FLK Termination place on VRM side KE0 KE Reset F_KE0 F_KE F_RT F_KE0 F_KE F_RT KE0 KE Reset LK# LK0# FLK Termination place on VRM side OT0 F_OT0 F_OT0 OT0 OT F_OT F_OT OT 0KRJ--GP R0 0KRJ--GP R09 0KRJ--GP R0 0KRJ--GP R 0KRJ--GP R 0KRJ--GP R 0KRJ--GP R 0KRJ--GP R 0KRJ--GP R 0KRJ--GP R bios.ru <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. GPU_P/LV/RT/GPIO(/) ize ocument Number Rev 0-H - Thursday, March 9, 0 ate: heet of 09

86 ER=0.ohm.V +/- % 0m (ee NV G) I_PX 09 U0VKX-GP _VREF _RET I_PX R0 RF-U-GP V_VG_0 V_MIL U0VKX-GP 0 I_PX U0VKX-GP 0 I_PX V_VG_0 0ohm@00MHz ER=0.0 L0 U0VKX-GP 0 I_PX UVKX-GP I_PX M00-R0-GP I_PX 0 Under GPU. Near GPU. VGN OF / GF0/GKx GF GF GF0/GKx G0 R _V N N I_L N R I_ P9 _VREF TEN_VREF P M9 _RET N N _HYN N N9 _VYN N K9 _RE N _GREEN L0 N L9 _LUE NP-G--GP.0NP.00U V_VG_0 RN0 RNKJ--GP I_PX VG_RT_LK 9 VG_RT_T 9 VG_RT_HYN 9 VG_RT_VYN 9 VG_RT_RE 9 VG_RT_GREEN 9 VG_RT_LUE 9 RN0 VG_RT_LUE VG_RT_GREEN VG_RT_RE RN0J--GP I_PX 0V_VG_0.0V +/- % 0m (ee NV G) 0V_VG_0 0ohm@00MHz R=0.0 PLLV_PWR P_PLLV_PWR 0ohm@00MHz ER=0. R=0.09 L0 LMPGN-GP 0 0UVMX-GP L0 H0KF-00T0-GP U0VKX-GP U0VKX-GP 0 Near GPU. TP-OP-GPTP09 TP09 U0VKX-GP 0 VIEO_LK_XTL_ R0 0KRJ--GP E H H MHZ_IN VGO / XTL_PLL PLLV P_PLLV VI_PLLV GF0/GKx XTL_IN XTL_IN NP-G--GP.0NP.00U 0 P0VJN--GP R0 MRJ--GP N GF R0 90RJ--GP MHZ_OUT_R X0 XTL-MHZ--GP-U.00.0 nd =.00. OF XTL_OUTUFF XTL_OUT J H MHZ_OUT P0VJN--GP NP_XTL_OUTUFF R0 0KRJ--GP NVII TLE ROM_I R Hynix G 00 **.Kohm Hynix G 000 ** 00MHZ Kohm..L.0.L amsung G 00 ** 00MHZ 0Kohm.00.L amsung G 0 ** 00MHZ Kohm..L V_VG_0 V_VG_0 RN0 RNKJ--GP M_THERM_NV M_THERM_NV M_THERM_NV,9,,9 ML_T_ /09 Q0 N00KW-GP.N0.F nd =.N0.FF M_THERM_NV ML_LK_,9,,9 V_VG_0 /09 V_VG_0 NVII TLE NP-G EV I: 0x0F NP-G-E EV I: 0x0F NP-GL EV I: 0x0E9 VGQ 0/9 MI OF T M_THERM_NV I_L T M_THERM_NV I_ RN0 RNKJ--GP RN RNKJ--GP TRP Kohm.0.L 0Kohm.00.L 0Kohm.0.L R I_L R I_ GPU_LV_LK 9 GPU_LV_T 9 R9 0KRJ--GP R0 0KRJ--GP TP0 TP-OP-GP TP-OP-GPTP0 TP0 TP-OP-GPTP0 TP0 TP-OP-GPTP0 TP0 TP0 THERMN K TP-OP-GP THERMN TP THERMP K TP-OP-GP THERMP NP_JTG_TK M0 NP_JTG_TM JTG_TK P NP_JTG_TI JTG_TM M NP_JTG_TO JTG_TI P NP_JTG_TRT# JTG_TO N JTG_TRT# R I_L R I_ P GPIO0 M GPIO L GPIO P GPIO P GPIO L GPIO M GPIO N GPIO M GPIO M GPIO9 L GPIO0 M GPIO N GPIO M GPIO R GPIO P GPIO0 P GPIO I_L I_ TP0 TP-OP-GP NP_GPIO GPIO_OVERT# GPIO9_LERT# GPUHOT# NP_GPIO NP_GPIO 9 V_VG_0 R H_VI 9 0KRJ--GP H_VI 9 R09 R0 VG_LKLT_TL 9 0KRJ--GP VG_LV_EN VG_LEN 9 H_VI 9 H_VI 9 H_VI0 9 H_VI 9 V_VG_0 0KRJ--GP GPUHOT# 9 R0 0RJ--GP - 0 Q0 9/ NP-G--GP OVERT#_G G TRP0 TRP TRP TRP TRP TRP_REF0_GN J J J J J.0NP.00U V_VG_0 VGP OF / MI R 0KRJ--GP H ROM_# ROM_# H ROM_I ROM_I ROM_O ROM_O H H ROM_LK TRP0 ROM_LK TRP TRP V_VG_0 TRP TRP R L 0KRJ--GP UFRT# J L NP_E MULTI_TRP_REF0_GN E GPIO_OVERT# R GPIO_OVERT#_R 0RJ--GP N00K--GP.N0.J I_PX GPUHOT GPUHOT_R G R9 0RJ--GP Q0 N00K--GP.N0.J I_PX I_PX GPU_LRM GPU_LRM_R G R 0RJ--GP Q0 N00K--GP.N0.J PURE_HW_HUTOWN#,, GPUHOT# GPIO9_LERT# ROM_I ROM_O ROM_LK TRP0 TRP TRP TRP TRP PH PH PH PL PH NP_G 0K ohm.99k ohm K.ohm.K ohm 0K ohm E PH PL PH PL PH NP_GL 0K ohm K ohm K.ohm.K ohm 0K ohm TRP GIO_PFG[0]=0 GIO_PFG[]= TRP0 UER[0]= GIO_PFG[]= UER[]= UER[]= UE (K) GIO_PFG[]=0 UER[]= TRP PI_EVI[0]= PI_EVI[]= PI_EVI[]= PI_EVI[]= PH PL K ohm 0K ohm PH PL K ohm 0K ohm UE 00 (K) NP-G E: (0) NP-GL: (00) I_PX R 0KRF-GP NP-G--GP V_VG_0 V_VG_0 bios.ru R0 KRF-L-GP TRP0 TRP TRP R KRJ--GP V_VG_0 R KRF--GP R K99RF-L-GP NP-G/GL=K R 0KRF-L-GP NP-GE/ GL=0K R KRF-GP NP-GQ NP-G TRP TRP R KRF-GP R0 KRF-GP R9 K99RF-L-GP ROM_I ROM_O R ROM_LK KRF-L-GP NP-GQ/E=0K R KRF--GP R KRF--GP NP-G R 0KRF--GP R 0KRF--GP NP-GL R K99RF-L-GP NP-G R KR-GP NP-GL <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. GPU_POWER(/) ize ocument Number Rev 0-H - Thursday, March 9, 0 ate: heet of 09