ME3 Block Diagram HDD G792 ICH8-M. Project code : 91.4X PCB P/N : Revision : PCB LAYER LPC DEBUG CONN. TPM SLB9635TT KBC. Intel CPU.

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1 M lock iagram RII lot 0 RII lot Power witch RJ ONN Line In INT.PKR Line Out (PIF) RJ INT. MI rray igital HMI (PIF),, Mini ard_ Robson Mic In -T ONN RII hannel RII hannel MP MP MOM -T IL 0/00 ontroller Realtek RTL0 M ard odec L LK N RLTK RTM New card odec L Mini ard_ 0.a/b/g/n ZLI PI- x PI- x PI- x ZLI T H T 0 Intel PU Meron M/M V F: or 00 MHz,, ROM Host U /MHz restline-m/ml TL+ PU I/F R I/F INTRT RHPI LV, RT I/F,,,0,, INTL IH-M MI I/F 00MHz 0 U.0/. ports THRNT (0/00/000Mb) High efinition udio T /00 PI. LP I/F PI/PI RI,,0, PT 0 PI x MHz.KHz PITY UTTON nvii NM- U.0 K,, R raphics RM -Mbit, Winbond WP Touch INT. Pad K Project code :.X0.00 P P/N : Revision : Finger print amera RF U X Realtek RTL LP U.KHz PI Flash Rom WX0- or TPM LTT.KHz TV OUT RT L HMI M/M Pro/x/ MM/ in PROM lue tooth LP U ONN. lock iagram ize ocument Number Rev M-iscrete ate: Monday, July 0, 00 heet of YTM / TP0 INPUT TOUT OUTPUT V_ V_ YTM / MX INPUT TOUT OUTPUT 0V_0 V_ YTM / FN INPUT TOUT MXIM HRR MX INPUT OUTPUT T+ TOUT V.0 V 00m PU / MXTL INPUT TOUT OUTPUT V_OR_0 OUTPUT V_OR 0.~.V P LYR L: ignal L: N L: ignal L: ignal L: L: N V L: ignal L: ignal L: N L0: ignal Prepare by teven F hou Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O..

2 INTL IH-M TRP PIN ignal H_OUT 0 nter XOR hain Hole,pring Rising dge of PWROK pulled low at rising edge of PWROK,sets bit of HMI:.0.0 H_YN NT# PIO0 NT# NT0# PI_# INTVRMN Reserved integrated VccLan_0VccL_0 LN00_LP TL# PKR TP PIO/ H_OK_N# Usage/When ampled XOR hain ntrance/ PI Port onfig bit, PI Port onfig bit0, Rising dge of PWROK. PI Port onfig bit0, Rising dge of PWROK. Top-lock wap Override. Rising dge of PWROK. oot IO estination election. Rising dge of PWROK. Integrated Vccus_0 Vccus_ and VccL_ VRM nable/isable.lways sampled. Integrated VccLN_0 VccL_0 VRM enable /isable. lways sampled. PI LN RVRL.Rising dge of PWROK. No Reboot. Rising dge of PWROK. XOR hain ntrance. Rising dge of PWROK. Flash escriptor ecurity Override trap Rising dge of PWROK. INTL RTLIN TRP PIN F trap LOW 0 HIH F MI X MI X F Low Power PI xpress Normal Low Power mode F PI xpress raphics Lane Reversal Normal Mode(Lanes Lane Reversal number in order) F F ynamic OT isabled nabled F MI Lane Reserved Normal Operation Reserved Lane F 0 oncurrent VO/PI Only PI or VO is operation PI and VO are operation simultaneous VO_TRL_T NO VO ard VO ard Present Present VO Present F XOR/LL-Z F PI_MIO PULL-UP 0K Wistron orporation LL(00) LH(0) HL(0) HH() Reserved XOR Mode nabled ll Z Mode nabled Normal Operation omment llows entrance to XOR hain testing when TP pulled low at rising edge of PWROK.When TP not RP.P(onfig Registers:offset h) ets bit0 of RP.P(onfig Registers:Offset h) ets bit of RP.P(onfig Registers:Offset h) Weak Internal PULL-OWN.NOT:This signal should not be pull HIH. ampled low:top-lock wap mode(inverts for all cycles targeting FWH IO space). Note: oftware will not be able to clear the Top-wap bit until the system is rebooted without NT# being pulled down. ontrollable via oot IO estination bit (onfig Registers:Offset 0h:bit :0). NT0# is M, 0-PI, 0-PI, -LP. nables integrated Vccus_0,Vccus_ and VccL_ VRM when sampled high nables integrated VccLN_0,VccL_0 VRM when sampled high This signal has weak internal pull-up. set bit of MP.LR(evice:Function0:Offset ) If sampled high, the system is strapped to the "No Reboot" mode(ihm will disable the TO Timer system reboot feature). The status is readable via the NO ROOT bit.(offset:0h:bit) This signal should not be pull low unless using XOR hain testing. Internal Pull-Up.If sampled low,the Flash escriptor ecurity will be overidden.if high,the ecurity measures defined in the Flash escriptor will be in.k PULL HIH effect. This should only be used in manufacturing environments XOR hain ntrance trap IH_RVtp 0 Z_OUT_IH 0 0 swap override strap PI_NT# OOT IO trap PI_NT#0 PI_# 0 0 LN00_LP FUL HIH No Reboot trap PKR LOW = efaule High=No Reboot escription RV Normal Operation(default) et PI port cofig bit low = swap override enable high = default OOT IO Location PI PI LP(efault) integrated Vccus_0,Vccus_,VccL_ M_INTVRMN High=nable Low=isable M: 00 L: 0 FP: 0 udio: 0 U: 0 High=nable Low=isable INTL IH-M INTRT PULL-UP and PULL-OWN INL H_IT_LK H_RT# H_IN[:0] H_OUT H_YN NT[:0] PIO[0] L[:0]#/FHW[:0]# LN_RX[:0] LRQ[0] LRQ[]/PIO PM# PWRTN# TL# PI_# PI_LK PI_MOI TH_[:0] PKR TP[] U[:0][P,N] L_RT# Resistor Type/Value PULL-OWN 0K NON PULL-OWN 0K PULL-OWN 0K PULL-OWN 0K PULL-UP 0K PULL-OWN 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-OWN 0K PULL-UP 0K PULL-OWN K T U :.0NM.00U (V) U: (udio) U:.0.0 (K) U:.00.0 (LN) U:.IHM.0U () U:.PM.0U (N) TV:.00.H <ore esign> ize ocument Number Rev M-iscrete ate: Friday, eptember, 00 heet of F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Table of ontent

3 V_0 V_0_K0 L ML-00--P 0 Y 0 Y V_0_K0 V_0_K0_IO U0VKX-P 0U0VZY-P UVZY-P UVZY-P UVZY-P LK_XTL_IN X LK_XTL_OUT X-M-P V_0 R V_0 0R-0-U-P U0VKX-P UVZY-P UVZY-P 0 LKTRQ# LKRQ#_ PLK_FWH LK_PI_T PLK_K LK_PI_IH 0 LK_M_IH V_0_K0 PI_TM R 0KRJ--P Y UVZY-P UVZY-P V_0_K0_IO 0U0VZY-P P0VN-P 0 P0VN-P 0 0 LK_M_IH 0 H_TP_PI# 0 H_TP_PU#,,0 IH_MLK,,0 IH_MT P0VN-P P0VN-P K_PWR LK_XTL_IN LK_XTL_OUT F R0 RJ--P PI_TM _L ITP_N F F V_0_K0 PU_LK RN0J--P PU_LK# RN MH_LK RN0J--P MH_LK# RN PU_XP RN0J--P PU_XP# RN RN R Y PI_MINI PI_MINI# RN RN0J--P MH_PLL MH_PLL# RN0J--P PI_IH RN0 PI_IH# RN0J--P RN PI_T PI_T# MHZ MHZ RFLKP RFLKN RN0J--P RN RNJ--P-U RN RN0J--P LK_PU_LK LK_PU_LK# LK_MH_LK LK_MH_LK# LK_PI_T LK_PI_T# LK_PI_LN LK_PI_LN# LK_PI_MINI LK_PI_MINI# LK_PI_NW LK_PI_NW# V_0 NWR_LKRQ# LK_PI_MINI LK_PI_MINI# LK_MH_PLL LK_MH_PLL# LK_PI_IH 0 LK_PI_IH# 0 LK_PI_T LK_PI_T# V_MHZ V_MHZ P_RFLKP P_RFLKN F_ F_ F_ PU UVZY-P UVZY-P UVZY-P P0VJN-P P0VJN-P L Y ML-00--P Y U0VZY-P R 0KRJ--P UVZY-P P0VN-P 0 R R RJ--P R RJ--P R RJ--P R RJ--P RJ--P U XIN XOUT FL/U PI_TOP#/R- PU_TOP#/R-# LK T K_PWR/P# R#_/PI-0 0 R#_/PI- TM/PI- R-_N/PI- M_L/PI- ITP_N/PIF- FL/TT_MO FL/TT_L/RF RT# RTM-0-LF-P V_RF V_ V_PI V_R V_PU V_PLL V_IO V_PLL_IO V_R_IO V_R_IO V_R_IO V_PU_IO N_ N_PI N_RF N_IO N_R N_R N_R N_PU N_PLL N 0 PU-0 PU-0# 0 PU- PU-# R-/PU_ITP R-#/PU_ITP# PI_LN RN0J--P R-/R#_F PI_LN# R-#/R#_ 0 RN PI_MINI RN0J--P R- PI_MINI# R-# RN PI_NW R-0 PI_NW# R-0# RN RN0J--P R#_H/R- 0 R 0KRJ--P R#_/R-# R- 0KRJ--P R-# R- R-# R#_/R- R#_/R-# R-/T R-#/T# R-/ R-#/ R-0/OT 0 R-0#/OT# R 0KRJ--P V_0_K0 Y R 0KRJ--P ITP_N R 0KRJ--P ITP_N Output 0 R PU_ITP PU_L PU_L PU_L0 0 00M 0 0 M M 0 M R 0KRJ--P R 0R00-P R KRJ--P F F F Y _L R 0KRJ--P _L PIN 0 PIN PIN PIN 0 OTT OT RT/LT_00 RT/LT_00 RT0 R0 M_N M_ R KRJ--P MH_LKL0 esign Note:. ll of Input pin didn't have internal pull up resistor.. lock Request (R) function are enable by registers.. Y integrated serial resistor of differential clock, so put 0 ohm serial resistor in the schematic. R KRJ--P R KRJ--P MH_LKL MH_LKL <Variant Name> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. lock generator Y ize ocument Number Rev M-iscrete ate: Tuesday, ugust, 00 heet of

4 H_#[..] U OF H_T#0 H_RQ#0 H_RQ# H_RQ# H_RQ# H_RQ# H_T# H_0M# H_FRR# H_INN# H_TPLK# H_INTR H_NMI H_MI# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_T#0 H_RQ#0 H_RQ# H_RQ# H_RQ# H_RQ# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_T# H_0M# H_FRR# H_INN# J L L K M N J N P P L P P R M K H K J L Y U R W U Y U R T T W W Y U V W V # # # # # # # 0# # # # # # # T0# RQ0# RQ# RQ# RQ# RQ# # # # 0# # # # # # # # # # 0# # # # # # T# 0M# FRR# INN# TPLK# LINT0 LINT MI# R ROUP 0 R ROUP IH XP/ITP INL ONTROL # NR# PRI# FR# RY# Y# R0# IRR# INIT# LOK# RT# R0# R# R# TRY# HIT# HITM# PM0# PM# PM# PM# PRY# PRQ# TK TI TO TM TRT# R# THRML PROHOT# THRM THRM THRMTRIP# HLK LK0 LK H H F F 0 H F F 0 H_# H_NR# H_PRI# H_FR# H_RY# H_Y# H_R0# H_IRR# H_INIT# H_LOK# H_RT# H_R#0 H_R# H_R# H_TRY# H_HIT# H_HITM# TP TP TP TP TP XP_PM# XP_TK XP_TI XP_TO XP_TM XP_TRT# XP_RT# H_THRM H_THRM H_THRMTRIP# LK_PU_LK LK_PU_LK# H_# H_NR# H_PRI# H_FR# H_RY# H_Y# H_R0# H_INIT#, H_LOK# H_RT# H_R#0 H_R# H_R# H_TRY# TP TP TP TP TP H_HIT# H_HITM# XP_RT# 0 H_THRMTRIP#, LK_PU_LK LK_PU_LK# 0V_0 PU_PROHOT# 0V_0 H_THRM H_THRM H_THRM, H_THRM routing together, Trace width / pacing = 0 / 0 mil TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP0 TP TP TP TP PU_RV0 PU_RV0 PU_RV0 PU_RV0 PU_RV0 PU_RV0 PU_RV0 PU_RV0 PU_RV0 PU_RV0 PU_RV M N T V F RV#M RV#N RV#T RV#V RV# RV# RV# RV# RV# RV#F KY_N RRV -KT-PU layout note:zo = ohm, 0." MX for TLRF layout note : hange R to ohm if using XTP to ITP adapter XP_RT# V_0 original value:-kt-pu 0V_0 XP_TI XP_TM XP_TO XP_PM# 0V_0 XP_TRT# XP_TK R RF--P R RF-L-P PU_PROHOT# R RJ--P R RJ-P TP TP R KRJ--P R RF-L-P R RF-L-P R RF-L-P R0 RF-L-P Y R RJ--P Y Q OP# 0 MMT0WT-P <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Meron(/)-TL+/XP ize ocument Number Rev ustom M-iscrete Wednesday, ugust, 00 ate: heet of

5 H_#[0..] UVKX-P H_TN#0 H_TP#0 H_INV#0 PU_L0 PU_L PU_L H_TN# H_TP# H_INV# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_TN#0 H_TP#0 H_INV#0 H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_TN# H_TP# H_INV# V_PU_TLRF OMP0 TP TP TT TLRF OMP0 R OMP R TP TP TT TT MI OMP U OMP TP TP TT TT OMP R OMP R TT TT OMP Y F R0 TT TT PU_L0 PU_L PU_L PL close to the TT PIN, make sure TT,TT,TT trace routing is reference to N and away other noisy signals PU_L PU_L PU_L PU_L0 00 Y 0 TP TP TP TP 0 0 U OF 0# F # # # F # # # # K # # J 0# J # H # F # K # H # J TN0# H TP0# H INV0# N # K # P # R # L 0# M # L # M # P # P # P # T # R # L # T 0# N # L TN# M TP# N INV# TT F TT TT L0 L L T RP0 T RP -KT-PU T RP T RP # Y # # V # V # V # T # U # U 0# Y # W # Y # W # W # # # TN# Y TP# INV# U # # 0# # # # # 0 # # F # # # 0# # # F # TN# TP# F INV# 0 PRTP# PLP# PWR# PWROO LP# PI# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_TN# H_TP# H_INV# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_TN# H_TP# H_INV# H_PRTP# H_PLP# H_PWR# H_PWROO H_PULP# PI# H_TN# H_TP# H_INV# H_TN# H_TP# H_INV# RF-L-P RF-L-P RF-L-P RF-L-P H_PRTP#,, H_PLP# H_PWR# H_PWROO H_PULP# PI# Resistor Placed within 0." of PU pin. Trace should be at least mils away from any other toggling signal. OMP[0,] trace width is mils. OMP[,] trace width is mils. V_OR_0 U OF V V V V 0 V V V V V V V V V V V V 0 V V V V V V 0 V V V V V V V V V V V V 0 V V V V 0 V V V V V V V V V V V V V V 0 V V V V V V V V V V V V V V V 0 V VP V VP V VP V VP V VP V VP 0 V VP F V VP F V VP F0 V VP F V VP F V VP F V VP F V VP F V VP F0 V VP V V V 0 V V V V VI0 V VI V VI V VI 0 V VI V VI 0 V VI 0 V V V VN V V V N -KT-PU F F0 F F F F F F0 V J K M J K M N N R R T T V W F F F F V_OR_0 R0 R 0R00-P 0R00-P PU_VI0 PU_VI PU_VI PU_VI PU_VI PU_VI PU_VI V_N _N V_N PU_VI[0..] V_N _N R 00RF-L-P-U _N R 00RF-L-P-U lose to PU pin within 00mils 0V_0 Y T 0UVM--P V_0 0UVKX-P V_OR_0 layout note: place near PIN 0U0VZY-P Length match within mils. The trace width/space/other is 0//. 0V_0 lose to PU pin Z0= ohm with in 00mils. R KRF--P V_PU_TLRF R KRF--P 0UVKX-P <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Meron(/)-TL+/PWR ize ocument Number Rev M-iscrete ate: Wednesday, ugust, 00 heet of

6 V_OR_0 U F F F F F F F F F F H H H H J J J J K K K K L L L L M M M M N N N N P OF P P P R R R R T T T T U U U U V V V V W W W W Y Y Y Y F F F F F F F F 0V_0 Place these capacitors on L (North side,econdary Layer) Place these capacitors on L (North side,econdary Layer) UVKX-P UVKX-P V_OR_0 0U0VKX-P 0U0VKX-P UVKX-P 0U0VKX-P 0U0VKX-P 0U0VKX-P 0U0VKX-P Y UVKX-P 0U0VKX-P 0U0VKX-P 0U0VKX-P 0U0VKX-P Y UVKX-P 0U0VKX-P 0U0VKX-P 0U0VKX-P 0U0VKX-P 0 0U0VKX-P Mid Frequencd ecoupling 0 UVKX-P Place these inside socket cavity on L (North side econdary) -KT-PU <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Meron(/)-N&ypass ize ocument Number Rev M-iscrete ate: Monday, July 0, 00 heet of

7 R RF-L-P H_#[0..] 0V_0 H_RT# H_PULP# H_VRF 0V_0 H_VRF H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_WN H_ROMP H_OMP H_OMP# H_RT# H_PULP# H_#0 H_# H_# M H_# H H_# H H_# H_# F H_# N H_# H H_# M0 H_#0 N H_# N H_# H H_# P H_# K H_# M H_# W0 H_# Y H_# V H_# M H_#0 J H_# N H_# N H_# W H_# W H_# N H_# Y H_# Y H_# P H_# W H_#0 N H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# Y H_# H_# H_# H_# H_# J H_# H H_# J H_#0 H_# H_# H H_# J H_# H H_# J H_# H_# J H_# J H_# H_#0 J H_# H H_# H H_# H_ROMP R RF-L-P 0V_0 H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_INV#0 H_INV# H_INV# H_INV# H_TN#0 H_TN# H_TN# H_TN# H_TP#0 H_TP# H_TP# H_TP# H_RQ#0 H_RQ# H_RQ# H_RQ# H_RQ# H_R#0 H_R# H_R# H_WN H_# H_T#0 H_T# H_NR# H_PRI# H_R0# H_FR# H_Y# LK_MH_LK LK_MH_LK# H_PWR# H_RY# H_HIT# H_HITM# H_LOK# H_TRY# H_INV#0 H_INV# H_INV# H_INV# H_TN#0 H_TN# H_TN# H_TN# H_TP#0 H_TP# H_TP# H_TP# H_RQ#0 H_RQ# H_RQ# H_RQ# H_RQ# H_R#0 H_R# H_R# 0, PM_PWROK H_#[..] 0, VT_PWR M_ROMP_VOH M_ROMP_VOL PM_XTT#0 PM_XTT# LKRQ#_ RTLIN-P-U-NF layout note : Route H_OMP and H_OMP# with trace width, spacing and impedance ( ohm) same as F data traces Layout Note : H_ROMP / H_VRF / H_WN trace width and spacing is 0/0 R KRF--P R RF-L-P R0 KRF--P Layout Note : Place within 00 mils of N UVZY-P U OF 0 HOT H_WIN H_ROMP W H_OMP W H_OMP# H_PURT# H_PULP# H_VRF H_VRF H_# J H_# H_# H_# M H_# H_# F H_# L H_#0 H_# H_# K H_# H_# L H_# J H_# H_# K H_# P H_# R H_#0 H_# H0 H_# L H_# H_# M H_# N H_# J H_# H_# H_# H_#0 H_# H_# H_# H_# H_# N H_# H_# H_T#0 H_T#0 H H_T# H_T# 0 H_NR# H_NR# H_PRI# H_PRI# H_R0# H_RQ# F H_FR# H_FR# H_Y# H_Y# 0 LK_MH_LK HPLL_LK M LK_MH_LK# HPLL_LK# M H_PWR# H_PWR# H H_RY# H_RY# K H_HIT# H_HIT# H_HITM# H_HITM# H_LOK# H_LOK# 0 H_TRY# H_TRY# H_INV#0 K H_INV# L H_INV# H_INV# H_TN#0 M H_TN# K H_TN# H_TN# H H_TP#0 L H_TP# K H_TP# H_TP# J0 H_RQ#0 M H_RQ# H_RQ# H_RQ# H H_RQ# H_R#0 H_R# H_R# R 00RF-L-P-U R RF--P UVZY-P Layout Note : Place near pin of N U0VZY-P U0VZY-P V_ R M R M R00 0KRJ--P V_0 MH_LKL0 MH_LKL MH_LKL F[:] have internal pull up F[:] have internal pull down From stro demo schematic 0RJ--P Y R 0UVKX-P 0UVKX-P R 0KRJ--P R 0KRJ--P R 0R00-P R K0RF--P 0 PM_MUY#,, H_PRTP# PM_XTT#0 PM_XTT#, H_THRMTRIP# 0, PRLPVR R KRJ--P R KRF--P R KRF--P PM_POK_R TP TP0 TP00 TP0 TP0 TP TP TP TP0 TP0 TP TP TP F IH_VO_T R KRJ--P R M R M PM_MUY# H_PRTP# PM_XTT#0 PM_XTT# PM_POK_R PLT_RT_R# H_THRMTRIP# PRLPVR P RV#P P RV#P R RV#R N RV#N R RV#R R RV#R M RV#M N RV#N J RV#J R RV#R M RV#M L RV#L M RV#M 0 RV#0 H0 RV#H0 RV# J0 RV#J0 K RV#K F RV#F H0 RV#H0 K RV#K J RV#J F RV#F RV# RV# RV# J RV#J RV# H RV#H W0 RV#W0 K0 RV#K0 RV# RV# RV# RV# RV# RV# RV# RV# RV# MH_LKL0 P MH_LKL F0 N MH_LKL F N F F F F F F F N F F F F J0 F F 0 F0 F R F F0 L F F J F F F 0 F K F F M0 F M F F L F F N F0 F L F0 PM_M_UY# L PM_PRTP# L PM_XT_T#0 J PM_XT_T# W PWROK V0 RTIN# N0 THRMTRIP# PRLPVR J N#J K N#K K0 N#K0 L0 N#L0 L N#L L N#L L N#L K N#K J N#J N# N# N# 0 N#0 0 N#0 N# K N#K PLT_RT_R# U OF 0 RV F PM N R 00RJ--P R MUXIN M_LK_R0 M_K0 V M_LK_R M_K M_LK_R M_K M_LK_R M_K V M_LK_R#0 M_K#0 W0 M_LK_R# M_K# M_LK_R# M_K# W M_LK_R# M_K# W R_K0_IMM M_K0 R_K_IMM M_K Y R_K_IMM M_K R_K_IMM M_K R_0_IMM# M_#0 0 R IMM# M_# K R IMM# M_# R IMM# M_# M_OT0 M_OT0 H M_OT M_OT J M_OT M_OT J M_OT M_OT M_ROMP_VOH M_ROMP_VOL LK_MH_PLL LK_MH_PLL# MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP FT_VI0 FT_VI FT_VI FT_VI FT_VR_N IH_VO_LK IH_VO_T MH_IH_YN# PLT_RT#,0,,,,, <ore esign> FOR alero: 0. ohm restline: 0 ohm M_LK_R0 M_LK_R M_LK_R M_LK_R M_LK_R#0 M_LK_R# M_LK_R# M_LK_R# R_K0_IMM R_K_IMM R_K_IMM R_K_IMM R_0_IMM# R IMM# R IMM# R IMM# M_OT0 M_OT M_OT M_OT M_ROMP M_ROMP L M_ROMP# M_ROMP# K R 0RF-P R 0RF-P R_VRF_ M_VRF#R R R_VRF_ M_VRF#W W PLL_RF_LK PLL_RF_LK# PLL_RF_LK H PLL_RF_LK# H LK RTLIN-P-U-NF MI MI M RPHI VI P_LK K P_LK# K MI_RXN0 N MI_RXN J MI_RXN N MI_RXN N MI_RXP0 M MI_RXP J MI_RXP N MI_RXP N MI_TXN0 J MI_TXN J MI_TXN M0 MI_TXN M MI_TXP0 J MI_TXP J MI_TXP M MI_TXP M FX_VI0 FX_VI FX_VI FX_VI FX_VR_N L_LK L_T L_PWROK L_RT# L_VRF VO_TRL_LK H VO_TRL_T K LKRQ# IH_YN# 0 K M_ROMP_VOH L M_ROMP_VOL MI_RXP0 0 MI_RXP 0 MI_RXP 0 MI_RXP 0 V_ LK_MH_PLL LK_MH_PLL# MI_TXN0 0 MI_TXN 0 MI_TXN 0 MI_TXN 0 MI_TXP0 0 MI_TXP 0 MI_TXP 0 MI_TXP 0 MI_RXN0 0 MI_RXN 0 MI_RXN 0 MI_RXN 0 TP TP TP TP TP TP0 TP LKRQ#_ MH_IH_YN# 0 IH_VO_T IH_VO_LK M L_LK0 0 K0 L_T0 0 T LPWROK_MH VT_PWR 0, N R0 0R00-P L_RT# 0 M0 L_VRF TT_MH TT TT_MH TT R R 0KRJ-L-P UVKX-P R 0R00-P V_0 R KRJ--P Y V_0 R KRF--P R RF-P R0 KRJ--P Y Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RTLIN(/)-TL+/MI/R ize ocument Number Rev ustom M-iscrete ate: Wednesday, ugust, 00 heet of

8 R [0..] R [0..] R M[0..] R Q[0..] R Q#[0..] R M[0..] R [0..] R [0..] R M[0..] R Q[0..] R Q#[0..] R M[0..] U OF 0 U OF 0 R 0 R R R R R R R R R R 0 R R R R R R R R R R 0 R R R R R R R R R R 0 R R R R R R R R R R 0 R R R R R R R R R R 0 R R R R R R R R R R 0 R R R R W Y R R T W F J 0 H W 0 F H 0 F0 R0 W0 T W W Y V T V T W V U T 0 0 Y 0 W Y T T Y R R R N M N0 T N M N _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q R YTM MMORRY _0 _# _M0 _M _M _M _M _M _M _M _Q0 _Q _Q _Q _Q _Q _Q _Q _Q#0 _Q# _Q# _Q# _Q# _Q# _Q# _Q# _M0 _M _M _M _M _M _M _M _M _M _M0 _M _M _M _R# _RVN# _W# K F L T W W Y N T H P T H P R 0 R R R # R M0 R M R M R M R M R M R M R M R Q0 R Q R Q R Q R Q R Q R Q R Q R Q#0 R Q# R Q# R Q# R Q# R Q# R Q# R Q# J R M0 0 K R M R M H R M L R M K J J R M R M R M L R M R M R M0 R M 0 R M J R M Y0 R R# _RVN# R W# R 0 P R 0 R Q0 _0 Y R R R Q _ W0 R R Q _ W R Q R # R # N R Q _# R # N0 R Q V0 R M0 R Q _M0 R0 V R M R Q _M 0 R M R Q _M K 0 R M R 0 _Q _M L R M R Q0 _M H 0 R M R Q _M J R M R Q _M F Y R M R Q _M W F0 R Q F R Q0 R Q _Q0 T0 J0 R Q R Q _Q 0 J R Q R Q _Q K J R Q R Q _Q K L R Q R 0 _Q _Q J K R Q R Q0 _Q L K R Q R Q _Q K R Q R Q _Q V K R Q#0 R Q _Q#0 U0 J R Q# R Q _Q# 0 L R Q# R Q _Q# L J R Q# R Q _Q# K J R Q# R Q _Q# K K R Q# R Q _Q# K J0 R Q# R 0 _Q _Q# F L R Q# R Q0 _Q# V K R Q K R M0 R Q _M0 R M R Q _M K R M R Q _M R M R Q _M W R M R Q _M F R M R Q _M R M R Q _M R M R 0 _Q _M J0 R M R Q0 _M Y L R M R Q _M K R M0 R Q _M0 L R M R Q _M K R M R Q _M K0 R M R Q _M J R Q J R R# R Q _R# V _RVN# R R# R R# F TP0 R Q _RVN# Y TP0 H R 0 _Q R W# R Q0 _W# R W# R W# R Q K R Q R Q R Q J R Q R Q R Q R R Q T R 0 _Q Y R Q0 Y R Q U R Q T _Q R YTM MMORY RTLIN-P-U-NF RTLIN-P-U-NF <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RTLIN(/)-R / H ize ocument Number Rev M-iscrete ate: Wednesday, ugust, 00 heet of

9 U OF 0 J0 L_KLT_TRL H L_KLT_N L_TRL_LK 0 L_TRL_T L LK L T K0 L_V_N L LV_I L LV_V N LV_VRFH N0 LV_VRFL LV_LK# LV_LK LV_LK# LV_LK LV_T#0 LV_T# F LV_T# 0 LV_T0 0 LV_T F LV_T LV_T#0 LV_T# LV_T# LV_T0 LV_T LV_T TV_ TV_ K TV_ F TV_RTN J TV_RTN L TV_RTN M TV_ONL0 P TV_ONL H RT_LU RT_LU# K RT_RN J RT_RN# F RT_R RT_R# K RT LK RT T RT_VYN RT_TVO_IRF F RT_HYN LV TV V PI_XPR RPHI 0V_0 P_OMPI N P_OMPO M P_RX#0 J P_RX# L P_RX# N P_RX# T P_RX# T0 P_RX# U0 P_RX# Y P_RX# Y0 P_RX# P_RX# W P_RX#0 P_RX# 0 P_RX# P_RX# H P_RX# P_RX# P_RX0 J0 P_RX L0 P_RX M P_RX U P_RX T P_RX T P_RX W P_RX W P_RX 0 P_RX Y P_RX0 P_RX P_RX H P_RX P_RX H P_RX R RF-L-P POMP TXN0 P_TX#0 N TXN P_TX# U TXN P_TX# U TXN P_TX# N TXN P_TX# R0 TXN P_TX# T TXN P_TX# Y TXN P_TX# W TXN P_TX# W TXN P_TX# TXN0 P_TX#0 TXN P_TX# TXN P_TX# TXN P_TX# H TXN P_TX# TXN P_TX# H TXP0 P_TX0 M TXP P_TX T TXP P_TX T TXP P_TX N0 TXP P_TX R TXP P_TX U TXP P_TX W TXP P_TX Y TXP P_TX Y TXP P_TX TXP0 P_TX0 TXP P_TX 0 TXP P_TX TXP P_TX TXP P_TX 0 TXP P_TX H POMP trace width and spacing is 0/ mils. P_RXP P_RXP P_RXP P_RXP P_RXP P_RXP0 P_RXP P_RXP P_RXP P_RXP P_RXP P_RXP P_RXP P_RXP P_RXP P_RXP0 P_RXN P_RXN P_RXN P_RXN P_RXN P_RXN0 P_RXN P_RXN P_RXN P_RXN P_RXN P_RXN P_RXN P_RXN P_RXN P_RXN0 0 U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P 0 U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P 0 U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P 0 U0VKX-P U0VKX-P U0VKX-P 0 U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P 0 U0VKX-P U0VKX-P P_TXP P_TXP P_TXP P_TXP P_TXP P_TXP0 P_TXP P_TXP P_TXP P_TXP P_TXP P_TXP P_TXP P_TXP P_TXP P_TXP0 P_TXN P_TXN P_TXN P_TXN P_TXN P_TXN0 P_TXN P_TXN P_TXN P_TXN P_TXN P_TXN P_TXN P_TXN P_TXN P_TXN0 F[:0] F Freq select F (MI select) F F (PU trap) F (Low power PI) F[:] trap Pin Table F (PI raphics Lane Reversal) F[:0] F[:] (XOR/LLZ) F[:] F (F ynamic OT) 0 = isable nable * Reversed VO_TRLT 0 = No VO evice Present * = VO evice Present F(MI Lane Reversal) F0(PI/VO consurrent) 00 = F 00MHz 0 = F MHz Others = Reserved 0 = MI x = MI x * Reserved 0 = Reserved = Mobile PU * 0 = Normal Operation * (Lane number in Order) = Reverse lane 0 = Only PI or VO is operational * = PI/VO are operating simu. 0 = Normal mode = Low Power mode * 0 = Reverse Lane = Normal Operation * Reserved 00 = Reserved 0 = XOR Mode nabled 0 = ll Z Mode nabled = Normal Operation (efault)* Reserved RTLIN-P-U-NF <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RTLIN(/)-V/LV/TV ize ocument Number Rev M-iscrete ate: Wednesday, ugust, 00 heet of

10 Intel spec: V_RXR_MI, Imax=00 m V_0_XF V_0_HPLL V_0_MPLL V_0_TXLV V_0_TV V_0_HPLL V_0_PPLL U0VKX-P UH OF 0 J V_YN V_RT_ V_RT_ 0 V V_PLL H V_PLL L V_HPLL M V_MPLL V_LV KP0VKX-P _LV K0 V_P_ K _P_ V_0_PPLL 0mil U V_P_PLL W V_M V V_0 V_0 M V_M U V_M U V_M R U V_M 0R00-P T V_M T V_M T V_M T V_M T V_M R V_M_NTF R V_0_M_K V_M_NTF R Y Y V_M_K 0R00-P V_M_K V_TV_ V_TV_ V_TV_ V_TV_ V_TV_ V_TV_ V_0 V_0_P_ R U0VKX-P UVZY-P 0R00-P TUVM-P U0VKX-P UVKX-P UVZY-P UVZY-P UVZY-P M V_RT L V_TV N V_Q N V_HPLL U V_P_PLL J V_LV H V_LV LV PLL RT P LV TV/RT RTLIN-P-U-NF TV K M X MI M K VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT V_X V_X V_X V_X V_X V_X V_X_NTF XF P V_XF V_XF V_XF V_MI V_M_K V_M_K V_M_K V_M_K V_TX_LV HV V_HV V_HV V_P V_P V_P V_P V_P V_RXR_MI V_RXR_MI VTTLF VTT POWR VTTLF VTTLF VTTLF U U U U U U U U U U T T T0 T T T T T T R R R T U U T T T0 R J0 K K J J 0 0 W0 W V V0 H0 H F H 0V_0 VTTLF VTTLF VTTLF 0 T0UVM-P Y T UVZY-P V_0_X V_0_XF V_0_MI V M_K 0V_0_P 0mil UVZY-P U0VKX-P 0 UVZY-P UVKX-P 0 UVKX-P 0U0VKX-P V_0_HV UVMX--P R0 0R00-P UVZY-P 0 UVZY-P V_0 V_0_MI R0 0 0R00-P UVZY-P 0V_0_P 0V_0_P 0mil 0V_0 MV- V_0 Intel spec: V_PX,Imax=00 m 0U0VKX-P V_0 R 0R00-P 0U0VKX-P V_0_PPLL L V_0 0 LMPN-P 0U0VKX-P Y UVZY-P T T0UVM-P UVZY-P Y 0 T T0UVM-P UVZY-P 0V_0 Y 0V_0_ R0 R 0R00-P 0RJ--P MLPT-P V M_K UVZY-P 0 UVZY-P UVZY-P V_0_TV 0UVKX-P UVZY-P V_0_HPLL V_0_MPLL 0U0VKX-P UVZY-P V_0_HV UVZY-P R 0R00-P UVZY-P R0 0R00-P R 0R00-P L L V_0 LMN-P 0U0VKX-P LMN-P 0 UVKX-P V_ V_0 V_0 V_0 <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RTLIN(/)-PWR ize ocument Number Rev M-iscrete ate: unday, eptember 0, 00 heet 0 of

11 0V_0 0V_0 LI UF OF 0 T T0UVM-P 0 U0VKX-P U0VKX-P UVMX-P UVZY-P 0 U0VKX-P 0V_0 0V_0 V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF F V_NTF F V_NTF H V_NTF H V_NTF H V_NTF H V_NTF J V_NTF J V_NTF K V_NTF K V_NTF K V_NTF K V_NTF V_NTF J V_NTF M V_NTF L V_NTF L V_NTF V_NTF V_NTF V_NTF P V_NTF P V_NTF R V_NTF R V_NTF Y V_NTF Y V_NTF Y V_NTF Y V_NTF Y V_NTF T0 V_NTF T V_NTF T V_NTF U V_NTF U V_NTF U V_NTF U V_NTF U V_NTF U V_NTF V V_NTF V V_NTF V V_NTF V V_NTF L V_XM_NTF L V_XM_NTF L V_XM_NTF M V_XM_NTF M 0U0VKX-P V_XM_NTF M 0U0VKX-P V_XM_NTF M V_XM_NTF M V_XM_NTF M V_XM_NTF P V_XM_NTF P V_XM_NTF P V_XM_NTF P V_XM_NTF L V_XM_NTF L V_XM_NTF L V_XM_NTF R V_XM_NTF R V_XM_NTF R V_XM_NTF UVZY-P U0VKX-P UVZY-P UVZY-P U OF 0 V NTF NTF RTLIN-P-U-NF _NTF T _NTF T _NTF U _NTF U _NTF V _NTF V _NTF _NTF _NTF _NTF _NTF _NTF F _NTF F _NTF K _NTF M _NTF M _NTF P _NTF P _NTF R _NTF R _NTF R POWR XM XM NTF L _ L _ V_XM T V_XM T V_XM K V_XM K V_XM K V_XM J V_XM J 0V_0 HH-0PT-P TP TP TP TP TP TP 0V_0 K R0 0RJ--P V_0 T Y U0VKX-P V_ T0UVM-P T T0UVM-P 0U0VKX-P UVMX-P UVMX-P 0U0VKX-P R0 0R00-P 0V_0 T V T V H V V V K V J V J V H V H V H V F V V_MH R0 V 0 0UVKX-P UVZY-P V OR U V_M U V_M U V_M V V_M W V_M W V_M Y V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M F V_M F V_M V_M V_M V_M H V_M H V_M H V_M J V_M J V_M J V_M K V_M K V_M K V_M K V_M L V_M U0 V_M R0 V_X T V_X W V_X W V_X Y V_X 0 V_X V_X V_X V_X V_X V_X V_X 0 V_X V_X V_X V_X V_X V_X V_X 0 V_X V_X V_X V_X F V_X F V_X V_X H0 V_X H V_X H V_X H V_X H V_X V_X J0 V_X N V_X POWR V M V FX RTLIN-P-U-NF V FX NTF V M LF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_M_LF V_M_LF V_M_LF V_M_LF V_M_LF V_M_LF V_M_LF T T T T T T T U U U U U0 U U U V V V V0 V V V Y Y Y Y Y0 Y Y Y Y Y Y F F H H H H J J J K K L L L L0 L L M M M M0 M M P P P P P0 P P P R0 R R R R V V V Y W VM_LF VM_LF VM_LF VM_LF VM_LF W VM_LF T VM_LF UVZY-P UVZY-P UVZY-P 0 UVKX-P U0VKX-P U0VKX-P U0VKX-P UVZY-P U0VKX-P U0VKX-P <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RTLIN(/)-PWR/N ize ocument Number Rev ustom M-iscrete ate: Monday, July 0, 00 heet of

12 UI OF 0 UJ 0 OF F0 F F F 0 H H0 H H H J J J J J J J J J K0 K K K K K L M M M M M M N N N N N N P P P0 R R R R R R T0 T T T U U U U U U U V V W W W RTLIN-P-U-NF W W W W W Y0 Y Y Y Y Y Y Y F F F H H0 H H H J J J J J J K K K K K K0 K K K L L L L L L 0 0 F F F F0 F0 H H H H J J J J J J J J K K K L L L0 L L L L L M M M M M M0 M N N N N N N N N N N P P P P P0 R T T T U U U0 V V W W W W W W Y Y Y Y Y Y Y0 Y P T T T R F F T V H0 RTLIN-P-U-NF <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RTLIN(/)-PWR/N ize ocument Number Rev M-iscrete ate: Monday, July 0, 00 heet of

13 R Q#[0..] M Layout Note: Place near M V_ Layout Note: Place one cap close to every pullup resistors terminated to +0.V R_VRF_0 Y R M R M R M R M UVZY-P UVZY-P R R# R_0_IMM# R M0 R 0 R W# R IMM# M_OT R # UVZY-P UVZY-P Y UVZY-P Y 0 UVZY-P RN RNJ--P RN RNJ--P RN RNJ--P R_K_IMM RN RNJ--P RN RNJ--P RN RNJ--P RN RNJ--P UVZY-P Y 0 UVZY-P Y UVZY-P R_VRF_0 RN RN RN RN RN RN RN0 UVZY-P UVZY-P R [0..] R M[0..] R Q[0..] R M[0..] Y 0 UVZY-P R [0..] UVZY-P Y 0 UVZY-P RNJ--P R R_K0_IMM RNJ--P R M R M RNJ--P R M R M RNJ--P R M R M RNJ--P R M0 R UVZY-P RNJ--P M_OT0 R M RNJ--P R M R M UVZY-P UVZY-P UVZY-P UVZY-P UVZY-P T UVZY-P T0UVM-P UVZY-P Layout Note: Place these resistors closely M,all trace length Max=." R_VRF_ R M M_OT0 M_OT R_VRF_ UVZY-P R M0 R M R M R M R M R M R M R M R M R M R M0 R M R M R M R M R R 0 R R 0 R R R R R R R R R R 0 R R R R R R R R R R 0 R R R R R R R R R R 0 R R R R R R R R R R 0 R R R R R R R R R R 0 R R R R R R R R R R 0 R R R R Q#0 R Q# R Q# R Q# R Q# R Q# R Q# R Q# R Q0 R Q R Q R Q R Q R Q R Q R Q M_OT0 M_OT UVZY-P MH 0 R# 0 W# 0 # 0# 0 # K0 K 0 0/P K0 0 K0# K K# / M0 0 M 0 M M M 0 M Q0 M 0 Q M Q Q Q Q L Q Q VP Q Q 0 Q0 00 Q Q N#0 0 Q N# Q N# Q N#0 0 Q N#/TT Q Q Q V Q0 V Q V Q V Q V Q V Q V 0 Q V 0 Q V Q V Q V Q0 V Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q 0 Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 Q Q Q Q0# Q# Q# Q# Q# Q# Q# 0 Q# Q0 Q Q Q Q Q Q Q OT0 OT 0 VRF N N 0 MH MH MH R-00P-0-P-U R R# R R# R W# R W# R # R # R_0_IMM# R_0_IMM# R IMM# R IMM# R_K0_IMM R_K0_IMM R_K_IMM R_K_IMM M_LK_R0 M_LK_R0 M_LK_R#0 M_LK_R#0 M_LK_R M_LK_R M_LK_R# M_LK_R# R M0 R M R M R M R M R M R M R M IH_MT IH_MT,,0 IH_MLK IH_MLK,,0 UVZY-P R 0KRJ--P R 0KRJ--P 0 PM_XTT#0 V_ <Variant Name> V_0 UVKX-P Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RII-OIMM LOT ize ocument Number Rev ustom M-iscrete Wednesday, ugust, 00 ate: heet of

14 R Q#[0..] R [0..] R M[0..] Layout Note: Place near M V_ Layout Note: Place one cap close to every pullup resistors terminated to +0.V R_VRF_0 Y R M R M RN0 R M0 R 0 R M0 R UVZY-P UVZY-P RN R IMM# R R# RN R W# R # RN R IMM# M_OT RN R M RN RN Y 0 UVZY-P UVZY-P 0 UVZY-P UVZY-P RNJ--P RNJ--P RNJ--P RNJ--P RNJ--P Y RNJ--P RNJ--P 0 UVZY-P UVZY-P UVZY-P R_VRF_0 R Q[0..] R M[0..] RN R [0..] RN0 RN RN RN RN RN UVZY-P UVZY-P RNJ--P UVZY-P UVZY-P 0 UVZY-P Y R M R M RNJ--P R_K_IMM R M RNJ--P R M R M RNJ--P R M R M RNJ--P R M R M UVZY-P RNJ--P M_OT R M UVZY-P RNJ--P R R_K_IMM 0 UVZY-P UVZY-P Y UVZY-P UVZY-P 0 UVZY-P Layout Note: Place these resistors closely M,all trace length Max=." R_VRF_ R M M_OT M_OT R_VRF_ M Y UVZY-P R M0 R M R M R M R M R M R M R M R M R M R M0 R M R M R M R M R R 0 R R 0 R R R R R R R R R R 0 R R R R R R R R R R 0 R R R R R R R R R R 0 R R R R R R R R R R 0 R R R R R R R R R R 0 R R R R R R R R R R 0 R R R R Q#0 R Q# R Q# R Q# R Q# R Q# R Q# R Q# R Q0 R Q R Q R Q R Q R Q R Q R Q M_OT M_OT UVZY-P /P / 0 Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q0# Q# Q# Q# Q# Q# Q# Q# Q0 Q Q Q Q Q Q Q OT0 OT VRF R# 0 W# 0 # 0# 0 # K0 K 0 K0 0 K0# K K# M0 0 M M M M 0 M M 0 M L VP 0 00 N#0 0 N# N# N#0 0 N#/TT V V V V V V V 0 V 0 V V V V R R# R R# R W# R W# R # R # R IMM# R IMM# R IMM# R IMM# R_K_IMM R_K_IMM R_K_IMM R_K_IMM M_LK_R M_LK_R M_LK_R# M_LK_R# M_LK_R M_LK_R M_LK_R# M_LK_R# R M0 R M R M R M R M R M R M R M IH_MT IH_MT,,0 IH_MLK IH_MLK,,0 UVZY-P V_0 R 0KRJ--P R0 0KRJ--P V_0 PM_XTT# V_ UVKX-P UVZY-P 0 MH N MH R-00P--P-U N 0 MH MH <Variant Name> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RII-OIMM LOT ize ocument Number Rev ustom M-iscrete Wednesday, ugust, 00 ate: heet of

15 RT I/F & ONNTOR Layout Note: POLYW-V--P HH-0PT-P Place these resistors close to the RT-out 0UVKX-P RT connector L RN Y RNKJ--P V_R RT_R LM0N-P RT_R TP0 TP L RT T_ON TP0 TP V_RN RT_ LM0N-P RT_ JV_H TP0 TP L JV_V 0 V_LU RT LK_ON LM0N-P 0P0VJN-P 0P0VJN-P P0VJN-P P0VJN-P VIO---P-U 0 P0VJN-P P0VJN-P Layout Note: * Must be a ground return path between this ground and the ground on the V connector. Pi-filter & 0 Ohm pull-down resistors should be as close as to RT ONN. R will hit Ohm first, pi-filter, then RT ONN. RT_R V--F-P MH_HYN MH_VYN R 0RF--P R 0RF--P R 0RF--P Hsync & Vsync level shift U THTPW-P V_0 0P0VJN-P UVZY-P HYN_ U THTPW-P VYN_ RN RNJ--P-U P0VN-P JV_H JV_V P0VN-P V_T V_LK P0VN-P V_0 V_RT_0 V_0 _LK & T level shift _LK_ON Y V--F-P RNKJ--P RN U F _T_ON N00W--P _LK_ON V_RT_0_ Y RT_ RT_ V--F-P V--F-P Y _T_ON V--F-P Y Y Y Y Y K V_RT_0 Y V_0 Layout Note: close to the TV-out connector V_TV_LUM TV_OMP TV JV_V P0V-P TV_LUM V--F-P V_TV_RM TV_RM LUM N# L TV_OMP RM TV_LUM LMN-P OMP N N P0VJN-P P0VJN-P N N# N VTPT-P <Variant Name> MININ--P P0V-P V_TV_OMP R 0RF--P R0 0RF--P R 0RF--P 0 P0VJN-P P0VJN-P P0V-P L LMN-P L LMN-P P0VJN-P P0VJN-P TV OUT ONN.00.H TV_RM VTPT-P VTPT-P V_0 JV_H V--F-P RT/TV ONNTOR Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev M-iscrete ate: Thursday, eptember, 00 heet of Y Y

16 L NP NP IPX-ON--P 0.F0.0 L/INVRTR ONN L_V TP TP0 TOUT UVKX-P 0UVKX-P L_LK L_T LV_0 LON_OUT RIHTN V_TXLK- V_TXLK+ V_TXOUT0- V_TXOUT0+ V_TXOUT- V_TXOUT+ V_TXOUT- V_TXOUT+ V_TXLK- V_TXLK+ V_TXOUT0- V_TXOUT0+ V_TXOUT- V_TXOUT+ V_TXOUT- V_TXOUT+ V_0 UVKX-P L_T L_LK 0KRJ--P R V_0 LON_OUT 000P0VJN-P 0 RIHTN UVKX-P L ONN I=. m V_0 H_L TY_L TP0 TP TP0 TP TP0 TP0 TP0 TP TP0 TP TP0 TP TP0 TP TP0 TP TP0 TP TP0 TP TP0 TP P_L# ROM_L# 0 T_L# MI_L#_N TY_L#_N H_L#_N P_L#_N NUM_L#_N POWR_L#_N K_PWR_TN#_N V_ V_0 0 -ON--P N Place Top side and close to connector TPTP0 TPTP0 V_0 I=. m U 0 mil 0 mil V_0 NUM_L#_N R NUM_L# RF-L-P THT0PWR-P 0 NUMLK_L# LV_0 LV_N R 00KRJ--P POWR_L#_N U V_0 PWR_L# THT0PWR-P UVKX-P V_UX_ V_ UVKX-P RN RNKJ--P R Q H_L#_N H_L# R RF-L-P R PTU--P R Q TY_L#_N TY_L# R RF-L-P R PTU--P V_0 I=. m U R P_L#_N P_L# RF-L-P THT0PWR-P I=. m U R MI_L#_N MI_L# RF-L-P THT0PWR-P TP0 TP U IN# N OUT IN# N IN# N IN# IN# RU-P R POWR_L# 00RJ--P 0UVKX-P 0UVKX-P LV_0 LV_N LV_0_R R 0RF--P U LV_ON# N00W-F-P R 0KRJ--P R K_PWR_TN#_N 00RJ--P 0 UVKX-P R00 0KRJ--P 000P0VJN-P Y K_PWR_TN# <Variant Name> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. L ONN & L ize ocument Number Rev M-iscrete Thursday, eptember, 00 ate: heet of

17 V_0 HMI HMI_TX HMI_TX# HMI_TX HMI_TX# HMI_TX0 HMI_TX0# HMI_TX 0 HMI_TX# HMI_ HMI_HP HMI_HP 0RJ--P R TP TP0 Y R 0KRF-L-P R 00KRJ-L-P HMI_L HMI_ HMI HMI_N L0 HP LMN-P KT-HMIP-P-U 0 Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. HMI ize ocument Number Rev M-iscrete ate: Wednesday, ugust, 00 heet of

18 V_0 RN0 RNKJ--P RN RNKJ--P RN PI_FRM# PI_NT# PI_RQ# PI_RQ# PI_NT# PI_RQ# PI_RR# PI_PIRQ# PI_NT#0 PI_PIRQ# PI_PLOK# PI_PRR# RNKJ--P RN PI_PIRQH# PI_PIRQ# PI_PIRQ# PI_RQ#0 RNKJ--P RN PI_IRY# PI_TRY# PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# U OF F 0 F PIRQ# PIRQ# PIRQ# 0 PIRQ# PI RQ0# NT0# RQ#/PIO0 NT#/PIO RQ#/PIO NT#/PIO NT#/PIO RQ#/PIO /0# /# /# /# IRY# PR PIRT# VL# PRR# FRM# PLOK# RR# TOP# TRY# PLTRT# PILK PM# Interrupt I/F PIRQ#/PIO PIRQF#/PIO PIRQ#/PIO PIRQH#/PIO F 0 F F0 0 F F PI_RQ#0 PI_NT#0 PI_RQ# PI_NT# PI_RQ# PI_NT# PI_NT# PI_RQ# PI_/#0 PI_/# PI_/# PI_/# PI_IRY# PI_PR PI_PIRT# PI_VL# PI_PRR# PI_FRM# PI_PLOK# PI_RR# PI_TOP# PI_TRY# PI_PLTRT# LK_PI_IH PI_PIRQ# PI_PIRQF# PI_PIRQ# PI_PIRQH# TP TP TP TP TP TP TP TP R KRJ--P LK_PI_IH V_ RNKJ--P RN PI_PIRQF# PI_NT# PI_VL# PI_TOP# IH-M--P-U-NF RNKJ--P V_ U0 PI_NT# PI_PIRT# LV0PWR-P R 00KRJ--P PIRT# R KRJ--P Y oot IO trap PI_NT0# PI_# oot IO Location R 0RJ--P Y swap override trap Low= swap override nable PI_NT# High= efault * 0 0 PI PI LP * PI_PLTRT# V_ U0 PLT_RT# LV0PWR-P R 00KRJ--P PLT_RT#,0,,,,, Place closely pin 0 PI_NT#0 V_ R 0RJ--P Y LK_PI_IH P0V-P R 0RJ--P Y Y Y R KRJ--P 0 PI_# Y PI_# R 0KRJ--P PI_PLTRT# 0 <Variant Name> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IH(/)-PI/INT ize ocument Number Rev M-iscrete ate: Wednesday, ugust, 00 heet of

19 +RTV V_0 LN00_LP R 0KRF-L-P M_INTRUR# R MRJ--P +RTV IH_INTVRMN R 0KRF-L-P R 0KRJ-L-P IH_RTX IH_RTX R 0MRJ-L-P U0VKX-P RO-KHZ-P X 0P0VJN-P 0P0VJN-P,, H_ITLK_O,, H_YN_O,, H_RT#_O H_IN0 H_IN H_IN,, H_OUT_O 0 T_RXN0_ 0 T_RXP0_ 0 T_TXN0 0 T_TXP0 RN RN P-OPN V_0 T_L# R RF-L-P 00P0VKX-P 0 00P0VKX-P IH_RTX IH_RTX IH_RTRT# M_INTRUR# IH_INTVRMN LN00_LP TP LN_OMP H_ITLK RNJ--P-U RNJ--P-U P-OPN TP T_TXN0_ T_TXP0_ U OF RTX F RTX F RTRT# INTRUR# F INTVRMN LN00_LP LN_LK LN_RTYN LN_RX0 LN_RX LN_RX LN_TX0 0 LN_TX 0 LN_TX H LN_OK#/PIO LN_OMPI LN_OMPO J H_IT_LK J H_YN H_RT# J H_IN0 H H_IN H H_IN H_IN H_OUT 0 H_OK_N#/PIO H_OK_RT#/PIO F0 TL# F T0RXN F T0RXP H T0TXN H T0TXP TRXN TRXP J TTXN J TTXP F TRXN F TRXP TTXN TTXP RT LN/LN IH T LP PU I FWH0/L0 FWH/L FWH/L FWH/L FWH/LFRM# LRQ0# LRQ#/PIO 0T 0M# PRTP# PLP# FRR# PUPWR/PIO INN# INIT# INTR RIN# NMI MI# TPLK# THRMTRIP# TP # # F F F F F 0 H V U V T V T T T R T V V U V U Y Y LP_L0 LP_L LP_L LP_L LP_FRM# LP_RQ0# H_0M# H_PLP# H_FRR# H_PWROO H_INN# H_INIT# KRT# H_NMI H_MI# H_TPLK# THRMTRIP_IH# TP I_P0 I_P I_P I_P I_P I_P I_P I_P I_P I_P I_P0 I_P I_P I_P I_P I_P TP TP H_PRTP# LP_L0, LP_L, LP_L, LP_L, LP_FRM#, K0 H_0M# H_PLP# H_FRR# H_PWROO H_INN# H_INIT#, H_INTR KRT# H_NMI H_MI# H_TPLK# R RJ-P I_P[0..] 0 I_P0 0 I_P 0 I_P 0 I_P# 0 I_P# 0 H_PRTP#,, I_PIORY INT_IRQ 0V_0 K0 KRT# H_FRR# H_PRTP# H_PLP# within " from R R0 RJ--P H_THRMTRIP#, placed within " from IHM R KRJ--P R0 KRJ--P Y RN RN0KJ--P R RJ--P TP0 TP V_0 0V_0 LK_PI_T# LK_PI_T R0 RF-L-P Within 00 mils T_LKN T_LKP TRI# TRI IOR# IOW# K# IIRQ IORY RQ W W Y Y Y W I_PIOR# 0 I_PIOW# 0 I_PK# 0 INT_IRQ 0 I_PIORY 0 I_PRQ 0 IH-M--P-U-NF V_UX_ RT XOR HIN NTRN TRP : RV U0VZY-P +RTV W=0mils R 00RJ--P W=0mils U HFPT-P TT. R W=0mils W=0mils KRJ--P PWR N NP NP NP NP T-ON--P-U <Variant Name> V_0 R KRJ--P Y H_OUT_O Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IH(/) LN,H,I,LP ize ocument Number Rev M-iscrete ate: Wednesday, eptember, 00 heet of

20 V_0 V_ RN INT_RIRQ PM_LKRUN# LKTRQ# THRM_I# RN0KJ--P NWR_RT# 0KRF--P R V_0 R PIO 0KRJ--P RN0 IH_RI# PM_TLOW#_R XP_RT# PIO RN0KJ--P RN M_LINK_LRT# OP# MI# RN0KJ--P PRLPVR R 00KRJ--P IH_RV R0 KRJ--P Y K suspend clock output TP TP H_TP_PI# H_TP_PU# Y V_0, RN RNKJ--P VT_PWR NW_PP# I# _WI# TP0, LP_P# XP_RT# PM_MUY# OP# PM_LKRUN#,, PI_WK#, INT_RIRQ V_ M_LK M_T M_LINK_LRT# MLINK0 MLINK IH_RI# XP_RT# PM_MUY# OP# H_TP_PI# H_TP_PU# INT_RIRQ THRM_I# VRMPWR R 0RJ--P T_TL Y TP TP PIO R PP# 0R00-P I# MI# TP PIO NWR_RT# PX_RT# PIO TP TP LKTRQ# LKTRQ# TP PIO TP PIO TP I_RT# _PKR MH_IH_YN# RN RNKJ--P _PKR MH_IH_YN# IH_RV J F F 0 H F J0 J J J H H 0 H F J 0 J J U MLK MT LINKLRT# MLINK0 MLINK RI# U_TT#/LPP# Y_RT# MUY#/PIO0 MLRT#/PIO TP_PI# TP_PU# LKRUN# WK# RIRQ THRM# VRMPWR TP TH/PIO TH/PIO TH/PIO PIO PIO TH0/PIO PIO PIO0 LOK/PIO QRT_TT0/PIO QRT_TT/PIO TLKRQ#/PIO LO/PIO TOUT0/PIO TOUT/PIO PKR MH_YN# TP OF M YPIO PIO MI T PIO LOK POWR MT ontroller Link T0P/PIO TP/PIO TP/PIO PIO LK LK ULK LP_# LP_# LP_# _TT#/PIO PWROK PRLPVR/PIO TLOW# PWRTN# LN_RT# RMRT# K_PWR LPWROK LP_M# L_LK0 L_LK L_T0 L_T L_VRF0 L_VRF L_RT# LPIO0/PIO LPIO/PIO0 LPIO/PIO LPIO/PIO J J0 F F H J H0 J F F F H J J J F LK_M_IH LK_M_IH IH_ULK PIO PM_PWROK PRLPVR PM_TLOW#_R K_PWR_R R VT_PWR LP_M# L_LK0 L_LK L_T0 L_T L_VRF0_IH L_VRF_IH PIO PIO0 PIO PIO T0_R0 T0_R T0_R T0_R R 0R00-P _RMRT# LK_M_IH LK_M_IH PM_LP_#,,,,,,, PM_LP_#,,, PM_PWROK, PRLPVR, _PWR_TN# PLT_RT#,,,,,, K_PWR 0R00-P VT_PWR, TP L_LK0 TP L_T0 TP L_RT# TP TP TP TP RN0 RN0KJ--P V_0 R 0KRJ--P V_ Place closely pin LK_M_IH K_PWR R NZ0MX-NL-P 0KRJ--P UVKX-P V Y R0 0RJ--P Y R R RF--P P0VN-P Y U KRF-P N V_0 Y R 0RJ--P Place closely pin R0 KRJ--P solve auto power on issue LK_M_IH R 0RJ--P Y P0VN-P Y 0 _RMRT# V_0 U IH_ULK V_ R0 0KRJ--P KHZ R0 0RJ--P _LK V_0 0KRJ--P R Y Low--> default High--> No boot _PKR IH-M--P-U-NF 0 UVKX-P R KRF-P R RF--P V_0,,, IH_MT M_LK U_O# U_O# U_O# U_O# U_O# U_O# TLX0MTX-P V_0 M_LK RN RN0KJ--P RN U_O#0 U_O# U_O# U_O# RN0KJ--P R R RN RNKJ--P 0KRF--P 0KRF--P U N00W--P V_ KHZ RN V_0 R0 0RJ--P Y M_T RN0KJ--P T LN Mini ard for ROON M_LINK_LRT# MLINK0 MLINK PI_WK# Mini ard M_T, IH_MLK,, TPM_K_LK New ard PI_RXN PI_RXP PI_TXN PI_TXP PI_RXN PI_RXP PI_TXN PI_TXP PI_RXN PI_RXP PI_TXN PI_TXP PI_RXN PI_RXP PI_TXN PI_TXP PI_RXN PI_RXP PI_TXN PI_TXP UVKX-P 0 UVKX-P UVKX-P UVKX-P UVKX-P UVKX-P 0 UVKX-P UVKX-P 0 UVKX-P UVKX-P PI_# PI TXN PI TXP PI TXN PI TXP PI TXN PI TXP PI TXN PI TXP PI TXN PI TXP U_O#0 U_O# U_O# U_O# U_O# U_O# U_O# U_O# U_O# U_O# P P N N M M L L K K J J H H F F F J F J H U OF PRN MI0RXN PRP MI0RXP PTN MI0TXN PTP MI0TXP PRN MIRXN PRP MIRXP PTN MITXN PTP MITXP PRN MIRXN PRP MIRXP PTN MITXN PTP MITXP PRN MIRXN PRP MIRXP PTN MITXN PTP MITXP PRN MI_LKN PRP MI_LKP PTN PTP MI_ZOMP MI_IROMP PRN/LN_RXN PRP/LN_RXP UP0N PTN/LN_TXN UP0P PTP/LN_TXP UPN UPP PI_LK UPN PI_0# UPP PI_# UPN UPP PI_MOI UPN PI_MIO UPP UPN O0# UPP O#/PIO0 UPN O#/PIO UPP O#/PIO U UPN O#/PIO UPP O#/PIO UPN O#/PIO0 UPP O#/PIO UPN O# UPP O# URI# URI IH-M--P-U-NF PI-xpress PI irect Media Interface V V U U Y Y W W T T Y Y H H H H J J K K K K L L M M M M N N F F MI_RXN0 MI_RXP0 MI_TXN0 MI_TXP0 MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP LK_PI_IH# LK_PI_IH MI_IROMP MI_RXN0 MI_RXP0 MI_TXN0 MI_TXP0 U_PN0 U_PP0 U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP URI R RF-L-P Within 00 mils V_0 MI_RXN MI_RXP MI_TXN MI_TXP R 0RJ--P MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP LK_N# LK_PI_IH# LK_PI_IH Within 00 mils V_0 R RF-L-P U U_ New ard ard Reader RF or T MINIR MR Finger Printer U_. <ore esign> U_. Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IH(/) PM,U,PIO ize ocument Number Rev ustom M-iscrete unday, eptember 0, 00 ate: heet of 0 R0 Y K_PWR 0RJ--P R VRMPWR 0RJ--P Q N00--P

21 V_P_0 IH_VRF_U IH_VRF_RUN V_0_LNPLL V_0_TPLL V_MIPLL_0 IH_VRF_U IH_VRF_RUN V_LN_0_INT_IH_ V_LN_0_INT_IH_ VL_0_IH VU IH_ VU IH_ V_ +RTV V_0 V_0 V_0 V_ V_ V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 0V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 0V_0 V_0 V_0 V_ V_ V_0 V_0 ize ocument Number Rev ate: heet of Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IH(/) POWR&N ustom Thursday, ugust, 00 M-iscrete <Variant Name> ize ocument Number Rev ate: heet of Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IH(/) POWR&N ustom Thursday, ugust, 00 M-iscrete <Variant Name> ize ocument Number Rev ate: heet of Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IH(/) POWR&N ustom Thursday, ugust, 00 M-iscrete <Variant Name> 0 mils 0 mils (T) (MI) 0 mils 00 MV T0UVM-P T0UVM-P UVZY-P UVZY-P TP0 TP0 0UVMX-P 0UVMX-P L IN-UH--P L IN-UH--P 0 UVZY-P 0 UVZY-P UVZY-P UVZY-P 0 UVMX-P 0 UVMX-P L LMPN-P L LMPN-P TP TP U0VZY-P U0VZY-P UVMX--P UVMX--P 0UVKX-P 0UVKX-P UVZY-P UVZY-P TP TP TP TP L LMPN-P L LMPN-P UVZY-P UVZY-P K HH-0PT-P HH-0PT-P UVZY-P UVZY-P 0UVMX-P 0UVMX-P TP0 TP0 TP TP U0VZY-P U0VZY-P UVZY-P UVZY-P U0VZY-P U0VZY-P TP TP L LMPN-P L LMPN-P UVZY-P UVZY-P VRT VRF T VRF VRF_U V V V U V V V U V V V W V Y V V V V V V V V V V V V F V F V V H V H V J V J V K V K V L V L V L V M V M V N V N V N V P V P V R V R V R V R V T V T V T V T V T VTPLL J V_0 L V_0 M V_0 P V_0 T V_0 U V_0 V V_0 V_0 L V_0 V V_0 V_0 V_0 V_0 V_0 V_0 V_0 F V_0 L V_0 V V_0 L V_0 V V_0 L V_0 V V_0 L V_0 M V_0 P V_0 T V_0 U V_0 V V W V V V F V V H V J V V 0 V V V V V V F V L V M V L V M V V V H V V V VUPLL VLN_0 F VLN_0 VLN_ F VLN_ 0 VLNPLL VLN_ VLN_ VLN_ VLN_ VLN_ VLN_ VMIPLL R V_MI V_MI V_PU_IO V_PU_IO V_ W V_ V V_ V_ F V_ V_ V_ V_ F V_ W V_ V_ W V_ Y V_ V_ V_ V_ V_ 0 V_ F V_ V_ V_ V_ V_ U V_ VH VUH VU_ VU_ J VU_0 J VU_0 F0 VU_ VU_ 0 VU_ VU_ VU_ H VU_ VU_ P VU_ R VU_ P VU_ P VU_ R VU_ P VU_ P VU_ R VU_ P VU_ R VU_ N VU_ P VU_ VL_ VL_ F0 VL_ VL_0 OF OR VP VP OR I PI RX TX U OR LN POWR VPU VPU U IH-M--P-U-NF OF OR VP VP OR I PI RX TX U OR LN POWR VPU VPU U IH-M--P-U-NF 0 U0VKX-P 0 U0VKX-P 0 UVZY-P 0 UVZY-P 0 UVZY-P 0 UVZY-P K 0 HH-0PT-P 0 HH-0PT-P 0 UVKX-P 0 UVKX-P UVZY-P UVZY-P UVZY-P UVZY-P 0 UVZY-P 0 UVZY-P L LMPN-P L LMPN-P TP TP UVZY-P UVZY-P L N M L N L N N M N L M N M N L M N M N M N N M L K N L N M M _NTF _NTF _NTF H _NTF _NTF J _NTF J _NTF _NTF J _NTF _NTF _NTF H _NTF J 0 F F F F F H0 H H H H F H H H H H H J 0 F F F F 0 H H H H H J J J J J J K K K K K N P P P P P P P P P R R R R R R R R R R T T T T T T T U U U U U U U U U U U V V V V W W W Y Y Y U W UF OF IH-M--P-U-NF UF OF IH-M--P-U-NF 0 UVZY-P 0 UVZY-P TP TP TP TP TP TP 0UVMX-P 0UVMX-P UVZY-P UVZY-P R 00RJ--P R 00RJ--P U0VZY-P Y U0VZY-P Y UVZY-P UVZY-P TP TP TP0 TP0 TP TP UVZY-P UVZY-P UVZY-P UVZY-P 0UVMX-P 0UVMX-P TP TP TP0 TP0 R 00RJ--P R 00RJ--P TP TP U0VKX-P U0VKX-P U0VZY-P U0VZY-P TP TP TP TP 0 0UVMX-P 0 0UVMX-P UVKX-P UVKX-P UVZY-P UVZY-P

22 FN_V V_0 RN *Layout* mil RN0KJ--P UVZY-P _L _ K 0 0U0VZY-P NW--P TP0 TP V_0 R 0KRJ--P TP0 TP TP0 TP 000P0VJN-P FN_F TP0 TP FN_V *Layout* mil TP0 TP0 N -ON--P-U V_0 *Layout* 0 mil R 00RF-L-P U0VZY-P etting T as 00 egree V_R =(((egree-)*0.0)+0.)*v R 00KRF-L-P V_ R 0KRF--P U0VZY-P V_0 TP UVZY-P THRM# THRM# V_R V 0 0 U V V XP XP XP LRT# THRM# THRM_T RT# FUF-P FN F LK L N# N N N N 0 N L Place Top side and close to connector _LK 0 _XN _XP 00P0VKX-P 00P0VKX-P Q PM0--P Q PM0--P THRM THRM U0,0 PM_PWROK LV0PWR-P PM_LP_# 0,,,,,,, _RT# R0 XP:0 egree XP:H/W etting XP: egree P-LO P-LO 0 00P0VKX-P H_THRM H_THRM 00KRJ--P Place near chip as close as possible V_UX_ THRM# V_0 _ U K_ V_0 R 0KRJ--P Y NW--F-P NW--F-P _NL U N _RT# Y V_UX_ V Y PWR N 0 K_L _L UVKX-P N0MX-NL-P N00W--P 0RJ--P R0 <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Thermal/Fan ontrollor ize ocument Number Rev ustom M-iscrete ate: Thursday, eptember, 00 heet of

23 Mini ard onnector Mini ard onnector for ROON V_ V_0 V_ V_0 UVKX-P UVKX-P UVKX-P UVKX-P 00 0 UVKX-P MINI UVKX-P MINI U0VMX-P NP MINI_WK# TP TP0 U0VMX-P NP V_0 MINI_WK# TP TP0 V_0 WL_PRIORITY UVKX-P T_PRIORITY MINI_LKRQ# UVKX-P 0 TP TP0 O LK_PI_MINI# 0 TP TP0 LK_PI_MINI LK_PI_MINI# LK_PI_MINI 0UVKX-P UVKX-P UVKX-P 0UVKX-P UVKX-P OKMINI R UVKX-P _Rx_R _Rx 0RJ--P WWN_N_R _Tx_R _Rx WIRL_N 0 _Tx WWN_N 0RJ--P R 0 0RJ--P _Tx,,0,,,, PLT_RT#,,0,,,, OKMINI PLT_RT# OKMINI R V_ PI_RXN 0 V_ V MINI PI_RXN 0 PI_RXP 0 OKMINI 0RJ--P R PI_RXP 0 Y R Y 0RJ--P M_LK_MINI M_LK_MINI 0, M_LK 0 0RJ--P 0, M_LK 0 M_T_MINI PI_TXN 0 M_T_MINI 0, M_T 0, M_T PI_TXN 0 PI_TXP 0 Y R Y R PI_TXP 0 0 U_PN 0 U_PP 0 V_0 0RJ--P _MINI_0 0 V_0_MINI 0RJ--P V_0 L_WWN# L_WWN#_ TP0 TP OKMINI R TP0 TP0 OKMINI R WLN_L# WLN_L# MINI_ TP0 TP TP0 TP 0RJ--P L_WPN# L_WPN#_ TP0 TP TP0 TP OKMINI R 0 0 V_ V MINI 0RJ--P V_ NP NP OKMINI R KT-MINIP--P.00. KT-MINIP--P.00. 0,,,,,,, PM_LP_#,,0,,,, PLT_RT# RJ--PI_RT#_NW_R TY# R PRT# YRT# NW_PU# PRT# NW_PP# PU# 0 TP0 TP NW_O# PP# O# 0,,, PM_LP_# 0 HN# NWR onnector 0 PI_RXP V_NW_0 V_NW_0 0 PI_RXN 0 LK_PI_NW U0VKX-P U0VKX-P V_NW_0 LK_PI_NW# 0 NW_PP# 0 0 NWR_LKRQ# U0VKX-P U0VKX-P V_NW_LN_ PRT# U0 0,, PI_WK# Y PI_WK#_R R 0RJ--P V_NW_0 0 RNJ--P-U M_T_NW 0, M_T M_LK_NW N 0, M_LK Y ONN_TP RN ONN_TP THRML_P TP0 TP TP0 TP U0VKX-P NW_PU# NW_PU# NW_PP# RU-P R 0RJ--P P0VJN-P V_0 V_0 U0VKX-P KT U0VKX-P bom.vout.vout.vin.vin.vout.vout.vin.vin U0VKX-P U0VKX-P U0VKX-P U0VKX-P RLKN UXIN UXOUT N# NW_LKN U0VKX-P TPTP0 V_ V_NW_LN_ NP RUP--P.H0.0 For Newcard socket 0 PI_TXP 0 PI_TXN 0 0 U_PP U_PN Y TYO-ON--P.00. Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. MINI R / NW R ize ocument Number Rev M-iscrete NW ate: Thursday, ugust, 00 heet of

24 Y R0 0R-0-U-P V_LN_ R0 V 0 mils They are for U V pin- and V_ 0 ~ 00 mils R 0KRJ--P Q O0-P V_LN_ 0 ~ 00 mils 0 P-LO-PWR 0R00-P UVZY-P 0 UVZY-P V V R0 KR-P M-WMNTP-P TRL Q PT--P V.V.V Y Only For F They are for U V V pin-,, and L V Y R P0VJN--P 0 mils 0 mils V X Q Q XTL-MHZ-0-P Please IN-UH--P 0R-0-U-P 0 RMOV RTL Need Need RMOV.000. lose PIN TUFF R R 0RJ--P 0R-0-U-P P0VJN--P RTL N/ N/ UVKX-P R 0KRJ--P Y Y N R 0R00-P LN_ LN_K LN_I LN_O Y U0VKX-P, PM_LN_NL U Q V U OR N R : I.K R KRF--P V RTL_RT_ TRL/V V LN_X LN_X V V T_L# LINK00 V V UVZY-P N PROM L OPTION U '0' (FIN IN P) => L0 : T => L : LINK (OTH 0/00 N I HIP) LINK V V N RT VR NR KTL KTL 0 V V L0 L L L V V V PI_RXP_ PI_RXN_ N V T_L# LINK00 LINK V OPIO IPIO 0 N# N# LNWK# PRT# V V HIP HIN N RFLK_P RFLK_N V HOP HON N V 0 0 Q N00--P V RTL-R-P.0.0 Power domain chart V V V RTL0 V/F RTL / RTL0.V.V.V N/ RTL.V.V.V V Only For 0 V Only For They are for U V pin-,, and 0/ TUFF 0/ TUFF Y RMOV R 0RJ--P F RMOV R MLK R 0, M_LK Y 0RJ--P Y V/LKRQ R 0RJ--P V R MT R TRL/V TRL 0, M_T R 0RJ--P 0RJ--P <Variant Name> 0,, PI_WK# R0 0RJ--P PI_WK#_LN PIRT# PIRT# R 0RJ--P V 0 PI_TXP PI_TXP 0 PI_TXN PI_TXN 0 Wistron orporation LK_PI_LN LK_PI_LN Y F,, ec., Hsin Tai Wu Rd., Hsichih, LK_PI_LN# LK_PI_LN# UVZY-P Taipei Hsien, Taiwan, R.O.. 0 PI_RXP PI_RXP U0VKX-P UVMX-P 0/ RMOV 0 PI_RXN PI_RXN U0VKX-P TUFF N/ TUFF RMOV UVZY-P They are for U V pin- and U TUFF P Only For R RMOV P V 0R-0-U-P Y TRL LN_K V ROUT K Only For LN_I MIP0 V I/UX V TRL MIP0 MIN0 MIP0 V LN_O V_0 MIN0 V/F MIN0 O Q0 LN_ They are for U V MIP F PT--P V MIP pin-,,,,,,,, and MIN MIP V Y MIN V MIN N# R V Only For 0 MIP V N# R 0 mils V MIP MIN MIP N#0 0 KRJ--P MIN 0 V MIN N# V MIP V V 0R-0-U-P V MIP MIN MIP V 0 0 IOLT# MIN V MIN IOLT# V V N# Y Y V N# N# V/LKRQ V LKRQ R KRF-P Y R 0RJ--P Y UVMX-P UVMX-P UVMX-P UVMX-P UVMX-P UVZY-P UVZY-P 0 UVZY-P UVZY-P UVZY-P R 0R-0-U-P UVZY-P UVZY-P UVZY-P UVZY-P UVZY-P 0 mils UVZY-P V RTL/0 M-iscrete ize ocument Number Rev ate: unday, eptember 0, 00 heet of UVZY-P UVZY-P UVZY-P 0 UVZY-P UVZY-P UVZY-P UVZY-P UVZY-P UVZY-P UVZY-P

25 0mil V 0 : R( 0 ohm ) XF(N) / : R (N) RX+ RX-.route on bottom as differential pairs. ONN_PWR_ XF R 0RJ--P R0 R 0RJ--P.Tx+/Tx- are pairs. Rx+/Rx- are pairs. 0R00-P MIP RJ_ MIP.No vias, No 0 degree bends. RJ MIN T+ TX+ RJ_ MIN T- TX-.pairs must be equal lengths. LINK00 MIP LINK00 MIP.mil trace width,mil separation. ONN_PWR_ R+ RJ--P MIN MIN LINK MT R- R0 T.mil between pairs and any other trace. LINK MT T 0 RJ_ 0RJ--P R.Must not cross ground moat,except RJ_ TT T RX+ RJ_ RJ_ T RX- UVKX-P RJ- moat. Y RJ_ RJ_ RJ_ Y XFORM-0-P RJ--P RJ_ RJ_ R RJ_ XF ONN_PWR_ 0UVKX-P 0UVKX-P 0UVKX-P 0UVKX-P MIP0 MIN0 MIP0 MIN0 MT MT Lan Transformer T T 0 T T R+ R- T+ T- TX+ TX- XFORM-0-P RJ_ RJ_ MIP MIN RJ_ RJ_ 0/00/000Mbps Lan Transformer FOR 0/00 0 R0,R,R0,R TUFF MIP MIN MIP0 MIN0 R RF-P RN MT MT LN_TRMINL MT I no need it at all, 0/00 keep MT 0 KPKVKX-P MI0X MIP MIN R R 0 0U0VZY-P RF-P RF-P V_LN_ MIX R0 0U0VZY-P RF-P ONN_PWR_ R 0RJ--P UVKX-P Y T_L# reen : Link up linking : TX/RX activity PIN0 : RN PIN : ORN PIN : YLLOW Off : Link 0 Mbps reen : Link 00 Mbps Orange : Link 000 Mbps RJ--P-U 0 RNJ--P <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. LN connector/nw R/IM ize ocument Number Rev ustom M-iscrete ate: unday, eptember 0, 00 heet of

26 RF V_RF_0 Webam TP0 TP TP0 TP U_- U_+ 0 0 U_PN U_PP R 0R00-P U_N_RF 0RJ--P RF RF R0 U_P_RF 0RJ--P 0R00-P R0 R UVKX-P RF TP0 TP TP0 TP U_- U_+ RF TPTP0 TPTP0 TPTP0 TPTP0 RF -ON--P-U 0 0 U_PN U_PP L-UH-P TR UVKX-P V_M_0 TP0 TP U_- U_+ TP0 TP0 TP0 TP TP Place Top side and close to connector M TY-ON--P TPTP0 TPTP0 RF_N# TP0 TP (O) 0 mil RF_N# U_O# UVZY-P V_ RF 00u rise time upply.~. U IN# IN# N/N# O# OUT# OUT# OUT# RU-P RF N N V_RF_0 Place Top side and close to connector 0UVKX-P RF 0 mil UVKX-P RF 0 UVZY-P V_0 U HN# N IN F-P T OUT WM_T R KRF-P Y V_M_0 0RJ--P R (.V) 0RJ--P R Y R KRF-P 0UVKX-P V_0 V_0 Finger Printer N PTWO-ON--P-U FP TPTP0 TPTP0 UVKX-P FP V_0 FP 0UVKX-P Place Top side and close to connector TPTP0 TP0TP0 TPTP0 U_PN 0 U_PP 0 TPTP0 LUTOOTH_N T U0VZY-P LUTOOTH_N V_ U HN# N IN U_PP U_PN T_PRIORITY WL_PRIORITY T T OUT F-P U0VZY-P T T R U_P_T 0RJ--P T R U_N_T 0RJ--P T_PRIORITY WL_PRIORITY V_T_0 T TP0 TP0 TP0 TP 0 UVZY-P Y R 00KRJ--P Y TP0 TP TP0 TP TP0 TP V_T_0 TP0 TP TP0 TP TP0 TP R0 00KRJ--P TP0 TP T_T LUTOOTH_N T_L bom 0 N -ON0--P-U T TPTP0 TPTP0 TPTP0 Place Top side and close to connector FP / amera / RF / T M-iscrete Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev ate: Thursday, eptember, 00 heet of