AG1(Alviso) Block Diagram 2005/11/01

Size: px
Start display at page:

Download "AG1(Alviso) Block Diagram 2005/11/01"

Transcription

1 (lviso) lock iagram 00//0 LK N. Mobile PU Project ode:.0.00 P:0-0 Line Out R II 00 MHz R II 00 MHz Line In Int. MI In INT.PKR P Layer tackup L: ignal L:V L: ignal L: ignal L: N L: ignal IT V,, odec L OP MP 00MHz 00MHz MOM M ard, LINK H 0 HOT U Intel 0ML MI I/F othan IH-M PT 00MHz 00MHz ROM 0,,,,0,,, U PORT PI U LP U R LV MINI U lue-tooth N 0 RT ONN L X, LN 0/00 RTL0L, K N K0 PWR W P Mini-PI 0.// TXFM Xbus Touch INT_K Pad 0 0 PMI ON LOT RJ IO ROM M IT PMLV00-0J <ore esign> LOK IRM ILV-T INPUT TM / TP0 INPUT OUTPUT TOUT INPUT TOUT V_ PU / TOUT V_ V_ PL-L PL0- INPUT OUTPUT V_ V_0 TM / IL V_ TP00Q INPUT HRR TOUT OUTPUT V_OR 0.~.V IL V_0 V_0 OUTPUT V_ R_VRF OUTPUT T+.V Wistron orporation Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev ustom ate: Tuesday, November 0, 00 heet of 0 R_VRF_ (lviso) 0

2 lviso trapping ignals and onfiguration page Pin Name F[:0] IH-M Integrated Pull-up and Pull-down Resistors Z_IT_LK, PRLP#, _IN, _OUT, NT[]#/PO[], NT[]#/PO[], LRQ[]/PI[], L[:0]#/F[:0]#, LRQ[0], IH internal 0K pull-ups F[:] F F F F[:] F[:] F[:] F F F PM#, PWRTN#, TP[] LN_RX[:0] Z_RT#, Z_IN[:0], Z_N, Z_OUT,Z_ITLK, PRLPVR, PKR, _, U[:0][P,N] [], RQ F F0 VORTL _T trap escription F Frequency elect Reversed MI x elect R I / R II PU trap Reversed XOR/LL Z test straps Reversed F ynamic OT Reversed PU core V elect PU VTT elect Reversed VO Present onfiguration 000 = Reserved 00 = F 00 = F00 0- = Reversed 0 = MI x = MI x (efault) 0 = R II = R I 0 = Prescott = othan (efault) 00 = Reserved 0 = XOR mode enabled 0 = ll Z mode enabled = Normal Operation (efault) 0 = ynamic OT isabled = ynamic OT nabled (efault) 0 =.0V =.V (efault) 0 =.0V (efault) =.V 0 = No VO device present (efault) = VO device present NOT: ll strap signals are sampled with respect to the leading edge of the lviso MH PWORK In signal. PI Routing 0 MiniPI LN IL IRQ.F. F RQ/NT 0 LN_LK [:0], IOW#, IOR#, RQ, K#, IOR, [:0], #, #, IIRQ IH internal 0K pull-ups IH internal 0K pull-downs approximately ohm IH-M 0 0.V IH internal K pull-downs IH internal.k pull-downs IH internal 00K pull-downs IH-M I Integrated eries Termination Resistors Wistron orporation Taipei Hsien, Taiwan, R.O.. <ore esign> Memo ize ocument Number Rev ate: Tuesday, November 0, 00 heet of 0 (lviso) 0

3 V_0 V_0 V_0 R 0R00-P V_PWR_0 U0VZ-P UVZ-P R0 RJ--P V_MPWR_0 0 UVKX-P 0 UVZ-P R0 0R00-P V_LKN_0 0 0U0VZ-P 0 UVZ-P UVZ-P 0 UVZ-P IN (V_0) H X N (_POO) L H OUT (VTT_PWR#) H Hi - Z -0-0 V_LKN_0 R0 KRJ--P R KRJ--P R KRJ--P F_ F_ -0-0 F_ -0-0 PU_L PU_L0, F_ PU M 0 0 M M 0 M 0 0 M 0 00M 0 00M Reserved PLK_MINI PLK_LN PLK_PM PLK_K LK_IHPI -0- V_0 P0VJN-P -- PM_TPPI#, M_IH, M_IH RFLK RFLK# X X-M-P 0 P0VJN--P R RJ--P RN RNJ--P LK_udio LK_IH LK_IH & LK_IO need equal length ITP_N PLK_MINI_ PLK_LN_ PLK_PM_ PLK_K_ H/L: 00/MHz _L H/L : PU_ITP/R RN RNJ--P-U RFLK_ RFLK#_ XTL_IN XTL_OUT RN RNJ--P-U R RF-L-P VTT_PWR# PI0 PI PI PI PIF/L00/# PIF0/ITP_N PI_TOP# L OT OT# XTL_IN XTL_OUT RF IRF VTT_PWR#/P V_PI V_PI V_RF V_PU V V V_R U V_PI V_PI nd LV LV# R R# 0 R R# R R# R R# R R# 0 R R# PU_ITP/R PU_ITP#/R# PU0 PU0# PU PU# 0 PU_TOP# F/TT_L F/TT_MO U/F V_R V_R V_RF V_PU V V V_R RFLK RFLK# LK_PI_IH LK_PI_IH# LK_MH_PLL LK_MH_PLL# LK_PU_LK LK_PU_LK# LK_MH_LK LK_MH_LK# PU_L0 PU_L F_ RN0 R0 V_LKN_0 V_PWR_0 V_MPWR_0 RN RJ--P RN RNJ--P-U RN RN RNJ--P-U RNJ--P RNJ--P-U RNJ--P-U LK_IH -0-0 RFLK RFLK# LK_PI_IH LK_PI_IH# LK_MH_PLL LK_MH_PLL# LK_PU_LK LK_PU_LK# LK_MH_LK LK_MH_LK# PM_TPPU#, ITVP-P --, _POO VTT_PWR# Q N00PT-U RN RN0KJ--P R0 0KRJ--P ITP_N _L R0 0KRJ--P -- LK_PU_LK LK_PU_LK# LK_MH_LK LK_MH_LK# LK_MH_PLL LK_MH_PLL# LK_PI_IH LK_PI_IH# RFLK# RFLK RFLK# RFLK RN0 RNF-P RN RNF-P RN RNF-P RN -0-0 RNF-P RN0 RNF-P RN RNF-P LK_IH PLK_PM PLK_MINI PLK_K LK_IHPI LK_IH <ore esign> MI capacitor 0P0VJN-P 0P0VJN-P 0 0P0VJN-P 0P0VJN-P 0P0VJN-P 0P0VJN-P lock enerator - IT Wistron orporation Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev ate: Friday, October, 00 heet of 0 (lviso) 0

4 R ROUP R ROUP 0 HLK THRM XTP/ITP INL ONTROL U TUL-KT- TP 0V_0 H_# H_#[..] P H_# # # N H_# U H_# # NR# L H_NR# V H_# # PRI# J H_PRI# R -0-0 H_# # V H_# # FR# L H_FR# R W H_# # R# H RJ--P H_R# T H_#0 # # M H_# W H_# 0# Place testpoint on H_# # R0# N H_RQ#0 H_IRR# with a N H_# # U H_IRR# 0." away H_# # IRR# H_# # INIT# H_INIT# H_# # # LOK# J H_LOK# H_T#0 U T#0 H_PURT# H_RQ#[..0] H_RQ#0 RT# H_R#[..0] R H_R#0 H_RQ# RQ0# R0# H H_R# U P H_RQ# RQ# R# K H_#[..0] T H_R# H_RQ# RQ# R# L TUL-KT- P H_#0 H_# H_RQ# RQ# TR# M H_TR# H_# 0# # H_INV#[..0] T H_# RQ# H_# # # H_# H_# HIT# K H_HIT# H_# # # T H_TN#[..0] F H_# H_HITM# H_# # HITM# K H_# # # U H_# H_# # XP_PM#0 H_# # # V H_TP#[..0] H_# H_#0 PM#0 TP TP # XP_PM# H_# # # R H_# H_# PM# TP TP 0# XP_PM# H_# # # R H_# H_# PM# TP TP # 0 XP_PM# H_# # # R H_#0 H_# # PM# TP TP 0 XP_PM# H_# # 0# H_# H_# # PR# 0 TP TP XP_PM# TP TP H_#0 # # U H_# H_# # PRQ# 0 XP_TK H_# H_# H_# # TK TP TP 0# # V XP_TI TP TP H_# # # U H_# H_# # TI XP_TO H_# H_# H_# # TO # # V TP TP XP_TM H_# H_# H_# # TM # # TP TP F XP_TRT# H_# # # H_# H_#0 # TRT# TP TP XP_RT# H_TN#0 # # H_TN# H_# 0# R# TP TP F H_TP#0 TN0# TN# W H_TP# # PU_PROHOT# H_INV#0 TP0# TP# W H_INV# H_T# T# PROHOT# TP TP INV0# INV# T THRM H_THRM H_0M# 0M# THRM H_THRM H_# H_# H_FRR# FRR# H PM_THRMTRIP-I#,, H_# # # H_# H_INN# INN# THRMTRIP# -- H_# # # L H_#0 -- H_# # 0# H_# H_TPLK# TPLK# ITP_LK M H_#0 # # 0 H_# H_INTR LINT0 ITP_LK0 H LK_PU_LK# H_# 0# # H_# H_NMI LINT LK F LK_PU_LK H_# # # H_# H_MI# MI# LK0 H_# # # J H_# H_# # # M H_# PM_THRMTRIP# H_# # # F J H_# Layout Note:.00.0 should connect to H_# # # L H_# omp0, connect with Zo=. ohm, make ONNTOR IH and lviso H_# # # F0 N H_# trace length shorter than 0.". without T-ing H_# # # M H_#0 omp, connect with Zo= ohm, make _- : ( No stub) H_# # 0# H H_# trace length shorter than 0.". H_#0 # # F N H_# H_# 0# # F K H_# H_TN# # # F K H_TN# -0-0 H_TP# TN# TN# L H_TP# H_INV# TP# TP# J H_INV# INV# INV# 0 0V_0 To V-OR WITH TP OMP0 R RF-L-P TP PI# OMP0 P R OMP OMP P R RF-L-P OMP, PU_L0 0R-0-U-P L0 OMP R RF-L-P OMP L OMP R RF-L-P R TP0 TP 00RF-L-P 0V_0 0V_0 MI PRTP# H_PRLP# -0-0 RV PLP# H_PLP# -0-0 TP0 TP F H_PWR# PU_PROHOT# TP TP RV PWR# R RF--P R H_PWR, KRF--P TP TP RV PWROO H_PULP#, XP_TI TP TP RV LP# R 0RF--P XP_TM R RF-P TLRF0 TT TP TP TLRF0 TT TT Layout Note: TT F TP TP XP_TO R RF-L-P 0." max length. -- H_PURT# TP R RF-L-P V_0 XP_RT# R 0RF--P R KRF-L-P L[:0] Freq.(MHz) ( tepping) L L 00 L H T RP 0 T RP T RP T RP.00.0 ONNTOR XP_TK R RF-L-P L[:0] Freq.(MHz) ( tepping) <ore esign> XP_TRT# R0 0RF-P L H 00 L L ll place within " to PU -0-0 Wistron orporation Taipei Hsien, Taiwan, R.O.. PU ( of ) ize ocument Number Rev (lviso) 0 ate: Monday, October, 00 heet of 0

5 TP_VN TP_VN V_OR_0 V_OR_0 V_0 0V_0 V_OR_0 V_OR_0 V_OR_0 0V_0 H_VI0 H_VI H_VI H_VI H_VI H_VI ize ocument Number Rev ate: heet of Wistron orporation Taipei Hsien, Taiwan, R.O.. PU ( of ) 0 Monday, October, 00 (lviso) 0 <ore esign> Layout Note: should be of equal length. Layout Note: Provide a test point (with no stub) to connect a differential probe between VN and VN at the location where the two.ohm resistors terminate the ohm transmission line. VN and VN lines UVKX-P 0UVKX-P TP TP TP TP U TUL-KT ONNTOR V0 V V V V V V V V V 0 V0 V V V V 0 V V V V V V0 V V V V 0 V V V V V V0 V V V V V V F0 V F V F V F V0 F V F V V 0 V V V V V V V0 V V V F V F0 V F V F V F V V V0 H V H V J V J V K V U V V V V V W V W V0 V V0 F V V N V VP0 0 VP VP VP VP VP VP VP F0 VP F VP F VP0 F VP K VP L VP L VP M VP M VP N VP N VP P VP P VP0 R VP R VP T VP T VP U VQ0 P VQ W VI0 VI F VI F VI VI VI H VN VN F 0UVKX-P UVZ-P 0 0UVKX-P 0UVKX-P 0 0UVKX-P UVZ-P U TUL-KT ONNTOR V V V V V V 0 V V V V0 V V V 0 V V V V V 0 V V0 V V V V V V V V V V0 V V V V V V 0 V V V V0 V V V V V V V V V V0 V V V V V V V 0 V V V0 V V 0 V V V F V F V F V F V F V0 F V F V F V F V F V V V V V V0 V V V V V V 0 V V V V0 V V V0 V V V V V V W V W V V V V00 V0 V0 V0 V0 V0 V0 V0 0 V0 V0 V0 V V 0 V V V F V F V F V F V F V0 F V F V F V F V F V F V V V V0 V V H V H V H V H V J V J V J V J V0 J V K V K V K V K V K V L V L V L V L V0 M V M V M V M V M V N V N V N V N V N V0 P V P V P V P V R V R V R V R V R V T V0 T V T V T V T V U V U V U V U V V V V V0 V V V V V V W V W V W V0 V V V F UVZ-P UVZ-P 0 UVZ-P UVZ-P 00 0UVKX-P T T00UVM-P 0UVKX-P UVZ-P 0 UVZ-P UVZ-P UVZ-P 0 0UVKX-P UVZ-P 0U0VZ-P

6 H_XROMP -0-0 H_#0 H_# H_# H0# H# H_# H_# H# H# F H_# H_# H# H# H H_# H_# H# H# H_# 0V_0 H_# H# H# 0 F H_# H_# H# H# F H_# H_# H# H# H_#0 H_# H# H0# 0 K H_# H_# H# H# 0 F H_# H_#0 H# H# 0 J H_# H_# H0# H# RF-L-P J H_# H_# H# H# R H H_# H_# H# H# F0-0-0 F H_# H_# H# H# K H_# H_XOMP H_# H# H# H H_# H_# H# H# 0 H H_# H_# H# H# H H_#0 H_# H# H0# K H_# 0V_0 H_# H# H# K H_# H_#0 H# H# J H_# H_# H0# H# H_# H_# H# H# F H H_# R H_# H# H# J H_# RF--P H_# H# H# L H_# 0V_0 H_# H# H# K H_# H_# H# H# J H_# H_XWIN H_# H# H# P H_#0 H_# H# H0# L H_# R H_# H# H# F J 00RF-L-P-U R H_#0 H# P H_# 00RF-L-P-U H_# H0# H# F L H_T#0-0-0 H_# H# HT#0 UVZ-P U H_T# H_# H# HT# V H_VRF H_# H# HVRF J R H_NR# H_# H# HNR# R H_PRI# H_# H# HPRI# P H_RQ#0 H_# H# HRQ0# R T H_PURT# H_# H# HPURT# H0 00RF-L-P R -0-0 H_# H# R H_#0 H# U H_ROMP H_# H0# R LK_MH_LK# H_# H# HLKINN T LK_MH_LK H_# H# HLKINP T H_# H# R H_# R H_# H# H# T H_FR# RF-L-P H_INV#[..0] H_# H# HFR# V H_INV#0 H_# H# HINV#0 H U H_INV# -0-0 H_# H# HINV# K W H_INV# H_# H# HINV# T U H_INV# H_#0 H# HINV# U V H_PWR# H_# H0# HPWR# W H_R# H_TN#[..0] H_# H# HR# F W H_TN#0 H_# H# HTN#0 U H_TN# 0V_0 H_# H# HTN# K U H_TN# H_# H# HTN# R H_TN# H_TP#[..0] H_# H# HTN# V H_TP#0-0-0 H_# H# HTP#0 V H_TP# H_# H# HTP# K H_TP# H_# H# HTP# R H_TP# W RF-L-P H_#0 H# HTP# W W TP_H_R# TP TP R H_# H0# HR# F H_HIT# H_# H# HHIT# H_HITM# H_# H# HHITM# W H_LOK# H_OMP H# HLOK# TP_H_PRQ# H_RQ#[..0] H_XROMP HPRQ# H_RQ#0 TP TP H_XOMP HXROMP HRQ#0 H_RQ# H_XWIN HXOMP HRQ# H_RQ# 0V_0 H_ROMP HXWIN HRQ# T H_RQ# H_OMP HROMP HRQ# L H_RQ# H_R#[..0] H_WIN HOMP HRQ# P H_R#0 HWIN HR0# H_R# HR# R H_R# HR# RF--P HPULP# H_PULP#, HTR# H_TR# R0 RF-L-P H_WIN H_#[..0] U HOT H_#[..] UVZ-P R 00RF-L-P-U -0-0 UVZ-P.0MH.0U <ore esign> Place them near to the chip Wistron orporation Taipei Hsien, Taiwan, R.O.. MH ( of ) ize ocument Number Rev (lviso) 0 ate: Tuesday, October, 00 heet of 0

7 VO_TRLT VO_TRLLK LI LK I LTL_T LTL_LK LKLT_RTL L_LV L_VRFH L_VRFL F F0 PM_XTT# MLW MXLW M_ROMPP M_ROMPN MI_RXP MI_RXP MI_RXP MI_RXP0 MI_RXN MI_RXN MI_RXN MI_RXN0 MI_TXP MI_TXP MI_TXP MI_TXP0 MI_TXN MI_TXN MI_TXN MI_TXN0 M_OOMP M_OOMP0 M_ROMPN M_ROMPP T I PM_XTT#0 PM_XTT#0 PM_XTT# VT_PWR LI L_ON LKLT_RTL VN LTL_T LTL_LK LK I T I HN RTIRF V_ V_0 R_VRF_ V_0 0V_0 V_PI_0 MH_LK MH_T MH_TXLK+ MH_TXLK- MH_TXOUT0+ MH_TXOUT0- MH_TXOUT+ MH_TXOUT- MH_TXOUT+ MH_TXOUT- RFLK RFLK# RFLK RFLK# PLT_RT#,, VT_PWR, L_ON MH_LU MH_RN MH_LV_ON MH_R M_K0, M_K, M_K, M_K, M_LK_R0 M_LK_R M_LK_R M_LK_R M_LK_R#0 M_LK_R# M_LK_R# M_LK_R# M_#0, M_#, M_#, M_#, M_OT0, M_OT, M_OT, M_OT, PM_MU# PM_THRMTRIP-I#,, LK_MH_PLL LK_MH_PLL# MI_RXN0 MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP LK I T I PU_L0, PU_L MH_TXOUT0+ MH_TXOUT0- MH_TXOUT+ MH_TXOUT- MH_TXOUT+ MH_TXOUT- MH_TXLK- MH_TXLK+ MH_VN MH_HN ize ocument Number R ev ate: heet of Wistron orporation Taipei Hsien, Taiwan, R.O.. MH ( of ) ustom 0 Tuesday, October, 00 (lviso) 0 <ore esign> Layout Note: Route as short as possible and TRLT pulldowns on-die lviso will provide VO_TRLLK F[:0] Freq.(MHz) R 0RF--P TP TP R 0RF-P RN RNKJ--P R RJ-L-P R RJ-L-P MI TV V LV PI-XPR RPHI U.0MH.0U VOTRL_T H VOTRL_LK H LKN LKP TV_ TV_ TV_ TV_RFT J TV_IRTN TV_IRTN TV_IRTN LK T LU LU# RN 0 RN# 0 R R# VN H HN RFT J0 LKLT_RTL LKLT_N F LTL_LK LTL_T L_LK F L_T F LV_N F LI LV LVRFH F LVRFL F LLKN 0 LLKP LLKN LLKP LTN0 LTN LTN LTP0 LTP LTP LTN0 LTN LTN LTP0 LTP LTP XP_OMPI XP_IOMPO XP_RXN0 0 XP_RXN F XP_RXN 0 XP_RXN H XP_RXN J0 XP_RXN K XP_RXN L0 XP_RXN M XP_RXN N0 XP_RXN P XP_RXN0 R0 XP_RXN T XP_RXN U0 XP_RXN V XP_RXN W0 XP_RXN XP_RXP0 0 XP_RXP XP_RXP F0 XP_RXP XP_RXP H0 XP_RXP J XP_RXP K0 XP_RXP L XP_RXP M0 XP_RXP N XP_RXP0 P0 XP_RXP R XP_RXP T0 XP_RXP U XP_RXP V0 XP_RXP W XP_TXN0 XP_TXN F XP_TXN XP_TXN H XP_TXN J XP_TXN K XP_TXN L XP_TXN M XP_TXN N XP_TXN P XP_TXN0 R XP_TXN T XP_TXN U XP_TXN V XP_TXN W XP_TXN XP_TXP0 XP_TXP XP_TXP F XP_TXP XP_TXP H XP_TXP J XP_TXP K XP_TXP L XP_TXP M XP_TXP N XP_TXP0 P XP_TXP R XP_TXP T XP_TXP U XP_TXP V XP_TXP W TP TP TP TP R 00RJ--P R 0RF-L-P R RF-P R 0KRJ--P UVZ-P 0 UVMX--P RN RN00KJ--P RN RN0KJ--P R RF-L-P R 0RF-P R MUXIN N LK PM MI F/RV U.0MH.0U MIRXN0 MIRXN MIRXN MIRXN MIRXP0 MIRXP MIRXP MIRXP MITXN0 MITXN MITXN MITXN MITXP0 MITXP MITXP MITXP M_K0 M M_K L M_K M_K J M_K F M_K 0 M_K0# N M_K# K M_K# 0 M_K# J M_K# F M_K# 0 M_K0 P M_K M M_K H M_K K M_0# N M_# M M_# H M_# M_OOMP0 F M_OOMP F M_OT0 P M_OT L M_OT M M_OT N0 MROMPN K0 MROMPP K MVRF0 F MVRF MXLWIN MXLWOUT MLWIN F MLWOUT F0 F0 F H F F F F F F F F F J F F0 F F F H F F H F J F H F F F0 RV RV RV J RV RV 0 RV RV M_U# J XT_T0# J XT_T# H THRMTRIP# F PWROK 0 RTIN# RF_LKN RF_LKP RF_LKN RF_LKP N P N N N P N P N P N N N N N N0 N R 0RF-L-P R KRF--P R 0RF--P UVZ-P R 0KRJ--P RN RNKJ--P R 0RF--P TP0 TP R KRJ--P UVMX--P TP TP

8 U U M Q[..0] M Q[..0] M Q0 M Q0 M Q Q0 _0# K M #0, M Q Q0 _0# J M #0, H M Q Q _# K M #, M Q Q _# M #, L M Q Q _# L M #, M Q Q _# M #, L M Q Q M M[..0] M M0 M Q Q M M[..0] H M M0 M Q Q _M0 J M M M Q Q _M0 F J M M M Q Q _M P M M M Q Q _M K K M M M Q Q _M L F M M M Q Q _M K L M M M Q Q _M P F0 M M M Q Q _M K M M M M Q Q _M P H M M M Q Q _M J0 N M M M Q0 Q _M P H M M M Q0 Q _M K P M M M Q Q0 _M J K M M M Q Q0 _M M M M M Q Q _M 0 M Q Q _M M M Q Q M Q[..0] M Q0 M Q Q M Q[..0] M M Q0 M Q Q _Q0 K M Q M Q Q _Q0 F L M Q M Q Q _Q P H M Q M Q Q _Q K M M Q M Q Q _Q N J M Q M Q Q _Q J N M Q M Q Q _Q P K0 M Q M Q Q _Q K P M Q M Q Q _Q M J0 M Q M Q Q _Q M0 N M Q M Q Q _Q M H M Q M Q Q _Q H P M Q M Q0 Q _Q J H M Q M Q0 Q _Q F L0 M Q M Q Q0 _Q K M Q Q0 _Q M0 M Q#[..0] M Q#[..0] M Q Q H0 M Q#0 M Q Q M M Q#0 M Q Q _Q0# K H M Q# M Q Q _Q0# F L M Q# M Q Q _Q# P M Q# M Q Q _Q# K P M Q# M Q Q _Q# N0 F M Q# M Q Q _Q# K M M Q# M Q Q _Q# N M Q# M Q Q _Q# J M M Q# M Q Q _Q# N J M M Q# M Q Q _Q# L0 M Q# M Q Q _Q# M K L M Q# M Q Q _Q# H M Q# M Q Q _Q# H H M M Q# M Q Q _Q# F M Q# M Q0 Q _Q# H N M [..0], M Q0 Q _Q# M [..0], M Q Q0 P M 0 M Q Q0 M 0 M Q Q _M0 L J M M M Q Q _M0 H M M Q Q _M P 0 L M M Q Q _M K M M Q Q _M P L M M Q Q _M H M M Q Q _M M P M M Q Q _M J M M Q Q _M N H P M M Q Q _M K M M Q Q _M M H P0 M M Q Q _M J M M Q Q _M L H0 L M M Q Q _M K M M Q Q _M P0 J M M M Q Q _M H M M Q0 Q _M M K N M M Q0 Q _M J0 M M Q Q0 _M L0 J N M 0 M Q Q0 _M H0 M 0 M Q Q _M0 M K N M M Q Q _M0 J M M Q Q _M N0 J P M M Q Q _M M M Q Q _M M0 H P M M Q Q _M 0 M M Q Q _M M K M M Q Q _M M Q Q J L M #, M Q Q M Q Q _# N J M M R#, M Q Q M #, M Q Q _R# P K K _RVNIN# M Q Q _# H M R#, M Q Q _RVNIN# F TP TP K _RVNOUT# M Q Q _R# K _RVNIN# M Q0 Q _RVNOUT# F TP TP M W#, M Q0 Q _RVNIN# F TP TP _RVNOUT# M Q Q0 _W# P M Q Q0 _RVNOUT# F TP TP M W#, M Q Q M Q Q _W# H L M Q Q H M Place Test P Near to hip M Q Q M Q Q H M Q Q as could as possible Place Test P Near to hip M Q Q M Q Q ascould as possible M Q Q F M Q Q M Q Q M Q Q M Q Q M Q Q M Q Q M Q Q M Q0 Q F M Q0 Q M Q Q0 F M Q Q0 M Q Q M Q Q M Q Q M Q Q Q Q R TM MMOR R TM MMOR.0MH.0U.0MH.0U <ore esign> Wistron orporation Taipei Hsien, Taiwan, R.O.. MH ( of ) ize ocument Number Rev (lviso) 0 ate: Monday, October, 00 heet of 0

9 V_0 V_LV_0 R V_RLL_0 0R00-P V_0 R0 0 0U0VZ-P 0R00-P T00UVM-P V_0 V_LV_0 R 0R00-P 0 0UVKX-P V_PI_0 V_0 R V_0 V_TV_0 V_0 V_TXLV_0 R R 0R00-P 0U0VZ-P 0R00-P 0R00-P U0VZ-P V_0 V_PLL_0 0U0VZ-P UVZ-P UVZ-P R UVZ-P V_LV_0 V_ 0R00-P 0U0VZ-P Note: ll VM pins shorted internally Note: ll VM pins shorted internally 0 UVZ-P V_TXLV_0 V 0 V_0 UVZ-P UVZ-P R 0U0VZ-P 0U0VZ-P 0U0VZ-P UVZ-P V._R_P V._R_P V._R_P V._R_P V._R_P V._R_P V_LV_0 0R00-P 0 UVZ-P W U R N L J F0 P F F M H P P N M L K J H F P N M L K J H F 0 P N M L K J H F P N M L K J H F 0 P M F F U.0MH.0U V_ F V_ V_PLL0 V_PLL V_PLL V0 V V V V V V V_M0 V_M V_M V_M VTX_LV0 VTX_LV VTX_LV VM0 VM VM VM VM VM VM VM VM VM VM0 VM VM VM VM VM VM VM VM VM VM0 VM VM VM VM VM VM VM VM VM VM0 VM VM VM VM VM VM VM VM VM VM0 VM VM VM VM VM VM VM VM VM VM0 VM VM VM VM VM VM VM VM VM VM0 VM VM VM VM VHV0 VHV VHV V_LV V_LV0 V_LV V_LV V_TV VQ_TV H V_TV H V_TV Route gnd from MH to decoupling cap groung lead and then connect to the gnd plane V_TV0 V_TV V_TV0 V_TV V_TV0 V_TV POWR Route TV gnd from MH to decoupling cap groung lead and then connect to the gnd plane VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 VTT V_N V_RT0 V_RT V_RT VH_MPLL VH_MPLL0 V_PLL V_PLL V_HPLL V_MPLL V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V K J K W V U T R P N M L K W0 V0 U0 T0 R0 P0 N0 M0 K0 J0 W U R P N M L J N M N M N M N M N M N M N M V N M H0 F T R N M K J V U T R P N M L K J H V U T R P N M L K J H K H K J K K K K W0 U0 T0 K0 V U K W V T K K V 0_0 for low speed graphic clock.v_0 for high speed clock.default use 0V_0 VP_MH_P VP_MH_P VP_MH_P VP_MH_P 0V_0 0V_0 R -0- V_0 0R-0-U-P MH_V_N R V_HMPLL_0 V_RT_0 U0VZ-P UVZ-P V_PLL_0 UVKX-P R 0R00-P UVKX-P UVKX-P L UVZ-P UVZ-P UVZ-P U0VZ-P UVZ-P UVKX-P UVKX-P 0R00-P UVZ-P UVZ-P 0U0VZ-P 0R00-P 0V_0 R 0 UVZ-P 0V_0 R 0R00-P KRJ--P V_PLL_0 V_0-0- UVZ-P 0U0VZ-P L V_HPLL_0 Route V_RT gnd from MH to decoupling cap ground lead and then <ore esign> 0R00-P connect to the gnd plane. UVZ-P MLPT-P UVZ-P 0 U0VZ-P UVMX--P L 0R00-P Layout Notes: V_RT Route caps within 0mil of lviso. Route F within " of lviso. 0U0VZ-P Wistron orporation Taipei Hsien, Taiwan, R.O.. UVZ-P V_MPLL_0 L 0R00-P MH ( of ) UVZ-P 0U0VZ-P (lviso) 0 ize ocument Number Rev ate: Monday, October, 00 heet of 0

10 0V_0 0V_0 V_ ize ocument Number Rev ate: heet of Wistron orporation Taipei Hsien, Taiwan, R.O.. MH ( of ) 0 0 Monday, October, 00 (lviso) 0 <ore esign> Place these Hi-Freq decoupling caps near MH UVZ-P V UF.0MH.0U V0 V V V V T V P V M V K V H V V N V0 L V J V F V V V V V V V V0 V W V V V U V T V R V P V N V M V L V0 K V J V H V V F V V V V N V H V0 V V V V V L V F V V W V V V0 U V T V R V P V N V M V L V K V J V H V0 V F V V V N V J V V V V V0 V V V L V V V W V V V U V T V0 R V P V N V M V L V K V J V H V V F V0 V V P0 V 0 V 0 V 0 V 0 V 0 V 0 V M V00 J V0 V0 V0 V0 W V0 V V0 U V0 P V0 L V0 H V0 V F V V V V V V V W V V0 N V L V J V V F V V V W V V V V J V V V V N V L V V V F V V J V L V0 N V V V J V V V F V J V K V V0 J V L V N V V K V V V H V K V L V0 V V F V J V N V V V U V L V V0 H V J V T V W V V N V 0 V 0 V 0 V F0 V0 0 V V0 V K0 V V F V F V N V V V V0 J V H V L V H V F V V V F V J V V0 J V P V T V V V V V H V L V N V V0 V V V V J V V H V L V P V U V0 V F V N V V W V L V P V V J V L V0 P V T V V V V J V V V V V V0 K V N V V V L V P V V L V V H V0 K V0 T V0 V V0 V0 V0 V0 H V0 N V0 0 V0 L0 V00 0 V 0 V F V H VLV V0 L V J V V0 V NTF UH.0MH.0U VM_NTF0 VM_NTF VM_NTF VM_NTF VM_NTF VM_NTF VM_NTF VM_NTF VM_NTF VM_NTF VM_NTF0 VM_NTF VM_NTF 0 VM_NTF 0 VM_NTF VM_NTF VM_NTF VM_NTF VM_NTF VM_NTF VM_NTF0 VM_NTF VM_NTF VM_NTF VM_NTF VM_NTF VM_NTF VM_NTF VM_NTF VM_NTF VM_NTF0 VM_NTF V_NTF P V_NTF0 N V_NTF M V_NTF L V_NTF 0 V_NTF R0 V_NTF P0 V_NTF N0 V_NTF M0 V_NTF L0 V_NTF V_NTF0 R V_NTF P V_NTF N V_NTF M V_NTF L V_NTF V_NTF R V_NTF P V_NTF N V_NTTF M V_NTF0 L V_NTF W V_NTF V V_NTF U V_NTF T V_NTF P V_NTF N V_NTF M V_NTF L V_NTF0 W V_NTF V V_NTF U V_NTF T V_NTF R V_NTF P V_NTF N V_NTF M V_NTF L V_NTF W V_NTF0 V V_NTF U V_NTF T V_NTF R V_NTF P V_NTF N V_NTF M V_NTF L V_NTF W V_NTF V V_NTF0 U V_NTF T V_NTF R V_NTF P V_NTF N V_NTF M V_NTF L V_NTF W V_NTF V V_NTF U V_NTF0 T V_NTF R V_NTF P V_NTF N V_NTF M V_NTF L V_NTF W V_NTF V V_NTF U V_NTF T V_NTF0 R V_NTF P V_NTF N V_NTF M V_NTF L V_NTF W V_NTF V V_NTF U V_NTF T V_NTF V_NTF V_NTF V_NTF V_NTF L V_NTF M V_NTF N V_NTF P V_NTF0 R V_NTF T V_NTF U V_NTF V V_NTF W V_NTF V_NTF V_NTF V_NTF L V_NTF M V_NTF0 N V_NTF P V_NTF R V_NTF T V_NTF U V_NTF V V_NTF W V_NTF V_NTF V_NTF V_NTF0 L V_NTF M V_NTF N V_NTF P V_NTF R V_NTF T V_NTF U V_NTF V V_NTF W V_NTF V_NTF0 V_NTF V_NTF R V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF0 0 V_NTF 0 V_NTF R V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF0 V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF0 VTT_NTF L VTT_NTF M VTT_NTF N VTT_NTF P VTT_NTF R VTT_NTF T VTT_NTF U VTT_NTF0 V VTT_NTF W VTT_NTF L VTT_NTF M VTT_NTF N VTT_NTF P VTT_NTF R VTT_NTF T VTT_NTF U VTT_NTF V VTT_NTF0 W 0U0VZ-P 0 UVZ-P UVZ-P UVZ-P UVZ-P

11 --, M [..0] M nd M 0, M [..0] M nd 0 M 0 M 0 /R 0 M R#, 0 M 0 /R 0 M R#, 0 M /W 0 M W#, 0 M /W 0 M W#, 00 M / M #, 00 M / M #, M M M /0 0 M_#0, M /0 0 M_#, M / M_#, M / M_#, M M M K0 M_K0, M K0 M_K, M K 0 M_K, M K 0 M_K, M 0 M 0 0 M 0/P K0 0 M_LK_R0 0 M 0/P K0 0 M_LK_R 0 M /K0 M_LK_R#0 0 M /K0 M_LK_R# M M K M_LK_R K M_LK_R /K M_LK_R# /K M_LK_R# M M[..0] M M0 M M[..0], M # M M0 / M0 0, M # M M / M0 0 M M M M M M, M #0 0 M M 0 M, M #0 0 M M 0 M, M # 0 M M M, M # 0 M M M M M M Q0 M 0 M M M Q0 M 0 M M M Q Q0 M M M M Q[..0] M Q Q0 M M M M Q Q M 0 M M M Q[..0] M Q Q M 0 M M M Q Q M M Q M RNJ--P-U Q -- M Q Q RN M_IH_ M Q Q M_IH_ M Q Q M_IH, M_IH_ M Q Q M_IH_ M_IH, M Q Q L M Q Q L M Q Q V_0 M Q Q M Q Q VP V_0 M Q Q VP M Q Q M Q Q M Q0 Q 0 M Q0 Q 0 V_0 M Q Q0 00 M Q Q0 00 M Q Q M Q Q 0 R M Q Q N#0 0 0 M Q Q N#0 0 M Q Q N# M Q Q N# -0-0 M Q Q N# M Q Q N# M Q Q N#0 0 M Q Q N#0 0 M Q Q N#/TT M Q Q N#/TT M Q Q M Q Q M Q Q M Q Q M Q0 Q V M Q0 Q V M Q Q0 V M Q Q0 V M Q Q V M Q Q V M Q Q V M Q Q V M Q Q V M Q Q V M Q Q V M Q Q V M Q Q V 0 M Q Q V 0 M Q Q V 0 M Q Q V 0 M Q Q V M Q Q V M Q Q V M Q Q V M Q0 Q V V_ M Q0 Q V M Q Q0 V V_ M Q Q0 V M Q Q M Q Q M Q Q V M Q Q V M Q Q V M Q Q V M Q Q V M Q Q V M Q Q V M Q Q V M Q Q V M Q Q V M Q Q V M Q Q V M Q Q V M Q Q V M Q0 Q V M Q0 Q V M Q Q0 V M Q Q0 V M Q Q V M Q Q V M Q Q V M Q Q V M Q Q V 0 M Q Q V M Q Q V 0 M Q Q V M Q Q V 0 M Q Q V 0 M Q Q V M Q Q V M Q Q V M Q Q V M Q Q V M Q Q V M Q0 Q V M Q0 Q V M Q Q0 V M Q Q0 V M Q Q V M Q Q V M Q Q V 0 M Q Q V M Q Q V 0 0 M Q Q V 0 M Q Q V M Q Q V M Q Q V M Q Q V M Q Q V M Q Q V M Q Q V M Q Q V M Q Q V M Q Q V M Q0 Q V 0 M Q0 Q V M Q Q0 V 0 M Q Q0 V M Q Q V M Q Q V M Q Q V M Q Q V Q V Q V M Q#0 V M Q#0 V M Q# /Q0 V M Q[..0] M Q# /Q0 V M Q# /Q V M Q#[..0] M Q# /Q V M Q# /Q V M Q# /Q V M Q# /Q V M Q# /Q V M Q# /Q V M Q# /Q V M Q# /Q V M Q# /Q V M Q# /Q V 0 M Q# /Q V 0 /Q V /Q V M Q0 V M Q0 V M Q Q0 V M Q#[..0] M Q Q0 V M Q Q V M Q[..0] M Q Q V M Q Q V 0 M Q Q V M Q Q V 0 M Q Q V M Q Q V M Q Q V M Q Q V M Q Q V M Q Q V M Q Q V Q V Q V V V, M_OT0 OT0 V <ore esign>, M_OT OT0 V, M_OT OT V, M_OT OT V V 0 V 0 R_VRF_ VRF V Wistron orporation R_VRF_ VRF V V V V V 0 0 Taipei Hsien, Taiwan, R.O.. 0 UVKX-P N N 0 0 UVKX-P N N 0 R-00P--P.00. R-00P--P.00. ONNTOR UVZ-P ONNTOR R ocket UVZ-P ize ocument Number R ev High.mm High.mm ustom (lviso) 0 nd source:.00. nd source:.00. ate: Tuesday, October, 00 heet of 0 NORML TP 0KRJ--P -- NORML TP

12 PRLLL TRMINTIONPut decap near power(0.v) and pull-up resistor R_VRF -0-0 ecoupling apacitor R RJ--P M M M M 0 M_K0, Put decap near power(0.v) and pull-up resistor R RJ--P M_OT, RN R_VRF M_#, M_OT, M [..0], RNJ--P RN0 M [..0], M M_K, M M #, RNJ--P RN RNJ--P UVZ-P UVZ-P UVZ-P UVZ-P UVZ-P UVZ-P UVZ-P UVZ-P UVZ-P UVZ-P 0 UVZ-P UVZ-P UVZ-P UVZ-P 0 UVZ-P 0 UVZ-P UVZ-P UVZ-P RN RNJ--P M M_OT, M_#, M R#, V_ Place these aps near M RN M M #, M 0 UVMX--P UVMX--P UVMX--P UVMX--P UVMX--P M RNJ--P RN RNJ--P M M M M_K, RN RNJ--P RN M M M #0, M W#, M #, M R#, M_#0, M_OT0, V_ 0 UVMX--P Place these aps near M UVMX--P UVMX--P UVMX--P 0 UVMX--P RNJ--P RN M M M 0 RNJ--P M #, RN0 RNJ--P RN RNJ--P M M M M #0, M W#, M #, M_#, M #, RN M_K, <ore esign> M M M RNJ--P RN RNJ--P M M M M 0 Wistron orporation Taipei Hsien, Taiwan, R.O.. R Termination Resistor (lviso) 0 ize ocument Number Rev ate: Tuesday, October, 00 heet of 0

13 -- L MH_LV_ON Pin Pin ymbol Pin 0 V U- U+ N N Inverter Pin Pin ymbol Vin Vin PWM LON N N Launch ymbol V_0 PWRTN# PRORM# UTTON# INTRNT# MIL# KOL MIL_L# T_L# PWRL# N N -0-0 MH_LV_ON 0 U0VZ-P LV Layout 0 mil V_0 V_0 I_LK I_T RIHTN FPK Layout 0 mil MH_TXLK- MH_TXLK+ MH_TXOUT- MH_TXOUT+ MH_TXOUT- MH_TXOUT+ MH_TXOUT0- MH_TXOUT0+ MH_TXOUT0- MH_TXOUT0+ MH_TXOUT- MH_TXOUT+ MH_TXOUT- MH_TXOUT+ MH_TXLK- MH_TXLK+ V_0 L/INVRTR/ ONN -- R KRJ--P L MH MH IPX-ON0--P 0.F0.00 ONNTOR U OUT LV_ON_ N ON/OFF# T0IU--TP UVZ-P UV0Z-P IN N IN UVZ-P 0U0VZ-P 000P0VJN-P TOP VIW L LV UVZ-P U0VZ-P VN HNNL O HNNL TOUT UVZ-P WLN_L# LT_L# UVZ-P U0VZ-P V_0 L ONN RIHTN FPK LK I UVZ-P VPT-P-U VPT-P-U L 0 MLX-ON--P-U ONNTOR 0.K0.00 T I P_L# NUM_L# I_L#,0 FRONT_PWRL# T_L# HR_L# _TFULL# V_0 Q FNN--P V_0 WLN_L# LT_L# -0-0 P_L# NUM_L# I_L# 0 0 UVZ-P Q FNN--P UVZ-P WLN_L# FRONT_PWRL# T_L# HR_L# _TFULL# LT_L# -0-0 V_0 L---U-P.00.0 L R0 00RJ--P L---P.00.J0 K L V_0 <ore esign> R00 0RJ--P RN00J--P RNKJ--P RN RN I_LK I_T L L ONN & L K UVZ-P V_ L---U-P.00.0 L L---U-P.00.0 L L---P.00.J0 L L---U-P.000.P0 V_0 Wistron orporation Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev ate: Friday, October, 00 heet of 0 (lviso) 0

14 RT ONNTOR MH_R MH_R Ferrite bead impedance: 0 Ohm Impedance L Ohm Impedance RT_R LM00NP MH_RN MH_RN L RT_ LM00NP MH_LU MH_LU L RT_ R 0RF--P -0-0 R 0RF--P R 0RF--P Hsync & Vsync level shift V_0 P0VN--P P0VN--P P0VN--P LM00NP P0VN-P P0VN-P P0VN-P MH_HN MH_HN RT_HN T MH_VN MH_VN RT_VN RT_HN UVZ-P U THTPW-P RT_VN P0VJN-P -0- _LK & T level shift 00P0VJN-P THTPW-P U P0VJN-P LK 00P0VJN-P 0P0VJN-P 0P0VJN-P Protection iode RT_R V_0 VPT-P-U V_0 V_RT_0 RN RNKJ--P V_0 -- V_0 RT -0-0 V_RT_0 H-0-P-U 0UVKX-P -0- VPT-P-U RT_ VPT-P-U RT_ RT_R MH_T MH_LK FNN--P Q LK T RT_ RT_ V_RT_0 0 T RT_HN RT_VN LK <ore esign> Wistron orporation Taipei Hsien, Taiwan, R.O.. FNN--P Q VIO---P-U ONNTOR RT onnector ize ocument Number Rev ustom (lviso) 0 Friday, October, 00 ate: heet of 0

15 R0 KRJ--P T LN_RTN PRLP# H_PRLP# H_PLP# 0KRJ--P PLP# LNRX[0] H_FRR_R FRR# F R LNRX[] RJ--P H_FRR# LNRX[] H_PWR, nd PUPWR/PO[] LNTX[0] -0-0 H_INN# -ON--P LNTX[] INN# FWH_INIT# TP 0.F0.00 LNTX[] INIT_V# H_INIT# RT ONNTOR R0 0R00-P INIT# F Z_ITLK 0 H_INTR Z_N_R Z_IT_LK INTR 0V_0, Z_N nd source: 0.F0.00 RJ-L-P R Z_N KRIN#_ 0 Z_RT#_R RIN#, Z_RT# 0 00P0VKX-P RJ-L-P R00 Z_RT# NMI F H_NMI Z_TIN0 F H_MI# R Z_IN[0] MI# -0-0 RF--P Z_TIN F0 Z_IN[] 0 H_TPLK# TP TP Z_IN[] TPLK# Z_TOUT_R H_THRMTRIP_R, Z_TOUT R0 PM_THRMTRIP-I#,, R RJ-L-P Z_O THRMTRIP# RJ--P T R MRJ--P UVZ-P 0UVKX-P -0- INTRUR# R 0MRJ-L-P R RJ--P LP_LRQ V_UX_ RT_UX_ X KRIN#_ H_PLP# K0T_ X-KHZ-PU RN RN0KJ--P U U0VZ-P LP_L[0..] T_ RT_X LP_L0 RT_X RTX L[0]/FWH[0] P LP_L P0VJN-P RTX L[]/FWH[] N LP_L -0-0 T--P R 0KRF-L-P RT_RT# L[]/FWH[] N LP_L RTRT# L[]/FWH[] N LP_LRQ#0 LP_LRQ 0V_0 TP TP TP TP LP_LFRM# K0T_ H_0M# H_PULP#, I_P0 0 I_P 0 I_P 0 I_P# 0 I_P# V_0-0-0 Layout Note: R needs to placed within " of IH, R must be placed within " of R w/o stub. T[]RXN [0] I_P0 0 T[]RXP [] F I_P 0 F T[]TXN [] F I_P 0-0- T[]TXP [] I_P 0 I_P 0 RT_UX_ [] T_LKN [] I_P 0 T_LKP [] I_P 0 [] I_P 0 I_P 0 R TRI# [] -0-0 F I_P 0 00KRJ--P TRI [] F [0] I_P0 0 [] I_P 0 P.H. for internal VU_ [] I_P 0 I_P 0 INTVRMN 0 I_PIOR F IOR [] 0 INT_IRQ IIRQ [] I_P 0 0 I_PK# K# [] I_P 0 0 I_PIOW# IOW# 0 I_PIOR# I_PRQ 0 R0 IOR# RQ 0RJ-P P0VJN-P INTRUR# INTVRMN R0 RT INTRUR# INTVRMN HLK _OUT F _IN F LN_LK TL# LN T[0]RXN T[0]RXP T[0]TXN F T[0]TXP LP PU LRQ[0]# N LRQ[]#/PI[] P T -/ZLI I LFRM#/FWH[] P 0T F 0M# F PULP# [0] [] [] # # 0KRJ--P R R RJ--P V_0 <ore esign> Wistron orporation Taipei Hsien, Taiwan, R.O.. IH-M ( of ) ize ocument Number Rev (lviso) 0 ate: Thursday, October, 00 heet of 0

16 U V_0,, PI_[..0] RN PM_RI# T PI_0 PI_RQ#0 PRn[] H PI_ RQ[0]# L PI_RQ#0 RN0KJ--P RI# [0] PI_NT#0 T0_R0 T0_R0 PRp[] H PI_ [] PI NT[0]# PI_NT#0 F PI_RQ# T0_R T0_R T[0]P/PI[] PTn[] PI_ [] RQ[]# PI_RQ# T0_R T0_R T[]P/PI[] PTp[] F PI_ [] NT[]# PI_NT# F PI_RQ# T0_R T0_R T[]P/PI[0] F PI_ [] RQ[]# M PI_RQ# T[]P/PI[] PRn[] K PI_ [] NT[]# F PI_NT# PI_RQ# PRp[] K F PI_ [] RQ[]# M_LK PTn[] J PI_ NT[]# TP TP MLK [] M_T W OOT_LOK# M_LINK_LRT# PTp[] J PI_ RQ[]#/PI[0] F TP TP MT [] TP TP MLINK0 LINKLRT# PI_0 [] NT[]#/PO[] W PI_RQ# MLINK MLINK[0] PRn[] M PI_ [0] RQ[]#/PI[] U PI_NT# MH_N# MLINK[] PRp[] M PI_ [] NT[]#/PO[] F PI_RQ# MH_N# PTn[] L PI_ [] RQ[]#/PI[0] PI_NT# Z_PKR F PKR PTp[] L H PI_ [] NT[]#/PO[] PI_ [] PM_U_TT# W U_TT#/LPP# PRn[] P J PI_/#0,, PI_ [] /[0]# J RT# PRp[] P K PI_/#,, PI_ [] /[]# H U _RT# PTn[] N K PI_/#,, PI_ [] /[]# -0-0 PTp[] N PI_/#,, PI_ [] /[]# PM_MU# MU# L MI_RXN0 PI_0 [] MI[0]RXN T PI_IR#,, MI_RXP0 PI_ [0] IR# I#_ Layout Note: PI_PR,, PI_ PR PI[] MI[0]RXP T H [] MI# R MI_TXN0 H PI coupling caps MI_TXP0 PI_ PIRT# R R PI[] MI[0]TXN R [] 0RJ--P PIRT#,, M_LRT# MI[0]TXP R H need to be within 0 mils of the driver. PI_VL#,, PI_ [] VL# W MLRT#/PI[] PI_PRR#,, MI_RXN PI_ [] PRR# M PI_LOK# IH_PI MI_RXP PI_ PLOK# TP0 TP MI[]RXN V [] M PI_RR#,, PI_ RR# P0VJN-P PI[] MI[]RXP V [] WI# R PI[] MI[]TXN U MI_TXN K PI_TOP#,, MI_TXP PI_ [] TOP# J MI[]TXP U K PI_TR#,, PI_ [] TR# J PM_TPPI# TP_PI# MI_RXN PI_0 [] L TP TP IH_PO MI[]RXN MI_RXP PI_ [0] K PLT_RT#_ PLTRT# R R RJ--P PO[] MI[]RXP [] PLT_RT#,, MI_TXN PILK MI[]TXN W LK_IHPI, PM_TPPU# TP_PU# MI[]TXP W MI_TXP,, PI_FRM# J FRM# PM# P IH_PM#, Int. PH TP TP IH_PO 0 MI_RXN Interrupt I/F K_LP_WK PO[] MI[]RXN V_0 MI_RXP INT_PIRQ# INT_PIRQ# K_LP_WK PO[] MI[]RXP N INT_PIRQ# MI_TXN INT_PIRQ# INT_PIRQ# PIRQ[]# PIRQ[]#/PI[] INT_PIRQF# MI[]TXN L Place within 00 mils of IH INT_PIRQF# MI_TXP INT_PIRQ# PIRQ[]# PIRQ[F]#/PI[] INT_PIRQ# P_VR V PIO[] MI[]TXP M INT_PIRQ# INT_PIRQ# PIRQ[]# PIRQ[]#/PI[] L INT_PIRQH# PIRQ[]# PIRQ[H]#/PI[] M KRJ--P R P MI_LKN LK_PI_IH# R PIO[] P_VR0 R LK_PI_IH RRV HK_PW# MI_LKP RF-L-P PIO[] HK_PW# T -0- TP TP RV[] TP TP PIO[] RV[],,, PM_LKRUN# F -0-0 TP TP IH_PIO RV[] F TP TP TP TP LKRUN# MI_ZOMP F RV[] F0 TP0 TP F IH_PIO MI_IROMP_R RV[] RV[] TP TP TP0 TP PIO[] TP TP RV[] TP[] U TP TP PIO[] MI_IROMP F TP TP IH_WK# V_ RV[] U WK# O[]#/PI[] O[]#/PI[0] RN U_O#,, INT_RIRQ 0 RIRQ O[]#/PI[] U_O# -0-0 U_O# IH Pullups V_ V_0 THRM# O[]#/PI[] U_O# THRM# 0 THRM# RN U_O#0 U_O#0 U_O#0 IH_WK# PI_RQ# O[0]# U_O# R0 KRJ--P PI_RQ#, VT_PWR F VRMPWR O[]# RN V_0 INT_PIRQ# 0 PM_TLOW#_R OOT_LOK# O[]# RN0KJ--P PI_RQ# PI_FRM# LK_IH 0 O[]# -0- R KRJ--P LK PI_RR# PI_TOP# UPN0 INT_PIRQF# PI_TR# MI# LK_IH LK UP[0]N V_0 UPP0 PI_PRR# R RN0KJ--P 00KRJ--P I#_ UP[0]P UPN V_0 RF WI# R0 00KRJ--P PM_U_LK V ULK UP[]N 0 UPP TP TP Z_PKR RN0KJ-L-P PM_LP_#_IH UP[]P 0 R 00KRJ--P T UPN UP[]N TP TP R KRJ--P LP_# RN UPP V_0 PI_LOK#, PM_LP_# T PM_LP_# UP[]P TP TP LP_# T UPN TP TP0 INT_PIRQ# PI_RQ# TP TP LP_# UP[]N UPP RF PI_VL# INT_PIRQ# Need to check what power we will use UP[]P TP TP UPN PI_IR# PM_LKRUN# PWROK UP[]N TP TP KRJ--P PWROK PI_NT# UPP PI_RQ# PM_PRLPVR_R UP[]P R UPN V_0 PM_PRLPVR 0 R0 PRLPVR UP[]N UPP RN0KJ-L-P -0-0 PM_TLOW#_R UP[]P TP TP 00RJ--P V UPN UPN RF TLOW# UP[]N TP TP KRJ--P RN UPP PI_NT# V_0 UPP PI_RQ#0 PM_PWRTN# UP[]P R 0 UPN INT_PIRQ# INT_RIRQ PM_PWRTN# U PWRTN# UP[]N UPN UPP UPP INT_PIRQ# THRM# PM_LP_#_IH LN_RT# UP[]P 00KRJ--P R PWROK INT_PIRQH# MH_N# PM_LP_#,,,, V R LN_RT# 0R00-P INT_PIRQ# URI# U_RI_PN V_0, RMRT#_K RMRT# URI R0 R0 RN0KJ-L-P PM_PRLPVR_R 00KRJ--P RF-L-P RN R R Place within 00 mils of IH M_LINK_LRT# 0 V_ R0 00KRJ--P 0KRJ--P -0-0 MLINK0 00KRJ--P M_LRT# HK_PW# -0-0 MLINK PM_RI# V_ RN0KJ-L-P RT# PIO U PI-XPR irect Media Interface POWR MT LOK U IH-M trapping Options RF FUNTION Layout Note: PI coupling caps need to be within 0 mils of the driver. FULT OPTIONL OVRRI RF No Reboot NO_TUFF TUFF RF wap Override NO_TUFF TUFF <ore esign> RF oot IO NO_TUFF TUFF Wistron orporation Taipei Hsien, Taiwan, R.O.. IH-M ( of ) ize ocument Number Rev (lviso) 0 ate: Monday, October, 00 heet of 0

17 Layout Note: Place above caps within 00 mils of IH near F, P, V_0 0 V V F V V U T V V U T0UVM-P V V U V V U V V U V V T F V V T F V V P F V V P V V M V V M Layout Note: V V L I decoupling V V L H V_0 V V L H V V L J LL NO_TUFF aps do V V L J not have layout V V K Place within 00 requirements but if V_0 V V 0 K mils of IH pin V_0 layout allows then place V V L, next to IH V L V_ 0 V M V_ UVZ-P V M V V_ *Within a given well, VRF needs to be up before the N UVZ-P V_ V corresponding.v rail N V V_ N V V_ N V V_ N V V_ P Layout Note: V_0 V_0 V_0 Layout Note: V V_ P istribute in PI section PI decoupling V V_ P near pin - near -H V P V V_ P R V V_ M RV-0--P R V_ L 0RJ--P V T UVZ-P V_ L R0 V T V V_ J U V_INT_ VRF_0 V V_ H U V V_ H V V V_ V V_ 0 V W V_ UVZ-P U0VZ-P V W UVZ-P UVZ-P V_0 V V VU_ U V VU_ R V_INT_ V_ V_ V Place within 00 V VU_ V_0 mils of IH V Layout Note: near pin V 0 V Place near IH RV-0--P V F0 UVZ-P 0RJ--P V V R V V UVZ-P V VRF_ V V F Place both V_0 V V within 00 mils V V 0 of IH near Place within 00 V U0VZ-P mils of IH V UVZ-P V near pin V V -0- V_0 V V V_PLL_IH_0 V V_PI_I V_0 V R V V R V V_ -0-0R00-P V_IH_0 V_ P 0RJ--P V F Place within 00 V UVZ-P Layout Note: V_ mils of IH 0U0VZ-P 0UVKX-P V Place near Place within 00 V_INT_ VRF mils of IH V_0 VRF U VMIPLL VRF_0 Place within 00 V_ VRF_ V_ 0UVKX-P mils of IH V_0 VRF_U F VOUT near, V_IH_0 VTPLL VIN 0 0 V_ VUPLL N UVZ-P VU_ Place within 00 R 0R00-P VLN_/VU_ F mils of IH VRT PL0--P VLN_/VU_ UVZ-P VLN_/VU_ V_INT_ UVZ-P Place within 00 VLN_/VU_ V_0 mils of IH VLN_/VU_ pin VU_ VLN_/VU_ 0 U Place within 00 RT_UX_ VU_ V mils of IH Place within 00 VU_ V_PU_IO V pin 0 Layout Note: mils of IH VU_ V_PU_IO W Place near pin 0 UVZ-P VU_ V_PU_IO 0V_0 V_ VU_ 0 VU_ UVZ-P VU_ VU_ UVZ-P VU_ VU_ F VU_ VU_ F UVZ-P Layout Note: <ore esign> F V_0 VU_ VU_ Place near Place within 00 VU_ VU_ mils of IH VU_ VU_ pin V_ UVZ-P UVZ-P 0U0VZ-P UVZ-P V_ UVZ-P UVZ-P UVZ-P UVZ-P Place within 00 mils of IH pin V PI T U OR I PI U OR U PI/I RF UVZ-P UVZ-P UVZ-P UVZ-P UVZ-P UVZ-P UVZ-P UVZ-P UVZ-P V_0 Place within 00 mils of IH pin Layout Note: Place near pin U0VZ-P Wistron orporation Taipei Hsien, Taiwan, R.O.. IH-M ( of ) ize ocument Number Rev ate: Monday, October, 00 heet of 0 UVMX--P -0-0 (lviso) 0

18 U V V F V_ V V K suspend clock output F V V F V V -0-0 F U0 V V W,,,, PM_LP_# O V V V R W V V PM_U_LK W KHZ N V V _K W V V W 0RJ--P V V V V V NZPX-P V V V 0 V V V V R V V U 00KRJ--P V V U V V 0 U V V U V V U V V T V V 0 T V V -0-0 T V V T V V T V V T V V -0-0 T V V T V V T V V T V V -0- R V V R V V R V_0 V V R V V 0 R RJ--P V V U R V V R R V V R,, PLT_RT# R0 V V RTRV#_ 0 R V V F R 0R00-P V V F R V V F P 00P0VJN-P THTPW-P R0 V V F P 0KRJ--P V V F0 P V V -0-0 F P V V P V V P V V N V V PIRT# V to V level shift for H & ROM N V V N V V N V V N V V 0 N V V N V V N V V N V V M V V M V V 0 M V V M V V M V V M V V M V V M V V M V V L V V L V V -- 0 L V V L V_ V_0 V V L V V K V V K V V 0 K V V K V V K RN V V J V V RN0KJ--P J V V J V V J V V H V V H V V H V V V_0 V V V V V V V V V V MU 0 V M_LK M_IH, Q <ore esign> N00PT-U M_T Q & Q connect MLINK and MU in ) for Mus.0 compliance Q N00PT-U M_IH, Wistron orporation Taipei Hsien, Taiwan, R.O.. IH-M ( of ) ize ocument Number Rev (lviso) 0 ate: Tuesday, October, 00 heet of 0

19 *Layout* mil FN_V UVZ-P U0VZ-P T--P -0- V_0-0-0 nd FN V_0-0-0 R 0KRJ--P THRM# V_0-0-0 etting T as 00 egree V_R =(((egree-)*0.0)+0.)*v -0-0 PWROK 00P0VKX-P *Layout* 0 mil U0VZ-P -0- R 0KRJ--P UVZ-P V_0-0-0 THRM# T_HW_HUT# V_R V 0 _RT# U V 0 V XP XP XP LRT# THRM# THRM_T RT# V FUF-P FN F LK L N# N N N N 0 N XP:0 egree XP:H/W etting XP: egree _XN _XN TOUT _K M_ M_ H_THRM _XP _XP H_THRM P-LO Place near chip as close as possible 00P0VKX-P FN_V *Layout* mil 0 00P0VKX-P 0P0VKX-P nd source: 0.F0.00 ystem 接第二組,V 接第三組 0 00P0VKX-P -ON--P 0.F0.00 ONNTOR 0P0VKX-P Q ystem ensor H_THRM H_THRM R MRJ--P T_HW_HUT# V_UX_ LOW_OFF Output type: Open-rain RT# HTH R KRF-P RMRT# INTRUR# R 0KRJ--P T--P R 0KRF-P P0VKX-P R 0KRJ--P R 00RF-L-P UVZ-P R KRF-L-P R KRF-L-P KRJ--P R UVZ-P 0 00P0VJN-P P-LO Q PM0--P PM0--P W--P UVZ-P (dummy, K already delay) U V HTH N RT#/RT LTH 0LTF-P R 0RJ-P UVZ-P <ore esign>, H_PWR -0-0 R KRJ--P UVZ-P -0- Q PMT-P Wistron orporation Taipei Hsien, Taiwan, R.O.. Thermal/Fan ontrollor (lviso) 0 ize ocument Number Rev ustom PM_THRMTRIP-I#,, ate: Thursday, October, 00 heet of 0

20 H onnector -ROM onnector V_0 V_0 V_0 heck UVZ-P UVZ-P I_P I_P I_P I_P I_P I_P0 I_P I_P I_P I_P I_P I_P I_P I_P I_P I_P0 I_P# I_P# I_P I_P I_P0 0U0VZ-P -0- K I_P I_P I_P I_P I_P I_P0 I_P I_P I_P I_P I_P I_P I_P I_P I_P I_P0 I_P# I_P# I_P I_P I_P0 MLLPT-P T00UVM- T -0-0 H +V_MOTOR +V_LOI # 0# 0-0- I_PIOR I_PK# INT_IRQ K 0 L PI# RT# P# INTRQ IOR IOR# IOW# MRQ MK# RRV# RRV# NP NP NP NP N 0 N 0 N N N N N N N N HL PI RTRV#_ INT_IRQ I_PIOR I_PIOR# I_PIOW# I_PRQ I_PK# RN RNKJ--P I_L# -0-0 R0 0RJ--P RTRV#_ I_L# INT_IRQ I_PIOR I_PIOR# I_PIOW# I_PRQ I_PK# -0-0 R 0KRJ--P V_0 V_0 0U0VZ-P -0-0 R 0KRJ--P UVZ-P I_P I_P I_P0 I_P I_P I_P I_P I_P I_PRQ I_PIOR# I_PK# PI I_P I_P# 0 UVZ-P O T-ONN0-R ONNTOR PIN,0 ON'T U RTRV#_ I_P I_P I_P I_P I_P I_P I_P I_P0 I_PIOW# I_PIOR INT_IRQ I_P I_P0 I_P# I_L# L R 0RJ-P R 0KRJ--P -0- V_0 N-ON--P ONNTOR 0.F0.0 <ore esign> Wistron orporation Taipei Hsien, Taiwan, R.O.. H and ROM ize ocument Number Rev ate: Monday, October, 00 heet 0 of 0 (lviso) 0

21 T 00U0VM-P 00 mil V_U_0 UVZ-P 00 mil V_U0_0 000P0VJN-P V_ U_PWR_N# U V_U0_0 N O# IN OUT N/N# OUT N/N# O# PUF-P V_U_0 RN0J--P RN UVZ-P -0- UVZ-P -0- U_O#0 U_O# U PORT -0-0 UPN UPP UPN UPP V_U0_0 V_U0_0 ONNTOR.0.J KT-U-0-P U ONNTOR.0.J KT-U-0-P T 00U0VM-P T0 00U0VM-P LUTOOTH MOUL V_T_0 U V_T_0 OUT IN N N# ON/OFF# UVZ-P UVZ-P T0IV-T-P.00.F 000P0VJN-P V_0 LUTOOTH_N -- nd LU UPN0 UPP0 V_U_0 ONNTOR.0.J KT-U-0-P -- U U UPN UPP V_T_0 M. ONNTOR T-ON--P 0.F00.00 ONNTOR st source: 0.0.0, Z_TOUT, Z_N Z_TIN, Z_RT# 0R00-P R Z_TOUT MH M nd Z_N R TIN_ 0 0R00-P Z_RT# MH P0VJN-P R 0 U0VZ-P 0RJ--P MP-ONN-P ONNTOR 0.F0.0 nd source: 0.F00.0 TP TP U0VZ-P TP TP V_ R 00KRJ--P UMM- Z_TLK_M -0-0 <ore esign> U / M / LUTOOTH Wistron orporation Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev ate: Friday, October, 00 heet of 0 (lviso) 0

22 TP0 TN0 TP TN LO TO LN HIP,, PI_/#[..0] X P0VJN-P XTL-MHZ-0P 0U0VKX-P 0U0VKX-P LN_X P0VJN-P V_LN_ U LN_K LV LN_I LN_O V_LN_ R0 V_LN_ V_LN_ LN KRF-P PI_0 PI_ TP0 PI_ V_LN_ TP0 TN0 MI0+ PI 0 TN0 LVL MI0- VPT 0 VL N 00 LV TP V V TP PI_ TRL TN MI+ PI PT--P TN PI_ LVL MI- PI Q PI_ TRL VL PI PI_ TRL PI V V 0 PI_ VH PI PI_/#0 LV V_0 0 LV H+ 0 T--P H- VPT PI_ V PI PI_ MI+ PI LVL MI- MN PI_0 R0 VL PI0 PI_ KRJ--P V PI PI_ MI+ PI LVL MI- V 0 PI_ VL PI PI_ VPT PI IOLT# N VPT R0 KRF-P LV IOLT# N 0 PI_ V PI INT_PIRQ# LV INT# V PI_/# V_LN_ V,, PIRT# PI_PR PIRT# PR PI_PR,, PI_RR# V_LN_ PLK_LN PI_RR#,, PI_NT# PI_NT# PILK RR# PI_RQ# PI_RQ# NT# N 0 RQ# N, IH_PM# LV PM# N PI_ V V PI_PRR# PI_PRR#,, PI_0 PI PRR# 0 R0 PI_TOP# PI0 TOP# 0R00-P PI_VL# PI_TOP#,, PI_VL#,, PI_ N VL# PI_TR# LVL PI_TR#,, PI_ PI TR# PI VPT PM_LKRUN# VPT LKRUN# PM_LKRUN#,,, PI_ LV <ore esign> PI_ PI_IR# PI_IR#,, PI_FRM# V_LN_ PI_FRM#,, PI_ PI_/# Wistron orporation PI_ PI_ -0-0 PI_/# PI_ Taipei Hsien, Taiwan, R.O.. LV PI_ R LN_IL PI_ LN_IL PI_ V_LN_ PI_ PI_ V_ V_LN_ LV RTL00L 00RF-L-P-U PI_ PI_0 P-LO-PWR ize ocument Number Rev U LN_X LN_X RT RTL00L-U V RT V TRL MI0X RN RNF-P V V XTL XTL MIX RN RNF-P VH 0 VPT N L0 V -- L L L N PI PI V PI PI V IL PI N PI PI VPT N PI0 V PI V PI PI PI FRM# N IR# V K V 0 I 0 O 0 V 0 0 LNWK 0 T_L# LV RTL_L# 0 0 PI0 PI T_L# RTL_L# ILN: RTL0L 0/00 LN:RTL00,, PI_[..0] V_LN_ V_LN_ PROM L OPTION U '0' (FIN IN P) => L0 : T => L : LINK (OTH 0/00 N I HIP) 0U0VZ-P UVZ-P LN_X -0- LN LN_K V R0 0KRJ--P LN_I K 0 R0 KR-P LN_O I OR O N UVZ-P UVZ-P UVZ-P UVZ-P U0VZ-P T-0U-P UVZ-P (lviso) 0 ate: Tuesday, October, 00 heet of 0 UVZ-P

23 0/00M Lan Transformer U nd TP0 TN0 T+ T- TX+ TX- 0 TP_RJ- TN_RJ- UVZ-P XRF_R XRF_T UVZ-P RJ_ RJ_ RN RNJ--P T T T T R+ R- RX+ RX- RP_RJ- RN_RJ- TP TN LN_TRMINL KPKVKX-LP 0U0VKX-P -0-.route on bottom as differential pairs..tx+/tx- are pairs. Rx+/Rx- are pairs..no vias, No 0 degree bends..pairs must be equal lengths..mil trace width,mil separation..mil between pairs and any other trace..must not cross ground moat,except RJ- moat. LN R0 V_ ONN_PWR_ 0RJ--P NP T_L# T_L# TP_RJ- RJ_ MW nd TIP_M RIN_M -ON-P-U 0.F0.00 ONNTOR nd source: L 0R00-P L 0R00-P -0-0 TIP RIN V_ RTL_L# LN onnector :LLOW :ORN :RN TN_RJ- RP_RJ- RJ_ RN_RJ- RJ_ R ONN_PWR 0RJ--P RIN TIP RTL_L# RJ_ RJ_ RJ_ RJ_ RJ_ RJ_ RJ_ RJ_ RJ_ NP 0 RJ-0-P connector.0.j0-0-0 <ore esign> Wistron orporation Taipei Hsien, Taiwan, R.O.. LN ONN ize ocument Number Rev (lviso) 0 ate: aturday, October, 00 heet of 0

24 V_0 R 0 KRJ--P V_0 000P0VJN-P UVZ-P UVZ-P RN0 _MFUN 0_RT# _MFUN INT_RIRQ _MFUN V_0 V_0 UVZ-P RN0KJ--P V_KT_0 V_0 V_0-0-0 _[0..] _[0..] 000P0VJN-P UVZ-P UVZ-P 000P0VJN-P UVZ-P RNKJ-L-P U0 RN,, PI_[..0] PI R# PI_0 R#/# _R# _ PI_ 0 / _RT PI_ / _O# PI_ /FRM# _# PI_ /TR# 0 _# PI_ /VL# 0 _ 0 _0 PI_ 0/TOP# 0 _0 _ PI_ /LOK# 0 _ -0-0 _ PI_ /RFU 00 PI_ / LKXX R RJ--P PI_0 /LK# 0 PI_ 0 /IR# 0 PI_ /PRR# 0 PI_ /PR 0 PI_ /# _ PI_ / _0 _0 PI_ 0/ _ PI_ / _ 0 _ PI_ /# PI_ / PI_0 /0 PI_ 0 / 0 PI_ / _ PI_ / PI_ / PI_ / _0 PI_ 0/ _0 PI_ / PI_ /RFU PI_ / PI_0 / 0 _ 0 / 0,, PI_/#[..0] _0 PI_/# 0/ PI_/# _# /0 PI_/# _# / 0 PI_/#0 _# / 0# /,, PI_FRM# FRM# / _ -0-0 V_KT_0,, PI_IR# IR# / _,, PI_TR# TR# /0 _,, PI_TOP# _ PI_ R_IL TOP# /RFU _ R IL / _ RF-L-P-U _0,, PI_VL# _0 R VL# 0/ _O# 0KRJ--P,, PI_PRR# PRR# O#/ _O#,, PI_RR# RR# W#/NT# 0 _W# _IOR#,, PI_PR PR IOR#/ _IOR# PLK_PM _IOWR# PI_LK IOW#/ _IOWR#,, PIRT# 0 RT# WP/IOI/LKRUN# _WP RI_OUT#/PM# INPK#/RQ# _INPK# R TP PI_NT#0 NT# R_IRQ#/INT# _R 0RJ--P PI_RQ#0 RQ# WIT#/RR# _WIT# /# _# /# _# _# /0 _# _# #/0# _# RT/RT# _RT P0VJN-P V/PKR/L/UIO _V# V/TH/RI/TH _V# V/V _V# V/V _V# LK_PM 0P0VJN-P _PKR R V# KR-P V0# INT_PIRQ# VPP INT_PIRQ# -0-0 _MFUN R VPP0 <ore esign> KRJ--P V_0 INT_RIRQ,, R 0KRJ--P _MFUN _MFUN PI_V PI_V 0 PI_V PI_V N N N N N N N N 0 U_UPN RT# V#/MLK/LK V0#/MT/T VPP VPP0/LTH UPN OMF OMF OMF OMF OMF OMF OMF0 PKR_OUT# 0 0 OR_V OR_V OR_V OR_V 0 OR_V OR_V UX_V OKT_V 0 OKT_V U Reduce start up noise PM_LKRUN#,,, ardus_n 0 Wistron orporation Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev (lviso) 0 ate: Tuesday, November 0, 00 heet of 0

25 PMI ocket V_KT_0 _[0..] _[0..] _IOR# _IOWR# _O# V_0 _W# V_0 _R# # _R _# WP _RT _ V_0 WIT# INPK# U0VZ-P UVZ-P KRJ--P _ R # _ U0 _# -0-0 _ 0 _# _V# UVZ-P U0VZ-P _HN# V#.V HN# _0.V _# V V V_KT_0 V_KT_0 _V# _O# V V _V# _V# V V TP TP _ 0 _IOR# V0# V0# VPP 0 VPP_KT_0 _ V# V# _IOWR# O# VPP0 _ VPP0 VPP _ VPP N TPIR-P _W# 000P0VJN-P _0 P _R _ 0 VPP_KT_0 _ RU-KT-P 0 UVZ-P _.H00.0 _ ONNTOR _V# _RT WIT# INPK# 0 R# Place close to pin. V# _0 UMM- _V# _0 0 _0 _WP lock termination _# _# 0U0VZ-P MHz clock for -bit ardbus card I/F ardbus I/F Power switch K R0 UMM-R UVZ-P PH 0 NP NP RUP--P.00. ONNTOR 0UVKX-P <ore esign> Wistron orporation Taipei Hsien, Taiwan, R.O.. PM ize ocument Number Rev (lviso) 0 ate: Tuesday, October, 00 heet of 0

26 _PKR Z_PKR U0VZ-P U0VZ-P _PKR Z_PKR K_P RN0 L UIO O UIO_P UVZ-P UIP_P_P RNKJ-L-P K_P R KRJ-P 00P0VKX-P U0VZ-P, Z_RT# 0 U0VZ-P R 0RJ--P RT# N N N N PHON P-P LF-OUT N-OUT MONO-OUT-R -N -R 0 -L MI MI U L-U-P MI MI_IN U0VZ-P MI_IN F- 0PF 0PPM V_0_U FLT 0 00P0VKX-P U -0-0 FLT 000P0VJN-P V_0 VR U0VZ-P _TLK V_0_U Z_RT# V N R RJ--P L_VRF Z_ITLK L_VRF VRFOUT NZ0MX-NL-P R0 VRFOUT RJ--P Z_TLK_M UVZ-P UVZ-P U0VZ-P R 0 UVZ-P _TLK U0VZ-P UVZ-P 0R00-P V_0, Z_N LK_udio POWR NRT V_TPIN _TLK 0R00-P R O_XTLL LININ_R LIN_IN_R XTLL LIN-R LIN_IN_R -0-0 LININ_L LIN_IN_L LIN-L LIN_IN_L 0R00-P J0/PIO0, Z_TOUT R U0VZ-P PON Z_TIN0 _IN OUT URR-OUT-R R RJ--P IN URR-OUT-L 0 U0VZ-P U HN# T N IN UVZ-P OUT -0TUF-P U0VZ-P UVZ-P -0- R 0R00-P P0VJN-P V_0 *Layout* 0 mil R KRF-P R 0KRF-L-P 0 N ITLK UVZ-P PIFI/P PIFO XTL-OUT XTL-IN V V -0-0 V V N#0 N# 0 FRONT-MI VRFOUT VRF U0VZ-P VR VR V_0 FRONT-OUT-R FRONT-OUT-L FILT FILT 0 J/PIO J <ore esign> -0-0 UX-R UX-L OUNR OUNL U HN# T N IN OUT -0TUF-P V_0 U0VZ-P R0 0R-0-U-P 0 U0VZ-P P0VJN-P V_0_U UVZ-P 000P0VJN-P P0VJN-P OUNR OUNL Wistron orporation Taipei Hsien, Taiwan, R.O.. ' O - L ize ocument Number Rev ate: Tuesday, November 0, 00 heet of 0 (lviso) 0

27 -0- V_0 I/P signal level need +V level R 0R00-P OP+V UIO OP MPLIFIR V_0_U 0U0VZ-P UVZ-P _LOUT_IN UVZ-P T--P TP TP U VOL 0 LV RV MUT HUTOWN N/H N/H N/H N/H 0 IN#/IN N N MP_HUTOWN UVZ-P -0-0 K_MUT UVZ-P U0VZ-P 0KRJ--P 0KRJ--P U0VZ-P U0VZ-P 0KRJ--P R R R OUN_L OUN_L_OP OUN_R_OP OUN_R OUNL OUN_L HP_L OUNL LIN RIN OUNR UVZ-P INL N OUN_L_OP PKR_L+ LIN RIN PKR_R+ OUN_R_OP OUNR OUN_R HP_R INR P PKR_L- LOUT+ ROUT+ R PKR_R- PKR_L+ HP_L LOUT- ROUT- R 0KRJ--P HNR# OUTL 0KRJ--P R PKR_R+ R LP U0VZ-P 0KRJ--P HNL# OUTR 0KRJ--P N# N# RP 0 _LOUT_IN U0VZ-P N# U0VZ-P 0QU-P 0P0VKX-P HP_R R 0KRJ--P QU-P Q K_MUT HTU-P P0VKX-P MUT_ UVZ-P R 00KRJ--P UVZ-P R IN R OUT N U0VZ-P R0 0KRJ--P V PV V PV 0 N# N# N N PN U -0-0 LIN OUT XT\Internal MI IN 0 UVZ-P P0VKX-P _LOUT_IN=High after PLU-IN V_0_U 0.F00.00 R PHON-JK-P-U T-ON--P KRJ--P NP Internal peaker MI -0-0 NP VRFOUT NP 00KRJ--P PKR_L- NP R PKR_L+ PKR_R R 00 _LOUT_IN KRJ--P U0VZ-P PKR_R+ PKR_R+ PKR_L+ MI_IN 0 INT_MI INT_MI XT_MI_IN_ R0 00R-P LOUT ONNTOR PKR 0 PHON-JK-P R00P0V--P 00P0VKX-P.0.0 R RN RNKJ--P ONNTOR nd 0P0VKX-P 0P0VKX-P st source: LIN IN RNKJ--P NP NP U_LIN_R LIN_IN_R <ore esign> U_LIN_L LIN_IN_L RN Wistron orporation 0 Taipei Hsien, Taiwan, R.O.. RN RN0KJ--P LIN ONNTOR udio MP and Jack.0.0 ize ocument Number Rev 00P0VJN-P 00P0VJN-P PHON-JK-P-U (lviso) 0 ate: Monday, October, 00 heet of 0

28 V_0 0,, PI_[..0] UVZ-P UVZ-P UVZ-P MINI V_0 WIRL_N V_0 TP TP 0_TIV INT_PIRQF# PLK_MINI PIRT#,, V_0 PI_RQ# 0 PI_NT# PI_ PM#_MINI TP TP 0 PI_ T_OX P0VJN-P PI_0 TP TP 0_TIV TP0 TP,, PI_/#,, PI_/#,, PI_IR#,,, PM_LKRUN#,, PI_RR#,, PI_PRR#,, PI_/# T_OX PI_ PI_ PI_/# PI_ PI_ PI_ PI_ PI_/# PI_/# PI_ PI_ PI_0 PI_ PI_ PI_ MO_IL PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ R 00RJ--P PI_ -- PI_ PI_/#0 PI_/#0,, PI_ PI_ PI_ PI_ PI_ PI_ PI_0 V_0 PI_ PIN - : LN RRV V_0 INT_PIRQF# -0-0 PI_PR,, PI_FRM#,, PI_TR#,, PI_TOP#,, PI_VL#,, INT_RIRQ,, WLN_TT_L WIRL_N -0-0 R 00KRJ--P Q HTU-P R IN R N00PT-U Q N00PT-U Q0 OUT N WLN_L# PILT--P ONNTOR.00.0 <ore esign> Wistron orporation Taipei Hsien, Taiwan, R.O.. MINI-PI ize ocument Number Rev (lviso) 0 ate: Tuesday, October, 00 heet of 0

29 -0- V_UX_ V_0 V_UX_ 0 L0 V_K_UX_ 0R00-P UVZ-P UVZ-P UVZ-P LP_L[0..] LP_L0 LP_L L0 PIO MTRIXI# LP_L L K Matrix PIO MTRIXI# LP_L L PIO PR_H 0 L LT_TN# 0 LP PIO PIO H_ON# LP_LFRM# LFRM# PIO 0 _OFF PLK_K LLK PIO 0,, INT_RIRQ TX PIO 0 TP RIRQ V_ PIO 0 # KIO_R# PIO0 0 T_IN# KIO_R# 0 KIO_W# R# PIO T_L# K NL# KIO_W# -0-0 KIO_# WR# PIO KIO_# MM# PIO INTRNT# 0 PIO 0 MIL# 0 R0 IO# K_[0..] PM_LP_#, K_0 PIO 0KRJ--P P_I -- K_ 0 PIO PM_U_TT# K_ PIO 0 K_ PIO P_L# K_ PIO FRONT_PWRL#,0 PM_PWRTN# K_ PIO0 K_ PIO0 K_MUT K_ PIO0 V_UX_ PIO0 0 K# 0 K0 PIO0 0 0 X-bus PIO0 0 PIO0 WIRL_TN# 0 RN KRIN# K0T PIO0 K0T_ ROM K0T PIO0 T_L PIO0 K# 0 T_ KRIN# PIO00 T_IN# KRIN#_ PIO0F RNKJ--P MI# MI# I# PIO0 I#_ PIO0 WIRL_N K_LP_WK 0 0 PIO0 PM_LKRUN#,,, PIO0 FPK PLT_RT#,, R 0KRJ--P HUPT-P NUM_L# PR_H 0 PIO0 R 0KRJ--P V_ PIOF LUTOOTH_N 0 PIO _TFULL# PIO LT_L# PIO WLN_TT_L R 0 PIO 00KRJ--P MIL_L# 0 0 HR_L# -0-0 PIO VV V_0 PIOI 0 TT_ PT PIOF RN 0 TLK_ PLK PIO MP_HUTOWN K_PIRT# P/ PT PIO R L_ON PLK PIO 0R00-P U0VZ-P L_ON PT PIO 0 PLK P0VJN-P V_0 RN0KJ--P RN TT_ TLK_ UVZ-P V_UX_ -0- UVZ-P V V V V V V V V PWM PWM PWM PWM PWM PWM PWM PWM0 VT KOL KOL KOL KOL KOL KOL KOL KOL KOL KOL0 KOL KOL KOL KOL KOL KOL 0 0 KO0 KO KO KO KO KO KO KO KO KO KO0 KO KO KO KO KO KO KO PWU0 PWU PWU PWU PWU PWU PWU PWU 0 KOL[..] 0 KROW[..] 0 KROW KROW KROW KROW KROW KROW KROW KROW 0 KI0 KI KI KI KI KI KI KI 0 RT# I# T_L T_ K_L K_ 0 L L N TN K_XO P0VJN-P X XLKO 0 XLKI K_XI N N N N N N P0VJN-P U K_L K_ RN RN0KJ--P V_0 V_UX_ -0-0 R Q N00PT-U 00KRJ--P R 00KRJ--P R0 00KRJ--P M_ M_ M_ M_ RN0KJ--P HN TO.00.0 K_P WI# RMRT#_K RIHTN K NL# _RT# I# -0- V_UX_ RN0KJ--P -0-0 R 0KRJ--P PM_PWRTN#, RMRT#_K _NL RIHTN,,,, PM_LP_# 0 K_PWRTN# _IN# 0 K_LI# K_LP_WK K_LP_WK P-OPN Place near K/ onnector (TOP side) UVZ-P Q0 N00PT-U H0PT-P RN Q RMRT# _NL -0-0 R 00KRF-L-P for the internal pull-up resistors on XIO[F:0] pins==>hig h=enable,low=isable for MRP==>High=isable,Low=nable for MW==>High=nable,Low=isable PIO0 for lock test mode==>high=test Mode,Low=KHz clock in normal running(recommended) U_PWR_N# PIO0 for PLL test mode==> High=Test Mode,Low=Normal operation(recommended) <ore esign> P_I -- Wistron orporation Taipei Hsien, Taiwan, R.O.. K N 0 (lviso) ize ocument Number R ev ustom ate: Thursday, October, 00 heet of 0

30 LUNH -0-0 LUNH ONN -ON-P 0.K0.0 ONNTOR nd nd source: 0.K0.0 V_0 MIL_L# MIL#_ INTRNT#_ K#_ K#_ PWRTN# INT_MI MIL_L# MIL#_ INTRNT#_ K#_ K#_ MIL# INTRNT# K# K# TP_LFT TP_RIHT W-TT--P-U TP_ROLL_LFT -- V_0 TP_ROLL_LFT.000. ONNTOR TP_ROLL_RIHT nd RL nd RL -ON-P ONNTOR RN 0.K0.0 WIRL_TN# RN0KJ--P WIRL_TN# nd source: 0.K0.0 LT_TN# Internal Keyoard ONN UVZ-P UVZ-P RN V_ -0-0 LT_TN# K_PWRTN# Level Trigger over Up witch RN0KJ--P OVR_W# K_LI# 0 K_LI# UVZ-P MIL_L# 0 00P0VJN-P 00RF-L-P-U PUH-W-P V_UX_ UVZ-P UVZ-P R00P0V--P R WLTN RN0J--P RN W-LI.00. ONNTOR TTN R 0KRJ--P R 0RJ--P W-LI.00. ONNTOR UVZ-P TOUH P TP_ROLL_UP RL TP_ROLL_OWN RL TP_LFT LFT ate: Tuesday, November 0, 00 heet 0 of 0 TP_T TP_LK TP_ROLL_RIHT TP_ROLL_UP TP_ROLL_OWN TP_RIHT RIHT KROW[..] KOL[..] R0 R TP_T Pin ==>*R0 KROW TP_LK Pin ==>*R0 KOL TP_RIHT K KOL TP_ROLL_RIHT Pin ==>*R0 KROW N# KROW Pin ==> 0 R00P0V--P 0... KROW 0 Pin ==> 0 R00P0V--P KROW 0 Pin ==> 0 R KOL KOL R R0 KOL Pin ==>*R0 KOL TP_ROLL_UP R0 KOL Pin ==> 0 KOL TP_ROLL_LFT R0 KROW KOL TP_ROLL_OWN 0 Pin ==> 0 KOL TP_LFT R0 KOL Pin0 ==> 0 R0 R00P0V--P KOL Pin ==> 0 R00P0V--P R0 0 R KOL Pin ==> 0 KOL R0 KOL Pin ==> 0 KOL R0 KOL KROW R0 KROW Pin ==>*R0 KOL 0 KOL0 Pin ==> 0 R0 KROW 0 Pin ==>*R0 R00P0V--P KROW 0 Pin ==>*R0 R KOL KOL R KOL Pin ==> KROW R KROW Pin ==> KOL0 0 0 KOL Pin0 ==>*R0 KROW R KOL R KOL Pin ==> R R00P0V--P KOL Pin ==> R R KROW Pin ==> N# <ore esign> KROW N# Pin ==> KROW -ON-P Pin ==> N KOL nd Wistron orporation 0.K0.0 R00P0V--P ONNTOR R Taipei Hsien, Taiwan, R.O.. nd source: 0.K0.0 KOL KOL KOL KOL UTTONs / K / TOUHP ize ocument Number Rev R00P0V--P MI ypass cap. W-TT--P-U.000. ONNTOR nd TT_ TLK_ nd source:.000. LI.00. ONNTOR W-TT--P-U.000. ONNTOR nd -0-0 R RN RN00J--P V_UX_ W-TT--P-U.000. ONNTOR nd UVZ-P R 0KRJ--P -0-0 W-TT--P-U.000. ONNTOR nd V_0 U0VZ-P 0 TP W-TT--P-U.000. ONNTOR nd -0 0

Morar Block Diagram 2005/05/28

Morar Block Diagram 2005/05/28 Morar lock iagram 00/0/ LK N. Mobile PU Project ode:.0.00 YTM / TP0, P:00- R II 0 MHz R II 0 MHz IT V,, HOT U Intel 0ML MI I/F 0MHz 00MHz,,,,0 R_VRF V_ R_VRF_ Line In Int. MI In, odec L 0MHz 0MHz LINK

More information

Canary2 Block Diagram

Canary2 Block Diagram anary lock iagram 0- V_0 0V_0 Line Out R II IN LK N. IT V RJ- RIL PORT, RT HOT U lviso-m MI I/F IH-M PT Port Replicator ( PIN) PRINTR MHz 00MHz ROM 0 P PI U LP U MI LIN IN LIN OUT TV OUT K TM R 00/MHz

More information

TV Out CRT LCD 13. Nvidia G72M-V 46 ~ 48, 51 ~ 55 PWR SW CP TI PCI ~ 25. Mini-PCI 30 LAN TXFM RJ45 RTL8111B DEBUG CONN 34

TV Out CRT LCD 13. Nvidia G72M-V 46 ~ 48, 51 ~ 55 PWR SW CP TI PCI ~ 25. Mini-PCI 30 LAN TXFM RJ45 RTL8111B DEBUG CONN 34 MYLL lock iagram a. Line In b. Mic In c. INT Mic d. Line Out e. INT.PKR R II O-IMM R II O-IMM P Layer tackup L: ignal L: V L: ignal L: ignal L: N L: ignal ~ LK N. IT V odec L OP MOM M ard ~ RM U / MHz

More information

G792 C/Y LVDS. 0 Ohm resistor (Y40) RGB CRT S 6,7,8,9,10. RGB switch. To Port Replicator (Y41) ENE. CardReader LAN 88E8055. Mini Card 802.

G792 C/Y LVDS. 0 Ohm resistor (Y40) RGB CRT S 6,7,8,9,10. RGB switch. To Port Replicator (Y41) ENE. CardReader LAN 88E8055. Mini Card 802. Y lock iagram INPUT OUTPUT R LK N. IT V / MHz, R / MHz INT.PKR RJ MOM M ard H 0 ROM 0 Mobile PU Yonah eleron M, T PT HOT U 00//MHz alistoga,,, MINI U TXFM Phone lue-tooth OM LPT U x port U P RT PORT PORT

More information

4 4 IDT CV125PA G S 533/667MHz TPS PCI Express x16 ATI. 3D3V_S0 2D5V_S0 VRAM x4 11,12. 1D8V_S3 1D5V_S0 Codec. CARDBUS CardReader

4 4 IDT CV125PA G S 533/667MHz TPS PCI Express x16 ATI. 3D3V_S0 2D5V_S0 VRAM x4 11,12. 1D8V_S3 1D5V_S0 Codec. CARDBUS CardReader YTM / TP0 LW- lock iagram LK N. IT VP Yonah P TKUP YTM /.//. TP, TOP INPUT OUTPUT TVO 0V_0 HOT U 00//MHz TOUT LV "WX+ V_ R /MHz L TP00 0 MHz alistoga, PI xpress x V_ R_VRF_0 TI RT V M Ver.: MP / MP R Ver.:

More information

4 4 RTM865T B0W 3 Max , 5 G TV Out CRT LCD. 3D3V_S0 2D5V_S0(130 ma) 11,12. Line In 1D8V_S3 1D5V_S0(5A) Codec

4 4 RTM865T B0W 3 Max , 5 G TV Out CRT LCD. 3D3V_S0 2D5V_S0(130 ma) 11,12. Line In 1D8V_S3 1D5V_S0(5A) Codec YTM / MX lock iagram RTMT-.00.0W P TKUP YTM / Max.00.00, TV Out TOP INPUT OUTPUT R LK N. / MHz, R / MHz /MHz Mobile PU Yonah eleron M HOT U 00//MHz@.0V alistoga TL+ PU I/F R Memory I/F INTRT RHPI Project

More information

Leopard2 Block Diagram

Leopard2 Block Diagram LK N I0 Leopard lock iagram Mobile PU othan V_UX onn PMI Power LOT witch TP0 /M in ard lost PI RU /M/MM/M lviso Host U 00/MHz V TI MP Mini-PI 0.a/b/g RJ ONN RJ ONN 0, 0/00 RTL00 MOM M ard, PI U -LINK,,,,,0,,,

More information

立成网. 视频教程 LICHENGNB.COM

立成网. 视频教程 LICHENGNB.COM 本图纸版权属原厂家所有 仅在服务该产品使用者时使用 YTM / TP0 Project code: 9.Q0.00 INPUT OUTPUT LW- lock iagram LK N. IT VP Yonah P TKUP YTM /.//. TP, TOP INPUT OUTPUT TVO 0V_0 HOT U 00//MHz TOUT LV "WX+ V_ R /MHz L TP00 0 MHz

More information

S Note-3 Block Diagram

S Note-3 Block Diagram Jan. ' Keyboard Light Thermal ensor MX99 LM I us / M us TML TRFN LIN OUT Int. MI MI IN RJ ONN Mus UNUFFR On-oard R OIMM x,,,, H 9 -PIN R OIMM UNUFFR R OIMM ocket, OP MP MX9 9 O 9,, Modem/luetooth U U lock

More information

4, 5. SVIDEO/COMP LVDS TPS51100(G2997) ,13. Marvell 88E Mini Card. abgn/bg 23. (100mA) INT.MIC. PCIex1.

4, 5. SVIDEO/COMP LVDS TPS51100(G2997) ,13. Marvell 88E Mini Card. abgn/bg 23. (100mA) INT.MIC. PCIex1. Volvi lock iagram YTM / MX LK N. Merom -00 INPUT OUTPUT T-0 P TKUP eleron M 0 (I LPR0).0 :.MROM.0U TOP V_(). :.MROM.0U, TOUT R / MHz R, /MHz Mobile PU HOT U /MHz@.0V Intel L0 TL+ PU I/F R Memory I/F INTRT

More information

Pamirs UMA Block Diagram

Pamirs UMA Block Diagram RJ ONN /IO/MM M/M Pro/x LK N ILPRKLFT-P RII / lot 0 RII / Ricoh R ardreader 0/00 NI Marvell 0 lot, Pamirs UM lock iagram RII hannel R II hannel PI LI Intel PU Meron M/M V F: or 00 MHz,, Host U /MHz restline-m/ml

More information

A8Jp/Jv/Je/Jn/Fm SCHEMATIC

A8Jp/Jv/Je/Jn/Fm SCHEMATIC Jp/Jv/Je/Jn/Fm HMTI P 0 0 0 0 ontent YTM P RF. Merom PU () Merom PU () PU P/THRML NOR LOK N. alistoga--pu alistoga--pi alistoga--r alistoga--powr alistoga--n alistoga--trap R O-IMM_0 R O-IMM_ R R TRMINTION

More information

ME3 Block Diagram HDD G792 ICH8-M. Project code : 91.4X PCB P/N : Revision : PCB LAYER LPC DEBUG CONN. TPM SLB9635TT KBC. Intel CPU.

ME3 Block Diagram HDD G792 ICH8-M. Project code : 91.4X PCB P/N : Revision : PCB LAYER LPC DEBUG CONN. TPM SLB9635TT KBC. Intel CPU. M lock iagram RII lot 0 RII lot Power witch RJ ONN Line In INT.PKR Line Out (PIF) RJ INT. MI rray igital HMI (PIF),, Mini ard_ Robson Mic In -T ONN RII hannel RII hannel MP MP MOM -T IL 0/00 ontroller

More information

THERMAL EMC2102 CRT 17 LCD HDMI MXM CONN. CardReader JMicro JMB385 LAN. MS/MS Pro/xD /MMC/SD. Giga LAN 88E PWR SW. New card. Mini Card.

THERMAL EMC2102 CRT 17 LCD HDMI MXM CONN. CardReader JMicro JMB385 LAN. MS/MS Pro/xD /MMC/SD. Giga LAN 88E PWR SW. New card. Mini Card. iger lock iagram LK N. I LPRKLFT R IMM /00 MHz INT.MI Line In MI In INT.PKR Line Out (PIF) RJ R IMM /00 MHz odec L V OP MP Q OP MP MOM M ard IO/H Mb /00MHz /00MHz ZLI PI H T O T T Mobile PU HOT U /00/0MHz@.0V

More information

FOXCONN Title. Schematics Page Index (Title / Revision / Change Date) Project Code & Schematics Subject:

FOXCONN Title. Schematics Page Index (Title / Revision / Change Date)   Project Code & Schematics Subject: Page of chematics Page 0 chematics Page Index 0 lock iagram 0 Penryn(HOT U) / 0 Penryn(HOT U) / 0 Penryn (Power/nd) / 0 LOK N 0 antiga (HOT) / 0 antiga (MI) / 0 antiga (RPHI) / 0 antiga (RII) / antiga

More information

YUHINA Block Diagram G768D ICH4-M. GMCH Montara-GT. Mobile CPU Portability Mobile P4 DDR*2 HDD 17 USB 4 PORT CD ROM RGB LVDS

YUHINA Block Diagram G768D ICH4-M. GMCH Montara-GT. Mobile CPU Portability Mobile P4 DDR*2 HDD 17 USB 4 PORT CD ROM RGB LVDS R* MHz LK N. Y,0 YUHIN lock iagram, HOT U MH Montara-T ' O XQ HU I/F MHz MHz IH-M,, PI U RU TWO LOT OP MP MOM+T M ard -Link PI,, LP U R LV N IO P RU PI HK // H U PORT LN RTL 0L //, K M Touch Pad PWR W

More information

RP-note4 Block Diagram

RP-note4 Block Diagram H F 0 pril 0 '0 Keyboard Light R Termination,ecap, FN Thermal ensor MX0 TPM(T0) RFI (P0) HP OUT 0 HP OUT Int. MI MI IN Mus MI IN tereo peaker x UNUFFR R OIMM Normal ocket 00-PIN R OIMM UNUFFR R OIMM Normal

More information

G D8V_S3 667/8000MHz WXGA/SXGA+ LVDS. New card G577 USB 2.0. ACPI in 1 TRL8101E 23 PCI-E / USB 2.0 LPC BUS KBC.

G D8V_S3 667/8000MHz WXGA/SXGA+ LVDS. New card G577 USB 2.0. ACPI in 1 TRL8101E 23 PCI-E / USB 2.0 LPC BUS KBC. E YTEM / Project code: TP P0 lock iagram YTEM / Mobile PU PWQI LK EN. ILPRYLFT-P RTMT-0-V-RT HOT U Penryn, /00/0MHz@.0V Line Out odec H udio PI-E/U.0 L IHM New card PIe ports MI In PI/PI RIE M/M Pro/ U.0

More information

C45/C46 Block Diagram

C45/C46 Block Diagram / lock iagram LK EN I LPR.00.00W Mobile PU Merom /., Project code:.u0.00 Project code:.v00.00 P Number : 0 Revision : - YTEM / TP0 INPUT TOUT OUTPUT V_() V_() YTEM / INPUT TOUT OUTPUT 0V_0(.) V_(.) R /

More information

Model : M30EI0. Mobile Dothan with INTEL 915GM / ICH6-M Chipset

Model : M30EI0. Mobile Dothan with INTEL 915GM / ICH6-M Chipset Revision History / ORIINL RELEE Model : MEI Mobile othan with INTEL M / IH-M hipset P INEX P YTEM LOK IRM P POWER IRM & EQUENE P PIO & POWER ONUMPTION P PU anias/othan-/ P PU anias/othan-/ P LOK EN I P

More information

G HDMI 4, 5. DVI ATI M76-M PCI-EG. Page.44~50 LAN 10/100/1000 PCI-E6. INTEL 82566MM Page.23,24 PCI-E3 PCI-E4 /USB 2.

G HDMI 4, 5. DVI ATI M76-M PCI-EG. Page.44~50 LAN 10/100/1000 PCI-E6. INTEL 82566MM Page.23,24 PCI-E3 PCI-E4 /USB 2. R lock iagram LK EN. / MHz R MI In x I LPR / MHz odec L /MHz ZLI OP MP Q INT.PKR x OK E R PI-E PI-Express U.0 PORT/PORT Repeater/ PIEQX0 ock Port x Jack In x RJ- Ethernet Port x HMI x RT x U.0 x udio In

More information

FOXCONN Title. Schematics Page Index (Title / Revision / Change Date) Rev M/B P/N:

FOXCONN Title. Schematics Page Index (Title / Revision / Change Date) Rev M/B P/N: Page 0 0 0 0 0 0 0 0 0 0 0 0 of chematics Page chematics Page Index lock iagram Merom(HOT U) / Merom(HOT U) / Merom(Power/nd) / LOK N restline (HOT) / restline (MI) / restline (RPHI) / restline (RII) /

More information

MYALL M Block Diagram

MYALL M Block Diagram VRMx L UP to 0 X 00 Mini ard 0.a/b/g MV /M PI x MYLL M lock iagram,,0,,,,,, RJ TXFM a. Line In b. Mic In c. INT Mic d. Line Out e. INT.PKR M PU NPT Processor Rev. F package M H UIO nvii MV HyperTransport+

More information

M630/M640 Main Board.

M630/M640 Main Board. chematics Page Index ( / Revision / hange ate) Page of chematics Page Rev. ate Page 0 chematics Page Index 0 lock iagram 0 Merom(HOT U) / 0 Merom(HOT U) / 0 Merom(Power/nd) / 0 0 LOK N 0 restline (HOT)

More information

SC 2003/01/03 G768D ICH4-M. GMCH Montara-GML. Project Code 91.49T Mobile CPU M/B 48.45Z01.0SC SC DDR*2 USB 3PORT HDD 18 CD ROM

SC 2003/01/03 G768D ICH4-M. GMCH Montara-GML. Project Code 91.49T Mobile CPU M/B 48.45Z01.0SC SC DDR*2 USB 3PORT HDD 18 CD ROM R* MHz LK N. I,0 M lock iagram Mobile PU P-M eleron, HOT U MH Montara-ML ' O XQ HU I/F 00MHz MHz IH-M,, PI U INT.PKR OP MP P00 MOM M ard -Link PI,, LP U R LV TV_OUT H ROM U PORT RU 0 R FW0 LN RTL 00L //

More information

46 D b r 4, 20 : p t n f r n b P l h tr p, pl t z r f r n. nd n th t n t d f t n th tr ht r t b f l n t, nd th ff r n b ttl t th r p rf l pp n nt n th

46 D b r 4, 20 : p t n f r n b P l h tr p, pl t z r f r n. nd n th t n t d f t n th tr ht r t b f l n t, nd th ff r n b ttl t th r p rf l pp n nt n th n r t d n 20 0 : T P bl D n, l d t z d http:.h th tr t. r pd l 46 D b r 4, 20 : p t n f r n b P l h tr p, pl t z r f r n. nd n th t n t d f t n th tr ht r t b f l n t, nd th ff r n b ttl t th r p rf l

More information

F80Q SCHEMATIC Revision 2.00

F80Q SCHEMATIC Revision 2.00 F0Q HMTI Revision.00 P 0 0 0 0 ontent YTM P RF. PU-Penryn() PU-Penryn() PU P, Thermal enor LOK N._ILPRLF N_-0L ()--PU N_-0L ()--R/P N_-0L ()--R bus N_-0L ()--POWR N_-0L ()--POWR N_-0L ()--/trapping R O-IMM_0

More information

Extreme/Meron 2M/4M SV FSB:667 or 800 MHz 4~7. Host BUS 667/800MHz. PCIe x16 8~14. DMI I/F 100MHz. USB 2.0 USB x 427 SATA PATA PCI/PCI BRIDGE 22~25

Extreme/Meron 2M/4M SV FSB:667 or 800 MHz 4~7. Host BUS 667/800MHz. PCIe x16 8~14. DMI I/F 100MHz. USB 2.0 USB x 427 SATA PATA PCI/PCI BRIDGE 22~25 LT- lock iagram YTEM / TP0 INPUT OUTPUT 0 /MM M/M Pro/x 0 RJ ONN EXT MI LK EN ILPR Thermal ensor/ Fan control MT RII / RII / lot lot Ricoh R ardreader OROM M0/M 0/00M/000M TLE RJ ML0 ONN RELTEK H UIO OE

More information

G792 4,5, 6,7 CLK GEN. ICS 9LPR462 (RTM870T-690) 10,11,12,13. PCI-E x 4. 25MHz KHz USB 16,17,18,19, KHz CCD.3M/1.

G792 4,5, 6,7 CLK GEN. ICS 9LPR462 (RTM870T-690) 10,11,12,13. PCI-E x 4. 25MHz KHz USB 16,17,18,19, KHz CCD.3M/1. RJ TXFM R OIMM IMM R OIMM Line In MI In INT.PKR Line Out (No-PIF) RJ IMM Yukon lock iagram Mini ard 0.a/b/g/n MHz MP Q, LN MP Q 0/00 Marvell00, INT. MI rray odec L MOM M ard H ROM R II //00 R II //00 HyperTransport

More information

RETICLE 2 NORTH SW2 DPDT SOUTH. LM339A TxD1 Out 11 U2D DEC PULSE 1 FOCUSER-2 3.0V 17 CCD EAST U2A AUX -6 FOCUSER-2 FOCUSER SW1 DPDT

RETICLE 2 NORTH SW2 DPDT SOUTH. LM339A TxD1 Out 11 U2D DEC PULSE 1 FOCUSER-2 3.0V 17 CCD EAST U2A AUX -6 FOCUSER-2 FOCUSER SW1 DPDT J KYP PWR J TX0\ RTIL RX0\ U V V NORTH V- NORTH/SH LM J RS V MIS XMIT LX00 XMIT LX00 RV MIS RV U SH V LM RN V V 0K J U LN 0 RX0\ 0 V TTRY LM Tx Out TX0\ Rx In Tx Out RTIL 0 Rx In U 0 V LM 0 PULS FOUSR-

More information

core Tiny6410.sch DM9000 DM9000-etc.sch AC97 AC97-etc.sch USB HUB USB-HUB.sch Tiny6410SDK 1103

core Tiny6410.sch DM9000 DM9000-etc.sch AC97 AC97-etc.sch USB HUB USB-HUB.sch Tiny6410SDK 1103 core Tiny0.sch M000 M000-etc.sch -etc.sch US HU US-HU.sch Tiny0SK 0 M_ VV V V V V V V V V V VN VSYN VLK VUS OTGI OTGM OTGP IN0 S_LK S_n S_T0 S_T OUT0 INT INT INT RST ( 红色 ) Tiny0 Tiny0 P Power Supply S

More information

l f t n nd bj t nd x f r t l n nd rr n n th b nd p phl t f l br r. D, lv l, 8. h r t,., 8 6. http://hdl.handle.net/2027/miun.aey7382.0001.001 P bl D n http://www.hathitrust.org/access_use#pd Th r n th

More information

4 8 N v btr 20, 20 th r l f ff nt f l t. r t pl n f r th n tr t n f h h v lr d b n r d t, rd n t h h th t b t f l rd n t f th rld ll b n tr t d n R th

4 8 N v btr 20, 20 th r l f ff nt f l t. r t pl n f r th n tr t n f h h v lr d b n r d t, rd n t h h th t b t f l rd n t f th rld ll b n tr t d n R th n r t d n 20 2 :24 T P bl D n, l d t z d http:.h th tr t. r pd l 4 8 N v btr 20, 20 th r l f ff nt f l t. r t pl n f r th n tr t n f h h v lr d b n r d t, rd n t h h th t b t f l rd n t f th rld ll b n

More information

8V Title SCHEMATIC, 8V89317EVB REV A. Date: Friday, June 14, Power Supply. XTAL Interface. 12.8MHz TCXO/OCXO LED Status IN1 OUT1

8V Title SCHEMATIC, 8V89317EVB REV A. Date: Friday, June 14, Power Supply. XTAL Interface. 12.8MHz TCXO/OCXO LED Status IN1 OUT1 isclaimer: IT is providing this schematic for reference purposes only. lthough the schematic was taken from a known working design, it is being provided "as is" without any express or implied warranty

More information

n r t d n :4 T P bl D n, l d t z d th tr t. r pd l

n r t d n :4 T P bl D n, l d t z d   th tr t. r pd l n r t d n 20 20 :4 T P bl D n, l d t z d http:.h th tr t. r pd l 2 0 x pt n f t v t, f f d, b th n nd th P r n h h, th r h v n t b n p d f r nt r. Th t v v d pr n, h v r, p n th pl v t r, d b p t r b R

More information

H NT Z N RT L 0 4 n f lt r h v d lt n r n, h p l," "Fl d nd fl d " ( n l d n l tr l t nt r t t n t nt t nt n fr n nl, th t l n r tr t nt. r d n f d rd n t th nd r nt r d t n th t th n r lth h v b n f

More information

D t r l f r th n t d t t pr p r d b th t ff f th l t tt n N tr t n nd H n N d, n t d t t n t. n t d t t. h n t n :.. vt. Pr nt. ff.,. http://hdl.handle.net/2027/uiug.30112023368936 P bl D n, l d t z d

More information

Mocha-1 Block Diagram

Mocha-1 Block Diagram May.0 Thermal ensor MX I us / M us us witch I 0 -in- lot RJ onn udio odec IOU ard Mus UNUFFR R OIMM Normal ocket 0-PIN R OIMM UNUFFR R OIMM Reverse ocket T H Media ard Reader U U.0 H U.0 H Media lice Finger

More information

PR D NT N n TR T F R 6 pr l 8 Th Pr d nt Th h t H h n t n, D D r r. Pr d nt: n J n r f th r d t r v th tr t d rn z t n pr r f th n t d t t. n

PR D NT N n TR T F R 6 pr l 8 Th Pr d nt Th h t H h n t n, D D r r. Pr d nt: n J n r f th r d t r v th tr t d rn z t n pr r f th n t d t t. n R P RT F TH PR D NT N N TR T F R N V R T F NN T V D 0 0 : R PR P R JT..P.. D 2 PR L 8 8 J PR D NT N n TR T F R 6 pr l 8 Th Pr d nt Th h t H h n t n, D.. 20 00 D r r. Pr d nt: n J n r f th r d t r v th

More information

Project Name :I36IAx Platform : Celeron GS40 + Park + ICH9M

Project Name :I36IAx Platform : Celeron GS40 + Park + ICH9M Project Name :IIx Platform : eleron + 0 + Park + IHM PE..... PU... 0_FF. 0...... -IHM.... 0.......... 0....... POWER... 0. ONTENT INEX YTEM LOK IRM POWER IRM & EQUENE Power on equence iagram PU Penryn

More information

C107 C108 C uF/10V Ta. 10uF/10V Ta. 100nF. 100nF. 100nF C106 C111 C110 VCC VCC AVCC (AD0)PA0 (AD1)PA1 (AD2)PA2 (AD3)PA3 (AD4)PA4 (AD5)PA5

C107 C108 C uF/10V Ta. 10uF/10V Ta. 100nF. 100nF. 100nF C106 C111 C110 VCC VCC AVCC (AD0)PA0 (AD1)PA1 (AD2)PA2 (AD3)PA3 (AD4)PA4 (AD5)PA5 ate: may 0 Kiad.... ize: Id: / RPIVR alarm v. File: rpialarm.sch heet: / pittnerovi.com P0 P P 0 P0 PI VR_ IRQ IRQ VR_ V R0 00k RFM_IRQ PWM LOOP LOOP0 comm comm.sch 00uF/.V R0 00k V VR_ K VR_ V V RT P0

More information

Alba Discrete ATI M92-LP gddr2 Schematics ufcpga Mobile Penryn Intel Cantiga-PM + ICH9M REV : SA

Alba Discrete ATI M92-LP gddr2 Schematics ufcpga Mobile Penryn Intel Cantiga-PM + ICH9M REV : SA lba iscrete TI M-LP gr chematics ufp Mobile Penryn Intel antiga-pm + IHM 00-0- REV : : Nopop omponent M : Pop when antiga is M PM : Pop when antiga is PM /P : OM control if antiga is PM Wistron

More information

22 t b r 2, 20 h r, th xp t d bl n nd t fr th b rd r t t. f r r z r t l n l th h r t rl T l t n b rd n n l h d, nd n nh rd f pp t t f r n. H v v d n f

22 t b r 2, 20 h r, th xp t d bl n nd t fr th b rd r t t. f r r z r t l n l th h r t rl T l t n b rd n n l h d, nd n nh rd f pp t t f r n. H v v d n f n r t d n 20 2 : 6 T P bl D n, l d t z d http:.h th tr t. r pd l 22 t b r 2, 20 h r, th xp t d bl n nd t fr th b rd r t t. f r r z r t l n l th h r t rl T l t n b rd n n l h d, nd n nh rd f pp t t f r

More information

XBee Wi-Fi Dev Kit Block Diagram Socketed Through-hole Variant PART NO O c Digi International Inc. 6. Disconnect switches

XBee Wi-Fi Dev Kit Block Diagram Socketed Through-hole Variant PART NO O c Digi International Inc. 6. Disconnect switches 0 Xee Wi-i or Xee Z isconnect switches ar raph river ar raph U-to-serial converter U onnector Vibration Motor Power upply Input:.V to V Output:.V PWM-to-frequency converter circuit uzzer (kz) arrel ack

More information

4 4 N v b r t, 20 xpr n f th ll f th p p l t n p pr d. H ndr d nd th nd f t v L th n n f th pr v n f V ln, r dn nd l r thr n nt pr n, h r th ff r d nd

4 4 N v b r t, 20 xpr n f th ll f th p p l t n p pr d. H ndr d nd th nd f t v L th n n f th pr v n f V ln, r dn nd l r thr n nt pr n, h r th ff r d nd n r t d n 20 20 0 : 0 T P bl D n, l d t z d http:.h th tr t. r pd l 4 4 N v b r t, 20 xpr n f th ll f th p p l t n p pr d. H ndr d nd th nd f t v L th n n f th pr v n f V ln, r dn nd l r thr n nt pr n,

More information

Caramel-1 Block Diagram

Caramel-1 Block Diagram JUL'0 Thermal ensor MX I us / M us us witch I -in- lot RJ onn udio odec IOU ard Mus UNUFFR R OIMM Normal ocket 0-PIN R OIMM UNUFFR R OIMM Reverse ocket T H Media ard Reader U U.0 H U.0 H Media lice luetooth

More information

828.^ 2 F r, Br n, nd t h. n, v n lth h th n l nd h d n r d t n v l l n th f v r x t p th l ft. n ll n n n f lt ll th t p n nt r f d pp nt nt nd, th t

828.^ 2 F r, Br n, nd t h. n, v n lth h th n l nd h d n r d t n v l l n th f v r x t p th l ft. n ll n n n f lt ll th t p n nt r f d pp nt nt nd, th t 2Â F b. Th h ph rd l nd r. l X. TH H PH RD L ND R. L X. F r, Br n, nd t h. B th ttr h ph rd. n th l f p t r l l nd, t t d t, n n t n, nt r rl r th n th n r l t f th f th th r l, nd d r b t t f nn r r pr

More information

0 t b r 6, 20 t l nf r nt f th l t th t v t f th th lv, ntr t n t th l l l nd d p rt nt th t f ttr t n th p nt t th r f l nd d tr b t n. R v n n th r

0 t b r 6, 20 t l nf r nt f th l t th t v t f th th lv, ntr t n t th l l l nd d p rt nt th t f ttr t n th p nt t th r f l nd d tr b t n. R v n n th r n r t d n 20 22 0: T P bl D n, l d t z d http:.h th tr t. r pd l 0 t b r 6, 20 t l nf r nt f th l t th t v t f th th lv, ntr t n t th l l l nd d p rt nt th t f ttr t n th p nt t th r f l nd d tr b t n.

More information

NV11,4Mx16 DDR, RGB, INTERNAL DVI-I, AGP.

NV11,4Mx16 DDR, RGB, INTERNAL DVI-I, AGP. . NV.V 00PF 00PF 00PF 0.UF 0.UF 0.UF 0.UF 0UF 0UF 0 0.UF 0.UF.V TO- -pin package Semtech Z, Unisem US0 00 NV O- RG-PWR-IN.V@ /- 0mV 0UF 00PF 00PF 0 00PF 0UF 00PF 0UF 0 0.UF 0 00PF 0.UF 0 O0 U POWR SNS

More information

CLKOUT CLKOUT VCC CLKOUT RESOUT OSCOUT ALE TEST AD0 66 AD2 INT0 INT0 AD INT1 AD INT2/INTA0 AD5 AD7 AD7 INT AD8 AD8 AD10

CLKOUT CLKOUT VCC CLKOUT RESOUT OSCOUT ALE TEST AD0 66 AD2 INT0 INT0 AD INT1 AD INT2/INTA0 AD5 AD7 AD7 INT AD8 AD8 AD10 I U N R 00K RSIN* RST S N.0u Y LK TP RP K L TP USY INT0 INT RISMINT P.0 P. P. P. P. P. P. RY OL RX0 TX0 T P.0 P. P. P. S* S* S* S* RROR* SLK U LKIN LKOUT LKOUT LKIN LKOUT OSOUT 0 OSOUT L L RSIN* L 0 0

More information

L53II0 M/B and Daughter P/N LIST:

L53II0 M/B and Daughter P/N LIST: Model : LII0 P P/N:L00- P P/N:L00- Intel Merom PU + M + IH-M hipset LII0 M/ and aughter P/N LIT: LII0 M/ ffiliated FF/able P/N LIT: P0 INEX P0 YTEM LOK IRM P0 POWER IRM & EQUENE P0 PIO & POWER ONUMPTION

More information

Sirius-Rx-232. Sirius-Tx-232. SIRIUS-Rx. STATUS Prog RC-5. SIRIUS-Rx. Prog RCA-5 DAB-SDA DAB-SCL STAYUS AM-SMETER POWER-ON POWER-ON CE-PLL

Sirius-Rx-232. Sirius-Tx-232. SIRIUS-Rx. STATUS Prog RC-5. SIRIUS-Rx. Prog RCA-5 DAB-SDA DAB-SCL STAYUS AM-SMETER POWER-ON POWER-ON CE-PLL UIO-OUT& U&.SH Sirius-Tx- +V-SY Sirius-Rx- -S -SL - S MU MU.SH M&M M&M.SH M ST M-SMETER E-PLL +V- +V- T-IN T-IN T-LK +V-STY +V-STY T-OUT ate: -Sep-00 Sheet of ile: :\aa\t. rawn y: RS-Tx RS-Rx R- STYUS

More information

Astrosphere Block Diagram

Astrosphere Block Diagram strosphere lock iagram YTM / TP M PU NPT Processor Rev. package,,, RII /00 hannel RII /00 hannel RII RII lot 0 lot, INPUT TOUT OUTPUT +VLW +VLW YTM / TP HP PROM HP HP HyperTransport X./ HMI HMI R RT TVOUT

More information

Th pr nt n f r n th f ft nth nt r b R b rt Pr t r. Pr t r, R b rt, b. 868. xf rd : Pr nt d f r th B bl r ph l t t th xf rd n v r t Pr, 00. http://hdl.handle.net/2027/nyp.33433006349173 P bl D n n th n

More information

J1B B1 B3 B5 B7 B9 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B35 B37 B39 B41 B43 B45 B47 B49 B51 B53 B55 B57 VCC VCC USB_DET

J1B B1 B3 B5 B7 B9 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B35 B37 B39 B41 B43 B45 B47 B49 B51 B53 B55 B57 VCC VCC USB_DET GP0 GP0 GP0 P0 GP0 GP GP GP GP GP GP GP P GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP00 UINO ONE PIN EFINE GP0 GP GP GP GP GP GP GP GP0 GP GP

More information

,. *â â > V>V. â ND * 828.

,. *â â > V>V. â ND * 828. BL D,. *â â > V>V Z V L. XX. J N R â J N, 828. LL BL D, D NB R H â ND T. D LL, TR ND, L ND N. * 828. n r t d n 20 2 2 0 : 0 T http: hdl.h ndl.n t 202 dp. 0 02802 68 Th N : l nd r.. N > R, L X. Fn r f,

More information

n

n p l p bl t n t t f Fl r d, D p rt nt f N t r l R r, D v n f nt r r R r, B r f l. n.24 80 T ll h, Fl. : Fl r d D p rt nt f N t r l R r, B r f l, 86. http://hdl.handle.net/2027/mdp.39015007497111 r t v n

More information

VF-co-cc. Spears AMD UMA Block Diagram. AMD CPU K8 Rev. G S1g1 package. North Bridge Ricoh R5C833 CardReader. South Bridge. Azalia CODEC OP AMP

VF-co-cc. Spears AMD UMA Block Diagram. AMD CPU K8 Rev. G S1g1 package. North Bridge Ricoh R5C833 CardReader. South Bridge. Azalia CODEC OP AMP LK N ILPR /IO/MM M/M Pro/x RJ ONN pears M UM lock iagram RII / RII / lot 0 lot Local Frame uffer RII M *, Ricoh R ardreader RealTek 0/00 RTL00 M RJ ONN MOM (Optional) igital Mic rray MI IN HP HP Internal

More information

NTCA2 2 LA6A JA6 CYA6 ACL3 VAA3 DA48 CYA19 LA6B DA45 CTA4B DA46 CTA5B G2 CTA3B RA135 QA6 RA144 CNA5 CNA6 VO-B1 S12VA SGND SGND GATE

NTCA2 2 LA6A JA6 CYA6 ACL3 VAA3 DA48 CYA19 LA6B DA45 CTA4B DA46 CTA5B G2 CTA3B RA135 QA6 RA144 CNA5 CNA6 VO-B1 S12VA SGND SGND GATE L Y Y N 0 F F L X V L X N L L L N Y Y NT L NT J L PV -T L L Y Y V L X N L N VM 0 0 J0 PN J PN PN J PN PN PN PN V VM 0 F P V V N (-) (+) (+) (-) L 0 0 0 0 0 0 0 0 0 0 L L T Q T T T Q + F Y Y 0 V/N N/VP

More information

Thurman UM chematics ocument ufp Mobile Merom Intel restline-m + IHM 00-0- REV : (ELL:X0) Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Thurman UM ize ocument Number

More information

Th n nt T p n n th V ll f x Th r h l l r r h nd xpl r t n rr d nt ff t b Pr f r ll N v n d r n th r 8 l t p t, n z n l n n th n rth t rn p rt n f th v

Th n nt T p n n th V ll f x Th r h l l r r h nd xpl r t n rr d nt ff t b Pr f r ll N v n d r n th r 8 l t p t, n z n l n n th n rth t rn p rt n f th v Th n nt T p n n th V ll f x Th r h l l r r h nd xpl r t n rr d nt ff t b Pr f r ll N v n d r n th r 8 l t p t, n z n l n n th n rth t rn p rt n f th v ll f x, h v nd d pr v n t fr tf l t th f nt r n r

More information

3V3 DECOUPLING DS90LV018A MCLKTON 4U7/10V +/-10% C196 +/-10% LCLK1IN+ NMCLKTON SK18 74LS123 MULTI +/-5% C N C94 10N

3V3 DECOUPLING DS90LV018A MCLKTON 4U7/10V +/-10% C196 +/-10% LCLK1IN+ NMCLKTON SK18 74LS123 MULTI +/-5% C N C94 10N 0 THIS RWG ONORMS TO.S. -T-0-00-0- U/0V +/-% 00N +/-0% 0N +/-0% U/0V +/-% 00N +/-0% 0 0N +/-0% R R 0R % P/0V +/-% K % U S YLLOW U 0 U U S0LV0 MLKTON /R S S R SK LS MULTI U/0V +/-% 00N +/-0% 0N +/-0% LLK+

More information

1K21 LED GR N +33V 604R VR? 1K0 -33V -33V 0R0 MUTE SWTH? JA? T1 T2 RL? +33V 100R A17 CB? 1N N RB? 2K0 QBI? OU T JE182 4K75 RB? 1N914 D?

1K21 LED GR N +33V 604R VR? 1K0 -33V -33V 0R0 MUTE SWTH? JA? T1 T2 RL? +33V 100R A17 CB? 1N N RB? 2K0 QBI? OU T JE182 4K75 RB? 1N914 D? L P.O. O X 0, N L R. PROROUH, ONRIO N KJ Y PHO N (0) FX (0) 0 WWW.RYSON. ate : Size : 000 File : OVRLL SHMI.Schoc Sheet : 0 of 0 Rev : rawn : 0.0 0K K 0K K 0K0 0K0 0K0 0K0 0K0 00K R K0 R K 0R??? 00N M?

More information

PCIextend 174 User s Manual

PCIextend 174 User s Manual PIextend 7 User s Manual Preliminary M6- February Sycard Technology 8-F Miraloma Way Sunnyvale, 98 (8) 79- (8) 79- FX PIextend 7 User s Manual Page. Introduction Sycard Technology's PIextend 7 PI extender

More information

Tibet Block Diagram. DDRII 667/800 Channel A. DDRII 667/800 Channel B 3,4,5,6. HyperTransport 16X16 6.4GB/S SVIDEO/COMP RGB CRT

Tibet Block Diagram. DDRII 667/800 Channel A. DDRII 667/800 Channel B 3,4,5,6. HyperTransport 16X16 6.4GB/S SVIDEO/COMP RGB CRT Tibet lock iagram YTM / MX M PU NPT Processor Rev. package,,, RII /00 hannel RII /00 hannel RII RII lot 0 lot, INPUT TOUT OUTPUT V_ V_ YTM / MX HP PROM HP HP HyperTransport X./ VIO/OMP TVOUT INPUT TOUT

More information

CD-DET TP5_CS- LCDPWR RFPWR CHPD5 GP05 GP25 RST5 L13 D12 D11 D10 LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS- LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS-

CD-DET TP5_CS- LCDPWR RFPWR CHPD5 GP05 GP25 RST5 L13 D12 D11 D10 LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS- LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS- SPST SW L 0uH.uF TP HEER NO STUFF TP 0 HEER NO STUFF TP TP pf Y.uF.uF 0 HEER NO STUFF 0 HEER NO STUFF MHz, 0ppm pf.uf (OUT) (IN) R 0K /W % 0uF OUT OUT OUT OUT KLT L 0 L_MISO L_MOSI L_SK S_S- L_S- L_- L_

More information

EDP-AM-DIO54 Digital IO Module User Manual. This document contains information on the DIO54 digital IO module for the RS EDP system.

EDP-AM-DIO54 Digital IO Module User Manual. This document contains information on the DIO54 digital IO module for the RS EDP system. P-M-IO igital IO Module User Manual This document contains information on the IO digital IO module for the RS P system. Version v.0, 0/0/00 P-M-IO Manual ontents. igital IO Module. igital Outputs.... Using

More information

Beyonce UMA Schematics Document. ufcpga Mobile Merom Intel Crestline-GM + ICH8M REV : -2 (DELL:A00)

Beyonce UMA Schematics Document. ufcpga Mobile Merom Intel Crestline-GM + ICH8M REV : -2 (DELL:A00) eyonce UM chematics ocument ufp Mobile Merom Intel restline-m + IHM 00-0- REV : - (ELL:00) Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. eyonce UM ize ocument Number

More information

Humanistic, and Particularly Classical, Studies as a Preparation for the Law

Humanistic, and Particularly Classical, Studies as a Preparation for the Law University of Michigan Law School University of Michigan Law School Scholarship Repository Articles Faculty Scholarship 1907 Humanistic, and Particularly Classical, Studies as a Preparation for the Law

More information

ISA INTERFACE & POWER SELECTION Size Document Number Rev Custom. XR82C684 EVAL BOARD 1.2 Date: Monday, August 13, 2007 DO NOT INSTALL CON_AT62B

ISA INTERFACE & POWER SELECTION Size Document Number Rev Custom. XR82C684 EVAL BOARD 1.2 Date: Monday, August 13, 2007 DO NOT INSTALL CON_AT62B IS_IRQ V._0._0._0 O NOT IS_IRQ R K_0._0.0_0 J J.0_0 0 RV_RESET V RV_RESET V TP J IS TEST._0 TP V X [0..] [0..] GN GN -I/O H K RESRV V 0 IRQ V -V REQ -V U 0WS 0 0 V 0 -IO_HRY._0 GN -I/O H RY 0 -SMEMW EN

More information

VF-co-cc. F3Jr CPU CLOCK GEN. ATI M64-M or M76-M NORTH DDR2 SO-DIMM0 BRIDGE DDR2 SO-DIMM1 TPM 1.2 INFINEON SLB9635 SOUTH BRIDGE EC ITE IT8510E

VF-co-cc. F3Jr CPU CLOCK GEN. ATI M64-M or M76-M NORTH DDR2 SO-DIMM0 BRIDGE DDR2 SO-DIMM1 TPM 1.2 INFINEON SLB9635 SOUTH BRIDGE EC ITE IT8510E 0 0 0 0 0 0 0 lock iagram ystem etting * PU-YONH(HOT) PU-YONH(PWR) * N-PM(HOT) * U ONN * I ROM * LE * R Mx x Option PU YONH MEROM W W LOK EN I 0 FJr 0 0 0 N-PM(MI & F) N-PM(RPHI) N-PM(R) N-PM(PWR) 0 &

More information

+18VL. 220uf 25V. 0.1u C10UF. 100k AGND LEFT_OUT_+VE R19 22R -18VL. C9 150pF +18VL LEFT_OUT_-VE R uf 25V 22R

+18VL. 220uf 25V. 0.1u C10UF. 100k AGND LEFT_OUT_+VE R19 22R -18VL. C9 150pF +18VL LEFT_OUT_-VE R uf 25V 22R RVIION ROR O NO: PPROV: T: VL LFT_IN_V Pt Q 0 Q R Q 0 R Q 0nf Q 0 N W R 0 00 0k Pt R 00 R R k R W R 00 0 00u W 00pf u R 00k N Q J u 0 Q Q 0 0.u 0UF 0uf V R 00k N R R LFT_OUT_V Notes: Use either Q/Q or

More information

R&D Division. Board name : Mother Board Schematic Project : Z11D (Santa Rosa) Version : 0.4 Initial Date : March 02, Inventec Corporation

R&D Division. Board name : Mother Board Schematic Project : Z11D (Santa Rosa) Version : 0.4 Initial Date : March 02, Inventec Corporation Inventec orporation R& ivision oard name : Mother oard chematic Project : Z (anta Rosa) Version : 0. Initial ate : March 0, 00 Inventec orporation F, No., ection, Zhongyang outh Road eitou istrict, Taipei

More information

DR1 (Roberts) Schematics Document ufcpga Mobile Penryn Intel Cantiga-GM + ICH9M REV : A00

DR1 (Roberts) Schematics Document ufcpga Mobile Penryn Intel Cantiga-GM + ICH9M REV : A00 R () chematics ocument ufpg Mobile Penryn Intel antiga-gm + IHM 00-0-0 REV : 00 : Nopop omponent Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. over Page

More information

Cover Sheet Block Diagram MAIN CLOCK GEN DDR CLOCK BUFFER mpga478-b INTEL CPU Sockets DDR SLOT DDR TERMINATOR SIS 961A SOUTH BRIDGE AC'97 CODEC

Cover Sheet Block Diagram MAIN CLOCK GEN DDR CLOCK BUFFER mpga478-b INTEL CPU Sockets DDR SLOT DDR TERMINATOR SIS 961A SOUTH BRIDGE AC'97 CODEC Last chematic Update ate: // M- VRION: I / HIPT Willamette/Northwood pin mp- Processor chematics over heet lock iagram MIN LOK N R LOK UFFR mp- INTL PU ockets - I / NORTH RI - PU: Willamette/Northwood

More information

AS1117M3 or LM1117MPX-ADJ ADJ. C20 0.1uF + C56. + C57 10uF. 10 uf R K 1% R18 GND 10.0K 1%

AS1117M3 or LM1117MPX-ADJ ADJ. C20 0.1uF + C56. + C57 10uF. 10 uf R K 1% R18 GND 10.0K 1% K POWER SW JP EXTERNL POWER FUSE 0. uf VT 0 uf R SM or LMMPX-J VIN VOUT U 0.0K % J R.K % 0uF REG_V 0 0.uF REG_V J PV PV_US_TGT V_M0X POWER_SELET R0 0Ohm V to V ENTER POSITIVE.

More information

Kendo-3 Workstation Block Diagram

Kendo-3 Workstation Block Diagram Feb. ' 0 RT Port Thermal ensor M 0 I / M us us witch I M us Keyboard Light.'' WUX+/ WX+ L RT LTION P connector isplay port to ocking UIO OMO Jack ual Link LV T H T O R RT isplay Port isplay Port et ombo

More information

A_SYNCOUT1_P A_SYNCOUT1_N A_SYNCOUT2_P A_SYNCOUT2_N A_SYNCOUT3_P A_SYNCOUT3_N

A_SYNCOUT1_P A_SYNCOUT1_N A_SYNCOUT2_P A_SYNCOUT2_N A_SYNCOUT3_P A_SYNCOUT3_N ate: //00 heet of File: :\User\..\MFO.choc rawn y: NIN_P NIN_N NOUT_P NOUT_N N_N N_P LE OLK_P OLK_N NTROUT_P NTROUT_N IN_P LK_P LK_N NV_P IN_N NV_N VO MFO.choc TK TI TO TK TI TO LK _IN ONE HWP INIT_ M

More information

Power supply, reset circuit, reference voltage and power indicator. Analogue and digital inputs with options for FET outputs

Power supply, reset circuit, reference voltage and power indicator. Analogue and digital inputs with options for FET outputs VR core and power 00v.0 Power supply, reset circuit, reference voltage and power indicator. Port 00v.0 nalogue and digital inputs with options for FET outputs Port 00v.0 igital inputs with optional FET

More information

Am186CC and Am186CH POTS Line Card

Am186CC and Am186CH POTS Line Card RVISION HISTORY RV. T INITILS.0 // JSK m and mh POTS Line ard Reference esign NOT: The purpose of this design is to illustrate how to connect some of the M digital blocks together. It is not intended to

More information

Generated by Foxit PDF Creator Foxit Software For evaluation only.

Generated by Foxit PDF Creator Foxit Software   For evaluation only. I_ST I_SLK K_% R K_% R L_0 L_ L_ L_ KEY TON_STHL /F NN_ NN_ P M VS OUTL P OUTR VR MIIN VREF V HOSI LOSI R X pf LOSO.KHZ M_% pf HOSO X pf MHz HOSI 0 pf POWER Generated by Foxit PF reator Foxit Software

More information

SHINAI-3 Switchable Graphics System Block Diagram

SHINAI-3 Switchable Graphics System Block Diagram Keyboard Light HINI- witchable raphics ystem lock iagram P Layer tackup L: TOP L: INL RT Port Thermal ensor M 0 I / M us us witch I." WX+ RT LTION P connector isplay port to ocking M us Touch creen 0 UIO

More information

PLAY0 CT7601 QFN48 REC ADC REC. Power LDO RCA RCA RCA*2. Ext. MCU RCA*2. SPDIF output. PWM LED x 2 POR. SPDIF input x 1 Flash. connector.

PLAY0 CT7601 QFN48 REC ADC REC. Power LDO RCA RCA RCA*2. Ext. MCU RCA*2. SPDIF output. PWM LED x 2 POR. SPDIF input x 1 Flash. connector. R SPIF output Power LO R SPIF input x Flash POR PWM LE x R* Lightning() P x pin Type connector US pin For Lightning & P T QFN RE PLY H Sel T PLY x PM Ext. MU H Sel T RE x S NE OP R* Size ocument

More information

RSC CHIP VDD P05 P03 P01 P04 VDD GND PWM0 AVDD VDD AVDD P0-2 P0-5 P0-1 P0-6 P0-4 P0.3 GND P00. Y1 3.58MHz P00 P01 AGND P01 P00 P02 P02 P07 P0-0 P0-7

RSC CHIP VDD P05 P03 P01 P04 VDD GND PWM0 AVDD VDD AVDD P0-2 P0-5 P0-1 P0-6 P0-4 P0.3 GND P00. Y1 3.58MHz P00 P01 AGND P01 P00 P02 P02 P07 P0-0 P0-7 Place as close to pins of U as possible. RS HIP 0-00 RS-x emo/evaluation oard: RS-000 Thursday, ecember, 00 Size ocument Number Rev ate: Sheet of P XI P0 P0 P0 P0 P00 PN P0 P0 P0 P0 P0 P0 P0 P0 P XO -XM

More information

Reference Schematic for LAN9252-HBI-Multiplexed Mode

Reference Schematic for LAN9252-HBI-Multiplexed Mode Reference Schematic for LN-HI-Multiplexed Mode onfigurations HI Multiplexed mode EEPROM - F (High) Port mode Port0 & Port = opper Page No. Schematic Page Title Power Supply LN(Part) LN(Part), Strap & EEPROM

More information

PCLKS SYNCHS PDATS[3:0] PCODES[3:0] STATCLKS CMDCLKS PCLKW SYNCHW PDATW[3:0] PCODEW[3:0] Sheet_2 CMDCLKS STATCLKW CMDDATW STATDATW PDACK[1:0]

PCLKS SYNCHS PDATS[3:0] PCODES[3:0] STATCLKS CMDCLKS PCLKW SYNCHW PDATW[3:0] PCODEW[3:0] Sheet_2 CMDCLKS STATCLKW CMDDATW STATDATW PDACK[1:0] STTTW STTLKW POW[:0] PTW[:0] SYNHW PLKW Sheet_ STTTS STTLKS POS[:0] PTS[:0] SYNHS PLKS Sheet_ Spareates PLKS SYNHS PTS[:0] POS[:0] STTLKS STTTS MLKS MTS Sheet_ PLKW PLKS SYNHW SYNHS PTW[:0] PTS[:0] POW[:0]

More information

MOL NM UR PM NUMR L RVON LVL T RWN K PPROV NOT P RVON T NUMR of -N TLP P0 K 0 0K R TLP P0 Z Z0WVX KTN Q U00 0 K KMZ Z R 0 0K 0 0 R K R N00 0 0K 0 K U00 0 K 0 KJ R U00 0 0.ohm R0 W -N Max.0KOM RX0 Min./W

More information

B0549-SCH-01 RD VEGA STDP4028 (DVI to DPTx) Reference Design PCB# Revision History

B0549-SCH-01 RD VEGA STDP4028 (DVI to DPTx) Reference Design PCB# Revision History 0-SH-0 R-0 VEG STP0 (VI to PTx) Reference esign P# 00- Revision History SHEMTI SHEET ate uthor Version omments 0. ontents, Revision History Sept., 00 Tony W. Rev. Initial schematic. 0. Overview Oct., 00

More information

T53S Main BD. R1.2 Block Diagram

T53S Main BD. R1.2 Block Diagram T Main. R. lock iagram LV PE Merom PU LV / ULV PE, F F 00/ MHz LOK EN. ILPRLF-T PE FN Thermal sensor PE 0 RT HMI PE PE M Nvidia NP- M PE 0,,,,,, PE udio L PE,, 0 F PI-E X zalia LP restline PM PE 0,,,,,

More information

H-LCD700 Service Manual

H-LCD700 Service Manual H-L00 Service Manual FULT ESIPTION: SOUN onfirm the volume isn t in silent mode before check. heck I0 () plug has audio output or not Speaker damaged heck I0 has supply V or not heck power heck I0 () plug

More information

SA CH SEGMENT /COMMON DRIVER FOR DOT MATRIX LCD

SA CH SEGMENT /COMMON DRIVER FOR DOT MATRIX LCD A06 A06 0 H EGMENT /OMMON RIVER FOR OT MATRIX L Ver. July, 000 A06 INTROUTION The A06 is an L driver LI which is fabricated by low power MO high voltage process technology. In segment driver mode, it can

More information

DAC PLAY0 PLAY0 CT7601 DAC REC ADC REC RCA * 2. Power LDO RCA. RCA * 2 SPDIF output x2 RCA RCA RCA. Ext. MCU POR. PWM LED x 2. SPDIF input x 1.

DAC PLAY0 PLAY0 CT7601 DAC REC ADC REC RCA * 2. Power LDO RCA. RCA * 2 SPDIF output x2 RCA RCA RCA. Ext. MCU POR. PWM LED x 2. SPDIF input x 1. R * SPIF output x Power LO R * R R SPIF input x POR Flash PWM LE x PM00 Lightning() P 0x0 0pin Type connector US 0pin For Lightning & P T0 RE PLY0 PLY H Sel Stereo T0 PLY0 T0 0x PLY 0x PM00 R Ext. MU H

More information

FOXCONN Title Index Page

FOXCONN Title Index Page Page 0 0 0 0 0 0 0 0 0 0 0 0 0 of chematics Page chematics Page Index lock iagram LOK N (K0) MROM(HOT U) / MROM(HOT U) / MROM(Power/nd) / restline (HOT) / restline (MI) / restline (RPHI) / restline (RII)

More information

JS3 VDDA PTA7/KBD7. Jmp VSSA PTA6/KBD6 PTA5/KBD5 PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 33 FP-1 PTA0/KBD0 VSSAD PTC3 VDDAD

JS3 VDDA PTA7/KBD7. Jmp VSSA PTA6/KBD6 PTA5/KBD5 PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 33 FP-1 PTA0/KBD0 VSSAD PTC3 VDDAD fb_inj fb_inj JS0 JS JS U JS Vsyn JS V PT/K 0 VSS PT/K GMXF- GMXF PT/K OS- JS OS PT/K OS- OS PT/K Squirt- RST PT/K ccel- PT0 PT/K Idle- JS Warmup- PT PT0/K0 FP- PT VSS 0 PT V TX- PT PT/ 0 JS JS0 RX- PT0/Tx

More information

Reference Schematic for LAN9252-SPI/SQI+GPIO16 Mode

Reference Schematic for LAN9252-SPI/SQI+GPIO16 Mode Reference Schematic for LN-SPI/SQI+GPIO Mode onfigurations SPI/SQI+GPIO Mode EEPROM - F (High) Port mode Port0 & Port = opper Page No. Schematic Page Title Power Supply LN(Part) LN(Part), Strap & EEPROM

More information

+12V R17 100K +12V R18 100K R19 100K R20 100K AVPP BVPP. C21 0.1uF. C20 0.1uF NOTES:

+12V R17 100K +12V R18 100K R19 100K R20 100K AVPP BVPP. C21 0.1uF. C20 0.1uF NOTES: +V +V R 00K U S S G G SI.V +V V _VPPEN _VPPEN0 _VEN _VEN0 _VPPEN _VPPEN0 _VEN _VEN0 R 00K R 00K + 0uF _VPPEN _VPPEN0 _VEN _VEN0 _VPPEN _VPPEN0 _VEN _VEN0 V U VIN VPPIN VPP0 VPP V0 V VPP0 VPP V0 V SHN 0

More information

Quickfilter Development Board, QF4A512 - DK

Quickfilter Development Board, QF4A512 - DK Quickfilter evelopment oard, QF - K nalog Inputs - U +.V +.V J N hannel J N hannel J N hannel J N hannel U +.V +.V U +.V U +.V Prototyping rea J J Optional +V External Power x Header 0." US onnector U

More information

Service Information. Service. Service. Service FW-V220. Product Service Group CE Audio A02-160

Service Information. Service. Service. Service FW-V220. Product Service Group CE Audio A02-160 Service Service Service W-V0 0-0 Product Service Group udio Service Information lready published Service Informations: ORRTION TO SRVI MNUL elow are corrections to the circuit diagram parts list: OMI OR

More information

AS1117M3 or LM1117MPX-ADJ REG_VDD ADJ. C20 0.1uF U6. + C57 10uF R K 1% GND 3.92K 1%

AS1117M3 or LM1117MPX-ADJ REG_VDD ADJ. C20 0.1uF U6. + C57 10uF R K 1% GND 3.92K 1% K POWER SW JP EXTERNL POWER FUSE 0. uf VT + 0 uf SM or LMMPX-J REG_V VIN VOUT + 0uF 0 0.uF U R 0.0K % J R.K % REG_V J PV PV_US_TGT V_M0X POWER_SELET R0 0Ohm V to V ENTER POSITIVE.

More information

Colby College Catalogue

Colby College Catalogue Colby College Digital Commons @ Colby Colby Catalogues College Archives: Colbiana Collection 1866 Colby College Catalogue 1866-1867 Colby College Follow this and additional works at: http://digitalcommons.colby.edu/catalogs

More information