PCI9054RDK-860 BLOCK DIAGRAM

Transcription

1 N HISTORY N NUMR T NOT xxx-xxx 0/0/. M signals added: R0, R, R, and R to include VFLS[:0] and FRZ to the M connector.. dded pull up to and : R, R, R, R, U, and U0. xxx-xxx 0//. SRM: added R MUX(U,U,U): hanged M[0:] to SRM, dded R and R for and. hanged W#(GPL_#).. FLSH: dded.v or V(V) PS Option. hanged W#(S_0#).. SRM: added IP# signal to the glue.. Power UP config: added,,0 (U,U,U) for the power up configurations.. hanged the PU/P (R)s for the Power Up onfigurations.. dded PU/P (R)s for the MP0 JTG Port. xxx-xxx 0/0/ dded R & R (Wait control input to UPM) xxx-xxx 0/0/. Removed SRM: Lattice and SRMs.. hanged R to K (I/O pull down R).. dded Pull-Up Resistor(0 ohm) for #.. dded Pull-own Resistor for TK and TRST#(K ohm).. Fixed SRM address MUX unit. xxx-xxx 0//. TSIZ0 (pin ) and TSIZ (pin ) were swapped. PI0RK-0 LOK IGRM xxx-xxx //0. orrect pull-up resistor at U-. It was R, now is R. Update OM to reflect P board Rev , and ocument Number NOT: (otherwise specified). ll resistors are I case style 00, % tolerance.. ll.uf caps are I case style 00, 0% tolerance.. ll resistors are 0 type and less than 0.0 ohms MP0 Peripherals PG ( indicates default, do not install other) SRM (M) PG MP0 PG FLSH (K) PG SRIL PORT PG LOL US PI0 PG PI US PLX THNOLOGY 0 Maude ve, Sunnyvale, 0 LOK IGRM Size ocument Number Rev ustom ate: Sheet of

2 .V U PI 0 (PQFP).V.V,,,,0 [0:] [:0],0 RN RN L0 0 0 L L L J-XX J-XX L L.V.V L RN RN L 0 L 0 L 0 0 L0 0 0 L L J-XX J-XX L L.V.V L RN RN L PI Signals L L 0 0 L L0 0 0 L J-XX J-XX L 0 L 0.V.V L 0 RN RN L 0 L 00 L 0 L L 0 0 L J-XX J-XX L,,,0 [0:] /0# /0#,0 0 PI Signals /# /#,0 0 /# /#,0 L /# /#,0 L0 L FRM# FRM#,0 L IRY# IRY#,0 L PI Signals TRY# TRY#,0.V L STOP# STOP#,0 0 RN L VSL# VSL#,0 PU0 L PRR# PRR#,0 PU0 L SRR# SRR#,0 PU0 0 L PU0 L LOK# LOK#,0 L0 PR PR#,0.V J-XX L RQ# RQ#,0 L PI Signals INT# INT#,0 R0K.V L PM# PM#,0 NUM# RN0 L NUM# PU0 L Lon/Lin PU0 L Lon/Lin PU0 L R 0K PU0 0 L P0 P0,,0 L P P,, J-XX L0 P P,,0 Lon/Lin 0 0 L P P,,0 NUM# 0.V L RN L PU0 PU0 L TS#/S# TS#,,0 PU0 PU L URST#/LST# URST#,,0 0 PU L R/WR# R/WR#,,0 PU0 PU L T#/RY# T#,,0 PU0 L IP#/WITi# IP#,, J-XX PU.V 0 L0/L0# R#/LHOL R#,,0 PU0 RN L/L# LINTi#/LINTo# LINT#,,0 PU0,,0 TSIZ PU TSIZ/L# LRSTo# LRSTO#,0 PU0,,0 TSIZ0 TSIZ0/L# USRi/K0#/LLOKi# LLOKI#,0 PU0 PU T#/LSRR# T#,,0 PU.V,,0 LLK MO LLK MRQ# J-XX 0 MO MO0 MO MRQ#/MPF/OT# P,,,,0 PU0 0 MO0 MO0 IGN#/WIT# IGN#,0 PU,0 TST PU TST USRo/RQ0#/LLOKo# USRO,,0 PU,,0 G# PU G#/LHOL I#/TRM# I#,,0 0 R R,,0 S0# S# #/RQi PU #,,0 0K 0K RTRY#/RQo RTRY#,,0.V.V,0 LK 0 U PLK S,0 RST# RST# PI Signals S SK S V,0 GNT# GNT# SK O I SK PR,0 ISL ISL I/O I P.V # O GN R L (IP-Socket) R0.K R.V.K K 0.uF J R 0K O 0 R K SK 0.V S 0 R K X PIN HR R 0K R0 K.V TO PI0 POWR PINS PROM present : install R, not install R R0K PROM not present : install R, not install R MO: [MO:MO0] = ; M-MO V V V V V V V V V V V V V V V 0 0 Normal operation: J:- open J:- open J:- open 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0 0.uF 0.uF PLX THNOLOGY 0 Maude ve, Sunnyvale, 0 PI 0 Size ocument Number Rev ustom ate: Sheet of

3 JTG Port S PG FOR YPSS PS evelopment Port MP0 PLX THNOLOGY 0 Maude ve, Sunnyvale, 0 ustom Size ocument Number Rev ate: Sheet of P P IP_ P R0 P P IP_ SI P P0 P 0 P P P IP_ P SO P R P P P P P R P TX IP_ 0 P P0 P P P IP_ P 0 P0 P P P P P SK TI IP_ P P P P P0 P 0 0 P MRQ# P RTS# 0 P 0 TRST# TO IP_ P TS# P0 P P P RX P TK P XTL IP_ IP_ P P IP_ 0 P XTL IP_0 IP_ P P IP_ IP_ P P P0 # P P XTLK IP_ P IP_0 P XF VSYN TK TRST# TO VSYN XF XTLK XTL XTL GN SRST# GN.V HRST# SI SO SK FRZ IP_0 FRZ IP_.V.V.V.V.V R 0K J R 0K U MP0 M M K W W W W0 W W W W U T V U T V V0 T0 U0 T V U V U T U V T U V V W U T R R R R P F F P R R0 R R R R R F G H J K L N M L K J H G F 0 M N P T P W M H F F F F F0 F F F F G G G G G0 G G G G H H H H H0 H H H H J J J J J0 J J J J K K K K K0 K K K K L L L L L0 L L L L M M M M M0 M M M M N N N N N0 N N N N P P P P P0 P P P P U T R P P N M M L K J G F U R N P N N L K L K J J F P N T W N R T U V H J J G G J K H J R W U U V T W V W T R V V U H V H G F F L H K F V V W V G V U W R P N P N L L M L G H H G G T T U W U U T T K R T T R M M L K J F R R R VH VH VH VH VH VH VH VH VH VH VH VH VH VH VH VH VH VH VH VH VH VH VH VH VH VH VH VH VH VH VH VH VH VH VH VH VH VH VH VH VH VH VH VH VH VL VL VL VL GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN LK/TOUT/LTLK/P0 LK/TIN/RGO/P LK/TOUT/LRLK/RGLK/P LK/TIN/RGOUT/P LK/TOUT/P LK/TIN/LTLK/RGOUT/P LK/TOUT/RGLK/P LK/TIN/LRLK/RGO/P LRX/P LTX/P LRX/P0 LTX/P TX/P RX/P TX/P RX/P RSTRT/P RGO/P LRQ/LST/P LRQ/LST/P RTS/LST/P RTS/LST/P SMRX/LLKO/P0 SMTX/LLKO/P SMSYN/SK/P SMSYN/SK/P P/SMRX P/SMTX P/ISL/RGO P/IS/RGO SPIMISO/RGO/P SPIMOSI/P SPILK/P0 SPISL/RJT/P XTL XTL XF LKOUT XTLK KPWR VSYN SYN SYN IP_0/IWP0/VFLS0 IP_/IWP/VFLS IP_/IOIS_/T IP_/IWP/VF IP_/LWP0/VF0 IP_/LWP/VF IP_/SI/T0 IP_/PTR/T L_/SK/T WIT_ P/RJT {TX[]} P/RJT {TX[]} P/RJT {TX[]} P/RTS {RX_V} P/RTS {RX_R} P/TX {RX_LK} P/RX {TX[0]} P0/TX {RX[0]} P/RX {TX_R} P/LSYN {M} P/LTSYN {RX[]} P/LRSYN {RX[]} P/LTSYN {RX[]} SPR {RS} SPR {MIO} SPR {TX_N} SPR {OL} R G TSIZ0/RG TSIZ R/WR URST I IP/GPL_ TS T T S RSV/IRQ KR/RTRY/IRQ/SPKROUT R/IRQ P0/IRQ P/IRQ P/IRQ P/IRQ FRZ/IRQ IRQ0 IRQ IRQ {TX_N} W0/S_0/IOR W/S_/IOWR W/S_/PO W/S_/PW S_0 S_ S_ S_ S/() S/() S S S S S S0 GPL_0/GPL_0 O/GPL_/GPL_ GPL_/GPL_/ GPL_/GPL_/ UPWIT/GPL_ UPWIT/GPL_ GPL_ PORST RSTONF HRST SRST TXP OP0 OP OP/MOK/SO OP/MOK/STS TI/SI TK/SK TRST TO/SO IP_0 IP_ IP_/OIS_ IP_ IP_ IP_ IP_ IP _ L_ WIT_ P//LRSYN P/TS/LTSYN/SK P//LRSYN P/TS/LTSYN/SK P//TGT P/TS P0//TGT P/TS P/LRQ/LST P/LRQ/LST P/RQ/RTS/LST P/RQ0/RTS/LST L.mH 0uF pf 0.uF 0.uF 0.uF U MHZ OS N GN OUT V R J X PIN HR 0 R R0 R K R K R 0.uF [0:],,,,0 [0:],,,0 R[:0],0 LKOUT IP_[:0],,0 P[:],,,,0 P[:0],,0 P[:],,0 P[:],,0 IP_[:0],0 RTRY#,,0 IRQ#,,0 P,,0 P,,0 _#,0 R/WR#,,0 T#,,0 S_#,,,0 URST#,,0 T#,,0 S_#,,0 S_#,,,0 TSIZ0,,0 S_#,,0 HRST#,,0 MOK,,0 G#,,0 GPL_#,,,,0 GPL_#,,,0 POR#,,0 TXP,,0 IRQ#,,0 S0#,,0 SSRM#,,,0 GPL_#,,,,0 OP,,0 L_,,0 IRQ0#,,0 S#,,0 P0,,0 S#,,0 GPL_#,,,0 L_,0 IP#,,0 IRQ#,,0 P,,0 TS#,,0 TSIZ,,0 I#,,0 S#,0 S_0#,,,0 S_#,,,0 _#,0 S_0#,,,0 S_#,,0 #,,0 GPL_#,,,,0 RSTONF#,0 SRST#,,0 OP0,,0 S#,0 SFLSH#,,,0 GPL_0#,,,,0 GPL_#,,,,0 MOK,,0 R#,,0 FRZ,0 LINT#,,0 S#,,0 S#,,0 WIT_#,,0 WIT_#,0 TI,0 TK 0,0 TO 0 TRST# 0 VSYN 0 XF 0 XTLK 0 XTL 0 XTL 0

4 PIN PL SOKT LOK UFFRS PL TRMINTORS T TR N MNUFTURING OPTION (O NOT INSTLL) SRM LOK NL/ISL These Resistors are not required SRM PLX THNOLOGY 0 Maude ve, Sunnyvale, 0 ustom Size ocument Number Rev ate: Sheet of P W# RS0# S0# QM0 QM QM QM 0 0 GPL_# K SRM_LK W# S0# RS0# SSRM# QM K SRM_LK QM W# S0# RS0# SSRM# K SRM_LK QM W# S0# RS0# SSRM# K SRM_LK QM0 W# S0# RS0# SSRM# SSRM# [0:] [0:] LLK SRM_LK POM_LK SRM_LK SRM_LK SPR_LK SPR_LK M M M M0/P M M M M M M0 M P 0 0 M M[:0] M M M0 M M M M M M M M M M M M M[:0] M M M M0/P M M M M M M M M M M0 M M M M0/P M M M M M M M M M M0 M M M M0/P M M M M M M M M M M0 K M0/P SRM_LK.V V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V U KS0-T0 TSOP SRM (MXITXNK) Q0 Q Q Q Q Q Q Q 0 S# RS# S# W# QMH(QM) LK K V0 V V VQ0 VQ VQ VQ 0 Q0 Q Q Q N0 N N N N N N N N N QML U KS0-T0 TSOP SRM (MXITXNK) Q0 Q Q Q Q Q Q Q 0 S# RS# S# W# QMH(QM) LK K V0 V V VQ0 VQ VQ VQ 0 Q0 Q Q Q N0 N N N N N N N N N QML U KS0-T0 TSOP SRM (MXITXNK) Q0 Q Q Q Q Q Q Q 0 S# RS# S# W# QMH(QM) LK K V0 V V VQ0 VQ VQ VQ 0 Q0 Q Q Q N0 N N N N N N N N N QML U KS0-T0 TSOP SRM (MXITXNK) Q0 Q Q Q Q Q Q Q 0 S# RS# S# W# QMH(QM) LK K V0 V V VQ0 VQ VQ VQ 0 Q0 Q Q Q N0 N N N N N N N N N QML R R R R R R R R R R0 R R U Y0 LK LK LK LK LKOUT V GN RF R R 0 pf R0 pf R pf R 0pF R R R R U LXMT 0 G / Y Y Y Y V GN U LXMT 0 G / Y Y Y Y V GN U LXMT 0 G / Y Y Y Y V GN R R R pf pf 0.uF 0.uF 0 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.0uF 0.uF U0 MLV00-0NS O W I/O0 I/O I/O I/O I/O I/O I/O I/O V GN 0 0 [0:],,,,0 SFLSH#,,,0 S_0#,,,0 S_#,,,0 S_#,,,0 S_#,,,0 GPL_#,,,,0 GPL_#,,,,0 GPL_#,,,,0 SSRM#,,,0 GPL_0#,,,,0 S_0#,,,0 LLK,,0 POM_LK LKOUT [0:],,,0 GPL_#,,,,0,,,0,,,0 K 0

5 .V.V RN,,0 P[:0] RN P0 P.V,,0 S# Power Up onfiguration P RN,,0 S#,,,,0 P[:] P P,,0 S# P,,0 S# J-XX P OS (f) MOK MOK J-XX P.V Mhz OS.V RN J-XX RN P P.V Mhz OS 0,,,0 SSRM# P RN,,,0 SFLSH# P P,,0 HRST# P,,0 SRST#.V J-XX P J-XX P.V.V.V R 0K RN J-XX R K RN P P.V,,0 IRQ0# U P0 RN R0 0K,,0 IRQ# P P Rk,,0 IRQ# MOK P MOK,,0 IRQ# J-XX P R 0K J-XX P,,,,0 R K.V,,,,0.V RN J-XX,,,,0 R0 0K RN P,,,,0 0 RK P,,,,0,,,0 S_0# P TX,,,,0 R 0K P RX HRST# R K,,0 S_#,,0 S_#.V G,,0 S_# R J-XX RN0 T/R# 0K,,0 P[:] R K J-XX P LXMT.V P R 0K.V RN P,,0 P[:] RN P P R K P,,,0 S_0# R 0K P J-XX,,,0 S_# P R K,,,0 S_#.V,,,0 S_# J-XX RN J-XX P.V P.V RN P RN P P0 P,,,,0 GPL_0# P J-XX,,,,0 GPL_# P,,,,0 GPL_#.V,,,,0 GPL_# J-XX RN J-XX P.V P.V RN P Indicator Ls RN P P P,,,0 GPL_# P J-XX,,,0 GPL_# P,,,,0 GPL_#.V J-XX RN J-XX P.V.V.V U.V RN RN P P,,0 USRO N# V,0 S# P J-XX,,0 MOK P R,,0 MOK,0 TI J-XX.V GN J-XX RN,0 IP_[:0].V IP_0 GRN_L RN0 IP_ NSZP P0 IP_ P IP_ U RN J-XX FRZ,,0 TXP.V N# V J-XX,,0 OP0 RN,,0 OP IP_,0 RSTONF# IP_ J-XX IP_ GN IP_ 0 V GN 0 NSZP U N# V GN NSZP R 0K R R_L,0 WIT_#,,0 WIT_#,0 _#,0 _#,,0 L_,0 L_,0 FRZ,0 RN J-XX RN J-XX.V,,0 IP_[:0] IP_0 IP_ IP_ IP_ IP_ IP_ IP_ IP_ J-XX RN J-XX RN J-XX.V.V Wait ontrol Input to UPM T# R K GPL_# R K GPL_# RST PLX THNOLOGY 0 Maude ve, Sunnyvale, 0 Size ocument Number Rev ustom ate: Sheet of

6 PI dge onnector LK,0 T VI/O -V VPI V J VPI V VI/O V -V TRST# TP TK V GN TO TI V V V INT# INT#,0 INT# INT# TP INT# V TP PRSNT# RSRV TP TP 0 0 RSRV VIO TP TP PRSNT# RSRV RSRV.Vaux,0 RQ# GN RST# RST#,0 LK VIO,0 [:0] GN GNT# GNT#,0 RQ# GN VIO PM# PM#,0 0 0 TP 0 0.V TP GN GN,0 /#.V /# ISL.V ISL,0 GN GN 0.V,0 /# /#.V GN FRM# FRM#,0,0 IRY# IRY# GN.V TRY# TRY#,0,0 VSL# VSL# GN GN STOP# STOP#,0,0 LOK# LOK#.V,0 PRR# 0 PRR# Reserved 0.V Reserved,0 SRR# SRR# GN,0 /#.V PR PR#,0 /#.V GN 0 0 GN GN V 0.V GN VIO K# V V /0#.V GN 0 VIO RQ# V V 0 V 0 /0#,0 PIONUNV Note: This connector is keyed for both.v and V PI I/O Local us Power Source ach power supply group pins must be tied together and have bypass capacitors (V, V,-V, and.v). V U LTM VIN VOUT R VPI Vout =.V().V V ach power group has.uf and 0uF caps. 0uF J R % R % R R & R must be less than 0.0 ohm (R) 0.uF 0uF 0uF VPI 0.uF 0uF V VI/O V -V 0.uF 0uF 0.uF 0uF 0.uF 0uF 0.uF U option:. If LTM (adjustable) is used, install R and R (default).. If LTM-. is used, do not install R and replace R with a jumper. Local us.v is selectable at manufacturing (R or R): Populate R if using.v supply from the PI connector Populate R if using.v supply from the Voltage regulator (default) PLX THNOLOGY 0 Maude ve, Sunnyvale, 0 PI dge onnector Size ocument Number Rev ustom ate: Sheet of

7 .V V Two groups of power supply to the POM (PLX Option Module):.V V R R install correct R R resistors for required power. V_G.V MP0 YPSS PS. TO POWR ONNTOR PINS 0 0.uF 0uF 0uF 0.uF V_G 0 0.uF 0.0uF 0.uF 0.0uF 0.uF 0.0uF 0.uF 0.0uF,,,0 GPL_# J POM,,,0 GPL_# P[:],,,,0,,,,0 GPL_# P GPL_# P P P P POM_LK LK P SK# P P P GPL_# P P 0.uF 0.0uF 0.uF 0.0uF 0.uF 0.0uF 0.uF 0.0uF,,0 P[0:] GPL_# P # P0 SPR P0 TS# P P0 IGN# P P USRIN P0 V_ 0 P P P P 0 P P P P MRQ# P P P P RTS# P[:],,0 P P P P P P P P P P P P.V P P P P P P Reset ircuitry P P V_ P P0 P P 0 P.V P P0 P 0 P P P P0 P0 P P V_ P P R 0.uF P P P P 0K R P TX P P P U0 0K P RX P P P SW P P IP_[:0],,0 IP_0 SPR IP_0 IP_ MR# V P SPR IP_ 0 0 IP_ SW PUSHUTTON P P IP_ IP_ RST# POR#,,0 P IP_ IP_ P IP_,0 LRSTO# RST_IN GN P P V_ IP_ P P IP_ IP_ MX0UK0-T P P IP_ IP_ P0 P IP_ P P0 L_ L_,,0 P P WIT_# WIT_#,,0 P P TXP TXP,,0 0 P OP 0 OP,,0 P OP0 OP0,,0 P P P P V_ P P GPL_0# GPL_0#,,,,0 P P GPL_# GPL_#,,,,0 P P P0 P GPL_# GPL_#,,,,0 P P0 GPL_# GPL_#,,,,0 P V V -V 00 -V,,0 P[:] Serial Port.V 0uF 0.uF R 0K U V FOROFF# FORON V 0 00nF - R 0K V- 00nF 00nF P 00nF R 0K GN - TS TX TIN TOUT 0 TX,,0 P RTS# TIN TOUT RTS,,0 P TIN TOUT RX 0 TS# ROUT INVLI#,,0 P RX ROUT RIN,,0 P # ROUT RIN,,0 P0 ROUT RIN R 0K ONN -ML ROUT RIN ROUT RIN R 0K MX PLX THNOLOGY 0 Maude ve, Sunnyvale, 0 LOK IGRM Size ocument Number Rev ustom ate: Sheet of

8 Note: Place the PL devices co-incident on the board; that is, they share common pins and the 0 fits inside the which fits inside the. Prototyping Footprints LOK IGRM PLX THNOLOGY 0 Maude ve, Sunnyvale, 0 ustom Size ocument Number Rev ate: Sheet of FP Pin TQFP Footprint FP 0 Pin PL Footprint FP Pin PL Footprint FP Pin PL Footprint FP Pin TQFP Footprint FP 0 Pin SOI Footprint FP 0 Pin SOI Footprint J X PIN HR J X PIN HR FP Pin SOI Footprint 0 0 FP Pin SOI Footprint 0 0 [0:],,,0 [0:],,,,0 IRQ#,,0 TS#,,0 T#,,0 R/WR#,,0 URST#,,0 IP#,,0 RTRY#,,0 T#,,0 TST,0 POR#,,0 R#,,0 LLK,,0 G#,,0 #,,0 I#,,0 TSIZ,,0 LLOKI#,0 USRO,,0 TSIZ0,,0 P,,,,0 S_#,,0 S_#,,0 S_0#,,,0 S_#,,0 GPL_#,,,,0 GPL_#,,,,0 GPL_0#,,,,0 GPL_#,,,,0 S_#,,,0 S_#,,,0 S_#,,,0 S_0#,,,0 IRQ#,,0 SFLSH#,,,0 S0#,,0 SSRM#,,,0 S#,,0 S#,,0 S#,,0 S#,,0 GPL_#,,,0 GPL_#,,,,0 GPL_#,,,0 IGN#,0 R,0 R0,0 R,0 IRQ#,,0 IRQ0#,,0 LINT#,,0 P0,,0 P,,0 P,,0 P,,0 MOK,,0 SRST#,,0 MOK,,0 HRST#,,0 S#,0

9 VI PLX THNOLOGY 0 Maude ve, Sunnyvale, 0 ustom 0 Size ocument Number Rev ate: Sheet of R R R P P P P P P P P P P0 P P P P P P0 P P P P IP_ IP_ IP_ IP_ IP_0 IP_ IP_ IP_ IP_ IP_0 IP_ IP_ IP_ IP_ IP_ IP_ P P P P0 P P P P P P0 P P P P P P P P0 P P P P P P P P P P P P P P P0 P P P P P P TP0 VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP0 VI TP VI TP VI TP00 VI TP VI TP0 VI TP0 VI TP0 VI TP0 VI TP VI TP0 VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP0 VI TP0 VI TP0 VI TP0 VI TP VI TP VI TP0 VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP0 VI TP VI TP0 VI TP0 VI TP VI TP0 VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP0 VI TP0 VI TP VI TP VI TP VI TP VI TP VI TP0 VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP0 VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP0 VI TP0 VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP0 VI TP0 VI TP VI TP VI TP0 VI TP VI TP0 VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP0 VI TP0 VI TP VI TP VI TP VI TP VI TP0 VI TP VI TP VI TP0 VI TP VI TP VI TP VI TP0 VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP0 VI TP VI TP VI TP VI TP0 VI TP VI TP VI TP VI TP VI TP VI TP0 VI TP VI TP0 VI TP VI TP00 VI TP VI TP VI TP0 VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP0 VI TP VI TP0 VI TP VI TP VI TP VI TP VI TP0 VI TP VI TP VI TP VI TP VI TP VI TP0 VI TP VI TP VI TP VI TP0 VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP0 VI TP0 VI TP VI TP VI TP VI TP VI TP VI TP VI TP VI TP0 VI TP VI TP00 VI TP VI TP0 VI TP VI TP VI TP VI TP VI [:0], /0#, /#, /#, /#, TRY#, IRY#, STOP#, FRM#, VSL#, SRR#, PRR#, LOK#, PR#, RQ#, INT#, PM#, NUM# HRST#,, SRST#,, TK POR#,,, RSTONF#, WIT_#,, R[:0], [0:],,,, P[:0],, P[:],, P[:],, P[:],,,, IP_[:0],, IP_[:0], K TRST# S#,, S#,, S#,, TI, S#,, TO S#, SSRM#,,, SFLSH#,,, XF _#, _#, XTL VSYN XTL XTLK L_, WIT_#, L_,, IRQ#,, IRQ#,, S_0#,,, FRZ, S#, IRQ0#,, IRQ#,, S_#,, S_#,, S_#,, S_#,,, S_0#,,, S_#,,, GPL_0#,,,, GPL_#,,,, S_#,,, GPL_#,,, GPL_#,,, GPL_#,,,, GPL_#,,,, GPL_#,,,, MOK,, OP0,, OP,, TXP,, MOK,, URST#,, LINT#,, T#,, TS#,, IP#,, R/WR#,, LRSTO#, LLOKI#, T#,, IGN#, R#,, USRO,, #,, RTRY#,, P,,,, I#,, SK LLK,, MO0 S O MO TST, G#,, Lon/Lin TSIZ0,, S0#,, P,, P,, TSIZ,, P,, P0,, LK, RST#, GNT#, ISL, [0:],,,

10 RST R/T US TST ONNTOR ONTROL SIGNL ONNTOR FLSH SRM.V Prototype rea URT MP0 GN POWR SUPPLY PI0 V MP0 Peripheral onnector Universal PI onnector (.V/V) Misc Parts G L P P PNL Static ag RS able L LV00 P racket SRW SRW Panel Screws Panel Screws PLX THNOLOGY 0 Maude ve, Sunnyvale, 0 LYOUT Size ocument Number Rev ustom ate: Sheet of