power_block GND 3.3V 5V Data_dram d_cs* d_we* d_cas* d_dqm d_data[31:0] d_addr[11:0] Control_dram c_dqm c_data[31:0] c_addr[9:0] c_ras*

Transcription

1 Test Points e_cs e_clk e_di e_do endev* limit PRT OF configuration d_addr[:0] c_data[:0] d_data[:0] power_block d_data[:0] d_addr[:0] rmii_clk_phy rmii_clk_phy GN rmii_clk_hertz ach part has additional fields: ssyopt and ssyopt If ssyopt== then this part should be assembled when using the PHY as the L drivers If ssyopt== then this part should be assembled when using the GT0 with the PL as the L driver Parts with ssyoptx==0 are not assembled When OM is generated, ass {ssyopt} or {ssyopt} to the field list a '0' or '' the the right of each part will tell if this part should be assembled rxd0[:0] txd0[:0] rxd0[:0] ata_dram txd0[:0] main_clk main_clk rst* rxd[:0] rst* d_cs* txd[:0] rxd[:0] d_we* txd[:0] GN d_ras* GN d_cas* d_qm d_data[:0] d_dramclk d_dramclk RS_dv[:0] txen[:0] RS_dv[:0] txen[:0] RX_R[:0] c_cs* c_we* c_ras* c_cas* MII_interface c_qm c_dramclk c_cs* c_data[:0] c_dramclk c_we* c_addr[:0] c_ras* c_cas* Glink_interface c_qm gtxclk txen[:0] c_data[:0] txen[:0] txen[:0] c_data[:0] c_addr[:0] gtxd[:0] c_addr[:0] gtxcmd RX_R[:0] grxclk RX_R[:0] GT0_main_block gtxd[:0] GN gtxd[:0] gtxcmd grxd[:0] GN gtxcmd grxcmd grx_clk RS_dv[:0] grx_clk grxd[:0] main_clk TMS RS_dv[:0] RS_dv[:0] grxd[:0] grxcmd TMS TK grxcmd TK TRST* txd0[:0] H_tdi H_tdi TRST* txd0[:0] txd[:0] txd0[:0] H_tdi H_tdo H_tdo txd[:0] txd[:0] txd[:0] H_tdo TRST* txd[:0] txd[:0] txd[:0] TRST* TK txd[:0] txd[:0] txd[:0] TK TMS led_controller txd[:0] txd[:0] txd[:0] TMS R txd[:0] txd[:0] txd[:0] led_data rst* txd[:0] txd[:0] txd[:0] led_data led_stb led_data rst* txd[:0] txd[:0] led_stb led_clk led_stb 0R rxd[:0] led_clk led_clk ssemble this resistor when the PL rxd[:0] rxd[:0] rxd[:0] L0P[:0] rxd[:0] rxd[:0] L0P[:0] is not asssembled rxd[:0] LNK[:0] rxd[:0] rxd[:0] rxd[:0] LNK[:0] rxd[:0] rxd[:0] rxd[:0] rst* rxd[:0] rxd[:0] rxd[:0] rst* rxd[:0] rxd[:0] rxd[:0] rxd[:0] rxd[:0] misc_interface rxd0[:0] rxd0[:0] rxd0[:0] main_clk gtxclk H_main_clk main_clk gtxclk c_dramclk H_main_clk H_main_clk c_dramclk c_dramclk rmii_clk_phy rmii_clk_hertz c_dramclk d_dramclk d_dramclk d_dramclk rmii_clk_phy H_clk_ d_dramclk H_clk_ H_clk_ L0P[:0] LNK[:0] L0P[:0] LNK[:0] e_cs e_clk e_di e_do endev* limit d_cs* d_we* d_ras* d_cas* d_qm d_data[:0] d_addr[:0] d_addr[:0] rmii_clk_phy rmii_clk_phy ontrol_dram GN rmii_clk_hertz PRT OF GN GN GT0_bga_power esigned by ompulab Ltd rmii_clk_hertz rmii_clk_phy rmii_clk_phy GT0 RMII V with M NetPHY-LP Size ocument Number Rev MIN 0 ate: Monday, ugust 0, Sheet of

2 terminations should be placed as close to pins as possible (all ohm) Place lose to the end of onductor PRT OF GT0 GT0 RMII V with M NetPHY-LP Monday, ugust 0, Size ocument Number Rev ate: Sheet of gtxcmd txd0 txd txd0 txd0 txd00 txd0 txd txd txd0 txd txd0 txd gtxd gtxd gtxd gtxd gtxd gtxd gtxd gtxd gtxd[:0] gtxd gtxd gtxd0 gtxd0 gtxd gtxd gtxd gtxd txd0 txd grxd[:0] RS_dv rxd rxd00 c_addr c_data c_data c_data grxd grxd grxd d_we* d_addr0 d_addr d_data c_addr c_data0 c_data H_tdi rxd d_data d_data d_data d_data c_addr c_data c_data c_data rxd0 d_addr c_data0 c_data c_data c_data c_data grxd d_ras* rxd0 d_data0 c_addr c_data c_data0 grxd txen txen rxd d_data0 d_data d_data d_data c_addr c_data c_data0 grxd0 txen RS_dv rxd d_addr d_data d_data d_data d_data c_addr c_data e_do txen RS_dv rmii_clk_hertz d_addr d_addr d_data d_data c_data c_data grxd H_tdo txen[:0] rxd0 d_data c_data c_data grxd txen rxd d_addr d_data c_data c_data grxd rxd d_addr d_addr d_data c_addr grxd d_cas* txen RS_dv[:0] rxd0 rxd0 d_addr d_data c_addr0 c_data c_data grxd TMS RS_dv d_data d_data d_data grxd RS_dv RS_dv0 d_data0 d_data c_data c_data d_cs* c_addr rxd d_addr d_addr0 d_data d_data d_data d_data c_data TRST* txen d_qm RS_dv rxd0 d_data d_data0 c_data grxd grxd TK txen0 RS_dv rxd0 rxd0 d_data c_addr c_data c_data grxd0 grxd txd txd0 R R R R R R R R R0 R R00 R R R R R0 0R R K TP R0 nf R R0 K R K R0 K R K R R R R R R R R R R R R R R R R R R R R R R R R R R R0 R R R R R T RM ONTROL RM PROM INTRF L INTRF MII/RMII INTRF JTG INTRF GLINK INTRF MIS INTRF U GT0 Y T M G Y R Y R W R Y R T T T U U L U V U W W W V V J P F F F G G G G H H H J J K K K L L L M M M N N N N P P J 0 0 Y Y Y Y Y Y V V V W N0 P P P J J K K F 0 0 Y 0 W0 T L G T M H U N J0 U0 N J 0 Y0 U N H 0 0 U M H 0 Y 0 W W Y Y K L0 L L F F G G0 R R R0 R 0 TXN0 _W* TXN _S* TXN _RS* TXN _S* TXN _QM TXN _W* TXN PROM_O TXN _S* PROM_I _RS* PROM_S _S* PROM_LK _QM L LK L ST L T LIMIT NV* LK RST* TRISTT* SN* TRST TMS TO TI TK GRXM GTXM GRX0 GRX GRX GRX GRX GRX GRX GRX GRX GRX GRX0 GRX GRX GRX GRX GRX GTX0 GTX GTX GTX GTX GTX GTX GTX GTX GTX GTX0 GTX GTX GTX GTX GTX GRX_LK _T0 _T _T _T _T _T _T _T _T _T _T0 _T _T _T _T _T _T _T _T _T _T0 _T _T _T _T _T _T _T _T _T _T0 _T _R0 _R _R _R _R _R _R _R _R _T0 _T _T _T _T _T _T _T _T _T _T0 _T _T _T _T _T _T _T _T _T _T0 _T _T _T _T _T _T _T _T _T _T0 _T _R0 _R _R _R _R _R _R _R _R _R _R0 _R M MIO SMI_USY_IN* SMI_USY_OUT* RX0_0 RX0_ RX0_ RX0_ RX_0 RX_ RX_ RX_ RX_0 RX_ RX_ RX_ RX_0 RX_ RX_ RX_ RX_0 RX_ RX_ RX_ RX_0 RX_ RX_ RX_ RX_0 RX_ RX_ RX_ RX_0 RX_ RX_ RX_ TXLK0 TXLK TXLK TXLK TXLK TXLK TXLK TXLK OL0 OL OL OL OL OL OL OL RXR0 RXR RXR RXR RXR RXR RXR RXR RXLK0 RXLK RXLK RXLK RXLK RXLK RXLK RXLK RXV0 RXV RXV RXV RXV RXV RXV RXV RS0 RS RS RS RS RS RS RS TX0_0 TX0_ TX0_ TX0_ TX_0 TX_ TX_ TX_ TX_0 TX_ TX_ TX_ TX_0 TX_ TX_ TX_ TX_0 TX_ TX_ TX_ TX_0 TX_ TX_ TX_ TX_0 TX_ TX_ TX_ TX_0 TX_ TX_ TX_ clk R rxd[:0] 0 rxd[:0] rxd[:0] 0 rxd[:0] rxd[:0] rxd[:0] txen[:0] 0,, d_cs* d_we* d_ras* d_cas* d_qm c_cs* c_we* c_ras* c_cas* c_qm led_stb led_clk led_data gtxcmd gtxd[:0] 0,, e_cs e_clk,0,, limit RS_dv[:0] 0, rst*, H_main_clk endev* grxcmd grxd[:0] rxd[:0] 0 grx_clk rxd0[:0] 0 c_addr[:0] d_data[:0], c_data[:0], d_addr[:0], H_clk_ e_do e_di txd[:0] txd0[:0] 0, txd[:0] 0 txd[:0] txd[:0], txd[:0] 0 txd[:0] 0 txd[:0] rmii_clk_hertz H_tdo H_tdi TMS TK TRST*

3 ssembled GT VI NUMR(msb) GT VI NUMR(lsb) ssembled NUMR OF VIS(msb) NUMR OF VIS(lsb) GT VI NUMR GT VI NUMR(msb) R0 K NUMR OF VIS(lsb) R0 K NUMR OF VIS NUMR OF VIS(msb) R0 K RM SIZ enable NOT: PLING JUMPR STS '' FOR LL JUMPRS R0 JP JP JP JP0 JP JP JP JP JP - device enabled when unconnected HRX HRX HRX HRX HRX HRX HRX HRX JP - R LINK STTUS WHN '', LS FOR should be unconnected if in stand-alone mode (enable) K -installing RN0 - will disable bytes packets if working with GT00 - this jumper should be connected (disabled), enabling is done by the GT00 JP - limits the # of re-transmits to when connected R GT VI NUMR(lsb) R K d_addr0 d_addr[:0] (should be left un connected) R R R00 R R R R RN K K K K K K K K K FOR LINK~ JP,, - ST TH # OF VIS ON Glink JP,,0 - ST TH VI NUMR JP - ST TH T RM SIZ (Mb when '') R K R K R K R K d_addr d_addr d_addr d_addr d_addr d_addr d_addr d_addr d_addr d_addr0 default should be : # of devices = ram Size = '' => Mb enable RK RK do not skip init enable buff thr limit endev* nev~ evice nabled JP HRX R0 K JP HRX R K e_do endev* limit limit ollisions c_data[:0] PROM INTRF e_cs S L mode = 0 c_data SMI mode = single HRTZ on port c_data e_clk LK P RN 0R SMI master/slave = HRTZ is master c_data e_di I ORG ORG = -> xbit e_do O GN RN R disable_kbyte c_data d_data[:0] K K L_PROM P = 0 -> programing disabled R R0 R0 (when resistor installed ) - installing RN will bypass the PLL - installing RN0 will set data-dram cas latency K K K to L - installing RN will set control-dram cas latency d_data R0 R R to L R K K K Reset onfiguration For PROM Size 00 -> k R 0ohm not connected =>PLL ONNT 0 -> k R 0ohm connected => PLL YPSS 0 -> k JP sets the size of eprom : - when installed :K - when uninstalled : no eprom - installing RN will allow setting size to K/K - installing RN will allow on-board programing of eprom U R K RN K JP HRX R K R K R K RN K control dram cas-lat` d_data data dram cas-lat` d_data R K R 0ohm connected => L R 0ohm not connected => L S latency '' -> L '0' -> L K R K R K R K R K ONFIGURTION NG_for_F nabled R K R0 K rmii K c_data R c_data0 c_data c_data c_data c_data c_data c_data c_data GT0 RMII V with M NetPHY-LP Size ocument Number Rev R0 K R K R0 K ate: Monday, ugust 0, Sheet of

4 prevent SRM active while in reset T RM GT0 RMII V with M NetPHY-LP Monday, ugust 0, Size ocument Number Rev ate: Sheet of d_ras* d_cs* d_cas* d_we* d_cas* d_ras* d_we* d_addr0 d_addr d_dramclk d_addr d_addr d_addr0 d_addr d_addr0 d_addr0 d_addr d_addr d_addr d_addr d_addr d_addr d_addr d_addr d_addr d_addr d_addr d_addr d_addr d_addr d_addr d_addr d_cs* d_data d_data d_data d_data d_data d_data d_data d_data d_data d_data0 d_data0 d_data d_data d_data d_data d_data d_data d_data d_data d_data0 d_data d_data d_data d_data0 d_data d_data d_data d_data d_data d_data d_data d_data d_qm d_qm R K U MTLMTG GN GN GN GN GN GN Q K Q Q LK Q 0 Q Q0 S Q Q W Q RS Q Q0 SL Q Q Q Q QML Q QMH / 0 U MTLMTG GN GN GN GN GN GN Q K Q Q LK Q 0 Q Q0 S Q Q W Q RS Q Q0 SL Q Q Q Q QML Q QMH / 0 R K R K d_data[:0], d_addr[:0], d_dramclk d_dramclk d_cs* d_we* d_ras* d_qm d_cas*

5 prevent SRM active while in reset ONTROL RM GT0 RMII V with M NetPHY-LP Monday, ugust 0, Size ocument Number Rev ate: Sheet of c_data c_data c_data c_data c_data c_data0 c_data c_data c_data c_data0 c_data c_data0 c_data c_data c_data c_data c_data c_data c_data c_data0 c_data c_data c_data c_data c_data c_data c_data c_data c_data c_data c_data c_data c_addr c_addr c_addr c_addr c_addr0 c_addr c_addr c_addr c_addr c_addr c_addr c_addr c_addr c_addr c_addr0 c_addr c_addr c_addr c_addr c_addr c_cas* c_ras* c_cs* c_we* c_qm c_ras* c_we* c_cas* c_qm c_cs* n_adr_ n_adr_ n_adr_ n_adr_ n_adr_ n_adr_ U MTLMTG GN GN GN GN GN GN Q K Q Q LK Q 0 Q Q0 S Q Q W Q RS Q Q0 SL Q Q Q Q QML Q QMH / 0 R K R0 K R K R K U MTLMTG GN GN GN GN GN GN Q K Q Q LK Q 0 Q Q0 S Q Q W Q RS Q Q0 SL Q Q Q Q QML Q QMH / 0 R0 K c_data[:0] c_addr[:0] c_cs* c_ras* c_qm c_dramclk c_we* c_cas* c_dramclk

6 GLINK connector (male) 00- GRX[:0] ON grxd[:0] GRXLK grxclk GTX[:0] GRX[:0] GTX0 GRX0 GRXM GN grxcmd GN GTX GRX main_clk main_clk, 0 GTX 0 GRX GN,,0, GN GTX GRX GTX[:0] gtxd[:0] GTXLK GTX GRX gtxclk 0 GTXM GN 0 GN JTG SHM gtxcmd GTX GRX HRTZ GTX GRX in (GLINK) IN OUT out(glink) GN 0 GN GTX 0 GRX H_tdo 0 - TK GTX GRX - TI GN GN - TO GTX 0 GRX 0 - TMS GTX0 GRX0 -TRST* GN GN GTX GRX 0 GTX 0 GRX GN GN GTX GRX GTX GRX 0 GN 0 GN GTX GRX R R R Pins + GTXM GRXM are connected GN 0 GN so that a GTXLK 0 GRXLK K K K GN GN UGT will TRST* know that the GN GN TK TK 0 main_clk HRTZ is GN 0 GN TMS connected to TK TMS GN GN TO TO H_tdo it TMS GN 0 TI TI 0 H_tdi GN GN TRST* TRST* male R 0 U NRR-K R K V/GN V/GN U NRR-K 0 V/GN V/GN R K K GRXM GRXLK GRX[:0] GRX0,,,,,,,0,,,,,, GRX GN GRX GN,,,,,,0,,,,,,, line twist is GRX for routing GRX GRX pullups resons GRX GRX when HRTZ not GRX connected with GRX GLINK/LVS GRX GRX0 GRX GRX GRX GRX GRX GT0 RMII V with M NetPHY-LP Size ocument Number Rev GLINK INTRF ate: Monday, ugust 0, Sheet of

7 rst*,, ON ON JTG ONTORS cut pin # R K R K U Y0 RST*/Y 0 GO 0 JP JP LNK HRX HRX led_clk port0_led_0 L0P PL LOS TO P led_stb I/O I/O port0_led_ L0P[:0] led_data I/O I/O L0P[:0] port_led_0 LNK gpp0 TP I/O0 I/O port_led_ gpp gpp I/O I/O port_led_0 L0P LNK[:0] I/O0 I/O LNK[:0] TP 0 port_led_ TP I/O I/O port_led_0 LNK R R gpp0 I/O I/O port_led_ TP I/O I/O K K port_led_0 TP I/O I/O0 port_led_ TP I/O I/O port_led_0 I/O I/O port_led_ I/O I/O port_led_0 L0P I/O I/O 0 port_led_ I/O I/O port_led_0 LNK rst* I/O0 I/O port_led_ I/O I/O L0P led_data led_stb ispn* GN LNK led_clk pal_tck ispn GN tdi TK*/Y L0P tdo *TI/IN 0, pal_tms *TO/IN 0 LNK TMS isplsi0lv tdo tdi ispn* pal_tms pal_tck 0uF * omponents on this page are not assembled when using the PHY to drive the L's Vdd Vdd L0P0 LNK0 L0P L0P LNK GT0 RMII V with M NetPHY-LP Size ocument Number Rev L_ontroller ate: Monday, ugust 0, Sheet of

8 LOK ROUTING (see recommendations): SRIS UMPING RSISTORS SHOUL PL S LOS S POSSIL TO OUTPUTS LK TRS SHOUL NOT INTRST H OTHR TRY TO ROUT LK ON SINGL LYR O NOT US 0deg NGLS "WRP" LK SIGNLS WITH GN/POWR U c_dramclk c_dramclk main_clk main_clk should be placed close to pin in case of ringings on clk from GT00 board - connect the termination RN 0R N c_dramclk close to driver pin! R R MIN LOK RF LK LK GN LKOUT LK LK close to driver pins! R R R R R R H_main_clk c_dramclk gtxclk H_main_clk c_dramclk gtxclk nf R Y0 K N N 0pF pf 0pF pf use capacitance to tune skew between Glink-clk to GT0-clk RMII :0Mhz 0nF U OS_GXO_0M R R N N N K K pf pf pf U RF LK LKOUT LK R R R R rmii_clk_hertz rmii_clk_phy LK GN LK R R rmii_clk_phy R R Y0 *ata ram clk (M) close to driver pins! U N/ N/ GN OS / IP LK place oscilator close to clk buffer 0nF R 0R R R _RM_ R 0R U FK RF LK S LK 0 S LK LK GN GN OS/IP-M Y0-H LK LK LK LK R R R R R R to GT0 H_clk_ d_dramclk d_dramclk N N pf pf pf pf GT0 RMII V with M NetPHY-LP Size ocument Number Rev MIS INTRF ate: Monday, ugust 0, Sheet of

9 txd0[:0] txd[:0] txd[:0] txd[:0] Quad PHY 0 txd0[:0] txd[:0] txd[:0] txd[:0] txen[:0] RS_dv[:0] txen[:0] RS_dv[:0] RX_R[:0] R RX_R[:0] K T+ T+ T+ rmii_clk_phy rmii_clk_phy T- rmii_clk_phy T- R+ T- R+ R- R+ R- R- can also use : XFT MQ T+ T+ T- T+ as magnetics T- R+ T- R+ R- R+ R- R- Quad PHY 0 SPL[:0] LNKL[:0] rxd0[:0] rxd[:0] rxd[:0] rxd[:0] T0+ T0- R0+ R0- T+ T- R+ R- QU_ txen[:0] HGN txen[:0] SPL[:] txen[:] SPL[:] LNKL[:] magnetics0 txen[:0] LNKL[:] T+ T- R+ R- txd[:0] txd[:0] rxd[:0] rxd[:0] txd[:0] txd[:0] rxd[:0] rxd[:0] txd[:0] txd[:0] rxd[:0] rxd[:0] txd[:0] txd[:0] rxd[:0] rxd[:0] leds txen[:] RS_dv[:] SPL[:0] txen[:] RS_dv[:] RX_R[:] SPL[:] SPL[:0] RX_R[:] SPL[:0] T+ LNKL[:0] rmii_clk_phy rmii_clk_phy T+ T- T+ LNKL[:] LNKL[:0] rmii_clk_phy T- R+ T- LNKL[:0] R+ R- R+ R- R- T+ T+ T- T+ T- R+ T- R+ R- R+ L0P[:0] L0P[:0] R- R- T+ LNK[:0] LNK[:0] T+ T- T+ T- R+ T- R+ R- R+ R- R- Quad PHY T+ T- R+ R- SPL[:0] LNKL[:0] T+ T- R+ R- T0+ T0- R0+ R0- T+ T- R+ R- rxd0[:0] rxd[:0] rxd[:0] rxd[:0] T+ T- R+ R- T0+ T0- R0+ R0- place capacitors/coil for coupling chasis ground to system gnd RS_dv[:] RS_dv[:0] RX_R[:] RX_R[:0] RS_dv[:0] RX_R[:0] RS_dv[:0] RX_R[:0] magnetics HGN HGN RJ - front view 0 GT0 RMII V with M NetPHY-LP Size ocument Number Rev RMII INTRF ate: Monday, ugust 0, Sheet of

10 rmii_clk_phy rxd[:0] txd[:0], rxd0[:0] txen[:0] rxd[:0] txd[:0] rxd0[:0] txen[:0] rxd rxd0 RX_R RS_dv txd txd0 txen rxd0 rxd00 R R R0 R R R R R RX_R RX0_R RX_R RX0_R MR MIOR RX0_R RX_R R R R R R R R R txen txd0 txd RS_dv RX_R rxd0 rxd txen txd0 txd rxd[:0] txd[:0],,, txd[:0] rxd[:0] txd[:0] RX_R[:0] RS_dv[:0] RX_R[:0] RS_dv[:0], txd0 txd0[:0] txd0[:0] txd00 txen0 PHY start address = R 0K RX_R0 RS_dv0 LNKL SPL LNKL0 SPL0, IRF R 0K 0 00 U MK\W RS_dv RX_R RX0_R RX_R SPL LNKL SPL LNKL R R0 R 0K R R rxd0 rxd SPL[:0] LNKL[:0] rxd[:0] RXR_/MIITXR RSV_/RXN_ GN_ TX_/MIIRX TX0_/MIIRX0 TXN_/RS_ GN_O LPX_/PHY LT_/PHY LSP_/PHY PX_/FX_IS T_/IM_IS LSP_/TP INTR RST GN_G IRF V_G V_G V_ V_O RX0_/MIITX0 RX_/MIITX V_ TXN_/RS_ TX0_/MIIRX TX_/MIIRX GN_ GN_O RSV_/RXN_ RXR_ RX0_/MIITX RX_/MIITX V_ RFLK M MIO TXN_/RS_ V_O TX0_/MIIRX RXIN_ RXIP_ GN_ GN_ TXOP_ TXON_ V_ V_ TXON_ TXOP_ GN_ GN_ RXIP_ RXIN_ V_ V_ RXIN_ RXIP_ GN_ TX_/MIIRXV GN_ RSV_/RXN_ RXR_ RX0_/TXN_ RX_/TXN_ V_ TXN_/RS_ GN_O TX0_/RXR GN_ TXOP_ TXON_ V_ V_ TXON_ TXOP_ GN_ GN_ RXIP_ RXIN_ TX_/MII_OL GN_ RSV_/RXN_ RXR_/PHY RX0_/TXN_ RX_/TXN_ V_O SP_/00 T_/RPTR PX_/PLX SP_/URIN T_/NG LPX_/SR FXTN_ FXTP_ FXRN_/TST FXRP_/TST SN_/TST SP_/TST0 V_ 0 0 R 0K rxd[:0] SPL[:0] LNKL[:0] R0- R0+ R0- R0+ T- T+ R+ R- R- R+ T+ T- T- T+ R+ R- T0+ T0- R+ R- T0+ T0- T- T+ R+ R- R- R+ T+ T- T- T+ The following pin have internal ull-up: p FX_IS () - No FX IM_IS () - No IM TP_ () - : trafo PLX () - Full duplex NG () - uto neg n SRM_N () - n Scramble GT0 RMII V with M NetPHY-LP Size ocument Number Rev ustom 0 ate: Monday, ugust 0, Sheet 0 of

11 ON R0+ 0 rx+ rx- R+ R0-0 R- T+ N R+ 0 Port 0 R- N U R/% T- R- 0 R rx- N 0 R 0uF RX0+ RX0+ N R+ 0 R+ R/% rx+ RX0- RX0- R RJ port R R 0 T+ TX0+ TX0+ R- 0 R/% rj_txc TX0 TX0 R R R R0 TX0- TX0-0 T- R/% R nf/kv R+ 0 R- R/% R- 0 R0 0 rx- ONF R 0uF RX+ RX+ rx+ F R+ R/% rx+ rx- R+ F RX- RX- R- F 0 T+ R/% TX+ TX+ rj_txc T+ F R TX TX N F TX- TX- Port R N F R/% T- 0 T- F N F R- N R/% RJ port R 0 rx- R R R 0uF RX+ RX+ R+ R/% rx+ R R R RX- RX- 0 T+ R/% TX+ TX+ rj_txc R TX TX nf/kv R TX- TX- R R/% 0 T- ON rx+ R0- rx- R+ R/% R- R 0 rx0- T+ R 0uF RX+ RX+ N Port R0+ R/% rx0+ N RX- RX- T- 0 T0+ R/% TX+ TX+ rj_tx0c N R TX TX N R TX- TX- RJ port R/% Pulse_H0 R R 0 T0- R R R HGN place close to magnetics nf/kv R TO PHY TO RJ ON rx0+ rx0- R+ R- T+ nf nf nf nf N N Port T- N N ouble Stacked RJ port mapping - front view R R R R0 R RJ port R nf/kv 0 HGN HGN sub-units arrangement Note: The Rx+/Rx- pairs are swapped to improve routing The NetPHY-LP design remains functional The reversal of the data pairs is corrected by the enabled auto-polarity detection on ouble-stacked and correction function which compensates for the reversal, such that the data received RJ connector remains intact F G H GT0 RMII V with M NetPHY-LP Size ocument Number Rev Magnetics phy 0 ate: Monday, ugust 0, Sheet of

12 rmii_clk_phy rxd[:0] txd[:0] rxd[:0] txen[:] rxd[:0] txd[:0] rxd[:0] txen[:] rxd rxd0 RX_R RS_dv txd txd0 txen rxd rxd0 R R R0 R R R R R R R R R R R R R txen txd0 txd RS_dv RX_R rxd0 rxd txen txd0 txd rxd[:0] txd[:0],,0, txd[:0] rxd[:0] txd[:0] RX_R[:] RS_dv[:] RX_R[:] RS_dv[:], txd[:0] RX_R RS_dv txd txd[:0] txd0 txen PHY start address = 0x0 R 0K LNKL SPL LNKL SPL, R 0K 0 00 U MK\W RS_dv RX_R R R R SPL LNKL SPL LNKL 0K R R rxd0 rxd SPL[:] LNKL[:] rxd[:0] RXR_/MIITXR RSV_/RXN_ GN_ TX_/MIIRX TX0_/MIIRX0 TXN_/RS_ GN_O LPX_/PHY LT_/PHY LSP_/PHY PX_/FX_IS T_/IM_IS LSP_/TP INTR RST GN_G IRF V_G V_G V_ V_O RX0_/MIITX0 RX_/MIITX V_ TXN_/RS_ TX0_/MIIRX TX_/MIIRX GN_ GN_O RSV_/RXN_ RXR_ RX0_/MIITX RX_/MIITX V_ RFLK M MIO TXN_/RS_ V_O TX0_/MIIRX RXIN_ RXIP_ GN_ GN_ TXOP_ TXON_ V_ V_ TXON_ TXOP_ GN_ GN_ RXIP_ RXIN_ V_ V_ RXIN_ RXIP_ GN_ TX_/MIIRXV GN_ RSV_/RXN_ RXR_ RX0_/TXN_ RX_/TXN_ V_ TXN_/RS_ GN_O TX0_/RXR GN_ TXOP_ TXON_ V_ V_ TXON_ TXOP_ GN_ GN_ RXIP_ RXIN_ TX_/MII_OL GN_ RSV_/RXN_ RXR_/PHY RX0_/TXN_ RX_/TXN_ V_O SP_/00 T_/RPTR PX_/PLX SP_/URIN T_/NG LPX_/SR FXTN_ FXTP_ FXRN_/TST FXRP_/TST SN_/TST SP_/TST0 V_ 0 0 R 0K rxd[:0], SPL[:] LNKL[:] R- R+ R- R+ T- T+ R+ R- R- R+ T+ T- T- T+ R+ R- T+ T- R+ R- T+ T- T- T+ R+ R- R- R+ T+ T- T- T+ The following pin have internal ull-up: p FX_IS () - No FX IM_IS () - No IM TP_ () - : trafo PLX () - Full duplex NG () - uto negn SRM_N () - n Scramble GT0 RMII V with M NetPHY-LP Size ocument Number Rev ustom 0 ate: Monday, ugust 0, Sheet of

13 HGN HGN R- ON R+ rx+ R- rx- R+ R+ R- R- T+ R+ N R- N R+ T- N R- N R/% U0 RJ port R 0 rx- R R0 R 0uF RX0+ RX0+ R R R+ R/% rx+ R RX0- RX0- T+ R/% TX0+ TX0+ rj_txc R0 TX0 TX0 nf/kv R TX0- TX0- R ONH T- R/% rx+ H R- rx- R+ H R/% R- H R rx- T+ 0 H R 0uF RX+ RX+ N H R+ R/% rx+ N H RX- RX- T- T+ H R/% TX+ TX+ rj_txc N H R0 TX TX N R TX- TX- RJ port T- R/% R R R R R- R 0 R/% R 0 rx- R 0uF RX+ RX+ nf/kv R+ R/% rx+ R RX- RX- ON T+ R/% TX+ TX+ rj_txc rx+ R TX TX rx- R+ R TX- TX- R- R/% T+ N T- N R- T- R/% N R rx- N 0 R 0uF RX+ RX+ RJ port R+ R/% rx+ R0 R0 RX- RX- T+ R R R/% TX+ TX+ rj_txc R R TX TX R TX- TX- T- R/% Pulse_H0 nf/kv R ONG rx+ G rx- R+ G R- G T+ G N nf nf nf nf G N G T- ouble Stacked RJ port mapping - front view TO PHY 0 TO RJ R R R0 R R R G G N N RJ port 0 nf/kv sub-units arrangement on ouble-stacked RJ connector F G H Note: The Rx+/Rx- pairs are swapped to improve routing The NetPHY-LP design remains functional The reversal of the data pairs is corrected by the enabled auto-polarity detection and correction function which compensates for the reversal, such that the data received remains intact GT0 RMII V with M NetPHY-LP Size ocument Number Rev Magnetics phy ate: Monday, ugust 0, Sheet of

14 * isassemble when using the PHY L0P[:0] indicate SP when driven by PHY as the L driver L0P[:0] indicate UPLX when driven by GT0 * ssemble when using the GT0 as the Ldriver SPL0K R 0 L assembly view for ssyopt (PHY riving L's) 0, SPL[:0] SPL[:0] SPL 0R R L0P L0P 0K HSMS-H0 R L_L0P L_L0P R PHY #: PHY R SPL0 R L0P0 0K R0 L_L0P0 R 00R 00R 0 SPL R L0P 0K R L_L0P LNK HSMG-H0 L_LNK R PHY #: PHY R SPL R L0P 0K R L_L0P SPL R0 L0P 0K R L_L0P L0P HSMS-H0 L_L0P R 00R Leds S View SPL R0 L0P 0K R L_L0P 00R SPL R L0P 0K R L_L0P LNK HSMG-H0 L_LNK R SPL R L0P 0K R L_L0P 00R L0P HSMS-H0 L_L0P R 0, LNKL[:0] LNKL[:0] 0R 00R LNKL0 R LNK0 0K R0 L_LNK0 LNK HSMG-H0 L_LNK R LNKL R LNK0K R L_LNK 00R LNKL R LNK 0K R L_LNK LNKL R LNK 0K R L_LNK LNKL R0 LNK 0K R0 L_LNK LNKL R0 LNK 0K R0 L_LNK L0P 0 HSMS-H0 L_L0P R LNKL R LNK 0K R L_LNK 00R LNKL R LNK 0K R L_LNK LNK HSMG-H0 L_LNK R 00R * ssemble when using the PHY as the L driver L0P HSMS-H0 L_L0P R PHY #: PHY R * isassemble when using the GT0 as the L driver LNK HSMG-H0 L_LNK R PHY #: PHY R 00R L0P HSMS-H0 L_L0P R 00R LNK HSMG-H0 L_LNK R 00R L0P HSMS-H0 L_L0P R 00R LNK HSMG-H0 L_LNK R 00R L0P[:0] LNK[:0] L0P[:0] LNK[:0] L polarity changes according to driving source: - athode to the left when driven by the GT0 - node to the left when driven by the PHY L0P0 LNK0 HSMS-H0 HSMG-H0 L_L0P0 L_LNK0 R0 R0 00R 00R ssemble the resistor that matches L polarity LS ate: Monday, ugust 0, Sheet of GT0 RMII V with M NetPHY-LP Size ocument Number Rev 0

15 place close to clk source! note : test-points for clk are smt hpconn/ hpconn0/ hpconn/0 hpconn/ hpconn/ hpconn/ hpconn/ hpconn/ hpconn/ hpconn/ hpconn/0 hpconn0/ hpconn0/ hpconn/ hpconn/ hpconn/0 hpconn0/ hpconn0/ hpconn0/ hpconn/ hpconn/ hpconn/ hpconn0/ hpconn0/ hpconn/ hpconn/ hpconn0/ hpconn/0 hpconn/ hpconn/0 hpconn0/ hpconn0/0 hpconn/ hpconn/ hpconn/ hpconn/ hpconn/ hpconn0/ hpconn/ hpconn/ hpconn/0 hpconn0/ hpconn/ hpconn0/ hpconn/ hpconn0/ hpconn0/ hpconn/ TST POINTS GT0 RMII V with M NetPHY-LP Monday, ugust 0, Size ocument Number Rev ate: Sheet of GN GN GN GN GN GN rxd GN GN GN GN GN GN GN GN GN GN GN GN GN GN txd0 txd00 txd txd0 rxd00 rxd0 txd00 txd0 RS_dv0 rxd00 rxd0 txen0 RS_dv txen RS_dv txen RS_dv txen RS_dv txen RS_dv txen RS_dv rxd0 txen rxd0 rxd RS_dv txen RX_R RX_R RX_R0 RX_R RX_R RX_R RX_R RX_R txen RS_dv txen RS_dv RS_dv0 txen0 txen txen RS_dv RS_dv RS_dv txen RS_dv txen txen RS_dv GN TP TP ON_N rst* main_clk RS_dv[:0] txd0[:0] txd[:0] rxd0[:0] rxd[:0] RX_R[:0] txen[:0] GN

16 ,,,,,,,0,,,,,,,,,,,,,,0,,,,, GN U GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN F F0 K K0 K K K K K0 L0 L L L L M0 M M M M N0 N N N N P P0 P P P P P0 V V0 Y Y Y GN GN GN GN GN GN GN GN GN GN GN GN 0 PRT OF R H 0R H0 M V M0 T PLL SUPPLY Y VSS T0 Y uf 0uF Y0 Y Y GT0 R 0R GT0 RMII V with M NetPHY-LP Size ocument Number Rev GT0-POWR LOK ate: Monday, ugust 0, Sheet of

17 ,,,,,,,,0,,,,,,,,,,,,0,,,,,, GN R 0R green Power Led L - (green), place close to pins! U NetPHY-LP ch 0,, 0,, uF 0uF 0uF 0uF 0uF 0uF 0uF 0uF 0uF 0uF,,,0 near 0uF place close to pins! U NetPHY-LP ch,,, 0,,00 0uF 0uF 0uF 0uF 0uF 0uF 0uF 0uF 0uF 0uF 0uF 0uF 0uF 0uF 0uF 0uF,,,0 near 0uF 0uF 0uF 0 0uF 0uF 0uF 0uF 0uF 0uF TP TP TP TP TP TP TP0 0uF 0uF 0uF NOT : PUT S MNY VIS S POSIL TWN TWO GROUN LYRS place accourding to filter-schem! Placement of decoupling capacitors uf I pin PHY capacitors apacitor P 0uF 0uF 0uF 0uF 0 0uF 0uF 0uF 0uF 0uF 0uF 0uF 0uF 0uF 0uF 0uF 0uF 0uF GN Power Via GT0 RMII V with M NetPHY-LP Size ocument Number Rev ate: Monday, ugust 0, Sheet of POWR

18 GT0 RMII V with M NetPHY-LP Revised: Monday, ugust 0, MIN Revision: 0 VN MIRO VIS esigned by ompulab Ltd ill Of Materials ugust, :0: Page Item Quantity Reference Part ssembly Option N,N,N,N,N, pf 0 N,N N nf 0 ON_N0- ON00-male ON ON ON RJ port,0nf uf,,,,,0,,0uf,,,,,,,0,,,,,,,,0,,,,,,,,,,0,,,,,,,,0,,,,,,0,,,,,,,,,,,,,,, 0, 0,, 0uF, 0pF,,,,0,, nf/kv 0,,,,,,, nf,, uf, pf,,,,,,,hsmg-h0,,,,0,,, HSMS-H0 L - (green) JP,JP,JP,JP,JP,JP0, HRX JP,JP,JP,JP,JP, JP,JP 0 RN,RN,RN,RN K 0 RN 0R 0 RN 0R 0 R,R,R,R,R0,R, K R,R,R,R00,R0, R0,R0,R0,R0,R0, R,R,R,R,R, R0,R,R0,R,R, R,R,R,R,R, R,R,R,R0,R0, R,R,R,R,R

19 R,R,R0,R,R, R,R,R0,R,R, R,R,R,R,R0, R,R,R,R,R, R,R,R0,R,R, R,R,R R,R,R,R,R0,R,R, R R,R,R,R,R,R, R,R,R,R,R,R0, R,R,R,R,R,R, R0,R,R,R,R0,R, R,R,R,R,R,R, R,R,R,R,R,R, R,R,R,R,R R,R0,R0,R,R,00R R,R,R,R,R, R,R,R,R,R, R R,R,R,R,R,R,R/% R,R,R,R0,R,R, R0,R,R,R,R,R, R,R,R,R,R,R, R,R,R,R0,R,R, R0,R R,R,R,R0,R0, 0K R,R,R,R,R, R,R0,R,R0,R, R,R,R,R,R, R,R,R,R R,R,R,R,R,R, R R,R,R,R,R, R0,R,R,R,R, R0,R0,R0,R,R, R,R0,R R,R,R,R,R, 0R R,R,R,R,R, R,R0,R0,R0,R0, R,R,R,R,R, R 0 R 00R 0 R 0K 0 R K R K R,R0,R,R,R, R,R,R,R00,R0, R,R,R,R,R, R,R R0 0R R 0R TP,TP,TP,TP,TP,TP, TPsmdx 0 TP,TP,TP TP,TP,TP,TP0,TP, TP_TH 0 TP,TP U OS_GXO_0M 0 U,U Y0 U,U MTLMTG- U0,U Pulse_H0 U,U MK\W U GT0 U L_PROM U OS/IP-M

20 U,U MTLMTG- U Y0-H U isplsi0lv 0 0 U,U NRR-K