TEST INTERFACE PORT 7,3. Schematics

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Beverley Webb
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1 Table Of ontents Page : over.sh Page : Inputs.SH Page : MH.SH Page : Ports.SH Page : isplays.sh Page : atainfo.sh Page : thernet.sh Page : ebug.sh TST INTRF PORT, Schematics RV. Sheet : Removed K pull down on N. hanged resistor values of R and R. dded a Schottky arrier Rectifier to power supply circuit. Sheet : dded TRST net to MH. Sheet : hanged resistor R form K to ohm. Sheet : hanged resistors R - R from K to K. Sheet : Ground VSS on U. dded k pull up resistor to IOHRY signal. Sheet : hanged SW_IRQ# nodename to MIN_IRQ. dvanced Micro evices, Inc. ("M") reserves the right to discontinue its products, or make changes in its products, at any time without notice. The information in this publication is believed to be accurate at the time of publication, but M makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication or the information contained herein, and reserves the right to make changes at any time, without notice. M disclaims responsibility for any consequences resulting from the use of the information included in this publication. This publication neither states nor implies any representations or warranties of any kind, including but not limited to, any implied warranty of merchantability or fitness for a particular purpose. M s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of M s product could create a situation where personal injury, death, or severe property or environmental damage may occur. M assumes no liability whatsoever for claims associated with the sale or use (including the use of engineering samples) of M products except as provided in M s Terms and onditions of Sale for such product. RV. Sheet : Replace H OR gate with H N gate. Removed pull down resistor R - R from shared interrupt signals. dded a pull up resistor to the PRINT signal. Sheet : dded a pull up resistor to the PM signal. while making the existing pull down resistor an optional populate resistor. Sheet : Routed IOHRY and TIPFLHS# nets to debug header opyright dvanced Micro evices, Inc. ll Rights Reserved () dvanced Micro evices, Inc. () - Note: Unless otherwise stated the resistors are a package and % Tol. Note: Unless otherwise stated the capacitors are a package and % Tol. NOT: n asterisk (*) in front of a resistor or capacitor value indicates a non populated component.. en White lvd. ustin, TX M Proprietary/ll Rights Reserved Size ocument Number Rev over.sh. ate: Thursday, pril, Sheet of

2 V V V V [:] U + uf S, V O# V O# V O# V O# V T T Y T Y T Y T Y T Y T Y T Y T Y T Y T Y - ** NOT ** T[:] T Y T Y Target boards should T Y use a pull down resistor on pin or a pull up T Y resistor on pin, for T Y auto detect of the TIP Y being active T[:] GN GN GN GN GN GN GN GN T[:] TI TGGR T[:] P T T T T G# G# T T V IR# IR# T T T T V T GN GN T T T U T T T T IR V T T IR V V T GN GN T G# V T T G# T T T V T T T T R K TIPSL# T TIPSL TN TN N N TR# TR# R K R# R# TWR # TWR # TS TS S S T NTIRQ MIN_IRQ T PRINT HRST# T SRINT TRST T SRINT FLSHR# T IOHRY FLSH T SL FLSHS# T V XTFLHS# T SL V R K MP - R K R K RK R K GN GN GN GN GN GN GN GN HRST# [:] uf S, V + HV TI TGGR V NOT: R V external power supply is MIN_IRQ required to provide V to the R K TIP board. ut a host board.m JP must be properly connected to the TIP before the external U supply is allowed to power the UJMP SW board. UINPOS V+ IN- HRST# IN+ HYST V- RF R GN OUT FSMJ LINR LTMS.M OMPRTOR R Power Supply ircuit HV HV V R K OMPROUT P TRST FLSHR# FLSH TIPFLHS# SW_INTRP# LTOUT U SLV SHUNT NTR SW_INTRP# KYON KL-- POWR ONN V IN IN G G Vs S S GN LINR LT MOSFT RIVR V () dvanced Micro evices, Inc. () - RV R K V. en White lvd. ustin, TX M Proprietary/ll Rights Reserved U SW FT FT G G S S /N FSMJ Temic SiY MOSFT (N-HN) Size ocument Number Rev Inputs.SH. T lcoswitch FSMJ arrel onnector LTOUT ate: Friday, pril, Sheet of

3 V V RV. PRINT NTIRQ U TP_IRQ SRINT Y SRINT Y MIN_IRQ V V NOT: Use of IRQ s on the TIP board have been configured for LVL TRIGGR HIGH. V R K U [:] U SW_IRQ I/O I/O G# I/O I/O IR# I/O I/O SRS# I/O I/O SRS# I/O I/O PRS# I/O I/O LN I/O I/O LRS I/O I/O LR/W I/O I/O LLK I/O I/O LO# I/O I/O HRLTLK I/O I/O HRLTO# I/O I/O HRFO# I/O I/O HXS# I/O I/O HXS# I/O I/O HXS# I/O I/O HXS# I/O I/O IPSWO# [:] I/O I/O IOSPR I/O I/O SP IOSPR SP I/O IOSPR TRST SP I/O I/O I/LK I/O [:] I/O I/O I/O I/O I/O I/O I/O I/O I/O NOT: R# I/O I/O O NOT US PIN of the MH it is not an available pin. It is used internally by the MH. I/LK I/O N I/LK I/O S I/O I/O V TIPFLHS# I I/O FLSHR# I/O P FLSH I TK SL I/O TK TMS I/O TMS SW_INTRP# TI I/O TI SLIT TO I/LK TO NL LOW NL TRST TRST R K M -U GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN V V V V V V V V V R K R K GN V Philips H GN V VNTIS MH-/-Y MH- H () dvanced Micro evices, Inc. () -. en White lvd. ustin, TX M Proprietary/ll Rights Reserved Size ocument Number Rev MH.SH. ate: Friday, pril, Sheet of

4 RV. With these resistors populated the serial port is in configuration. NOT: This is the default configuration of the TIP board. Parallel onnector R R R U PRINT PRST# PRS# PM TRI ST# PRF# NIRQ PM F# PRRR# [:] NIRQ RR# PRNIT# INT INIT# PRSLIN# S# SLIN# PRP SR_ P PRP SR_ P PRP P PRP V P PRP P PRP [:] P SW PRP R P PRP P K SR_ PRK# SWHIGH SF SR_ K# PRUSY MP - SLIT SR_ USY PRP SWL OW P PRSLT SR_ IOW# SLT omponent R K RST# IOR# SR_# SRIL ONFIGURTION side view RST# # SR_TR# LK TR# SR_SOUT With these resistors populated O SOUT SR_TS# the serial port is in configuration. R# TS# SR_SIN INT SIN NOT: This is the default configuration SR_RTS# of the TIP board. SRINT RXRY# RTS# SR_SR# TXRY# SR# SR_RI# SRS# S# RI# U R P SR_# #_T #_ INT # SR_TR# R SRINT ROUT RIN TR#_T TR#_ RXRY# TR# R SR_SOUT TIN TOUT SOUT_T SOUT_ TXRY# SOUT R SRS# SR_TS# TIN TOUT TS#_T TS#_ S# TS# R SR_SIN ROUT RIN SIN_T SIN_ V SIN R SR_RTS# ROUT RIN RTS#_T RTS#_ RTS# R SR_SR# SR#_T SR#_ V SR# SR_RI# TIN TOUT R ROUT RIN RI# RMRST V RI# TIN TOUT V V ROUT RIN GN SRVM SRP GN R V- + R MP - Serial onnector GN TRST U N# TI TLFN S SRM V SRP - + SRVP V+ SRM - GN V U R P #_T R #_ ROUT RIN TR#_T R TR#_ TIN TOUT SOUT_T R SOUT_ V Y TIN TOUT TS#_T R TS#_ ROUT RIN SIN_T SIN_ O V R ROUT RIN RTS#_T R RTS#_ LKMHZ SR#_T SR#_ GN OUT TIN TOUT R ROUT RIN RI# RMRST LIPTK -.M TIN TOUT ROUT RIN SRP R V- + MP - SRVM NOT: T SRIL ONFIGURTION R N# S SRM V To configure as T serial port, the SRP - resistors must be removed then + SRVP V+ the below resistor must me populated. HRST# SRM - GN V #_T R #_ SR#_T R TR#_ Sipex SP SIN_T R SOUT_ RTS#_T R TS#_ SOUT_T R SIN_ TT-.M TS#_T R RTS#_ TR#_T R SR#_ () dvanced Micro evices, Inc. () -. en White lvd. ustin, TX M Proprietary/ll Rights Reserved Size ocument Number Rev Ports.SH. SF MT ate: Thursday, pril, Sheet of LO V V V P Sipex SP #_T SR#_T SIN_T RTS#_T SOUT_T TS#_T TR#_T R R R R R R R #_ TR#_ SOUT_ TS#_ SIN_ RTS#_ SR#_

5 MLS- GN GN U U U U U U U U TOP VIW TIL SPRS F L S H L isplays.sh. () dvanced Micro evices, Inc. () -. en White lvd. ustin, TX M Proprietary/ll Rights Reserved Friday, pril, Size ocument Number Rev ate: Sheet of LH LL LL LH HXS# HXS# LH HXS# HXS# LL LL LH VSW UVO VSW [:] V V V V V V V V V V V V V V V R R R R R U TI TIL V GN L STR LNK L R N N N U VL LLTRIS MLS-K-LV-G GN V VO RS R/W *SP *SPR_ Y Y Y Y Y Y Y Y Y V GN *SP *SPR_ Y Y V Y GN Y Y Y JP HR, JP HR, U M MFT O W V GN U TI TIL V GN L STR LNK L R N N N U TI TIL V GN L STR LNK L R N N N U TI TIL V GN L STR LNK L R N N N U TI TIL V GN L STR LNK L R N N N U TI TIL V GN L STR LNK L R N N N U TI TIL V GN L STR LNK L R N N N K POTNTIOMTR R R U TI TIL V GN L STR LNK L R N N N R R R HXS# HXS# LN LRS LR/W HXS# HXS# FLSHR# [:] [:] TIPFLHS# FLSH [:] [:] LTOUT

6 V V V V OUTHR Y OUTHR Y OUTHR Y OUTHR Y OUTHR Y OUTHR Y OUTHR Y OUTHR Y L Y L OUTHR[:] Y L Y L Y L Y L Y L Y L Y LO# HRLTO# [:] LLK HRLTLK IPSWO# HRFO# U V V V V GN GN GN GN O# O# O# O# GN GN GN GN TI TGGR L[:] L SSL-LXYG-RP R RLN R V L R RLN R R L RLN R V R V L RLN R V SW INPSW INPSW INPSW INPSW INPSW INPSW INPSW INPSW INPHR INPHR INPHR INPHR INPHR INPHR INPHR INPHR U L L L L L L L L OUTHR OUTHR OUTHR OUTHR OUTHR OUTHR OUTHR OUTHR L L L L RLN RLN RLN RLN R R K R K R K R K R K R K R K R K MP -- O# O# O# O# GN GN GN GN V V V V Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y GN GN GN GN TI TGGR U L L # O# GN GN GN GN V V V V Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q GN GN GN GN TI TW R R R R R R R R K R K R K R K R K R K R K RK OUTHR[:] P OUTHR OUTHR OUTHR OUTHR OUTHR OUTHR OUTHR OUTHR () dvanced Micro evices, Inc. () - MP -. en White lvd. ustin, TX SW OPS of MP -- M Proprietary/ll Rights Reserved X HR SSL-LXYG-RP YL TH GRN Size ocument Number Rev atainfo.sh. ate: Friday, pril, Sheet of

7 NOT: For anolog decoupling, the boxed in area should be routed as shown, and the capacitors should be connected to the prescribed pins, not vias. L V V X UX pf UX pf NTIRQ R VSS GN V. V V uf S, FILTV K K K K K K K K K R R R R R R R R R R R IRQ R R R R R R U TRST N XTL IRQ IRQ XTL IRQ IRQ IOHRY R# SM# IRQ IRQ SM# [MSTR#] IRQ IRQ RST IRQ IRQ PM# N IRQ SRS# PM# [FLashW#] IRQ IRQ IOR# IRQ V SH# IOW# SLP# MMR# SH# SLP# MMW# MMR# IOS# IOHRY RF# MMW# IOHRY SHFUSY SSL-LXYG-RP [:] SMM# RF# SHFUSY SRW# SMM# [K#] [S] SRW# SRMO# R R [RQ] SRO# RSL S [RQ] S [RQ] XVR/R# R R S [RQ] PS# NTL RSL S [K#] L NTL S [K#] L NTL R R S [K#] L NTL RSL S [L] L INIP S [L] I R. R. R R S [L] I+ ING RSL S [L] I- IPOS S [L] I+ I S [S] I- R. R. P S [S] The main outer pin-out is for O+ INIP S [S] Othe M (TQFP ) Pulse S [S] configured in the US SLV TXNG U S [S] TX- TXPOS mode. The pin names in "[]" PR TX+ TXNG TX- TPOS PR are for the the device TXP- TXPOS TX+ T+ TNG PR configured in the US MSTR TXP+ RXNG T- PR RXmode. RXPOS TXP- PR RX+ TXP+ RPOS PR PR R+ RNG PR PR PR RX- R- PR PR PR RX+ PR PR PR PR PR PR PR PR V V V V V V V V V V V PR PR PR PR V [:] [N] PMI_MO U PR PRO/SK PR SK V PR/I PR I N PR/O S O N S S GN NTIONL SMI NMN V V TO TMS TI TK PR [S] PR [S] PR [S] PR [S] PR [S] PR [S] PR [S] PR [S] PR [S] PR [S] PR [S] PR [S] PR [S] PR [S] PR [S] PR [S] M MV PR[:] U N N N N N N N N N N N PR VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS S S S S S S S S S S S S S S S S PR PR PR PR PR PR PR PR PR PR PR PR PR PR VSS PR[:] PR V PR PR PR PR PR PR PR I/O I/O I/O I/O I/O I/O I/O I/O - V VSS R/W O# # From component side TOSHI TFTI-V Front View Mounting Hole Layout () dvanced Micro evices, Inc. () -. en White lvd. SSL-LXYG-RP ustin, TX M Proprietary/ll Rights Reserved YL TH GRN Size ocument Number Rev thernet.sh. M--.MTR ate: Friday, pril, Sheet of

8 P +V LK RV. SRINT LK TIPFLHS# SRINT IOHRY PRS# PRINT SRS# NTIRQ SRS# GN MP - HR, X P +V LK LK GN MP - HR, X [:] P +V LK FLSHR# R# R# LK FLSH HRST# N N MIN_IRQ S S T T T T T T T T GN MP - HR, X T[:] HP onn. SPRS SNTPW V V SPR U SPR V V V U U UF S SPR SPR SPRF () dvanced Micro evices, Inc. () -. en White lvd. ustin, TX M Proprietary/ll Rights Reserved U S S S S Size ocument Number Rev ebug.sh. ate: Friday, pril, Sheet of

ZCRMZN00100KITG. Crimzon Development Board Kit. Product User Guide. Introduction. Kit Contents. Applying Power to Development Board

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