IX4340NE. Automotive Grade 5-Ampere, Dual Low-Side MOSFET Driver INTEGRATED CIRCUITS DIVISION. Features. Description. Applications
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1 Automotive Grade -Ampere, Dual Low-Side MOSFET Driver Features AEC-Q100 qualified Two independent drivers, each capable of sourcing and sinking A V to 20V supply voltage range AEC-Q100 Grade 1-0 C to +12 C operating temperature range AEC-Q100 Classification 3A ±kv ESD rating (Human Body Model) Thermally enhanced 8-pin SOIC package CMOS and TTL compatible inputs Independent enable for each driver Under voltage lockout circuitry Fast propagation delays (16ns typical) Fast rise and fall times (7ns typical) Applications On-board chargers DC-DC converters Electric vehicle charging stations Motor controllers Power inverters Description The is an automotive grade, AEC-Q100 qualified dual, high current, low side gate driver. Each of the two outputs is capable of sourcing and sinking A of peak current, and has a maximum voltage rating of 20V. The two outputs can be paralleled for higher current applications. Fast propagation delay times (16ns typical) and fast rise and fall times (7ns) make the well suited for high frequency applications. The inputs are TTL and CMOS logic compatible, and there is an independent Enable function for each output. Under voltage lockout circuitry (UVLO) prevents the high side source driver from conducting until there is sufficient supply voltage. The outputs are held low if the logic inputs are floating. The is available in a thermally enhanced 8-pin SOIC package. Ordering Information Part Number TR Description 8-Pin SOIC w/ Exposed Thermal Pad (100/Tube) 8-Pin SOIC w/ Exposed Thermal Pad (000/Reel) Functional Block Diagram ENA 1 8 ENB INA 2 7 OUTA GND 3 UVLO 6 INB OUTB DS--R01 1
2 1. Specifications Pin Configuration Logic Table Pin Definitions Absolute Maximum Ratings Electrical Characteristics Thermal Characteristics Performance Data Manufacturing Information Moisture Sensitivity ESD Sensitivity Soldering Profile Board Wash Mechanical Dimensions R01
3 1 Specifications 1.1 Pin Configuration 1.2 Logic Table IXx ENx OUTx ENA 1 8 ENB 1 1 >UVLO ON 1 INA 2 A 7 OUTA 0 1 >UVLO ON 0 x 0 >UVLO ON 0 GND 3 6 x x <UVLO ON 0 INB B OUTB 1.3 Pin Definitions Pin # Name Description 1 ENA Enable input for Channel A. A logic high (or floating) enables Channel A (the state of OUTA is determined by INA). A logic low disables OUTA (OUTA held low regardless of INA). 2 INA Channel A logic input. Internally pulled to GND. 3 GND Ground. Common ground reference for the device. INB Channel B logic input. Internally pulled to GND. OUTB Channel B output, capable of sourcing and sinking A 6 Supply Voltage. 7 OUTA Channel A output, capable of sourcing and sinking A 8 ENB Enable input for Channel B. A logic high (or floating) enables Channel B (the state of OUTB is determined by INB). A logic low disables OUTB (OUTB held low regardless of INB). The thermal pad on the bottom of the thermally enhanced may be connected to GND or left floating; it must not be connected to any other net. The thermal pad is not intended to carry current. 1. Absolute Maximum Ratings Parameter Symbol Minimum Maximum Units Supply Voltage V Input Voltage V IN V Output Current I OUT - ± A ESD Rating (Human Body Model) V ESD V Junction Temperature T J C Storage Temperature T STG C Absolute maximum electrical ratings are at T A =2 C Absolute maximum ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not implied. R01 3
4 1. Electrical Characteristics = 12V, T J = -0 C to +12 C, unless otherwise noted. Parameter Conditions Symbol Minimum Typical Maximum Units Supply Supply Current OUTA and OUTB Open I CC ma Under Voltage Lockout (UVLO) UVLO Rising Threshold Rising UVLO ON UVLO Falling Threshold Falling UVLO OFF UVLO Threshold Hysteresis - UVLO HYS Logic Inputs (INA, INB, ENA, ENB) Input Low Voltage - V IL Input High Voltage - V IH Output Drivers (OUTA, OUTB) Output Pull-Up Resistance I OUT = -100mA, T J = 2 C R I OH OUT = -100mA Output Pull-Down Resistance I OUT = 100mA, T J = 2 C R I OL OUT = 100mA Rise Time C LOAD = 1.8nF t R Fall Time C LOAD = 1.8nF t F Propagation Delay, Low to High C LOAD = 1.8nF t DLH Propagation Delay, High to Low C LOAD = 1.8nF t DHL Propagation Delay Matching - t M - - V V ns V IH INx V IL 90% t DLH t DHL OUTx 10% t R t F 1.6 Thermal Characteristics Parameter Symbol Rating Units Thermal Impedance, Junction-to-Ambient JA 8 C/W Thermal Impedance, Junction-to-Case JC 10 R01
5 2 Performance Data Unless otherwise noted, data presented in these graphs is typical of device operation at T A =2ºC. Supply Current (ma) Supply Current vs. Temperature Outputs in DC ON/OFF Condition (ENA=ENB= =12V) Input= Input=0V 1.2 Supply Current (ma) Operating Supply Current vs. Temperature (Outputs Switching) ( =12V, f=00khz, C L =00pF) Supply Current (ma) Operating Supply Current vs. Frequency (C L =1.8nF, Both Channels Switching) =18V =12V =10V =V Frequency (khz) 2.0 Input Threshold vs. Temperature ( = 12V) 2.0 Enable Threshold vs. Temperature ( =12V).0 UVLO Threshold vs. Temperature Input Threshold (V) V IH V IL Enable Threshold (V) V IH V IL UVLO Threshold (V) UVLO ON UVLO OFF Propagation Delay (ns) Input To Output Propagation Delay vs. Temperature ( =12V, C L =1.8 nf) t DHL t DLH 10 Propagation Delay (ns) Enable to Output Propagation Delay vs. Temperature ( =12V, C L =1.8nF) EN to Output Low EN to Output High 1 Propagation Delay (ns) Propagation Delay vs. Supply Voltage (C L =1.8nF) Input to Output High EN to Output High Input to Output Low EN to Output Low Supply Voltage (V) R01
6 Rise Time (ns) Rise Time vs. Temperature ( =12V, C L =1.8nF) 6.2 Rise Time (ns) Rise Time vs. Supply Voltage (C L =1.8nF ) Supply Voltage (V) Output Resistance (Ω) Output Pull-Up Resistance vs. Temperature ( =12V, I OUT = -100mA) 0.6 Fall Time (ns) Fall Time vs. Temperature ( =12V, C L =1.8 nf) 6.00 Fall Time (ns) Fall Time vs. Supply Voltage (C L =1.8nF ) Supply Voltage (V) Output Resistance (Ω) Output Pull-Down Resistance vs. Temperature ( = 12V, I OUT = 100mA) R01
7 3 Manufacturing Information 3.1 Moisture Sensitivity All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated Circuits Division classifies its plastic encapsulated devices for moisture sensitivity according to the latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee proper operation of our devices when handled according to the limitations and information in that standard as well as to any limitations set forth in the information or standards referenced below. Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced product performance, reduction of operable life, and/or reduction of overall reliability. This product carries a Moisture Sensitivity Level (MSL) classification as shown below, and should be handled according to the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033. Device Moisture Sensitivity Level (MSL) Classification MSL ESD Sensitivity This product is ESD Sensitive, and should be handled according to the industry standard JESD Soldering Profile Provided in the table below is the Classification Temperature (T C ) of this product and the maximum dwell time the body temperature of this device may be (T C - )ºC or greater. The classification temperature sets the Maximum Body Temperature allowed for this device during lead-free reflow processes. For through-hole devices, and any other processes, the guidelines of J-STD-020 must be observed. Device Classification Temperature (T C ) Dwell Time (t p ) Max Reflow Cycles 260 C 30 seconds 3 3. Board Wash IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. Board washing to reduce or remove flux residue following the solder reflow process is acceptable provided proper precautions are taken to prevent damage to the device. These precautions include but are not limited to: using a low pressure wash and providing a follow up bake cycle sufficient to remove any moisture trapped within the device due to the washing process. Due to the variability of the wash parameters used to clean the board, determination of the bake temperature and duration necessary to remove the moisture trapped within the package is the responsibility of the user (assembler). Cleaning or drying methods that employ ultrasonic energy may damage the device and should not be used. Additionally, the device must not be exposed to flux or solvents that are Chlorine- or Fluorine-based. R01 7
8 3. Mechanical Dimensions 3..1 Package Dimensions 0.31 / 0.1 (0.012 / 0.020) 8x TOP VIEW BOTTOM VIEW PCB Land Pattern 0.60 (0.02) 1. (0.061).80 / 6.20 (0.228 / 0.2) 3.80 /.00 (0.10 / 0.17) 1.9 / 2.29 (0.076 / 0.090) 3.8 (0.12) 2.11 (0.083) PIN #1 1.2 MIN (0.09 MIN) 1.70 MAX (0.067 MAX) 0 / 0.1 (0 / 0.006) x.80 /.00 (0.189 / 0.197) 0.10 (0.00) 3..2 TR Tape & Reel Dimensions A GAUGE PLANE SEATING PLANE 1.9 / 2.29 (0.076 / 0.090) A 0.2 (0.010) / 0.2 (0.00 / 0.010) 0.0 / 1.27 (0.016 / 0.00) 2.11 (0.083) Dimensions MIN / MAX Notes: 1. Controlling dimension: millimeters. 2. All dimensions are in mm (inches). 3. This package conforms to JEDEC Standard MS-012, variation BA, Rev. F.. Dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.1mm per end.. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.2mm per side. 6. The thermal pad on the bottom of the device may be connected to GND or left floating; it must not be connected to any other signal. The thermal pad is not intended to carry current. 7. Lead thickness includes plating. 330 DIA. (13.00 inch DIA) B 0 =.20 W=12.0±0.3 Embossed Carrier Embossment K 0 =2.10 K 1 =1.70 A 0 =6.0 P1=8.00 Direction of feed Notes: sprocket hole pitch cumulative tolerance ± Camber in compliance with EIA Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole.. All dimensions in millimeters. For additional information please visit our website at: IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in IXYS Integrated Circuits Division s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes to its products at any time without notice. Specification: DS--R01 Copyright 2018, IXYS Integrated Circuits Division All rights reserved. Printed in USA. 12/18/ R01
IX Ampere, Dual Low-Side MOSFET Driver INTEGRATED CIRCUITS DIVISION. Features. Description. Applications. Ordering Information
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8-Bit Shift Register with Output Register The MC74LV594A is an 8 bit shift register designed for 2 V to 6.0 V V CC operation. The device contain an 8 bit serial in, parallel out shift register that feeds
74AC08 74ACT08 Quad 2-Input AND Gate
Quad 2-Input AND Gate General Description The AC/ACT08 contains four, 2-input AND gates. Ordering Code: Features I CC reduced by 50% on 74AC only Outputs source/sink 24 ma Device also available in Tape
MM74HCT138 3-to-8 Line Decoder
3-to-8 Line Decoder General Description The MM74HCT138 decoder utilizes advanced silicon-gate CMOS technology, and are well suited to memory address decoding or data routing applications. Both circuits
NC7SB3157 TinyLogic Low Voltage UHS Analog Switch 2-Channel Multiplexer/Demultiplexer (Preliminary)
September 1999 Revised November 1999 TinyLogic Low Voltage UHS Analog Switch 2-Channel Multiplexer/Demultiplexer (Preliminary) General Description The is a high performance, Analog Switch 2- channel CMOS
2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device.
74HC1G09 Rev. 02 18 December 2007 Product data sheet 1. General description 2. Features 3. Ordering information The 74HC1G09 is a high-speed Si-gate CMOS device. The 74HC1G09 provides the 2-input ND function
74HC1GU04GV. 1. General description. 2. Features. 3. Ordering information. Marking. 5. Functional diagram. Inverter
Rev. 5 1 July 27 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. It provides an inverting single stage function. The standard output
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MMBZ5xxBLT Series, SZMMBZ5xxBLTG Series Zener Voltage Regulators 5 mw SOT Surface Mount This series of Zener diodes is offered in the convenient, surface mount plastic SOT package. These devices are designed
The 74LVC1G11 provides a single 3-input AND gate.
Rev. 0 September 200 Product data sheet 1. General description 2. Features The is a high-performance, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The input
SN74LS132MEL. Quad 2 Input Schmitt Trigger NAND Gate LOW POWER SCHOTTKY
Quad 2 Input Schmitt Trigger NAND Gate The SN74LS32 contains four 2-Input NAND Gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly
74VHC00 Quad 2-Input NAND Gate
Quad 2-Input NAND Gate General Description The HC00 is an advanced high-speed CMOS 2-Input NAND Gate fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent
-202mA. Pin 1 D1. Diode. Part Number Case Packaging DMC21D1UDA-7B X2-DFN ,000/Tape & Reel
DMCDUDA COMPLEMENTARY PAIR ENHANCEMENT MODE MOSFET Product Summary Device BV DSS R DS(ON) max I D max T A = + C.99Ω @ V GS =.V ma Q V.Ω @ V GS =.V ma.8ω @ V GS =.8V 8mA.Ω @ V GS =.V 9mA Features and Benefits
DM74LS09 Quad 2-Input AND Gates with Open-Collector Outputs
August 1986 Revised March 2000 DM74LS09 Quad 2-Input AND Gates with Open-Collector Outputs General Description This device contains four independent gates each of which performs the logic AND function.
NL37WZ07. Triple Buffer with Open Drain Outputs
Triple Buffer with Open Drain Outputs The N7WZ7 is a high performance triple buffer with open drain outputs operating from a.6 to. supply. The internal circuit is composed of multiple stages, including
NPN/PNP low V CEsat Breakthrough in Small Signal (BISS) transistor pair in a SOT457 (SC-74) Surface Mounted Device (SMD) plastic package.
Rev. 02 14 July 2005 Product data sheet 1. Product profile 1.1 General description NPN/PNP low V CEsat Breakthrough in Small Signal (BISS) transistor pair in a SOT457 (SC-74) Surface Mounted Device (SMD)
MM74C906 Hex Open Drain N-Channel Buffers
Hex Open Drain N-Channel Buffers General Description The MM74C906 buffer employs monolithic CMOS technology in achieving open drain outputs. The MM74C906 consists of six inverters driving six N-channel
74HC02; 74HCT02. The 74HC02; 74HCT02 provides a quad 2-input NOR function.
Rev. 03 September 200 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin compatible
Quad bus transceiver; 3-state. The output enable inputs (OEA and OEB) can be used to isolate the buses.
Rev. 03 12 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The is specified in compliance
74AC153 74ACT153 Dual 4-Input Multiplexer
Dual 4-Input Multiplexer General Description The AC/ACT153 is a high-speed dual 4-input multiplexer with common select inputs and individual enable inputs for each section. It can select two lines of data
CD74HC147, CD74HCT147
Data sheet acquired from Harris Semiconductor SCHS149 September 1997 CD74HC147, CD74HCT147 High Speed CMOS Logic 10-to-4 Line Priority Encoder [ /Title (CD74 HC147, CD74 HCT14 7) /Subject (High Speed CMOS
74VHC244 Octal Buffer/Line Driver with 3-STATE Outputs
74VHC244 Octal Buffer/Line Driver with 3-STATE Outputs General Description The VHC244 is an advanced high speed CMOS octal bus buffer fabricated with silicon gate CMOS technology. It achieves high speed
DM74LS08 Quad 2-Input AND Gates
DM74LS08 Quad 2-Input AND Gates General Description This device contains four independent gates each of which performs the logic AND function. Ordering Code: August 1986 Revised March 2000 Order Number
MM74HC540 MM74HC541 Inverting Octal 3-STATE Buffer Octal 3-STATE Buffer
September 1983 Revised February 1999 MM74HC540 MM74HC541 Inverting Octal 3-STATE Buffer Octal 3-STATE Buffer General Description The MM74HC540 and MM74HC541 3-STATE buffers utilize advanced silicon-gate
Low Voltage 2-1 Mux, Level Translator ADG3232
Low Voltage 2-1 Mux, Level Translator ADG3232 FEATURES Operates from 1.65 V to 3.6 V Supply Rails Unidirectional Signal Path, Bidirectional Level Translation Tiny 8-Lead SOT-23 Package Short Circuit Protection
1-A Dual-HBD (Dual-Half-Bridge Driver) TLE4207G
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CD4071BC CD4081BC Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate
Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate General Description The CD4071BC and CD4081BC quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed
74AHC86; 74AHCT86. Quad 2-input EXCLUSIVE-OR gate. The 74AHC86; 74AHCT86 provides a 2-input exclusive-or function.
Rev. 02 5 November 2007 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They
MM74HC374 3-STATE Octal D-Type Flip-Flop
3-STATE Octal D-Type Flip-Flop General Description The MM74HC374 high speed Octal D-Type Flip-Flops utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power consumption
74HC1G02; 74HCT1G02. The standard output currents are half those of the 74HC02 and 74HCT02.
Rev. 04 11 July 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G02 and 74HCT1G02 are high speed Si-gate CMOS devices. They provide a 2-input NOR function. The HC
DM74S373 DM74S374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops General Description These 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or