Nvidia N12P-GE N12P-GV1 N12P-GV. PCI-Express. Graphics Interfaces PG 15,16,17,18,19,20,21 INT_HDMI INT_CRT INT_LVDS

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1 KL Intel Huron River Platform with iscrete GFX 0 FN / THERML EM0- RIII-SOIMM PG RIII-SOIMM PG Speaker PG udio Jack (External MI) PG Head-Phone Jack PG ual hannel R /00.V ST - H USeST PG ST - -ROM UIO OE L -MI PG PG PG PG R SYSTEM MEMORY ST 0M ST 0M ST 0M PG,,, IH <MH Process> Sandyridge 0. rpg FI FI PH MI MI ougarpoint 0. PG,,,0,, MIX PI-E Graphics Interfaces US.0 PI-E PI-Express Port,, Port Port US.0 Ports X X Mini PI-E ard (WLN) luetooth Nvidia NP-GE NP-GV NP-GV INT_RT INT_LVS X LN Mini PI-E ard X Realtek (0/00/G LN) p PG,,,,,0, INT_HMI PG PG PG 0 MHz HMI ON PG L ONN PG Port RT PG amera PG Port 0 ard Reader RTS PGE REGULTOR (R).VSUS, 0.VSMR_VTERM,.V.V_GPU,.V_PU REGULTOR.0V_VTT,.V / VPU, VPU, V PU ore VG ore iscrete PG PG PG.KHz LP RTLE-V-GR RTL0E PGE 0 PGE -IN- ard Reader ONN PG E MHz IT PGE PROJET : KL Quanta omputer Inc. Size ocument Number Rev ustom LOK IGRM ate: Friday, October, 00 Sheet of

2 0 PGE ESRIPTION Schematic lock iagram LOK GENERTOR PineView PU RII SO-IMM 0 Front Page TigerPoint L onn Table of ontents RT onn. udio odec X0 LN(RTL0EL/L) ST H US x ardreader U MINI-ard (WLN) MINI-ard ( WWN) LUETOOTH K/TP SW/LE/Other FN & Thermal K IT0E HOL & SKEW ischarge harger R.V (TPS) VP (OZLN) V/V (ISL) Vore (ISL) V.V/ GFX ORE Power lock ianram POWER PLNE VRT VPU VPU V LNV VSUS V.V.0V VOLTGE,0,,,0,0,,,0,,,, PGE,,,,,,,,0,,,,0,,,,,,,,,,,,,,,0,,,,,,,,,,,,,,,0, ESRIPTION MIN POWER ONTROL SIGNL VV_EN VV_EN VV_EN LN_ON V_S V,0,0 PH SUS POWER S_ON V_S.V,,,,,0 Sys Management,PH Resume S_ON Well,Intel H udio,us,wln WiMX POWER VSUS 0.VSMR_VTERM V.V 0V~0V.0V~.V.V V V.V V.V 0.V V.V.V.V.0V,0,,,,,,,,,,,,,0,,,,0,,,,,,, Power States RT ITE0 POWER / POWER I SOURE LRGE POWER LN POWER SLP_S# TRL POWER SLP_S# TRL POWER R SOIMM REFERENE POWER SLP_S# TRL POWER SLP_S# TRL POWER LVS,NVM POWER Mini PIe,Express ard POWER SUSON SUSON MIN_ON MIN_ON MIN_ON MIN_ON MIN_ON MIN_ON TIVE IN V_GFX_ORE 0.V~.V, VG ORE POWER MIN_ON S0 V_ORE,0, PH ORE POWER PU ORE POWER LV.V L Power L_V_EN S0 T-V 0V~V MIN TTERY VRON HG_PTT S0~S S0~S S0~S S0~S S0~S S0~S S0~S S0~S S0~S S0 S0 S0 S0 S0 S0 S0 S0~S PROJET : KL Quanta omputer Inc. Size ocument Number Rev ustom Front page Friday, October, 00 ate: Sheet of

3 MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP FI_TXN0 FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXP0 FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_FSYN0 FI_FSYN FI_INT FI_LSYN0 FI_LSYN ep_omp Sandy ridge Processor (MI,PEG,FI) INT_eP_HP_Q ep_omp connect to PIN W:mils/S:mils/L: 00mils. ep_omp connect to PIN W:mils/S:mils/L: 00mils. G E F G F0 H E F 0 E G E0 G 0 F J J H0 J H F G E F U MI_RX#[0] MI_RX#[] MI_RX#[] MI_RX#[] MI_RX[0] MI_RX[] MI_RX[] MI_RX[] MI_TX#[0] MI_TX#[] MI_TX#[] MI_TX#[] MI_TX[0] MI_TX[] MI_TX[] MI_TX[] FI0_TX#[0] FI0_TX#[] FI0_TX#[] FI0_TX#[] FI_TX#[0] FI_TX#[] FI_TX#[] FI_TX#[] FI0_TX[0] FI0_TX[] FI0_TX[] FI0_TX[] FI_TX[0] FI_TX[] FI_TX[] FI_TX[] FI0_FSYN FI_FSYN FI_INT FI0_LSYN FI_LSYN ep_ompio ep_iompo ep_hp ep_ux ep_ux# ep_tx[0] ep_tx[] ep_tx[] ep_tx[] ep_tx#[0] ep_tx#[] ep_tx#[] ep_tx#[] PU-P-rPG MI Intel(R) FI ep PI EXPRESS* - GRPHIS PEG_IOMPI PEG_IOMPO PEG_ROMPO PEG_RX#[0] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[0] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX[0] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[0] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_TX#[0] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[0] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX[0] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[0] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] J J H K M L J J H H G G0 F E E J L K H H G G F F0 E E F E M M M L L K K J0 J H G E F F E M M M0 L L K0 K J J H G E F E PEG_RXN0 PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN0 PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXP0 PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP0 PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_TXN0_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN0_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXP0_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP0_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_OMP PEG_OMP connect to PIN H&J W:mils/S:mils/L: 00mils. PEG_OMP connect to PIN J W:mils/S:mils/L: 00mils. PEG_RXN[0..] PEG_RXP[0..],,, PLTRST# U0 N IN, 0 0 SN_IV# N. at SN ES # 0.v H_SN_IV# E_PEI H_PROHOT# PM_THRMTRIP# V GNOUT PM_SYN H_PWRGOO.0V_PH PU_PLTRST# V_S LVG0GW 0.U/0V_ R R0 0 PU_PLTRST# R R R R TP TP /J_ *0 short *0 short 0K/J_ *0.U/0V_ /J_ /J_, SKTO# TP_TERR# H_PROHOT#_R PM_SYN_R H_PWRGOO_R PM_RM_PWRG_R PU_PLTRST#_R SYS_PWROK PM_RM_PWRG Sandy ridge Processor (LK,MIS,JTG) RV *EG-00 N L N L N M P V R U PRO_SELET# SKTO# TERR# PEI PROHOT# THERMTRIP# PM_SYN UNOREPWRGOO SM_RMPWROK RESET# PU-P-rPG R R 0/J_ *0/J_ MIS THERML PWR MNGEMENT V_S LOKS R MIS JTG & PM U *0.U/0V_ R0 *HG0GW LK LK# PLL_REF_LK PLL_REF_LK# SM_RMRST# SM_ROMP[0] SM_ROMP[] SM_ROMP[] PRY# PREQ# TK TMS TRST# TI TO R# PM#[0] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] PM_RM_PWRG_Q */J_ R K P P R R P0 R P L T R R0 T0 P R T R.V_PU R0 00/F_ R LK_PLL_SSLKP_R LK_PLL_SSLKN_R SM_ROMP_0 SM_ROMP_ SM_ROMP_ XP_PRY# XP_PREQ# XP_TLK XP_TMS XP_TRST# XP_TI_R XP_TO XP_RST# R R R R R LK_PU_LKP LK_PU_LKN R Rb Rc Ra *IS@0/J_ *IS@0/J_ PU_RMRST# 0/F_./F_ 00/F_ PM_RM_PWRG_R SW@0X.0V_PH SM_ROMP[0] W:0mils/S:0mils/L: 00mils, SM_ROMP[] W:0mils/S:0mils/L: 00mils, SM_ROMP[] W:mils/S:0mils/L: 00mils, 0/F_ TP TP TP TP TP TP TP XP_RST# LK_PLL_SSLKP LK_PLL_SSLKN Ra Rb Rc IS N 0 ohm 0 ohm 0 SW/UM 0 ohm N N PM_RM_PWRG_Q R *K/F_ Q0 *N00K MINON#, FI isable R0 *IS@K/F_ R R0 R R *IS@K/F_ *IS@0/J_ *IS@0/J_ *IS@0/J_ FI_INT FI_FSYN0 FI_FSYN FI_LSYN0 FI_LSYN FI_FSYN can gang all these signals together and tie them with only one K resistor to GN (G V0. h..). PEG x (UM Non-stuff) PEG_TXP[0..] PEG_TXP0_ 0 IS@0.U/0V_ PEG_TXP0 PEG_TXN0_ PEG_TXP_ IS@0.U/0V_ PEG_TXP PEG_TXN_ PEG_TXP_ IS@0.U/0V_ PEG_TXP PEG_TXN_ PEG_TXP_ IS@0.U/0V_ PEG_TXP PEG_TXN_ PEG_TXP_ IS@0.U/0V_ PEG_TXP PEG_TXN_ PEG_TXP_ IS@0.U/0V_ PEG_TXP PEG_TXN_ PEG_TXP_ IS@0.U/0V_ PEG_TXP PEG_TXN_ PEG_TXP_ IS@0.U/0V_ PEG_TXP PEG_TXN_ PEG_TXP_ IS@0.U/0V_ PEG_TXP PEG_TXN_ PEG_TXP_ 0 IS@0.U/0V_ PEG_TXP PEG_TXN_ PEG_TXP0_ IS@0.U/0V_ PEG_TXP0 PEG_TXN0_ PEG_TXP_ IS@0.U/0V_ PEG_TXP PEG_TXN_ PEG_TXP_ IS@0.U/0V_ PEG_TXP PEG_TXN_ PEG_TXP_ IS@0.U/0V_ PEG_TXP PEG_TXN_ PEG_TXP_ 0 IS@0.U/0V_ PEG_TXP PEG_TXN_ PEG_TXP_ IS@0.U/0V_ PEG_TXP PEG_TXN_ IS@0.U/0V_ PEG_TXN0 IS@0.U/0V_ PEG_TXN IS@0.U/0V_ PEG_TXN IS@0.U/0V_ PEG_TXN IS@0.U/0V_ PEG_TXN IS@0.U/0V_ PEG_TXN IS@0.U/0V_ PEG_TXN IS@0.U/0V_ PEG_TXN IS@0.U/0V_ PEG_TXN IS@0.U/0V_ PEG_TXN IS@0.U/0V_ PEG_TXN0 IS@0.U/0V_ PEG_TXN IS@0.U/0V_ PEG_TXN IS@0.U/0V_ PEG_TXN IS@0.U/0V_ PEG_TXN IS@0.U/0V_ PEG_TXN PEG_TXN[0..] P & PEG ompensation.0v_ph.0v_ph.0v_ph R./F_ PEG_OMP PEG_IOMPI and ROMPO signals should be routed within 00 mils typical impedance = mohms PEG_IOMPO signals should be routed within 00 mils typical impedance =. mohms R R 0K_./F_ INT_eP_HP_Q ep_omp ep_ompio and IOMPO signals should be shorted near balls and routed with typical impedance < mohms Processor pull-up(pu).0v_ph H_PROHOT# R /F_ XP_TO R /J_ XP_TMS R /J_ XP_TI_R R0 /J_ XP_PREQ# R */J_ XP_TLK R /J_ XP_TRST# R /J_ PROJET : KL Quanta omputer Inc. Size ocument Number Rev Sandy ridge / ate: Sheet of Friday, October, 00

4 Sandy ridge Processor (R) 0 U U M Q[:0] M S#0 M S# M S# M S# M RS# M WE# M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q F0 F G0 G F F G G K K K J J J J K M N0 N N M0 M N M G G K K H H J J J K J K H H L L P N L M M L P N J H L K L K J H E0 F0 V E F S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_S[0] S_S[] S_S[] S_S# S_RS# S_WE# R SYSTEM MEMORY S_LK[0] S_LK#[0] S_KE[0] S_LK[] S_LK#[] S_KE[] RSV_TP[] RSV_TP[] RSV_TP[] RSV_TP[] RSV_TP[] RSV_TP[] S_S#[0] S_S#[] RSV_TP[] RSV_TP[] S_OT[0] S_OT[] RSV_TP[] RSV_TP[0] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] V V0 W W0 K L G H H G G H G J M L M R M F K N L M R M 0 W W W V V W W V W V W F V V M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP M 0 M M M M M M M M M M 0 M M M M M M LKP0 M LKN0 M KE0 M LKP M LKN M KE M S#0 M S# M OT0 M OT M QSN[:0] M QSP[:0] M [:0] M Q[:0] M S#0 M S# M S# M S# M RS# M WE# M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q 0 G F F G G F F G J J K0 K J J0 K K M N N N M N M M M M R P N N N P P N T T P N R R R J T T H R J H T N R T T N R T R 0 S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_S[0] S_S[] S_S[] S_S# S_RS# S_WE# R SYSTEM MEMORY S_LK[0] S_LK#[0] S_KE[0] S_LK[] S_LK#[] S_KE[] RSV_TP[] RSV_TP[] RSV_TP[] RSV_TP[] RSV_TP[] RSV_TP[] S_S#[0] S_S#[] RSV_TP[] RSV_TP[] S_OT[0] S_OT[] RSV_TP[] RSV_TP[0] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] E R E R0 T T0 E E E E F K N N P K P G J M N P K P T R T T T T R T R R T 0 R R M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP M 0 M M M M M M M M M M 0 M M M M M M LKP0 M LKN0 M KE0 M LKP M LKN M KE M S#0 M S# M OT0 M OT M QSN[:0] M QSP[:0] M [:0] PU-P-rPG PU-P-rPG.V_SUS R0 K/F_ R0 *0/J_, R_RMRST# R0 K/F_ PU_RMRST#_R PU_RMRST# RMRST_NTRL_PH R00 *0 short Q N00K 0.0U/0V_ R.K/F_ PROJET : KL Quanta omputer Inc. Size ocument Number Rev Sandy ridge / ate: Friday, October, 00 Sheet of

5 U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ 0 U/.V_ U/.V_ 0 U/.V_ Reserved *U/.V_ PU ore Power SN W: uf x uf x (Non-stuff) U/.V_ 00 U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ *U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ 0 U/.V_ 0 U/.V_ U/.V_ U/.V_ *U/.V_ 0 U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ 0 U/.V_ U/.V_ Sandy ridge Processor (POWER) V_ORE G G G G G G0 G G G G F F F F F F0 F F F F Y Y Y Y Y Y0 Y Y Y Y V V V V V V0 V V V V U U U U U U0 U U U U R R R R R R0 R R R R P P P P P P0 P P P P UF V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V00 POWER ORE SUPPLY SENSE LINES SVI PEG N R VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO0 VILERT# VISLK VISOUT V_SENSE VSS_SENSE VIO_SENSE VSSIO_SENSE H H0 G0 0 Y0 U0 P0 L0 J J J J H H H G G G F F F F E E E J J J0 J J J 0 0.0V_PH.0V_VTT_0 H_PU_SVILRT# H_PU_SVILK H_PU_SVIT PU VTT SN W:. uf x 0 uf x (Non-stuff) U/.V_ *U/.V_ *U/.V_ 0U/.V_ *U/.V_ VTT_SENSE TP0 uf (Reserved) *U/.V_ R U/.V_ U/.V_ *0/short_ R R00,, *U/.V_ U/.V_ 0U/.V_ 00/J_ 00/J_ SMR_VREF U/.V_ 0 0U/.V_ *U/.V_.0V_PH PU VPL SN W: 0uF/mohm x 0uF x uf x V_ORE V_SENSE VSS_SENSE.V PU VGT SN W: VR_REF_PU IS Ra 0 ohm Sandy ridge Processor (GRPHI POWER) SW N Layout note: need routing together and LERT need between LK and T H_PU_SVILK Place PU resistor close to PU H_PU_SVIT.0V_PH PU-P-rPG Place PU resistor close to PU POWER uf x UG TP uf x (Reserved) R 00/J_ V_GFX V_GFX T K VXG VXG_SENSE V_XG_SENSE T K VXG VSSXG_SENSE VSS_XG_SENSE T R0 00/J_ VXG T0 U/.V_ U/.V_ U/.V_ U/.V_ VXG T VXG TP T VXG R VXG R VXG R VXG R0 U/.V_ VXG0 R VXG R VXG P L VR_REF_PU VXG SM_VREF VR_REF_PU 0 P U/.V_ U/.V_ U/.V_ U/.V_ VXG P Note: VR_REF_PU should VXG P0 VXG have 0 mil trace width P VXG P VXG PU MH N VXG N VXG0 SN W: N U/.V_ VXG N0 VXG 0uF/mohm x N VXG N 0uF x U/.V_ U/.V_ U/.V_ U/.V_ VXG M F VXG VQ.V_PU M F VXG VQ M F VXG VQ M0 VXG VQ M 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ VXG VQ M VXG0 VQ L Y VXG VQ L Y VXG VQ L Y VXG VQ L0 U VXG VQ0 L U VXG VQ L U 0 *0U/V_ VXG VQ K P 0U/.V_ 0U/.V_ U/.V_ U/.V_ *U/.V_ *U/.V_ *U/.V_ *U/.V_ VXG VQ K P VXG VQ K P VXG VQ uf (Reserved) K0 VXG0 K VXG K VXG J VXG J VXG J VXG J0 VXG J VXG J VXG H VXG H VXG0 H M VXG VS 0.V H0 M VXG VS H L R Ra *IS@0/J_ VXG VS H J 0 0 VXG VS J 0U/.V_ 0U/.V_ 0U/.V_ *0U/.V_ VS J VS H VS H VS R0 *0/J_ 0U/.V_ U/.V_ U/.V_ *0U/V_ R R 0/F_ VPLL VPLL VPLL *0 short R GRPHIS.V RIL *0 short.0v_ph.0v_ph SENSE LINES S RIL R -.V RILS VREF MIS SVI LK lose to VR R./F_ VR_SVI_LK SVI T lose to VR R 0/F_ VS_SENSE F_ VS_VI VR_SVI_T SVI LERT H H_F_ R R 0K/J_ 0K/J_ MINON_V VUS_SENSE VS_SEL.V_SUS, MINON# PU S SN W:. 0uF/mohm x 0uF x Q O 0 *0P/0V_.V_PU R0 0/J_ Q MN0K- 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_.V_SUS / add for Intel. Placement close to PU. 0.0V_PH PU-P-rPG MINON_V Q N00K R 00K/J_ H_PU_SVILRT# R0 /J_ R0 /J_ R *0 short VR_SVI_LERT# PROJET : KL Quanta omputer Inc. Size ocument Number Rev Sandy ridge / ate: Sheet of Friday, October, 00

6 UH T VSS T VSS T VSS T VSS T VSS T VSS T VSS T VSS T VSS T0 VSS0 T VSS T VSS T VSS R VSS R VSS R VSS R VSS R VSS R0 VSS R VSS0 R VSS R VSS P VSS P VSS P VSS P VSS P VSS P VSS P VSS P VSS0 P0 VSS P VSS P VSS P VSS N0 VSS N VSS N VSS N VSS N VSS N VSS0 N VSS N0 VSS N VSS N VSS M VSS M VSS M VSS M VSS M VSS M VSS0 M0 VSS M VSS M VSS M VSS M VSS M VSS L VSS L VSS L VSS L VSS0 L VSS L VSS L VSS L VSS L0 VSS L VSS L VSS L VSS K VSS K0 VSS0 K VSS K VSS K VSS K VSS K VSS K VSS K0 VSS K VSS K VSS J VSS0 Sandy ridge Processor (GN) VSS UI VSS J VSS J VSS J T VSS VSS J T VSS VSS J0 T VSS VSS J T VSS VSS J T VSS VSS J T0 VSS VSS J T VSS VSS0 J T VSS VSS H T VSS VSS H T VSS0 VSS H P VSS VSS H0 P VSS VSS H P VSS VSS H P VSS VSS H P VSS VSS H P VSS VSS H N VSS VSS00 H N VSS VSS0 H N VSS VSS0 H N VSS0 VSS0 H N VSS VSS0 G N0 VSS VSS0 G N VSS VSS0 G N VSS VSS0 F N VSS VSS0 F N VSS VSS0 F M VSS VSS0 F L VSS VSS E L0 VSS VSS E L VSS0 VSS E L VSS VSS E L VSS VSS E L VSS VSS E0 L VSS VSS E L VSS VSS E L VSS VSS E L VSS VSS0 E L VSS VSS E K VSS VSS K VSS00 VSS K VSS0 VSS K VSS0 VSS J VSS0 VSS J VSS0 VSS H VSS0 VSS H0 VSS0 VSS H VSS0 VSS0 H VSS0 VSS H VSS0 VSS H VSS0 VSS H VSS VSS 0 H VSS VSS H0 VSS VSS H VSS VSS H VSS VSS H VSS VSS Y H VSS VSS0 Y H VSS VSS Y H VSS VSS Y H VSS0 VSS Y H VSS VSS Y H VSS VSS W G VSS VSS W G VSS VSS W G VSS VSS W G VSS VSS W G VSS VSS0 W0 G0 VSS VSS W G VSS VSS W G VSS0 VSS W F VSS VSS W F VSS VSS U F VSS VSS U VSS U VSS U VSS U VSS0 U VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS F F E0 E E E E E E E0 E E E E E E E E E SMR_VREF_Q0_M SMR_VREF_Q_M TP TP TP FG0 FG FG FG FG FG SMR_VREF_Q0_M SMR_VREF_Q_M Sandy ridge Processor (RESERVE, FG) R *K/J_ TP R *K/J_ UE K FG[0] K FG[] L FG[] L FG[] K FG[] L FG[] L0 FG[] M FG[] M FG[] M0 FG[] M FG[0] M FG[] N FG[] N FG[] N FG[] M FG[] K FG[] N FG[] J VXG_VL_SENSE H VSSXG_VL_SENSE J V_VL_SENSE H VSS_VL_SENSE J RSV RSV F RSV F RSV F RSV0 RSV G RSV G RSV E RSV RSV 0 RSV RSV 0 RSV RSV 0 RSV0 RSV 0 RSV RSV J0 RSV RSV VIO_SEL J RSV RSV PU-P-rPG RESERVE RSV L RSV G RSV0 E RSV K RSV W RSV T RSV M RSV J RSV T RSV J RSV H RSV0 G RSV R RSV T RSV T RSV P RSV R RSV RSV RSV RSV RSV0 RSV J RSV K V_IE_SENSE RSV T RSV T RSV R KEY H RSV N TP RSV M TP Reserved for Intel ebug For rpg socket, RSV pin should be left N 0 PU-P-rPG PU-P-rPG Processor Strapping FG (PEG Static Lane Reversal) The FG signals have a default value of '' if not terminated on the board. Normal Operation 0 Lane Reversed FG FG FG R R R K/F_ *K/F_ *K/F_ FG FG R R *K/F_ *K/F_ FG[:] (PIE Port ifurcation Straps) : (efault) x - evice functions and disabled 0: x, x - evice function enabled ; function disabled 0: Reserved - (evice function disabled ; function enabled) 00: x,x,x - evice functions and enabled FG (P Presence Strap) FG (PEG efer Training) isable; No physical P attached to ep PEG train immediately following xxreset de assertion Enable; n ext P device is connected to ep PEG wait for IOS training PROJET : KL Quanta omputer Inc. Size ocument Number Rev Sandy ridge / ate: Friday, October, 00 Sheet of

7 ougar Point (LVS,I) 0 SUS_PWR_K_R E_PWROK_R MI_OMP MI_RIS XP_RST# PIE_WKE# XP_RST# K SYS_RESET# WKE# PIE_WKE#,, SYS_PWROK *U/.V_ PM_RM_PWRG E_PWROK RSMRST# SUS_PWR_K SIO_PWRTN#.0V_PH MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP R R0 R R R R R R./F_ 0/F_ *0/J_ *0 shortsys_pwrok_r *0/J_ *0 shorte_pwrok_r *0 shortpwrok_r PM_RM_PWRG RSMRST# *0 shortsus_pwr_k_r ougar Point (MI,FI,PM) U E0 G G0 E 0 J J0 W W0 V Y Y0 Y U J G H P L L0 K E0 MI0RXN MIRXN MIRXN MIRXN MI0RXP MIRXP MIRXP MIRXP MI0TXN MITXN MITXN MITXN MI0TXP MITXP MITXP MITXP MI_ZOMP MI_IROMP MIRIS SUSK# SYS_PWROK PWROK PWROK RMPWROK RSMRST# MI System Power Management V V_S V_S V_S FI FI_RXN0 FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXP0 FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_INT FI_FSYN0 FI_FSYN FI_LSYN0 FI_LSYN SLP_S# / GPIO SLP_S# SUSWRN#/SUSPWRNK/GPIO0 V_S SLP_S# PWRTN# SWVRMEN PWROK LKRUN# / GPIO SUS_STT# / GPIO SUSLK / GPIO SLP_# J Y E H J G0 G G F G E G J0 H W V 0 V 0 E N G N 0 H F G0 R SWVREN LKRUN# LP_P# PH_SUSLK SLP_S# SLP_# *0 short R0 PWROK FI_TXN0 FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXP0 FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_INT FI_FSYN0 FI_FSYN FI_LSYN0 FI_LSYN *0 short RSMRST# T0 T T T LKRUN# PM_SLP_S# SIO_SLP_S# INT_RT_HSYN INT_RT_VSYN INT_LVS_LON INT_LVS_VEN LVS_RIGHT_PWM INT_EILK INT_EIT INT_TXLLKOUTN INT_TXLLKOUTP R V INT_TXLOUTN0 INT_TXLOUTN INT_TXLOUTN INT_TXLOUTP0 INT_TXLOUTP INT_TXLOUTP INT_RT_LU INT_RT_GRE INT_RT_RE INT_LK INT_T R R0 0ohm for SW; ohm for UM R R.K/F_ /J_ /J_ INT_EILK INT_EIT T LV_IG INT_TXLLKOUTN INT_TXLLKOUTP INT_TXLOUTN0 INT_TXLOUTN INT_TXLOUTN INT_TXLOUTP0 INT_TXLOUTP INT_TXLOUTP INT_RT_LU INT_RT_GRE INT_RT_RE INT_RT_HSYN_R INT_RT_VSYN_R _IREF R K/F_.K/J_.K/J_ J M P T0 K T P F F E E K K0 N M K J N M K J F0 F H H F F H H F F N P T T M0 M M T T U L_KLTEN L_V_EN L_KLTTL L LK L T L_TRL_LK L_TRL_T LV_IG LV_VG LV_VREFH LV_VREFL LVS_LK# LVS_LK LVS_T#0 LVS_T# LVS_T# LVS_T# LVS_T0 LVS_T LVS_T LVS_T LVS_LK# LVS_LK LVS_T#0 LVS_T# LVS_T# LVS_T# LVS_T0 LVS_T LVS_T LVS_T RT_LUE RT_GREEN RT_RE RT LK RT T RT_HSYN RT_VSYN _IREF RT_IRTN ougarpoint_rp0 LVS RT igital isplay Interface SVO_TVLKINN SVO_TVLKINP SVO_STLLN SVO_STLLP SVO_INTN SVO_INTP SVO_TRLLK SVO_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P P M M0 P P0 P M T T T0 V V0 V V U U V V P P P P T Y Y Y Y M M T T H F E F E J G INT_HMI_HP_Q P_HP_PU P_HP_PU V INT_HMI_SL INT_HMI_S INT_HMI_TXN INT_HMI_TXP INT_HMI_TXN INT_HMI_TXP INT_HMI_TXN0 INT_HMI_TXP0 INT_HMI_TXN INT_HMI_TXP INT. HMI INT. P _PRESENT R *0 short_present_r PM_TLOW# PM_RI# H0 E0 0 PRESENT / GPIO SW TLOW# / GPIO V_S RI# V_S SLP_SUS# PMSYNH SLP_LN# / GPIO G P K SLP_LN# T T PM_SYN R R R place close to PH 0/F_ 0/F_ INT_RT_LU INT_RT_GRE INT_HMI_HP_Q R *00K/J_ Q N00K INT_HMI_HP R 00K/J_ ougarpoint_rp0 R0 0/F_ INT_RT_RE PH Pull-high/low(LG) V V_S LKRUN# R.K/J_ PM_RI# R 0K/J_ XP_RST# R 0K/J_ PM_TLOW# R0.K/J_ R *K/J_ PIE_WKE# R0 0K/J_ RSMRST# R 0K/J_ SLP_LN# R *0K/J_ SYS_PWROK R0 00K/J_ SUS_PWR_K R 0K/J PRESENT R 0K/J_ PM_RM_PWRG R *00/F_ System PWR_OK(LG) U0, SYS_PWROK SYS_PWROK TSH0 V_S *0.U/0V_ IMVP_PWRG E_PWROK R 00K/J_ V_RT R0 0K/J_ SWVREN R *0K/J_ On ie SW VR Enable High = Enable (efault) Low = isable PWROK FOR SW VPU VPU V_SW R R *0K_ *0K_ V_S *R00V-0 VPU *R00V-0 Q *PTEU Q *N00 PWROK *0.U/0V_ V P_HP_PU R 0K/J_ P_HP_PU R 0K/J_ Follow PG ep disable guide PROJET : KL Quanta omputer Inc. Size ocument Number Rev ougar Point / ate: Sheet of Friday, October, 00

8 RT ircuitry(rt) 0mils V_SW R *0/J_ V_RT R0 0/J_ V_RT_ VPU R 0K/J_ V_RT_ V_RT_0 0MIL T U/.V_ 0mils R0 K/J_ R 0K/J_ U/.V_ U/.V_ 0MIL T T_ONN H us(lg) To Separate odec Sync by P Z_ITLK R /J_ Z_ITLK_R Z_SYN R /J_ Z_SYN_OE Z_RST# R /J_ Z_RST#_R Z_SYN_OE Z_SOUT R /J_ Z_SOUT_R Q PH JTG ebug (LG) V_S RT_RST# J *SHORT_ P SRT_RST# J *SHORT_ P V Z_SYN_R N00 PH(LG) 0 P/0V_ P/0V_ V_RT Y.KHZ SPKR Z_SIN0 INTEL_T_OFF# 0 R V_S OR_I R 0M/J_ M/J_ R TP TP TP TP0 RT_X RT_X RT_RST# SRT_RST# SM_INTRUER# PH_INVRMEN Z_ITLK_R Z_SYN_R SPKR Z_RST#_R Z_SOUT_R 0K/J_ TP0 OR_I PH_JTG_TK_R PH_JTG_TMS_R PH_JTG_TI_R PH_JTG_TO_R ougar Point (H,JTG,ST) G K N L T0 K E G N J H K H U RTX RTX RTRST# SRTRST# INTRUER# INTVRMEN H_LK H_SYN SPKR H_RST# H_SIN0 H_SIN H_SIN H_SIN H_SO RT IH H_OK_EN# / GPIO H_OK_RST# / GPIO JTG_TK JTG_TMS JTG_TI JTG_TO JTG ST LP ST G V V V_S FWH0 / L0 FWH / L FWH / L FWH / L FWH / LFRME# LRQ0# LRQ# / GPIO SERIRQ ST0RXN ST0RXP ST0TXN ST0TXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STIOMPO STIOMPI STROMPO E K V M M P P M0 M P P0 H H 0 F F Y Y Y Y Y Y0 L_K_OFF ST_OMP LP_L0, LP_L, LP_L, LP_L, LP_LFRME#, LP_RQ#0 L_K_OFF# IRQ_SERIRQ, Remove ST port / R./F_.0V_PH ST_RXN ST_RXP ST_TXN_ ST_TXP_ ST_RXN ST_RXP ST_TXN_ ST_TXP_ ST_RXN ST_RXP ST_TXN_ ST_TXP_ IRQ_SERIRQ O_PRSNT# L_K_OFF# ST_T# INTEL_T_OFF# ST H ST O EST # R R R R00 R 0 V.K/J_ *0K/J_ 0K_ 0K_ 0K_ R *0/F_ R *0/F_ R *0/F_ STOMPI ST_OMP R./F_ R *00/F_ R *00/F_ PH_JTG_TMS_R PH_JTG_TI_R PH_JTG_TO_R PH_JTG_TK_R R0 R *00/F_ */J_ *0P/0V/OG_ S0 PH_SPI_LK RF request PH Strap Table PH_SPI_LK PH_SPI_S0# VPU R0 *0K/J_ PH_SPI_SI PH_SPI_SO PH_SPI_LK PH_SPI_S0# PH_SPI_S# PH_SPI_SI PH_SPI_SO T SPI_LK Y SPI_S0# T SPI_S# V SPI_MOSI U SPI_MISO ougarpoint_rp0 SPI V V STRIS STLE# ST0GP / GPIO STGP / GPIO H P V P ST_RIS ST_T# S_IT0 R 0/F_ ST_T# O_PRSNT# PH ual SPI (LG) Mbit (M yte), SPI PH_SPI_S0# PH_SPI_LK PH_SPI_SI PH_SPI_SO R R R /J_ /J_ /J_ MXL0MI-G: KEFP0Z00 WXVSSIG: KEZP0N00 Socket: G PH_SPI_LK_R PH_SPI_SI_R PH_SPI_SO_R *P/0V_ U E# SK SI SO WP# MXL0 V HOL# VSS R V_PH_SPI.K/J_ 0.U/0V_ Pin Name Strap description Sampled onfiguration 0 = efault (weak pull-down 0K) SPKR No reboot mode setting PWROK = Setting to No-Reboot mode GNT# / GPIO GNT# / GPIO GPIO Top-lock Swap Override oot IOS Selection [bit-] oot IOS Selection 0 [bit-0] PWROK PWROK PWROK 0 = "top-block swap" mode = efault (weak pull-up 0K) INTVRMEN Integrated.0V VRM enable LWYS Should be always pull-up GNT# 0 GNT0# 0 oot Location SPI LP * V V_RT R R R *K/J_ *K/J_ SPKR PI_GNT# PH_INVRMEN efault weak pull-up on GNT0/# [Need external pull-down for LP IOS] R0 R 0K/J_ *K/J_ *K/J_ S_IT S_IT0 V_PH_SPI R.K/J_ H_SO Flash escriptor Security RSMRST 0 = Override = efault (weak pull-up 0K) V_S R *K/J_ Z_SOUT_R V V_PH_SPI V_S R 0/J_ R *0/J_ F_TVS GPIO MI/FI Termination voltage On-die PLL Voltage Regulator PWROK RSMRST# 0 = Set to Vss = Set to Vcc (weak pull-down 0K) 0 = isable = Enable (efault) R R R *K/J_.K/J_.K/J_.V PLL_OVR_EN 0 F_TVS 0 H_SN_IV# H_SYN On-ie PLL VR Voltage Select RSMRST 0 = Support by.v (weak pull-down) = Support by.v V_S R K/J_ Z_SYN_R GPIO Integrated lock hip Enable RSMRST# Should be pull-down (weak pull-up 0K) SPI_MOSI itpm function isable PWROK 0 = efault (weak pull-down 0K) = Enable V R *K/J_ PH_SPI_SI NV_LE Intel nti-theft H protection PWROK 0 = isable (Internal pull-down 0kohm) PROJET : KL Quanta omputer Inc. Size ocument Number Rev ougar Point / ate: Sheet of Friday, October, 00

9 , O_M# LK_PI_ LK_LP_EUG LK_PI_F GPU Power ON RF_ON S_IT T_IS PI_GNT# R R R R TP *0_ /J_ /J_ /J_ PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# GPU_HOL_RST# RF_ON GPU_PWR_EN# S_IT T_IS PI_GNT# MP_PWR_TRL# O_M_R# EXTTS_SNI_RV0_PH EXTTS_SNI_RV_PH PI_PLTRST# RV *EG-00 LK_PI_E_R LK_PI_LP_R LK_PI_F_R ougar Point-M (PI,US,NVRM) G J H J G H H K K N0 H H M M Y K L M0 Y G E 0 E J E0 F G V U Y0 U Y V W0 K0 K H G E0 E F G G0 K0 H H J K H0 UE TP TP TP TP TP TP TP TP TP TP0 TP TP TP TP TP TP TP TP TP TP0 TP TP TP TP TP TP TP TP TP TP0 TP TP TP TP TP TP TP TP TP TP0 PIRQ# PIRQ# PIRQ# PIRQ# REQ# / GPIO0 REQ# / GPIO REQ# / GPIO GNT# / GPIO GNT# / GPIO GNT# / GPIO PIRQE# / GPIO PIRQF# / GPIO PIRQG# / GPIO PIRQH# / GPIO PME# PLTRST# LKOUT_PI0 LKOUT_PI LKOUT_PI LKOUT_PI LKOUT_PI ougarpoint_rp0 RSV PI V V V V V V V V V V US V_S V_S V_S V_S V_S V_S V_S V_S RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV RSV RSV RSV RSV USP0N USP0P USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USP0N USP0P USPN USPP USPN USPP USPN USPP USRIS# USRIS O0# / GPIO O# / GPIO0 O# / GPIO O# / GPIO O# / GPIO O# / GPIO O# / GPIO0 O# / GPIO Y V U G T0 U T T T Y T V V E F V V0 T Y T F K H E N M L0 K0 G0 E0 0 0 L K G E K0 L NV_LE USP0- USP0 USP- USP USP- USP USP- USP USP- USP USP- USP USP0- USP0 USP- USP US_IS US_O0# US_O# US_O# US_O# US_O# US_O# US_O# US_O# R TP USP0- USP0 USP- USP USP- USP USP- USP USP- USP USP- USP USP- USP USP0-0 USP0 0./F_ US_O0# US_O# US_O# US_O# US/eST ombo #(Phoenix debug) US#0-> L port((ios debug) WLN WWN(common design reserved) luetooth US#-->R port(right side) US #-->R port(&ios debug) ard Reader US port,disable for HM. LK_M_R_ LK_FLEX LK_PI_F_R LK_PI_LP_R LK_PI_E_R LK_PH_M LK_UF_LKN LK_UF_LKP LK_UF_PIE_GPLLN LK_UF_PIE_GPLLP LK_UF_REFLKN LK_UF_REFLKP LK_UF_REFSSLKN LK_UF_REFSSLKP EHI EHI S0 S0 S0 S S S S S S S S S S0 S RF request LN WLN US.0 *0P/0V/OG_ *0P/0V/OG_ *0P/0V/OG_ *0P/0V/OG_ *0P/0V/OG_ *0P/0V/OG_ *0P/0V/OG_ *0P/0V/OG_ *0P/0V/OG_ *0P/0V/OG_ *0P/0V/OG_ *0P/0V/OG_ *0P/0V/OG_ *0P/0V/OG_ PIE_RXN_LN PIE_RXP_LN PIE_TXN_LN PIE_TXP_LN -0 PIE_RXN PIE_RXP PIE_TXN PIE_TXP PIE_RXN PIE_RXP PIE_TXN PIE_TXP 0 0 IS_ULE_LE TP TP 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ *0.U/0V_ *0.U/0V_ PIE_TXN_LN_ PIE_TXP_LN_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIELKRQ0# LKOUT_PIEN LKOUT_PIEP PIELKRQ# LKOUT_PIEN LKOUT_PIEP PIELKRQ# PIELKRQ# -0 LKOUT_PIEN LKOUT_PIEP PIELKRQ# PIELKRQ# IS_ULE_LE PIELKRQ# LK_PH_ITPN_R LK_PH_ITPP_R ougar Point-M (PI-E,SMUS,LK) G J V U E F Y G J V U F E Y G H Y J G U V G0 J0 Y0 0 E W Y Y0 Y J M V0 Y Y Y Y L V V L 0 E V0 V T V V K K K U PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP LKOUT_PIE0N LKOUT_PIE0P LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP ougarpoint_rp0 PI-E* PIELKRQ0# / GPIO PIELKRQ# / GPIO PIELKRQ# / GPIO0 PIELKRQ# / GPIO PIELKRQ# / GPIO PIELKRQ# / GPIO LKOUT_PEG N LKOUT_PEG P PEG LKRQ# / GPIO LKOUT_PIEN LKOUT_PIEP PIELKRQ# / GPIO LKOUT_PIEN LKOUT_PIEP PIELKRQ# / GPIO LKOUT_ITPXP_N LKOUT_ITPXP_P V_S V_S V V LOKS SMUS ontroller V_S V_S V_S V_S V_S V_S V_S V_S V_S SMLLERT# / PHHOT# / GPIO V_S SMLLK / GPIO V_S SMLT / GPIO Link V FLEX LOKS V V V SMLERT# / GPIO SMLK SMT SML0LERT# / GPIO0 SML0LK SML0T L_LK L_T L_RST# PEG LKRQ# / GPIO LKOUT_PEG N LKOUT_PEG P LKOUT_MI_N LKOUT_MI_P LKOUT_P_N LKOUT_P_P LKIN_MI_N LKIN_MI_P LKIN_GN_N LKIN_GN_P LKIN_OT_N LKIN_OT_P LKIN_ST_N LKIN_ST_P REFLKIN LKIN_PILOOPK XTL_IN XTL_OUT XLK_ROMP LKOUTFLEX0 / GPIO LKOUTFLEX / GPIO LKOUTFLEX / GPIO LKOUTFLEX / GPIO E H G E M M T P0 M0 V U M M F E J0 G0 G E K K K H V V Y K F H K SMLERT# SM_PH_LK SM_PH_T RMRST_NTRL_PH SM_ME0_LK SM_ME0_T SMLLERT#_R SM_ME_LK SM_ME_T L_LK L_T L_RST# PEG_LKREQ# LKOUT_PEG N LKOUT_PEG P LK_UF_PIE_GPLLN LK_UF_PIE_GPLLP LK_UF_LKN LK_UF_LKP LK_UF_REFLKN LK_UF_REFLKP LK_UF_REFSSLKN LK_UF_REFSSLKP LK_PH_M LK_PI_F XTL_IN XTL_OUT XLK_ROMP LK_FLEX LK_M_R_ R TP TP TP 0./F_ RMRST_NTRL_PH.0V_PH PEG_LKREQ# LK_PU_LKN LK_PU_LKP Mz support IS only TP0 TP R _ LK_PLL_SSLKN LK_PLL_SSLKP R M/J_ LK_M_R 0 0 Y MHZ 0 0 P/0V_ P/0V_ R0 V *IS@0_ V PEG LK detect SMus(LK) V,, GFXON U IS@TSH0FU(F) MINON,,,,,,,, IS@MEN00E Q R IS@K_ GPU_PWR_EN# SW: Stuff UM: Non-Stuff GFXPG 0, SM_PH_T V Q N00K R.K/J_ SM_RUN_T SM_RUN_T, PEG_LKREQ# PEX_LKREQ# R.K/J_ Q IS@MEN00E SM_PH_LK Q N00K SM_RUN_LK SM_RUN_LK, PLTRST#(LG) PI_PLTRST# GPU RST#(LG) V_S 0.U/0V_ PLTRST# U TSH0FU R 00K/J_ R *0_ PLTRST# PLTRST#,,, R *IS@0_ V 0 IS@0.U/0V_ PLTRST# GPU_HOL_RST# U IS@TSH0FU R IS@00K/J_ GPU_RST# PI/USO# Pull-up(LG) V_S R 0 US_O# US_O# US_O# US_O0# US_O# US_O# US_O# US_O# 0KX V R 0 EXTTS_SNI_RV0_PH GPU_PWR_EN# O_M_R# MP_PWR_TRL# EXTTS_SNI_RV_PH T_IS 0KX V PI_PIRQ# R0.K/J_ PI_PIRQ# R.K/J_ PI_PIRQ# R.K/J_ PI_PIRQ# R0.K/J_ RF_ON R 0K/J_ GPU_HOL_RST# R *0K/J_ RF_ON R 00K/J_ WLN LN US.0 LK_PIE_WLNN LK_PIE_WLNP PIE_LKREQ_WLN# LK_PIE_LNN LK_PIE_LNP PIE_LKREQ_LN# LK_00_US0_N LK_00_US0_P LK_PIE_VGN LK_PIE_VGP R0 SW:Stuff UM:Non-stuff MP Switch ontrol MP_PWR_TRL# MP_PWR_TRL# R R R LKOUT_PIEN LKOUT_PIEP PIELKRQ# LKOUT_PIEN LKOUT_PIEP PIELKRQ# LKOUT_PIEN LKOUT_PIEP LKOUT_PEG N LKOUT_PEG P Low = MP ON High = MP OFF (efault) R 0X R *0X IS@0X *K/J_ *0 short *0 short -0-0 SW:Ra UM:Rb LK_REQ/Strap Pin(LG) V V_S R R R R R R R R R Ra PEG_LKREQ# LK_UF_LKN LK_UF_LKP LK_UF_PIE_GPLLN LK_UF_PIE_GPLLP LK_UF_REFLKN LK_UF_REFLKP LK_UF_REFSSLKN LK_UF_REFSSLKP LK_PH_M IS_ULE_LE 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ IS@0K/J_ PIE_LKREQ_WLN# PIE_LKREQ_LN# PIELKRQ0# PIELKRQ# PIELKRQ# PIELKRQ# PIELKRQ# IS_ULE_LE R R R0 R R R R R R0 R PEG_LKREQ# R Rb *UM@0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 00K/J_ SMus/Pull-up(LG),,, M_T SM_ME_T Q N00K V_S R K/J_ RMRST_NTRL_PH R 0K/J_ SMLERT# R.K/J_ SM_PH_LK R.K/J_ SM_PH_T R.K/J_ SM_ME0_LK R.K/J_ SM_ME0_T R 0K/J_ SMLLERT#_R V_S R.K/J_,,, M_LK SM_ME_LK Q N00K V_S R.K/J_ PROJET : KL Quanta omputer Inc. Size ocument Number Rev ougar Point / ate: Friday, October, 00 Sheet of

10 , E_EXT_SMI# E_EXT_SI# LN_ISLE# S_GPIO E_EXT_SMI# OR_I E_EXT_SI# LN_ISLE# R 00_ TP HOST_LERT#_R I_EN# ougar Point (GPIO,VSS_NTF,RSV) UF T MUSY# / GPIO0 V V TH / GPIO 0 PU_I TH / GPIO V V TH / GPIO R.K/F_ H TH / GPIO V V TH / GPIO0 OLOR_ENGINE_ET E TH / GPIO V V TH / GPIO 0 OR_I 0 GPIO V_S LN_PHY_PWR_TRL / GPIO V_S G GPIO V_S 0GTE P E_0GTE LN_ISLE# 0 GPIO Pull-up/Pull-down(LG) R 0K/J_ V_S V GFXPG_R GFXPG_R U IS@TSH0FU(F) PLL_OVR_EN T_ON#, TEMP_LERT# R *IS@0_ V R OR_I0 GFXPG_R IOS_RE US0_I GPIO SYSTEM_I T_ON# FI_OVRVLTG MFG_MOE GPU_PRSNT# TEST_SET_UP SV_ET *0 short TP PLL_OVR_EN_R MI_OVRVLTG HWPG,,0,,,, GFXPG, U 0 T E E P K K V M N M V V E STGP / GPIO V TH0 / GPIO V SLOK / GPIO V GPIO / MEM_LE V_S GPIO SW GPIO V_S STP_PI# / GPIO V GPIO V STGP / GPIO V STGP / GPIO V SLO / GPIO V STOUT0 / GPIO V STOUT / GPIO V STGP / GPIO V GPIO V_S VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ GPIO NTF PU/MIS PEI RIN# PROPWRG THRMTRIP# INIT_V# F_TVS TS_VSS TS_VSS TS_VSS TS_VSS N_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ U P Y Y0 T Y H K H0 K0 P G G H H J J J J J J E E_RIN# PH_THRMTRIP# TP R 0/J_ E_RIN# H_PWRGOO PM_THRMTRIP# F_TVS oard I For Function SV SIV SIT SVT SOVP TEST_SET_UP SYSTEM_I GPIO SV_SET_UP I GPIO I: 0--> layer --> layer System I: 0-->KL -->KL PU_I: 0-->W -->W High = Strong (efault) R R 0K/J_ *0/J_ I GPIO V V I GPIO R R0 R R0 R R R OLOR_ENGINE_ET R E_EXT_SMI# R E_EXT_SI# R E_0GTE R E_RIN# R TEMP_LERT# R T_ON# R0 GPIO R0 GFXPG_R R I0 GPIO US0_I US.0 Non-US.0 PU_I GPIO *0K/J_ PU_I 0K/J_ OR_I0 *0K/J_ OR_I 0K/J_ OR_I *0K/J_ SYSTEM_I 0K/J_ OR_I GPIO 0 *0K/J_ US0_I oard I -0 oard I use below GPIO: OR_I0 OR_I OR_I R R R R R R R0 0K_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ IS@0K/J_ OR_I R0 *0K/J_ SV_ET R0 00K/J_ V 0K/J_ *0K/J_ 0K/J_ *0K/J_ 0K/J_ V_S *0K/J_ 0K/J_ V_S E F F VSS_NTF_ VSS_NTF_ VSS_NTF_ ougarpoint_rp0 VSS_NTF_0 VSS_NTF_ VSS_NTF_ SGPIO S_GPIO V V V E F F R R0 V 0K/J_ *0/J_ HOST_LERT#_R R0 Low = isable (efault) High = Enable K/J_ V_S Intel ME rypto Transport Layer Security (TLS) cipher suite V R Stuff No Stuff SWITHLE R R *0K/J_ GPU_PRSNT# R UM R R IS@00K/J_ R FI TERMINTION VOLTGE OVERRIE 00K/J_ FI_OVRVLTG R LOW - Tx, Rx terminated to same voltage *K/F_ MI TERMINTION VOLTGE OVERRIE MI_OVRVLTG R Low = Tx, Rx terminated to same voltage ( oupling Mode) (EFULT) *00K/F_ IOS_RE R R IOS REOVERY 0K/J_ *0/J_ High = isable (efault) Low = Enable MFG-TEST MFG_MOE R R V 0K/J_ *0/J_ PROJET : KL Quanta omputer Inc. Size ocument Number Rev ougar Point / ate: Friday, October, 00 Sheet 0 of

11 PH(LG).0V_PH.0V_PH R.0V_PH L R 0_0.0V_PH_V.0V_PH_VPLL_EXP *0 short.0v_vpll_exp *uh/m_.0v_ph.0v_vio VccIO =. (0mils) R 0_0 V U/.V_ *0U/.V_ U/.V_ R.0V_PH VccORE =. (0mils) U/.V_ U/.V_ 0 U/.V_ V_V_EXP *0 short VFI_VRM R R 0 U/.V_ U/.V_ 0 0U/.V_ 0.U/0V_ *0/J_ *0 short.0v_ph VFI_VRM 0U/.V_ VFI_VRM.0V_VPLL_FI.0V_VPLL_FI F F G G G G G G J J J J J N J N N N N N P P P P T N N H P G P U0 OUGR POINT (POWER) UG VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[0] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VIO[] VPLLEXP VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] V_[] VVRM[] VccFIPLL VIO[] VMI[] ougarpoint_rp0 POWER V ORE VIO FI RT LVS FT / SPI MI HVMOS V VSS VLVS VSSLVS VTX_LVS[] VTX_LVS[] VTX_LVS[] VTX_LVS[] V_[] V_[] VVRM[] VMI[] VLKMI VFTERM[] VFTERM[] VFTERM[] VFTERM[] VSPI U U K K M M P P V V T T0 G G J J V VFI_VRM V Vcc =m(mils) L VLVS V VccLVS=m(mils) R SW@0/J_ V_TX_LVS VccTX_LVS=0m(0mils) L V_V_GIO 0 U/.V_ VP_NN V_VME_SPI U/.V_ R *0/J_ 0.0U/V_ R 0.U/0V_ V VFI_VRM.V_V_MI_I R0 R 0.0U/V_ L *0U/.V_ R 0 0.U/0V_ 0 0.0U/V_ *0 short *0 short 0/J_ *0/J_.V 0.U/0V_ V V_S U/.V_ R Ra Rb 0U/.V_.V_V_MI V_MI_I Ra Rb IS SW 0 ohm N 0 ohm N VMI = m(0mils) *0uH_ R R U/.V_ VSPI = 0m(mils) 0ohm/ SW@0.uH_ *IS@0/J_.0V_PH *0 short.0v_ph VPNN = 0 m(mils) V.V VLKMI = 0m(mils) R R0 *IS@0/J_ */F_ *0 short.0v_ph L.0V_PH.0V_PH.0V_PH V_S V_SW R VPLL_PY_PH VME(.0V) =??(??mils) R 0_0 R R R R *0uH/00m_.0V_PH VSW_= m.0v_vepw VccSW =.0 (0mils) *0 short *0 short *0 short *0/J_ R 0 U/.V_ U/.V_ U/.V_ U/.V_ 0/J_ *0/J_.0V_PH *0U/.V_ 0 U/.V_ U/.V_ R 0.U/0V_ R0 0 U/.V_ U/.V_ VFI_VRM m(0mils) m(mils) *0/J_ 0 *0.U/0V_ *0 short *U/.V_ 0.U/0V_ VLK VPSW PH_VSW V_SUS_LKF VPLL_PY VSUS VRTEXT VFI_VRM.0V_V PL.0V_V PL VIFFLK VIFFLKN VIFFLKN= m(0mils) VSS= m(0mils) V.0V_SSV ougar Point-M (POWER) T V T H L L W W W W W W W N Y F F F F G G UJ VLK VSW_ PSUSYP V_[] VPLLMI VIO[] PSUS[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[0] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[0] PRT VVRM[] VPLL VPLL VIO[] VIFFLKN[] VIFFLKN[] VIFFLKN[] VSS POWER lock and Miscellaneous ST PI/GPIO/LP US VIO[] VIO[0] VIO[] VIO[] VIO[] VSUS_[] VSUS_[] VSUS_[] VSUS_[0] VSUS_[] VIO[] VREF_SUS PSUS[] VSUS_[] VREF VSUS_[] VSUS_[] VSUS_[] VSUS_[] V_[] V_[] V_[] V_[] VIO[] VIO[] VIO[] VIO[] VPLLST VVRM[] VIO[] VIO[] VIO[] N P P T T T T V V P T M N N P N0 N P0 P W T J F H H F V_VPUS V_VUG VUPLL V_PH_VREFSUS V_USSUS V_VPSUS V_PH_VREF V_VPSUS V_VPORE V 0 0.U/0V_ V.0S_ST V.LN_VPLL VVRM= K m(mils) F VFI_VRM.0V_VIO 0 U/.V_.0V_VUSORE R *U/.V_ L R R U/.V_ 00 0.U/0V_ 0.U/0V_ *0 short 0 *0U/.V_ R R 0 0.U/0V_ U/.V_ V *0 short *0 short *0 short *0 short.0v_ph R0 R R.0V_PH V_S VREFSUS=m VREF= m??m(??mils).0v_ph.0v_ph V_S V_S V V V_S V.0V_PH VSUS_ = m(mils) R00V-0 0/F_ R00V-0 *0 short VPORE = m(0mils) 0 0.U/0V_ 0.U/0V_ R R *0uH/00m_ 0/F_ *0 short VSUS_ = m(mils) U/0V_ U/0V_ *0 short.v R 0/J_ VVRM:.V (estop) 0/0 del for Pre-ES.V (Mobile) *U/.V_ 0.U/0V_ VSST V PSST.0V_VEPW VME =.0(0mils).0V_PH R *0/J_.0V_PH m(mils) R VRT<m(mils) V_RT *0 short.u/.v_ 0.U/0V_ 0.U/0V_ V.0M_VSUS VTT_VPPU T PSUS[] V PSUS[] J V_PRO_IO PU MIS VSW[] T VSW[] V VSW[] T R0 *0/J_.V_SUS 0 U/.V_ 0 0.U/0V_ 0.U/0V_ VRT ougarpoint_rp0 RT H VSUSH P V._._H_IO R *U/.V_ 0.U/0V_ 0/J_ V_S VSUSH= 0m(mils).0V_PH L0 0uH/00m.0V_V PL V *0U/.V_ U/.V_ R R *0/J_ /F_ V_SUS_LKF_R L 0uH/00m_ V_SUS_LKF L 0uH/00m.0V_V PL 0U/.V_ U/0V_ *0U/.V_ U/.V_ PROJET : KL Quanta omputer Inc. Size ocument Number Rev ougar Point / ate: Friday, October, 00 Sheet of

12 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : KL ougar Point / Friday, October, 00 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : KL ougar Point / Friday, October, 00 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : KL ougar Point / Friday, October, 00 IEX PEK-M (GN) PH(LG) UH ougarpoint_rp0 UH ougarpoint_rp0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] 0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] F0 VSS[] F VSS[] VSS[] F VSS[] F VSS[] F VSS[0] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[0] F VSS[] G VSS[] G VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H0 VSS[0] H VSS[] H VSS[] H VSS[] J VSS[] J VSS[] J VSS[] K VSS[] K VSS[0] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[0] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] M VSS[] M VSS[] M VSS[00] M VSS[0] M VSS[0] M VSS[0] M VSS[0] N VSS[0] N VSS[0] N VSS[0] N VSS[0] P VSS[0] P VSS[] P VSS[] P0 VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] R VSS[0] R VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T0 VSS[] T VSS[] T VSS[] T VSS[] T VSS[] U VSS[] U0 VSS[] V VSS[] V0 VSS[] V VSS[] V0 VSS[0] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] W VSS[] W VSS[] W VSS[] W VSS[0] W VSS[] W VSS[] W VSS[] W0 VSS[] W VSS[] V VSS[] Y VSS[] Y VSS[] Y VSS[0] VSS[] E VSS[] VSS[] P VSS[0] H VSS[] F VSS[] VSS[] VSS[] J VSS[] J VSS[] E VSS[] T VSS[0] T VSS[0] M VSS[] L VSS[] L UI ougarpoint_rp0 UI ougarpoint_rp0 VSS[] Y VSS[0] Y VSS[] Y VSS[] Y VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] 0 VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] E VSS[] E VSS[] E0 VSS[] F0 VSS[00] F VSS[0] F VSS[0] F0 VSS[0] F VSS[0] F VSS[0] F VSS[0] F VSS[0] VSS[0] F0 VSS[0] F VSS[0] F0 VSS[] F VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[0] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] K VSS[] L VSS[] L VSS[] L0 VSS[] L VSS[] L VSS[0] L VSS[] L VSS[] M VSS[] P VSS[] M VSS[] M VSS[] M VSS[] M0 VSS[] M VSS[] M VSS[0] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] N VSS[] P0 VSS[] P VSS[] P VSS[0] T VSS[] P0 VSS[] P VSS[] P VSS[] P VSS[] R VSS[] R VSS[] T VSS[] T VSS[] T VSS[00] T VSS[0] W VSS[0] T VSS[0] T VSS[0] T VSS[0] V VSS[0] V VSS[0] V VSS[0] V VSS[0] V VSS[0] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] VSS[] VSS[0] VSS[] VSS[] E VSS[] E VSS[] G VSS[] G0 VSS[] G VSS[] G VSS[] G VSS[] G VSS[0] H VSS[] H VSS[] W VSS[] W VSS[] W VSS[0] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] G VSS[] N VSS[0] J VSS[] N VSS[] H VSS[] H VSS[] H VSS[] H0 VSS[] H VSS[] H VSS[] F VSS[] K VSS[] K VSS[] H VSS[0] K VSS[] K VSS[] VSS[] VSS[] E0 VSS[] G VSS[] G VSS[] H VSS[0] T VSS[] G VSS[] G VSS[] VSS[] P VSS[] F VSS[] H0 VSS[] M VSS[] P VSS[] P VSS[] E VSS[0] VSS[] G VSS[] J

13 R_RVS(R) V R R0 JIM M Q[:0] M [:0] M 0 M Q M 0 Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q 0 M Q M Q M Q M Q M Q M Q M Q M 0 Q 0 M Q M 0/P Q0 M Q0 M Q M Q M /# Q M Q M Q 0 M Q M Q M Q Q M Q0 Q M Q M S#0 0 0 Q M Q M S# 0 Q M Q M S# Q M Q M S#0 S0# Q0 0 M Q M S# S# Q M Q M LKP0 0 K0 Q 0 M Q M LKN0 0 K0# Q M Q M LKP 0 K Q M Q0 M LKN 0 K# Q M Q M KE0 KE0 Q M Q M KE KE Q M Q M S# S# Q M Q M RS# 0 RS# Q M Q M WE# 0K/J_ IMM_S0 WE# Q0 M Q 0K/J_ IMM_S S0 Q 0 0 M Q S Q, SM_RUN_LK 0 M Q SL Q, SM_RUN_T 00 M Q S Q SMR_VREF_Q_M M Q Q M OT0 M Q OT0 Q 0 M OT 0 M Q OT Q M Q Q 0 M Q M0 Q M Q0 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q 0 M Q M Q M Q M Q M Q M QSP[:0] M QSP0 Q 0 M Q M QSP QS0 Q M Q M QSP QS Q M Q M QSP QS Q0 M Q M QSP QS Q M Q M QSP QS Q M Q0 M QSP QS Q M Q M QSP QS Q M Q M QSN[:0] M QSN0 QS Q 0 M Q M QSN QS#0 Q M Q M QSN QS# Q M Q M QSN QS# Q M Q M QSN QS# Q M Q0 M QSN QS# Q0 0 M Q M QSN QS# Q M Q M QSN QS# Q M Q QS# Q 0/ Remove 0ohm to GN P00 R SRM SO-IMM (0P) SMR_VREF_Q_M R SMR_VREF_Q_M R R V PM_EXTTS#0, R_RMRST# 0/J_ *0/J_. V.V_SUS 0K/J_ JIM V V V V V V V V V 00 V0 0 V 0 V V V V V V V VSP N N NTEST EVENT# 0 RESET# SMR_VREF_Q VREF_Q SMR_VREF_IMM VREF_ VSS VSS VSS VSS VSS VSS VSS 0 VSS VSS VSS0 VSS VSS VSS VSS VSS P00 R SRM SO-IMM (0P) R-IMM0_H= VSS VSS VSS VSS VSS0 VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VTT 0 0 VTT GN 0 GN 0 0.V_R_VTT R-IMM0_H=.V_SUS Place these aps near So-imm. 0 0U/.V_ 0U/.V_ 0U/.V_ 0 0 U/0V_ U/0V_ SMR_VREF_IMM SMR_VREF_Q VREF Q M Solution 0u/.V_ 0U/.V_ 0U/.V_ *0U/.V_ U/0V_ 0 U/0V_ 0U/.V_ 0 0U/.V_ 0.U/0V_.U/.V_ 0.U/0V_.U/.V_ V 0.V_R_VTT.U/.V_ 0.U/0V_ U/.V_ U/.V_ U/.V_ U/.V_ 0 0U/.V_ *0U/.V_ VREF Q M Solution.V_SUS ST H ST H FOX R K/F_ LTK GMK00000 GMK0000,, SMR_VREF R *0/J_ SMR_VREF_Q_M R K/F_ 0.U/0V_ SUY MLX GMK0000 GMK00000 Standard H type:r--00-0p- PROJET : KL Quanta omputer Inc. Size ocument Number Rev RIII SO-IMM-0 ate: Friday, October, 00 Sheet of

14 M 0 M M M M M M 0 M M M M M M M M M M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q IMM0_S0 IMM0_S SMR_VREF_IMM PM_EXTTS#0 SMR_VREF_Q0 SMR_VREF_Q0_M SMR_VREF_Q0_M SMR_VREF_IMM SMR_VREF_Q0_M M [:0] M S#0 M S# M S# M S#0 M S# M LKP0 M LKN0 M LKP M LKN M KE0 M KE M S# M RS# M WE# M QSP[:0] M QSN[:0] M OT0 M OT M Q[:0] SM_RUN_LK, SM_RUN_T, R_RMRST#, SMR_VREF_Q0_M SMR_VREF,, SMR_VREF,,.V_SUS V 0.V_R_VTT V.V_SUS.V_SUS SMR_VREF_IMM V.V_SUS 0.V_R_VTT SMR_VREF_Q0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : KL RIII SO-IMM- Friday, October, 00 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : KL RIII SO-IMM- Friday, October, 00 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : KL RIII SO-IMM- Friday, October, 00. R_ST(R) VREF Q0 M Solution GMK00000 GMK0000 GMK0000 ST H GMK00000 ST H FOX LTK SUY MLX Standard H type:r--0-0p VREF Q0 M Solution Place these aps near So-imm0. 0/ Remove 0ohm to GN P00 R SRM SO-IMM (0P) JIM R-IMM_H= P00 R SRM SO-IMM (0P) JIM R-IMM_H= V V V V V V V V V V0 00 V 0 V 0 V V V V V V VSP N N NTEST EVENT# RESET# 0 VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VTT 0 VTT 0 GN 0 GN 0 R 0K/J_ R 0K/J_ P00 R SRM SO-IMM (0P) JIM R-IMM_H= P00 R SRM SO-IMM (0P) JIM R-IMM_H= 0 0 0/P 0 /# S0# S# K0 0 K0# 0 K 0 K# 0 KE0 KE S# RS# 0 WE# S0 S 0 SL 0 S 00 OT0 OT 0 M0 M M M M M M 0 M QS0 QS QS QS QS QS QS QS QS#0 0 QS# QS# QS# QS# QS# QS# QS# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q0 Q Q Q Q Q Q Q 0 Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q 0P/0V_ 0P/0V_.U/.V_.U/.V_ 0.U/0V_ 0.U/0V_ R *0/J_ R *0/J_ U/.V_ U/.V_ U/.V_ U/.V_ 0.U/0V_ 0.U/0V_ R 0K/J_ R 0K/J_ 0 U/0V_ 0 U/0V_ 0U/.V_ 0U/.V_ U/0V_ U/0V_ 0U/.V_ 0U/.V_ 0 0U/.V_ 0 0U/.V_ 0.U/0V_ 0.U/0V_ 00 0U/.V_ 00 0U/.V_ 0 U/0V_ 0 U/0V_.U/.V_.U/.V_ u/.v_ u/.v_.u/.v_.u/.v_ R *0/J_ R *0/J_ 0U/.V_ 0U/.V_ R0 0K/J_ R0 0K/J_ R 0K/J_ R 0K/J_ R *0/J_ R *0/J_ R 0K/J_ R 0K/J_ 0 U/0V_ 0 U/0V_ 0U/.V_ 0U/.V_ R K/F_ R K/F_ U/.V_ U/.V_ 0U/.V_ 0U/.V_ *0U/.V_ *0U/.V_ 0U/.V_ 0U/.V_ *0U/.V_ *0U/.V_ 0.U/0V_ 0.U/0V_ R 0/J_ R 0/J_ 0 0U/.V_ 0 0U/.V_ R K/F_ R K/F_ *0U/V_ *0U/V_

15 .0V_GFX_PIE.0V_GFX_PIE V_GPU GFX_ORE.0V_GFX_PIE PEX_IOVPEX_IOVQPEX_PLLV >. 0.. ~ mils width V_GPU L R0 R0 P LOSE TO G ~ mils width for 0m L LMPGSN 0.U/0V_ U/.V_ 00.U/.V_ 0.U/0V_ 0.U/0V_ U/.V_ U/.V_.U/.V_ 0 0U/.V_ U/.V_ 0.U/0V_ 0.U/0V_ U/.V_ U/.V_.U/.V_ 0U/.V_ U/.V_ 0.U/.V_ U/.V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0/J_ PEX_PLLV PEX_SV_V U/.V_ 0.U/0V_.U/.V_ *0K/J_ PGOO *0.K/F_ MULTI_STRP_REF_GN U fcbga-nvidia-np-ge OMMON K PEX_IOV_ PEX_RX0 K PEX_IOV_ PEX_RX0* K PEX_IOV_ PEX_RX K PEX_IOV_ PEX_RX* K PEX_IOV_ PEX_RX PEX_RX* PEX_RX PEX_RX* PEX_RX PEX_RX* G PEX_IOVQ_ PEX_RX G PEX_IOVQ_ PEX_RX* G PEX_IOVQ_ PEX_RX G PEX_IOVQ_ PEX_RX* G PEX_IOVQ_ PEX_RX G PEX_IOVQ_ PEX_RX* G PEX_IOVQ_ PEX_RX G PEX_IOVQ_ PEX_RX* G PEX_IOVQ_ PEX_RX G PEX_IOVQ_0 PEX_RX* G PEX_IOVQ_ PEX_RX0 G PEX_IOVQ_ PEX_RX0* J PEX_IOVQ_ PEX_RX J PEX_IOVQ_ PEX_RX* J PEX_IOVQ_ PEX_RX J PEX_IOVQ_ PEX_RX* J PEX_IOVQ_ PEX_RX J PEX_IOVQ_ PEX_RX* J PEX_IOVQ_ PEX_RX J PEX_IOVQ_0 PEX_RX* K PEX_IOVQ_ PEX_RX K0 PEX_IOVQ_ PEX_RX* K PEX_IOVQ_ K PEX_IOVQ_ L PEX_IOVQ_ PEX_TX0 PEX_TX0* PI EXPRESS PEX_TX PEX_TX* J0 V_ PEX_TX J V_ PEX_TX* J V_ PEX_TX J V_ PEX_TX* J V_ PEX_TX PEX_TX* 0 V_SENSE PEX_TX N_/ V_SENSE PEX_TX* P N_/ V_SENSE PEX_TX PEX_TX* PEX_TX GN_SENSE PEX_TX* E N_0/ GN_SENSE PEX_TX R N_/ GN_SENSE PEX_TX* PEX_TX PEX_TX* PEX_TX0 G PEX_PLLV PEX_TX0* PEX_TX PEX_TX* PEX_TX PEX_TX* PEX_TX PEX_TX* G PEX_L_P_VQ/ PEX_SV_V PEX_TX F N_/ PEX_SV_V PEX_TX* PEX_TX PEX_TX* G0 PEX_L_PU_GN/ N N_ N_ N_ F N_ G N_ J N_ K N_ L N_ E N_ H N_ M N_ P N_ U N_ V N_ PEX_REFLK PEX_REFLK* PEX_TSTLK_OUT PEX_TSTLK_OUT* PEX_RST* PEX_LKREQ* PEX_TERMP TESTMOE P N N P R R0 P0 N0 N P R R P N N P R R P N N P R R P N N P R R R P L M M M L K L0 M0 M M L K L M M M L K L M M M L K K L M M0 M M N P R R J J M R G P PEG_RXP_ PEG_RXN_ PEG_RXP_ PEG_RXN_ PEG_RXP_ PEG_RXN_ PEG_RXP_ PEG_RXN_ PEG_RXP_ PEG_RXN_ PEG_RXP0_ PEG_RXN0_ PEG_RXP_ PEG_RXN_ PEG_RXP_ PEG_RXN_ PEG_RXP_ PEG_RXN_ PEG_RXP_ PEG_RXN_ PEG_RXP_ PEG_RXN_ PEG_RXP_ PEG_RXN_ PEG_RXP_ PEG_RXN_ PEG_RXP_ PEG_RXN_ PEG_RXP_ PEG_RXN_ PEG_RXP0_ PEG_RXN0_ PEX_TSTLK R0 PEX_TSTLK# VG_RST# PEX_TERMP TESTMOE U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ LK_PIE_VGP LK_PIE_VGN R R R *00/J_ R 0K/J_.K/F_ 0K/J_ *0 short PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP0 PEG_TXN0 PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP0 PEG_TXN0 PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP0 PEG_RXN0 PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP0 PEG_RXN0 GPU_RST# V_GPU PEX_LKREQ#,, GFXON R 00K/J_ GPU_RST#.V_GPU *EV@000P/0V/XR_@N.V_GPU For power-down sequency V V_GPU V_GPU.V_GPU V_GPU GFX_ORE R00V-0 R0 R *EV@000P/0V/XR_@N R0 0/J_.0V_GFX_PIE EV@0K/F_ EV@0K/F_ R0 *0_ *U/.V_ Q *MMT0 V Q0 Q PTTT R00V-0 V R0 *00K/F_ R *.K_ *MEN00E R EV@0K/F_ Q PTTT R0 *EV@0_ R0 EV@0K/F_ Q MMT0 V_GPU_EN GFXPG,0 PROJET : KL Quanta omputer Inc. V_GPU_EN Size ocument Number Rev VG-NP G-(PIe) ate: Friday, October, 00 Sheet of

16 VM_M VM_M0 VM_M VM_M VM_M VM_M VM_M VM_M VM_WQS VM_WQS0 VM_WQS VM_WQS VM_WQS VM_WQS VM_WQS VM_WQS VM_RQS VM_RQS0 VM_RQS VM_RQS VM_RQS VM_RQS VM_RQS VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_M F_PLLV F_EUG F_EUG F_L_P_VQ F_L_PU_GN F_L_TERM_GN VM_M VM_M VM_M VM_M0 VM_M VM_M VM_M VM_M VM_WQS VM_WQS VM_WQS VM_WQS0 VM_WQS VM_WQS VM_WQS VM_WQS VM_RQS VM_RQS VM_RQS VM_RQS0 VM_RQS VM_RQS VM_RQS VM_RQS VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q F_VREF VM_RQS VM_M VM_M VM_M VM_M VM_M VM_M VM_M0 VM_M VM_M0 VM_M VM_M VM_M VM_M0 VM_M0 VM_M F_PLLV VM_LKP 0 VM_LKN 0 VM_LKN0 0 VM_LKP0 0 VM_Q[..0] 0 VM_M[..0] 0 VM_WQS[..0] 0 VM_RQS[..0] 0 VM_RQS[..0] VM_WQS[..0] VM_M[..0] VM_Q[..0] VM_LKP VM_LKN0 VM_LKP0 VM_LKN VM_M 0 VM_M 0 VM_M0 0 VM_M 0 VM_M 0 VM_M 0 VM_M 0 VM_M 0 VM_M0 0 VM_M 0 VM_M 0 VM_M 0 VM_M0 0 VM_M 0 VM_M 0 VM_M 0 VM_M 0 VM_M 0 VM_M 0 VM_M 0 VM_M 0 VM_M0 0 VM_M 0 VM_M 0 VM_M 0 VM_M 0 VM_M 0 VM_M 0 VM_M0 VM_M VM_M VM_M VM_M VM_M VM_M0 VM_M VM_M VM_M VM_M VM_M0 VM_M VM_M VM_M VM_M VM_M VM_M VM_M0 VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_M 0 VM_M VM_M.0V_GFX_PIE.V_GPU.V_GPU.V_GPU.V_GPU.V_GPU.V_GPU.0V_GFX_PIE.V_GPU Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : KL VG-NP G-(MEM IF) Friday, October, 00 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : KL VG-NP G-(MEM IF) Friday, October, 00 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : KL VG-NP G-(MEM IF) Friday, October, 00 mils width mils width POP For ebug only / hange to 0.ohm mils width PLE UNER LLS PLE NER LLS L LMPG00SN L LMPG00SN R 0K/F_ R 0K/F_ 0 U/.V_ 0 U/.V_ T T L PY00T-Y-N L PY00T-Y-N R0 0./F_ R0 0./F_ T T R 0K/F_ R 0K/F_ 0.U/0V_ 0.U/0V_ R *0K/F_ R *0K/F_ 0.U/0V_ 0.U/0V_ R 0K/F_ R 0K/F_.U/.V_.U/.V_ 0.U/0V_ 0.U/0V_ R 0./F_ R 0./F_ 0 0.U/0V_ 0 0.U/0V_ R 0K/F_ R 0K/F_ R0 0K/F_ R0 0K/F_ T T R 0K/F_ R 0K/F_.U/.V_.U/.V_ R 0K/F_ R 0K/F_ 0.U/0V_ 0.U/0V_ 0U/.V_ 0U/.V_ T T R 0K/F_ R 0K/F_ 0.U/0V_ 0.U/0V_ R 0./F_ R 0./F_ T T MEMORY I/F OMMON fcbga-nvidia-np-ge U MEMORY I/F OMMON fcbga-nvidia-np-ge U F_VREF J F_WK_N H F_WK G F_WK_N E F_WK F_WK_N M F_WK L F_WK0_N R F_WK0 P F_QS_RN J F_QS_RN J F_QS_RN F_QS_RN F_QS_RN G F_QS_RN H F_QS_RN0 L F_QS_RN N F_QS_WP J F_QS_WP J F_QS_WP F_QS_WP E F_QS_WP H F_QS_WP J F_QS_WP0 L F_QS_WP N F_QM L F_QM L F_QM F F_QM F F_QM H F_QM J0 F_QM0 P F_QM P0 F_PLLV0 F F_LLV0 G F_EUG T0 F_LK* 0 F_LK F_LK0* T F_LK0 T F_ R0 F_0 R F_ P F_ N0 F_ L F_ M F_ M0 F_ L0 F_0 P F_0 P F_0 N F_0 P F_0 N F_0 L F_00 L F_0 N F_ K F_0 K0 F_ G0 F_ K F_ G F_ H0 F_ F0 F_ G F_ H F_0 K F_0 K F_ G F_0 K F_ E F_ E F_ G F_ G0 F_ H F_ G F_ F F_ F0 F_ 0 F_ F_ E0 F_ E F_ F F_ F F_ E F_ E F_0 E F_ F_ F_0 N F_ K F_ L F_ M F_ L F_ K0 F_ J0 F_ H0 F_ M F_ H F_ H F_ H F_0 H F_ M F_ L F_ J F_M0 V F_M W F_M U F_M Y F_M F_M F_M W F_M W F_M W0 F_M T F_M0 T F_M F_M Y0 F_M Y F_M W F_M 0 F_M F_M Y F_M U F_M Y F_M0 U F_M Y F_M W F_M V0 F_M U F_M U0 F_M U F_M 0 F_M F_M T F_M0 W FVQ_ J FVQ_ J FVQ_ J FVQ_ FVQ_ FVQ_ FVQ_ FVQ_ FVQ_ FVQ_ FVQ_ E FVQ_ J FVQ_0 FVQ_ E FVQ_ G FVQ_ G FVQ_ G FVQ_ G FVQ_ G FVQ_ H FVQ_ J FVQ_ J FVQ_0 J FVQ_ J FVQ_ J0 FVQ_ J FVQ_ J R 0./F_ R 0./F_ 0.U/0V_ 0.U/0V_ R 0K/F_ R 0K/F_ 0 U/.V_ 0 U/.V_ MEMORY I/F OMMON fcbga-nvidia-np-ge U MEMORY I/F OMMON fcbga-nvidia-np-ge U F_WK_N G F_WK G F_WK_N G F_WK G F_WK0_N G F_WK0 G F_WK_N G F_WK G F_QS_RN F_QS_RN F_QS_RN F_QS_RN F F_QS_RN0 F_QS_RN E F_QS_RN 0 F_QS_RN F_QS_WP F_QS_WP F_QS_WP F_QS_WP E F_QS_WP0 F_QS_WP F_QS_WP 0 F_QS_WP E0 F_QM F_QM F_QM F_QM F_QM0 F_QM F_QM 0 F_QM F F_L_TERM_GN M F_L_PU_GN L F_L_P_VQ K N/ F_PLLV J N/ F_LLV J F_EUG G F_LK* E F_LK F_LK0* F_LK0 E FVQ_ Y FVQ_ W FVQ_ V FVQ_ V FVQ_ V FVQ_ U FVQ_ U FVQ_ T FVQ_0 R FVQ_ P FVQ_ N F_ F_ E F_ F0 F_ F_ F F_ F F_ E F_0 F F_0 F_0 F_ F_ F_ F_ F_0 F_ 0 F_ F_ E F_ F F_ F F_0 F F_ E F_ F F_ F F_0 F_0 F_00 F_0 F_0 F_0 F_0 F_0 F_ F_ F_ E F_ F F_ F F_ E F_ F F_ F_ F_ F_ F_0 F_ F_ F_ F_ F_ E F_ F F_ 0 F_ E F_ F_ F_ F F_0 E F_ F_0 F_ F_ F_ F_ F_ F_ F_M0 F_M F_M F_M F F_M F_M F_M F_M E0 F_M G F_M F0 F_M0 F F_M F F_M F_M F_M F_M F F_M F_M E F_M 0 F_M F_M0 F_M F_M 0 F_M E F_M F_M F F_M F_M F F_M F_M 0 F_M0 0 0 U/.V_ 0 U/.V_ U/.V_ U/.V_ R 0K/F_ R 0K/F_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_.U/.V_.U/.V_ 0 0.U/0V_ 0 0.U/0V_ 0.U/0V_ 0.U/0V_