Sapporo 1.0 BLOCK DIAGRAM

Transcription

1 PU ORE.V/.V /.V/.VM VPU/VPU Sapporo. LOK IGRM P P P Merom Pins (Micro-FG) P,P PU Thermal Sensor MX P.MHz lock Generator K P.V/SMR_VTERM/SMR_VREFP TT HRGER MX/ ISHRGE VM_LN_SW/V_S/V_K/VSUS/V P V/VSUS P H (. inch) P V-ROM P P P mbient Light Sensor L Panel P RT port ST/PT PT P LVS R.G, IHM / MHz FS restline ufg P,P,P,P,P MI Singal hannel R PI-E PI-E R-SOIMM WLN Miniard P P able ocking TO US HU LINE IN LINE OUT RJ RT PORT SVIEO OUT POWER JK US PORT P US PORT (POWER US) P luetooth Module P FingerPrint(ES) P WWN Miniard P US. P,P,P,P SMUS ccelerometer LISLVL.V LP, MHz SPI zalia PI US PMI /SMRT R P PMI ontroller Ricoh P,P udio OE P P,P LN Intel Nineveh-MM RJ P P,P MP TP P UIO JK P SIM R P US for ocking P TPM (.) SL SMS K P SYSTEM IOS P MOEM M. P MP TLVGKR P RJ JK P MI JK P FN Track Keyboard P PointP P PROJET : OT Quanta omputer Inc. Size ocument Number Rev ustom System lock iagram ate: Thursday, March, Sheet of

2 INEX Pg# escription NOTE Power & Ground Label TIVE escription ontrol Signal Schematic lock iagram System Information System Power lock iagram Merom PU/THERML SENSOR restline_ IH_M R II SO-IMM LOK GEN L ONNETOR / L PWR WN/WWN /SIM R connector RUS ONTROLLER UIO OE / UIO JK LN/TRNSFORMER K RT PORT H / -ROM FN,K,LEs,TRK POINT US,LUE TOOTH,FINGER PRINT, M,TPM POWER SEQUENE,IOS LE OKING ISHRGE -HRGER(MX/) MX(VPU/VPU) MX(.VSUS/R_VTERM) MT VRT V PU_ORE.V V VSUS V_S VPU V VSUS VPU.V.VSUS.V V S, S, S, S.M.M.Moff S, S, S, S.M.M.Moff S, S, S, S.M.M.Moff S, S, S, S.M.M.Moff V S S S S, S S, S, S, S S, S, S, S.M.M.Moff S S, S S PTER (V) MIN TTERY (~V) RT & K POWER (_V) PU ORE POWER (./.V) FS POWER (.V) LWYS POWER (V) LWYS POWER (V) UIO NLOG POWER (V) VRON MIN.VM M.M IMT_ON V_S.VM SMR_VTERM SMR_VREF S, S, S, S S, S, S, S.M.M.Moff MIN SUSON S_ON MIN SUSON MIN S, S R ORE POWER SUSON S S S M.M S, S R OMMN & ONTROL PULL UP POWER R REF POWER S_ON IMT_ON MINON MINON SUSON MINON V_K M.M IMT_ON V_LN_SW M.M IMT_ON MX (.V/.V).V S MIN --MX VM/V_S/.V_M.VM M.M IMT_ON POWER SEQUENE PI EVIES IRQ ROUTING P STK UP SM US EVIE ISEL # REQ/GNT # PI_INT LYER : TOP LYER : GN LYER : IN LYER : IN LYER : V LYER : IN LYER : GN LYER : OT EVIE LOK GENERTOR R II ccelemter sensor HRGER PU THERML SENSOR RESS US PROJET : OT Quanta omputer Inc. Size ocument Number Rev ustom System Information ate: Thursday, March, Sheet of

3 S_ON SYSTEM POWER LOK IGRM S.W MOS-FET V_S IMT_ON daptor S.W MOS-FET S.W MOS-FET IMT_ON V_K MX VPU LWYS IMT_ON S.W MOS-FET VM_LN_SW S.VM MIN S.W V HRGER MX/ SUS MOS-FET VSUS V MIN SUS S.W MOS-FET V VSUS VPU LWYS TTERY S.W MOS-FET SUSON MINON MX.VSUS MINON TPS SMR_VTERM SMR_VREF MINON MX.V MIN S.V VRON IMT_ON.V_M S.W MOS-FET.V MINON PU_VI[..] HWPG PRSLPVR STP_PU# MX PU_ORE K_PW_ON SLP_S# SLP_S# TSHFU TSHFU TSHFU S_ON SUSON ISHRGE ISHRGE ISHRGE S_ON SUS MIN PROJET : OT Quanta omputer Inc. Size ocument Number Rev ustom System pwr block diagram Thursday, March, ate: Sheet of

4 () H_#[..] () H_ST# () H_REQ#[..] () H_#[..] () H_M# () H_FERR# () H_IGNNE# () H_STPLK# () H_INTR () H_NMI () H_SMI# XP_PM# XP_PM#.V XP_PM# XP_PM# H_#[..] H_REQ#[..] H_#[..] T () H_ST# H_PWRGOO R.V R H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_REQ# H_REQ# H_REQ# H_REQ# H_REQ# R R * R R */F R R () L_LKTL () L_LKTL H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# K/F./F R /F U J []# L []# L []# K []# M []# N []# J N P P L P P R M K H K J L Y U R W U Y U R T T W W Y U V W V []# []# []# []# []# []# []# []# XP_PM# XP_PM# XP_OS XP_OS XP_OS XP_OS H_PWRG_XP L_LKTL L_LKTL XP_TK ST[]# REQ[]# REQ[]# REQ[]# REQ[]# REQ[]# []# []# []# []# []# []# []# []# []# []# []# []# []# stage:change for change list R GROUP R GROUP []# []# []# []# []# []# ST[]# M# FERR# IGNNE# STPLK# LINT LINT SMI# IH M RSV[] N RSV[] T RSV[] V RSV[] RSV[] RSV[] RSV[] RSV[] RSV[] F RSV[] RESERVE T T ONTROL XP/ITP SIGNLS THERML H LK Merom all-out Rev a S# H NR# E PRI# G EFER# H RY# F SY# E R# F IERR# INIT# LOK# H RESET# RS[]# F RS[]# F RS[]# G TRY# G HIT# HITM# PM[]# PM[]# PM[]# PM[]# PRY# PREQ# TK TI TO TMS TRST# R# PROHOT# THERM THERM THERMTRIP# LK[] LK[] G E JITP H_IERR# GN OSFN_ OSFN_ GN OST_ OST_ GN OST_ OST_ GN OSFN_ OSFN_ GN OST_ OST_ GN OST_ OST_ GN PWRG/HOOK HOOK V_OS_ HOOK HOOK GN S SL TK TK GN *ONN_ITP-XP P XP_PM# XP_PM# XP_PM# XP_PM# XP_PM# XP_PM# XP_TK XP_TI XP_TO XP_TMS XP_TRST# XP_RESET# R H_PROHOT# H_THERM H_THERM GN OSFN_ OSFN_ GN OST_ OST_ GN OST_ OST_ GN OSFN_ OSFN_ GN OST_ OST_ GN OST_ OST_ GN ITPLK/HOOK ITPLK#/HOOK V_OS_ RESET#/HOOK R#/HOOK GN TO TRSTn TI TMS GN H_S# () T R H_NR# () H_PRI# () H_EFER# () H_RY# () H_SY# () H_R# ().V H_INIT# ().V H_LOK# () H_RESET# () H_RS# () H_RS# () H_RS# () H_TRY# () H_HIT# () H_HITM# () XP_RESET# (,) H_PROHOT# () PM_THRMTRIP# (,) LK_PU_LK () LK_PU_LK# () Layout Note: Place voltage divider within." of GTLREF pin :change for intel schematic R PU_TEST R *K/F PU_TEST *K/F PU_TEST R *.U/V PU_TEST * Place close to the PU_TEST pin. Make sure PU_TEST routing is reference to GN and away from other noisy signal. For the purpose of testability, route these signals through a ground referenced Z = ohm trace that ends in a via that is near a GN via and is accessible through an oscilloscope connection. layout note for H_THERM/H_THERM - Trace width/spacing should be / mils SI stage:no install to avoid leakage current R XP_RESET# R XP_TO XP_TRST# XP_TI XP_TMS.V R K/F R K/F XP_RESET# (,) LK_PU_XP () LK_PU_XP# ().V K/F *K/F R *./F R R R stage:change for change list H_RESET# V () H_#[..] () H_STN# () H_STP# () H_INV# () H_#[..] () H_STN# () H_STP# () H_INV# () PU_SEL () PU_SEL () PU_SEL.U.U V P () SYS_SHN#.U.V R R V H_#[..] H_#[..] H_THERM H_THERM H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# PU_SEL PU_SEL PU_SEL P T P T U E []# F []# E []# G []# F []# G []# E []# E []# K []# G J J H F K H L M L M P P P T R L H/W MONITOR []# []# []# []# []# []# []# J STN[]# H STP[]# H INV[]# N []# K []# P []# R []# []# []# []# []# []# []# []# []# []# []# T []# N []# L STN[]# M STP[]# N INV[]# V_PU_GTLREF PU_TEST GTLREF PU_TEST TEST PU_TEST TEST PU_TEST TEST F PU_TEST TEST F PU_TEST TEST TEST U V XP XN SEL[] SEL[] SEL[] PU_TEST PU_TEST SMLK SMT -OVT GN MX/GMT- T GRP T GRP T GRP T GRP MIS Merom all-out Rev a -LT SMK SMT THERM_LERT# []# []# []# []# []# []# []# []# []# []# []# []# []# []# []# []# Y V V V T U U Y W Y W W STN[]# Y STP[]# INV[]# U R U Y omp, connect with Zo=.ohm,omp, connect with Zo=ohm, make those traces length shorter than.".trace should be at least mils away from any other toggling signal. Size ocument Number Rev ustom (HOST US)/THERML ate: Thursday, March, Sheet of H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# []# E H_# []# H_# []# H_# []# H_# []# H_# []# H_# []# H_# []# E F H_# []# H_# []# E H_# []# H_# []# H_# []# H_# []# F H_# []# H_# []# STN[]# E STP[]# F INV[]# OMP[] OMP[] OMP[] OMP[] PRSTP# E PSLP# PWR# PWRGOO SLP# PSI# E OMP OMP OMP OMP SMK (,,) SMT (,,) H_#[..] H_#[..] OMP OMP OMP OMP THERM_LERT# () R./F H_#[..] () H_STN# () H_STP# () H_INV# () H_#[..] () H_STN# () H_STP# () H_INV# () H_PRSTP# (,) H_PSLP# () H_PWR# () H_PWRGOO () H_PUSLP# () PSI# () R./F PROJET : OT Quanta omputer Inc. R./F R./F

5 V_ORE V_ORE ll use U.V(-%,XR,)Pb-Free. inside cavity, north side, secondary layer. V_ORE V_ORE inside cavity, south side, secondary layer. V_ORE inside cavity, north side, primary layer. V_ORE.V U/.V U/.V U/.V U/.V U/.V U/.V U/.V U/.V U/.V U/.V U/.V U/.V U/.V U/.V U/.V U/.V U/.V U/.V U/.V inside cavity, south side, primary layer. U/.V U/.V V_ORE V_ORE VSENSE VSSSENSE.V stage:change to u Layout Note: Place near PIN. VSENSE VSSSENSE.V V_ORE U/.V U/.V U/.V E E E E E E E E E F F F F F F F F F U V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] Merom all-out Rev a. U/V R /F Layout out: Place these inside socket cavity on North side secondary..u/v.u/v.u/v Route VSENSE and VSSSENSE traces at.ohms and length matched to within mil. Place PU and P within inch of PU. E E E E E E E E F F F F F F F F VP[] G VP[] V VP[] J VP[] K VP[] M VP[] J VP[] K VP[] M VP[] N VP[] N VP[] R VP[] R VP[] T VP[] T VP[] V VP[] W V[] V[] VI[] VI[] VI[] VI[] VI[] VI[] VI[] VSENSE VSSSENSE F E F E F E F E U VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] F VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] G VSS[] G VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[] H VSS[] J VSS[] J VSS[] J VSS[] J VSS[] K VSS[] K VSS[] K VSS[] K VSS[] L VSS[] L VSS[] L VSS[] L VSS[] M VSS[] M VSS[] M VSS[] M VSS[] N VSS[] N VSS[] N VSS[] N VSS[] P VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] Merom all-out Rev a. P P P R R R R T T T T U U U U V V V V W W W W Y Y Y Y E E E E E E E E E F F F F F F F F U/.V U/.V U/.V U/.V U/.V U/.V R /F.U/V U/.V U/.V U/V H_VI () H_VI () H_VI () H_VI () H_VI () H_VI () H_VI () VSENSE () VSSSENSE ().U/V.U/V.U/V Size ocument Number Rev ustom Merom(POWER/N) ate: Thursday, March, Sheet of PROJET : OT Quanta omputer Inc.

6 .V.V R /F R /F R./F R./F H_SWING R./F H_SOMP H_SOMP# H_ROMP.U/V () H_#[..] Layout Note: H_ROMP trace should be -mil wide with -mil spacing..v R K/F R K/F () H_RESET# () H_PUSLP# H_#[..] H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_SWING H_ROMP H_SOMP H_SOMP# H_REF H_#[..].U/V E G G M H H G F N H M N N H P K M W Y V M J N N W W N Y Y P W N E Y E G J H J E E H J H J E J J E J H H U H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_SWING H_ROMP W H_SOMP W H_SOMP# H_PURST# E H_PUSLP# H_VREF H_VREF RESTLINE_p HOST H_# H_#_ J H_# H_#_ H_# H_#_ H_# H_#_ M H_# H_#_ H_# H_#_ F H_# H_#_ L H_# H_#_ G H_# H_#_ H_# H_#_ K H_# H_#_ H_# H_#_ L H_# H_#_ J H_# H_#_ K H_# H_#_ P H_# H_#_ R H_# H_#_ H_# H_#_ H H_# H_#_ L H_# H_#_ H_# H_#_ M H_# H_#_ N H_# H_#_ J H_# H_#_ H_# H_#_ E H_# H_#_ H_# H_#_ H_# H_#_ E H_# H_#_ H_# H_#_ H_# H_#_ H_# H_#_ N H_# H_#_ H_S# G H_ST#_ H H_ST#_ G H_NR# H_PRI# E H_REQ# F H_EFER# H_SY# HPLL_LK HPLL_LK# H_PWR# H_RY# H_HIT# H_HITM# H_LOK# H_TRY# H_INV#_ H_INV#_ H_INV#_ H_INV#_ H_STN#_ H_STN#_ H_STN#_ H_STN#_ H_STP#_ H_STP#_ H_STP#_ H_STP#_ M M H K E G K L E M K H L K J H_REQ#_ M H_REQ#_ E H_REQ#_ H_REQ#_ H H_REQ#_ H_RS#_ H_RS#_ H_RS#_ E H_#[..] () H_S# () H_ST# () H_ST# () H_NR# () H_PRI# () H_R# () H_EFER# () H_SY# () LK_MH_LK () LK_MH_LK# () H_PWR# () H_RY# () H_HIT# () H_HITM# () H_LOK# () H_TRY# () H_INV# () H_INV# () H_INV# () H_INV# () H_STN# () H_STN# () H_STN# () H_STN# () H_STP# () H_STP# () H_STP# () H_STP# () H_REQ# () H_REQ# () H_REQ# () H_REQ# () H_REQ# () H_RS# () H_RS# () H_RS# () Layout Note: Place the. uf decoupling capacitor within mils from GMH pins. Size ocument Number Rev ustom restline_(host) ate: Thursday, March, Sheet of PROJET : OT Quanta omputer Inc.

7 SM_ROMP_VOH.U/V SM_ROMP_VOL.U/V K/F.U/V.U/V R P T P T P T P T P T P T R P T.K/F P T P T P T P T P T P T P T R K/F PM_EXTTS# PM_EXTTS#.VSUS PLTRST#_R PM_THRMTRIP# P T P T P T P T P T P T P T P T P T P T P T P T P T P T P T P T P T P T P T P T P T P T P T P T P T P T P T P T P T P T P T P T P T P T P T P T P T P T P T P T TP_N TP_N TP_N TP_N TP_N TP_N TP_N TP_N TP_N TP_N TP_N TP_N TP_N TP_N TP_N TP_N P P R N R R M N J R M L M H J K F H K J F G R U PLTRST#_R R MUXING RSV LK SMROMPP SMROMPN SM_ROMP_VOH SM_ROMP_VOL SMR_VREF_MH GFX_VR_EN FGT_VI_ () FGT_VI_ () FGT_VI_ () FGT_VI_ () R PV stage:install for HP request MH_LVREF L_IG R.K FG FG FG [:] FG FG FG UM SMROMPP SMROMPN.VSUS R /F MI X Select PI Express Graphic Lane XOR/LLZ/lock Un-gating FS ynamic OT MI Lane Reversal SVO/PIE oncurrent Operation L_LON MH_LVREF.U/V L_IG P T R K R /F PST_PWM L_LON L_LKTL L_LKTL EILK EIT ISP_ON R TV_Y/G TV_/R L_VG L_VREFH L_VREFL TXLLKOUT- TXLLKOUT PEG_LK K LK_MH_GPLL () R /F PEG_LK# K LK_MH_GPLL# () F R /F TV_RTN J TV_RTN L V TV_RTN Layout Note: R.K MI_RXN_ N MI_MRX_ITX_N () M TV_ONSEL_ J R.K Location of all MH_FG strap MI_RXN_ MI_MRX_ITX_N () P TV_ONSEL_ MI_RXN_ N MI_MRX_ITX_N () resistors needs to be close to Stage: MI_RXN_ N MI_MRX_ITX_N () R /F minmize stub. R /F MI_RXP_ M MI_MRX_ITX_P () R /F () MH_SEL P FG_ MI_RXP_ J MI_MRX_ITX_P () () MH_SEL N FG_ MI_RXP_ N MI_MRX_ITX_P () () MH_SEL N FG FG_ MI_RXP_ N MI_MRX_ITX_P () P T RT_ FG FG_ () RT_ H RT_LUE P T R *.K/F FG FG_ MI_TXN_ J MI_MTX_IRX_N () G RT_G RT_LUE# F K P T FG FG_ MI_TXN_ J MI_MTX_IRX_N () () RT_G RT_GREEN N J FG FG_ MI_TXN_ M MI_MTX_IRX_N () RT_R RT_GREEN# P T G F FG FG_ MI_TXN_ M MI_MTX_IRX_N () () RT_R RT_RE P T J E R *.K/F FG FG_ RT_RE# P T FG FG_ MI_TXP_ J MI_MTX_IRX_P () R FG FG_ MI_TXP_ J MI_MTX_IRX_P () P T L M LK K R *.K/F FG FG_ MI_TXP_ MI_MTX_IRX_P () () LK T RT LK J M G R *.K/F FG FG_ MI_TXP_ MI_MTX_IRX_P () () T R /F RT T E F P T FG FG_ () RT_HSYN R.K/F RTIREF RT_HSYN E FG FG_ R R /F VSYN RT_TVO_IREF P T K E R *.K/F FG FG_ () RT_VSYN RT_VSYN M <check lisr & R> V FG FG_ P T M For alero :.VM P T FG FG_ L For resstline:.k/f R *.K/F FG FG_ N R *.K/F FG FG_ For external VG: L R :install FG_ ohm K/F RESTLINE_p V () PM_MUSY# (,) H_PRSTP# () PM_EXTTS# (,,) ELY_VR_PWRGOO (,) PM_THRMTRIP# (,) PM_PRSLPVR () PLT_RST-R# R G L L J W V N G J K K L L L L K J E K RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV H RSV W RSV K RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV PM_M_USY# PM_PRSTP# PM_EXT_TS#_ PM_EXT_TS#_ PWROK RSTIN# THERMTRIP# PRSLPVR N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ RESTLINE_p MI FG GRPHIS VI PM ME N MIS SM_K_ V SM_K_ SM_K_ SM_K_ V SM_K#_ W SM_K#_ SM_K#_ W SM_K#_ W SM_KE_ SM_KE_ SM_KE_ SM_KE_ SM_S#_ SM_S#_ SM_S#_ SM_S#_ SM_OT_ SM_OT_ SM_OT_ SM_OT_ SM_ROMP SM_ROMP# SM_ROMP_VOH SM_ROMP_VOL SM_VREF_ SM_VREF_ PLL_REF_LK PLL_REF_LK# PLL_REF_SSLK PLL_REF_SSLK# GFX_VI_ GFX_VI_ GFX_VI_ GFX_VI_ GFX_VR_EN L_LK L_T L_PWROK L_RST# L_VREF E Y G G K G E H J J E L K K L R W H H E E M K T N M SVO_TRL_LK H SVO_TRL_T K LK_REQ# G IH_SYN# G TEST_ TEST_ R R K M_LK_R () M_LK_R () M_LK_R# () M_LK_R# () R_KE_IMM () R_KE_IMM () R_S_IMM# () R_S_IMM# () M_OT () M_OT () MH_REFLK () MH_REFLK# () REF_SSLK () REF_SSLK# () L_LK () L_T () MPWROK (,) IH_L_RST# () LKREQ#_ () MH_IH_SYN# () R () () R /F TV_Y/G TV_/R FGT_VR_EN () () PST_PWM () L_LON () L_LKTL () L_LKTL () EILK () EIT () ISP_ON () TXLOUT- () TXLOUT- () TXLOUT- () TXLLKOUT- () TXLLKOUT TXLOUT- TXLOUT- TXLOUT- () TXLOUT () TXLOUT () TXLOUT TXLOUT TXLOUT TXLOUT R R */F L L N N E G E F G E G K K K :change to k Low=MIx High=MIx(efault) Low= Reveise Lane High=Normal operation =. =XOR Mode Enabled. =LL-Z Node Enabled. =lock gating Enabled(default). Low=ynamic OT isable High=ynamic OT Enable(default). Low=Normal(default). High=Lane Reversed Low=Only SVO or PIEx is operational (defaults) High=SVO and PIEx are operating simultaneously via PEG port U J L_KLT_TRL H L_KLT_EN E L_TRL_LK E L_TRL_T L LK L T K L_V_EN LVS_IG LVS_VG LVS_VREFH LVS_VREFL LVS_LK# LVS_LK LVS_LK# LVS_LK LVS_T#_ LVS_T#_ LVS_T#_ G LVS_T_ E LVS_T_ F LVS_T_ LVS_T#_ LVS_T#_ LVS_T#_ E LVS_T_ LVS_T_ LVS_T_ TV_ TV_ TV_ R *K L_LKTL L_LKTL FGT_VR_EN LVS TV VG UM V SMR_VREF_MH PI-EXPRESS GRPHIS.U/V.VSUS PEG_OMPI PEG_OMPO PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ stage:add PM_EXTTS# R K R K PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ R *K/F R *K/F N M J L N T T U Y Y W G H G G J L M U T T W W Y H G H G N U U N R T Y W W H E H M T T N R U W Y Y G E H PM_EXTTS# PM_EXTTS# stage:r install R SMR_VREF R * R./F PROJET : OT Quanta omputer Inc. Size ocument Number Rev ustom restline(vg,mi) ate: Thursday, March, Sheet of V_PEG SMR_VREF (,) PM_PRSLPVR (,)

8 J renamed to S_M pin for intel update / E renamed to S_M pin for intel update / restline(r) ustom Thursday, March, Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : OT R M R M R M R M R M R M R M R M R QS R QS R QS R QS R QS R QS R QS R QS R M R M R M R M R M R M R M R M R S R WE# R RS# R S# R S R S R M R M R M R M R M R M R QS# R QS# R QS# R QS# R QS# R QS# R QS# R QS# R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R M R SYSTEM MEMORY UE RESTLINE_p P R E Y F F J J J L W K K K K J L J J K J W L K K E K E G N J L K L K K J J F H N G K E J R T V Y Y U T V Y G G E R K L H J F W T K K J L E V U L K K K F V G G E G G W F E Y V Y E S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_S_ S_S_ S_S_ S_S# S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_RS# S_RVEN# S_WE# S_M_ T *P R SYSTEM MEMORY U RESTLINE_p R W G J G H E W E G E F H G F R W T W W Y Y V T V T W V U T R E Y G W Y R T T Y R R R N M N T T N M N W F K F L T W W G Y T E H P N T H P J E G J K H L K J J L E Y J S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ S_S_ S_S_ S_S_ S_S# S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_M_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_RS# S_RVEN# S_WE# S_M_ R S () R WE# () R RS# () R S () R S () R S# () R QS#[..] () R M[..] () R QS[..] () R M[..] () R [..] ()

9 Layout Note: Place where LVS and R taps. Layout Note: Place on the edge. Layout Note: Inside GMH cavity. Layout Note: Place close to GMH edge. Layout Note: Inside GMH cavity. Layout Note: mils from edge. Layout Note: Inside GMH cavity for V_XG. Layout Note: mils from edge. restline_(v,ntf) ustom Thursday, March, Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : OT VSM_LF VSM_LF VSM_LF VSM_LF VSM_LF VSM_LF VSM_LF L_ET _ET V_GMH_L VGFX VGFX VGFX _ET L_ET _ET L_ET _ET L_ET V VGFX.VM.VSUS.V.V.VM.VSUS.V R HH-HPT U/.V POWER V ORE V SM V GFX V GFX NTF V SM LF UG RESTLINE_p K J J H H H F T F J W Y E E E U F G G G H H H J J U K K K K U U U U U U V V V V T V V V Y Y Y Y Y Y Y T Y Y Y Y T F F H H H H T J J J K K L L L L L T L M M M M M P P P T P P P U U L V W T T U R T W W Y F F H H H H P P R R R R R R H J N W E W T H M U V V V Y V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_SM_ V_SM_ V_SM_ V_XG_NTF_ V_ V_SM_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_ V_XG_ V_XG_ V_XG_ V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_XG_ V_XG_ V_ V_XG_NTF_ V_SM_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ U/.V U/.V.U/V U/.V U/V.U/V.U/V.U/V.U/V.U/V.U/V U/V.U/V.U/V.U/V U/V POWER V NTF VSS NTF VSS S V XM V XM NTF UF RESTLINE_p K P U F F H H H H J K K K L L P R R T T T U U U U U V V V T T U U V V F K M P R R R Y K K J J L L L M M M M P P R Y Y Y Y L L J F J K L L L M M M M P P P R R T T V V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ V_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ V_NTF_ V_XM_ V_XM_ V_XM_ V_XM_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ VSS_S VSS_S VSS_S VSS_S VSS_S VSS_S V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ VSS_NTF_ V_NTF_ V_XM_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ VSS_NTF_ V_XM_NTF_ V_XM_NTF_ V_NTF_ VSS_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_NTF_ V_XM_ V_XM_ V_NTF_.U/V U/V.U/V.U/V JP *SHORT P U/V.U/V U/V.U/V U/V U/V U/.V.U/V.U/V _ET () L_ET () _ET () L_ET ()

10 V.VM.V F_ohm-%_mHz_m_.ohm L LMS V_MPLL_L U/V m Mx. F_ohm-%_mHz _m_.ohm V_HPLL F_ohm-%_MHz.ohm nf &.uf for V_TV:_R should be placed with in mils from restline. V_TVG_R.V L LMPGSN U/V *HH-HPT TV Voltage Follower ircuit - mv. V_RT L V_PEG_PLL LMPGSN V.VM.aps should be placed mils with in its pins. m Mx. uh-%_m F_ohm-%_mHz_m_.ohm R L LMS V_MPLL R./F/.U/V.U/V R /F/ U/.V L LMPGSN V_TVG *nf.v V R * V_TV_L.VM.U/V.U/V R.U/V U/V R /F L uh/m V_PLL L V_PLL uh/m.vm U/V V_TV V_TV V_TV R U/.V.U/V.U/V.U/V.U/V V_RT_R.VSUS.U/V U/V U/V *nf.u/.v U/V R R R.U/V.U/V V V U/V U/V V_TV_R *nf V_TV_R *nf V_TV_R *nf.u/v P/V.U/V U/V.U/V R.V V_RT_R V_TVG_R V_PLL V_PLL V_HPLL V_MPLL V_TX_LVS V_PEG_PLL U/V V_SM_K V_TV_R V_TV_R V_TV_R V_TV_R VQ_TV_R V_PEG_PLL U/V L VQ_TV LMPGSN F_ohm-%_ mhz_m_.ohm J H L M K K U W V U U U T T R R N N U UH VSYN V_RT V_RT V G VSS G V_PLL V_PLL V_HPLL V_MPLL V_LVS VSS_LVS V_PEG_G VSS_PEG_G V_PEG_PLL V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ T V_SM_ T V_SM_ T V_SM_ V_SM_ V_SM_ V_SM_NTF_ V_SM_NTF_ V_SM_K_ V_SM_K_ V_TV V_TV V_TV V_TV V_TV V_TV M V_RT L V_TV V_Q V_HPLL V_PEG_PLL J V_LVS_ H V_LVS_ U/.V VTTLF VTTLF VTTLF.U/V.U/V RT PLL K SM PEG LVS POWER TV TV/RT LVS R.U/V R.U X XF SM K HV MI PEG VTT VTTLF.U/V VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ V_SM_K_ V_SM_K_ V_SM_K_ V_SM_K_ V_RXR_MI_ V_RXR_MI_ VTTLF VTTLF VTTLF RESTLINE_p V_TV_R VQ_TV_R *nf U U U U U U U U U U U T T T T T T T T T R R R V_X_ T V_X_ U V_X_ U V_X_ T V_X_ T V_X_ T V_X_NTF V_XF_ V_XF_ V_XF_ V_MI V_TX_LVS V_HV_ V_HV_ R J K K J J V_PEG_ V_PEG_ W V_PEG_ W V_PEG_ V V_PEG_ V nf H H F H.U/V SI stage:change R to ohm and,, install.v Place on the edge. Place on the edge. V_XF V_SM_K V_TX_LVS VTTLF VTTLF VTTLF.U/.V.U/.V V_X_L L L pad for inductor. U/V U/V Place caps close to V_X. V.U/V V_RXR_MI.U/V.U/V P/V U/V uh-%_m L uh/m V_PEG V_SM_K U/V U/V.V.U/V U/V U/V L nh/. uh-%_. U/.V.V L nh/. uh-%_. U/.V.U/V uh-%_m V_SM_K_L.VM L uh/m R /F/ U/.V V_HV *HH-HPT Place caps close to V_XF.V PROJET : OT Quanta omputer Inc. Size ocument Number Rev ustom restline_e(power) ate: Thursday, March, Sheet of V_XF U/V.V V.V.VSUS V_HV_L R * R U/.V.VSUS

11 SI stage: add test pin restline(vss) ustom Thursday, March, Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : OT L_ET L_ET L_ET L_ET _ET _ET _ET _ET _ET _ET _ET _ET _ET _ET _ET _ET _ET _ET _ET _ET _ET _ET _ET _ET _ET _ET _ET _ET _ET _ET _ET _ET _ET _ET _ET _ET _ET _ET _ET _ET _ET _ET _ET _ET L_ET _ET V V V V R K R K R K R * R K T T Q NE T R * R K VSS UJ RESTLINE_p E E E E E E F F F F F G G G G G G G G G G G G H H H H J J J J J J J J K K K L L L L L L L L M M M M M M M N N N N N N N N N N P P P P P R T T T U U U W W W W W W Y Y Y V V Y Y Y Y Y P T T T R F F T V H VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ Q NE R * VSS UI RESTLINE_p E E E F F F F G G G G G H H H H H J J J J J J J J J K K K K K K L M M M M M M N N N N N N P P P R R R R R R T T T T W W W W W W Y Y Y Y Y Y Y Y E E E E E E E F F F G G G G G G G G H H H H H J J J J J J K K K K U U U U U U U V V W W K K K L L K K L L L L VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ R K Q NE R K R K R * Q NE T G_MON_ET (,) L_ET () _ET () _ET () L_ET ()

12 VRT VRT R K/F IH_INTVRMEN R K/F IH_LN_SLP VPU N T_ONN VRT_ R K () Z_ITLK_I () Z_SYN_I (,) Z_RST_I# () Z_SIN () Z_SIN () Z_SOUT_I () Z_ITLK_M () Z_SYN_M () Z_RST_M# () Z_SOUT_M VRT HH- HH- VRT R M/F *P *P *P R K *P *P *P U *P U *P G SHORT_ P INTRUER# R R R R R R R R P Y.KHZ P LK_KX LK_KX.V_PIE_IH Z_SIN Z_SIN R./F GLN_OMP Z_LK Z_SYN Z_RST# Z_SOUT JP () G_TLE# R M () GLN_LK () LN_RSTSYN () LN_RX () LN_RX () LN_RX () LN_TX () LN_TX () LN_TX () ENERGY_ET *SHORT P T T R T T T T STIS G F F E H J J E E E G F F F H H G G J J G G R * U RTX RTX RTRST# INTRUER# IH_INTVRMEN F IH_LN_SLP INTVRMEN LN_SLP *./F T T T T T T T T GLN_LK LN_RSTSYN LN_RX LN_RX LN_RX LN_TX LN_TX LN_TX GLN_OK#/GPIO GLN_OMPI GLN_OMPO H_IT_LK H_SYN H_RST# J H_SIN H H_SIN H H_SIN H_SIN H_SOUT STLE# STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP F STRXN F STRXP E STTXN E STTXP ST_LKN ST_LKP STRIS# STRIS IHM REV. RT LP LN / GLN IH H_OK_EN#/GPIO H_OK_RST#/GPIO ST PU IE FWH/L FWH/L FWH/L FWH/L FWH/LFRME# LRQ# LRQ#/GPIO GTE M# PRSTP# PSLP# FERR# PUPWRG/GPIO IGNNE# INIT# INTR RIN# NMI SMI# STPLK# THRMTRIP# TP S# S# IOR# IOW# K# IEIRQ IORY REQ E F G F G E F G F E G F E H G E V U V T V T T T R T V V U V U Y Y W W Y Y Y W L/FWH L/FWH L/FWH L/FWH P P P P P P P P P P P P P P P P GTE H_FERR# KPURST# PS# PS# LFRME#/FWH P P THERMTRIP#_IH P P P R * T T R /F H_PRSTP# R /F H_PSLP# R /F P T GTE () H_M# () R H_FERR# () H_IGNNE# ()./F PIOR# () PIOW# () PK# () IRQ () PIORY () PREQ () H_PRSTP# (,) H_PSLP# () H_INIT# () H_INTR () KPURST# () H_NMI () H_SMI# () H_STPLK# () L/FWH (,) L/FWH (,) L/FWH (,) L/FWH (,) LFRME#/FWH (,) H_PWRGOO () P[:] () P[:] () PS# () PS# () H_PRSTP# H_PSLP# H_FERR# GTE KPURST# V R R *.V.V R * R K V R R K PM_THRMTRIP# (,) V R.K R.K R *K R *K Z_SOUT IH_RSV () Size ocument Number Rev ustom IH(PU,ST,IE) ate: Thursday, March, Sheet of PIORY IRQ PROJET : OT Quanta omputer Inc.

13 SI stage:hange power source to avoid leakage current V_S MINI R PI-E INT# INT# INT# INT# E E G F E E E E F U PI Interrupt I/F PIRQ# PIRQ# PIRQ# PIRQ# IHM REV. REQ# GNT# REQ#/GPIO GNT#/GPIO REQ#/GPIO GNT#/GPIO REQ#/GPIO GNT#/GPIO /E# /E# /E# /E# IRY# PR PIRST# EVSEL# PERR# PLOK# SERR# STOP# TRY# FRME#.U.U E F E F E G F F G F REQ# GNT# REQ# GNT# REQ# GNT# REQ# GNT# /E# /E# /E# /E# IRY# PR PI_RST#_G EVSEL# PERR# LOK# SERR_# STOP# TRY# FRME# INTE# INTF# INTG# SES_INT PIE_RXN PIE_RXP PIE_TXN_ PIE_TXP_ P T P T P T P T P T P T PLT_RST-R# PLTRST# G LK_PI_IH PILK G PI_PME# PME# PIRQE#/GPIO PIRQF#/GPIO PIRQG#/GPIO PIRQH#/GPIO P P N N M M L L K K J J H H G G U PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PI-Express irect Media Interface SPI R K R *K LP PI SPI No stuff No stuff Stuff PI EVIES IRQ ROUTING ardus No stuff Stuff No stuff EVIE ISEL # REQ/GNT # PI_INT LK_PI_IH R *,,E *.P/V for EMI. Place resister and cap close to IH. V PI_RST#_G PLT_RST-R# SERR_# SI stage:add to avoid leakage currurt F PERN MI_LKN T LK_PIE_IH# () F PERP MI_LKP T LK_PIE_IH () E Intel LN PETN E R./F PETP MI_ZOMP Y MI_OMP Place within mils of IH PIE_RXN MI_IROMP Y.V_PIE_IH () PIE_RXN PIE_RXP PERN/GLN_RXN USP- () PIE_RXP PIE_TXN_ PERP/GLN_RXP USPN G USP- ().U USP SYSTEM(RIGHT) V_S R.K () PIE_TXN.U PIE_TXP_ PETN/GLN_TXN USPP G USP () () PIE_TXP PETP/GLN_TXP USPN H USP- () USP FINGER PRINT SI stage:hange power source to avoid leakage current R USPP H USP () USP- () SPI_LK stage:change for HP R SPI_LK USPN H P T USP request USO# () SPI_S# P T R SPI_S_R# SPI_S# USPP H () USO# USP- (,) SPI_S# E SPI_S# USPN J P T PV stage:change R to ohm for intel request USP P T R USPP J () SPI_SI SPI_MOSI USPN K P T F P T R /F SPI_MISO USPP K USP- () SPI_SO USO# USPN K USP- () J USP SYSTEM(LEFT) R /F USO# O# USPP K USP () USP- () T_OFF G USO# O#/GPIO USPN L USP- () G USP luetooth Module R /F USO# O#/GPIO US USPP L USP () USP- V V_S () WWN_OFF# E USO# O#/GPIO USPN M USP- () F USP ocking USO# O#/GPIO USPP M USP () USP- RP G USO# O#/GPIO USPN M USP- () USP WWN RP USO# USO# O#/GPIO USPP M USP () J USP- P T USO# USO# USO# O#/GPIO USPN N USP P T USO# USO# USO# O# USPP N H REQ# USO# USO# O# F REQ# USO# USO#.U/V USRIS# F USRIS STOP# FRME# USRIS V EVSEL#.KX USO#.U/V IHM REV. SI stage:hange power source to avoid leakage current.kx USO#.U/V Short F and F at the package V_S R USO#.U/V and keep length to less than V./F USO#.U/V mils. Trace Impedance RP should be ohms /- %. INTF# R USO#.U/V INTG#.K REQ# USO#.U/V INT# TRY# V SERR_# USO# SPI_S_R# oot IOS Strap GNT#.KX SI stage:add to avoid WWN Noise GNT# SPI_S# () [..] () () INT# INT# () PIE_RXN () PIE_RXP () PIE_TXN () PIE_TXP REQ# () GNT# () /E# () /E# () /E# () /E# () IRY# () PR () EVSEL# () PERR# () SERR_# () STOP# () TRY# () FRME# () LK_PI_IH () PI_PME# () INTE# () SES_INT () PLT_RST-R# () MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP V V U U Y Y W W MI_MTX_IRX_N () MI_MTX_IRX_P () MI_MRX_ITX_N () MI_MRX_ITX_P () MI_MTX_IRX_N () MI_MTX_IRX_P () MI_MRX_ITX_N () MI_MRX_ITX_P () MI_MTX_IRX_N () MI_MTX_IRX_P () MI_MRX_ITX_N () MI_MRX_ITX_P () MI_MTX_IRX_N () MI_MTX_IRX_P () MI_MRX_ITX_N () MI_MRX_ITX_P ().U/V.U/V HH-HPT IRY# INT# INTE# LOK# V U SH R * V U SH RP.KX SERR# REQ# INT# INT# PERR# dd uffers as needed for Loading and fanout concerns. R K stage:add PROJET : OT Quanta omputer Inc. Size ocument Number Rev ustom IH(US,PIE,MI) V ate: Thursday, March, Sheet of R K SERR# () PIRST# () PLTRST# (,,,)

14 V Option to " isable " clkrun. Pulling it down will keep the clks running. R.K LKRUN# LK_PWRG stage:add for pr_insert_dock# stage:change to V_S stage:dd,refer to Oak schematic (,,) ELY_VR_PWRGOO () LI_SW# E R LN_PHYP_R () LN_PHYP * G T GPIOH R GPIO (,) SPI_S# T E V T GPIOG stage:delete PV stage:add option (dd R)from LN_PHYP and T H Q,R,add U, to reserve R () LS_EN# T control VRMPWRG T G SI stage:delete R,add T test T SLO F R point T STOUT J *K T STOUT V V_S MH_IH_SYN#_R PT_SM PLK_SM V_S NLSZFTG SMLERT# V V_S PR_INSERT# V R PSPK PZ. (,) PR_INSERT_OK# PR_INSERT# (,) R K R K R _ET K R J_ET K R _ET K R J_ET K R.K PM_TLOW#_R R * K SI stage: add test pin PR_INSERT# No Reboot strap. T T RF_OFF# MPWROK OP# PSPK MH_IH_SYN#_R Low = efault. High = No Reboot. V _ET _ET GPIO GPIO GPIO R.KNPI_RST# V V R K stage:dd,refer to Oak schematic R MPWROK SUSM_# L_VREF L_VREF VM PV stage:dd for intel suggestion R J_ET H_STP_PI# H_STP_PU# R Q R K LN_PHYP_R * NE R K _IN# R (,) SLP_S# GPIO () PV stage:no install R,R R R *KIH_L_RST# R SI stage: add to avoid leakage current for intel request K ME_E_LK * R K ME_E_T stage:no R K IH_RI# install R,due to SI stage:delete,dd R *KOP# R K PIE_WKE# dual pull up R (,,) LN_LINKLE# R K XP_RESET# SUSM_# R SI stage:add R,Q,reserve R for SUSM# (,) SI stage: install to avoid leakage current auto power on issue stage:dd,refer to stage:change R to.k,and pull R *.K PM_MUSY# Oak schematic SI stage:delete Q,add R up to V stage:no install R to avoid leakage current U V PLK_SM J J R.K (,) PLK_SM stage:add R refer to PT_SM SMLK STGP/GPIO J (,) PT_SM Oak schematic IH_L_RST# SMT STGP/GPIO _LE () NPI_RST# () IH_L_RST# G R LINKLERT# STGP/GPIO F NPI_RST# () STGP () ME_E_LK STOUT R K R SMLINK STGP/GPIO G P T () ME_E_T E STGP R.K SMLINK LK_IH_M SERIRQ stage:reserve IH_RI# LK G LK_IH_M () R K F LK_IH_M STOUT R K RI# LK G LK_IH_M () ohm F IH_SUSLK () SUS_STT# P T RUNSI_E# R SUS_STT#/LPP# SUSLK K (,) XP_RESET# SYS_RESET# G SLO R K PM_MUSY# SLP_S# SLP_S# (,) G F R () PM_MUSY# MUSY#/GPIO SLP_S# SLP_S# () stage:change R to k refer to intel schematic SMLERT# SLP_S# R SLP_S# () G SMLERT#/GPIO PV stage:r install for intel suggestion H V S_STTE#/GPIO S_STTE () R () THERM_LERT# () H_STP_PI# E R STP_PI#/GPIO G E IH_PWROK () H_STP_PU# V STP_PU#/GPIO PWROK IH_PWROK ().U/V/ LKRUN# H J PM_PRSLPVR_R R (,,) LKRUN# LKRUN#/GPIO PRSLPVR/GPIO stage:ddr R PIE_WKE# E E PM_TLOW#_R () PIE_WKE# U K/F SERIRQ WKE# TLOW# TLOW# () F HH-HPT (,,) SERIRQ SERIRQ NSWON# SI stage:add R to modify LK_PWRG timing to avoid PU frequency THRM# PWRTN# NSWON# () R () VR_PWRG_LKEN# LN_RST# () error R J H R * IH_PWROK VRMPWRG LN_RST# () R *K PSPK RP PR-.K R * R K R K_ () RUNSI_E# () MH_IH_SYN# () IH_RSV () OP# R T T () T _ET () _ET J J J H J J R.K R.K R.K TP TH/GPIO TH/GPIO TH/GPIO GPIO GPIO TH/GPIO GPIO GPIO SLOK/GPIO QRT_STTE/GPIO QRT_STTE/GPIO STLKREQ#/GPIO SLO/GPIO STOUT/GPIO STOUT/GPIO SPKR MH_SYN# TP IHM REV. R K ST SM SYS GPIO NE GPIO locks Power MGT MIS GPIO ontroller Link NE R * R * Q E E J F E F F H J :reserve k ohm Place these close to IH. PM_PRSLPVR (,) :no install R,due to dual layout LN_WOL_EN PM_RSMRST#_R MPWROK PM_PRSLPVR_R RF_OFF# () _IN# R ET_P () R MT P_PRES () LN_WOL_EN LN_WOL_EN () V_S R K V V R * J_ET R * R *K NE R *K G PM_RSMRST#_R R /F RSMRST# RSMRST# K_PWRG LPWROK SLP_M# L_LK L_LK L_T L_T L_VREF L_VREF L_RST# MEM_LE/GPIO J ME_E_LERT/GPIO J E_ME_LERT/GPIO F WOL_EN/GPIO G Q G_MON_ET (,) () J_ET G_MON_ET (,) () J_ET K NE R K LK_PWRG () MPWROK (,) L_LK () IH_L_LK () L_T () IH_L_T () IH_L_RST# () Q Q RSMRST# () G_MON_ET (,) G_MON_ET (,) L_VREF.U/V LK_IH_M LK_IH_M stage:delete R VM PROJET : OT Quanta omputer Inc. Size ocument Number Rev ustom IH(PM,GPIO,SM) ate: Thursday, March, Sheet of R *K R.K/F R *K R *K R *M R K R /F R * R * L_VREF.U/V *.P/V *.P/V V_S R.K/F R /F

15 uh-%_m F_ohm-%_mHz_._. ohm uh-%_m uh-%_m stage:change for check list stage:change,, for intel recommend SI stage:change size to SI stage:hange footprint to SI stage:hange footprint to SI stage:wwn Noise -IH improvements IH(POWER,GN) ustom Thursday, March, Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : OT IH_VREF_SUS IH_VREF_RUN.V_MIPLL TP_VSUS._ TP_VSUS._ TP_VSUS._ TP_VSUS._ TP_VL. VL_ VSTPLL VSTPLL_L VSTPLL TP_VSUSLN TP_VSUSLN VGLNPLL VGLNPLL_L VGLNPLL.V_MIPLL_R V_PU_IO V_PU_IO.V V V_S V V VPU VPU VRT.V V_S VM.V.V.V.V.V.V VM.V V.V_PIE_IH.V V.V_PIE_IH.V.V.V.U/V.U/V TP R U/V.U/.V.U/V.U/V U/.V *U/V T P.U/V.U/V.U R.U.U/V R.U/V R /.U/V/ R *.U/V U/V.U/V L LMPGSN.U/V.U/V U/V *HH-HPT.U/V T P HH-HPT L uh/m UE IHM REV. E E E E E E E E F F F F F G G H H H H H F H H H H H H J E E E E F E F F F G E G G G G G G G H H H H H J J J J J J K K K K K L L L L L L L M M M M M M M M M M N N N N N N N N N N N N N N P P P P P P P P P R R R R R R R R R R T T T T T T T U U U U U U U U U U U V V V V W W W Y Y Y H H J J J J U K W VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS_NTF[] VSS_NTF[] VSS_NTF[] VSS_NTF[] VSS_NTF[] VSS_NTF[] VSS_NTF[] VSS_NTF[] VSS_NTF[] VSS_NTF[] VSS_NTF[] VSS_NTF[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[].U/V U/V R */ U/V ORE VGP TX RX IE US ORE PI GLN POWER VP_ORE VPSUS VPUS UF IHM REV. T G E E E F F G H H J J K K L L L M M N N N P P R R R R T T T T T U F R E F G H J J F G E F G L L L L L L M M P P T T F G U V W W W Y E E F G H P P N P P P P P R R R G G J F F L L M M W U V V V U V V V F E R H J E E G G F W V U Y V V VREF[] VREF[] VREF_SUS V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V_[] VMIPLL V [] V [] V [] V [] V [] VSTPLL V_[] V [] V [] V [] V [] V [] VUSPLL VLN_[] VLN_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] VLN_[] VLN_[] VH VSUSH V_PU_IO[] V_PU_IO[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] VRT VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] V [] V [] V [] V [] V [] V [] VSUS_[] VSUS_[] V [] V [] V [] V [] V [] VSUS_[] V_[] V [] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] VGLN_[] VGLN_[] VGLN_[] VGLN_[] VGLN_[] VGLN_ VGLNPLL V_[] V_[] V_[] V_[] VSUS_[] V [] VSUS_[] V [] V [] VSUS_[] V_MI[] V_MI[] VL_ VL_[] VL_[] VL_ V [] V [] V [] V [] V [] V [].U/V.U/V T P.U/V.U/V U/V.U/V L uh_m U/V.U/ U/.V T P T P.U/V R /.U/V.U/V.U/V.U/V HH-HPT.U/V L uh_m U/V U/.V.U/V.U/V.U/V TP _ET () _ET () J_ET () J_ET ()

16 is required to route to Top SoIMM for MT to function.this will need to change for M () R_KE_IMM () R S () R S () R WE# () R S# () R_S_IMM# () M_OT RT_SM RLK_SM VM SMbus address R R R QS# R QS R R R R R QS# R QS R R R R R QS# R QS R R R R R M R R R S R M R M R M R M R M R M R M R S R WE# R S# M_OT R R R QS# R QS R R R R R M R R R R R QS# R QS R R R R R M R R.VSUS RT_SM RLK_SM SMR_VREF_ JIM VREF VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS M N VSS Q Q VSS KE V N _ V V V /P WE# V S# S# V OT VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS M VSS Q Q VSS Q Q VSS NTEST VSS QS# QS VSS Q Q LOK, KE, OT VSS Q Q VSS M VSS Q Q VSS S SL V(SP) P R SRM SO-IMM VSS Q Q VSS M VSS Q Q VSS Q Q VSS M VSS K K# VSS Q Q VSS VSS Q Q VSS N M VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS KE (P) V V V V RS# S# V OT V N VSS Q Q VSS M VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS K K# VSS M VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS S S FOX_S-MSN-F.VSUS R R R M R R R R R M R R R R PM_EXTTS# R M R R R R R QS# R QS R R R M R M R M R M R M R M R M M_OT R M R R R M R R R R R QS# R QS R R R R R M R R R R R QS# R QS R R R K R K SMR_VREF_ dd for intel update VM R R M[..] () R [..] () R QS[..] () R QS#[..] () R M[..] ().U/V M_LK_R () M_LK_R# () R_KE_IMM () R S R S () R RS# R RS# () R_S_IMM# () M_OT () PM_EXTTS# () M_LK_R () M_LK_R# ().U/.V VM *K stage:reaerve.u/.v.u/v SMR_VREF_.VSUS.VSUS.U/V SMR_VTERM SMR_VTERM.U/.V *.U (,) PT_SM (,) PLK_SM Place these aps near So-imm. Place these aps near So-imm. *.U.U/V *.U/V.U/V.VSUS.U/.V R *K/F R *K/F R SMR_VREF VM VM Q RHUN.U/V RT_SM RLK_SM OT dd for intel update Please these resistor closely IMM,all trace length< mil. TOP Layout note: Place cap close to every R-pack terminated to SMR_VTERM..U/V *.U/V.U/.V.U/V Q RHUN.U/V *.U/V.U/.V *.U/V.U/.V stage:on install for,--- for only one channel IMM R K.U/V SMR_VREF (,) R K.U/V *.U/V.U/V *.U/V () R M[..].U/V *.U/V () R RS# () R S () M_OT () R S () R S () R WE# () R S# ().U/V M_OT () R_S_IMM# () R_S_IMM# () R_KE_IMM () R_KE_IMM *.U/V.U/V Size ocument Number Rev ustom R SO-IMM(P) ate: Thursday, March, Sheet of *.U/V R M R M R M R M R M R RS# R S R M M_OT R S R M R M R M R M R M R S R M R WE# R S# R M R M R PR-S- RP PR-S- RP PR-S- R R M R R R R R.U/V *.U/V.U/V *.U/V RP PR-S- RP PR-S- RP PR-S- RP PR-S- RP PR-S- RP PR-S- RP PR-S- RP.U/V *.U/V PROJET : OT Quanta omputer Inc. SMR_VTERM.U/V *.U/V

17 VM_K L R. KHM ohms@mhz L KHM L KHM :change R for intel schematic (,) PT_SM MINILK_REQ#G ST_LKREQ# LKREQ#_ LK_PI_IH_ R..U/V.U/V.U/V VM_K VM_K LK_SEL SMT Pull low for UM SMK SMT PLKK LK_XTL_IN LK_XTL_OUT SMK (,) PLK_SM SMK (,,) R K R *K R K R K Q NE R. V.U/V.U/V.U/V Q NE.U/V () LK_PWRG V R K VPU.U/V.U/V.U/V R K P.U/V U/V VIO R R.K U/V U/V SMT (,,) U VPLL V VPI VREF VSR VPU VI/O VPLLI/O VSRI/O VSRI/O VSRI/O VPU_IO N X X K_PWRG/P# FSL/TEST_MOE SLK ST GN GN GN GNPU GNPI GNREF GNSR GNSR GNSR PU lock select K PULKT PULK PULKT PULK PUT_ITP/SRT PUT_ITP/SR OTT_/SRT OT_/SR MHz_Nonss/SRLK/SE Mhz_ss/SRL/SE SRLKT/STL SRLK/STL SRLKT/R#_ SRLK/R#_ SRLKT SRLK PI_STOP# PU_STOP# SRLKT SRLK SRLKT/R#_F SRLK/R#_E SRLKT SRLK SRLKT SRLK internal have already build-in ohm damping resisteor PV stage:delete RP,add R,R PU_LK PU_LK# MH_LK MH_LK# PU_XTP PU XTP# OT OT# PIE_ST PIE_ST# PIE_IH PIE_IH# MH_GPLL MH_GPLL# PIE_MINI PIE_MINI# R. R. T T RP RP PR-S- RP PR-S- RP PR-S- PR-S- RP PR-S- RP PR-S- RP PR-S- RP PR-S- LK_XTL_IN PV stage:reserve for WWN issue Stage:no install RP,R due to no ST H P/V SRLKT/R#_H T MINILK_REQ# R SRLK/R#_G _% MINILK_REQ#G MINILK_REQ#G () SI stage:add R for E team test easy ST_LKREQ# PILK/R#_ LKREQ# R _% PILK/R#_ LKREQ#_ () R PILK/TME SI stage:delete,r, R due PLK_P_ to () PILK R no use PILK/_SELET PLK_TPM () PLKK R PLK_K () R PV stage: change R,R to ohm for E issue PLK_R () LK_PI_IH_ R PI_F/ITP_EN LK_PI_IH () R LK_IH_M () US_MHZ/FSL R LK_SEL R.K *KLL FSL/TST_SL/REF L LK_SEL R K ISLPRSGLFT R R M_K () L *KLL R LK_IH_M () :change R,R PV stage:change R,R to ohm for E issue for intel schematic SI stage:reserve L, L,add R,R for WWN noise improvement.p.p *P *P LK_PIE_IH () LK_PIE_IH# () LK_MH_GPLL () LK_MH_GPLL# () H_STP_PI# () H_STP_PU# () LK_PIE_MINI () LK_PIE_MINI# () Y.MHZ LK_XTL_OUT P/V LK_PU_LK () LK_PU_LK# () LK_MH_LK () LK_MH_LK# () LK_PU_XP () LK_PU_XP# () MH_REFLK () MH_REFLK# () REF_SSLK () REF_SSLK# ().MHz EMI FS PLK_TPM FS PLK_K FS LK_IH_M *P PLK_R *P LK_PI_IH *P LK_IH_M *P M_K *P *P *P PU RSV SR PI.V R R / LK_SEL () PU_SEL MH_SEL () () PU_SEL R */ R *K/ R / R */ LK_SEL K/F R K/F MH_SEL () FS LK SEL SEL SEL.V () PU_SEL.V R *K/ R / R */ R *K/ LK_SEL R K/F MH_SEL () SI stage: strapping options for PU_SEL{:} Size ocument Number Rev ustom LOK(K) ate: Thursday, March, Sheet of PROJET : OT Quanta omputer Inc.

18 V N L_ON PWM_INV_ EIT_ EILK_ R TXLLKOUT TXLLKOUT- TXLOUT TXLOUT- TXLOUT TXLOUT- LV LS_EN TXLOUT TXLOUT- P V V.U TXLOUT () TXLOUT- () TXLOUT () TXLOUT- () TXLOUT () TXLOUT- () TXLLKOUT () TXLLKOUT- () P LS_EN *.U V U/V R Q NE U TSHFU LS_EN# () FPK () L_LON L *.U/ SI stage:delete L_LON KHS-T V R K Q TEU PST_PWM () V R K FPK Q TEU SS N LI SW HH-HPT HH-HPT V_S.U R K.U LI_SW_E# () LI_SW# () PV stage:reser for Lid s/w function to E R *K PNEL V ONTROL VPU R K () EILK () EIT R.K R.K Q Q NE V NE EILK_ EIT_ () ISP_ON V R *K R K R Q TEU K.U Q FP G S V.U L FMHM U/V/ mil P.U LV.U/V SI stage:add soft start for L panel rush current issue PROJET : OT Quanta omputer Inc. Size ocument Number Rev L ON ate: Thursday, March, Sheet of

19 Mini PI-E ard LN VPU () *SW RF_LINK LUELE RF_LINK stage:change V_S P.U.U/V.V_WLN U/V/ E V_S R * IH_L_LK_ V VM_WLN R R SI stage:change footprint to VM V_S R *K VM_WLN R R stage:change power source stage:change R,R to footprint Stage:delete R,R () PIE_TXP dd R () PIE_TXN V R * stage:install () PIE_WKE# V_S R Q TEU () IH_L_RST# () IH_L_T () IH_L_LK () PIE_RXP () PIE_RXN () LK_PIE_MINI () LK_PIE_MINI# () MINILK_REQ#G () H_LK () H_T stage:change R R R R R PIE_RXP_ PIE_RXN_ SI stage:delete R due to no use MINILK_REQ#G R * I_LK R * I_T IH_L_LK_ N GN PETp PETn GN GN PERp PERn GN GN REFLK REFLK- GN LKREQ# WKE# PI-E ard.v GN.V LE_WPN# LE_WLN# LE_WWN# GN US_ US_- GN SM_T SM_LK.V GN.Vaux PERST# GN.V GN.V R * stage:change to footprint R * LUELE R RF_LINK T VM_WLN.V_WLN P P SMT (,,) SMK (,,) PLTRST# (,,,).U/V.U/V U VM_WLN RF_OFF#_ HH-HPT.V Stage:delete RP,RP,R R SI stage:change to HH-HPT for lower Vf U/V/ RF_OFF#_ SI stage:no install stage:change power source RF_OFF# () stage:change Mini PI-E ard WWN.V VSUS V () WWN_OFF# R WWLN_OFF_SIM P.U.U/V U/V/ P.U/V U P.U/V U/V/ V R VSUS V N GN PETp PETn GN GN PERp PERn GN GN REFLK REFLK- GN LKREQ# WKE# PI-E ard.v GN.V LE_WPN# LE_WLN# LE_WWN# GN US_ US_- GN SM_T SM_LK.V GN.Vaux PERST# GN.V GN.V.V WWLN_OFF_SIM UIM_VPP R UIM_RST UIM_LK_ R UIM_LK UIM_T_ R UIM_T UIM_PWR V R * R R.U V.U WWN# () USP () USP- () SMT (,,) SMK (,,) PLTRST# (,,,) *.U *.U R *K U H H VN VP H H *M_ST N GN V VPP I_O N/ T SHIEL -- RST LK N/ ET SHIEL UIM_PWR UIM_RST UIM_LK V VW EMI UIM_LK R *R *P UIM_PWR PV stage:dd shielding connect to GN PROJET : OT Quanta omputer Inc. Size ocument Number Rev ustom WN/WWN R ate: Thursday, March, Sheet of E

20 V V U/.V.U.U.U U stage:change power source form VSUS to V due to not support wake up in S V W R R V_PI V_PI V_PI V_V V_V V_V V_V F J K G R E L E V_RIN V_RIN V_ROUT V_ROUT.U.U.U.U U/.V U/.V.U.U.U.U.U.U.U V_M () [..] GN J GN J M GN K M E When HWSPN# is controlled by U GN N system, the pull-up GN R N GN T resistor(r) dose not need to R[..] () N GN V N apply. GN W P R GN L V R/ J P R GN M J R/ R R GN K N R/FRME# R R GN L R/TRY# R R GN L R/EVSEL# T R GN PMSPK# () M N R/STOP# T R GN N U R R R GN N U K R R SHIEL GN E P N R/ V R TEST F L V R/LK T R TEST R K R R/IRY# V R *LOK LINE FOR RUS MOE N N R/PERR# W R N R/PR R R K T R R/E# R R V F K N R/ R HWSPN# T U V R/ W R R PMSPK# R/ R R SPKROUT# F E P N R/E# V R J V R/ W R H T R R/ R E H N R/ V R *K G R R/ W R GRESET# PIRST# G R * T K R.U R/ R F V G K R/ R F UIO U R/ W R PR E S R/ T[..] () () PR V /E# PR UIO H V P T () /E# /E# /E# SL WP T/ U W T () /E# R * /E# /E# UIO H SL T W W T (,) HWPG () /E# /E# /E# V S GN T/ T T () /E# /E# UIO H V T/ P T () ISEL * V T/ T REQ# UIO H T/ M Serial EEPROM T () REQ# V GNT# REQ# T/ M J * NOT Use EEPROM : T () GNT# FRME# GNT# UIO/SRIRQ# SERIRQ (,,) T/ V T () FRME# IRY# FRME# W T/ V T () IRY# TRY# IRY# W T/ W R,R,R : installed T () TRY# EVSEL# TRY# W T/ T R,U,: NOT installed T () EVSEL# R STOP# EVSEL# T T/ V J * Use EEPROM : T () STOP# K PERR# STOP# INT# INT# () R T/ W R: NOT installed T () PERR# SERR_# PERR# T T K T () SERR_# SERR# INT# INT# () T/ R,R,U,,R : E T GRESET# T/ G K installed PIRST# GRST# INT# INTE# () () PIRST# L PLK_R PIRST# () PLK_R K PILK N L E T MIO OE#/ OE# () M SHIEL GN LKRUN# WE#/GNT# WE# () (,,) LKRUN# L U/V R_PME# LKRUN# T MIO E#/ E# () G PME#/RI_OUT# V E#/E# E# () F REG#/E# REG# () H MIO RESET/RST# RESET () G MIO WIT#/SERR# WIT# () R E Stage:R from k chang to MIO WP/LKRUN# WP () *K M K to solve GRST too slow for /Firewire MI MIO RY/INT# RY () F R-V_ MI MIO V/UIO V () E PowerOnReset for Vccore MI MIO V/STSHG V () E H MI MIO VS#/VS VS# () R MIO VS#/VS VS# () When GRESET# is controlled by system, MI #/# # () the pull-up resistor(r) and T MIO #/# # () orelogic LOKRUN# G capacitor() do not need to apply. MI INPK#/REQ# INPK# () MIO When LKRUN# is controlled by IFFERENTIL IMPENE : ohms SHIEL GN system, the pull-down P SV_MSV MIO IOR#/ IOR# () P resistor(r) dose not need to IOWR#/ IOWR# () MIO apply. P V MIO USP T W V MI USM T P N MIO EMI MI MI R MI_R MIO MI R MI_R T PLK_R MI MI_R T R MIO M VPPEN W MIO VPPEN () SHIEL GN V V MI VPPEN VPPEN () T R MI R MI_R MIO VEN# VEN# () *R LK R R VEN# VEN# () K R K VSS R_PME# P VSS PI_PME# () MI R MI_R *P Q T NE HEK FOOTPRINT MI R MI_R R-V_ T S_SLOT V R S K G Q O M.U m.u U R *K SV_MSV PI / OTHER P P MI R GN GN /WP MI_R WP stage:change to push-push type RUS / MEI R R MI R MI_R Q TEU MI change :modify for detect function reserve for MM card detect properly PROJET : OT Quanta omputer Inc. Size ocument Number Rev R() Thursday, March, ate: Sheet of