MODEL REV CHANGE LIST 1 2A 2A 2A 1A 1A 2A 2A 1A 1A 2A 2A 1A 1A 1A 1A 1A 1A 1A CT3/5 MB BOARD. Page CT3/5 MB 31CT3MB CT3MB0031

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1 MOEL REV HNGE LIST Model Page T/ M OR FROM TO T/ M TM00 TM00 PGE --- Enable LKM from clokc generator for the PLL circuit of, and disable the ocsillator circuit of PI PLL. PGE --- Remove H/W shutdown circuit that supported M0. PGE --- Use XR type to replace YV type for PU ecoupling/ypass capacitor. PGE dd a terminal resistor R0 for -OE_RST# to improve signal quality. PGE ---. dd a 0K pull-up resistor on MH_SYN# for booting.. hange the power plane of PIE_WKE# from VSUS to V_S to solve system can't turn off issue.. hange the power plane of IH_THRM# and SI_# from VSUS to +V to reduce leakage. PGE --- We can also use VSUS to instead of V_S to save cost of MOSFET(00). PGE --- dd a level-shift cicuit for EI interface. PGE ---. dd a off-page and a EMI solution for LKM.. Remove the reserve resistors (R~R) of parallel interface for PI0. PGE --- Remove R, connect controller and power switch directly. PGE --- hange R&R value from ohms to 0 ohm cause of OM error at -test. PGE ---. hange M type from YV to XR to improve singal quality.. onnect H/H to GN via a 0 ohm resistor by onexant's comment. PGE ---. dd a terminal resistor R0 for RTL00/0 id selection.. dd a 0.uF to make Q0 turn on slowly to aviod VPU drop issue. PGE --- Modified transformer circuit cause of T can't connect each other on 0/00M application. PGE --- dd a flashrom as PL type for IOS debugging. PGE ---. hange R value from 0K ohms to 0M ohms.. dd a LP debug port for software team to debug convenient. PGE dd GMT fan controller for -test to costdown. PGE ---. dd ES protection circuit for S-VIEO signal to ocking.. dd R to enable the mux in the Tampa- cable PGE --- hange PR value from 00K to 0K to solve display abnormal issue. PGE ---. Move V_S circuit to Page.. e-popuplate PQ and PR.. hange PR value from ohm to ohm. PGE --- Remove P0 and PQ but reserve V_S power circuit

2 MOEL REV HNGE LIST Model Page T/ M OR FROM TO T/ M TM00 TM00 PGE ---. dd 0 for LKM to get better EMI performance. PGE ---. dd R as pull-up resistor for PREQ#. PGE ---. dd RF_OFF# and T_OFF# PGE circuit Populate R0 and 0 to get better EMI performance.. Remove R0 & R0 for unused PIVGF circuit. PGE ---. isconnect SM_PHYS_WP on controller side.. Tie SM_EL_WP with SM_PHYS_WP on conn side to allow for normal operation of S and SM.. dd a discharge circuit for media card power.. dd R to solve cross-talk issue of MS-Pro card.. dd R to solve SM card can't write protect issue.. dd R~R as terminal on all multi-function pins.. dd pull-up circuit. PGE ---. Reserve for RF_OFF# and T_OFF# circuit.. Modify LP pin name. PGE ---. hange H and O select definition. PGE djust apacitors and ead to improve RT timing issue.. hange L, L, L from K0HM0 to.. Remove,,.. hange,, from P to.p.. hange,, 0 from 0P to.p.. hange L, L, L from K0HM0 to LM0SNT. PGE ---. hange L,L,L,,,,,, value to improve S-video quality.. Reserve S-video impedance match circuit

3 P STK UP LYER : TOP LYER : GN LYER : IN LYER : IN LYER : V LYER : OT P THIKNESS:.mm PU THERML SENSOR MX / GMT- +V PGE: V_ORE VP V Processor Intel Pentium-M Intel eleron-m Pins (micro F-PG) FS 00/ MHZ PGE:, HLK_PU HLK_PU# HLK_MH HLK_MH# SR_MH SR_MH# SR_IH SR_IH# REFSSLK REFSSLK# OT OT# 00MHZ 00MHZ 00MHZ 00MHZ 00MHZ MHZ T LOK IGRM PENTIUM-M / LVISO / IH-M.MHz LOK GEN IS0 YZX +V PGE: MHZ MHZ MHZ MHZ MHZ MHZ MHZ SYSTEM POWER MX.VSUS/.V_S PGE: PLK_ PU ORE MX0 PLK_ POWER.V PLK_IH PGE: PLK_MINI PLK_LN SYSTEM POWER MX LK_US POWER(V/V/V) PGE: M_IH RT port PGE: 0 L PanelPGE: MINI-IN PGE: US PORT 0, PGE: R.G, LVS S-VIEO US.0 VP.VSUS +.V +.V +V lviso-gm GMH MI interface 00MHZ X GM/GME PG IH-M PGE:,,.KHz R I/F.V MHz Single hannel MHZ,.V PI R-SOIMM.VSUS SMR_VTERM R-SOIMM PGE: SYSTEM POWER MX VP PGE: NS L VTT_R TT HRGER MX ISHRGE PGE: PGE: PGE: st IE - H PGE: nd IE - ROM PGE: T /00 T /00 +V VSUS +V V_S VSUS +.V +.V.V_S VRT GMH_VTT.KHz 0FM 0 G PGE:,, 0.V LP, MHz PWRLKP PWRLKN I_TN I_TP.MHz X0- MM0-00 PGE: 0 LNV MHz LN Realtek 00L PGE: +V +V LNV MINI-PI PGE:.MHz MHz RUS / IEEE ONTROLLER/F TI PGE:,,, VSUS LE OK aughter oard TV, US, LUE TOOTH PGE: PGE: V OR Power oard PGE: PGE: PI EVIES IRQ ROUTING VPU +V VRT P TQFP PGE: SMRT MOEM, M PGE: WIRE MP TP0 PGE: RJ JK PGE: Intel WLN W00 0.b/g IN R REER S/MM, SM, MS, X PGE: RUS SLOT X PGE: ONN PGE: EVIE ISEL # GIT ETHERNET MINIPI SLOT ardus/ REQ/GNT # 0 PI_INT, E,F,G FN PGE: 0 Touchpad PGE: Keyboard PGE: FLSH PGE: RJ JK PGE: JK HEPHONE, N HEPHONE, MI PGE: PROJET : T Quanta omputer Inc. Size ocument Number Rev ustom LOK IGRM ate: Monday, ecember, 00 Sheet of

4 +V +V L 0L-0 0 ohms@00mhz L 0L-0 0 ohms@00mhz LKV 0.U R.R LK_V LKV R0.R LK_V R R 0.U 0 0.U LK_VREF 0.U 0.U 0.U 0 0.U 0 0.U.U/0V.U/0V.U/0V 0.U 0.U 0.0U_00 Enable LKM from KG. by R0 for the PLL circuit of, and disable the ocsillator circuit at PI side. Sting 0//00 LKM LK_US Iref=.m, Ioh=*Iref OT OT# P P R *M LK_EN# STP_PI#, STP_PU# LK_US R R G_SEL R.K OT OT# R0 R XIN Y.MHZ L=0pF XOUT SMK SMT G_SEL0 G_SEL U_FS LK_VREF LKV LKV LKV LK_V R /F IREF RP X R_OT R_OT# U 0 XTL_IN XTL_OUT V_PI_ V_PI_ V_SR0 V_SR V_SR LK_V 0 VTT_PWRG#/P PI_STOP# PU_STOP# SLK ST FS/US_ FS/TEST_MOE FS/TEST_SEL V_REF V_PU V_ IREF OT OT# V GN_ GN_REF GN_PI_ GN_PI_ GN_SR GN_PU K-0M REF PI PI PI PI PIF PIF0/ITP_EN Place these termination to close K0M. PU0 PU0# PU PU# 0 PU_ITP/SR PU#_ITP/SR# SR SR# SR SR# 0 SR SR# SR SR# SR SR# SR SR# 0 SR0 SR0# M_REF R RP RHLK_PU RHLK_PU# RP RHLK_MH RHLK_MH# T T RSR_IH RSR_IH# RSR_MH RSR_MH# T T T T T T T T RP RREFSSLK RREFSSLK# R_PLK_ R_PLK_ R_PLK_IH R_PLK_MINI R_PLK_LN ITP_EN RP RP R R0 R R R./F X X X X X R R R R R M_IH HLK_PU HLK_PU# HLK_MH HLK_MH# SR_IH SR_IH# SR_MH SR_MH# REFSSLK REFSSLK# PLK_ PLK_ PLK_IH 0 PLK_MINI PLK_LN FS FS FS PU SR PI RESERVE * Frequence select by PU auto sense. SELPS_LK SELPS0_LK R R +V VP VP R 0K R *0K R *K R * OTHN FS 00 OTHN FS R *K G_SEL0 G_SEL G_SEL R * R0 R K K SMT PT_SM SMT To IH-M SMK PLK_SM SMK MH_SEL MH_SEL Q N00E +V +V Q N00E R 0K R 0K To R-SOIMM PV stage: dd 0 for LKM to get better EMI performance. Sting //00 K-0M IS0 EMI MHZ 0 *0P LK_US 0 0P LKM MHZ 0 *0P PLK_ 00 *0P PLK_ 0 *0P PLK_IH 0 *0P PLK_MINI 0 *0P PLK_LN.MHZ M_IH 0m ( MX. ) SMbus address 0 *0P R0 0K R_PLK_LN 0: SRLK=MHZ : SRLK=00MHZ R_PLK_LN HLK_PU HLK_PU# HLK_MH HLK_MH# SR_MH SR_MH# SR_IH SR_IH# REFSSLK REFSSLK# OT OT# ITP_EN 0: SR_ Pair : PU_ ITP Pair R R R R R R R R R R R R R 0K./F./F./F./F./F./F./F./F./F./F./F./F +V R,R othan- can remove so that the FS frequency will be selected by hardware setting(r,r,r,r). othan- should be populated. PROJET : T Quanta omputer Inc. LOK GENERTOR Size ocument Number Rev ustom ate: Monday, ecember, 00 Sheet of

5 E H#[..] U H#[..] H# P S# H# # S# N S# U NR# H#[0..] H#[0..] H# # NR# L NR# PRI# VP H#[0..] U V H# # PRI# J PRI# R H#0 H# H# # EFER# H# 0# # Y V H# H# # EFER# L EFER# RY# H# # # W H# H# # RY# H RY# SY# H# # # T T H# H#0 # SY# M R SY# H# # # U W H# H# 0# HREQ0# H# # # V Y H# H# # R0# N R HREQ0# H# # # R Y H# H# # IERR# H# # # R U H# H# # IERR# 0 PUINIT# H# # # R H#0 H# # INIT# PUINIT# 0 0 H# # 0# Y H# H# # HLOK# H#0 # # U H# HST0# # LOK# J HLOK# H# 0# # V HST0# U H# ST#0 E PURST# H# # # U H# HREQ#0 RESET# PURST# RS#0 H# # # V HREQ#0 R H# HREQ# HREQ# REQ0# RS0# H RS#0 RS# H# # # Y P H# RS# HREQ# REQ# RS# K E RS# H# # # HREQ# T H# RS# HREQ# HREQ# REQ# RS# L HTRY# HSTN0# # # Y P HSTN# HTRY# HREQ# HREQ# REQ# TRY# M HSTN0# HSTP0# HSTP0# STN0# STN# W HSTN# T HSTP# HSTP# H#[..] REQ# HIT# STP0# STP# W HIT# INV#0 INV# H# HIT# K HITM# H#[0..] INV0# INV# T F H#[0..] HITM# H# # HITM# K H# # PM#0 H# H# H#0 # PM#0 T H PM# H# # # H# H# 0# PM# T G PM# H# # # H#0 H# # PM# T L PM# H# # 0# E H# H# # PM# T M PRY# H#0 # # 0 H# H# # PRY# 0 T H PREQ# VP H# 0# # H# H# # PREQ# 0 T F TK H# # # G H# H# # TK TI H# # # J H# H# # TI TO H# # # E E M H# H# # TO TMS H# # # F R J H# H# # TMS TRST# H# # # F L H# H#0 # TRST# R# H# # # F0 E R H# R# N H# 0# R# H# # # E F M H#0 HST# # PU_PROHOT# H# # 0# H# HST# E ST# PROHOT# H THERM H#0 # # F N H# 0 0M# 0M# THERM THERM H# 0# # F K H# 0 FERR# FERR# 0M# THERM HSTN# HSTN# # # F K HSTN# HSTN# 0 IGNNE# IGNNE# FERR# THRMTRIP# HSTP# STN# STN# E HSTP# IGNNE# THERMTRIP# THRMTRIP#,0 HSTP# L STP# STP# E HSTP# INV# J INV# 0 STPLK# STPLK# INV# INV# 0 T 0 INTR INTR STPLK# ITP_LK PM_PSI# OMP0 R./F T T E 0 NMI NMI LINT0 ITP_LK0 HLK_PU# PSI# OMP0 P OMP VP HLK_PU# 0 SMI# HLK_PU SELPS0_LK OMP P R.R LINT LK OMP HLK_PU SELPS0_LK R0./F SMI# LK0 SELPS_LK SEL0 OMP OMP SELPS_LK SEL OMP R.R othan_p MIS R 00/F T0 RSV RSV/PRSTP# G H_PRSTP# 0 T RSV PSLP# H_PSLP# 0 F PWR# T RSV PWR# PWR# PUPWRG T RSV PWRGOO E PUPWRG 0 T E RSV SLP# H_PUSLP#,0 VP R K/F H_GTLREF H_TEST GTLREF TEST Layout note: 0." max length. H_TEST TEST F +V othan_p R R R K/F H_GTLREF = / * VP +-% VP an't shared with GMH *K *K R K R GROUP 0 R GROUP ONTROL XTP/ITP SIGNLS THERM H LK T GRP 0 T GRP T GRP T GRP THRMTRIP# R R R Q MMT0 THRM_E THRM_E To E --> Send FNSIG to control fan. Q +V +V +V +V R N00E 0K R 0K R 0 Remove H/W shutdown circuit (R&Q)that supported M0. Sting 0//00 TI TMS TO PURST# PREQ# R0 0/F R.R R *.R R.R R R VP PV stage: dd R as pull-up resistor for PREQ#. Sting //00, MT 0.U/00 V THLK_SM Q N00E V SMLK THLK_SM THERM THT_SM, MLK XP SMT +V THT_SM 0 _RST# H/W Shutdown 00P THERM H/W MONITOR U XN -OVT -LT GN MX/GMT- IH_THRM# IH_THRM# To S --> System throttling TK TRST# R R./F PROJET : T Quanta omputer Inc. Size ocument Number Rev ustom othan PU (Host us) ate: Monday, ecember, 00 Sheet of E

6 E E TP_SENSE PU_VI0 PU_VI PU_VI PU_VI PU_VI TP_V PU_VI TP_V TP_V TP_VSENSE PU_VI PU_VI PU_VI0 PU_VI PU_VI PU_VI PU_ORE PU_V PU_ORE PU_ORE PU_ORE VP +.V PU_ORE PU_ORE PU_ORE PU_ORE PU_ORE PU_ORE PU_ORE PU_ORE PU_V PU_ORE VP VP Size ocument Number Rev ate: Sheet of PU POWER / GN ustom Monday, ecember, 00 Size ocument Number Rev ate: Sheet of PU POWER / GN ustom Monday, ecember, 00 Size ocument Number Rev ate: Sheet of PU POWER / GN ustom Monday, ecember, 00 PU de-coupling capacitor PU ypass capacitor Remove +.V optional cause of the V is powered by +.V in Intel specification. 0m Use XR type to replace YV type for ecoupling/ypass capacitor. Sting 0//00 Sting 0/0/00 0 0U/0V/00 0 0U/0V/00 0.U 0.U 0.U 0.U 0.U 0.U 0 0U/0V/00 0 0U/0V/00 T T 0U/0V/00 0U/0V/00 0.U 0.U 0 0U/0V/00 0 0U/0V/00 R0 *.R R0 *.R E E E E0 E E 0 E E E0 E E F F F F F 0 F F F F F E 0 E 0 E 0 E0 0 E 0 E 0 E E E0 E E F F F F F 0 F F F F F F F G G G 0 G G H H H H J J J J 0 J K K K K K L L L L 0 M M M M M N N N N N 0 P P P P R R R R R T 0 T T T T U U U U V V 0 V V V W W W W W Y Y 0 Y Y U othan_p U othan_p 0.U 0.U 0.U 0.U 0.U 0.U 0U/0V/00 0U/0V/00 0.U 0.U 0U/0V/00 0U/0V/00 0.U 0.U 0.U 0.U 0.U 0.U R R 0U/0V/00 0U/0V/00 T T R0 *.R R0 *.R 0.U 0.U 0 0U/0V/00 0 0U/0V/00 T T 0.U 0.U 0U/0V/00 0U/0V/00 0.U 0.U 0.U 0.U + 0U/.V_ + 0U/.V_ 0 0U/0V/00 0 0U/0V/00 0.0U_00 0.0U_00 0U/0V/00 0U/0V/00 0.U 0.U Quanta omputer Inc. PROJET : T Quanta omputer Inc. PROJET : T 0 0U/0V/00 0 0U/0V/ U/0V/ U/0V/00 0.U 0.U 0U/0V/00 0U/0V/00 0U/0V/00 0U/0V/00 0.U 0.U 0.U 0.U V0 V V V V V V V V V 0 V0 V V V V 0 V V V V V V0 V V V V 0 V V V V V V0 E V E V E V E V E V E V F0 V F V F V F V0 F V F V V 0 V V V V E V E V E V0 E V E V E V F V F0 V F V F V F V G V G V0 H V H V J V J V K V U V V V V V W V W V0 Y V Y V0 F V/RSV V/RSV N V/RSV VP0 0 VP VP VP VP E VP E VP E VP F0 VP F VP F VP0 F VP K VP L VP L VP M VP M VP N VP N VP P VP P VP0 R VP R VP T VP T VP U VQ0 P VQ W VI0 E VI F VI F VI G VI G VI H VSENSE E SENSE F U othan_p U othan_p 0.U 0.U 0.U 0.U 0.U 0.U 0 0U/0V/00 0 0U/0V/00 0U/0V/00 0U/0V/00 0.U 0.U 0 0U/0V/00 0 0U/0V/00 0U/0V/00 0U/0V/00 0U/0V/00 0U/0V/00 0U/0V/00 0U/0V/00 0 0U/0V/00 0 0U/0V/00 0.U 0.U 0 0.U 0 0.U 0 0.U 0 0.U 0 0U/0V/00 0 0U/0V/00 0U/0V/00 0U/0V/00 0U/0V/00 0U/0V/00 0U/0V/00 0U/0V/00 0U/0V/00 0U/0V/00 0.U 0.U 0.U 0.U 0U/0V/00 0U/0V/00 0U/0V/00 0U/0V/00 0.U 0.U 0 0U/0V/00 0 0U/0V/00 0 0U/0V/00 0 0U/0V/00 0.U 0.U 0U/0V/00 0U/0V/00 0U/0V/00 0U/0V/00 0U/0V/00 0U/0V/00 0U/0V/00 0U/0V/00 0U/0V/00 0U/0V/ U 0 0.U

7 H#[0..] H#[0..] U H#[..] H#[..] H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# HXROMP HXSOMP HXSWING HYROMP HYSOMP HYSWING This group should be routed as 0:0 E E F H E F E K F J J H F K H H H K K J G H J L K J P L J P L U V R R P T R R U R T T R T V U W U V W W U U Y Y V Y W W Y Y W T L P H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# HXROMP HXSOMP HXSWING HYROMP HYSOMP HYSWING HOST H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# HS# HST0# HST# HVREF HNR# HPRI# REQ0# HPURST# HLKINN HLKINP HSY# HEFER# HINV#0 HINV# HINV# HINV# HPWR# HRY# HSTN0# HSTN# HSTN# HSTN# HSTP0# HSTP# HSTP# HSTP# HERY# HHIT# HHITM# HLOK# HPREQ# HREQ0# HREQ# HREQ# HREQ# HREQ# HRS0# HRS# HRS# HPUSLP# HTRY# G E 0 F 0 E0 G0 E F0 G G 0 F G E F F E J E H0 E H K T U G F G K R V G K R W F G H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# H# H# H# H# H# H# H# H# H#0 H# S# HST0# HST# HVREF NR# PRI# HREQ0# PURST# HLK_MH# HLK_MH SY# EFER# INV#0 INV# INV# INV# PWR# RY# HSTN0# HSTN# HSTN# HSTN# HSTP0# HSTP# HSTP# HSTP# HIT# HITM# HLOK# HREQ#0 HREQ# HREQ# HREQ# HREQ# RS#0 RS# RS# HPUSLP# HTRY# S# HST0# HST# NR# PRI# HREQ0# PURST# HLK_MH# HLK_MH SY# EFER# INV#0 INV# INV# INV# PWR# RY# HSTN0# HSTN# HSTN# HSTN# HSTP0# HSTP# HSTP# HSTP# HIT# HITM# HLOK# HREQ#0 HREQ# HREQ# HREQ# HREQ# RS#0 RS# RS# HTRY# VP R0 00/F R0 00/F T T R0 0.U H_PUSLP#,0 LK_SRM0 LK_SRM T LK_SRM LK_SRM T LK_SRM0# LK_SRM# T LK_SRM# LK_SRM# T,,,,,,,, MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP KE0 KE KE KE SM_S0# SM_S# SM_S# SM_S# SMR_VREF MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP LK_SRM0 M LK_SRM L LK_SRM E LK_SRM J LK_SRM F LK_SRM 0 LK_SRM0# N LK_SRM# K LK_SRM# E0 LK_SRM# J LK_SRM# F LK_SRM# 0 KE0 KE KE KE SM_S0# SM_S# SM_S# SM_S# M_OOMP0 F M_OOMP F M_ROMPN M_ROMPP SMXSLEW SMYSLEW Y Y P M H K N M H G P L M N0 K0 K F E E F F0 It's point to point, ohm trace, keep as short as possible. U MIRXN0 MIRXN MIRXN MIRXN MIRXP0 MIRXP MIRXP MIRXP MITXN0 MITXN MITXN MITXN MITXP0 MITXP MITXP MITXP SM_K0 SM_K SM_K SM_K SM_K SM_K SM_K0# SM_K# SM_K# SM_K# SM_K# SM_K# SM_KE0 SM_KE SM_KE SM_KE SM_S0# SM_S# SM_S# SM_S# MI R MUXING SM_OOMP0 SM_OOMP SM_OT0 SM_OT SM_OT SM_OT SMROMPN SMROMPP SMVREF0 SMVREF SMXSLEWIN SMXSLEWOUT SMYSLEWIN SMYSLEWOUT LVISO FG/RSV PM LK N FG0 FG FG FG FG FG FG FG FG FG FG0 FG FG FG FG FG FG FG FG FG FG0 RSV RSV RSV RSV RSV RSV RSV M_USY# EXT_TS0# EXT_TS# THRMTRIP# PWROK RSTIN# REF_LKN REF_LKP REF_SSLKN REF_SSLKP N N N N N N N N N N0 N G FG0 R0 K VP H MH_SEL MH_SEL G MH_SEL MH_SEL F FG FG F FG T G FG FG E FG FG FG FG J FG T FG FG E FG0 T0 FG FG E FG FG H FG FG FG T H FG T J FG FG H FG T G FG FG G FG FG FG0 T G G J 0 +.V R0 R0 0K 0K J PM_MUSY# J PM_EXTTS#0 PM_MUSY# H PM_EXTTS# F R0 THRMTRIP#,0 0 IMVPOK, E R0 0 PLTRST# 0,, OT# OT REFSSLK# REFSSLK P TP_N T N TP_N T0 P TP_N T P TP_N T P TP_N T N TP_N T TP_N T TP_N T TP_N T TP_N0 T TP_N T0 LVISO VP VP VP.VSUS R /F R 00/F HXSWING 0.U R /F R0 00/F HYSWING 0.U VP R.R R R.R R./F./F HXSOMP HXROMP HYSOMP HYROMP R *0./F Route as short as possible. M_OOMP0 M_OOMP R *0./F R 0./F M_ROMPN M_ROMPP R 0./F PROJET : T Quanta omputer Inc. Size ocument Number Rev ustom LVISO-Host ate: Monday, ecember, 00 Sheet of

8 RT_ RT_G RT_R R 0/F R 0/F R 0/F Place near chip 0 0 VSYN HSYN S-VS S-Y S- KLON EILK EIT ISP_ON TXLLKOUT- TXLLKOUT+ TXLOUT0- TXLOUT- TXLOUT- TXLOUT0+ TXLOUT+ TXLOUT+ T T SR_MH# SR_MH# SR_MH SR_MH R R 0/F R0 0/F R 0/F 0 LK 0 T 0 RT_ 0 RT_G 0 RT_R R R R R R /F VSYN_N HSYN_N REFSET R 00K R 00K +.V R.K R.K T T R.K/F T T T T T00 T0 T0 T0 T0 T0 T0.K/F H H J E E E 0 0 H G J0 E F F F F F F 0 UF SVOTRL_T SVOTRL_LK GLKN GLKP TV_ TV_ TV_ TV_REFSET TV_IRTN TV_IRTN TV_IRTN LK T LUE LUE# GREEN GREEN# RE RE# VSYN HSYN REFSET LKLT_TRL LKLT_EN LTL_LK LTL_T L_LK L_T LV_EN LIG LVG LVREFH LVREFL LLKN LLKP LLKN LLKP LTN0 LTN LTN LTP0 LTP LTP LTN0 LTN LTN LTP0 LTP LTP MIS TV VG LVS PI-EXPRESS GRPHIS EXP_OMPI EXP_IOMPO EXP_RXN0 EXP_RXN EXP_RXN EXP_RXN EXP_RXN EXP_RXN EXP_RXN EXP_RXN EXP_RXN EXP_RXN EXP_RXN0 EXP_RXN EXP_RXN EXP_RXN EXP_RXN EXP_RXN EXP_RXP0 EXP_RXP EXP_RXP EXP_RXP EXP_RXP EXP_RXP EXP_RXP EXP_RXP EXP_RXP EXP_RXP EXP_RXP0 EXP_RXP EXP_RXP EXP_RXP EXP_RXP EXP_RXP EXP_TXN0 EXP_TXN EXP_TXN EXP_TXN EXP_TXN EXP_TXN EXP_TXN EXP_TXN EXP_TXN EXP_TXN EXP_TXN0 EXP_TXN EXP_TXN EXP_TXN EXP_TXN EXP_TXN EXP_TXP0 EXP_TXP EXP_TXP EXP_TXP EXP_TXP EXP_TXP EXP_TXP EXP_TXP EXP_TXP EXP_TXP EXP_TXP0 EXP_TXP EXP_TXP EXP_TXP EXP_TXP EXP_TXP E0 F G0 H J0 K L0 M N0 P R0 T U0 V W0 Y 0 E F0 G H0 J K0 L M0 N P0 R T0 U V0 W E F G H J K L M N P R T U V W Y E F G H J K L M N P R T U V W EXP_OMP R T T T T T T T0 T T T T T T T T T T00 T0 T0 T0 T0 T0 T0 T0 T0 T0 T0 T T T T T T T T0 T T T T T T T0 T T T T T T T T T T0 T T T T T T T T T T0 T T./F VG_PIE +.v These pins can't leave as N if we didn't use PI-E on system cause it also used for MI compensation. LVISO Strapping FG R *.K FG FG FG FG FG FG FG R *.K R *.K R0 *.K FG R *.K FG FG R.K FG[:0] 00=MT/S FS 0=00MT/S FS FG[:] have internal pullup. FG[:] have internal pulldown. Low=MIx High=MIx (efault) Low=PIE Reverse Lanes High=PIE Normal Operation (efault) 00 : Reserved 0 : XOR Mode Enabled Low=R II High=R (efault) Low=FS ynamic OT isabled High=FS ynamic OT Enabled 0 : ll Z Mode Enabled : Normal Operation (efault) (efault) FG FG +.V FG FG FG FG +.V R *.K Low=T/Transportable PU High=Mobile PU (efault) FG FG Low=PU core V.0V High=PU core V.V R *K (efault) Low=FS R *.K Low=R R *.K FG FG R *K Low=PU VTT.0V High=PU VTT.V (efault) Size ocument Number Rev ustom LVISO MI ate: Monday, ecember, 00 Sheet of PROJET : T Quanta omputer Inc.

9 S_RVENIN# M M R_SM_QS0 R_SM R_M R_M R_M S_RVENOUT# M M R_SM R_M R_M R_M R_M M M M M M M R_SM_QS R_SM R_M0 R_M R_M R_M R_M R_M0 R_M R_M0 M M M M M M M M R_SM R_SM R_M0 R_M R_M M M R_M R_M R_M R_M0 R_M R_M M SRS# M 0 R_SM R_M R_M R_M R_M R_M M M M M M SS# R_M R_M R_M R_M M M R_SM_QS R_SM_QS R_SM0 R_M R_M R_M S_RVENIN# M M M M M M SS# R_SM_QS R_SM R_M R_M R_M R_SM_QS R_M R_M R_M R_M M M M M M M M M R_M R_M R_M R_M R_M M M R_M R_M R_M M M M MWE# R_SM_QS R_M M M0 M M0 R_M0 R_M R_M M M0 M M R_M0 R_M R_M R_M R_M R_M R_M R_SM_QS R_M R_M M M0 M M M M M SRS# M M[0..] R_M R_M R_M0 M M M R_M R_M R_M R_M M R_M M R_M R_M R_M R_M M M R_M R_M R_M R_M R_M0 R_M M M R_M R_M M R_M0 R_M R_M R_M M R_M R_M M R_M0 M R_M R_M M R_M M R_M R_M R_M M0 M0 M M M R_M R_M M R_M R_M M M M R_M M0 M R_M R_M0 R_M M M0 R_M M R_M M R_M M0 R_M R_M R_M M M M R_M R_M M M M R_M M M M M M0 R_M0 M M R_M R_M0 M R_M R_M M M M M R_M R_M M R_M M R_M M M M R_M R_M M M R_M M M M M M0 M R_M M R_M M R_SM R_SM_QS SM R_SM_QS R_SM SM0 SM SM_QS0 SM_QS R_SM_QS R_SM_QS SM SM_QS SM R_SM R_SM R_SM R_SM_QS SM_QS R_SM SM R_SM_QS R_SM SM SM_QS R_SM0 SM_QS R_SM_QS R_SM_QS0 SM_QS SM_QS SM M M M M M M M M M M M M M M M M0 M M M M M M M M M M M0 M M M0 M M M0 M M0 M M M M M M M M M M M M M M M0 M M M M M M M M M0 M M M M M M M M M M M M M SM_S0# M M M M KE0 M M SM_S# KE M M M M M M SM_S# KE M M M M M M M M M MWE# M M0 SM_S# M SRS# M M M M M M M SS# M M M 0 M M SRS# M M M M KE M M M SS# M M0 M M M M M M M0 M M SM SM SM_QS SM SM SM SM_QS SM_QS SM_QS SM0 SM_QS0 SM SM SM_QS SM_QS SM_QS M M 0 SM_S0# M M[0..] M SS# M SRS# M SRS# M M[0..] SM_S# SM_S# M MWE# KE[0..] SM_S# SM_QS[0..] M[0..] SM[0..] M M0 M M M 0 M 0 M 0 M MWE# M SS# S_RVENOUT# M MWE# M MWE# M M[0..] SM_S#, M SRS# M SM_S0#, M 0 M SS# SM_S#, KE[0..], M MWE# M M[0..] M M[0..] M SRS# SM_S#, M[0..] SM_QS[0..] SM[0..] M M 0 M MWE# M SS# SMR_VTERM SMR_VTERM SMR_VTERM SMR_VTERM SMR_VTERM Size ocument Number Rev ate: Sheet of LVISO R ustom Monday, ecember, 00 Size ocument Number Rev ate: Sheet of LVISO R ustom Monday, ecember, 00 Size ocument Number Rev ate: Sheet of LVISO R ustom Monday, ecember, 00 For terminal R-pack. 0 0.U 0 0.U RN PR-S- RN PR-S- RN0 PR-S-0 RN0 PR-S-0 0.U 0.U R R R R R R R R T0 T0 RN0 PR-S-0 RN0 PR-S U 0 0.U Quanta omputer Inc. PROJET : T Quanta omputer Inc. PROJET : T 0 0.U 0 0.U RN PR-S-0 RN PR-S U 0 0.U RN PR-S-0 RN PR-S-0 R R R R R R RN PR-S- RN PR-S- RN PR-S- RN PR-S U 00 0.U R R R R R R R R R0 R R0 R RN PR-S- RN PR-S- RN0 PR-S- RN0 PR-S- RN PR-S- RN PR-S- RN PR-S- RN PR-S- RN PR-S- RN PR-S- RN PR-S- RN PR-S- RN PR-S- RN PR-S- RN PR-S- RN PR-S- RN0 PR-S-0 RN0 PR-S-0 R R 00 0.U 00 0.U RN PR-S- RN PR-S- RN PR-S- RN PR-S- R R 0.U 0.U SQ0 E SQ E SQ G SQ G SQ E SQ E SQ F SQ F0 SQ H SQ H SQ0 K SQ G0 SQ G SQ G SQ H SQ J SQ K0 SQ J0 SQ H SQ H SQ0 K SQ H0 SQ H SQ G SQ F SQ G SQ J SQ K SQ H SQ H SQ0 G SQ J SQ G0 SQ G SQ G SQ H SQ H SQ H0 SQ J SQ K SQ0 J SQ K SQ J SQ H SQ K SQ J SQ J SQ K SQ G SQ G SQ0 SQ SQ H SQ G SQ E SQ SQ SQ SQ SQ SQ0 SQ SQ SQ S_S0# J S_S# G S_S# G S_M0 F S_M K S_M K S_M K S_M J0 S_M K S_M E S_M S_QS0 F S_QS K S_QS J S_QS K S_QS M0 S_QS H S_QS F S_QS S_QS0# F S_QS# K S_QS# K S_QS# J S_QS# L0 S_QS# H S_QS# F S_QS# S_M0 H S_M K S_M H S_M J S_M K S_M J S_M K S_M H S_M J0 S_M H0 S_M0 J S_M G S_M G0 S_M G S_S# H S_RS# K S_RVENIN# F S_RVENOUT# F S_WE# H R SYSTEM MEMORY UG LVISO R SYSTEM MEMORY UG LVISO RN PR-S-0 RN PR-S-0 RN PR-S- RN PR-S- R R RN0 PR-S- RN0 PR-S- 0 0.U 0 0.U 00 0.U 00 0.U RN PR-S- RN PR-S- RN PR-S-0 RN PR-S-0 RN PR-S- RN PR-S- R R R R RN PR-S-0 RN PR-S-0 0.U 0.U RN0 PR-S- RN0 PR-S- RN0 PR-S- RN0 PR-S- 0 0.U 0 0.U RN PR-S-0 RN PR-S U 0 0.U RN PR-S-0 RN PR-S-0 RN PR-S- RN PR-S- RN0 PR-S- RN0 PR-S- RN PR-S- RN PR-S U 00 0.U R R R R R R RN0 PR-S-0 RN0 PR-S-0 0.U 0.U RN00 PR-S-0 RN00 PR-S-0 RN PR-S- RN PR-S- RN0 PR-S- RN0 PR-S U 00 0.U RN PR-S-0 RN PR-S-0 RN0 PR-S- RN0 PR-S- RN PR-S- RN PR-S- R R 0 0.U 0 0.U RN PR-S-0 RN PR-S U 00 0.U R R R R RN PR-S- RN PR-S- 0 0.U 0 0.U R R RN0 PR-S-0 RN0 PR-S U 0 0.U R R RN PR-S- RN PR-S- RN PR-S- RN PR-S- SQ0 G SQ H SQ L SQ L SQ H SQ J SQ K SQ L SQ M SQ N SQ0 P SQ M SQ M SQ M SQ L SQ M SQ N SQ P SQ N SQ P SQ0 L0 SQ M0 SQ M SQ L SQ P SQ M SQ M SQ M SQ L SQ M SQ0 N SQ P SQ M SQ L SQ L SQ P SQ P SQ P0 SQ L SQ M SQ0 N SQ N SQ N SQ P SQ P SQ M SQ L SQ M SQ K SQ K SQ0 G SQ G SQ L SQ M SQ H SQ G SQ F SQ E SQ SQ SQ0 F SQ F SQ SQ S_S0# K S_S# K S_S# L S_M0 J S_M P S_M L S_M P S_M P S_M P S_M J S_M S_QS0 K S_QS P S_QS N S_QS P S_QS M S_QS M S_QS J S_QS E S_QS0# K S_QS# P S_QS# N0 S_QS# N S_QS# N S_QS# M S_QS# H S_QS# E S_M0 L S_M P S_M P S_M M S_M N S_M M S_M L S_M P0 S_M M S_M L0 S_M0 M S_M N0 S_M M0 S_M M S_S# N S_RS# P S_RVENIN# F S_RVENOUT# F S_WE# P R SYSTEM MEMORY U LVISO R SYSTEM MEMORY U LVISO RN PR-S-0 RN PR-S-0 R R R R RN PR-S- RN PR-S- RN PR-S- RN PR-S- RN PR-S- RN PR-S- R R R R RN PR-S- RN PR-S- RN PR-S- RN PR-S- RN PR-S-0 RN PR-S-0 R0 R0 RN PR-S- RN PR-S- RN PR-S-0 RN PR-S-0 R0 R R0 R 0 0.U 0 0.U 0 0.U 0 0.U RN0 PR-S- RN0 PR-S- RN0 PR-S- RN0 PR-S- 0 0.U 0 0.U 00 0.U 00 0.U 0 0.U 0 0.U RN PR-S-0 RN PR-S-0 RN PR-S-0 RN PR-S U 0 0.U RN PR-S- RN PR-S- R R 00 0.U 00 0.U RN0 PR-S-0 RN0 PR-S U 0 0.U RN PR-S-0 RN PR-S-0 RN PR-S-0 RN PR-S-0 RN PR-S- RN PR-S- R R R R RN PR-S- RN PR-S- R R R R RN PR-S- RN PR-S- RN PR-S-0 RN PR-S U 00 0.U R R U U RN PR-S- RN PR-S- 0 0.U 0 0.U RN PR-S-0 RN PR-S-0 RN PR-S-0 RN PR-S U 0 0.U 00 0.U 00 0.U RN PR-S- RN PR-S- RN PR-S- RN PR-S- T T RN0 PR-S- RN0 PR-S- RN PR-S- RN PR-S- RN PR-S- RN PR-S- 0 0.U 0 0.U RN PR-S-0 RN PR-S-0 T T R R R R R R R0 R0 RN PR-S-0 RN PR-S-0 RN PR-S- RN PR-S- RN PR-S- RN PR-S U 00 0.U RN PR-S-0 RN PR-S-0 RN0 PR-S- RN0 PR-S- T T RN PR-S- RN PR-S U 00 0.U RN PR-S- RN PR-S- RN PR-S-0 RN PR-S-0 R R R R 0.U 0.U RN PR-S- RN PR-S- RN PR-S-0 RN PR-S-0 0.U 0.U R R R R RN PR-S-0 RN PR-S-0 RN PR-S- RN PR-S- RN PR-S- RN PR-S- RN PR-S- RN PR-S- R R

10 +.V L uh m + 0U 0.U 0m L LMS +.V VP +.V L uh R 0.U 0.0U U 0U.U.U/0V 0m L 0uH +.V RV-0 0.U 0.U 0.U 0.U + 0.U 0U VP 0m +.V L 0uH +.V 0.U/ U 0.U 0m 0U/0V/00 VP +.V m VP_GMH_P VP_GMH_P VP_GMH_P VP_GMH_P 0m VP. K K T V W K U V K0 T0 U0 W0 K K K K J K H K H J K L M N P R T U V G H J K L M N P R T U V J K M N R T 0U/0V/00 0U/0V/00 0U/0V/00 0.U V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 +.V +V V_MPLL V_HPLL V_PLL V_PLL VH_MPLL0 VH_MPLL V_RT G V_RT E V_RT0 F V_SYN H0 G M N V M N M N M N M N M N M N M N J L M N P R U W Y J0 K0 M0 N0 P0 R0 T0 U0 V0 W0 K L M N P R T U V W K J K UH 0.U 0.U VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 0m POWER RV-0 R0 R _GG V_GG V_GPLL V_GPLL V_GPLL0 VG VG VG VG VG VG VG0 V_SM V_SM V_SM V_SM0 VTX_LVS VTX_LVS VTX_LVS0 VSM VSM VSM VSM VSM0 VSM VSM VSM VSM VSM VSM VSM VSM VSM VSM0 VSM VSM VSM VSM VSM VSM VSM VSM VSM VSM0 VSM VSM VSM VSM VSM VSM VSM VSM VSM VSM0 VSM VSM VSM VSM VSM VSM VSM VSM VSM VSM0 VSM VSM VSM VSM VSM VSM VSM VSM VSM VSM0 VSM VSM VSM VSM VSM VSM VSM VSM VSM VSM0 VHV VHV VHV0 V_LVS V_LVS V_LVS V_LVS0 VQ_TV V_TV _TVG V_TVG V_TV V_TV0 V_TV V_TV0 V_TV V_TV0 E F E F G H H 0.0U E M P 0 E F G H J K L M N P E F G H J K L M N P E E E E E E E0 E E E E E F G H J K L M N P E F G H J K L M N P P H M F F P F0 J L N R U W E Y Y Y G F 0.U 0 0.0U 0.U 00 0.U L LMS 0 0.U V._R_P +.V V._R_P.VSUS V._R_P.0 0.U 0.U 0.U 0.U + 0U/0V/00 0m 0U/.V/ESR- 0U/0V/00 +.V 0.0U U.U/0V Note: ll VSM pins shorted internally. Note: ll VSM pins U 0.U 0.U shorted internally U V._R_P V._R_P V._R_P V_RLL VG_PIE V_GPLL +.V L0 m L +.V V_RLL 00m +.V R 0./F V_GPLL m 0 0.U 0 0.0U LMS LMS 0.U + 00U 0U/0V/ U +.V L LMS 0.0U 0.U 0m 0m VG_PIE L +.V +.V m +.V +.V VG_PIE PROJET : T Quanta omputer Inc. 0.U 0 0.U LMS + 0U/0V/00 0.0U_00 0U/0V/00 0U 0.U Size ocument Number Rev ustom LVISO POWER 0U/0V/00 0U/0V/00 ate: Monday, ecember, 00 Sheet of

11 .VSUS VP VP Size ocument Number Rev ate: Sheet of LVISO /NTF ustom Monday, ecember, 00 Size ocument Number Rev ate: Sheet of LVISO /NTF ustom Monday, ecember, 00 Size ocument Number Rev ate: Sheet of LVISO /NTF ustom Monday, ecember, 00 0 G Y V T P M K H E N 0 L J F E E 0 Y W V U T R P N M L 0 K J H G F E N H 0 L F W V 0 U T R P N M L K J H 0 G F E N J 0 Y L G W V U T 0 R P N M L K J H G F 0 E P0 E Y0 0 M 00 J 0 G W 0 V 0 U 0 P 0 L 0 H 0 G F E W E 0 N L J G F W G E 0 J G J F F H L H 0 J E N F F K0 V0 0 G0 F0 E0 0 0 N G W T J 0 H L U N J F G 0 L K H K N L 0 J G K J F J 0 N L J G F Y H F 0 00 Y0 0 L N 0 H 0 E V 0 T 0 K H L Y P L E N 0 K G V G J E T 0 P L J P L W E N F 0 Y U P L H J 0 N L H E V T P 0 L J G E N L J G 0 Y LVS UE UE VTT_NTF0 W VTT_NTF V VTT_NTF U VTT_NTF T VTT_NTF R VTT_NTF P VTT_NTF N VTT_NTF M VTT_NTF L VTT_NTF W VTT_NTF0 V VTT_NTF U VTT_NTF T VTT_NTF R VTT_NTF P VTT_NTF N VTT_NTF M VTT_NTF L VSM_NTF0 VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF0 VSM_NTF VSM_NTF 0 VSM_NTF 0 VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF0 VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF0 VSM_NTF V_NTF0 W V_NTF V V_NTF U V_NTF T V_NTF R V_NTF P V_NTF N V_NTF M V_NTF L V_NTF W V_NTF0 V V_NTF U V_NTF T V_NTF R V_NTF P V_NTF N V_NTF M V_NTF L V_NTF W V_NTF V V_NTF0 U V_NTF T V_NTF R V_NTF P V_NTF N V_NTF M V_NTF L V_NTF W V_NTF V V_NTF U V_NTF0 T V_NTF R V_NTF P V_NTF N V_NTF M V_NTF L V_NTF W V_NTF V V_NTF U V_NTF T V_NTF0 R V_NTF P V_NTF N V_NTF M V_NTF L V_NTF W V_NTF V V_NTF U V_NTF T V_NTF P V_NTF0 N V_NTF M V_NTF L V_NTF Y0 V_NTF R0 V_NTF P0 V_NTF N0 V_NTF M0 V_NTF L0 V_NTF Y V_NTF0 R V_NTF P V_NTF N V_NTF M V_NTF L V_NTF Y V_NTF R V_NTF P V_NTF N V_NTF M V_NTF0 L V_NTF W V_NTF V V_NTF U V_NTF T V_NTF P V_NTF N V_NTF M V_NTF L _NTF0 _NTF _NTF Y _NTF _NTF _NTF Y _NTF _NTF _NTF Y _NTF _NTF0 _NTF Y _NTF _NTF _NTF Y _NTF _NTF _NTF Y _NTF R _NTF 0 _NTF0 0 _NTF _NTF _NTF _NTF _NTF _NTF _NTF Y _NTF R _NTF _NTF0 _NTF Y _NTF W _NTF V _NTF U _NTF T _NTF R _NTF P _NTF N _NTF M _NTF0 L _NTF _NTF _NTF Y _NTF W _NTF V _NTF U _NTF T _NTF R _NTF P _NTF0 N _NTF M _NTF L _NTF _NTF _NTF Y _NTF W _NTF V _NTF U _NTF T _NTF0 R _NTF P _NTF N _NTF M _NTF L _NTF _NTF Y _NTF _NTF Y NTF U NTF U Quanta omputer Inc. PROJET : T Quanta omputer Inc. PROJET : T

12 VP FERR# R H_PSLP# R *R RIN# R GTE0 R PIORY R.K VPU 000P R 0K 0K VRT +V +V +V R00V-0 R00V-0 T RT-T R *R P VRT PLK_IH 0 *P RT VRT R 0K RT_N0 RT_N0 R Q MMT0 Y0.KHZ U/V P U/V K R 0M RTRST# VRT NMI 0M# FERR# IGNNE# INTR PUINIT# RIN# GTE0,, [0..] VPU R.K R0 K,, PI_PME# PLK_IH,, LKRUN# R G *SHORT_ P +V LK_KX LK_KX RTRST# M NMI 0M# FERR# R IGNNE# INTR PUINIT# RIN# GTE0 [0..] PLK_IH PI_RST# PLTRST#_ SM_INTRUER# R.K R U0 Y RTX Y RTX RTRST# INTRUER# INTVRMEN F NMI F 0M# F FERR# G IGNNE# G INTR F INIT# RIN# F 0GTE E 0 E F F E F E 0 H J K K L G 0 H H H M K K L 0 K P PME# G PILK R PIRST# R PLTRST# F LKRUN#/GPIO RT LP PU PI L0 L/F L/F L/F LRQ0# LRQ#/GPI LFRME# PUPWRG/GPO INIT_V# THRMTRIP# SMI# STPLK# PUSLP# PSLP#/TP[] PRSLP#/TP[] /E0# /E# /E# /E# FRME# IRY# TRY# EVSEL# STOP# PR SERR# PERR# PLOK# REQ0# REQ# REQ# REQ# REQ#/GPI0 REQ#/GPI REQ#/GPI0 GNT0# GNT# GNT# GNT# GNT#/GPO GNT#/GPO GNT#/GPO PIRQ# PIRQ# PIRQ# PIRQ# PIRQE#/GPI PIRQF#/GPI PIRQG#/GPI PIRQH#/GPI P N N N N P P GPI R0 R G PUPWRG PUPWRG E T E THERMTRIP#_IH R R THRMTRIP#, PI Pullups G R SMI# E STPLK# +V STPLK# E R * RP H_PUSLP#, R REQ# H_PSLP# E R STOP# H_PRSTP# REQ0# INT# INT# INT# +V 0 INT# J /E0#,, H.KX /E#,, G /E#,, G +V /E#,, RP J FRME# FRME#,, IRY# REQ# FRME# IRY#,, J TRY# SERIRQ TRY# TRY#,,,,, SERIRQ EVSEL# IRQ EVSEL#,, J STOP# RT_SENSE# STOP#,, +V 0 PR PR,, G SERR#.KX SERR#,, E PERR# PERR#,, PLOK# +V PLOK# RP RT_SENSE#,0 L REQ0# IRY# REQ0# REQ# EVSEL# LYI REQ# M REQ# REQ# PERR# REQ# REQ# PLOK# SERR# F GPI0 +V 0 LYI0 E LYI0 LYI.KX F E F N L M L M INT# INTH# Internal already pull-up L0/FWH0 L/FWH L/FWH L/FWH LP_RQ0# LFRME#/FWH GNT0# GNT# GNT# T0 T T T INT# INT# INT# INTE# INTF# INTG# VP These signals have internal pull-up PIRQ#: RTL00L PIRQ#: N PIRQ#: MINI PI PIRQ#: MINI PI PIRQE#: PIRQF#: PIRQG#: PIRQH#: Internal US escription For oathan -X step For oathan -X step & later GPI0 INTG# INTF# INTE# INTH# R *0 RP PR-.K R.K +V R *0 0 PI_RST#,, PLTRST# +V 0.U U TSH0FU R * PLTRST# R U R VSUS SZ 0 0.0U PLTRST#_ PIRST#,,, P[0..] PS# PS# P0 P P PIOR# PIOW# PIORY IRQ PREQ PK# P[0..] PS# PS# P0 P P PIOR# PIOW# PIORY IRQ PREQ PK# P0 P P P P P P P P P P0 P P P P P F F E E F E G E E F 0 0 S# S# 0 IOR# IOW# IORY IEIRQ REQ K# IH-M_ IE ST -/ ZLI STLE# ST0_RXN ST0_RXP ST0_TXN ST0_TXP ST_RXN ST_RXP ST_TXN ST_TXP ST_LKN ST_LKP STRIS# STRIS Z_IT_LK Z_SYN Z_RST# Z_SIN0 Z_SIN Z_SIN Z_SO E G F F G G F 0 0 R0 F F0 0 _SIN T0 R T T T T onnect to GN if S-T didn't use on platform ITLK,0, SYN,0, -OE_RST,0, SIN 0, SIN T SOUT,0, 0- -MOEM GPI PV stage: GPI0 & GPI for bios request. Griffey //00 Intel suggested us to add a terminal resistor R0 for -OE_RST to improve signal quality. Sting 0//00 R0.K PROJET : T Quanta omputer Inc. Size ocument Number Rev ustom IH-M (PU/PI/IE) ate: Monday, ecember, 00 Sheet 0 of

13 E USP0+ USP+ USP0+ USP0- USP0P USPP 0 RP USP+ USP- O# USP0- O0# USP0N USPN 0 O# USP- O# O0# VSUS LK_US M_IH USP+ O0# O# O# O# USP+ USP- USPP USPP O# O# USP- O# USPN USPN US O# O# USP+ USP+ VSUS 0 O# O# USP+ USP- USPP USPP USP+ R R USP- USP- E O# USPN USPN O# USP- 0KX R *R O#/GPI O#/GPI0 USPP USPP O# USPN USPN O# 0 0 O#/GPI O#/GPI LK_US USRIS.P *P USRIS LK_US R./F LK USRIS# Place within 00mils of IH- MI_RXN0 MI_RXN MI_RXN0 T MI_RXP0 MI0_RXN MI_RXN Y MI_RXP MI_RXN MI_RXP0 T Y MI_RXP MI_TXN0 MI0_RXP MI_RXP MI_TXN MI_TXN0 R MI_TXN MI_TXP0 MI0_TXN MI_TXP MI_TXP0 R MI MI_TXN W W MI0_TXP MI_TXP MI_TXP MI_RXN MI_RXN MI_RXN V MI_RXN MI_RXP MI_RXN MI_RXN MI_RXP MI_RXP V MI_RXP MI_TXN MI_RXP MI_RXP MI_TXN MI_TXN U MI_TXN MI_TXP MI_TXN MI_TXN MI_TXP MI_TXP U MI_TXP MI_TXP MI_TXP SR_IH# SR_IH# F SR_IH SR_IH MI_LKN MI_ZOMP F MI_ZOMP R./F MI_LKP MI_IROMP +.V Place within 00mils of IH- T0 H HSIN0 HSIN M T T H M HSIP0 HSIP G PI-EXPRESS T +V T HSON0 HSON L T G L RP T HSOP0 HSOP T STGP K STGP T HSIN HSIN P T K STGP T0 HSIP HSIP P T J ST0GP T HSON HSON N T T J N HSOP HSOP T PR-0K PLK_SM SMLINK0 PLK_SM Y W PT_SM SMLK SMLINK0 W SMLINK PT_SM These signals should be SMLERT# SMT SMLINK U SM_LINK_LERT# W SM&SMI Y SMLERT#/GPI LINKLERET# RI# SUS# RI# T IH_THRM# RI# SLP_S# T SUS# SUS# IH_THRM# 0 T PWROK THRM# SLP_S# SUS# LN_RST# should be connected to PWROK PRSLPVR PWROK SLP_S# T T PRSLPVR E0 V PLTRST# PLTRST# if internal LN didn't use. +V TLOW# PRSLPVR/TP PLTRST#,0, TLOW# V PM LN_RST# U R# NSWON# TLOW#/TP0 SYS_RESET# R# PIE_WKE# NSWON# U U R 0K SP_ON RSMRST# PWRTN# WKE# MH_SYN# SUS# RSMRST# Y G R *0K IMVPOK RSMRST# MH_SYN#, IMVPOK F PM_MUSY# VRMPWRG STP_PI# PM_MUSY# STP_PI# R *0K PLTRST# SUS_STT# M_USY#/GPIO STP_PI#/GPO W STP_PU# PWROK SUSLK SERIRQ STP_PU#, R 0K SUS_STT#/LPP# STP_PU#/GPO0 RSMRST# T V SERIRQ 0,,, R0 0K SUSLK SERIRQ 0 M_IH SM_EN# M_IH E0 P SPK LK GPIO T ST0GP 0 SPK F F RT_SENSE# SPKR ST0GP/GPIO FPK# 0,0 RT_SENSE# E R FPK# KSMI# GPI GPIO LI KSMI# R T SI_# GPI STGP LI M MIS&GPIO GPIO E SS SWI_# GPI STGP/GPIO R F STGP GPI STGP/GPIO0 STGP SI# G GPO STGP/GPIO VSUS SWI# 0 SS GPO F0 SP_ON GPO LI SP_ON RP GPIO V SUS_STT# S_RF_OFF# LI R 0 GPIO GPIO, RF_OFF# TLOW# S_T_OFF#, T_OFF# R# R 0 E MH_SYN# R 0K RI# LN_RX0 +V E EE_S LN_RX PR-0K LI0 EE_SHLK LN_RX LI0 LN EE_OUT LN_TX0 F RP EE_IN LN_TX E SWI_# LN_TX PV stage: F SMLINK. dd RF_OFF# and T_OFF# LN_LK SMLINK0 LN_RSTSYN circuit. Griffey /0/00 PR-0K RSV RSV F RSV RSV F RESERVE G RP RSV RSV G U PT_SM RSV RSV PLK_SM RSV SMLERT# IH-M_ SM_LINK_LERT# +V V_S PR-0K R *0K R0 R SUS# 0K 0K IH_THRM# SI_# R *0K *0.U V_S V_S U *NWZPX R *K R * V_S U U0 *NWZPX RSMRST# LI0 LI LI Enable able I RN PR-0K +V pulled-up to +V via a.k~0k if didn't used as S-T interlock switch or GPI signals. R should be populated, because MH_SYN# is internally Ned with PWROK.System will not booting without this pulled-up resistor. Sting 0//00 R PIE_WKE#. hange the power plane of PIE_WKE# from VSUS to V_S to solve system can't turn off issue.. hange the power plane of IH_THRM# and SI_# from VSUS to +V to solve leakage issue. Sting 0/0/00 PROJET : T Quanta omputer Inc. Size ocument Number Rev ustom IH-M (US/HU/LP) ate: Monday, ecember, 00 Sheet of E

14 VREF_SUS +.V_PIE VREF_SUS VREF_SUS VREF VREF +.V.V_S.V_S V_S +.V +.V VRT +.V +V V_S V_S +.V +.V V_S +V +.V +.V +.V +V VP +.V VRT V_S V_S.V_S +V VSUS +V +V Size ocument Number Rev ate: Sheet of ustom Monday, ecember, 00 Size ocument Number Rev ate: Sheet of ustom Monday, ecember, 00 Size ocument Number Rev ate: Sheet of ustom Monday, ecember, 00 IH-M (POWER) 00m We can also use VSUS to instead of V_S to save cost if V_S isn't implemetation on system. Sting 0//00 PV stage: The root cause that is V_S leakage current to VSUS by R on S/S stage. Griffey //00 0.U 0.U 0.U 0.U RV-0 RV-0 0.U 0.U R00 R00 U/V U/V 0 0.U 0 0.U 0.0U_00 0.0U_00 0.U 0.U L LMP00SPG L LMP00SPG 0.U 0.U 0.U 0.U 0.U 0.U 0.U 0.U U/V U/V 0.U 0.U 0.U 0.U 0.U 0.U 0.U 0.U 0.U 0.U 0.U 0.U 0.U 0.U E0 0 E 0 E 0 E 00 E 0 E 0 E 0 E 0 F0 0 F 0 F 0 F 0 F 00 G 0 F 0 0 G 0 G 0 G 0 G0 0 G 0 G 0 G E 0 E 00 E 0 E 0 E 0 F 0 F 0 F 0 F 0 G 0 G 0 G 00 G 0 G 0 H 0 H 0 H 0 J 0 J 0 J 0 J 0 K 00 K 0 K 0 K 0 K 0 L 0 L 0 L 0 L 0 L 0 M 0 M M M M M M M M N N 0 N N N N N N N P P P 0 P P P R R R R R R R 0 R R R R T T T T T T 0 T T T T U U U U U V 0 V V V W W W W W Y Y 0 Y Y E GN U0 IH-M_ GN U0 IH-M_ 0.U 0.U 0.U 0.U U/V U/V 0.U 0.U 0 0.U 0 0.U 0.U 0.U 0.0U_00 0.0U_00 U/V U/V 0.U 0.U 0U/0V/00 0U/0V/00 0.U 0.U 0.U 0.U 0.U 0.U Quanta omputer Inc. PROJET : T Quanta omputer Inc. PROJET : T 0 0.U 0 0.U V V V V V V V V F V F V 0 F V G V G V G V G V H V H V J V J V K V 0 K V L V L V M V M V N V N V N V N V N V 0 P V P V P V P V R V R V T V T V U V U V 0 V V V V W V W V Y V Y V V V V V 0 V V E V E V F V G V V V V V 0 V V E V E V F V G VMIPLL V E VSTPLL E V G0 VLN_/VSUS VLN_/VSUS F VLN_/VSUS G VLN_/VSUS G VSUS VSUS U VSUS V VSUS V VSUS W VSUS Y VSUS VSUS VSUS VSUS 0 F VSUS G VSUS G V V 0 0 V V L V L V L V L V L V M V M V P V 0 P V T V T V U V U V U V U V U V F V V V V V V V G V G V 0 G V 0 V V V E V H V H V J V L V L V 0 M V P VSUS R VSUS U VSUS G V V V 0 V V E0 V E V E V E V E V F0 V G0 V G V P V VREF VREF VREF_SUS F VUSPLL VSUS 0 VRT VLN_/VSUS G0 VLN_/VSUS G V_PU_IO V_PU_IO V_PU_IO G VSUS VSUS VSUS E VSUS F VSUS F VSUS G VSUS G V U0 IH-M_ V U0 IH-M_ L LMS L LMS U/V U/V 0.U 0.U 0.0U_00 0.0U_00 0.U 0.U R0 R R0 R R * R * 0.U 0.U 0 0.U 0 0.U R R 0.U 0.U + 0U/V + 0U/V RV-0 RV-0 0.U 0.U 0.U 0.U 0.U 0.U 0.U 0.U 0U/0V/00 0U/0V/00 0.U 0.U 0.U 0.U 0.U 0.U 0.U 0.U 0.U 0.U 0 0.U 0 0.U 0U/0V/00 0U/0V/00

15 .VSUS.VSUS.VSUS.VSUS.VSUS 0.U 0.U 0.U 0.U N N VREF VREF.VSUS M VREF VREF M M M M0 Q0 Q M M0 Q0 Q M Q Q SM_QS0 V V 0 Q Q SM0 SM_QS0 V V 0 SM0 M QS0 M0 M M QS0 M0 M Q Q 0 M Q Q M M M 0.U 0.U M Q Q 0.U 0.U M M Q Q M Q Q 0 M V V Q Q 0 M M V V M.VSUS SM_QS Q Q SM SM_QS Q Q SM QS M M QS M M M M M0 Q0 Q 0 M M0 Q0 Q 0 M 0 Q Q LK_SRM0 V V Q Q LK_SRM LK_SRM0 0.U 0.U LK_SRM0# K0 V V V LK_SRM 0.U 0.U LK_SRM# LK_SRM0# K0 K0 V LK_SRM# 0 K0 0.VSUS M M0 M M0 M Q Q0 M M Q Q0 M Q Q SM_QS V V Q Q SM SM_QS V V SM M QS M M M QS M M 0 Q Q 0 M Q Q 0 M M M 0.U 0.U M Q Q 0.U 0.U M M Q Q M Q Q M V V Q Q M M V V M.VSUS SM_QS Q Q 0 SM SM_QS Q Q 0 SM QS M M QS M M0 M M0 M Q Q0 M M Q Q0 M 0 Q Q V V 0 Q Q V V 0 0.U 0.U 0 0.U 0.U 0 QS M QS M 0 SMR_VTERM V V 0 V V.VSUS.VSUS U U/RESET R 0 U U/RESET K 0 R 0 R 0 R 0 K V K 0 0.U 0.U 0.U 0.U KE V V K V KE0 KE V V KE KE KE0 KE KE0 M M U U/ M M M M U U/ M M M M 00 0 M M M M 00 M M M M M M M M 0 M M M M M M M M 0 M M M M M M M M 0 M M M M 0 0 M M0 M M 0 M M0 0 M M0 V V 0 M M M0 V V M M 0 0/P M SRS# M 0 M SRS# M MWE# 0 RS 0/P M SS# M MWE# M SS# SM_S0# WE S 0 0 RS SM_S# SM_S# WE S 0 SM_S# M M S0 S M M U() U S0 S M U() U M M M M Q Q M M Q Q M Q Q 0 SM_QS V V Q Q 0 SM SM_QS V V SM M QS M M M QS M M Q Q M Q Q M M M M0 Q Q 0 M M0 Q Q 0 M Q0 Q M V V Q0 Q M M V V M SM_QS Q Q SM SM_QS Q Q SM QS M M 0 QS M M M 0 M M Q Q M M Q Q M Q Q V V Q Q LK_SRM# V V LK_SRM# V K LK_SRM# LK_SRM# LK_SRM V K LK_SRM K 0 LK_SRM LK_SRM M K 0 M M M M Q Q M M Q Q M Q Q SM_QS V V Q Q SM SM_QS V V SM M0 QS M 0 M M0 QS M 0 M Q0 Q M Q0 Q M M M M Q Q M M Q Q M Q Q0 M0 V V 0 Q Q0 M M0 V V 0 M SM_QS Q Q SM SM_QS Q Q SM QS M M QS M M M M M Q Q M M Q Q M Q Q 0 SMT V V Q Q 0 SMT V V SMT +V SMK S S0 SMK S S0 SL S SMK SL S +V +V R *0K V(SP) S V(I) U 00 SMbus address 0 R *0K V(SP) S V(I) U 00 MP_R_SOIMM_H. MP_R_SOIMM_H. SMbus address 0.U LOK 0, 0.U LOK, SMR_VREF SOIMM0 P00 R SRM SO-IMM (00P) KE 0, SMR_VREF SMR_VREF KE, SOIMM P00 R SRM SO-IMM (00P) SMR_VREF 0 0.U 0.U 0.U 0.U 0.U.VSUS 0 0U/.V_ M M[0..] M 0 M M SRS# M SS# M MWE# M M[0..] M 0 M M SRS# M SS# M MWE# M[0..] SM_QS[0..] SM[0..] SM_S0# SM_S# SM_S# SM_S# KE0 KE KE KE 0.U 0.U 0.U 0.U 0.U 0.U 0.U 0.U 0.U 0.U 0U/.V_ 0.U 0.U 0.U 0.U 0.U M M[0..] M 0 M M SRS# M SS# M MWE# M M[0..] M 0 M M SRS# M SS# M MWE# M[0..] SM_QS[0..] SM[0..] SM_S0#, SM_S#, SM_S#, SM_S#, KE0, KE, KE, KE, 0.U 0.U 0.U 0.U 0.U PROJET : T Quanta omputer Inc. Size ocument Number Rev R IMM ate: Monday, ecember, 00 Sheet of 0.U 0.U 0.U 0.U

16 +V N PLK_MINI RF_LINK, RF_OFF# R0 R P +V 0EX R *0K 0,0, ITLK R *0K SS 0 INT# 0 REQ# 0,, 0,, 0,, R 0,, K 0,, /E# 0,, 0,, 0,, 0,, 0,, /E# 0,, IRY# 0,, LKRUN# 0,, SERR# 0,, PERR# 0,, /E# 0,, 0,, 0,, 0 0,, 0,, 0,, 0,, 0,, 0,0, SYN 0 SIN *P R SIN R +V 0K R0 0K +V R SIN TIP LN LN LN LN LE_GP LE_GN N -INT +V R(IRQ) GN PILK GN -REQ +V GN (V) -E GN GN -E -IRY +V -LKRUN -SERR GN -PERR -E GN 0 GN +V (V) +V GN SYN SIN0 ITLK -_PRIMRY EEP GN +MI -MI GN -RI +V GN RING LN LN LN LN 0 LE_YP LE_YN N +V -INT 0 R(IRQ) +VUX -RST +V -GNT 0 GN -PME (V) 0 +V 0 ISEL GN 0 0 PR 0 GN -FRME -TRY -STOP +V 0 -EVSEL GN 0 GN -E0 +V 0 0 (V) SERIRQ 00 GN 0 MEN 0 SOUT 0 SIN 0 -RESET 0 -MPIK GN +SPK -SPK GN 0 N +VUX GN MINIPI_TYPE_III +V MINI PI TYPE III SLOT +V INT# 0 LNV PIRST# 0,,, VSUS GNT# 0 MINIPI_PME# R0 K 0EX 0 0,, R 0,, R0 0,, 0K 0,, 0 MINIPI_PME# 0,, 0 0,, PR 0,, Q 0,, N00E 0,, FRME# 0,, TRY# 0,, STOP# 0,, EVSEL# 0,, 0,, 0,, 0,, 0,, /E0# 0,, 0,, +V 0,, 0,, 0 0,, R SERIRQ 0,,, *0K SOUT 0,0, -OE_RST 0,0, R K R 0K LNV PI_PME# 0,, LNV +V +V +V +V 0.U/00 0.U/00 0.U/00 0.U/00 0.U/ U/00 0.U/00 0.U/00 0.U/00 0.U/00 0.U/00 0.U/00 0.U/00 PROJET : T Quanta omputer Inc. Size ocument Number Rev ustom MINIPI_TYPE_III ate: Monday, ecember, 00 Sheet of

17 VJ_R LON VIN +V 0.U/00 0.U/00 N L_ON0 VJ_R R K +V L PY00T- EIT_ EILK_ LON LI LI LI0 VJ VIN LV TXLOUT0+ TXLOUT0- TXLOUT+ TXLOUT- TXLOUT+ TXLOUT- TXLLKOUT+ TXLLKOUT- +V Q TEU RF_LE#, dd a level-shift circuit for EI interface. Sting 0/0/00 EILK EIT 0U/V R0.K R0.K 0.U_00_V Q Q 0.U/00 N00E +V N00E EILK_ EIT_ VPU +V R Q SIV 0K R K LON KLON LI_E# SS R K ISP_ON R 0K G Q TEU S +V LV mil 0m 0U/0V/00 0.U SW LI FPK# Q TEU PROJET : T Quanta omputer Inc. Size ocument Number Rev ustom L ONN ate: Monday, ecember, 00 Sheet of

18 _INPK# OE# _0 STSHG_P _REG# _# _SPKR_P _WE# _0 # IOWR# _WIT# _VS# _IREQ# _IOR# VS# _0 _E# IOIS# 0 _0 _RESET _E# _ TPS_LOK TPS_LTH TPS_T _E# _IOWR# INPK# _E# IOIS# STSHG_P _0 _RESET _OE# _VS# 0 _# 0 VS# _0 REG# _IREQ# _WIT# _0 SPKR_P _# _IOR# _WE# _ TPS_LOK TPS_T TPS_LOK TPS_LTH PIGRST#, _V _V _V VSUS VSUS VSUS VSUS VSUS _V VPP VPP Size ocument Number Rev ate: Sheet of ustom Monday, ecember, 00 Size ocument Number Rev ate: Sheet of ustom Monday, ecember, 00 Size ocument Number Rev ate: Sheet of ustom Monday, ecember, 00 ardus onnector RUS SLOT ardus onnector RUS POWER SWITH For PI For PI0 PV stage: Remove unused PIVGF circuit. Griffey /0/00 _/ 0/_ E _/ / / /_ E _/_ F _/ RSV/ / /_ E _/E0/_E G _/_0 _0/_E _/_OE _/_IOR _/ /_IOWR E _/_ G _/_ 0 _/E/_ 0 _RSV/_ 0 _PR/_ G0 _LOK/_ E0 _PERR/_ F0 _STOP/_0 _GNT/_WE _EVSL/ LK/_ E _TRY/ IRY/ FRME/ /E/_ F _/ / / VS/_VS E _0/_ G _RST/_RESET _/ / REQ/_INPK E _/ /E/_REG _/_ E _/ /_0 _VS/_VS _INT/_REY(IREQ) _SERR/_WIT _UIO/_V(SPKR) _STSHG/_V(STSHG/RI) _LKRUN/_WP(IOIS) _/_ E _/_0 _/ / 0/ RSV/ /_0 V V U- PIGHK U- PIGHK V _/_0 _0/ / / /_0 _/_0 _/ / /_ E _/_ E _/_ G _0/_ F _/_ H _/_ H _/_ G _/_ K _/_IOWR L _/_ K _/_IOR L _/_ L _/_OE L _0/_E L _/_0 M _/_ M _/_ M _/_ N _/_ N _/_ N _/_ M _/_ P _/_ P _0/_ P _/E/_REG F _/E/_ G _/E/_ K _/E0/_E M _PR/_ K _FRME/_ G _TRY/_ H _IRY/_ J _STOP/_0 J _EVSL/_ H _LOK/_ J _PERR/_ J _SERR/_WIT _REQ/_INPK E _GNT/_WE J _STSHG/_V(STSHG/RI) F _LKRUN/_WP(IOIS) _LK/_ H _INT/_REY(IREQ) _RST/_RESET F _UIO/_V(SPKR) _/_ N _/ VS/_VS _VS/_VS F _RSV/_ N _RSV/ RSV/_ K V K U- PIGHK U- PIGHK 0.0U_00 0.0U_00 R *K R *K + 0 0U/0V/ U/0V/00 0.U_00_V 0.U_00_V R R R R V_0 V_ T LOK LTH N_0 VPP/VORE V0 V 0 GN RESET# V_0.VIN.VIN0 O# N_ V0 V VPP/VORE V_ 0 SHN# N_ N_ V_ N U TPS/0 (PWR) U TPS/0 (PWR) SKT0/ SKT/ SKT/ SKT/ SKT/ SKT/ SKT/ SKT/ SKT/ SKT/0 SKT0/E# SKT/OE# SKT/ 0 SKT/IOR# SKT/ SKT/IOWR# SKT/ SKT/ SKT/ SKT/ SKT0/ SKT/ SKT/ SKT/ SKT/ SKT/ SKT/0 SKT/0 0 SKT/ SKT/ SKT0/ SKT/0 -SKTE0/E# -SKTE/ -SKTE/ -SKTE/REG# SKTPLK/ -SKTFRME/ -SKTIRY/ 0 -SKTTRY/ -SKTEVSEL/ 0 -SKTSTOP/0 SKTPR/ -SKTPERR/ 0SKTSERR/WIT# -SKTREQ/INPK# 0 -SKTGNT/WE# -SKTINT/RY -SKTLOK/ -SKTLKRUN/WP -SKTRST/RESET SKTRSV/ 0 -SKTRSV/ -SKTVS/VS# -SKTVSVS# -SKT/# -SKT/# -SKTSTSHG/V SKTRSV/ SKTUIO/V SKT/V SKT/V SKT/VPP SKT/VPP GN GN GN GN GN GN 0 GN GN GN GN0 GN GN GN GN GN GN 0 GN GN GN GN0 GN GN GN GN N FOX=WZ-G N FOX=WZ-G 0.0U_00 0.0U_ U_ U_00.U/0V.U/0V Quanta omputer Inc. PROJET : T Quanta omputer Inc. PROJET : T 0U/0V/00 0U/0V/00 0.U_00_V 0.U_00_V 0.U_00_V 0.U_00_V 000P 000P.U/0V.U/0V

19 ardus 0,, [0..] 0,, /E# 0,, /E# 0,, /E# 0,, /E0# 0,, PR 0,, FRME# 0,, TRY# 0,, IRY# 0,, STOP# 0,, EVSEL# 0,, PERR# 0,, SERR# 0 REQ0# 0 GNT0# PLK_ 0,,, PIRST#, PIGRST# RI# R PLK PME# R0 VSUS W W0 U V V U W V U V V U R P W V U R V U R N V0 U0 R0 N0 V U R W V U N W W W W W P V R U W N W V U U T P R T T U- VP VP /E /E /E /E0 PR FRME TRY IRY STOP EVSEL ISEL PERR SERR REQ GNT PLK PRST GRST RI_OUT/PME PIGHK SUSPEN T LOK LTH SPKROUT MFUN0 MFUN MFUN MFUN MFUN MFUN MFUN LK_ R N L N L N M P P P N R M VSUS R0 0K TPS_T TPS_LOK TPS_LTH GN Remove reserve resistor R~R for PIVGF Sting 0//00 MHz lock Y LKM OUT V OE *SG-00 M L *FM0K PMSPK 0 INTE# 0 INTF# 0 INTG# 0 SERIRQ 0,,, PLOK# 0 R_LE, LKRUN# 0,, LKM Remove all componet of PLL circuit and dd LKM input from KG. Sting 0//0 TPS_T TPS_LOK TPS_LTH VSUS VSUS VSUS 0.00U_00 0.0U_00 0.U R0 * 0.U SL S VSUS U SL S PIXX Power Terminals VSUS VSUS PV stage: Remove R0 & R0 for unused PIVGF circuit. When -V0 and -V asserted high, PLOK# and INTF# will provide a S Griffey /0/00 signaling for I bus, PLOK# will provide a SL signaling for I bus. PV stage: Remove reserve relatived circuit for PIVGF. +V L0 *FM0K 0 *0.0U_00 *0.0U_ U_00 0.0U_00 0.U U- PIGHK Griffey /0/00 0.U SL S 0.U M M 0.U V 0 N SL S GN L0 VSUS U- H V H V H0 V H V H V J V M V J V M V M0 V M V K V K V N V G G G H J J0 J K K0 K L L L0 L L M GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN PIGHK.V.V VR_EN M H H R R.K R.K 0.U 0.U VR_EN# :0 Internal voltage regulator enable for./.v core power. U- 0,, PI_PME# VSUS TEU Q0 R0 0K _PME# W T N TEST0 P VO_LF PIGHK U-0 _US_EN E _US_EN E PIGHK R0 *0K R0 *0K VSUS EMI PLK_ R *R 0 *P LKM R0 R 0 P PV stage: Pouplate R0 and 0 for getting better EMI performance. Sting //00 PROJET : T Quanta omputer Inc. ardus Size ocument Number Rev ustom ate: Monday, ecember, 00 Sheet of

20 M_PWR_TRL_0# U- F M_PWR_TRL_0 F M_PWR_TRL_ S_ MS_ SM_ E F F S_Z MS_Z SM_Z PV stage: Remove reserve relatived circuit for PIVGF. Griffey /0/00 L U- S_PWR_TRL S_ R POWER ONTROL L Reserve for smart card which is powered by V. MS_LK/S_LK/SM_EL_WP G MS_S/S_M/SM_WE F MS_T/S_T/SM_ H MS_T/S_T/SM_ G MS_T/S_T/SM_ G MS_SIO(T0)/S_T0/SM_0 G S_LK/SM_RE/S_GPIO J S_M/SM_LE/S_GPIO J S_T0/SM_/S_GPIO H S_T/SM_/S_GPIO J S_T/SM_/S_GPIO J S_T/SM_/S_GPIO J S_WP/SM_E H SM_LE/S_GPIO0 J SM_R//S_RFU K SM_PHYS_WP/S_F K MS_LK_S_LK_SM_ELWPZ_R R MS_S_S_M_SM_WEZ MS_T_S_T_SM_ MS_T_S_T_SM_ MS_T_S_T_SM_ MS_T0_S_T0_SM_0 SM_REZ SM_LE SM_ SM_ SM_ SM_ S_WP_SM_EZ SM_LE SM_RZ R MS_LK_S_LK_SM_ELWPZ Remove reserve resistor R fro PIVGF. Sting 0//00 PIGHK S_LK S_RST S_V_V S_T S_O K K K L L VSUS R R R *0K VSUS 0K VSUS VSUS M_PWR_TRL_0# V_X PV stage: R dd a discharge circuit for media R card power. Sting //00 Q N00E PIGHK PV stage:. isconnect SM_PHYS_WP.. Tie SM_EL_WP with SM_PHYS_WP of SM card to allow for normal operation of S and SM. M_PWR_TRL_0#.K Q O0 Sting //00 V_X MS_LK_S_LK_SM_ELWPZ R0.K V_X R K SM_X_WP X_WP# U GN NSZPX V OE U 0 SM_Z VSUS Griffey /0/00 PV stage:. dd quick switch circuit., R_LE S_Z *SS 0 SM_Z Q *N00E VSUS R *00K R0 00K 0U/0V/00 LOSE TO X SOKET SM_X_WP R * X_WP# *SS V_X V_X SM_Z S_WP_SM_EZ X-S-MS- X-S-MS-0 MS_LK_S_LK_SM_ELWPZ MS_S_S_M_SM_WEZ X-S-MS- X-S-MS- MS_S_S_M_SM_WEZ X-S-MS- X-S-MS-0 X-S-MS- MS_Z X-S-MS- MS_LK_S_LK_SM_ELWPZ SM_ SM_ R R R R S-LK MS-LK X- X- 0 0 N IN_GN SM--OM SM--SW N S-WP-SW S-T S-T0 S-LK S-V S-M S-T S-T MS-S MS-T MS-T0 MS-T MS-INS MS-T MS-LK MS-V SM/X- SM/X- TITWUN-R00-00-N-P SM/X- SM/X- SM-LV #SM/X-R/ #SM/X-RE #SM/X-E SM-V #SM- 0 SM/X- SM/X- SM/X- SM-0 SM/X-WP-IN #SM/X-WE #SM/X-LE ##SM/X-LE X- X-V 0 S--OM S--SW SM-WP-SW IN_GN IN_GN IN_GN X- X- X-S-MS- X-S-MS- X-S-MS- X-S-MS-0 R R R R R0 R0 R R * K SM_ SM_ SM_RZ SM_REZ S_WP_SM_EZ SM_Z MS_T_S_T_SM_ MS_T_S_T_SM_ MS_T_S_T_SM_ MS_T0_S_T0_SM_0 X_WP# MS_S_S_M_SM_WEZ SM_LE SM_LE SM_Z S_WP_SM_EZ X_V V_X S_Z X_WP# SM_Z VSUS R.K V_X VSUS R R * Q O0 X_V 00 U PV stage:. dd pull-up circuit. Griffey /0/00 IN R REER PV stage:. dd R to solve SM card can't write protect issue.. dd R to solve cross-talk issue of MS-PRO card.. dd R~R as terminal on all multi-funtion pin. Sting //00 V_X MS_S_S_M_SM_WEZ R 0K SM_REZ S_WP_SM_EZ SM_RZ R R R 0K 0K K PROJET : T Quanta omputer Inc. Size ocument Number Rev R REER ONN Monday, ecember, 00 ate: Sheet of

21 U- IEEE a V V V V VPLL R0 R TPIS0 TP0+ TP0- TP0+ TP0- PHY_TEST_M R R V V T U U U V W V W R R0 R VSUS R.K FM0 _V TPIS0 TP0P TP0N 0.U L TP0P TP0N R.K PHY_TEST_M 0.0U_00 0.U 0.00U_00 0.U/00 IEEE ONNETOR TPIS0 R./F R./F TP0_F R./F TP0P TP0N TP0P TP0N R./F *0P U/V R R ML *MM-S L_TP0+ L_TP0- L_TP0+ L_TP0- ML *MM-S R R N _ONN PIGHK PS N XO XI P0 (TEST) P (TEST) P (TEST) VSPLL GN GN GN GN TPIS TP+ TP- TP+ TP- M PS P N R _XOUT R _XIN R U V T N P U U U V W V W R 0K R0 0K 0 P Y.MHZ P TPIS _TP+ _TP- R R./F./F _TP+ _TP- _TP+ _TP- losed Phy I TPIS R0.K/F 0 0P losed Phy I VSUS U IN OUT R ON# SET R GN.K 0.U/00 T0 R USP0- USP0+ L *MMT-00M-S R0 hange R and R value from R to cause of OM error in -test. Sting 0//00 0P 00U/0V ES USPWR0 USP0- USP0+ US 0P _TP+ _TP- U/V VSUS 0 0.U/00 U IN OUT ON# SET GN T0 0 0P USP- USP+ N GN GN GN GN Suyin_000MR00S00ZU TP_F R.K/F R./F R./F *0P R R0.K *lamp-iode 0 *lamp-iode 00U/0V R L R *MMT-00M-S ES USPWR USP- USP+ N GN GN GN GN Suyin_000MR00S00ZU US 0 *lamp-iode *lamp-iode PROJET : T Quanta omputer Inc. Size ocument Number Rev ustom IEEE, USX ate: Monday, ecember, 00 Sheet of

22 The M0-00 modem is used for mother board family MM0-00. VSUS M M 0.U 0.U_00_V I_TN I_TP M 0.U M 0.U MR M K 0U_0_0V R_OS MU ROS V I_TN I_TP V V 0 V_LK V V MV SPKOUT P_EEP LINE_IN_L 00m M 0U/0V/00 M 0.U P_EEP MV M 000P M0 0.U M0 0U/0V/00 GN P_EEP LINEINL_PR M M.U/0V 0.U_00_V PWRLKP PWRLKN PWRLKP PWRLKN I0# I# LINE_IN_R LINE_OUT_L LINE_OUT_R 0 MPL MPR LINEINR_PR MPL, MPR,, MUTE_LE 0,, -OE_RST 0,, SYN 0,, SOUT 0,, ITLK 0, SIN ITLK SIN MR MR MR R R R 0 PRIMRY_N _RESET# SYN ST_OUT ITLK ST_IN0 ST_IN SmartM HP_OUT_L HP_OUT_R MI_IN _IN_L _IN_R _IN_GN SPIF 0 MI_ UL UR GN M LINEOUTL_PR LINEOUTR_PR 0U/0V/00 SPIF, MI_IS MR *K MR MI MI,, OK_OK MR M0 R MR0 *M MY.MHZ M K K GPIO_ GPIO_ XTLO XTLI GN GN GN GN _LK GN GN REF_FLT V_S VREF_S MIS/V X0- MI_IS M 0.U M 0.U_00_V M U/V M 0.U_00_V P P GN GN MR0 0K SIN MR GN FROM -ROM P SPEKER UL UL 0 U/V INL INL UR UR 0 U/V INR INR +V GN GN 0 U/V GN GN R 0K R 0K R 0K 0.U_00_V GN GN GN PMSPK SPK R0 0K PEEP U TSHFU R K PEEP 0 000P R0.K 0.U P_EEP MI_IS MI_IS GN PROJET : T Quanta omputer Inc. Size ocument Number Rev M OE ate: Monday, ecember, 00 Sheet 0 of