Centrino DOTHAN CELEROM-M. Page : 3, 4 PCIE. HOST BUS 533MHz HOST BUS 400MHz ALVISO 1257 BGA LVDS RGB TVOUT. Page : 5 ~ 8 DMI I/F PCIE ICH6-M 609 BGA

Size: px
Start display at page:

Download "Centrino DOTHAN CELEROM-M. Page : 3, 4 PCIE. HOST BUS 533MHz HOST BUS 400MHz ALVISO 1257 BGA LVDS RGB TVOUT. Page : 5 ~ 8 DMI I/F PCIE ICH6-M 609 BGA"

Transcription

1 V /.V / V Page :.V /.V Page :.V /.V /.V Page : PU ORE Page :.V Page : TTERY HRGER Page : TTERY SELET Page : VPU V_LWYS V V V_S VSUS VSUS.VSUS.V.V MVREF_M SMR_VTERM.V_S.V GP_V (.V).VT VTT V_ORE VG_ORE.V_VG LOK GEN IS IS Page : R-SOIMM Page:~ IE - H Page: IE-O Page: MEI Y Page: UIO OE ONEXNT - Page: MP MX Page: MOEM ONEXNT - Page: /MHZ R /MHZ R R-SOIMM Page:~ ST - H Page: T / ST INTEL Mobile_ PU entrino OTHN ELEROM-M LVISO G Page : ~ MI I/F IH-M G Page : ~ LP NS K() Page : Page :, HOST US MHz HOST US MHz PIE PI US US. RNE ( ZL ) PIE LVS RG TVOUT NS SIO () Page : TI MP/MP M / M Page : ~ VI H Page: NEW R Page : EXT_LVS EXT_RT EXT_TV-OUT INT_LVS INT_RT INT_TV-OUT E@ INT. VG WITH OK I@ INT. VG WITH OK N@ W/O OKING 要打 SWITH IRUIT TI PMI IN PI Page: MINI-PI Wireless LN Modem/LN Page : ROOM //G LN / M Page: OM MRK E@ EXT VG 要打 I@ INTVG 要打 S@ ST 要打 F@ FIXE O 要打 SW@ SWPPLE O in 要打 N@ NEW R M OKING 要打 RT Page: LVS Page: TV-OUT Page: OKING/VI Page: IN Page: PMI Page: Page: OTHHN RJ TRNSFORMER Page: Page: MI IN Page: LINE IN Page: SPEKER Page: LINE OUT Page: RJ OKING PS Touchpad Keyboard Ir Page: Page: Page: Page: Page: PI ROUTING TLE ISEL INTERUPT OKING Print Port Page: EVIE OKING OM Port Page: SYSTEM US PORT Page : US,, OKING US PORT Page : US, MINI-US Page: US REV. REQ# / GNT# REQ# / GNT# REQ# / GNT# INT# INT#, INT# INT#,INT#,INT# ROOM LN MINI-PI TI PROJET : ZL Quanta omputer Inc. Size ocument Number Rev LOK IGRM ate: Tuesday, March, Sheet of

2 V V SELPS_LK V_KG_PU VP VP V L R *_ L L- L- U/V_ R K_ R R. R K_ SELPS_LK R *_.U_ SELPS_LK V_KGREF LKV.U_.U_ R K_.U_ <> LK_US <,> SELPS_LK <,> SELPS_LK.U_.U_.U_ <> OT <> OT# <> LK_EN# <> STP_PI# <,> STP_PU# G_XIN G_XOUT SMK SMT R _ SELPS_LK SELPS_LK SELPS_LK Iref=m, Ioh=*Iref Y.MHZ/PF V_KG_PU V_KG_ R /F_ LK_EN# SMbus address IREF R_OT R_OT# SMUS RESS:, V_KG.U_ IS m ( MX. ) M_REF R_HLK_PU R_HLK_PU# R_HLK_MH R_HLK_MH# R_MH_GPLL R_MH_GPLL# R_PIE_VG R_PIE_VG# R_PIE_ST R_PIE_ST# R_PIE_EZ R_PIE_EZ# R_PIE_IH R_PIE_IH# R_PIE_EZ R_PIE_EZ# R_PIE_NEW R_PIE_NEW# R_PLK_ R_PLK_PM R_PLK_LN R_PLK_SIO R_PLK_MINI R_PLK_IH Place these termination to close KM. R./F_ R./F_ R./F_ R./F_ R./F_ R./F_ R RP PR-S- RP PR-S- RP PR-S- RP E@PR-S- RP S@PR-S- RP PR-S- RP N@PR-S- R _ R _ R _ R _ R _ R _ K_ HLK_PU <> HLK_PU# <> HLK_MH <> HLK_MH# <> LK_MH_GPLL <> LK_MH_GPLL# <> NEW_LKREQ# <> EZ_LKREQ# <> LK_PIE_VG <> LK_PIE_VG# <> LK_PIE_ST <> LK_PIE_ST# <> LK_PIE_EZ <> LK_PIE_EZ# <> LK_PIE_IH <> LK_PIE_IH# <> LK_PIE_EZ <> LK_PIE_EZ# <> LK_PIE_NEW <> LK_PIE_NEW# <> PLK_ <> PLK_PM <> PLK_LN <> PLK_SIO <> PLK_MINI <> PLK_IH <> efine pin, function PULL HIGH TO SET PIN, TO HOST LK LK_SS_IN M_SIO EZ_LKREQ# NEW_LKREQ# M_SIO M_SIO <> M_IH <> PEREQ# - SR,, ST PEREQ# - SR,, EFLT OFF EFLT OFF V V *K_ *K_ R R V SS_V SMUS RESS:, LK_SS_IN SMK SMT SS_S SS_S SS_S LK_EN# R *K_ U LKIN S S S V V LKOUT LKOUT# SLK IREF ST IREF PWRWN REFOUT/SEL *MK-GT SS_V *.U_ R_REFSSLK R_REFSSLK# RP R */F_ *PR-S- V REFSSLK <> REFSSLK# <> OT OT# LK_PIE_VG LK_PIE_VG# LK_PIE_ST LK_PIE_ST# LK_PIE_EZ LK_PIE_EZ# LK_PIE_IH LK_PIE_IH# LK_PIE_EZ LK_PIE_EZ# LK_PIE_NEW LK_PIE_NEW# R N@./F_ R N@./F_ SMT <,,,> PT_SM SMT <> Q N V U/V_ U/V_ R *K_.U_ P_ P_ I@PR-S- RP R. XTL_IN XTL_OUT VTT_PWRG#/P PI/SR_STOP# PU_STOP# SLK ST FS/US_ FS/TEST_MOE FS/TEST_SEL V_REF V_PI_ V_PI_ V_PU V_SR V_SR V_SR U V_ IREF GN_ GN_REF GN_PI_ GN_PI_ GN_SR GN_PU V K-M REF PU PU# PU PU# PU_ITP/SR PU#_ITP/SR# *PERREQ# *PERREQ# SR SR# STLK STLK# SR SR# SR SR# SR SR# SR SR# PI *Internal Pull-own Resistor PI PI OT PI OT# PIF PIF/ITP_EN U/V_ R *_ R _ R _ R *K_ P_ R K_ *K_ R *U/V_ L *L- R *./F_ R *./F_ R I@./F_ R I@./F_ R E@./F_ R E@./F_ R S@./F_ R S@./F_ R./F_ R./F_ RP PR-S-K SMK <,,,> PLK_SM SMK <> Q N OTHN- OTHN- FS FS FS PU SR PI RSV Place these termination to close KM. QUNT OMPUTER LOK GENERTOR Size ocument Number Rev ZL ate: Tuesday, March, Sheet of

3 V V VP R _ TI G: N for othan and PRSTP# for Yonah <,> THERMTRIP# VP <> H#[..] <> HST# <> HST# <> HREQ# <> HREQ# <> HREQ# <> HREQ# <> HREQ# <> S# <> HREQ# <> PRI# <> NR# <> HLOK# <> HIT# <> HITM# <> EFER# <> HTRY# <> RS# <> RS# <> RS# <> M# <> FERR# <> IGNNE# <> PUPWRG <> SMI# T T <> R# <> INTR <> NMI <> STPLK# <,> PUSLP# <> PSLP# <> PRSLP# R R _ *_ H#[..] M# FERR# IGNNE# PUPWRG SMI# STPLK# PUSLP# PSLP# THERM THERM H# P H# U H# V H# R H# V H# W H# T H# W H# Y H# Y H# U H# H# Y H# H# F H# H# H# H# H# E H# H# H# H# H# E H# H# F H# E H# F IERR# PM# PM# PM# PM# TK TO TI TMS TRST# PREQ# PRY# R# THERMTRIP#_PWR PU_PROHOT# U E R P T P T N N J L J K K L M H K L E G U # # # # # # # # # # # # # # # # # # # # # # REQUEST # PHSE # SIGNLS # # # # # ST# ST# REQ# REQ# REQ# REQ# REQ# ERROR S# SIGNLS IERR# REQ# RITRTION PRI# PHSE NR# SIGNLS LOK# HIT# SNOOP PHSE HITM# SIGNLS EFER# PM# RESPONSE PM# PHSE PM# SIGNLS PM# TRY# RS# RS# RS# M# P FERR# OMPTIILITY IGNNE# SIGNLS PWRGOO SMI# TK IGNOSTI TO & TEST TI SIGNLS TMS TRST# ITP_LK ITP_LK PREQ# PRY# R# LINT EXEUTION LINT ONTROL STPLK# SIGNLS SLP# PSLP# PRSTP# THERM THERM THERMTRIP# THERML IOE PROHOT# othan Processor othan OF T PHSE SIGNLS # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # STN# STP# STN# STP# STN# STP# STN# STP# INV# INV# INV# INV# SY# RY# LK LK INIT# RESET# PWR# E E H G L M H F G J M J L N M H N K Y T U V R R R U V U V Y Y E F F E F F F K L W W E E J T M H H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# PUINIT# PURST# H#[..] HSTN# <> HSTP# <> HSTN# <> HSTP# <> HSTN# <> HSTP# <> HSTN# <> HSTP# <> HI# <> HI# <> HI# <> HI# <> SY# <> RY# <> HLK_PU# <> HLK_PU <> V THERM THERM PUINIT# <> PURST# <> PWR# <> H#[..] <> R mil trace / mil space MIL THERMTRIP#_PWR TI TMS TO TRST# PURST# TK TK TRST# IERR# PUPWRG V_THM.U_ P VP PU junction temp up to degree output signal. shut down system TK NO STU R./F_ VP close to ITP conn close to PU R _ R _ U KSMT V SMT KSMLK XN SMLK XP -LT -OVT GN R R./F_ R _ MX VP R _ R /F_ R *./F_ R VP Q VP R _ *./F_ *./F_ MMT V V V V _SHT# <> JITP ONN MT QUNT OMPUTER othan Processor (HOST) MLK VP PM# PM# PM# PM# PRY# PREQ# MT <,,> Level shift MX_L# <> R# MLK <,,> MX_OV# EPOP R, R, R, WHEN NO JITP R./F_ T T T T T T R K_ R *K_ R K_ T T T T T T T T Q N R K_ Q N V_S R _ Size ocument Number Rev ZL *.U_ ate: Tuesday, March, Sheet of

4 OMP OMP OMP OMP TEST TEST GTLREF OMP OMP OMP OMP PU_V PU_V SELPS_LK SELPS_LK SEL SEL Z Z PU_VI <> PU_VI <> PU_VI <> PU_VI <> PU_VI <> PU_VI <> SELPS_LK <,> SELPS_LK <,> VP VP V_ORE V_ORE V_ORE VP V_ORE V_ORE V_ORE V_ORE.V VP V_ORE Size ocument Number Rev ate: Sheet of QUNT OMPUTER ZL othan Processor (POWER) Wednesday, March, Size ocument Number Rev ate: Sheet of QUNT OMPUTER ZL othan Processor (POWER) Wednesday, March, Size ocument Number Rev ate: Sheet of QUNT OMPUTER ZL othan Processor (POWER) Wednesday, March, ESR = m ohm/ // m ohm/ // m ohm/ Total caps = uf Place pulldown resistors within." of OMP pins Place voltage divider within." of GTLREF pin OTHN- N OTHN- POP el. R cancel reserve.v us speed select U_.V U_.V U_.V U_.V U_.V U_.V R./F_ R./F_.U_.U_.U_.U_.U_.U_ T T.U_.U_.U_.U_ U_.V U_.V T T T T U_.V U_.V U_.V U_.V U_.V U_.V U_.V U_.V.U_.U_ U_.V U_.V U_.V U_.V U_.V U_.V U_.V U_.V U_.V U_.V U_.V U_.V.U/V_.U/V_ U_.V U_.V V V V V V V V W V J V E V E V V V V V V Y V K V V E V V V V V V W V J V V F V V F V V F V E V F V E V E V E V F V E V E V F V F V F V F V F V G V F V E V V V V V V V V H V V V V V V Y V U V E V V V V V V V V H V G V E V F V V N V OMP P OMP P OMP OMP GTLREF TEST TEST F E E E E E E E E E E E F F F F F F F F F F F F G G G G G H H H H J J J J J K K K K K L L L L M M M M M N N N N N P P P P R R N RSV RSV F RSV RSV E OF POWER, GROUN, RESERVE SIGNLS othan U othan Processor OF POWER, GROUN, RESERVE SIGNLS othan U othan Processor T T R./F_ R./F_ R./F_ R./F_ U_.V U_.V T T U_.V U_.V U_.V U_.V T T U/V <Type> U/V <Type> U_.V U_.V.U_.U_ U_.V U_.V R./F_ R./F_ T T U_.V U_.V U_.V U_.V R *K_ R *K_ T T U_.V U_.V T T R _ R _.U_.U_.U_.U_ VI E VI F VI F VI G VI G VSENSE E VP VP VP VP VP E VP E VP E VP F VP F VP F VP F VP K VP L VP L VP M VP M VP N VP N VP P VP P VP R VP R VP T VP T VP U VQ P VQ W VI H SEL SEL PSI E W W Y Y Y Y E E E E E E E E E E E F F F F F F F F F F W W W V V V V V U U U U T T T T T R R R SENSE F OF POWER, GROUN N N VI othan U othan Processor OF POWER, GROUN N N VI othan U othan Processor.U_.U_ U_.V U_.V R *K_ R *K_ U_.V U_.V U_.V U_.V U_.V U_.V U_.V U_.V R K/F_ R K/F_ U_.V U_.V R _ R _ U_.V U_.V U_.V U_.V U_.V U_.V U_.V U_.V R _ R _ R K/F R K/F U_.V U_.V U_.V U_.V U_.V U_.V

5 H# H# H# H# H# H# H# H# H# H#[..] H# H# H# H# HPUSLP#_GMH H# H# H# H# HXSOMP H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# HXROMP HXSOMP HYSWING HYSWING HYROMP H# H# H# H# H# H# HVREF H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# H# HYSOMP H# H# H# H# H# HXROMP H# H# H# H# H# H# H# H# H# H# H# HYROMP H# H# H# H# H# H# H# H# HYSOMP H# H# H# H# H# H# H# H# H# HXSWING H# H# H#[..] HXSWING HLOK# <> EFER# <> HREQ# <> HSTP# <> HIT# <> HI# <> HI# <> RS# <> HSTP# <> HREQ# <> HREQ# <> HSTN# <> PUSLP# <,> HI# <> HREQ# <> HREQ# <> RS# <> H#[..] <> HST# <> PRI# <> PWR# <> HSTN# <> H#[..] <> S# <> HSTP# <> RS# <> NR# <> SY# <> HLK_MH# <> HSTP# <> HTRY# <> HREQ# <> HSTN# <> HST# <> PURST# <> HI# <> HITM# <> RY# <> HLK_MH <> HSTN# <> VP VP VP VP VP Size ocument Number Rev ate: Sheet of QUNT OMPUTER ZL lviso (Host) Tuesday, March, Size ocument Number Rev ate: Sheet of QUNT OMPUTER ZL lviso (Host) Tuesday, March, Size ocument Number Rev ate: Sheet of QUNT OMPUTER ZL lviso (Host) Tuesday, March, O NOT INSTLL FOR OTHN- N INSTLL FOR OTHN- T *P T *P R./F_ R./F_ R./F_ R./F_ R /F_ R /F_ R /F_ R /F_ R _ R _ T *P T *P R /F_ R /F_ R /F_ R /F_ H# E H# E H# F H# H H# E H# F H# E H# H# K H# F H# J H# J H# H H# F H# K H# H H# H H# H H# K H# K H# J H# G H# H H# J H# L H# K H# J H# P H# L H# J H# P H# L H# U H# V H# R H# R H# P H# T H# R H# R H# U H# R H# T H# T H# R H# T H# V H# U H# W H# U H# V H# W H# W H# U H# U H# Y H# Y H# V H# Y H# W H# W H# Y H# Y H# W HTRY# H# G H# H# E H# H# H# F H# H# H# E H# G H# H# E H# F H# G H# G H# H# H# H# H# H# H# F H# G H# E H# H# H# H# H# F HS# F HPREQ# HREQ# HREQ# HREQ# HREQ# HPRI# HNR# HLOK# HHIT# HHITM# HEFER# E HSY# HRY# F HPWR# G HRS# HRS# HRS# HPURST# H HLKINN HLKINP REQ# E HINV# H HINV# K HINV# T HINV# U HST# HST# E HSTN# G HSTN# K HSTN# R HSTP# W HSTP# G HSTP# K HSTP# R HSTN# V HYROMP T HXSWING HVREF J HXSOMP HXROMP HERY# F HREQ# HPUSLP# G HYSOMP L HYSWING P HOST HOST R /F_ R /F_ R./F_ R./F_ R /F_ R /F_ G Y V T P M K H E N L J F E E Y W V U T R P N M L K J H G F E N H L F W V U T R P N M L K J H G F E N J Y L G W V U T R P N M L K J H G F E P E Y M J G W V U P L H G F E W E N L J G F W G E J G J F F H L H J E N F F K V G F E N G W T J H L U N J F G L K H K N L J G K J F J N L J G F Y H F Y L N H E V T K H L Y P L E N K G V G J E T P L J P L W E N F Y U P L H J N L H E V T P L J G E N L J G Y LVS R./F_ R./F_.U_.U_

6 PM_EXTTS# PM_EXTTS# PM_EXTTS# PM_EXTTS# SM_S# SM_S# SM_S# SM_S# KE KE KE KE LK_SRM# LK_SRM LK_SRM# LK_SRM M_OOMP M_OOMP SMXSLEW SMYSLEW FG FG FG FG M_ROMPN FG FG FG M_ROMPP FG FG FG FG FG FG FG FG INT_LON INT_ISP_ON TV_REFSET REFSET FG FG FG FG REFSSLK# REFSSLK INT_TV_OMP INT_TV_Y/G INT_TV_/R GMHEXP_TXN[..] GMHEXP_RXN[..] GMHEXP_RXP[..] GMHEXP_TXP[..] INT_TXUOUT- INT_TXUOUT INT_TXUOUT INT_TXUOUT INT_TXUOUT- INT_TXUOUT- INT_TXLOUT INT_TXLOUT INT_TXLOUT- INT_TXLOUT- INT_ISP_ON INT_LON TXUOUT TXUOUT- TXLOUT- TXUOUT ISP_ON TXUOUT TXUOUT- TXLOUT TXLOUT- LON TXLOUT TXUOUT- TP_N TP_N TP_N TP_N TP_N TP_N TP_N TP_N TP_N INT_TXLOUT- INT_TXLOUT TXLOUT TXLOUT- INT_TXULKOUT INT_TXULKOUT- INT_TXLLKOUT INT_TXLLKOUT- TXLLKOUT- TXLLKOUT TXULKOUT- TXULKOUT INT_TXLOUT- INT_TXLOUT INT_TXULKOUT INT_TXLLKOUT INT_TXLLKOUT- INT_TXUOUT- INT_TXUOUT INT_TXUOUT INT_TXUOUT- INT_TXLOUT INT_TXLOUT INT_TXLOUT- INT_TXLOUT- INT_TXUOUT INT_TXUOUT- SVO_R SVO_R- SVO_G SVO_G- SVO_ SVO_- SVO_LK SVO_LK- GMHEXP_TXP GMHEXP_TXN GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN INT_TXULKOUT- FG GMHEXP_RXN GMHEXP_RXN GMHEXP_RXN GMHEXP_RXN GMHEXP_RXN GMHEXP_RXN GMHEXP_RXN GMHEXP_RXN GMHEXP_RXN GMHEXP_RXN GMHEXP_RXN GMHEXP_RXN GMHEXP_RXN GMHEXP_RXN GMHEXP_RXN GMHEXP_RXN GMHEXP_RXP GMHEXP_RXP GMHEXP_RXP GMHEXP_RXP GMHEXP_RXP GMHEXP_RXP GMHEXP_RXP GMHEXP_RXP GMHEXP_RXP GMHEXP_RXP GMHEXP_RXP GMHEXP_RXP GMHEXP_RXP GMHEXP_RXP GMHEXP_RXP GMHEXP_RXP GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXN GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP GMHEXP_TXP M_ROMPP M_ROMPN OT OT# INT_VG_RE INT_VG_LU INT_VG_GRN INT_TV_Y/G INT_TV_/R INT_TV_OMP MI_TXN <> MI_TXN <> MI_TXP <> MI_TXP <> SM_S# <,> SM_S# <,> SM_S# <,> SM_S# <,> KE <,> KE <,> KE <,> KE <,> LK_SRM# <> LK_SRM <> LK_SRM# <> LK_SRM <> LK_SRM# <> LK_SRM <> LK_SRM# <> LK_SRM <> LK_MH_GPLL# <> LK_MH_GPLL <> MI_RXN <> MI_RXN <> MI_RXP <> MI_RXP <> MI_TXN <> MI_TXN <> MI_TXP <> MI_TXP <> MI_RXN <> MI_RXN <> MI_RXP <> MI_RXP <> SELPS_LK <,> PLTRST# <,,,,,,,> THERMTRIP# <,> PM_MUSY# <> IMVP_PWRG <,> SVO_TRLT <> SVO_TRLLK <> INT_VG_RE <> INT_VG_GRN <> INT_VG_LU <> INT_HSYN <> INT_VSYN <> INT_LK <> INT_T <> SELPS_LK <,> GMHEXP_RXP[..] <,> GMHEXP_RXN[..] <,> GMHEXP_TXP[..] <> GMHEXP_TXN[..] <> INT_TV_/R <> INT_TV_OMP <> INT_TV_Y/G <> SVO_R <> SVO_R- <> SVO_G <> SVO_G- <> SVO_ <> SVO_- <> SVO_LK <> SVO_LK- <> ISP_ON <,> LON <,> TXLLKOUT- <,> TXLLKOUT <,> TXULKOUT- <,> TXULKOUT <,> TXLOUT- <,> TXLOUT <,> TXLOUT- <,> TXLOUT <,> TXLOUT- <,> TXLOUT <,> TXUOUT- <,> TXUOUT <,> TXUOUT- <,> TXUOUT <,> TXUOUT- <,> TXUOUT <,> I_EILK <> I_EIT <> OT <> OT# <> M_OT <,> M_OT <,> M_OT <,> M_OT <,> REFSSLK# <> REFSSLK <>.V.VSUS VG_PIE VP.VSUS Size ocument Number Rev ate: Sheet of QUNT OMPUTER ZL lviso (VG,MI) ustom Tuesday, March, Size ocument Number Rev ate: Sheet of QUNT OMPUTER ZL lviso (VG,MI) ustom Tuesday, March, Size ocument Number Rev ate: Sheet of QUNT OMPUTER ZL lviso (VG,MI) ustom Tuesday, March, Route as short as possible. FG Low=MIx High=MIx It's point to point, ohm trace, keep as short as possible. FOR R FG FOR PU FG[:]= FOR FS FG[:]= FOR FS FG Low=R High=R FG Low=REVERSE LNE High=NORML FG[:] have internal pullup resistors. FG[:] have internal pulldown resistors For R R *K_ R *K_ R I@_ R I@_ R.K/F R.K/F T T T T SVOTRL_T H SVOTRL_LK H GLKN GLKP TV_ TV_ TV_ TV_REFSET J TV_IRTN TV_IRTN TV_IRTN LK E T E LUE E LUE# GREEN GREEN# RE RE# VSYN H HSYN G REFSET J LKLT_TRL E LKLT_EN F LTL_LK LTL_T L_LK F LV_EN F LIG LVG LVREFH F LVREFL F L_T F LLKN LLKP LLKN LLKP LTN LTN LTN LTP LTP LTP LTN LTN LTN LTP LTP LTP EXP_OMPI EXP_IOMPO EXP_RXN E EXP_RXN F EXP_RXN G EXP_RXN H EXP_RXN J EXP_RXN K EXP_RXN L EXP_RXN M EXP_RXN N EXP_RXN P EXP_RXN R EXP_RXN T EXP_RXN U EXP_RXN V EXP_RXN W EXP_RXN Y EXP_RXP EXP_RXP E EXP_RXP F EXP_RXP G EXP_RXP H EXP_RXP J EXP_RXP K EXP_RXP L EXP_RXP M EXP_RXP N EXP_RXP P EXP_RXP R EXP_RXP T EXP_RXP U EXP_RXP V EXP_RXP W EXP_TXN E EXP_TXN F EXP_TXN G EXP_TXN H EXP_TXN J EXP_TXN K EXP_TXN L EXP_TXN M EXP_TXN N EXP_TXN P EXP_TXN R EXP_TXN T EXP_TXN U EXP_TXN V EXP_TXN W EXP_TXN Y EXP_TXP EXP_TXP E EXP_TXP F EXP_TXP G EXP_TXP H EXP_TXP J EXP_TXP K EXP_TXP L EXP_TXP M EXP_TXP N EXP_TXP P EXP_TXP R EXP_TXP T EXP_TXP U EXP_TXP V EXP_TXP W MIS PI-EXPRESS GRPHIS TV VG LVS MIS PI-EXPRESS GRPHIS TV VG LVS T T E@.U_ E@.U_ E@.U_ E@.U_ RN I@PR-S- RN I@PR-S- T T R *./F_ R *./F_ T T T T I@.U_ I@.U_ T T RN I@PR-S- RN I@PR-S- T T T T E@.U_ E@.U_ E@.U_ E@.U_ E@.U_ E@.U_ R /F_ R /F_ RN I@PR-S- RN I@PR-S- I@.U_ I@.U_ E@.U_ E@.U_ T T E@.U_ E@.U_ E@.U_ E@.U_ R /F_ R /F_ R.K_ R.K_ R K_ R K_ R./F_ R./F_ E@.U_ E@.U_ E@.U_ E@.U_ RN I@PR-S- RN I@PR-S- I@.U_ I@.U_ R I@_ R I@_ E@.U_ E@.U_ E@.U_ E@.U_ T T T T T T E@.U_ E@.U_ T T E@.U_ E@.U_ E@.U_ E@.U_ I@.U_ I@.U_ R./F_ R./F_ T T RN I@PR-S- RN I@PR-S- E@.U_ E@.U_ R /F_ R /F_ T T R K_ R K_ T T T T E@.U_ E@.U_ R K_ R K_ T T T T RN I@PR-S- RN I@PR-S- T T R /F_ R /F_ RN I@PR-S- RN I@PR-S- R _ R _ E@.U_ E@.U_ T T T T R R I@.U_ I@.U_ E@.U_ E@.U_ RN I@PR-S- RN I@PR-S- I@.U_ I@.U_ T T E@.U_ E@.U_ R *K_ R *K_ R /F_ R /F_ R K_ R K_ T T T T R K_ R K_ T T E@.U_ E@.U_ E@.U_ E@.U_ I@.U_ I@.U_ T T I@.U_ I@.U_ T T R /F_ R /F_ R *./F_ R *./F_ E@.U_ E@.U_ T T MIRXN MIRXN MIRXP Y MIRXP MITXN MITXN MITXP Y MITXP SM_K M SM_K L SM_K E SM_K J SM_K F SM_K SM_K# N SM_K# K SM_K# E SM_K# J SM_K# F SM_K# SM_KE P SM_KE M SM_KE H SM_KE K SM_S# N SM_S# M SM_S# H SM_S# G SM_OOMP F SM_OOMP F SM_OT P SM_OT L SM_OT M SM_OT N SMROMPN K SMROMPP K SMVREF F SMVREF SMXSLEWIN E SMXSLEWOUT E SMYSLEWIN F SMYSLEWOUT F FG G FG H FG G FG F FG F FG G FG E FG FG J FG FG E FG FG E FG H FG FG H FG J FG H FG G FG G FG RSV G RSV G RSV J RSV RSV RSV RSV M_USY# J EXT_TS# J EXT_TS# H THRMTRIP# F PWROK RSTIN# E REF_LKN REF_LKP REF_SSLKN REF_SSLKP N P N N N P N P N P N N N N N N N MIRXN MIRXN MIRXP MIRXP MITXN MITXN MITXP MITXP MI R MUXING FG/RSV PM LK N MI R MUXING FG/RSV PM LK N T T R./F_ R./F_ T T T T T T E@.U_ E@.U_ T T R.K/F R.K/F E@.U_ E@.U_ E@.U_ E@.U_ E@.U_ E@.U_ T T R *K_ R *K_ E@.U_ E@.U_ E@.U_ E@.U_ T T T T R K_ R K_ E@.U_ E@.U_ R /F_ R /F_ E@.U_ E@.U_ T T E@.U_ E@.U_

7 S_RVENIN# S_RVENOUT# R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R S# R M R M R M R M R M R M R M R M R M R M R M R M R M R QS R QS R QS R QS R QS R QS R QS R M R M R M R M R MWE# R SRS# R SS# R S# R S# R M R M R M R M R M R M R M R QS R M R QS# R QS# R QS# R QS# R QS# R QS# R QS# R QS# R M R M R M R M R M R M R M R M R M R M R M R M R M R M R MWE# R SRS# R SS# R S# R S# R S# R M R M R M R M R M R M R M R M R QS R QS R QS R QS R QS R QS R QS R QS# R QS# R QS# R QS# R QS# R QS# R QS# R QS# R M R M R M R M R M R M R M R M R M R M R M R M R M R M R QS R M R M R M R M R M R M R M S_RVENIN# S_RVENOUT# R S# <,> R M[..] <> R MWE# <,> R SRS# <,> R S# <,> R S# <,> R SS# <,> R QS#[..] <> R M[..] <> R M[..] <,> R QS[..] <> R M[..] <> R QS#[..] <> R M[..] <,> R QS[..] <> R M[..] <> R MWE# <,> R SRS# <,> R SS# <,> R S# <,> R S# <,> R S# <,> Size ocument Number Rev ate: Sheet of QUNT OMPUTER ZL lviso (R) ustom Tuesday, March, Size ocument Number Rev ate: Sheet of QUNT OMPUTER ZL lviso (R) ustom Tuesday, March, Size ocument Number Rev ate: Sheet of QUNT OMPUTER ZL lviso (R) ustom Tuesday, March, T T SQ G SQ H SQ L SQ L SQ H SQ J SQ K SQ L SQ M SQ N SQ P SQ M SQ M SQ M SQ L SQ M SQ N SQ P SQ N SQ P SQ L SQ M SQ M SQ L SQ P SQ M SQ M SQ M SQ L SQ M SQ N SQ P SQ M SQ L SQ L SQ P SQ P SQ P SQ L SQ M SQ N SQ N SQ N SQ P SQ P SQ M SQ L SQ M SQ K SQ K SQ G SQ G SQ L SQ M SQ H SQ G SQ F SQ E SQ SQ SQ F SQ F SQ SQ S_S# K S_S# K S_S# L S_M J S_M P S_M L S_M P S_M P S_M P S_M J S_M S_QS K S_QS P S_QS N S_QS P S_QS M S_QS M S_QS J S_QS E S_QS# K S_QS# P S_QS# N S_QS# N S_QS# N S_QS# M S_QS# H S_QS# E S_M L S_M P S_M P S_M M S_M N S_M M S_M L S_M P S_M M S_M L S_M M S_M N S_M M S_M M S_S# N S_RS# P S_RVENIN# F S_RVENOUT# F S_WE# P R SYSTEM MEMORY R SYSTEM MEMORY T T SQ E SQ E SQ G SQ G SQ E SQ E SQ F SQ F SQ H SQ H SQ K SQ G SQ G SQ G SQ H SQ J SQ K SQ J SQ H SQ H SQ K SQ H SQ H SQ G SQ F SQ G SQ J SQ K SQ H SQ H SQ G SQ J SQ G SQ G SQ G SQ H SQ H SQ H SQ J SQ K SQ J SQ K SQ J SQ H SQ K SQ J SQ J SQ K SQ G SQ G SQ SQ SQ H SQ G SQ E SQ SQ SQ SQ SQ SQ SQ SQ SQ S_S# J S_S# G S_S# G S_M F S_M K S_M K S_M K S_M J S_M K S_M E S_M S_QS F S_QS K S_QS J S_QS K S_QS M S_QS H S_QS F S_QS S_QS# F S_QS# K S_QS# K S_QS# J S_QS# L S_QS# H S_QS# F S_QS# S_M H S_M K S_M H S_M J S_M K S_M J S_M K S_M H S_M J S_M H S_M J S_M G S_M G S_M G S_S# H S_RS# K S_RVENIN# F S_RVENOUT# F S_WE# H R SYSTEM MEMORY R SYSTEM MEMORY T T T T

8 V_RLL V_MPLL V_HPLL V_RT VP_GMH_P VP_GMH_P VP_GMH_P VP_GMH_P V._R_P V._R_P V._R_P V._R_P V._R_P V_GPLL_ V_GPLL V._R_P V_TV V_TVG V_QTV.V V_PLL V_PLL V_PLL V_PLL VGFOLLOW V_RT V_VFOLLOW VG_PIE V_QTV V_TVG V_TV V_TV VP VP.V.V.V.V.VSUS VG_PIE.V.V.V.V.V.V.V.VSUS VP VP VP V V V.V.V.V.V.V.V.V VP.V V Size ocument Number Rev ate: Sheet of QUNT OMPUTER ZL lviso (Power) Tuesday, March, Size ocument Number Rev ate: Sheet of QUNT OMPUTER ZL lviso (Power) Tuesday, March, Size ocument Number Rev ate: Sheet of QUNT OMPUTER ZL lviso (Power) Tuesday, March, Note: ll VSM pins shorted internally. Note: ll VSM pins shorted internally. close to PIN close to PIN,, m m m m m m m m m m m m m m EPOP,,, WHEN NO EXT.VG NO FILTER WHEN EXT. VG NO FILTER WHEN EXT. VG For R U_.V U_.V L LMPGSN L LMPGSN I@.U_ I@.U_.U_.U_.U.U.U/V_.U/V_.U_.U_ I@.U_ I@.U_ I@.U_ I@.U_ I@.U_ I@.U_ R R L UH L UH U/.V U/.V U_.V U_.V I@.U_ I@.U_ I@.U_ I@.U_ I@.U_ I@.U_.U_.U_ U_.V U_.V.U_.U_.U_.U_ U_.V U_.V.U_.U_ L UH L UH.U_.U_ I@U/.V I@U/.V.U/V.U/V H H.U_.U_ I@.U_ I@.U_ U_.V U_.V R./F R./F L UH L UH I@.U_ I@.U_.U_.U_.U.U.U_.U_ I@.U_ I@.U_.U_.U_ U_.V U_.V.U/V_.U/V_ I@U_.V I@U_.V U/.V U/.V.U_.U_ I@.U_ I@.U_.U_.U_ I@.U_ I@.U_.U_.U_ H H V T V R V N V M V K V J V V V U V T V R V P V N V M V L V K V J V H V G V V V U V T V R V P V N V M V L V K V J V H V K V H V K V J V K V K V K V K V W V U V T V K V V V U V K V W V V V T V K V K VH_MPLL VH_MPLL V_PLL V_PLL V_HPLL V_MPLL V_RT F V_RT E V_RT G V_SYN H VTT K VTT J VTT K VTT W VTT V VTT U VTT T VTT R VTT P VTT N VTT M VTT L VTT K VTT W VTT V VTT U VTT T VTT R VTT P VTT N VTT M VTT K VTT J VTT Y VTT W VTT U VTT R VTT P VTT N VTT M VTT L VTT J VTT N VTT M VTT N VTT M VTT N VTT M VTT VTT N VTT M VTT N VTT M VTT N VTT M VTT N VTT M VTT VTT V VTT N VTT M VTT G V_TV F V_TV E V_TV V_TV V_TV F V_TV E V_TVG H _TVG G V_TV VQ_TV H V_LVS V_LVS V_LVS V_LVS VHV VHV VHV VSM M VSM H VSM P VSM VSM VSM VSM P VSM N VSM M VSM L VSM K VSM J VSM H VSM G VSM F VSM E VSM P VSM N VSM M VSM L VSM K VSM J VSM H VSM G VSM F VSM E VSM E VSM E VSM E VSM E VSM E VSM E VSM E VSM E VSM E VSM E VSM E VSM P VSM N VSM M VSM L VSM K VSM J VSM H VSM G VSM F VSM E VSM P VSM N VSM M VSM L VSM K VSM J VSM H VSM G VSM F VSM E VSM VSM VSM VSM VSM VSM P VSM M VSM E VTX_LVS VTX_LVS VTX_LVS V_SM F V_SM P V_SM F V_SM F VG E VG W VG U VG R VG N VG L VG J V_GPLL Y V_GPLL Y V_GPLL Y V_GG F _GG G POWER POWER VTT_NTF W VTT_NTF V VTT_NTF U VTT_NTF T VTT_NTF R VTT_NTF P VTT_NTF N VTT_NTF M VTT_NTF L VTT_NTF W VTT_NTF V VTT_NTF U VTT_NTF T VTT_NTF R VTT_NTF P VTT_NTF N VTT_NTF M VTT_NTF L VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF VSM_NTF V_NTF W V_NTF V V_NTF U V_NTF T V_NTF R V_NTF P V_NTF N V_NTF M V_NTF L V_NTF W V_NTF V V_NTF U V_NTF T V_NTF R V_NTF P V_NTF N V_NTF M V_NTF L V_NTF W V_NTF V V_NTF U V_NTF T V_NTF R V_NTF P V_NTF N V_NTF M V_NTF L V_NTF W V_NTF V V_NTF U V_NTF T V_NTF R V_NTF P V_NTF N V_NTF M V_NTF L V_NTF W V_NTF V V_NTF U V_NTF T V_NTF R V_NTF P V_NTF N V_NTF M V_NTF L V_NTF W V_NTF V V_NTF U V_NTF T V_NTF P V_NTF N V_NTF M V_NTF L V_NTF Y V_NTF R V_NTF P V_NTF N V_NTF M V_NTF L V_NTF Y V_NTF R V_NTF P V_NTF N V_NTF M V_NTF L V_NTF Y V_NTF R V_NTF P V_NTF N V_NTF M V_NTF L V_NTF W V_NTF V V_NTF U V_NTF T V_NTF P V_NTF N V_NTF M V_NTF L _NTF _NTF _NTF Y _NTF _NTF _NTF Y _NTF _NTF _NTF Y _NTF _NTF _NTF Y _NTF _NTF _NTF Y _NTF _NTF _NTF Y _NTF R _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF Y _NTF R _NTF _NTF _NTF Y _NTF W _NTF V _NTF U _NTF T _NTF R _NTF P _NTF N _NTF M _NTF L _NTF _NTF _NTF Y _NTF W _NTF V _NTF U _NTF T _NTF R _NTF P _NTF N _NTF M _NTF L _NTF _NTF _NTF Y _NTF W _NTF V _NTF U _NTF T _NTF R _NTF P _NTF N _NTF M _NTF L _NTF _NTF Y _NTF _NTF Y NTF NTF U/.V U/.V.U_.U_.U_.U_ U_.V U_.V.U_.U_ U_.V U_.V.U_.U_ I@U/.V I@U/.V I@.U_ I@.U_.U_.V.U_.V R R U_.V U_.V L UH L UH U_.V U_.V.U_.U_ U_.V U_.V L LMPGSN L LMPGSN U/.V- U/.V- U/V U/V L LMPGSN L LMPGSN I@.U_ I@.U_

9 R M R M R QS R QS# R M R M R M R M R QS R M R M R M R M R QS# R M R QS R M R S# R MWE# R M SM_S# R M R M R SS# R QS# R M SM_S# R M R QS# R M R M R M R QS R QS R M R M R M R QS# M_OT M_OT LK_SRM LK_SRM# R S# R QS# R QS R QS# R SRS# R M R M R M R QS R M R M KE R M R M KE R M R M R S# R QS R M R M R QS# R M R M R S# R QS R QS# R M R M KE R M R M R S# R SS# R M R M R QS# R M R M R M R M R M R M R M R QS R MWE# R M LK_SRM R QS# R S# R M R M R QS R QS R M R M SM_S# R M LK_SRM# R QS R QS# R QS# R M M_OT R M R M R M R QS# R QS# R M R M R M R M R M R QS R M KE SM_S# R M R M R QS R SRS# R M M_OT R M R M R M R M R M R M R QS# R QS LK_SRM LK_SRM# LK_SRM# LK_SRM R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M R M SMK SMT SMT SMK R S# <,> R MWE# <,> R QS#[..] <> R M[..] <> R M[..] <,> R M[..] <> R QS[..] <> SM_S# <,> R QS#[..] <> R M[..] <> SM_S# <,> R SS# <,> R M[..] <,> R S# <,> R M[..] <> M_OT <,> R SRS# <,> M_OT <,> LK_SRM <> LK_SRM# <> R QS[..] <> R S# <,> R MWE# <,> SM_S# <,> R SS# <,> SM_S# <,> R S# <,> M_OT <,> M_OT <,> LK_SRM <> LK_SRM# <> R SRS# <,> KE <,> KE <,> KE <,> KE <,> LK_SRM# <> LK_SRM <> R S# <,> LK_SRM# <> LK_SRM <> R S# <,> SMT <> SMK <>.VSUS V V.VSUS.VSUS.VSUS V V V.VSUS.VSUS.VSUS.VSUS.VSUS.VSUS.VSUS.VSUS Size ocument Number Rev ate: Sheet of R SO-IMM ( P ) Tuesday, March, Size ocument Number Rev ate: Sheet of R SO-IMM ( P ) Tuesday, March, Size ocument Number Rev ate: Sheet of R SO-IMM ( P ) Tuesday, March, lose to JIMM lose to JIMM Place lose to JIMM LOK,, LOK,, SMbus address SMbus address KE, KE, Place lose to JIMM.U_.U_.U_.U_.U_.U_.U_.U_.U/.V.U/.V.U/.V.U/.V R K_ R K_.U/.V.U/.V.U/.V.U/.V.U/.V.U/.V R K_ R K_ Quanta omputer Inc. PROJET : ZL Quanta omputer Inc. PROJET : ZL.U/.V.U/.V.U_.U_.U_.U_.U_.U_.U/.V.U/.V VREF Q Q QS# QS Q Q Q Q QS# QS Q Q Q Q QS# QS Q Q Q Q M N Q Q KE V N _ V V V /P WE# V S# S# V OT Q Q QS# QS Q Q Q Q Q Q M Q Q Q Q M K K# Q Q Q Q N M Q Q Q Q QS# QS Q Q KE V V V V RS# S# V OT V N Q Q M Q Q Q Q M Q Q Q Q NTEST QS# QS Q Q Q Q M Q Q S SL V(SP) QS# QS Q Q Q Q K K# M Q Q Q Q QS# QS Q Q S S P R SRM SO-IMM (P) JIM P_R_.MM_REV P R SRM SO-IMM (P) JIM P_R_.MM_REV.U/.V.U/.V.U_.U_ VREF Q Q QS# QS Q Q Q Q QS# QS Q Q Q Q QS# QS Q Q Q Q M N Q Q KE V N _ V V V /P WE# V S# S# V OT Q Q QS# QS Q Q Q Q Q Q M Q Q Q Q M K K# Q Q Q Q N M Q Q Q Q QS# QS Q Q KE V V V V RS# S# V OT V N Q Q M Q Q Q Q M Q Q Q Q NTEST QS# QS Q Q Q Q M Q Q S SL V(SP) QS# QS Q Q Q Q K K# M Q Q Q Q QS# QS Q Q S S P R SRM SO-IMM (P) JIM P_R_.MM_ST P R SRM SO-IMM (P) JIM P_R_.MM_ST.U_.U_.U/.V.U/.V.U/.V.U/.V R K_ R K_.U_.U_.U/.V.U/.V.U/.V.U/.V.U/.V.U/.V R K_ R K_.U_.U_.U/.V.U/.V.U_.U_

10 .V.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_ Layout note: Place one cap close to every pullup resistors terminated to.v.v R M[..] <,>.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_.U_ R M[..] <,> Layout note: Place one cap close to every pullup resistors terminated to.v R M R S# RP <,> R S# PR-S- R S# <,> R S# <,> M_OT KE RP <,> KE PR-S- <,> SM_S# R M <,> R SS# R M RP PR-S-.V <,> R MWE# R M R M RP M_OT SM_S# RP R SS# R MWE# RP PR-S- PR-S- PR-S-.V <,> R SRS# R SRS# <,> KE SM_S# RP <,> SM_S# PR-S- M_OT <,> M_OT <,> KE SM_S# RP <,> SM_S# PR-S- <,> R S# R M <,> R S# R S# RP PR-S- R M <,> M_OT KE <,> KE R M RP PR-S- M_OT RP PR-S- R M R M RP PR-S-.V KE R M KE R S# R M R M R M R M RP RP RP RP PR-S- PR-S- PR-S- PR-S-.V R M R M R M R M R M R M RP RP RP PR-S- PR-S- PR-S-.V <,> R MWE# <,> R SS# <,> R S# R MWE# R SS# RP R M R M RP R M R S# RP PR-S- PR-S- PR-S-.V <,> R SRS# <,> SM_S# <,> M_OT <,> R S# R M R M R SRS# SM_S# R M M_OT R S# R M RP RP RP RP PR-S- PR-S- PR-S- PR-S-.V PROJET : ZL Quanta omputer Inc. Size ocument Number Rev R TERMINTION ate: Tuesday, March, Sheet of

11 <> GMHEXP_TXP[..] <> GMHEXP_TXN[..] <,> GMHEXP_RXP[..] <,> GMHEXP_RXN[..] GMHEXP_RXP GMHEXP_RXN GMHEXP_RXP GMHEXP_RXN GMHEXP_RXP GMHEXP_RXN GMHEXP_RXP GMHEXP_RXN GMHEXP_RXP GMHEXP_RXN GMHEXP_RXP GMHEXP_RXN GMHEXP_RXP GMHEXP_RXN GMHEXP_RXP GMHEXP_RXN GMHEXP_RXP GMHEXP_RXN GMHEXP_RXP GMHEXP_RXN GMHEXP_RXP GMHEXP_RXN GMHEXP_RXP GMHEXP_RXN GMHEXP_RXP GMHEXP_RXN GMHEXP_RXP GMHEXP_RXN GMHEXP_RXP GMHEXP_RXN GMHEXP_RXP GMHEXP_RXN <> LK_PIE_VG <> LK_PIE_VG# R VG.V R R V R R V R *K_ R E@K_ E@P_ XT_IN E@TX=MHz Y R *M_ E@P_ XT_OUT V R GMHEXP_TXP GMHEXP_TXN GMHEXP_TXP GMHEXP_TXN GMHEXP_TXP GMHEXP_TXN GMHEXP_TXP GMHEXP_TXN GMHEXP_TXP GMHEXP_TXN GMHEXP_TXP GMHEXP_TXN GMHEXP_TXP GMHEXP_TXN GMHEXP_TXP GMHEXP_TXN GMHEXP_TXP GMHEXP_TXN GMHEXP_TXP GMHEXP_TXN GMHEXP_TXP GMHEXP_TXN GMHEXP_TXP GMHEXP_TXN GMHEXP_TXP GMHEXP_TXN GMHEXP_TXP GMHEXP_TXN GMHEXP_TXP GMHEXP_TXN GMHEXP_TXP GMHEXP_TXN VTHM_LK VTHM_T *K_ M_O U H PIE_RXP G PIE_RXN G PIE_RXP F PIE_RXN E PIE_RXP E PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP Y PIE_RXN W PIE_RXP W PIE_RXN V PIE_RXP V PIE_RXN U PIE_RXP T PIE_RXN T PIE_RXP R PIE_RXN R PIE_RXP P PIE_RXN N PIE_RXP N PIE_RXN M PIE_RXP M PIE_RXN L PIE_RXP K PIE_RXN K PIE_RXP J PIE_RXN E@.U_ V_GMHEXP_RXP F E@.U_ V_GMHEXP_RXN PIE_TXP E E@.U_ V_GMHEXP_RXP PIE_TXN E@.U_ V_GMHEXP_RXN PIE_TXP E@.U_ V_GMHEXP_RXP PIE_TXN E@.U_ V_GMHEXP_RXN PIE_TXP E@.U_ V_GMHEXP_RXP PIE_TXN E@.U_ V_GMHEXP_RXN PIE_TXP E@.U_ V_GMHEXP_RXP PIE_TXN Y E@.U_ V_GMHEXP_RXN PIE_TXP W E@.U_ V_GMHEXP_RXP PIE_TXN Y E@.U_ V_GMHEXP_RXN PIE_TXP W E@.U_ V_GMHEXP_RXP PIE_TXN Y E@.U_ V_GMHEXP_RXN PIE_TXP W E@.U_ V_GMHEXP_RXP PIE_TXN U E@.U_ V_GMHEXP_RXN PIE_TXP T E@.U_ V_GMHEXP_RXP PIE_TXN U E@.U_ V_GMHEXP_RXN PIE_TXP T E@.U_ V_GMHEXP_RXP PIE_TXN U E@.U_ V_GMHEXP_RXN PIE_TXP T E@.U_ V_GMHEXP_RXP PIE_TXN P E@.U_ V_GMHEXP_RXN PIE_TXP N E@.U_ V_GMHEXP_RXP PIE_TXN P E@.U_ V_GMHEXP_RXN PIE_TXP N E@.U_ V_GMHEXP_RXP PIE_TXN P E@.U_ V_GMHEXP_RXN PIE_TXP N E@.U_ V_GMHEXP_RXP PIE_TXN L E@.U_ V_GMHEXP_RXN PIE_TXP K E@.U_ V_GMHEXP_RXP PIE_TXN L E@.U_ V_GMHEXP_RXN PIE_TXP K E@.U_ V_GMHEXP_RXP PIE_TXN L E@.U_ V_GMHEXP_RXN PIE_TXP K PIE_TXN R R *_ *_ F PIE_REFLKP E PIE_REFLKN G LK G T J SSIN H SSOUT M_IN H XTLIN J XTLOUT R E@K_ Z_V H R E@_ Z_V TESTEN E R E@_ Z_V TEST_YLK TEST_MLK F R T PLLTEST Z_V H E@K_ STEREOSYN E@M/M/M SS PI EXPRESS E@/F_ VPIE_R E@/F_ VPIE_R- PIE_LRP E@K/F VPIE_L PIE_LRN *K_ VPIE_TIN PIE_LI E@K_ E PIE_TESTIN PLTRST#_M -VPIE_RSTM PERSTb PERSTb_MSK V_RSET H RSET EXT_TV_Y/G K R EXT_TV_/R Y_G J EXT_TV_OMP _R_PR E@/F K OMP P T J T HSYN K VSYN R T E@K_ LK LVS VO / EXT TMS / GPIO THERM TMS GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO_PWRNTL GPIO_MEMSSIN VOMOE VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ PVT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPNTL_ VPNTL_ VPNTL_ VPNTL_ VREFG TXOUT_LN TXOUT_LP TXOUT_LN TXOUT_LP TXOUT_LN TXOUT_LP TXOUT_LN TXOUT_LP TXLK_LN TXLK_LP TXOUT_UN TXOUT_UP TXOUT_UN TXOUT_UP TXOUT_UN TXOUT_UP TXOUT_UN TXOUT_UP TXLK_UN TXLK_UP IGON LON TXM TXP TXM TXP TXM TXP TXM TXP LK T HP R G HSYN VSYN RSET T LK GPIO_UXWIN PLUS MINUS J H J K H F J K H J H H G G G F F E H J K H K J H J H J K H E G F E F E G F E F G F J K J H G VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPNTL VPNTL VPNTL VPNTL VREFG H EXT_TXLOUT- E@PR-S- RN TXLOUT- H EXT_TXLOUT TXLOUT J EXT_TXLOUT- E@PR-S- RN TXLOUT- J EXT_TXLOUT TXLOUT J EXT_TXLOUT- E@PR-S- RN TXLOUT- K EXT_TXLOUT TXLOUT J T E@PR-S- RN K T EXT_TXLLKOUT- TXLLKOUT- J EXT_TXLLKOUT TXLLKOUT G EXT_TXUOUT- E@PR-S- RN TXUOUT- G EXT_TXUOUT TXUOUT F EXT_TXUOUT- EXT_TXUOUT E@PR-S- RN TXUOUT- TXUOUT E EXT_TXUOUT- EXT_TXUOUT E@PR-S- RN TXUOUT- TXUOUT F T F T EXT_TXULKOUT- TXULKOUT- G EXT_TXULKOUT E@PR-S- RN TXULKOUT E ISP_ON LON ISP_ON <,> K J J J K K J K E E F TMS_TXM TMS_TXP TMS_TXM TMS_TXP TMS_TXM TMS_TXP TMS_TXM TMS_TXP TMS_LK TMS_T EXT_HSYN EXT_VSYN EXT_T EXT_LK VGTHRM VGTHRM- R R R R R R K EXT_VG_RE J EXT_VG_GRN J EXT_VG_LU J K H V_RST R G F G F E R E@K_ R *K_ T T T T T T T T T ROMIFG <> T T T VG_PWR_SW V_MEMSSIN E@P_ VOMOE R E@_ T T T T T T T T T T T T T T T T VPT_ <> VPT_ <> EIT <> EILK <> VPT_ <> VPT_ <> VPT_ <> -VG_LERT E@K_ E@K_ E@K_ E@K_ E@/F_ E@/F_ E@.U_ PLTRST#_M mil trace / mil space VGTHRM TMS_TXM TMS_TXP TMS_TXM TMS_TXP TMS_TXM TMS_TXP TMS_TXM TMS_TXP VGTHRM- XT_IN _S E@ KO V TMS_LK <,> TMS_T <,> R V_THM TMS_HP <,> E@LMPGSN EXT_VG_RE <> EXT_VG_GRN <> EXT_VG_LU <> EXT_HSYN <> EXT_VSYN <> E@/F EXT_T <> EXT_LK <> R *K_ V V R MEMORY LOK SPRE SPETRUM VG_PWR_SW <> U E@TSHFU V V hange to ohm for TI recommend R TXLOUT- <,> TXLOUT <,> TXLOUT- <,> TXLOUT <,> TXLOUT- <,> TXLOUT <,> TXLLKOUT- <,> TXLLKOUT <,> TXUOUT- <,> TXUOUT <,> TXUOUT- <,> TXUOUT <,> TXUOUT- <,> TXUOUT <,> TXULKOUT- <,> TXULKOUT <,> E@K_ MIL LON <,> lose to pin SI R R R R *_ E@_ E@_ E@_ Hi:.V Lo:.V E@.U_ E@P_ E@_ R U XIN XOUT V SRS P SSLK REF E@Y MK- PLE LOSE TO SI : New add U V XN XP GN VTHM_T_E VTHM_LK_E R E@_ R E@_ R E@_ R E@_ R E@_ R E@_ R E@_ R E@_ V R *K S R *K_ XT_OUT MK_V MK_P MK_M R PLTRST# <,,,,,,,> V VTHM_T_E VTHM_LK_E TX- <,> TX <,> TX- <,> TX <,> TX- <,> TX <,> LK- <,> LK <,> MK_P E@_ MOUT dd buffer for PLTRST# SLVE RESS: R *K_ <> EXT_TV_Y/G <> EXT_TV_/R <> EXT_TV_OMP MT MLK V : FOR E ONTROL FN VG_FN <> SRS= OWN -.% OWN -.% M OWN -.% HNGE TO LK_OUT FOR M R E@./F Q E@N E@P_ M@_ R M_IN M_O M@_ VGM R E@/F E@G- /LERT S SLK PWM E@N Q R VTHM_T_E R VTHM_LK_E R VTHM_LK R VTHM_T R VPT_ R EXT_TV_Y/G EXT_TV_/R E@.U_ PLE LOSE TO SI EXT_VG_RE EXT_VG_GRN R R E@/F_ E@/F_ EXT_VG_LU R E@/F_ EXT_TV_OMP R MT <,,> MLK <,,> R V R R R L V E@ E@U/V_ -VG_LERT MEMVMOE <> Size ocument Number Rev ustom VG HOST(TI M) ate: Wednesday, March, Sheet of V R E@K_ E@K_ R E@_ *_ E@.K/F E@.K/F E@.K/F E@.K/F *K_ E@/F_ E@/F_ E@/F_ Q E@N PROJET : ZL Quanta omputer Inc. V

12 VG_PIE PV MPV LVR V V_VQ V_V VG_V TXVR V V_V V_VQ LPV VRH V LVR PIE_PV.V.V.V.V.V V V VG.V VG.V.V.V.V.V.V.V.V.V V.V.V.V.V.V.V.V.V VG.V Size ocument Number Rev ate: Sheet of TI M(POWER) ustom Tuesday, March, Size ocument Number Rev ate: Sheet of TI M(POWER) ustom Tuesday, March, Size ocument Number Rev ate: Sheet of TI M(POWER) ustom Tuesday, March, (VG ORE=. OR.V) (EXT.TMS) (IO.POWER) (PIE.V) (QUIET PIE.V) (PIE PLL/IO.V) PROJET : ZL Quanta omputer Inc. (m) (m) (.m) (m) (m) (m) () (m) (m) (m) (m) (m) (m) (m) (m) (.m) E: dd bulk cap. for acer RT L E@LMPGSN L E@LMPGSN E@U/V_ E@U/V_ E@.U_ E@.U_ E@.U_ E@.U_ E@U/V_ E@U/V_ E@.U_ E@.U_ E@.U_ E@.U_ E@.U_ E@.U_ E@U/V_ E@U/V_ E@U/V E@U/V E@.U_ E@.U_ L E@LMPGSN L E@LMPGSN L E@LMPGSN L E@LMPGSN E@.U_ E@.U_ T T E@.U_ E@.U_ L E@LMPGSN L E@LMPGSN E@.U_ E@.U_ L E@_ L E@_ E@U/V_ E@U/V_ E@P_ E@P_ L *_ L *_ E@P_ E@P_ E@.U_ E@.U_ E@U/V E@U/V E@P_ E@P_ E@.U_ E@.U_ E@.U_ E@.U_ E@.U_ E@.U_ E@U/V E@U/V E@.U_ E@.U_ E@.U_ E@.U_ E@U/V_ E@U/V_ E@.U_ E@.U_ E@P_ E@P_ E@P_ E@P U U _U U _W W _W W _Y Y _K K _J J PIE K K PIE L L PIE M M PIE M M PIE M M PIE M M PIE M M PIE P P PIE N N PIE R R PIE R R PIE R R PIE R R PIE R R PIE R R PIE T T PIE T T PIE U U PIE V V PIE V V PIE V V PIE V V PIE V V PIE Y Y PIE W W PIE W W PIE PIE PIE PIE PIE PIE PIE PIE PIE PIE PIE PIE E E PIE F F PIE H H _M M _N N _N N _P P _P P _R R _R R _R R _R R _R R _R R _R R _T T _T T _T T _W W _V V _V V _U U _U U _T T _T T _T T _T T V_W W V_M M V_R R V_T T _F F _G G _G G _G G _G G _G G _G G _H H _H H _H H _H H _H H _H H _H H _H H _H H _H H _J J _J J G G _G G _G G _R R _P P _M M _M M _L L _K K _K K _K K _R R _T T V_P P V_P P V_P P V_U U V_U U V_U U V_U U V_U U V_U U V_V V V_V V V_V V V_V V V_V V V_V V V_N N V_N N V_N N V_W W V_W W V_W W V_W W V_W W V_N N V_N N V_M M V_M M V_M M V_N N V_M M V_M M V_P P V_P P V_P P V_M M V_W W ENTER RRY ORE GN UE E@M/M/M ENTER RRY ORE GN UE E@M/M/M L E@LMPGSN L E@LMPGSN L E@LMPGSN L E@LMPGSN E@.U_ E@.U_ E@.U_ E@.U_ E@U/V E@U/V E@P_ E@P_ E@P_ E@P_ E@.U_ E@.U_ E@.U_ E@.U_ E@.U_ E@.U_ E@U/V_ E@U/V_ E@.U_ E@.U_ E@U/V_ E@U/V_ E@.U_ E@.U_ E@P_ E@P_ E@.U_ E@.U_ E@P_ E@P_ E@.U_ E@.U_ T T E@U/V E@U/V E@U/V_ E@U/V_ E@.U_ E@.U_ E@.U_ E@.U_ E@P_ E@P_ E@U/V_ E@U/V_ E@P_ E@P_ E@.U_ E@.U_ E@.U_ E@.U_ E@P_ E@P_ E@P_ E@P_ E@.U_ E@.U_ L E@LMPGSN L E@LMPGSN E@.U_ E@.U_ E@.U_ E@.U_ E@U/V_ E@U/V_ E@.U_ E@.U_ L E@LMPGSN L E@LMPGSN E@.U_ E@.U_ E@.U_ E@.U_ E@U/V_ E@U/V_ E@U/.V E@U/.V E@U/V_ E@U/V_ E@U/V E@U/V E@.U_ E@.U_ E@.U_ E@.U_ E@.U_ E@.U_ E@.U_ E@.U_ L E@LMPGSN L E@LMPGSN E@P_ E@P_ E@U/V_ E@U/V_ E@.U_ E@.U_ E@U/V_ E@U/V_ T T T T V_ V_ V_ V_ V_ V_P P V_Y Y V_ V_ V_H H V_H H V_M M V_Y Y VR_ VR_ VR_ VR_ VR_ VR_ VR_ VR_G G VR_ VR_ VR_ VR_ PIE_VR G G PIE_VR K K PIE_VR J J PIE_VR G G PIE_VR G G PIE_PV N N PIE_PV N N PIE_PV P P PIE_PV U U PIE_PV T T PIE_PV V V PIE_PV W W N_ N_ N_ N_ N_E E N_T T N_ Q LR_F F LR_H H LR_G G LR_G G LP H TP H TXR_H H TXR_G G TXR_G G RH F RH M N_H H N_G G Q F N H I E I E P J MP VR_T T VR_R R VR_R R VR_N N VR_N N VR_M M VR_L L VR_K K VR_K K VR_N N VR_J J VR_J J VR_J J VR_J J VR_H H VR_H H VR_H H VR_H H VR_T T VR_V V VR_V V VR_V V VR_ VR_ VR_ VR_ VR_ VR_ VR_ VR_ VR_ VR_ VR_ VR_ VR_ VR_ VR_ VR_ VR_ VR_ VR_ VR_E E VR_F F VR_G G VR_G G VR_G G VR_G G VR_G G VR_G G VR_G G VR_H H VR_H H VR_ VR_L L LVR E E LVR E E LVR F F LVR E E LPV H TPV H TXVR_F F TXVR_F F VRH F VRH N V_F F V_E E VQ F V H VI E VI E PV K MPV I/O POWER U E@M/M/M I/O POWER U E@M/M/M T T E@.U_ E@.U_ E@U/V E@U/V E@U/V_ E@U/V_ E@U/V_ E@U/V_ E@P_ E@P_ E@U/V_ E@U/V_ E@U/V E@U/V E@.U_ E@.U_ E@P_ E@P_ E@.U_ E@.U_ E@.U_ E@.U_ L E@LMPGSN L E@LMPGSN L E@_ L E@_ E@U/V_ E@U/V_ T T E@.U_ E@.U_ E@.U_ E@.U_ E@U/V_ E@U/V_ E@.U_ E@.U_ E@R E@R E@.U_ E@.U_ E@P_ E@P_ T T E@.U_ E@.U_ E@.U_ E@.U_ E@P_ E@P_ E@.U_ E@.U_ E@.U_ E@.U_ E@.U_ E@.U_ E@.U_ E@.U_ E@P_ E@P_ L E@LMPGSN L E@LMPGSN E@.U_ E@.U_

13 <> M[..] M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M H H J J J H H G G E E G G F G F E F E F E F E F E F E F E E E F F E F F Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q U MEMORY INTERFE E@M/M/M M M M M M M M M M M M M M M M QM# QM# QM# QM# QM# QM# QM# QM# QS QS QS QS QS QS QS QS RS# S# WE# S# S# KE LK LK# LK LK# MVREF MVREFS IM_ IM_ E F F E J F E F E J F F E F E E E F M M M M M M M M M M M M M M -QM -QM -QM -QM -QM -QM -QM -QM QS QS QS QS QS QS QS QS -RS -S -WE -S -S KE R LK R -LK R LK R -LK R <> M[..] M[..] <> -QM[..] <> QS[..] <> -RS <> -S <> -WE <> -S <> -S <> KE <> E@K_ E@ M_LK <> E@ -M_LK <> E@ M_LK <> E@ -M_LK <>.V.V R R E@ E@ MVREF MVREFS IM R T IM E@ T E@.U_ E@.U_ R E@ M M Q F M Q E M Q G M Q G M Q F M Q E M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q G M Q H M Q H M Q J M Q K M Q K M Q L M Q L M Q G M Q F M Q H M Q E M Q F M Q J M Q F M Q H M Q U M Q U M Q U M Q V M Q W M Q W M Q Y M Q Y M Q U M Q V M Q V M Q V M Q W M Q Y M Q Y M Q M Q M Q M Q M Q M Q M Q M Q E M Q E M Q M Q M Q M Q M Q M Q E M Q E M Q E Q VR.V U MEMVMOE_ GN MEMORY INTERFE E@M/M/M M M M M M M M M M M M M M M M QM# QM# QM# QM# QM# QM# QM# QM# QS QS QS QS QS QS QS QS RS# S# WE# S# S# KE LK LK# LK LK# IM_ IM_ ROMS# MEMVMOE_ MEMVMOE_ MEMTEST MEMVMOE_ V_T N M M L L M M P N K K J P P P E J G W W F K G V W R T T R R M M M M M M M M M M M M M M -QM -QM -QM -QM -QM -QM -QM -QM QS QS QS QS QS QS QS QS -RS -S -WE -S -S R KE R N LK R N -LK R T T E F LK -LK IM IM MMTEST R E@ R R MEMVMOE R M@.K_ -RS <> -S <> -WE <> -S <> -S <> E@K_ E@ E@ E@ E@ M[..] <> -QM[..] <> QS[..] <> KE <> M_LK <> -M_LK <> M_LK <> -M_LK <> T T : RESERVE FOR M R E@K_ MEMVMOE <>.V Place close to SI.V V_T GN For M: ohm SJ GPIO_ GPIO_ GPIO_(,) GPIO_ GPIO_ PI-Express urrent alibration andgap ackup : use reference voltage from andgap : use reference voltage from resistor divider PI-Express PLL alibration force enable : isable PLL force calibration : Enable PLL force calibration : PI Express. mode : RESERVE : PI Express. mode : RESERVE Turn off PI-Express impedance / strength calibration : enable : disable ypass PI-Express PLL GPIO_ GPIO_ GPIO(,:) INT P/ VPT_~ MEM TYPE : Normal : Inject extra current for output buffer switching Strap to set the debug muxes to bting out EUG signals even if registers are inaccessible ROMIFG STRPS PIN PI-Express transmitter current compensation xx: No ROM, HG_I= xx: No Rom, HG_I= : Parallel ROM, hip I'S from ROM : Parallel ROM, hip I'S from ROM VPT_: =Mx =Mx VPT_: =M =M VPT_: =Hynix =Samsung R *K_ ROMIFG R E@K_ FOR MP ONLY : M : M ROMIFG V R E@K_ VPT_ R *K_ ROMIFG <> R *K_ : FOR HYNIX MEMORY VPT_ VPT_ VPT_ VPT_ VPT_ R E@K_ VPT_ <> VPT_ <> VPT_ <> VPT_ <> VPT_ <> VPT_ VPT_ VPT_ VPT_ R E@K_ R *K_ R *K_ R E@K_ PROJET :ZL Quanta omputer Inc. Size ocument Number Rev ustom TI M MEM/STRPS PIN ate: Tuesday, March, Sheet of R *K_ R E@K_

14 M M M M M -QM MVREF_ M QS MVREF_ M M M M M M M M QS M MVREF_ -S -QM MVREF_ -WE M M M M M M M -M_LK KE M M -RS M M -S M -S M M_LK M -S MVREF_ M M M M M MVREF_ MVREF_ -QM -WE -S KE -QM M -S -RS M -M_LK M_LK QS M M M M QS M M M M MVREF_ M M M M M -S -S M M M M M M M M M M M M M M M M M -WE -M_LK KE -RS -S -S M_LK -WE -S KE -S -RS -M_LK M_LK M_LK- M_LK- M_LK- M_LK- QS -QM QS -QM M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M QS QS -QM -QM M M M M M M M M M M M M M M QS M -QM QS -QM M M M M M M M M M M M M M M M M M M M M M M M M QS -QM QS -QM M M M M M M M M QS -QM M M M M M M M M M M M M M M M M QS -QM M M M M M M -QM M M M M M M M M M M M QS QS M M -QM M M M M M -QM[..] <> M[..] <> QS[..] <> M[..] <> -S <> M[..] <> M[..] <> -QM[..] <> QS[..] <> -WE <> -S <> -RS <> -S <> KE <> -S <> -RS <> -S <> -WE <> -S <> KE <> M_LK <> -M_LK <> -M_LK <> M_LK <> -M_LK <> M_LK <> -M_LK <> M_LK <>.V.V.V.V.V.V.V.V.V.V.V.V Size ocument Number Rev ate: Sheet of VG R VRM- NNEL Tuesday, March, Size ocument Number Rev ate: Sheet of VG R VRM- NNEL Tuesday, March, Size ocument Number Rev ate: Sheet of VG R VRM- NNEL Tuesday, March, Memory decoupling Place close to memory More Memory decoupling PROJET : ZL Quanta omputer R Mbit MXX ug VG R MEMORY More Memory decoupling Memory decoupling More Memory decoupling More Memory decoupling Memory decoupling Place close to memory VG R R Mbit MXX ug These resistors and caps must be placed to minimize any stubs. These must also be placed after the memory t least a.: spacing between the pair t least a.: spacing between the pair These resistors and caps must be placed to minimize any stubs. These must also be placed after the memory Mx KWT KQF-G.V Mx KW-T KE-G.V T T E@U/V E@U/V E@.U_ E@.U_ E@.U_ E@.U_ E@U/V E@U/V E@P E@P R E@.K/F R E@.K/F T T E@U/V_ E@U/V_ T T E@U/V_ E@U/V_ T T R E@.K/F R E@.K/F T T E@.U_ E@.U_ R E@.K/F R E@.K/F E@U/V_ E@U/V_ E@.U_ E@.U_ E@U/V E@U/V VREF M M M L M M L M M (P) M M L L QM QM G QM G QM RS L S K WE K S M LK L KE M L N M N N N G N G N K N K V_ K N L N L N/TH G N/TH G N/TH H VQ_ J N/TH H QS VQ_ Q Q Q Q Q Q Q Q Q J Q J Q H Q H Q F Q F Q E Q E Q E Q E Q F Q F Q H Q H Q J Q J Q Q Q Q Q Q Q Q V_ V_ V_ V_ V_ K V_ K V_ K VQ_ VQ_ VQ_ VQ_ VQ_ VQ_ VQ_ VQ_ E VQ_ E VQ_ F VQ_ F VQ_ H VQ_ H _ J _ K LK# L N/TH H N/TH H N/TH G N/TH G N/TH E N/TH E N/TH E N/TH E N/TH F N/TH F N/TH F N/TH F _ J _ J _ J _ K _ K _ Q_ Q_ Q_ Q_ Q_ Q_ E Q_ E Q_ F Q_ F Q_ G Q_ G Q_ H Q_ H Q_ J Q_ J VQ_ J QS G QS G QS Q_ Q_ Q_ Q_ Q_ ML L U E@VRM_MX- PG-VRM U E@VRM_MX- PG-VRM E@.U_ E@.U_ E@.U_ E@.U_ T T E@U/V E@U/V E@P E@P E@.U_ E@.U_ E@P E@P E@P E@P T T E@.U_ E@.U_ T T E@.U_ E@.U_ T T T T T T R E@_ R E@_ E@U/V E@U/V VREF M M M L M M L M M (P) M M L L QM QM G QM G QM RS L S K WE K S M LK L KE M L N M N N N G N G N K N K V_ K N L N L N/TH G N/TH G N/TH H VQ_ J N/TH H QS VQ_ Q Q Q Q Q Q Q Q Q J Q J Q H Q H Q F Q F Q E Q E Q E Q E Q F Q F Q H Q H Q J Q J Q Q Q Q Q Q Q Q V_ V_ V_ V_ V_ K V_ K V_ K VQ_ VQ_ VQ_ VQ_ VQ_ VQ_ VQ_ VQ_ E VQ_ E VQ_ F VQ_ F VQ_ H VQ_ H _ J _ K LK# L N/TH H N/TH H N/TH G N/TH G N/TH E N/TH E N/TH E N/TH E N/TH F N/TH F N/TH F N/TH F _ J _ J _ J _ K _ K _ Q_ Q_ Q_ Q_ Q_ Q_ E Q_ E Q_ F Q_ F Q_ G Q_ G Q_ H Q_ H Q_ J Q_ J VQ_ J QS G QS G QS Q_ Q_ Q_ Q_ Q_ ML L U E@VRM_MX- PG-VRM U E@VRM_MX- PG-VRM R E@_ R E@_ T T E@.U_ E@.U_ T T E@.U_ E@.U_ E@.U/V_ E@.U/V_ E@.U/V_ E@.U/V_ T T T T R E@.K/F R E@.K/F E@.U_ E@.U_ E@.U_ E@.U_ E@.U_ E@.U_ E@.U_ E@.U_ R E@_ R E@_ E@.U_ E@.U_ T T E@.U_ E@.U_ R E@.K/F R E@.K/F T T E@.U_ E@.U_ T T E@P E@P T T E@U/V E@U/V T T R E@.K/F R E@.K/F T T VREF M M M L M M L M M (P) M M L L QM QM G QM G QM RS L S K WE K S M LK L KE M L N M N N N G N G N K N K V_ K N L N L N/TH G N/TH G N/TH H VQ_ J N/TH H QS VQ_ Q Q Q Q Q Q Q Q Q J Q J Q H Q H Q F Q F Q E Q E Q E Q E Q F Q F Q H Q H Q J Q J Q Q Q Q Q Q Q Q V_ V_ V_ V_ V_ K V_ K V_ K VQ_ VQ_ VQ_ VQ_ VQ_ VQ_ VQ_ VQ_ E VQ_ E VQ_ F VQ_ F VQ_ H VQ_ H _ J _ K LK# L N/TH H N/TH H N/TH G N/TH G N/TH E N/TH E N/TH E N/TH E N/TH F N/TH F N/TH F N/TH F _ J _ J _ J _ K _ K _ Q_ Q_ Q_ Q_ Q_ Q_ E Q_ E Q_ F Q_ F Q_ G Q_ G Q_ H Q_ H Q_ J Q_ J VQ_ J QS G QS G QS Q_ Q_ Q_ Q_ Q_ ML L U E@VRM_MX- PG-VRM U E@VRM_MX- PG-VRM T T E@.U_ E@.U_ T T E@.U_ E@.U_ T T R E@_ R E@_ T T E@.U_ E@.U_ E@P E@P E@.U_ E@.U_ E@P E@P R E@_ R E@_ E@U/V_ E@U/V_ E@U/V E@U/V E@U/V E@U/V R E@_ R E@_ E@.U_ E@.U_ E@U/V_ E@U/V_ E@U/V_ E@U/V_ E@U/V_ E@U/V_ T T E@.U_ E@.U_ E@.U_ E@.U_ E@.U_ E@.U_ E@.U/V_ E@.U/V_ E@P E@P E@.U_ E@.U_ E@.U_ E@.U_ T T T T E@.U_ E@.U_ E@.U_ E@.U_ E@.U_ E@.U_ R E@_ R E@_ E@.U_ E@.U_ E@.U_ E@.U_ E@.U/V_ E@.U/V_ E@U/V_ E@U/V_ E@.U_ E@.U_ E@U/V_ E@U/V_ R E@.K/F R E@.K/F T T E@.U_ E@.U_ R E@.K/F R E@.K/F E@U/V_ E@U/V_ E@.U_ E@.U_ E@U/V_ E@U/V_ VREF M M M L M M L M M (P) M M L L QM QM G QM G QM RS L S K WE K S M LK L KE M L N M N N N G N G N K N K V_ K N L N L N/TH G N/TH G N/TH H VQ_ J N/TH H QS VQ_ Q Q Q Q Q Q Q Q Q J Q J Q H Q H Q F Q F Q E Q E Q E Q E Q F Q F Q H Q H Q J Q J Q Q Q Q Q Q Q Q V_ V_ V_ V_ V_ K V_ K V_ K VQ_ VQ_ VQ_ VQ_ VQ_ VQ_ VQ_ VQ_ E VQ_ E VQ_ F VQ_ F VQ_ H VQ_ H _ J _ K LK# L N/TH H N/TH H N/TH G N/TH G N/TH E N/TH E N/TH E N/TH E N/TH F N/TH F N/TH F N/TH F _ J _ J _ J _ K _ K _ Q_ Q_ Q_ Q_ Q_ Q_ E Q_ E Q_ F Q_ F Q_ G Q_ G Q_ H Q_ H Q_ J Q_ J VQ_ J QS G QS G QS Q_ Q_ Q_ Q_ Q_ ML L U E@VRM_MX- PG-VRM U E@VRM_MX- PG-VRM E@.U_ E@.U_ E@U/V_ E@U/V_ T T E@U/V_ E@U/V_ E@U/V_ E@U/V_ T T E@.U_ E@.U_ E@U/V_ E@U/V_ E@.U_ E@.U_ E@.U_ E@.U_ R E@_ R E@_ E@U/V_ E@U/V_ T T

15 .V.V R I@K_ SVO_TRLLK R I@K_ SVO_TRLT <> SVO_R <> SVO_R- <> SVO_G <> SVO_G- <> SVO_ <> SVO_- <> SVO_LK <> SVO_LK- SVO_R SVO_R- SVO_G SVO_G- VI_V SVO_ SVO_- INT- SVO_LK SVO_LK- INT I@.U/V_ GMHEXP_RXN <,> GMHEXP_RXP <,> PULL LOW FOR VO NOT PRESENT(INTERNL PULLLOW IN GM) VI_V I@.U/V_.V m V m.v R *K_ L L I@LMS I@LMS V VI_V_PLL VI_V V_PLL V.V <,,,,,,,> PLTRST# RESET* SVO_STLL- S SVO_STLL INT- <> SVO_TRLLK SP SVO_INT- I@.U_ I@U/V_ INT <> SVO_TRLT SP SVO_INT I@.U_ I@.U_ I@.U_ I@U/V_ GN_PLL GN VOT GN GN TMS_HP <,> VOLK S_PROM HPET VI_V S_PROM V L <,> TMS_T S_ TPG R I@K_ I@LMS R <,> TMS_LK I@K_.V VI_V S_ SEN V VSWING R I@.K_ I@.U_ I@.U_ I@U/V_ I@H-E L I@LMS VI_TV V I@.U_ I@.U_ I@U/V_ VI_LK- VI_LK R I@K_ VI_TX- VI_TX VI_TX- VI_TX VI_TX- VI_TX U V SVO_LK- SVO_LK GN SVO_- SVO_ V SVO_G- SVO_G GN SVO_R- SVO_R TL* TL TV T* T TGN T* T TV T* T TGN LWYS NOT ON, TEST ONLY VOLK VOT SL S U WP *T V GN V V *.U_ VI_LK- VI_LK VI_TX- VI_TX VI_TX- VI_TX VI_TX- VI_TX R R R R R R R R I@_ I@_ I@_ I@_ I@_ I@_ I@_ I@_ LK- LK TX- TX TX- TX TX- TX LK- <,> LK <,> TX- <,> TX <,> TX- <,> TX <,> TX- <,> TX <,> V V R *K_ VOLK R *K_ VOT H/ QUNT OMPUTER Size ocument Number Rev ustom ZL ate: Tuesday, March, Sheet of

16 V R I@K_ PULL HIGH TO V_S T PGE U R _ ISPON LI#.U_ LV_ LV LI# <,> IN OUT S GN IN ISP_ON U/V_.U/V_ U/V_ <,> ISP_ON ON/OFF GN.U_.U_ VSUS TRE MIL I@S LON <,> SW MISKI_LI T_ R E@K_ Lid Switch Q TEU E_FPK# <> <> I_EILK <> EILK.V R.K_.V R.K_.V.V Q I@FVN Q V R.K_ EILK V R.K_ <,> TXULKOUT- <,> TXULKOUT <,> TXUOUT- <,> TXUOUT <,> TXLOUT- <,> TXLOUT <,> TXLOUT- <,> TXLOUT <,> TXLOUT- <,> TXLOUT <,> TXLLKOUT- <,> TXLLKOUT TXULKOUT- TXULKOUT TXUOUT- TXUOUT TXLOUT- TXLOUT TXLOUT- TXLOUT TXLOUT- TXLOUT EILK EIT TXUOUT- TXUOUT TXLLKOUT- TXLLKOUT TXUOUT- TXUOUT INV R _ VJ ISPON LV N FOXONN_LVS V VSUS TXUOUT- <,> TXUOUT <,> TXUOUT- <,> TXUOUT <,> VIN L KLL.U_ VIN P_ *U/V-T ONTRST <> <> I_EIT I@FVN EIT <> EIT LEVEL SHIFT FOR EI : hange to FV for Vgs issue <,> PR_INSERT_V V.U_ V PR_INSERT_V TV_Y/G PR_INSERT_V TV_/R U SEL OM GN V V IN_ TV_Y/G_PR IN_ U SEL V V OM IN_ IN_ TV_/R_PR TV_/R_SYS GN TV_Y/G_PR <> TV_/R_PR <> S-VIEO L TV_/R_SYS TV-HROM FM---T R /F_ P_ P_ N TV-LUM L FM---T P_ P_ TV_Y/G_SYS R V PR_INSERT_V TV_OMP U SEL OM GN V IN_ IN_ V TV_OMP_PR TV_OMP_SYS TV_OMP_PR <> TV-OMP L FM---T P_ P_ TV_OMP_SYS R R N@_ TV_Y/G R N@_ TV_Y/G_SYS TV_/R R N@_ TV_/R_SYS TV_OMP TV_OMP_SYS IRUITS WHEN NO OKING <> INT_TV_Y/G <> INT_TV_/R <> INT_TV_OMP <> EXT_TV_Y/G <> EXT_TV_/R <> EXT_TV_OMP R R R R R R I@_ TV_Y/G I@_ TV_/R I@_ TV_OMP E@_ TV_Y/G E@_ TV_/R E@_ TV_OMP PROJET : ZL Quanta omputer Inc. Size ocument Number Rev VO H & RJ- ON ate: Friday, pril, Sheet of

17 <> INT_VG_RE <> INT_VG_GRN <> INT_VG_LU <> INT_VSYN <> INT_HSYN <> INT_LK <> INT_T R R R RN RN I@_ I@_ I@_ VG_RE VG_GRN VG_LU I@PR-S- VSYN HSYN I@PR-S- RTLK RTT <,> PR_INSERT_V SEL FUNTION LOW IN_ HIGH IN_ PR_INSERT_V VG_RE PR_INSERT_V VG_GRN U SEL V V OM IN_ VG_RE_PR VG_RE_SYS IN_ U SEL V V OM IN_ VG_GRN_PR VG_GRN_SYS IN_ GN V VG_RE_PR <>.U_ V VG_GRN_PR <>.U_ V R.V R RTT E@_ RTPU I@_ R.K_ Q FVN RTV R.K_ T_ T_ <> <> EXT_VG_RE <> EXT_VG_GRN <> EXT_VG_LU <> EXT_VSYN <> EXT_HSYN <> EXT_LK <> EXT_T R R R RN RN E@_ E@_ E@_ VG_RE VG_GRN VG_LU E@PR-S-VSYN HSYN E@PR-S-RTLK RTT PR_INSERT_V VG_LU U SEL V V OM IN_ VG_LU_PR VG_LU_SYS IN_ R N@_ VG_RE_SYS V VG_LU_PR <>.U_ RTLK RTPU R.K_ Q FVN RTV R.K_ LK_ LK_ <> VG_GRN R N@_ VG_GRN_SYS : hange to FVN for Vgs issue. VG_LU R N@_ VG_LU_SYS N VG_RE_SYS VG_GRN_SYS VG_LU_SYS TO RT R R R RTV T_ RT_HS_ RT_VS_ LK_.V V V VG_RE_SYS U RTVSYN RTVSYN <> RT_VS_ V.U_ RTV RTV VG_LU_SYS V L L L RT_R_ RT_G_ RT L L L RT_R_ LMSN RT_G_ LMSN RT LMSN RT_ONN /F_ /F_ /F_ P_ P_ P_ *P_ *P_ *P_ P_ P_ P_ R I@_.U_ R E@_ U.U_ VSYN HTGH R _ L F POLY_SWITH_. H U.U_ U R K_ RTHSYN <> U VG_GRN_SYS HSYN HTGH R _ RTHSYN LOSE TO U, U L *P_ RT_HS_ *P_ HNGE TO ohm for cer L PROJET : ZL Quanta omputer Inc. Size ocument Number Rev RT & S-VIEO ate: Tuesday, March, Sheet of

MODEL REV CHANGE LIST ZL9. Preliminary Release

MODEL REV CHANGE LIST ZL9. Preliminary Release E MOEL REV HNGE LIST ZL Preliminary Release Page : dd.pf for Signal quanlity Page : dd R0 0om for UM. Page : seprate STLE# for IE interrupt. Page :add R 0ohm for M-T. Page : enlarge H,H to mm for VG sink

More information

ZR1 Block Diagram PCIE. Yonah / Merom. INTEL Mobile_479 CPU. Page : 3,4. HOST BUS 667/533MHz. Calistoga 945GM / 945PM / 940GML 1466 BGA TVOUT RGB

ZR1 Block Diagram PCIE. Yonah / Merom. INTEL Mobile_479 CPU. Page : 3,4. HOST BUS 667/533MHz. Calistoga 945GM / 945PM / 940GML 1466 BGA TVOUT RGB LOK GEN IS0 Page : V /.V / 0V Page :.V / 0.V / VP Page : NVV /.V Page : PU ORE /.V Page : TTERY HRGER Page : HOST 00/MHz PI-E 00MHz VG MHz US MHz PI MHz REF MHz VPU V S SUS VSUS V V V_S 0.VSUS 0.V VP NVV.V.V

More information

MODEL REV CHANGE LIST 1 2A 2A 2A 1A 1A 2A 2A 1A 1A 2A 2A 1A 1A 1A 1A 1A 1A 1A CT3/5 MB BOARD. Page CT3/5 MB 31CT3MB CT3MB0031

MODEL REV CHANGE LIST 1 2A 2A 2A 1A 1A 2A 2A 1A 1A 2A 2A 1A 1A 1A 1A 1A 1A 1A CT3/5 MB BOARD. Page CT3/5 MB 31CT3MB CT3MB0031 MOEL REV HNGE LIST Model Page T/ M OR FROM TO T/ M TM00 TM00 PGE --- Enable LKM from clokc generator for the PLL circuit of, and disable the ocsillator circuit of PI PLL. PGE --- Remove H/W shutdown circuit

More information

DC/DC +3V_SRC +5VSUS PG 34 LVDS TVOUT USB2.0 (P3) USB2.0 (P2) USB2.0 (P0~P1,P4) USB2.0 (P0~P7) LAN RTL8100S PG 25 CARDBUS PC7411 PG 21,22,23

DC/DC +3V_SRC +5VSUS PG 34 LVDS TVOUT USB2.0 (P3) USB2.0 (P2) USB2.0 (P0~P1,P4) USB2.0 (P0~P7) LAN RTL8100S PG 25 CARDBUS PC7411 PG 21,22,23 E-UM ESIGN VER : RUN POWER SW PG /TT ONNETOR TT HRGER PG PG othan ( Micro-FPG) PG, / V_SR VSUS PG PU VR PG LOKS PG R-SOIMM PG, R-SOIMM PG, MHZ R I FS MHZ lviso GM/GML PG PG,,,0, LVS TVOUT VG Panel onnector

More information

MA1 SYSTEM BLOCK DIAGRAM. Intel Dothan/Yonah Processor. 478 ufcpga. VinaFix.com P3,4. FSB 533/400MHz. Alviso-GM GMCH PCI-EXPRESS 82875GM/GME

MA1 SYSTEM BLOCK DIAGRAM. Intel Dothan/Yonah Processor. 478 ufcpga. VinaFix.com P3,4. FSB 533/400MHz. Alviso-GM GMCH PCI-EXPRESS 82875GM/GME M (.V &.VSUS ) P M SYSTEM LOK IGRM 'TL.M S ( VP.V ) S ( VG_ORE ) M ( VPU & VPU) M ( PU_ORE ) TTERY HRGER TTERY SELET ISHRGE TO Port Replicator MI IN JK P H (PT OR ST) V YV H(PT & P ST)/-ROM/US F Line-in

More information

DC/DC NVDD/+1.2V +3V/+5V +1.05V/+1.8VSUS/+1.8V/+0.9V +1.5V/+2.5V. HOST BUS 533/667 MHz. Page 12,13,14,15 INT_LVDS INT_TVOUT INT_VGA +2.

DC/DC NVDD/+1.2V +3V/+5V +1.05V/+1.8VSUS/+1.8V/+0.9V +1.5V/+2.5V. HOST BUS 533/667 MHz. Page 12,13,14,15 INT_LVDS INT_TVOUT INT_VGA +2. INT@:UM XT@:iscrete V@:M VRM V@:M VRM G@:LN 0 G@:LN G@:LN 0 0.V 0.VSUS.VSUS R-SOIMM Page 0, R-SOIMM Page 0, Parallel-H Page L (odec) & MP Page 0 Multi-ay Head phone Page Internal-MI Page LIN-IN Page Page

More information

SVT-2 REV : 3C

SVT-2 REV : 3C / ( VRM & VR0 ) MX0 P / ( VRM ) MXETG P / ( VRM & V0R ) MX & F P / ( VM & VM ) MX0ETU PU ORE ( VPUORE ) ISL HRGER MXETI TSURUMI KVT P P P0 ( V & V & VR & VR ) P R II SOIMM0 R II SOIMM VR R_VREF V0R P,0

More information

ZH2 Block Diagram. Yonah/Merom INTEL Mobile_479 CPU. Page : 3,4. HOST BUS 533/667 MHz SDVO CALISTOGA-GM 1466 FCBGA TVOUT RGB. Page : 6 ~ 11 DMI I/F

ZH2 Block Diagram. Yonah/Merom INTEL Mobile_479 CPU. Page : 3,4. HOST BUS 533/667 MHz SDVO CALISTOGA-GM 1466 FCBGA TVOUT RGB. Page : 6 ~ 11 DMI I/F LOK GEN IS0G V /.V / 0V Page :.V / 0.V /.V Page :.V /.0V Page : Page : Page : Page : PU ORE TTERY HRGER HOST MHz/MHz PI-E 00MHz VG MHz US MHz PI MHz REF MHz VPU V_PU V_S V_S VSUS VSUS V V 0V.VSUS.V 0.VSUS

More information

ZC1 SYSTEM BLOCK DIAGRAM. Yonah/Merom 479 ufcpga

ZC1 SYSTEM BLOCK DIAGRAM. Yonah/Merom 479 ufcpga TVOUT TFT L Panel." WSXG+ X'TL M VI RT luetooth US US P P P P P amera Module(.M) P in ardreader (SMS ) P US US Port x US0~ P VI TVout LVS VG Media-ay O/nd H/nd attery P X'TL.MHZ lock Generator H IS0GLF

More information

REVISION HISTORY DESCRIPTION INITIAL SCHEMATIC AIY REMOVED ANALOG SWITCHES CHANGED FEEDBACK

REVISION HISTORY DESCRIPTION INITIAL SCHEMATIC AIY REMOVED ANALOG SWITCHES CHANGED FEEDBACK REVISION HISTORY Notes - Unless otherwise noted. Resistances values in Ohms. apacitance values in micrarads (uf). ll 0.uF and 0.0uF capactors are decoupling and should be placed near the I they are shown

More information

Generated by Foxit PDF Creator Foxit Software For evaluation only.

Generated by Foxit PDF Creator Foxit Software   For evaluation only. I_ST I_SLK K_% R K_% R L_0 L_ L_ L_ KEY TON_STHL /F NN_ NN_ P M VS OUTL P OUTR VR MIIN VREF V HOSI LOSI R X pf LOSO.KHZ M_% pf HOSO X pf MHz HOSI 0 pf POWER Generated by Foxit PF reator Foxit Software

More information

othan RJ lock iagram PIN (micro F-PG) P,,, w, w inch XG, SXG+ / MHz VI M/M LVS L P LVS lviso GM/PM RII / UNUFFERE RII SOIMM P Hyper memory P,, R/G/ RT PIE Lanes P R/G/ PIN (micro FG) P,,, RII / UNUFFERE

More information

8V Title SCHEMATIC, 8V89317EVB REV A. Date: Friday, June 14, Power Supply. XTAL Interface. 12.8MHz TCXO/OCXO LED Status IN1 OUT1

8V Title SCHEMATIC, 8V89317EVB REV A. Date: Friday, June 14, Power Supply. XTAL Interface. 12.8MHz TCXO/OCXO LED Status IN1 OUT1 isclaimer: IT is providing this schematic for reference purposes only. lthough the schematic was taken from a known working design, it is being provided "as is" without any express or implied warranty

More information

PCB NO. DM205A SOM-128-EX VER:0.6

PCB NO. DM205A SOM-128-EX VER:0.6 V. M0 M M M M M M M MQM0 MQS0N MQS0P M M M0 M M M M M MQM MQSN MQSP U RM R0 Q00 M0 U Q0 M T Q0 M R Q0 M U Q0 M U Q0 M T Q0 M T Q0 M T M0 M U QS0N M U QS0P M0 M W0 Q0 M W Q0 M V0 Q0 M U0 Q M W Q W Q 0 V

More information

REV MODEL CHANGE LIST FIRST RELEASE

REV MODEL CHANGE LIST FIRST RELEASE MOEL NT M/ REV FIRST RELESE HNGE LIST PGE: hange OREVTT power good circuit for ORE V Sequence. PGE,: dd PU PROHOT IRUT (Throttle) at battery only. PGE: ecause system.v will change to.v for support.v VRM

More information

CONTENTS: REVISION HISTORY: NOTES:

CONTENTS: REVISION HISTORY: NOTES: ONTENTS: PGE - ONTENTS PGE - POWER, XOS PGE - SI, SI, JTG PGE - S/eMM, US, HMI, GPIO, OMPOSITE PGE - SOIMM REVISION HISTORY: V.0 - /0/0 NOTES: These reduced schematics omit core SMPS and LPR circuitry

More information

INDEX/ RESET& EEPROM JINPIN ELECTRICAL COMPANY LTD.ZHUHAI.S.E.Z SF_CE SF_SO SF_CLK SF_SI SF_CE SF_SO SF_CLK SF_SI PC_SCL PC_SDA SCL SDA RST

INDEX/ RESET& EEPROM JINPIN ELECTRICAL COMPANY LTD.ZHUHAI.S.E.Z SF_CE SF_SO SF_CLK SF_SI SF_CE SF_SO SF_CLK SF_SI PC_SCL PC_SDA SCL SDA RST N Updata /N P. R.K R 00 R 00 R.K P_SL P_S V R K SF_E U PMVF00 E SO WP VSS V HOL SK SI SF_LK V 0.UF/V SF_E SF_LK P_SL P_S SL S V SL' S' SF_E SF_LK P_SL P_S SL S V SL' S' U T 0 V WP SL S SL' S' 0.UF/V R

More information

CD-DET TP5_CS- LCDPWR RFPWR CHPD5 GP05 GP25 RST5 L13 D12 D11 D10 LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS- LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS-

CD-DET TP5_CS- LCDPWR RFPWR CHPD5 GP05 GP25 RST5 L13 D12 D11 D10 LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS- LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS- SPST SW L 0uH.uF TP HEER NO STUFF TP 0 HEER NO STUFF TP TP pf Y.uF.uF 0 HEER NO STUFF 0 HEER NO STUFF MHz, 0ppm pf.uf (OUT) (IN) R 0K /W % 0uF OUT OUT OUT OUT KLT L 0 L_MISO L_MOSI L_SK S_S- L_S- L_- L_

More information

RSC CHIP VDD P05 P03 P01 P04 VDD GND PWM0 AVDD VDD AVDD P0-2 P0-5 P0-1 P0-6 P0-4 P0.3 GND P00. Y1 3.58MHz P00 P01 AGND P01 P00 P02 P02 P07 P0-0 P0-7

RSC CHIP VDD P05 P03 P01 P04 VDD GND PWM0 AVDD VDD AVDD P0-2 P0-5 P0-1 P0-6 P0-4 P0.3 GND P00. Y1 3.58MHz P00 P01 AGND P01 P00 P02 P02 P07 P0-0 P0-7 Place as close to pins of U as possible. RS HIP 0-00 RS-x emo/evaluation oard: RS-000 Thursday, ecember, 00 Size ocument Number Rev ate: Sheet of P XI P0 P0 P0 P0 P00 PN P0 P0 P0 P0 P0 P0 P0 P0 P XO -XM

More information

SHELBY-INTEGRATED CLOCKS ICS PG 17. sdvo SI1362 PG 18 USB2.0 (P5,P6) USB2.0 (P3,P4) USB2.0 (P7) 1394 CONN PG 25 USB2.

SHELBY-INTEGRATED CLOCKS ICS PG 17. sdvo SI1362 PG 18 USB2.0 (P5,P6) USB2.0 (P3,P4) USB2.0 (P7) 1394 CONN PG 25 USB2. IMVP- PU VR PG RUN POWER SW PG UIO ST00 PG, / +V_SR +VSUS PG /TT ONNETOR TT SELETOR TT HRGER POWER / R-SOIMM PG, R-SOIMM PG, ST - H PG Internal Media ay -ROM PG S/PIF to OK PG udio Jacks PG RJ to OK PG

More information

L13X DAUGHTER CARDS TABLE OF CONTENTS REV SL NO. TABLE OF CONTENTS VERSION VERSION HISTORY BLOCK DIAGRAM 4 UART-0 INTERFACE

L13X DAUGHTER CARDS TABLE OF CONTENTS REV SL NO. TABLE OF CONTENTS VERSION VERSION HISTORY BLOCK DIAGRAM 4 UART-0 INTERFACE LX UGHTER RS TLE OF ONTENTS SL NO. ONTENTS PGE NO REV TLE OF ONTENTS VERSION HISTORY VERSION.0.. LOK IGRM URT-0 INTERFE N US INTERFE URT INTERFE PROFI US & SOFT IR INTERFE SOFT URTS REV NO. NTURE OF HNGE

More information

SIT REV : 3A

SIT REV : 3A Inverter"WXG VIN(V): W.V: W Power / converter Page 0~ lcok Gen. K0-M PU IS0 / P-M(othan)/eleron IS0 Page / Page V lock iagram SIT RV : 00-0- SVIO Page RT Page lviso-gm R /00 Page //// Page /0 WLN Mini-PI

More information

SVT REV : 3B

SVT REV : 3B Inverter"WXG VIN(V): W.V: W Power / converter Page 0~ lcok Gen. K0-M PU IS0 / P-M(othan)/eleron IS0 Page / Page V lock iagram SVT RV : 00-0- SVIO Page RT Page lviso-gm R /00 Page //// Page /0 WLN Mini-PI

More information

#1 10P/DIL NORTH #3 #3 #3 #3 #3 #3 #3 #3 R198 RES0603 RES0603 DNP DNP DNP RES0603 RES0603 RES SDI_N 3-SDO_N 3-ALERT_N 3-CS_N 3-SCLK_N 3-CONV_N

#1 10P/DIL NORTH #3 #3 #3 #3 #3 #3 #3 #3 R198 RES0603 RES0603 DNP DNP DNP RES0603 RES0603 RES SDI_N 3-SDO_N 3-ALERT_N 3-CS_N 3-SCLK_N 3-CONV_N P REVISION REOR J SP88 0 - RE N_JK P 90-00_-POS TP # - Remove these components to stack north # - Populate these components to stack north Use k Resistors or adjust as needed Header - Molex 90-0 PITORS,

More information

J1B B1 B3 B5 B7 B9 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B35 B37 B39 B41 B43 B45 B47 B49 B51 B53 B55 B57 VCC VCC USB_DET

J1B B1 B3 B5 B7 B9 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B35 B37 B39 B41 B43 B45 B47 B49 B51 B53 B55 B57 VCC VCC USB_DET GP0 GP0 GP0 P0 GP0 GP GP GP GP GP GP GP P GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP00 UINO ONE PIN EFINE GP0 GP GP GP GP GP GP GP GP0 GP GP

More information

D28 D28 1N4001 1N4001 R301 R375 R k. 10k R82 R82. 47k. 47k USB_IN. 20k. 20k R87 R87 +3V. C uF. C uF GND +1V8. C uF.

D28 D28 1N4001 1N4001 R301 R375 R k. 10k R82 R82. 47k. 47k USB_IN. 20k. 20k R87 R87 +3V. C uF. C uF GND +1V8. C uF. POWER_KEY POWER_OFF US_IN WKEUP H_ET HG_STTUS PLYKEY +VRT VT VUS +VRT LI_.V LI_.V VUS VT VTT VTT VTT +V +V +V +V VTT V +V T uf uf R k R k uf uf R k R k VIN VOUT U XPM U XPM Vbat ON ON ON ON KW ON/OFF KW

More information

Realtek Semiconductor Corp. Title RTL8213(M)_FHG_V1.0

Realtek Semiconductor Corp. Title RTL8213(M)_FHG_V1.0 Fiber LE RJ M RYSTL EEPROM SRM & FLSH POWER PWRJK Jumper for GPIOs URT Realtek Semiconductor orp. RTL(M)_FHG_V.0 Size ocument Number Rev lock diagram.0 ate: Tuesday, November, 00 Sheet of ,, /ISGPIOSTP

More information

R2 44.2K_1% 5DVCC 5DVCC GND COMP SS24 DW1. EC2 470uF/16V. 470uF/16V 内内内内内内 DW2; 去去 U103,L9 33V. 33V C15 NC/10uF 33V C17 D2 NC/UDZ33B-33V

R2 44.2K_1% 5DVCC 5DVCC GND COMP SS24 DW1. EC2 470uF/16V. 470uF/16V 内内内内内内 DW2; 去去 U103,L9 33V. 33V C15 NC/10uF 33V C17 D2 NC/UDZ33B-33V JK_P JP V V L 0u/N F FUSE() FUSE E 0uF/V E. V L 0u/N V 00nF 00nF V, R 00K 00nF U MP IN EN SS OMP 0nF S SW F 0.nF R K SW L u R.K_% R 0K_% V E 0uF/V V,,, ST-V V 00nF.uF 00P SS W ST-V E 0uF/V E 00nF TO U

More information

P STK UP LYER : TOP LS lock iagram LYER : S LYER : IN LYER : IN LYER : V LYER : OT V_ORE +.V +.V +.V +.VSUS +VPU +V_S +VSUS +V +VPU +V_S +V SMR_VTERM SMR_VREF HMI Page TV-OUT Page RT Page L(WXG+.W) Page

More information

2.5V 1.2V / 1.5V CORE 3.3V I/O MOUNTING HOLES GROUND TESTPOINTS +5.0V DC IN. SoC Solutions FB2 R K C12 15 PF FERRITE_BEAD C14 C C13 2.

2.5V 1.2V / 1.5V CORE 3.3V I/O MOUNTING HOLES GROUND TESTPOINTS +5.0V DC IN. SoC Solutions FB2 R K C12 15 PF FERRITE_BEAD C14 C C13 2. +.0V IN J PJ-0 _ONN VUS JP JUMPERT VUS_FP 00 F FERRITE_E..V U TPS0 GN F TGN PF R.K % VP. R K %.V /.V ORE.V I/O U TPS0 JP VP JP HR VP_GL U TPS0 R.K LM0EM -. JP HR VORE_GL VORE. GN F TGN 0 PF R.K % R K %.

More information

1 INDEX & POWER, RESET 2 RF, SERVO & MPEG - MT1389E 3 MEMORY - SDRAM, FLASH/EEPROM 4 VIDEO OUT 5 AUDIO DAC WMA8766

1 INDEX & POWER, RESET 2 RF, SERVO & MPEG - MT1389E 3 MEMORY - SDRAM, FLASH/EEPROM 4 VIDEO OUT 5 AUDIO DAC WMA8766 OMMON_H_V MT (LQFP) V emo oard for Sanyo Slim H PUH INX & PO, ST F, SVO & MPG - MT MMOY - SM, FLSH/POM VIO OUT UIO WM NM TYP VI igital V SUPPLY V igital.v MT FV Servo.V MT LO_V Laser iode.v F V PIKUP H

More information

AD2_BUSY AD2_DIN AD2_DOUT AD2_/CS AD1_/CS AD1_DOUT AD1_DIN AD_SCLK AD_CCLK AD_OSC_EN AD1_BUSY AD_CONVERT GNDIO - P115

AD2_BUSY AD2_DIN AD2_DOUT AD2_/CS AD1_/CS AD1_DOUT AD1_DIN AD_SCLK AD_CCLK AD_OSC_EN AD1_BUSY AD_CONVERT GNDIO - P115 PL ENOER OUNTER / PWM MOTOR ONTROL / GLUE LOGI PL YPSS PITORS LE0 LE LE LE ESTOP_U ESTOP_IRQ _USY _IN _OUT _/S _/S _OUT _IN _SLK 0.uF +.V 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF P0.[0:] [0:] 0 P0. P0. P0. P0.

More information

Quanta Computer Inc. REV 3A PROJECT : ZO1 COVER SHEET 1 OF 1 PROJECT LEADER: JIM HSU DOCUMENT NO: 204 DATE :2007/04/14 MB ASSY'S P/N : 31Z01MB00XX

Quanta Computer Inc. REV 3A PROJECT : ZO1 COVER SHEET 1 OF 1 PROJECT LEADER: JIM HSU DOCUMENT NO: 204 DATE :2007/04/14 MB ASSY'S P/N : 31Z01MB00XX MOEL: Z0 Motheroard REV: HNGE LIST: FIRST RELESE PGE0.. R,, MOIFY to EP P/N:SF PGE0.. STUFF HOLE P/N:FZ00000,. STUFF HOLE,, P/N:FE000,. STUFF HOLE P/N:FZ00000 PGE0.. STUFF HOLE, P/N:FZ00000,. STUFF HOLE

More information

CLKOUT CLKOUT VCC CLKOUT RESOUT OSCOUT ALE TEST AD0 66 AD2 INT0 INT0 AD INT1 AD INT2/INTA0 AD5 AD7 AD7 INT AD8 AD8 AD10

CLKOUT CLKOUT VCC CLKOUT RESOUT OSCOUT ALE TEST AD0 66 AD2 INT0 INT0 AD INT1 AD INT2/INTA0 AD5 AD7 AD7 INT AD8 AD8 AD10 I U N R 00K RSIN* RST S N.0u Y LK TP RP K L TP USY INT0 INT RISMINT P.0 P. P. P. P. P. P. RY OL RX0 TX0 T P.0 P. P. P. S* S* S* S* RROR* SLK U LKIN LKOUT LKOUT LKIN LKOUT OSOUT 0 OSOUT L L RSIN* L 0 0

More information

HIgh Voltage chip Analysis Circuit (HIVAC)

HIgh Voltage chip Analysis Circuit (HIVAC) ate: esigner: RWING NO: SLE: SHEET: OF TOP MK HIgh Voltage chip nalysis ircuit (HIV) March H_I_RSEL H_I_RSEL H_I_SEL H_I_ H_I_ H_I_ H_I_SEL H_I_SW H_I_S H_I_S H_I_S H_I_P H_I_P H_I_P H_I_P H_I_PSH H_I_PSL

More information

Power. Video out. LGDC Subsystem

Power. Video out. LGDC Subsystem Power LE_UX# LG Evaluation System: Mainboard Revision: P Reference I: 00 # Video out LG Subsystem _N[..0] SM[..0] I[..0] LE_UX# _N[..0] SM[..0] I[..0] LE_UX# _N[..0] SM[..0] I/O ISP_LK I[..0] ISP_[..0]

More information

B0549-SCH-01 RD VEGA STDP4028 (DVI to DPTx) Reference Design PCB# Revision History

B0549-SCH-01 RD VEGA STDP4028 (DVI to DPTx) Reference Design PCB# Revision History 0-SH-0 R-0 VEG STP0 (VI to PTx) Reference esign P# 00- Revision History SHEMTI SHEET ate uthor Version omments 0. ontents, Revision History Sept., 00 Tony W. Rev. Initial schematic. 0. Overview Oct., 00

More information

AS1117M3 or LM1117MPX-ADJ REG_VDD ADJ. C20 0.1uF U6. + C57 10uF R K 1% GND 3.92K 1%

AS1117M3 or LM1117MPX-ADJ REG_VDD ADJ. C20 0.1uF U6. + C57 10uF R K 1% GND 3.92K 1% K POWER SW JP EXTERNL POWER FUSE 0. uf VT + 0 uf SM or LMMPX-J REG_V VIN VOUT + 0uF 0 0.uF U R 0.0K % J R.K % REG_V J PV PV_US_TGT V_M0X POWER_SELET R0 0Ohm V to V ENTER POSITIVE.

More information

KEIm Baseboard. PAGE DESCRIPTION 1 Block Diagram, History 2 SoM Connector. 3 LCD Connector. 4 Ethernet. 5 UART 6 Analog 7 Peripheral 8 Power

KEIm Baseboard. PAGE DESCRIPTION 1 Block Diagram, History 2 SoM Connector. 3 LCD Connector. 4 Ethernet. 5 UART 6 Analog 7 Peripheral 8 Power KEIm aseboard REV TE PGES ESRIPTION.0.0 Oct//0 ll INITIL REVISION RELESE..0 Feb//0 ll MP REVISION RELESE PGE ESRIPTION lock iagram, History SoM onnector L onnector Ethernet URT nalog Peripheral Power KONO

More information

All use SMD component if possible

All use SMD component if possible R0 0K MF SW0 NEXT R0 0R LE0 STNY & POWER ON GN R0 SW0 PREV R 0 MF R 0 MF R 0K MF R0 K MF SW0 FF GN SNP OFF OR GN Q0 S Q0 S LE R k R k 00n R 0K MF M0 R0 K MF SW0 FR +V() Q0 R 0K MF GN R0 0 R 0 GN VF_on_off

More information

HF SuperPacker Pro 100W Amp Version 3

HF SuperPacker Pro 100W Amp Version 3 HF SuperPacker Pro 00W mp Version Revised 0 0 V Stamps KOOR This is the third generation HF SuperPacker Pro 00W Version home construction project offered by HF Projects. This is a group construction project

More information

DAC PLAY0 PLAY0 CT7601 DAC REC ADC REC RCA * 2. Power LDO RCA. RCA * 2 SPDIF output x2 RCA RCA RCA. Ext. MCU POR. PWM LED x 2. SPDIF input x 1.

DAC PLAY0 PLAY0 CT7601 DAC REC ADC REC RCA * 2. Power LDO RCA. RCA * 2 SPDIF output x2 RCA RCA RCA. Ext. MCU POR. PWM LED x 2. SPDIF input x 1. R * SPIF output x Power LO R * R R SPIF input x POR Flash PWM LE x PM00 Lightning() P 0x0 0pin Type connector US 0pin For Lightning & P T0 RE PLY0 PLY H Sel Stereo T0 PLY0 T0 0x PLY 0x PM00 R Ext. MU H

More information

AS1117M3 or LM1117MPX-ADJ ADJ. C20 0.1uF + C56. + C57 10uF. 10 uf R K 1% R18 GND 10.0K 1%

AS1117M3 or LM1117MPX-ADJ ADJ. C20 0.1uF + C56. + C57 10uF. 10 uf R K 1% R18 GND 10.0K 1% K POWER SW JP EXTERNL POWER FUSE 0. uf VT 0 uf R SM or LMMPX-J VIN VOUT U 0.0K % J R.K % 0uF REG_V 0 0.uF REG_V J PV PV_US_TGT V_M0X POWER_SELET R0 0Ohm V to V ENTER POSITIVE.

More information

CPU Thermal Sensor GMT781-1 EXT.CLOCK GEN ICS954226AG-T. 533 MHZ Memory Dual channel DDR II CHANNEL A DDR II CHANNEL B 1X PCI-E<PORT1> 2.

CPU Thermal Sensor GMT781-1 EXT.CLOCK GEN ICS954226AG-T. 533 MHZ Memory Dual channel DDR II CHANNEL A DDR II CHANNEL B 1X PCI-E<PORT1> 2. NRL lok IGRM PU YONH/MERON eleron u-fpg PIN PU Thermal Sensor GMT- EXT.LOK GEN ISG-T attery In / & harge FS RT x -SU -Pin L " Square XG RT Hx LVS MHZ N LISTOG GML R II HNNEL R II HNNEL MHZ MHZ Memory ual

More information

H-LCD700 Service Manual

H-LCD700 Service Manual H-L00 Service Manual FULT ESIPTION: SOUN onfirm the volume isn t in silent mode before check. heck I0 () plug has audio output or not Speaker damaged heck I0 has supply V or not heck power heck I0 () plug

More information

core Tiny6410.sch DM9000 DM9000-etc.sch AC97 AC97-etc.sch USB HUB USB-HUB.sch Tiny6410SDK 1103

core Tiny6410.sch DM9000 DM9000-etc.sch AC97 AC97-etc.sch USB HUB USB-HUB.sch Tiny6410SDK 1103 core Tiny0.sch M000 M000-etc.sch -etc.sch US HU US-HU.sch Tiny0SK 0 M_ VV V V V V V V V V V VN VSYN VLK VUS OTGI OTGM OTGP IN0 S_LK S_n S_T0 S_T OUT0 INT INT INT RST ( 红色 ) Tiny0 Tiny0 P Power Supply S

More information

Intel ECX Form Factor POC Board Based on Intel 915GM Chipset

Intel ECX Form Factor POC Board Based on Intel 915GM Chipset Intel EX Form Factor PO oard ased on Intel GM hipset TITLE OVER SHEET LOK IGRM PU K- LOK SYNTHESIZER INTEL GM GMH R SO-IMM INTEL FM IH-M IH IE,F,US,FP LVS,ST,FWH,PS/ LN(INTEL QM/ER) SUPER I/O(WHF),F,IO

More information

P STK UP LYER : TOP LYER : SGN LYER : IN PU ORE ISL Li / lock iagram PU Penryn PU THERML SENSOR.MHz 0 LYER : IN LYER : V LYER : OT P (upg)/w LK_PU_LK,LK_PU_LK# LK_MH_LK,LK_MH_LK# REFLK,REFLK# REFSSLK,REFSSLK#

More information

HOSCO HOSCI AS M AS M C1 18P C2 18P C1 18P C2 18P GND VCC3 GPIOK7 R82 R82 10K A20 10K. #OffHook. FmHook #TRANSLED. VxBP 0.1U 0.

HOSCO HOSCI AS M AS M C1 18P C2 18P C1 18P C2 18P GND VCC3 GPIOK7 R82 R82 10K A20 10K. #OffHook. FmHook #TRANSLED. VxBP 0.1U 0. 0 #E0 GPIOK #MWR #MR #FWE HOSI KEYI0 GPIO0 HOSO V V VREFI KEYI GPIO GPIO_ V KEYO GPIO #E OUTR MIIN VMI GPIO_0 #LON V #HOL 0 0 #E KEYO GPIO 0 KEYO0 GPIO GPIO_ GPIO_0 #MR #MWR V V V V TSEL #E #E0 V HOSI

More information

Power. I/O Extensions. CPU Extensions. JADE-D Subsystem

Power. I/O Extensions. CPU Extensions. JADE-D Subsystem XXSvideo- Revision: P. Power WI V_ORE_PG WI V_ORE_PG Reference I: 00 # WI PU Extensions HOST_SPI[..0] SPI_0[..0] PU_[..] PU_[..0] MEM_TRL[..0] MEM_RY VIN0_[..0] HOST_SPI[..0] S PI_0[..0] PU_[..] PU_[..0]

More information

Quickfilter Development Board, QF4A512 - DK

Quickfilter Development Board, QF4A512 - DK Quickfilter evelopment oard, QF - K nalog Inputs - U +.V +.V J N hannel J N hannel J N hannel J N hannel U +.V +.V U +.V U +.V Prototyping rea J J Optional +V External Power x Header 0." US onnector U

More information

VER : 3A. Thermal Sensor & Fan P37 LVDS. E-switch PI2PCIE412-DZHE LVDS MXM III-NB8E (GT/SE/GLM) VRAM 256M VRAM 512M P18 HDMI HDMI P19 P17 SPDIF_MXM

VER : 3A. Thermal Sensor & Fan P37 LVDS. E-switch PI2PCIE412-DZHE LVDS MXM III-NB8E (GT/SE/GLM) VRAM 256M VRAM 512M P18 HDMI HDMI P19 P17 SPDIF_MXM Module Y Mini PI (for ebug) P H / O (ST) P P X'TL.MHz LOK GENERTOR YLFXT RII SO-IMM RII SO-IMM P H (ST) P H / O (PT) P P in ard Reader ontroller R P,P in ard Reader connector P ST ST PT PI us MX(Maddog.)

More information

DISPLAY 1 DISPLAY 2 a. a b. a f. a f. b g. c d. c d. 16 x 2 HD44780 BASED ALPHANUMERIC DISPLAY LCD 16 X 2

DISPLAY 1 DISPLAY 2 a. a b. a f. a f. b g. c d. c d. 16 x 2 HD44780 BASED ALPHANUMERIC DISPLAY LCD 16 X 2 SEGMENT LE ISPLY R MUX MUX MUX MUX R nf SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ U R xt P P P P P P P P MX MX ss SL S P P P P P P P P nf S SEG_SL SEG_S SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_I_SL_

More information

PTN3356 Evaluation and Applicaiton Board Rev. 0.10

PTN3356 Evaluation and Applicaiton Board Rev. 0.10 E PTN Evaluation and pplicaiton oard Rev. 0.0 REVISION STORY : ------------------------------------- 0. June 0, 0 - ase on PTN_ONLY_REV.SN 0. July, 0 - OM changes due to long lead time items, LEs 0. July,

More information

NV11,4Mx16 DDR, RGB, INTERNAL DVI-I, AGP.

NV11,4Mx16 DDR, RGB, INTERNAL DVI-I, AGP. . NV.V 00PF 00PF 00PF 0.UF 0.UF 0.UF 0.UF 0UF 0UF 0 0.UF 0.UF.V TO- -pin package Semtech Z, Unisem US0 00 NV O- RG-PWR-IN.V@ /- 0mV 0UF 00PF 00PF 0 00PF 0UF 00PF 0UF 0 0.UF 0 00PF 0.UF 0 O0 U POWR SNS

More information

Project: Date. Version. Items V1.01 C C. SIM Technology TITLE DRAWN BY PORJECT. SIM800C+SIM28M_VTS Reference CONTENT VER CHECKED BY SIZE V1.

Project: Date. Version. Items V1.01 C C. SIM Technology TITLE DRAWN BY PORJECT. SIM800C+SIM28M_VTS Reference CONTENT VER CHECKED BY SIZE V1. Project: ate Version Items V.0 RWN Y PORJET SIM800+SIM8M_VTS Reference ONTENT HEKE Y V.0 SHEET of 7 POWER POWER -0V F0 0 L0 VIN LO X0 SM0 SWRH07 uh T-PIN-X TVS0 Z0 + 0 VT U0 VZ=V,Pd=W SM7 00uF V GN VOUT

More information

A[0..14] A[0..15] D[0..7] A[0..15] D[0..7] D[0..7] R/W I/O Phi0 MAP R/W R/W. I/O Phi0 MAP. Phi0 MAP. ROMDIS Phi2. ROMDIS Phi2. Id: 1/

A[0..14] A[0..15] D[0..7] A[0..15] D[0..7] D[0..7] R/W I/O Phi0 MAP R/W R/W. I/O Phi0 MAP. Phi0 MAP. ROMDIS Phi2. ROMDIS Phi2. Id: 1/ Power power.sch udio SOUN_OUT audio.sch Phi P[0..] P[0..] Phi P[0..] P[0..] PU Phi P[0..] P[0..] [0..] [0..] I/O MP ROMIS Phi [0..] [0..] I/O MP ROMIS Phi UL [0..] [0..] VI_S MP ula.sch LUE RE SYN M[0..]

More information

Design Overview. Page 2 Power,Flash,SDcard User switch,reset switch. Page 3 Ethernet. Page 4 Audio. Page 5 USB. Page 6 JTAG,BOOTSW,LED,Header

Design Overview. Page 2 Power,Flash,SDcard User switch,reset switch. Page 3 Ethernet. Page 4 Audio. Page 5 USB. Page 6 JTAG,BOOTSW,LED,Header esign Overview Page Power,Flash,Scard User switch,reset switch. Page Ethernet Page udio Page US Page JTG,OOTSW,LE,Header isclaimer: Schematic's are for reference only. provides no warranty for the use

More information

COVER PAGE, TOP 04 ~ 05 VGA, LED, 7SEGMENT

COVER PAGE, TOP 04 ~ 05 VGA, LED, 7SEGMENT LTER YLONE III EP evelopment & Education OR SHEMTI ONTENT PGE TOP MEMORY OVER PGE, TOP SRM,FLSH 0 ~ 0 0 ~ 0 ISPLY VG, LE, SEGMENT 0 ~ 0 IN/OUT LOK, PS, RS, UTTON, SWITH, ONNETOR,S R 0 ~ FPG yclone II EP

More information

A L A BA M A L A W R E V IE W

A L A BA M A L A W R E V IE W A L A BA M A L A W R E V IE W Volume 52 Fall 2000 Number 1 B E F O R E D I S A B I L I T Y C I V I L R I G HT S : C I V I L W A R P E N S I O N S A N D TH E P O L I T I C S O F D I S A B I L I T Y I N

More information

PA1A BLOCK DIAGRAM NWD/PRESCOTT / SPRINGDALE

PA1A BLOCK DIAGRAM NWD/PRESCOTT / SPRINGDALE P LOK IGRM NW/PRSOTT / SPRINGL /TT ONNTOR TT HRGR PG PG NW/PRSOTT Pins (Micro-FPG) PU Thermal Sensor PG locking K PG PU OR ISL PG, / MX PG PG R-SOIMM R-SOIMM Primary Master I - H PG HNNL R SRM.V, MHz.

More information

PLAY0 CT7601 QFN48 REC ADC REC. Power LDO RCA RCA RCA*2. Ext. MCU RCA*2. SPDIF output. PWM LED x 2 POR. SPDIF input x 1 Flash. connector.

PLAY0 CT7601 QFN48 REC ADC REC. Power LDO RCA RCA RCA*2. Ext. MCU RCA*2. SPDIF output. PWM LED x 2 POR. SPDIF input x 1 Flash. connector. R SPIF output Power LO R SPIF input x Flash POR PWM LE x R* Lightning() P x pin Type connector US pin For Lightning & P T QFN RE PLY H Sel T PLY x PM Ext. MU H Sel T RE x S NE OP R* Size ocument

More information

XIO2213ZAY REFERENCE DESIGN

XIO2213ZAY REFERENCE DESIGN XIOZY REFERENE ESIGN XIOZY Reference Size ocument Number Rev ate: Wednesday, September, 00 Sheet of TP+ TP- TP+ TP- TPIS TP+ TP- TP+ TP- TPIS TP0+ TP0- TP0+ TP0- TPIS0 REFLK+ REFLK- V_ V_ V_ORE PLLV_ORE

More information

POWER Size Document Number Rev Date: Friday, December 13, 2002

POWER Size Document Number Rev Date: Friday, December 13, 2002 R0 [ /W 0 0.00uF/00V - D0 KP0M L0 L D0 N 0 00uF/00V 0 0.uF R0 M [ /W R0 M [ /W R0 M [ /W R0 M [ /W 0 0.00uF/KV D0 PS0R 0 0uF R0 00K [ W D0 FR0 R0 0 [ /W O O T0 O,, POWER X'FMR 0, D0 DQ0 R [ /W 0.00uF/00V

More information

VF-co-cc. F3Jr CPU CLOCK GEN. ATI M64-M or M76-M NORTH DDR2 SO-DIMM0 BRIDGE DDR2 SO-DIMM1 TPM 1.2 INFINEON SLB9635 SOUTH BRIDGE EC ITE IT8510E

VF-co-cc. F3Jr CPU CLOCK GEN. ATI M64-M or M76-M NORTH DDR2 SO-DIMM0 BRIDGE DDR2 SO-DIMM1 TPM 1.2 INFINEON SLB9635 SOUTH BRIDGE EC ITE IT8510E 0 0 0 0 0 0 0 lock iagram ystem etting * PU-YONH(HOT) PU-YONH(PWR) * N-PM(HOT) * U ONN * I ROM * LE * R Mx x Option PU YONH MEROM W W LOK EN I 0 FJr 0 0 0 N-PM(MI & F) N-PM(RPHI) N-PM(R) N-PM(PWR) 0 &

More information

12V SMPS_1_2 SMPS_4/5 SMPS6 VDD_CORE VDD_MPU VDD_DSP 5V0 PS_3V3 VDD_3V3 5V0 .01, C2 5V0_SNS 10.2K,1% 100uF,10V 1.91K PS_3V3 .

12V SMPS_1_2 SMPS_4/5 SMPS6 VDD_CORE VDD_MPU VDD_DSP 5V0 PS_3V3 VDD_3V3 5V0 .01, C2 5V0_SNS 10.2K,1% 100uF,10V 1.91K PS_3V3 . V.7uF,0V.LESR.7uF,0V.LESR 0.uf,V,00 R 69K U- U- U- V TO V U OOT VIN EN SS TPS.nF,0V,00 9 P PH GN 7 OMP 6 VSNS U- U-6 R SKFL-TP V0_OMP L.7uH V0_SNS V0 R 0.K,% R + 00uF,0V V0_TP V0 R.0,06 V SMPS SMPS_/ SMPS6

More information

Virtex 5 FF1136 DUT. Single Ended Socket Clocks 2X. Differential SMA MGT Clocks 2X D. Differential SMA Clocks 2X. Upstream Connector.

Virtex 5 FF1136 DUT. Single Ended Socket Clocks 2X. Differential SMA MGT Clocks 2X D. Differential SMA Clocks 2X. Upstream Connector. PGE System Monitor ux PGE System Monitor PGE System ce Upstream PGE Upstream onnector PGE Single Ended Socket locks X PGE ifferential SM locks X PGE ifferential SM MGT locks X PGE - Power us and Switches

More information

Am186CC and Am186CH POTS Line Card

Am186CC and Am186CH POTS Line Card RVISION HISTORY RV. T INITILS.0 // JSK m and mh POTS Line ard Reference esign NOT: The purpose of this design is to illustrate how to connect some of the M digital blocks together. It is not intended to

More information

M13 M14 FQP FFP VC1 VC2 VC3 MIX ATNEXPOT ADSR1 BM-VCF FAH1 FAW1 H W ATNEXPOT LFO FAH2 FAW2 H W +10VR FFP BP FQP FAH1 FAW1 FAH2 FAW2 R2 100K M15

M13 M14 FQP FFP VC1 VC2 VC3 MIX ATNEXPOT ADSR1 BM-VCF FAH1 FAW1 H W ATNEXPOT LFO FAH2 FAW2 H W +10VR FFP BP FQP FAH1 FAW1 FAH2 FAW2 R2 100K M15 MP_ MP_ MIIV JP HEE JP V0 V V V S_0 S_ S_0 S_ MIILK STTSTOP ESET SMP_ SMP_ HEE JP 0V 0V 0V 0V 0V 0V 0V 0V HEE X 000 JP9 000 MII VP VP 9 0 POTSLE POTH POTL POTSLE POTSLE POTH POTL POTSLE 9 0 HEE X 000 HEE

More information

+12V R16 100K +12V R17 100K R19 R18 100K 100K AVPP BVPP C21. C20 0.1uF. 0.1uF NOTES:

+12V R16 100K +12V R17 100K R19 R18 100K 100K AVPP BVPP C21. C20 0.1uF. 0.1uF NOTES: +V +V R 00K U S S G G SI.V +V V _VPPEN _VPPEN0 _VEN _VEN0 _VPPEN _VPPEN0 _VEN _VEN0 R0 00K R 00K + 0uF _VPPEN _VPPEN0 _VEN _VEN0 _VPPEN _VPPEN0 _VEN _VEN0 V 0.uF U VIN VPPIN VPP0 VPP V0 V VPP0 VPP V0 V

More information

+12V R17 100K +12V R18 100K R19 100K R20 100K AVPP BVPP. C21 0.1uF. C20 0.1uF NOTES:

+12V R17 100K +12V R18 100K R19 100K R20 100K AVPP BVPP. C21 0.1uF. C20 0.1uF NOTES: +V +V R 00K U S S G G SI.V +V V _VPPEN _VPPEN0 _VEN _VEN0 _VPPEN _VPPEN0 _VEN _VEN0 R 00K R 00K + 0uF _VPPEN _VPPEN0 _VEN _VEN0 _VPPEN _VPPEN0 _VEN _VEN0 V U VIN VPPIN VPP0 VPP V0 V VPP0 VPP V0 V SHN 0

More information

BL1 CELERON-M/PENTIUM-M. VF-co-cc. INTEL Mobile_479 CPU. Page:2, 3 HOST BUS 400MHZ NB RC410MB/RC410MD ATI. Page: 5, 6, 7, 8 2X PCIE.

BL1 CELERON-M/PENTIUM-M. VF-co-cc. INTEL Mobile_479 CPU. Page:2, 3 HOST BUS 400MHZ NB RC410MB/RC410MD ATI. Page: 5, 6, 7, 8 2X PCIE. PU ORE SENTEH S VPU V_S/VSUS V VSUS/V V/V.V_S MXIM MXETJ.VSUS/.V.V MXIM MXEEI.V SENTEH S*.VSUS.V GMT G Page: Page: Page: TTERY HRGER MXIM MX Page: Page:, Power State Table Power Name ontrol Signal V_ORE

More information

FREEDOM KE02Z. 1 Title 2 Block Diagram 3 KE02Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Initial Draft 02/01/13

FREEDOM KE02Z. 1 Title 2 Block Diagram 3 KE02Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Initial Draft 02/01/13 Table of ontents Title lock iagram KEZ MU OpenS INTERFE I/O Headers and Power Supply Rev X escription Initial raft Revisions. Remove Motor ontrol onnector J. Remap J, J, J, J pinout. dd one series resister

More information

QUANTA COMPUTER INC.

QUANTA COMPUTER INC. QUNT OMPUTER IN. PGE ontent PGE ontent 0 0 0 T PGE OVER T LOK IGRM NW/PS (HOST US) NW/PS (POWER/N) MH (Host bus) MH (GP bus & HU I/F) GMH (PWR & GN) GMH R- & R- IH-M(PU,PI,IE) IH-M (US,HU,LP) IH-M(POWER&GN)

More information

3V3 DECOUPLING DS90LV018A MCLKTON 4U7/10V +/-10% C196 +/-10% LCLK1IN+ NMCLKTON SK18 74LS123 MULTI +/-5% C N C94 10N

3V3 DECOUPLING DS90LV018A MCLKTON 4U7/10V +/-10% C196 +/-10% LCLK1IN+ NMCLKTON SK18 74LS123 MULTI +/-5% C N C94 10N 0 THIS RWG ONORMS TO.S. -T-0-00-0- U/0V +/-% 00N +/-0% 0N +/-0% U/0V +/-% 00N +/-0% 0 0N +/-0% R R 0R % P/0V +/-% K % U S YLLOW U 0 U U S0LV0 MLKTON /R S S R SK LS MULTI U/0V +/-% 00N +/-0% 0N +/-0% LLK+

More information

FP7 (CULV) BLOCK DIAGRAM

FP7 (CULV) BLOCK DIAGRAM FP (ULV) LOK IGRM P STK UP 0 L HI TOP GN IN IN V OT PU SU00 eleron FS /00/0 P (G) 0W PGE,, PU THERML SENSOR PGE LK_PU_LK,LK_PU_LK# LK_MH_LK,LK_MH_LK# LK_PIE_VG,LK_PIE_VG#.MHz LOK GEN RTMN-0-V-GRT PGE RIII-on

More information

176 5 t h Fl oo r. 337 P o ly me r Ma te ri al s

176 5 t h Fl oo r. 337 P o ly me r Ma te ri al s A g la di ou s F. L. 462 E l ec tr on ic D ev el op me nt A i ng er A.W.S. 371 C. A. M. A l ex an de r 236 A d mi ni st ra ti on R. H. (M rs ) A n dr ew s P. V. 326 O p ti ca l Tr an sm is si on A p ps

More information

Virtex 5 FF1760 DUT. Differential SMA Clocks 2X D. Single Ended Socket Clocks 2X. Upstream Connector. Upstream. Power Bus and Switches 5V

Virtex 5 FF1760 DUT. Differential SMA Clocks 2X D. Single Ended Socket Clocks 2X. Upstream Connector. Upstream. Power Bus and Switches 5V PGE System Monitor ux PGE System Monitor PGE System ce Upstream PGE Upstream onnector PGE Single Ended Socket locks X PGE ifferential SM locks X PGE -0 Power us and Switches V OR V JK RIK VINT VINT JK

More information

Sirius-Rx-232. Sirius-Tx-232. SIRIUS-Rx. STATUS Prog RC-5. SIRIUS-Rx. Prog RCA-5 DAB-SDA DAB-SCL STAYUS AM-SMETER POWER-ON POWER-ON CE-PLL

Sirius-Rx-232. Sirius-Tx-232. SIRIUS-Rx. STATUS Prog RC-5. SIRIUS-Rx. Prog RCA-5 DAB-SDA DAB-SCL STAYUS AM-SMETER POWER-ON POWER-ON CE-PLL UIO-OUT& U&.SH Sirius-Tx- +V-SY Sirius-Rx- -S -SL - S MU MU.SH M&M M&M.SH M ST M-SMETER E-PLL +V- +V- T-IN T-IN T-LK +V-STY +V-STY T-OUT ate: -Sep-00 Sheet of ile: :\aa\t. rawn y: RS-Tx RS-Rx R- STYUS

More information

J400 C UF,50V,20% V-STBY 10.0K,1%,1/4W R63 R61 1M,5%,1/4W V-STBY R K,1%,1/4W AC-OK RY3A R11INT 1 NC NO COM 47K,5%,1/4W R11

J400 C UF,50V,20% V-STBY 10.0K,1%,1/4W R63 R61 1M,5%,1/4W V-STBY R K,1%,1/4W AC-OK RY3A R11INT 1 NC NO COM 47K,5%,1/4W R11 MNL-PIN J MNL-PIN J MNL-PIN J MNL-PIN J J00-00 MNL-PIN J MV J MNL-PIN PHS-REF (Sh. ) IN-RET (Sh.,) -OK (Sh. ) HOT-IN 0V(US) 00V(INT) MV LIN-XFER (Sh. ) +V OOST (Sh. ) TRIM (Sh. ) MNL-PIN MNL-PIN 0V(US)

More information

A B C D TXD[15:0] TXD10 TXPAR 2.2K R38 RA12 1 RA13 AD10 +3V J98 PHY_INT HSERR R70 PRST TXPAR. ATM Physical Local Bus. Local Bus Interface.

A B C D TXD[15:0] TXD10 TXPAR 2.2K R38 RA12 1 RA13 AD10 +3V J98 PHY_INT HSERR R70 PRST TXPAR. ATM Physical Local Bus. Local Bus Interface. S J TXR0 TXR TXR TXR[:0] TXR TXR LK TX[:0] TX0 TX TX0 TX TX TX TX TX TX TX TX TX TX TX TX TX R 0K R 0K J J0 PIV R 0K TXPR R0. H/E0 H/E H/E TXLV TXSO J J HRST HLK HPERR HGNT HISEL HEVSEL HSTOP HTRY HIRY

More information

SVS 5V & 3V. isplsi_2032lv

SVS 5V & 3V. isplsi_2032lv PU 000pF 000pF 000pF 0 000pF 000pF 000pF 000pF 000pF 000pF 000pF 000pF 000pF 000pF 0 000pF 000pF 000pF 000pF 000pF 000pF 000pF FLSH.0uF.0uF.0uF 0.0uF ata uffer.0uf.0uf.0uf.0uf SVS V & V.0uF.0uF.0uF isplsi_0lv.0uf.0uf

More information

A B C D REVISIONS +3V J39 PHY_INT TXD15 TXPAR PRST AC16 AC21 AD22 AF22 AE22 AF17 AC22 AE16 AE21 AD18 AE7 AD17 AE19 AE20 AF20 AC20 A16 B13 TXD14

A B C D REVISIONS +3V J39 PHY_INT TXD15 TXPAR PRST AC16 AC21 AD22 AF22 AE22 AF17 AC22 AE16 AE21 AD18 AE7 AD17 AE19 AE20 AF20 AC20 A16 B13 TXD14 A ISIONS ZONE LTR ESRIPTION ATE APPROVE A INITIAL RELEASE --_0:0 J 0 0 0,,,, AF JP PAR [:0] ON PIV 0 SO LAV EN LK PHYS M LK STAT_A M0 M R R R R R R R 0K J J AR AR[:0] AR AR AR AR0 AR AR[:0] AR AR AR AR0

More information

PCIextend 174 User s Manual

PCIextend 174 User s Manual PIextend 7 User s Manual Preliminary M6- February Sycard Technology 8-F Miraloma Way Sunnyvale, 98 (8) 79- (8) 79- FX PIextend 7 User s Manual Page. Introduction Sycard Technology's PIextend 7 PI extender

More information

ZCRMZN00100KITG. Crimzon Development Board Kit. Product User Guide. Introduction. Kit Contents. Applying Power to Development Board

ZCRMZN00100KITG. Crimzon Development Board Kit. Product User Guide. Introduction. Kit Contents. Applying Power to Development Board ZRMZN0000KITG rimzon evelopment oard Kit PUG000-0 Product User Guide Introduction Zilog s ZRMZN0000KITG rimzon evelopment oard Kit is designed for use as a target with the rimzon In-ircuit Emulator (ZRMZNIE0ZEMG).

More information

01 TITLE PAGE 02 MCU 03 DEBUG INTERFACE 05 POWER BRIDGE 06 MOSFET DRIVERS / VI SENSING XSKEAZ128REFDES

01 TITLE PAGE 02 MCU 03 DEBUG INTERFACE 05 POWER BRIDGE 06 MOSFET DRIVERS / VI SENSING XSKEAZ128REFDES Table of ontents 0 TITLE PGE 0 MU 0 EUG INTERFE 0 SUPPLY 0 POWER RIGE 0 MOSFET RIVERS / VI SENSING utomotive Product Group 0 William annon rive West ustin, T 9 esigner:. ZUZEK rawn by:. ZUZEK pproved:

More information

OTG_FS_VBUS OTG_FS_N OTG_FS_P OTG_FS_ID OTG_FS_OC OTG_FS_PWR OTG_FS_VBUS OTG_FS_N OTG_FS_P OTG_FS_ID OTG_FS_OC OTG_FS_PWR OLLO_SLEEP OLLO_SLEEP

OTG_FS_VBUS OTG_FS_N OTG_FS_P OTG_FS_ID OTG_FS_OC OTG_FS_PWR OTG_FS_VBUS OTG_FS_N OTG_FS_P OTG_FS_ID OTG_FS_OC OTG_FS_PWR OLLO_SLEEP OLLO_SLEEP MU ROOTIS / ORO MU_NRESET R_[0..] R_[0..] R_ R_ R_ R_ R_ R_0 R_0 R_ R_ R_ R_ R_ R_ OTG_S_VUS OTG_S_N OTG_S_P OTG_S_I OTG_S_O OTG_S_PWR OTG_S_I OTG_S_N OTG_S_P OTG_S_O OTG_S_VUS UT_USER UT_USER SW_USER

More information

TE1 Block Diagram. Intel. Merom (35W) FSB(667/800MHZ) Page 18 CRT. PCI-E 16X Lan. Crestline GM 533/ 667 MHZ DDR II. Page 5,7,8,9,10,11.

TE1 Block Diagram. Intel. Merom (35W) FSB(667/800MHZ) Page 18 CRT. PCI-E 16X Lan. Crestline GM 533/ 667 MHZ DDR II. Page 5,7,8,9,10,11. P STK UP TE lock iagram LYER : TOP LYER : S LYER : IN LYER : V LYER : IN LYER : IN LYER : S LYER : OT V_ORE HMI Page LE PNEL Page HMI RT Page 0 Transmitter Sil Page L PNEL Page LE river I Page zalia SVO

More information

ZG5 NB Block Diagram

ZG5 NB Block Diagram VTERM(+0.V) VTT(+.0V) +.VSUS +.V +.VSUS +.V +.V VPU +.V +.VSUS L_.V L_V +V RT P." panel P LVS ZG N lock iagram iamondville VORE:+. ~ +0. VP:+.0V V:+.V or +.V FS GMS P, HOST P R P LVS, MI, R LK P POWER

More information

C uF T16 VDD T15 TMS TMS MCU_PORT_VDD T14 TDO TDO T13 JCOMP JCOMP PF3 T12 PF3 T11 VDDE3 5.0V PF4 T10 PF4 PJ5 PJ5 PF6 PF6 PF9 PF9 5.0V 5.

C uF T16 VDD T15 TMS TMS MCU_PORT_VDD T14 TDO TDO T13 JCOMP JCOMP PF3 T12 PF3 T11 VDDE3 5.0V PF4 T10 PF4 PJ5 PJ5 PF6 PF6 PF9 PF9 5.0V 5. Size FSM No. WG No. Rev of 9 Galen Street Floor M 0 US MP0EMO Schematic -- MU and Symbol V V P P P P P 9 P0 0 P P P P0 VE V REFYP V P PK P P P 9 P 0 P0 P P P V P P P P9 P P P0 P P 9 P 0 P P P9 P P P P

More information

Revisions. 2 Notes. 4 FXLC95000CL / MCU Circuit 5 Power and Battery Charger Circuit. KITFXLC95000EVM Drawn by:

Revisions. 2 Notes. 4 FXLC95000CL / MCU Circuit 5 Power and Battery Charger Circuit. KITFXLC95000EVM Drawn by: Table of ontents Notes lock iagram FXL000L / MU ircuit Power and attery harger ircuit Rev escription Revisions Original Release Remove signal line U- pin and add additional signal line between J-pin0 and

More information

Revisions. TWR-LCD-RGB Drawn by: Initial Release 15-JUL-11

Revisions. TWR-LCD-RGB Drawn by: Initial Release 15-JUL-11 Table of ontents Notes lock iagram isplay and Tower onnectors MU & apacitive Touch kt Rev X X escription Revisions Initial Release ate -JUL- pproved hanged Power L colours-jul- Removed J and J dded J &

More information

For max 243 R2OUT is low when R2IN is disconnected enabling the MAX 489 (RS-485) This will not work if MAX232 is used!

For max 243 R2OUT is low when R2IN is disconnected enabling the MAX 489 (RS-485) This will not work if MAX232 is used! JP RS_SELET V For max ROUT is low when RIN is disconnected enabling the MX (RS-) This will not work if MX is used! V On Front Panel -F (To Pg.) RS- RE_ RE_ RV_Y RV_Z 0.uF V U MXUK STR U- H G U MX 0 Y Z

More information

2004 Lexus LS 430 V8-4.3L (3UZ-FE) Vehicle > Powertrain Management > Diagrams > Electrical - Interactive Color (Non OE) Engine Controls - Page 1 of 7

2004 Lexus LS 430 V8-4.3L (3UZ-FE) Vehicle > Powertrain Management > Diagrams > Electrical - Interactive Color (Non OE) Engine Controls - Page 1 of 7 //0 Engine ontrols (Powertrain Management) - LLDT 00 Lexus LS 0 V-.L (UZ-E) Vehicle > Powertrain Management > Diagrams > Electrical - Interactive olor (Non OE) Engine ontrols - Page of https://my.alldata.com/repair/#/repair/article/0/component//itype//nonstandard/00

More information

PS2_B_CLOCK PS2_B_DATA PS2_A_CLOCK PS2_A_DATA UART_C_RXD UART_B_RXD UART_A_RXD UART_C_TXD UART_B_TXD UART_A_CTS UART_A_TXD UART_A_RTS GPIO[0:31]

PS2_B_CLOCK PS2_B_DATA PS2_A_CLOCK PS2_A_DATA UART_C_RXD UART_B_RXD UART_A_RXD UART_C_TXD UART_B_TXD UART_A_CTS UART_A_TXD UART_A_RTS GPIO[0:31] V. V. V. V. PI_RX URT LK URT TX PI_RX _TS_EXPHR _RX_EXPHR _RX_EXPHR Uarts URT TS URT RTS URT TX URT RX PS LOK PS T PS LOK PS T URT TX URT RX URT TX URT RX V. V. Ethernet ETH RX[0:] ETH RXV ETH RXER ETH

More information

XO2 DPHY RX Resistor Networks

XO2 DPHY RX Resistor Networks PHY_0_P_RX PHY_0_N_RX [] [] R R LP_0_P_RX HS_0_P_RX HS_0_N_RX LP_0_N_RX PHY_LK0_P_RX PHY_LK0_N_RX PHY_LK_P_RX PHY_LK_N_RX [] [] [] [] R R6 R8 R0 LP_LK0_P_RX HS_LK0_P_RX HS_LK0_N_RX LP_LK0_N_RX LP_LK_P_RX

More information

ISA INTERFACE & POWER SELECTION Size Document Number Rev Custom. XR82C684 EVAL BOARD 1.2 Date: Monday, August 13, 2007 DO NOT INSTALL CON_AT62B

ISA INTERFACE & POWER SELECTION Size Document Number Rev Custom. XR82C684 EVAL BOARD 1.2 Date: Monday, August 13, 2007 DO NOT INSTALL CON_AT62B IS_IRQ V._0._0._0 O NOT IS_IRQ R K_0._0.0_0 J J.0_0 0 RV_RESET V RV_RESET V TP J IS TEST._0 TP V X [0..] [0..] GN GN -I/O H K RESRV V 0 IRQ V -V REQ -V U 0WS 0 0 V 0 -IO_HRY._0 GN -I/O H RY 0 -SMEMW EN

More information

P a g e 5 1 of R e p o r t P B 4 / 0 9

P a g e 5 1 of R e p o r t P B 4 / 0 9 P a g e 5 1 of R e p o r t P B 4 / 0 9 J A R T a l s o c o n c l u d e d t h a t a l t h o u g h t h e i n t e n t o f N e l s o n s r e h a b i l i t a t i o n p l a n i s t o e n h a n c e c o n n e

More information

DM1 DC/DC CPU VR PG 43 PG 39 LVDS. Chrontel 7009 DVOB TV EN-CONDE PG 13 USB ATA 66/100 ATA 66/100 33MHZ, 3.3V PCI PHY PG 32 SWITCH PG 33 USB

DM1 DC/DC CPU VR PG 43 PG 39 LVDS. Chrontel 7009 DVOB TV EN-CONDE PG 13 USB ATA 66/100 ATA 66/100 33MHZ, 3.3V PCI PHY PG 32 SWITCH PG 33 USB M RUN POWER SW PG /TT ONNETOR TT SELETOR PG PG othan (Micro-FPG) PG, / PG PU VR PG Vtt & V_._MH.V,.V.V,.V PG 0 PG, LOKS PG RESET KT PG R-SOIMM PG 0 R-SOIMM PG 0 R-Termiation TT HRGER PG 00// MHZ R PS.V

More information

Reference Schematic for LAN9252-SPI/SQI+GPIO16 Mode

Reference Schematic for LAN9252-SPI/SQI+GPIO16 Mode Reference Schematic for LN-SPI/SQI+GPIO Mode onfigurations SPI/SQI+GPIO Mode EEPROM - F (High) Port mode Port0 & Port = opper Page No. Schematic Page Title Power Supply LN(Part) LN(Part), Strap & EEPROM

More information