TE1 Block Diagram. Intel. Merom (35W) FSB(667/800MHZ) Page 18 CRT. PCI-E 16X Lan. Crestline GM 533/ 667 MHZ DDR II. Page 5,7,8,9,10,11.

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1 P STK UP TE lock iagram LYER : TOP LYER : S LYER : IN LYER : V LYER : IN LYER : IN LYER : S LYER : OT V_ORE HMI Page LE PNEL Page HMI RT Page 0 Transmitter Sil Page L PNEL Page LE river I Page zalia SVO RT Intel Merom (W) Page, FS(/00MHZ) restline GM PI-E X Lan zalia LOK GENERTOR K0 ISLPR Page VG ONNETOR (FOX) Page RT HMI L/LE +.V +.0V +.V +.VSUS +.V +VPU +V_S +VSUS +V +VPU +V_S +V +SMR_VTERM +SMR_VREF HP Page 0 MI JK Page 0 INT SPK Page Reserve MI Page Reserve MI Page SPK MP Page UGHTER OR UGHTER OR UGHTER OR ST - H Page IE - O Page Port- Port- LN/ US Page amera Page WLN Page Finger Printer Page luetooth Page New ard Page M/ US Page Felica Page M/ US Page TV/ROSON Page UIO OE (X0) Page FM TUNER & M Page 0 (FT) (FT) (FT) Port- M oard US-0 US- US- US- US- US- US- US- US- US- ST PT Reserve FM Page RJ LVS US.0 zalia Page VR Page 0 FN Page Page,,,,0, IHM Page,,, LP WPE Kill SW Page MI(x/x).KHz / MHZ R II PI-Express PI us Key FLSH IR oard ROM Page Page Page PIE- MINI R- U&.H_WLN Page RII-SOIMM RII-SOIMM Page, MINI R- U H_H-V Page PMI ontroller ( 0) PMI MINI R- U.H_TV/ROSON.H_H-V Page ard Reader/ (OZT) Page Page PI ROUTING TLE ISEL REQ0# / GNT0# REQ# / GNT# G-Sensor Page PIE- PIE- IN INTERUPT INT# INT# MINI R- ROSON Page PIE- (FT) PIE- NEW R Page EVIE OZT 0 TO OM OPTION IV@ : UM EV@ : : R US GS@ : G-SENSOR NEW@ : NEW R L@ : L TYPE PNEL LE@ : LE TYPE PNEL IR@ : IR PIE- onnector Page Marvell LN 0/00/Giga E00T/E0 Transformer LN/RJ/RJ/US/RF UGHTER OR RJ RJ US LE oard Low ost oard Page MM oard Page Power oard Page Touch Pad oard Page Quanta omputer Inc. PROJET : TE Size ocument Number Rev lock iagram UGHTER OR RF Saturday, January, 00 ate: Sheet of

2 lock Generator +.V_V V :0., 0.0(Typ) PY00T-0Y-N_ L +.V +V L PY00T-0Y-N_ V_K_V_PI 0.u/0V_ 0 *0u/0V_ 0.u/0V_ 0u/0V_ *0u/0V_ 0u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ To PMI To OZ To E To S To S To S 0p/0V_ L=0p 0p/0V_ To ebug ard () () () () () () () G_XIN G_XOUT Realtek FE PI: Int P driven issue. dd Ext P for Realtek PLK_EUG PLK_PM PLK_OZ PLK_ PLK_IH LKUS_ M_IH +V LKUS_ LK_SEL0 R0 LK_SEL LK_SEL M_IH PLK_EUG PLK_PM PLK_OZ PLK_ PLK_IH +V R *0K_ PLK_ +V R Y.MHZ 0K_ R0 R0 R 0 R _ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ *0K_ 0K_.K_ 0K_ R R R0 VIO : 0.0, 0.0(Typ) +.V_V R _ R R _ R _ R0 _ *0K_ 0K_ R _ 0K_ *@_ PLK_OZ PLK_EUG_R PLK_OZ_R PLK_IH_R G_XIN G_XOUT FS FS PLK_PM_R PI_LK_SIO_R PLK R U V_PI V_ V_PLL V_REF V_SR V_PU V IO V_PLL_IO V_SR_IO_ V_SR_IO_ V_SR_IO_ V_PU_IO PI0/R#_ PI/R#_ PI/TME PI PI/SR_EN PIF/ITP_EN XTL_IN XTL_OUT US_/FS FS/TEST/MOE REF0/FS/TESTSEL VSS_PI VSS_ VSS_IO VSS_PLL VSS_PU VSS_SR VSS_SR VSS_SR VSS_REF K0 IO_VOUT SLK S SR/PI_STOP# SR#/PU_STOP# PU0 PU0# PU PU# SR/ITP SR#/ITP# SR0# SR0 SR SR# SR SR# SR SR# SR/SE SR#/SE 0 SR/R#_H SR#/R#_G 0 SR/R#_F SR#/R#_E 0 SR/R#_ SR#/R#_ SR/ST SR#/ST# SR0/OT SR0#/OT# KPWRG/PWRWN# GLK_SM GT_SM LK_PU_LK_R LK_PU_LK#_R LK_MH_LK_R LK_MH_LK#_R LK_PIE_MINI&_R LK_PIE_MINI&#_R LK_PIE_GPLL#_R LK_PIE_GPLL_R LK_MH_OE#_R NEW_LKREQ#_R LK_PIE_NEW_R LK_PIE_NEW_R# LK_PIE_MINI_R LK_PIE_MINI#_R LK_PIE_MINI_R LK_PIE_MINI#_R LK_PIE_LN_R LK_PIE_LN#_R LK_PIE_IH_R LK_PIE_IH#_R LK_PIE_ST_R LK_PIE_ST#_R REFSSLK_R REFSSLK#_R REFLK_R REFLK#_R RP RP RP R R RP RP RP RP RP RP0 RP 0X 0X 0X /F_ /F_ NEW@0X 0X 0X 0X 0X 0X *IV@0X PM_STPPI# () PM_STPPU# () LK_PU_LK () LK_PU_LK# () LK_MH_LK () LK_MH_LK# () LK_PIE_GPLL# () LK_PIE_GPLL () LK_MH_OE# () NEW_LKREQ# () LK_PIE_NEW () LK_PIE_NEW# () LK_PIE_MINI () LK_PIE_MINI# () LK_PIE_MINI () LK_PIE_MINI# () LK_PIE_LN () LK_PIE_LN# () LK_PIE_IH () LK_PIE_IH# () LK_PIE_ST () LK_PIE_ST# () REFLK () REFLK# () K_PWRG () To PU To N To N To New ard To MINI To MINI To LN To S To S To N Pin Pin Pin Pin ISLPRS (LPRSK) PI/TME PI- PI-/M_SEL PIF-/ITP_EN RTMT-0 (L000K0) PI/TME internal P PI-/SR_EN internal P PI-/M_SEL internal P PIF-/ITP_EN internal P PULL HIGH NO OVERLOKING PIN/ IS SR PIN / IS MHz PIN / IS PUITP (default) PULL OWN NORML RUN PIN/ IS PI_STOP/PU_STOP PIN / IS SR/OT PIN / IS SR (default) (default) (default) PLK_PM PLK_ LKUS_ M_IH PLK_IH PLK_EUG ISLPRSGLFT hange to p/0v_ 0 *p/0v_ *p/0v_ p/0v_ *p/0v_ *p/0v_ *p/0v_ LK_PIE_MINI&_R LK_PIE_MINI&#_R REFSSLK_R REFSSLK#_R RP RP RP0 RP *IV@0X EV@0X *IV@0X EV@0X LK_PIE_MINI () LK_PIE_MINI# () LK_PIE_MINI () LK_PIE_MINI# () REFSSLK () REFSSLK# () LK_MXM () LK_MXM# () To MINI To MINI To N To VG ard SEL Frequency Select Table lock Gen I +V FS FS FS Frequency Mhz 0 0 Mhz () PU_SEL0 +.0V R 0_ R R *_ *K_ LK_SEL0 MH_SEL0 () (,,,) ST Q RHU00N0 R 0K_ GT_SM GT_SM () 0 Mhz +V Mhz 00Mhz () PU_SEL +.0V R0 0_ R0 R0 *0_ *K_ LK_SEL MH_SEL () (,,,) SLK Q RHU00N0 R 0K_ GLK_SM GLK_SM () Mhz Mhz R0 0_ LK_SEL () PU_SEL MH_SEL () R0 *0_ +.0V R *K_ +V R 0K_ NEW_LKREQ#_R Quanta omputer Inc. PROJET : TE Size ocument Number Rev LK. GEN./ K0 Wednesday, January, 00 ate: Sheet of

3 PU(HOST) +.0V R K/F_ () () () () () () () () () () () () () () () () () () () () H_#[:] H_ST0# H_REQ#[:0] H_#[:] H_ST# H_0M# H_FERR# H_IGNNE# H_STPLK# H_INTR H_NMI H_SMI# H_#[:0] H_STN#0 H_STP#0 H_INV#0 H_#[:] H_STN# H_STP# H_INV# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_REQ#0 H_REQ# H_REQ# H_REQ# H_REQ# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# J L L K M N J N P P L P P R M K H K J L Y U R W U Y U R T T W W Y U V W V M N T V F E F E G F G E E K G J J H F K H J H H N K P R L M L M P P P T R L T N L M N U []# []# []# []# []# []# []# [0]# []# []# []# []# []# []# ST[0]# REQ[0]# REQ[]# REQ[]# REQ[]# REQ[]# []# []# []# [0]# []# []# []# []# []# []# []# []# []# [0]# []# []# []# []# []# ST[]# 0M# FERR# IGNNE# R GROUP 0 R GROUP STPLK# LINT0 LINT SMI# RSV[0] RSV[0] RSV[0] RSV[0] RSV[0] RSV[0] RSV[0] RSV[0] RSV[0] RSV[0] Merom all-out Rev a U [0]# []# []# []# []# []# []# []# []# []# [0]# []# []# []# []# []# STN[0]# STP[0]# INV[0]# []# []# []# []# [0]# []# []# []# []# []# []# []# []# []# [0]# []# STN[]# STP[]# INV[]# T GRP XP/ITP SIGNLS T GRP 0 ONTROL T GRP T GRP []# []# []# []# []# []# []# []# [0]# []# []# []# []# []# []# []# STN[]# STP[]# INV[]# []# []# [0]# []# []# []# []# []# []# []# []# []# [0]# []# []# []# STN[]# STP[]# INV[]# H_IERR# PURESET# XP_TK XP_TI XP_TMS XP_TRST# XP_RESET# H_PROHOT_R# H_THERM H_THERM THERMTRIP#_PWR Y V V V T U U Y W Y W W Y U E 0 E F E F E F 0 H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# R L T T T T T T T R./F_ LK_PU_LK () LK_PU_LK# () +.0V K0LM-T_ R 0_ R./F_ *.K_ H_#[:] () H_STN# () H_STP# () H_INV# () H_#[:] () H_STN# () H_STP# () H_INV# () H_S# () H_NR# () H_PRI# () H_EFER# () H_RY# () H_SY# () H_REQ#0 () H_INIT# () H_LOK# () H_RS#0 () H_RS# () H_RS# () H_TRY# () H_HIT# () H_HITM# () SYS_RST# () +.0V H_PROHOT# () <check list> efault PU ohm if no use. Serial R N, If connect to power side PU ohm. Serial R.K H_GTLREF R OMP0 R./F_ <heck list & R> R *K_ PU_TEST GTLREF OMP[0] U OMP R./F_ Layout note: L<0." R *0_ PU_TEST TEST MIS R *K_ OMP[] OMP R0./F_ OMP0/ Z=.ohm <heck list & R> PU_TEST TEST OMP[] OMP R./F_ OMP/ Z=. Layout note: Z= ohm T Y PU_TEST TEST OMP[] H_GTLREF<0." T F PU_TEST TEST T F E IH_PRSTP# (,,) PU_TEST TEST PRSTP# T0 PSLP# H_PSLP# () R TEST PWR# H_PWR# () K/F_ () PU_SEL0 SEL[0] PWRGOO H_PWRG () () PU_SEL SEL[] SLP# H_PUSLP# () () PU_SEL E SEL[] PSI# PSI# () Merom all-out Rev a S# NR# PRI# EFER# RY# SY# R0# IERR# INIT# LOK# RESET# RS[0]# RS[]# RS[]# TRY# HIT# HITM# PM[0]# PM[]# PM[]# PM[]# PRY# PREQ# TK TI TO TMS TRST# R# THERML IH RESERVE PROHOT# THERM THERM THERMTRIP# H LK LK[0] LK[] H E G H F E F 0 H F F G G G E 0 H_PURST# () PU Thermal monitor (,) () (,) XP_TMS XP_TI XP_TK XP_TRST# N_MLK N_MT PU FN THERM_LERT# () () SYSFNON# VFN +V +V PU/P (ITP00) R +V +.0V R 0_ R _ R +V +V R0 R R 0_ /F_ 0/F_ R Q0 RHU00N0 Q RHU00N0.u/.V_ Thermal Trip (,,) THERMTRIP#_PWR 0K_ *0_ 0K_ U /FON VSET THERM_LERT#_R THER_SH# VO G FNPWR =.*VSET ELY_VR_PWRGOO +.0V R 0K_ R0./F_ () R 0K_ +V LM RESS: H FNSIG TH_FN_POWER 0u/0V_ +.0V U SLK S LERT# OVERT# R 00_ +V Q MMT0 V XP LMV XN Q MMT u/V_ R K_ Q FV0N R 0_ *0.0u/V_ R *0K_ +V R 0.u/0V_ 0 00p/0V_ SYS_SHN# () PM_THRMTRIP# (,) H_THERM H_THERM SYS_SHN# () R 0K_ *S N 00K_ Quanta omputer Inc. PROJET : TE FN_ON

4 PU(Power) V_ORE 0u/.V_ 0u/.V_ *0u/.V_ *0u/.V_ + P 0u/.V_ 0u/.V_ 0u/.V_ 0u/.V_ *0u/.V_ *0u/.V_ *0u/.V_ *0u/.V_ *0u/.V_ + P 0u/.V_ 0u/.V_ *0u/.V_ *0u/.V_ *0u/.V_ 0u/.V_ *0u/.V_ 0 *0u/.V_ *0u/.V_ 0 0u/.V_ *0u/.V_ *0u/.V_ *0u/.V_ 0u/.V_ *0u/.V_ 0u/.V_ *0u/.V_ 0u/.V_ *0u/.V_ 0u/.V_ *0u/.V_ U V[00] V[0] 0 V[00] V[0] 0 V[00] V[00] V[00] V[0] V[00] V[0] V[00] V[0] V[00] V[0] V[00] V[0] 0 V[00] V[0] V[00] V[0] V[0] V[0] 0 V[0] V[0] 0 V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] 0 V[0] V[0] E V[0] V[0] E0 0 V[00] V[0] E V[0] V[0] E V[0] V[0] E V[0] V[00] E V[0] V[0] E V[0] V[0] E0 V[0] V[0] F 0 V[0] V[0] F0 V[0] V[0] F V[0] V[0] F V[00] V[0] F V[0] V[0] F V[0] V[0] F E V[0] V[00] F0 E V[0] E0 V[0] VP[0] G E V[0] VP[0] V E V[0] VP[0] J E V[0] VP[0] K E V[0] VP[0] M E V[00] VP[0] J E0 V[0] VP[0] K F V[0] VP[0] M F V[0] VP[0] N F0 V[0] VP[0] N F V[0] VP[] R F V[0] VP[] R F V[0] VP[] T F V[0] VP[] T F V[0] VP[] V F0 V[00] VP[] W V[0] V[0] V[0] 0 V[0] V[0] V[0] V[0] VI[0] V[0] VI[] F V[0] VI[] E V[0] VI[] F 0 V[0] VI[] E V[00] VI[] F 0 V[0] VI[] E 0 V[0] V[0] V[0] VSENSE F V[0] V[0] V[0] VSSSENSE E Merom all-out Rev a. +V_PRO +.0V H_VI0 () H_VI () H_VI () H_VI () H_VI () H_VI () H_VI () <REV.NO. 0./REF.NO.> Ivcc Max Ivccp Max (VP supply before Vcc stable) Max (VP supply after Vcc stable) Ivcca Max 0m 0.u/V_ + 0u/V_ V_ORE <heck list> ESR=m ohm <R>.0U near to ball R 00/F_ R0 00/F_ 0.u/V_ 0.u/V_ 0.0u/V_ 0.u/V_ 0.u/V_ R 0_ 0u/0V_ +.V VSENSE () VSSSENSE () <R> Routing.ohm with 0mils spacing PU/P near to PU " 0.u/V_ U VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] F VSS[00] VSS[00] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[00] E VSS[0] E VSS[0] E VSS[0] F VSS[0] F VSS[0] F VSS[0] F VSS[0] F VSS[0] F VSS[0] F VSS[00] F VSS[0] F VSS[0] G VSS[0] G VSS[0] G VSS[0] G VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[00] J VSS[0] J VSS[0] J VSS[0] J VSS[0] K VSS[0] K VSS[0] K VSS[0] K VSS[0] L VSS[0] L VSS[00] L VSS[0] L VSS[0] M VSS[0] M VSS[0] M VSS[0] M VSS[0] N VSS[0] N VSS[0] N VSS[0] N VSS[00] P VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] P P P R R R R T T T T U U U U V V V V W W W W Y Y Y Y E E E E E E E E E F F F F F F F F Merom all-out Rev a. Size ocument Number Rev PU( of ) Quanta omputer Inc. PROJET : TE Wednesday, January, 00 ate: Sheet of

5 N(HOST) +.0V R K/F_ R K/F_ () H_#[:0] +.0V R /F_ H_SWING R0 0 00/F_ 0.u/0V_ H_ROMP 0:0 mils(width:spacing) R0./F_ +.0V R./F_ Impedance ohm H_SOMP +.0V R Impedance ohm./f_ H_SOMP# () H_PURST# () H_PUSLP# 0.U close to,l<00mils 0 0.u/0V_ H_PURST# *0.u/0V_ H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_SWING H_ROMP H_SOMP H_SOMP# H_PURST# H_VREF U E H_#_0 G H_#_ G H_#_ M H_#_ H H_#_ H H_#_ G H_#_ F H_#_ N H_#_ H H_#_ M0 H_#_0 N H_#_ N H_#_ H H_#_ P H_#_ K H_#_ M H_#_ W0 H_#_ Y H_#_ V H_#_ M H_#_0 J H_#_ N H_#_ N H_#_ W H_#_ W H_#_ N H_#_ Y H_#_ Y H_#_ P H_#_ W H_#_0 N H_#_ H_#_ E H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ Y H_#_ H_#_ E H_#_ H_#_ G H_#_ J H_#_ H H_#_ J H_#_0 E H_#_ E H_#_ H H_#_ J H_#_ H H_#_ J H_#_ E H_#_ J H_#_ J H_#_ E H_#_0 J H_#_ H H_#_ H H_#_ H_SWING H_ROMP W H_SOMP W H_SOMP# H_PURST# E H_PUSLP# H_VREF H_VREF RESTLINE_p0 HOST GM : JSLT0T0 PM : JSLU0T 0GML : JSLV0T0 H_#_ J H_#_ H_#_ H_#_ M H_#_ H_#_ F H_#_ L H_#_0 G H_#_ H_#_ K H_#_ H_#_ L H_#_ J H_#_ H_#_ K H_#_ P H_#_ R H_#_0 H_#_ H0 H_#_ L H_#_ H_#_ M H_#_ N H_#_ J H_#_ H_#_ E H_#_ H_#_0 H_#_ E H_#_ H_#_ H_#_ H_#_ N H_S# G H_ST#_0 H H_ST#_ G0 H_NR# H_PRI# E H_REQ# F H_EFER# H_SY# 0 HPLL_LK M HPLL_LK# M H_PWR# H H_RY# K H_HIT# E H_HITM# H_LOK# G0 H_TRY# H_INV#_0 K H_INV#_ L H_INV#_ H_INV#_ E H_STN#_0 M H_STN#_ K H_STN#_ H_STN#_ H H_STP#_0 L H_STP#_ K H_STP#_ H_STP#_ J0 H_REQ#_0 M H_REQ#_ E H_REQ#_ H_REQ#_ H H_REQ#_ H_RS#_0 E H_RS#_ H_RS#_ H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_INV#0 H_INV# H_INV# H_INV# H_STN#0 H_STN# H_STN# H_STN# H_STP#0 H_STP# H_STP# H_STP# H_REQ#0 H_REQ# H_REQ# H_REQ# H_REQ# H_RS#0 H_RS# H_RS# H_#[:] () H_S# () H_ST0# () H_ST# () H_NR# () H_PRI# () H_REQ#0 () H_EFER# () H_SY# () LK_MH_LK () LK_MH_LK# () H_PWR# () H_RY# () H_HIT# () H_HITM# () H_LOK# () H_TRY# () H_INV#[:0] () H_STN#[:0] () H_STP#[:0] () H_REQ#[:0] () H_RS#[:0] () Quanta omputer Inc. PROJET : Size ocument Number Rev GMH HOST( of ) TE ate: Wednesday, January, 00 Sheet of

6 (,) M (,) M () MH_SEL0 () MH_SEL () MH_SEL () MH_FG_ () MH_FG_ () MH_FG_ () MH_FG_ () MH_FG_ () MH_FG_ () MH_FG_0 () PM_MUSY# (,,) IH_PRSTP# () PM_EXTTS#0 () PM_EXTTS#,,) ELY_VR_PWRGOO () PLTRST#_N (,) PM_THRMTRIP# (,) PM_PRSLPVR U P RSV P RSV R RSV N RSV R RSV R RSV M RSV N RSV J RSV R RSV0 M RSV L RSV M RSV 0 RSV H0 RSV0 RSV J0 RSV K RSV F RSV H0 RSV K RSV J RSV F RSV G RSV RSV0 RSV J RSV E RSV H RSV W0 RSV K0 RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV P FG_0 N FG_ N MH_FG_ FG_ T MH_FG_ FG_ T FG_ F MH_FG_ FG_ T N MH_FG_ FG_ T G MH_FG_ FG_ T J0 FG_ 0 MH_FG_0 FG_ T0 R MH_FG_ FG_0 T L FG_ J FG_ E MH_FG_ FG_ T E0 MH_FG_ FG_ T K FG_ M0 MH_FG_ FG_ T M MH_FG_ FG_ T L FG_ N FG_ L FG_0 G PM_M_USY# L PM_EXTTS#0 PM_PRSTP# L PM_EXTTS# PM_EXT_TS#_0 J PM_EXT_TS#_ W R 00_ RST_IN#_MH PWROK V0 R *0_ PM_THRMTRIP#_GMH RSTIN# N0 THERMTRIP# G PRSLPVR J N_ K N_ K0 N_ L0 N_ L N_ L N_ L N_ K N_ J N_ E N_0 N_ N_ 0 N_ 0 N_ N_ K N_ RESTLINE_p0 RSV R MUXING LK FG MI GRPHIS VI PM ME N MIS SM_K_0 SM_K_ SM_K_ SM_K_ SM_K#_0 SM_K#_ SM_K#_ SM_K#_ SM_KE_0 SM_KE_ SM_KE_ SM_KE_ SM_S#_0 SM_S#_ SM_S#_ SM_S#_ SM_OT_0 SM_OT_ SM_OT_ SM_OT_ SM_ROMP SM_ROMP# SM_ROMP_VOH SM_ROMP_VOL SM_VREF_0 SM_VREF_ PLL_REF_LK PLL_REF_LK# PLL_REF_SSLK PLL_REF_SSLK# PEG_LK PEG_LK# MI_RXN_0 MI_RXN_ MI_RXN_ MI_RXN_ MI_RXP_0 MI_RXP_ MI_RXP_ MI_RXP_ MI_TXN_0 MI_TXN_ MI_TXN_ MI_TXN_ MI_TXP_0 MI_TXP_ MI_TXP_ MI_TXP_ GFX_VI_0 GFX_VI_ GFX_VI_ GFX_VI_ GFX_VR_EN L_LK L_T L_PWROK L_RST# L_VREF SVO_TRL_LK SVO_TRL_T LK_REQ# IH_SYN# TEST_ TEST_ V V W0 W W E Y G G0 K G E H J J E L K K L R W H H K K N J N N M J N N J J M0 M J J M M E E M K0 T N M0 H K G G0 R M_ROMP M_ROMP# SM_ROMP_VOH SM_ROMP_VOL REFLK REFLK# REFSSLK REFSSLK# MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP +.V_L_VREF LK_MH_OE# GMH_TEST GMH_TEST +.VSUS SMR_VREF_MH R R00 (0) (0) () () M_LK_R0 () M_LK_R () M_LK_R () M_LK_R () M_LK_R#0 () M_LK_R# () M_LK_R# () M_LK_R# () M_KE0 (,) M_KE (,) M_KE (,) M_KE (,) M_S#0 (,) M_S# (,) M_S# (,) M_S# (,) M_OT0 (,) M_OT (,) M_OT (,) M_OT (,) L_LK0 () L_T0 () MPWROK () L_RST#0 () INT_LVS_PWM INT_LVS_LON REFLK () REFLK# () REFSSLK () REFSSLK# () LK_PIE_GPLL () LK_PIE_GPLL# () MI_TXN[:0] () MI_TXP[:0] () MI_RXN[:0] () MI_RXP[:0] () INT_RT_LK INT_RT_T (0) INT_HSYN (0) INT_VSYN SVO_TRLLK () SVO_TRLT () LK_MH_OE# () MH_IH_SYN# () R 0_ R 0K_ R *0K_ *0K_ K/F_ R 0_ +V +V () () () INT_LVS_EILK INT_LVS_EIT INT_LVS_IGON +.VSUS (0) (0) (0) SM_ROMP_VOH R0 R R () () +SMR_VREF R R 0 0.u/0V_ R R R () () () () () () INT_RT_LU INT_RT_GRN INT_RT_RE +.V_X R0 K/F_ R R R0 R /F_ EV@0_ EV@0_ *IV@0_ INT_TXLOUT0- INT_TXLOUT- INT_TXLOUT- INT_TXLLKOUT- INT_TXLLKOUT+ INT_TXLOUT0+ INT_TXLOUT+ INT_TXLOUT+ For EV@ TV // use 0 ohm R R 0_ R 0_ *IV@0/F_ *IV@0/F_ *IV@0K_ *IV@0K_ *IV@.K/F_ EV@0_ EV@0_ EV@0_ For IV@ TV // use ohm R L_TRL_LK L_TRL_T T T T0 T T T T T T INT_RT_LK INT_RT_T HSYN_ RTIREF VSYN_ LVS_IG N_TV N_TV N_TV N_TV_ONSEL_0 N_TV_ONSEL_ INT_RT_LU INT_RT_GRN INT_RT_RE For EV@ RT R/G/ use 0 ohm R R R R R J0 H E E0 K0 L L N N0 E G E F G0 E0 F G E E G K F J L M P H G K J F E K G F E U L_KLT_TRL L_KLT_EN L_TRL_LK L_TRL_T L LK L T L_V_EN LVS_IG LVS_VG LVS_VREFH LVS_VREFL LVS_LK# LVS_LK LVS_LK# LVS_LK EV@0_ EV@0_ EV@0_ EV@0_ For IV@ USE.K ohm R For EV@ USE 0 ohm R RP0 LVS_T#_0 LVS_T#_ LVS_T#_ LVS_T_0 LVS_T_ LVS_T_ LVS_T#_0 LVS_T#_ LVS_T#_ LVS_T_0 LVS_T_ LVS_T_ TV_ TV_ TV_ TV_RTN TV_RTN TV_RTN TV_ONSEL_0 TV_ONSEL_ RT_LUE RT_LUE# RT_GREEN RT_GREEN# RT_RE RT_RE# RT LK RT T RT_HSYN RT_TVO_IREF RT_VSYN RESTLINE_p0 For IV@ RT R/G/ use 0 ohm R INT_RT_LU INT_RT_GRN INT_RT_RE RTIREF EV@0X LVS PI-EXPRESS GRPHIS TV VG REFLK REFLK# N EXP OMPX R./F_ PEG_OMPI PEG_OMPO M PEG_RX#_0 J PEG_RXN0 () PEG_RX#_ L PEG_RXN (,) N PEG_RX#_ PEG_RXN () T PEG_RX#_ PEG_RXN () T0 PEG_RX#_ PEG_RXN () U0 PEG_RX#_ PEG_RXN () Y PEG_RX#_ PEG_RXN () PEG_RX#_ Y0 PEG_RXN () PEG_RX#_ PEG_RXN () W PEG_RX#_ PEG_RXN () PEG_RX#_0 PEG_RXN0 () PEG_RX#_ 0 PEG_RXN () G PEG_RX#_ PEG_RXN () PEG_RX#_ H PEG_RXN () G PEG_RX#_ PEG_RXN () PEG_RX#_ G PEG_RXN () PEG_RX_0 J0 PEG_RXP0 () L0 PEG_RX_ PEG_RXP (,) PEG_RX_ M PEG_RXP () PEG_RX_ U PEG_RXP () T PEG_RX_ PEG_RXP () T PEG_RX_ PEG_RXP () PEG_RX_ W PEG_RXP () W PEG_RX_ PEG_RXP () PEG_RX_ 0 PEG_RXP () PEG_RX_ Y PEG_RXP () PEG_RX_0 PEG_RXP0 () PEG_RX_ PEG_RXP () PEG_RX_ H PEG_RXP () PEG_RX_ G PEG_RXP () PEG_RX_ H PEG_RXP () PEG_RX_ G PEG_RXP () N _PEG_TXN0 EV@0.u/0V_ PEG_TX#_0 U _PEG_TXN EV@0.u/0V_ PEG_TX# PEG_TXN PEG_TX#_ U EV@0.u/0V PEG_TXN 0 EV@0.u/0V_ PEG_TX#_ N _PEG_TXN EV@0.u/0V_ PEG_TX#_ R0 _PEG_TXN EV@0.u/0V_ PEG_TX#_ T Y _PEG_TXN EV@0.u/0V_ PEG_TX#_ W _PEG_TXN EV@0.u/0V_ PEG_TX#_ W _PEG_TXN EV@0.u/0V_ PEG_TX# PEG_TXN EV@0.u/0V_ PEG_TX# PEG_TXN0 EV@0.u/0V_ PEG_TX#_0 _PEG_TXN EV@0.u/0V_ PEG_TX# PEG_TXN EV@0.u/0V_ PEG_TX# PEG_TXN EV@0.u/0V_ PEG_TX#_ H _PEG_TXN EV@0.u/0V_ PEG_TX#_ E _PEG_TXN EV@0.u/0V_ PEG_TX#_ H _PEG_TXP0 EV@0.u/0V_ PEG_TX_0 M _PEG_TXP EV@0.u/0V_ PEG_TX_ T _PEG_TXP EV@0.u/0V_ PEG_TX_ T _PEG_TXP EV@0.u/0V_ PEG_TX_ N0 _PEG_TXP EV@0.u/0V_ PEG_TX_ R _PEG_TXP EV@0.u/0V_ PEG_TX_ U _PEG_TXP 00 EV@0.u/0V_ PEG_TX_ W _PEG_TXP 0 EV@0.u/0V_ PEG_TX_ Y _PEG_TXP 0 EV@0.u/0V_ PEG_TX_ Y _PEG_TXP EV@0.u/0V_ PEG_TX PEG_TXP0 EV@0.u/0V_ PEG_TX_0 _PEG_TXP EV@0.u/0V_ PEG_TX_ 0 _PEG_TXP EV@0.u/0V_ PEG_TX PEG_TXP PEG_TX_ G EV@0.u/0V PEG_TXP PEG_TX_ E0 EV@0.u/0V PEG_TXP EV@0.u/0V_ PEG_TX_ H _PEG_TXP0 0 *IV@0.u/0V PEG_TXN0 0 *IV@0.u/0V PEG_TXP 0 *IV@0.u/0V PEG_TXN 0 *IV@0.u/0V PEG_TXP 0 *IV@0.u/0V PEG_TXN 0 *IV@0.u/0V PEG_TXP 0 *IV@0.u/0V PEG_TXN 0 *IV@0.u/0V_ R0 EV@0_ R EV@0_ R EV@0_ R EV@0_ +V_PEG PEG_TXN0 PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN0 PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXP0 PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP0 PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP HSYN_ VSYN_ INT_RT_LK INT_RT_T PEG_TXN0 () PEG_TXN () PEG_TXN () PEG_TXN () PEG_TXN () PEG_TXN () PEG_TXN () PEG_TXN () PEG_TXN () PEG_TXN () PEG_TXN0 () PEG_TXN () PEG_TXN () PEG_TXN () PEG_TXN () PEG_TXN () PEG_TXP0 () PEG_TXP () PEG_TXP () PEG_TXP () PEG_TXP () PEG_TXP () PEG_TXP () PEG_TXP () PEG_TXP () PEG_TXP () PEG_TXP0 () PEG_TXP () PEG_TXP () PEG_TXP () PEG_TXP () PEG_TXP () SVO_RE+ () SVO_RE- () SVO_GREEN+ () SVO_GREEN- () SVO_LUE+ () SVO_LUE- () SVO_LK+ () SVO_LK- () M_ROMP# +.VSUS +V R.0K/F_ 0.0u/V_.u/.V_ RP EV@0X REFSSLK REFSSLK# R 0/F_ M_ROMP R 0/F_ R R R 0K_ LK_MH_OE# 0K_ PM_EXTTS#0 0K_ PM_EXTTS# R K/F_ SM_ROMP_VOL 0.0u/V_.u/.V_ Quanta omputer Inc. PROJET : TE Size ocument Number Rev GMH MI/VIEO( of ) Wednesday, January, 00 ate: Sheet of

7 N(Memory controller) () M Q[:0] M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q U R S_Q_0 W S_Q_ S_Q_ Y S_Q_ R S_Q_ R S_Q_ T S_Q_ W S_Q_ S_Q_ F S_Q_ G S_Q_0 J S_Q_ S_Q_ G0 S_Q_ H S_Q_ E S_Q_ W S_Q_ E S_Q_ G S_Q_ E0 S_Q_ F S_Q_0 H S_Q_ G0 S_Q_ F0 S_Q_ R0 S_Q_ W0 S_Q_ T S_Q_ W S_Q_ W S_Q_ Y S_Q_ V S_Q_0 T S_Q_ V S_Q_ T S_Q_ W S_Q_ V S_Q_ U S_Q_ T S_Q_ S_Q_ S_Q_ E0 S_Q_0 0 S_Q_ S_Q_ Y S_Q_ G0 S_Q_ W S_Q_ S_Q_ S_Q_ S_Q_ Y S_Q_ T S_Q_0 T S_Q_ Y S_Q_ S_Q_ R S_Q_ R S_Q_ R S_Q_ N S_Q_ M S_Q_ N0 S_Q_ T S_Q_0 N S_Q_ M S_Q_ N S_Q_ RESTLINE_p0 R SYSTEM MEMORY S_S_0 S_S_ S_S_ S_S# S_M_0 S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_QS_0 S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS#_0 S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_M_0 S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_0 S_M_ S_M_ S_M_ S_RS# S_RVEN# S_WE# K F L T W W G Y N T E H P T H P J 0 K H L K J J L E G0 J E Y0 M M0 M M M M M M M M M M M M M M M QS0 M QS M QS M QS M QS M QS M QS M QS M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M 0 M M M M M M M M M M 0 M M M TP_S_RVEN# M S#0 (,) M S# (,) M S# (,) M S# (,) M M[:0] () M QS[:0] () M QS#[:0] () M [:0] (,) M RS# (,) T M WE# (,) () M Q[:0] M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q UE P S_Q_0 R S_Q_ W0 S_Q_ W S_Q_ N S_Q_ N0 S_Q_ V0 S_Q_ V S_Q_ 0 S_Q_ 0 S_Q_ S_Q_0 E0 S_Q_ S_Q_ Y S_Q_ F0 S_Q_ F S_Q_ J0 S_Q_ J S_Q_ J S_Q_ L S_Q_ K S_Q_0 K S_Q_ K S_Q_ K S_Q_ J S_Q_ L S_Q_ J S_Q_ J S_Q_ K S_Q_ J0 S_Q_ L S_Q_0 K S_Q_ K S_Q_ E S_Q_ K S_Q_ S_Q_ S_Q_ E S_Q_ S_Q_ G S_Q_ J0 S_Q_0 L S_Q_ K S_Q_ L S_Q_ K S_Q_ K0 S_Q_ J S_Q_ J S_Q_ F S_Q_ H S_Q_ G S_Q_0 S_Q_ K S_Q_ E S_Q_ S_Q_ J S_Q_ S_Q_ S_Q_ R S_Q_ T S_Q_ Y S_Q_0 Y S_Q_ U S_Q_ T S_Q_ RESTLINE_p0 R SYSTEM MEMORY S_S_0 S_S_ S_S_ S_S# S_M_0 S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_QS_0 S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS#_0 S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_M_0 S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_0 S_M_ S_M_ S_M_ S_RS# S_RVEN# S_WE# Y G G E R0 K L H J F W T0 0 K K J L E V U0 0 L K K K F V G G W F E Y G E G V Y M M0 M M M M M M M M M M M M M M M QS0 M QS M QS M QS M QS M QS M QS M QS M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M 0 M M M M M M M M M M 0 M M M TP_S_RVEN# M S#0 (,) M S# (,) M S# (,) M S# (,) M M[:0] () M QS[:0] () M QS#[:0] () M [:0] (,) M RS# (,) T M WE# (,) Size ocument Number Rev MH R( of ) Quanta omputer Inc. PROJET : TE ate: Wednesday, January, 00 Sheet of

8 VSM_LF VSM_LF VSM_LF VSM_LF VSM_LF VSM_LF VSM_LF +.0_V_XG_NTF +.0V +.0V +.0V +.VSUS +.0V +.0V +.0_V_XG_NTF +.0_V_XG_NTF Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMH Power-( of ) Wednesday, January, 00 TE Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMH Power-( of ) Wednesday, January, 00 TE Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMH Power-( of ) Wednesday, January, 00 TE N(Power-) GM:.m PM:0m MHz:00m MHz:00m 00m 0m 0 *IV@0.u/0V_ 0 *IV@0.u/0V_ 0u/0V_ 0u/0V_ 0.u/0V_ 0.u/0V_ 0.u/.V_ 0.u/.V_ R0 *IV@0_ R0 *IV@0_ 0.u/0V_ 0.u/0V_ + 0 *0u/.V_ + 0 *0u/.V_ V_NTF_ V_NTF_0 K V_NTF_ P V_NTF_ U V_NTF_ F V_NTF_0 F V_NTF_ H V_NTF_ H V_NTF_ H V_NTF_ H V_NTF_ J V_NTF_ K V_NTF_ K V_NTF_ K V_NTF_ V_NTF_ L V_NTF_ L V_NTF_ V_NTF_0 P V_NTF_ R V_NTF_ R V_NTF_ T0 V_NTF_ T V_NTF_0 T V_NTF_ U V_NTF_ V_NTF_ U V_NTF_ U V_NTF_ U V_NTF_ U V_NTF_ V V_NTF_ V V_NTF_0 V V_NTF_ V_NTF_ V_NTF_ VSS_NTF_ T VSS_NTF_ T VSS_NTF_ U VSS_NTF_ U VSS_NTF_ V VSS_NTF_ V VSS_NTF_ VSS_NTF_ VSS_NTF_0 V_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ F VSS_NTF_ K VSS_NTF_ M VSS_NTF_ P VSS_NTF_ R VSS_NTF_0 R VSS_NTF_ R V_NTF_ Y V_XM_ K V_XM_ K V_XM_ J V_XM_ J V_XM_NTF_ L V_XM_NTF_ L V_XM_NTF_ L V_XM_NTF_ M V_XM_NTF_ M V_XM_NTF_ M V_XM_NTF_ M V_XM_NTF_0 P V_XM_NTF_ P V_XM_NTF_ R V_NTF_ Y V_NTF_ Y V_NTF_ Y V_NTF_ Y VSS_S VSS_S VSS_S VSS_S L VSS_S L VSS_S V_NTF_ V_NTF_ V_NTF_ V_NTF_ J V_NTF_ VSS_NTF_ F V_NTF_ J V_XM_ K V_XM_NTF_ L V_XM_NTF_ L V_XM_NTF_ L VSS_NTF_ M V_XM_NTF_ M V_XM_NTF_ M V_NTF_ M VSS_NTF_ P V_XM_NTF_ P V_XM_NTF_ P V_XM_NTF_ R V_XM_NTF_ R V_XM_ T V_XM_ T V_NTF_ V POWER V NTF VSS NTF VSS S V XM V XM NTF UF RESTLINE_p0 POWER V NTF VSS NTF VSS S V XM V XM NTF UF RESTLINE_p0 0.u/.V_ 0.u/.V_ *IV@0.u/0V_ *IV@0.u/0V_ 0 0.u/.V_ 0 0.u/.V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ R0 *IV@0_ R0 *IV@0_ u/0v_ u/0v_ 0.u/0V_ 0.u/0V_ 0.u/.V_ 0.u/.V_ 0.u/0V_ 0.u/0V_ 0u/0V_ 0u/0V_ 0.u/.V_ 0.u/.V_ *IV@u/0V_ *IV@u/0V_ 0.u/0V_ 0.u/0V_ V_ V_ K V_ J V_ J V_ H V_0 H V_ H V_ F V_ T V_ V_SM_0 V_SM_0 F V_SM_0 J V_SM_ W V_SM_ Y V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ E V_SM_ E V_SM_ E V_SM_ U V_SM_ F V_SM_ G V_SM_ G V_SM_ G V_SM_ H V_SM_ H V_SM_ H V_SM_ J V_SM_ J V_SM_ U V_SM_ K V_SM_ K V_SM_ K V_SM_ K V_XG_NTF_0 U V_XG_NTF_ U V_XG_NTF_ U0 V_XG_NTF_ U V_XG_NTF_ U V_XG_NTF_ U V_XG_NTF_ V V_XG_NTF_ V V_XG_NTF_ V V_XG_NTF_ V0 V_XG_NTF_ T V_XG_NTF_0 V V_XG_NTF_ V V_XG_NTF_ V V_XG_NTF_ Y V_XG_NTF_ Y V_XG_NTF_ Y V_XG_NTF_ Y V_XG_NTF_ Y0 V_XG_NTF_ Y V_XG_NTF_ Y V_XG_NTF_ T V_XG_NTF_0 Y V_XG_NTF_ Y V_XG_NTF_ Y V_XG_NTF_ Y V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ T V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ F V_XG_NTF_ F V_XG_NTF_ H V_XG_NTF_ H V_XG_NTF_ H V_XG_NTF_ H V_XG_NTF_ T V_XG_NTF_0 J V_XG_NTF_ J V_XG_NTF_ J V_XG_NTF_ K V_XG_NTF_ K V_XG_NTF_ L V_XG_NTF_ L V_XG_NTF_ L V_XG_NTF_ L0 V_XG_NTF_ L V_XG_NTF_ T V_XG_NTF_0 L V_XG_NTF_ M V_XG_NTF_ M V_XG_NTF_ M V_XG_NTF_ M V_XG_NTF_ M V_XG_NTF_ P V_XG_NTF_ P V_XG_NTF_ P V_XG_NTF_ T V_XG_NTF_0 P V_XG_NTF_ P0 V_XG_NTF_ P V_XG_NTF_ U V_XG_NTF_ U V_SM_ L V_SM_ V V_SM_ W V_XG_NTF_ T V_ T V_SM_ U V_XG_ R0 V_XG_ T V_XG_ W V_XG_ W V_XG_ Y V_XG_ 0 V_XG_ V_XG_ V_XG_ V_XG_0 V_XG_ V_XG_ V_XG_ 0 V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_0 0 V_XG_ V_XG_ V_XG_ V_XG_ F V_XG_ F V_XG_ H0 V_XG_ H V_XG_ H V_XG_0 H V_XG_NTF_ P V_XG_NTF_ P V_XG_NTF_ R0 V_XG_NTF_ R V_XG_NTF_ R V_XG_NTF_ R V_XG_NTF_ R V_ R0 V_XG_ H V_XG_ J0 V_XG_ N V_SM_LF W V_SM_LF V_SM_LF E V_SM_LF V_SM_LF V_SM_LF W V_SM_LF T V_XG_ V_XG_ V_ H V_XG_NTF_ M0 V_SM_ U0 V_XG_NTF_0 V V_XG_NTF_ V V_XG_NTF_ V V_XG_NTF_ Y POWER V ORE V SM V GFX V GFX NTF V SM LF UG RESTLINE_p0 POWER V ORE V SM V GFX V GFX NTF V SM LF UG RESTLINE_p0 u/0v_ u/0v_ R EV@0_ R EV@0_ 0.u/0V_ 0.u/0V_ 00 *IV@u/.V_ 00 *IV@u/.V_ 0 *IV@0.u/0V_ 0 *IV@0.u/0V_ R *IV@0_ R *IV@0_ 0.u/.V_ 0.u/.V_ 0u/0V_ 0u/0V_ *IV@0u/0V_ *IV@0u/0V_ 0u/0V_ 0u/0V_

9 N(Power-) +.V L *IV@0uh_ +V R +V_VSYN *IV@0_ 0m R RT/TV isable/enable guideline all Enable isable all Enable isable LVS isable/enable guideline External VG with EV@part,Internal VG with IV@ part If SVO isable If SVO enable If SVO enable Signal LVS isable LVS isable LVS enable +V +.V R0 EV@0_ L L *IV@0uh_ +.V_V_PLL +.V_V_PLL R EV@0_ *IV@u/.V_ + *IV@0u/.V_ + 00m *IV@0u/.V_ +.V +.V *IV@PY00T-0Y-N_ 0 *IV@0u/0V_ u/.vv_ *IV@0.u/0V_ *IV@0.u/0V_ *IV@0.u/0V_ *IV@0.u/0V_ L0 L +V V.M_MPLL_R +.V +V_TV_ *IV@0.u/0V_ 0m 0m *IV@n/V_ *IV@n/V_ L +V_TV_ R0 0_ + *00u/.V_ *IV@n/V_ R0 PY00T-0Y-N_ PY00T-0Y-N_ R 0./F_ R0 0_ R0 EV@0_ *IV@PY00T-0Y-N_ **IV@u/.V_ 0.u/0V_ 0m 0m *IV@0_ u/.vv_ +V 0 *u/.v_ *u/v_ +.V +.V *IV@0.u/0V_ *IV@0.u/0V_ 0 *IV@0.u/0V_ 0.u/0V_ *u/v_ R 0_ 0.u/0V_ R R 0m 0m L0 0.u/.V_ 0u/0V_ R 0_ +V_V_RT_ +V_V G *IV@n/V_ EV@0_ *IV@000p/0V_ 0.m EV@0_ *IV@n/V_ *IV@0_ 0m m +.V_V_PLL +.V_V_PLL +.VM_V_HPLL +.VM_V_MPLL 0m +.VSUS_V_TX_LVS 0.m +V_V_PEG_G Share V_PEG_PLL 0.u/0V_ +.V_V_PEG_PLL R:0m 0.u/0V_ 0.u/0V_ u/.vv_ PY00T-0Y-N_ R EV@0_ R EV@0_ +.VM_V_SM 0 u/0v_ m +.VM_V_SM_K 0m 0m 0m +.V_V_RT +.V_V_TV +.V_V_Q +.VM_MH_V_HPLL +.V_V_PEG_PLL J 0 H L M K0 K U W V U U U T T T T T R R M L N N U J H V_RT V_RT VQ_RT V TVO V TVO UH VSYN V_RT V_TV.V.V.V.V.V V_RT V_RT V G VSS G V_PLL V_PLL V_HPLL V_MPLL V_LVS VSS_LVS V_PEG_G VSS_PEG_G V_PEG_PLL V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_0 V_SM_ V_SM_NTF_ V_SM_NTF_ V_SM_K_ V_SM_K_ V_TV V_TV V_TV V_TV V_TV V_TV V_Q V_HPLL V_PEG_PLL V_LVS_ V_LVS_ RESTLINE_p0 RT PLL K SM PEG LVS V TVO V_TVO VG_ VSSG_ V_SYN POWER TV TV/RT LVS X SM K MI.V.V.V.V VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_ V_X_NTF XF PEG VTT V_XF_ V_XF_ V_XF_ V_MI V_SM_K_ V_SM_K_ V_SM_K_ V_SM_K_ V_TX_LVS HV V_HV_ V_HV_ V_PEG_ V_PEG_ V_PEG_ V_PEG_ V_PEG_ V_RXR_MI_ V_RXR_MI_ VTTLF VTTLF VTTLF VTTLF.V U U U U U U U U U U T T T0 T T T T T T R R R T U U T T T0 R J0 K K J J 0 0 W0 W V V0 H0 H F H +.0V 0m +.V_X +.V_V_XF +.V_V_MI m +.VSUS_V_SM_K m +.VSUS_V_TX_LVS 0.u/.V_ +V_V_HV V_LVS V_LVS VTX_LVS 00m 00m 00m 0.u/.V_.u/0V_ u/0v_ 00m 0m 0m 0 0.u/0V_ 0 0.u/.V_ EXTERNL.u/0V_ R0 0_ *u/.v_ 0 u/0v_ 0 0.u/0V_ 0u/0V_ +V_PEG.V R 0_ 0 0u/0V_ R 0_ R EV@0_.u/0V_ L R _ 0u/0V_ 0.u/0V_ *IV@000p/0V_ +.V.V.V.V INTERNL +.V +.V +V._SMK_R L L uh_ + 0u/.V_ +.VSUS +.0V *IV@uh_ + *IV@0u/.V_ nh_l u/.vv_ +.VSUS +.0V R _ 0 0.u/0V_ +.V R 0_ +V.S_PEGPLL_F 0 0u/0V_ +V_VSYN R *IV@0_ VGFPLLOW *IV@PZ. +.0V 0 0.u/0V_ n/v_ +.VSUS R *IV@0_ 0m +.V_V_LVS +.0V PZ. +.0V_S R +V_V_HV R0 *IV@00/F_ *IV@0.u/0V_ *IV@n/V_ 0 *IV@u/0V_ R EV@0_ *IV@u/0V_ **IV@0u/0V_ R EV@0_ +V 0_ R 0_ 0.u/0V_ Quanta omputer Inc. PROJET : TE Size ocument Number Rev GMH Power-( of ) Wednesday, January, 00 ate: Sheet of

10 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMH Power-( of ) 0 Wednesday, January, 00 TE Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMH Power-( of ) 0 Wednesday, January, 00 TE Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMH Power-( of ) 0 Wednesday, January, 00 TE N(Power-) VSS_ VSS_00 0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 E0 VSS_0 E VSS_ E VSS_ E VSS_ E VSS_ E VSS_ F VSS_ F VSS_ F VSS_ F0 VSS_ F0 VSS_0 G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G VSS_0 G VSS_ G VSS_ H VSS_ H VSS_ H VSS_ H VSS_ J VSS_ J VSS_ J VSS_ J VSS_0 J VSS_ J VSS_ J VSS_ J VSS_ K VSS_ K VSS_ K VSS_ L VSS_ L VSS_0 L0 VSS_ L VSS_ L VSS_ L VSS_ L VSS_ L VSS_ M VSS_ M VSS_ M VSS_ M VSS_0 M VSS_ M0 VSS_ M VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_0 N VSS_ N VSS_ N VSS_ P VSS_ P VSS_ P VSS_ P VSS_ P0 VSS_ R VSS_ T VSS_0 T VSS_ T VSS_ U VSS_ U VSS_ U0 VSS_ W VSS_ W VSS_ W VSS_0 W VSS_ W VSS_ W VSS_ Y VSS_ Y VSS_ Y VSS_ V VSS_ V VSS_ Y VSS_ Y VSS_ Y VSS_ Y0 VSS_00 Y VSS_0 P VSS_0 T VSS_0 T VSS_0 T VSS_0 R VSS_0 VSS_0 VSS_0 VSS_0 F VSS_0 F VSS_ T VSS_ V VSS_ H0 VSS UJ RESTLINE_p0 VSS UJ RESTLINE_p0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ 0 VSS_ VSS_0 VSS_ VSS_ VSS_ 0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ 0 VSS_ VSS_0 E0 VSS_ E VSS_ E VSS_ F0 VSS_ F VSS_ F VSS_ F VSS_ G VSS_ G VSS_ G VSS_0 G VSS_ G0 VSS_ H VSS_ H0 VSS_ H VSS_ H VSS_ H VSS_ J VSS_ J VSS_ J VSS_0 J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ K0 VSS_ K VSS_ K VSS_ K VSS_0 K VSS_ K VSS_ L VSS_ M VSS_ M VSS_ M VSS_ M VSS_ M VSS_ M VSS_ N VSS_0 N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ P VSS_ P VSS_ P0 VSS_ R VSS_ R VSS_0 R VSS_ R VSS_ R VSS_ R VSS_ T0 VSS_ T VSS_ T VSS_ T VSS_ W VSS_00 W VSS_0 W VSS_0 W VSS_0 W VSS_0 W VSS_0 Y0 VSS_0 Y VSS_0 Y VSS_0 Y VSS_0 Y VSS_0 Y VSS_ Y VSS_ Y0 VSS_ 0 VSS_ 0 VSS_ VSS_ VSS_ 0 VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ 0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ 0 VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ E VSS_ E VSS_ E VSS_0 E0 VSS_ E VSS_ E VSS_ E VSS_ F VSS_ F VSS_ F VSS_ G VSS_ G VSS_ G VSS_0 G VSS_ G VSS_ G VSS_ G VSS_ G VSS_ H VSS_ H0 VSS_ H VSS_ H VSS_ H VSS_0 J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ K VSS_ K VSS_ K VSS_ K VSS_ U VSS_ U VSS_0 U VSS_ U VSS_ U VSS_ U VSS_ U VSS_ V VSS_ V VSS_ W VSS_ W VSS_0 K VSS_ K VSS_ K VSS_ L VSS_ L VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ K0 VSS_ K VSS_ L VSS_ L VSS_ L VSS_0 L VSS_ VSS_ VSS_ VSS UI RESTLINE_p0 VSS UI RESTLINE_p0

11 Strap table(base on checklist Ver.) ll strap are sampled with respect to the leading edge of the GMH Power OK(PWROK) Signal FG[:] Have internal Pull-up FG[:] Have internal Pull-down ny FG signal strapping option not list below should be left N Pin Pin Name Strap description onfiguration FG[:0] FS Frequency Select 00 = FS 00MHz 0 = FS MHz FG[:] FG MI X Select 0 = MI X = MI X(efault) FG FG Intel? Management Engine rypto strap 0 = Intel? Management Engine rypto Transport Layer.Security (TLS) cipher suite with no confidentiality = Intel Management Engine rypto TLS ipher Suite with confidentiality (default) FG FG PI Express Graphics Lane Reversal 0 = Reverse Lanes = Normal operation(efault) FG[:0] FG[:] XOR/LLZ 00 = 0 = XOR Mode Enable 0 = ll-z Mode Enabled = Normal operation(efault) FG[:] FG FS ynamic OT 0 = ynamic OT disable = ynamic OT Enable(efault) FG[:] SVO_TRLT SVO Present 0 = No SVO ard present(efault) = SVO ard Present FG MI Lane Reversal 0 = Normal operation(efault) = Reverse Lanes FG0 SVO/PIe concurrent 0 = Only SVO or PIE is operation(efault) = SVO and PIE are operating simultaneously via the PEG port MI X Select MI Lane Reversal XOR /LLz /lock Un-gating PI Express Graphics SVO Present MH_FG_ Low = MIX High = IMIX(efault) MH_FG_ Low = Normal operation(efault) High = Reverse Lane MH_FG_ MH_FG_ 0 0 onfiguration lock gating disable MH_FG_ Low = Reverse Lane High = Normal operation(efault) Strap define at External HMI control page () MH_FG_ +V 0 XOR Mode Enable () MH_FG_ R *.0K_ R *.0K_ 0 LL-z Mode Enable Normal operation(efault) R *.0K_ FS ynamic OT () MH_FG_ SVO/PIE oncurrent operation MH_FG_ Low = OT isable High = OT Enable(efault) MH_FG_0 Low = Only SVO or PIE is operational(efault) High = SVO andpie are operating simultaneously via the PEG port () MH_FG_ +V () MH_FG_ () MH_FG_ R0 *.0K_ () MH_FG_0 R *.0K_ R *.0K_ R *.0K_ Quanta omputer Inc. PROJET : TE Size ocument Number Rev GMH Strap( of ) Wednesday, January, 00 ate: Sheet of

12 R ual channel / PU M [..0] M [..0] (,) RII HNNEL M [..0] M [..0] (,) RII HNNEL +SMR_VTERM +SMR_VTERM u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ Place one cap close to every pull-up resistor terminated to SMR_VTERM M M RP X +SMR_VTERM M M RP X M M RP X +SMR_VTERM M M RP X (,) (,) M_KE M S# RP X (,) M_KE M RP0 X (,) (,) M_OT M_S# RP X (,) M_KE0 M RP X (,) (,) M_OT M S#0 RP X (,) M S# M RP X (,) M S#0 M 0 RP X (,) M S# M 0 RP X (,) (,) M S# M WE# RP X (,) M_S#0 (,) M RS# RP X M 0 RP X +SMR_VTERM (,) M WE# (,) M S# (,) M_S# RP X M M RP X (,) M_KE M RP X (,) M S# M 0 RP X (,) M_OT (,) M RS# RP0 X M M RP X (,) M_OT0 M RP X M M RP X (,) M_S# M RP X M M RP X M M RP X (,) (,) M M R _ R _ +SMR_VTERM Quanta omputer Inc. PROJET : TE Size ocument Number Rev R RES. RRY Wednesday, January, 00 ate: Sheet of

13 R ual channel / ONN R V(SUS) R-00 each dimm is. R- EH IMM IS. VTERM(SUS) (,) (,) (,) (,) (,) (,) (,) M_KE0 M S# M S#0 M WE# M S# M_S# M_OT +V M Q M Q M QS#0 M QS0 M Q M Q M Q M Q M QS# M QS M Q M Q M Q M Q0 M QS# M QS M Q M Q M Q M Q M M M Q M Q M M M M M M M 0 M Q M Q M QS# M QS M Q M Q M Q0 M Q M M M Q M Q M Q M Q M QS# M QS M Q0 M Q M Q M Q0 M M M Q M Q GT_SM GLK_SM SMR_VREF_IMM +.VSUS N VREF VSS Q0 Q VSS QS#0 QS0 VSS Q Q VSS Q Q VSS QS# QS VSS Q0 Q VSS0 VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS M N VSS Q Q VSS KE0 V N _ V V V0 0/P 0 WE# V S# S# V OT VSS Q Q VSS QS# QS VSS Q Q VSS Q0 Q VSS M VSS Q Q VSS0 Q Q VSS NTEST VSS0 QS# QS VSS Q0 Q VSS Q Q VSS M VSS Q Q VSS S SL V(SP) R_H P00 R SRM SO-IMM (00P) VSS Q Q VSS M0 VSS Q Q VSS Q Q VSS M VSS K0 K0# VSS Q Q VSS VSS0 Q0 Q VSS N M VSS Q Q VSS Q Q VSS QS# QS VSS0 Q0 Q VSS KE V V V 0 V RS# S0# V OT0 V N VSS Q Q VSS M VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS K K# VSS M VSS Q Q VSS Q0 Q VSS QS# QS VSS Q Q VSS S0 S M Q M Q M M M Q M Q M Q M Q M QS# M QS M Q0 M Q M M M M M M 0 M M Q M Q M M M Q M Q M Q M Q M QS# M QS M Q M Q M Q M Q M M M Q M Q M Q M Q M QS# M QS M Q M Q SMR_VREF_IMM M M[0..] () M Q[0..] () M QS[0..] () +.VSUS +.VSUS +.VSUS M QS#[0..] () N M [0..] (,) VREF VSS M Q M Q0 VSS Q M Q0 M Q Q0 Q Q VSS M M0 M QS#0 VSS M0 0 M QS0 QS#0 VSS M Q QS0 Q M Q M Q VSS Q M Q Q VSS 0 M Q Q Q M Q M Q VSS Q M Q Q VSS M M Q M M QS# VSS VSS 0 M QS QS# K0 M_LK_R0 () QS K0# M_LK_R#0 () M Q VSS VSS M Q0 M Q0 Q0 Q M Q Q Q 0 VSS0 VSS R R 0K_ 0K_ SO-IMM0 SP ddress is 0x0 SO-IMM0 TS ddress is 0x0 M Q M Q M M0 M Q M Q M Q M Q M M M Q M Q M M[0..] () M Q[0..] () M QS[0..] () M QS#[0..] () M [0..] (,) M_LK_R () M_LK_R# () M Q0 VSS VSS0 M Q M Q Q Q0 M Q Q Q M QS# VSS VSS M QS QS# N 0 PM_EXTTS# () PM_EXTTS#0 () M M QS M M Q VSS VSS M Q M Q Q Q M Q Q Q M Q VSS VSS 0 M Q M Q Q Q M Q Q Q M M VSS VSS M QS# M QS# M QS N QS 0 M Q VSS VSS0 M Q0 M Q Q Q0 M Q Q Q VSS VSS (,) M_KE 0 KE0 KE M_KE (,) M_KE (,) V V N (,) M S# _ M (,) M (,) M V V M M 0 M M M M V V M M 00 M M 0 0 M M 0 V0 V 0 0 0/P M S# (,) M S# (,) (,) M S# RS# M RS# (,) M RS# (,) (,) M WE# 0 0 WE# S0# M_S# (,) M_S#0 (,) V V (,) M S# S# OT0 M_OT (,) M M_OT0 (,) (,) M_S# S# V V (,) M_OT 0 OT N M Q VSS VSS M Q M Q Q Q M Q Q Q M QS# VSS VSS 0 M M M QS QS# M QS VSS M Q M Q VSS Q M Q M Q Q Q Q VSS 0 M Q M Q0 VSS Q M Q M Q Q0 Q Q VSS M QS# M M VSS QS# M QS M QS 0 M Q VSS VSS M Q M Q Q Q M Q Q Q M Q VSS0 VSS M Q M Q Q Q 0 M Q Q Q VSS VSS NTEST K M_LK_R () M_LK_R () M_LK_R# () M QS# VSS0 K# M_LK_R# () M QS QS# VSS 0 M M QS M M Q VSS VSS M Q M Q Q0 Q M Q0 Q Q M Q VSS VSS 0 M Q0 M Q Q Q0 M Q Q Q M M VSS VSS M QS# M QS# M QS M Q VSS QS 0 M Q Q VSS M Q Q Q M Q GT_SM VSS Q () GT_SM GLK_SM S VSS R0 0K_ () GLK_SM SL S0 +V 00 R0 0K_ V(SP) S R_0.H P00 R SRM SO-IMM (00P) H: mm H: 0.mm LOK 0, LOK, KE 0, KE, +V SO-IMM SP ddress is 0x SO-IMM TS ddress is 0x lose to IMM0 +.VSUS +.VSUS SMR_VREF_IMM lose to IMM +.VSUS +.VSUS + *0u/.V_ 0.u/0V_ 0.u/0V_ + *0u/.V_ 0.u/0V_ SMR_VREF_IMM 0.u/0V_ 0.u/.V_.u/.V_ 0 0.u/0V_.u/.V_ 0.u/0V_.u/.V_ R0.u/.V_ 0.u/0V_ SMR_VREF_IMM *0K_.u/.V_ 0 0.u/0V_.u/.V_ 0.u/0V_.u/.V_ 0 0.u/0V_ R 0_ R0 *0K_ +V +V Wednesday, January, 00 ate: Sheet of +SMR_VREF +.VSUS Quanta omputer Inc. PROJET : TE Size ocument Number Rev R SO-IMM(00P).u/.V_.u/.V_.u/.V_.u/.V_ 0.u/.V_ 0.u/0V_.u/.V_ 0 0.u/0V_

14 RT VRT S- +VPU H00H-0 VRT u/0v_ VRT_ H00H-0 R 0K_ elay ~ms p/0v_ R K_ N RT_ONN +VPU R K/F_ R.K/F_ R0 E K_ VRT_ R M_ MOS Setting G lear MOS Short Keep MOS Open R VRT_ K/F_ ST isable VRT_ Q MMT0 u/0v_ () () () () () () () Z_SIN0 Z_SIN ST_LE# ST_RXN0 ST_RXP0 ST_TXN0 ST_TXP0 +.V_PIE Y.KHZ Z_SIN 0 R T T 00p/V_ 00p/V_ 00p/V_ 00p/V_ T T./F_ LK_KX LK_KX RTRST# SM_INTRUER# IH_INTVRMEN LN00_SLP GLN_OMP_S Z_LK Z_SYN Z_RST# Z_SOUT ST_LE# ST_RXN0_ ST_RXP0_ ST_TXN0_ ST_TXP0_ LRQ# GTE0 RIN# H_THERMTRIP_R IH_TP P0 P P P P P P P P P P0 P P P P P P0 P P L0 (,) L (,) L (,) L (,) LFRME# (,) T0 LRQ# () GTE0 () H_0M# () IH_PRSTP# (,,) H_PSLP# () H_PWRG () H_IGNNE# () H_INIT# () H_INTR () RIN# () H_NMI () H_SMI# () H_STPLK# () R /F_ P[:0] () P[:0] () PS# () PS# () +.0V_V_PU_IO R./F_ +.0V_V_PU_IO RIN# GTE0 H_FERR# () Placement close S L<" PM_THRMTRIP# (,) +V +V G *SHORT_P 0 p/0v_ R R R R R 0M_ T T 0K_ 0K_ T 0K_ 0K_ G F F F E0 0 H J J E J H H E E0 G F0 F F H H G G J J F F E E U RTX RTX RTRST# INTRUER# INTVRMEN LN00_SLP GLN_LK LN_RSTSYN LN_RX0 LN_RX LN_RX LN_TX0 LN_TX LN_TX GLN_OK#/GPIO GLN_OMPI GLN_OMPO H_IT_LK H_SYN H_RST# H_SIN0 H_SIN H_SIN H_SIN H_SOUT H_OK_EN#/GPIO H_OK_RST#/GPIO STLE# ST0RXN ST0RXP ST0TXN ST0TXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP IH LN / GLN RT IE PU LP ST FWH0/L0 FWH/L FWH/L FWH/L FWH/LFRME# LRQ0# LRQ#/GPIO 0GTE 0M# PRSTP# PSLP# FERR# PUPWRG/GPIO IGNNE# INIT# INTR RIN# NMI SMI# STPLK# THRMTRIP# TP S# S# E F G F G E F G F E G F E 0 H G E V U V T V T T T R T V V U V U Y Y T R./F_ R *0_ R 0K_ R.K_.onnect to : ST[:0]RXp/n, STRIS, STRIS#, ST_LKP, STLKN.N: ST[:0]TXp/n, STLE#.VccSTPLL should be connected directly to Vcc_,Filter cap are not required.ios disable () () LK_PIE_ST# LK_PIE_ST R./F_ ST_IS L<00mils G G ST_LKN ST_LKP STRIS# STRIS IHM REV.0 IOR# IOW# K# IEIRQ IORY REQ W W Y Y Y W PIOR# () PIOW# () PK# () IRQ () PIORY () PREQ () S Strap IH-M Internal VR Enable strap (Internal VR for Vccsus_0,VccSus_ and VccL_) IH-M LN00_SLP Strap (Internal VR for VccLN_0 and VccL.0) XOR hain Entrance Strap IH_RSV0 H_SOUT escription H IT_LK_UIO R Z_SOUT R _ R0 *IHM@_ Z_SOUT_UIO () Z_SOUT_HMI () INTVRMEN Low = Internal VR disable High = Internal VR enable(efault) LN00_SLP Low = Internal VR disable High = Internal VR enable(efault) RSV Enter XOR hain Normal opration(efault) *_ 0 *p/0v_ Z_SYN R0 _ R *IHM@_ Z_SYN_UIO () Z_SYN_HMI () Set PIE port config bit Z_LK R _ IT_LK_UIO IT_LK_UIO () VRT VRT +V IT_LK_HMI R *IHM@_ IT_LK_HMI IT_LK_HMI () R0 K/F_ IH_INTVRMEN R0 *0_ R K/F_ LN00_SLP R *0_ R *K_ Z_SOUT R *K_ IH_TP () R *_ *p/0v_ Z_RST# R0 _ R00 *IHM@_ Z_RST#_UIO () Z_RST#_HMI () Quanta omputer Inc. PROJET : TE

15 S-PIE/US/MI To New ard To MINI- To MINI- To MINI- To LN To MINI- () PIE_RXN () PIE_RXP () PIE_TXN () PIE_TXP () PIE_RXN () PIE_RXP () PIE_TXN () PIE_TXP () PIE_RXN () PIE_RXP () PIE_TXN () PIE_TXP () PIE_RXN () PIE_RXP () PIE_TXN () PIE_TXP () PIE_RXN () PIE_RXP () PIE_TXN () PIE_TXP () PIE_RXN () PIE_RXP () PIE_TXN () PIE_TXP (,) USO#_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ T0 T T T T (,) USO#0 R 0_ R 0_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ SPI_S# USO#0 USO# USO# USO# USO# USO# USO# USO# USO# USO# U P PERN P PERP N PETN N PETP M PERN M PERP L PETN L PETP K PERN K PERP J PETN J PETP H PERN H PERP G PETN G PETP F PERN F PERP E PETN E PETP E F J G G E F G J H PERN/GLN_RXN PERP/GLN_RXP PETN/GLN_TXN PETP/GLN_TXP SPI_LK SPI_S0# SPI_S# SPI_MOSI SPI_MISO O0# O#/GPIO0 O#/GPIO O#/GPIO O#/GPIO O#/GPIO O#/GPIO0 O#/GPIO O# O# IHM REV.0 PI-Express irect Media Interface SPI US MI0RXN MI0RXP MI0TXN MI0TXP MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MI_LKN MI_LKP MI_ZOMP MI_IROMP USP0N USP0P USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USRIS# USRIS V V U U Y Y W W T T Y Y G G H H H H J J K K K K L L M M M M N N F F MI_RXN0 () MI_RXP0 () MI_TXN0 () MI_TXP0 () MI_RXN () MI_RXP () MI_TXN () MI_TXP () MI_RXN () MI_RXP () MI_TXN () MI_TXP () MI_RXN () MI_RXP () MI_TXN () MI_TXP () LK_PIE_IH# () LK_PIE_IH () MI_IROMP_R USP0- () USP0+ () USP- () USP+ () USP- () USP+ () USP- () USP+ () USP- () USP+ () USP- () USP+ () USP- () USP+ () USP- () USP+ () USP- () USP+ () US_RIS_PN R L<00mils./F_ +.V_PIE R./F_ ohm L<00mils To US OR To Finger Printer To luetooth To amera To Felica To WLN To M/ US To M/ US To New ard +V SWP Override strap PI_GNT# Low = swap override enabled High = efault GNT# R *K_ IH oot IOS select PI_GNT#0 SPI_S# oot IOS Location 0 SPI(efault) 0 PI LP SPI_S# R *K_ GNT0# R *K_ +V RP SERR# INTH# REQ0# INTF# 0 INTE#.KX S-PI (,) [0..] () INT# () INT# T INT# INT# INT# INT# 0 E 0 E G 0 F E E E E F 0 U PIRQ# PIRQ# PIRQ# PIRQ# PI ROUTING TLE ISEL REQ0# / GNT0# REQ# / GNT# 0 PI REQ0# GNT0# REQ#/GPIO0 GNT#/GPIO REQ#/GPIO GNT#/GPIO REQ#/GPIO GNT#/GPIO INTERUPT INT# INT# /E0# /E# /E# /E# IRY# PR PIRST# EVSEL# PERR# PLOK# SERR# STOP# TRY# FRME# PLTRST# PILK PME# Interrupt I/F IHM REV.0 PIRQE#/GPIO PIRQF#/GPIO PIRQG#/GPIO PIRQH#/GPIO REQ0# GNT0# E REQ# GNT# REQ# F GNT# REQ# 0 GNT# E F E IRY# G EVSEL# PERR# LOK# F0 SERR# STOP# TRY# FRME# G PLT_RST-R# 0 PLK_IH G F INTE# G INTF# F INTG# INTH# R EVIE OZT 0 T T *0_ REQ0# () GNT0# () REQ# () GNT# () E0# (,) E# (,) E# (,) E# (,) IRY# (,) PR (,) PIRST# (,) EVSEL# (,) PERR# () SERR# () STOP# (,) TRY# (,) FRME# (,) PLK_IH () PI_PME# (,) RT_SENSE# (0,) R R 0_ PLT_RST-R# R 00K_ EV@0_ GFXRST# () PLTRST#_N () +V_S 0.u/0V_ U TSH0FU USO# USO# USO# USO# +V_S USO# USO#0 REQ# EVSEL# FRME# STOP# +V LOK# PERR# IRY# INT# +V PLTRST# (,,,,,,) RP 0.KX R R RP 0.KX RP 0.KX.K_.K_ +V_S USO# USO# USO# USO# +V_S +V_S +V INTG# TRY# REQ# +V INT# INT# INT# REQ# Quanta omputer Inc. PROJET : TE Size ocument Number Rev IHM PIE( of )/ IOS Wednesday, January, 00 ate: Sheet of

16 S-GPIO () PM_STPPI# () PM_STPPU# () S_GPIO () S_GPIO () FM_INT +V R *0K_ () R *0K_ R 0_ FM_ET R 0_ R 0_ MH_IH_SYN# (,,,) (,,,) () () () (,) SLK ST L_RST# PM_MUSY# LKRUN# (,,) PIE_WKE# (,,) SERIRQ () THERM_LERT# () () () () () SYS_RST# Port_# SI# RST_H# SPKR IH_TP T T R 0_ SLK ST L_RST# SMLINK0 SMLINK RI# LP_P# SYS_RST# SM_LERT# LKRUN# PIE_WKE# SERIRQ THERM_LERT# VR_PWRG_LKEN IH_TP KSMI#_IH SI# OR_I0 OR_I LOW_ET OR_I GPIO RST_H# IH_GPIO IH_GPIO SPKR MH_IH_SYN#_R U J SMLK SMT G LINKLERT# SMLINK0 E SMLINK F RI# F SUS_STT#/LPP# SYS_RESET# G MUSY#/GPIO0 G SMLERT#/GPIO E0 STP_PI#/GPIO G STP_PU#/GPIO H LKRUN#/GPIO E WKE# F SERIRQ THRM# J0 VRMPWRG J TP J TH/GPIO J TH/GPIO H TH/GPIO E GPIO GPIO G TH0/GPIO H GPIO E GPIO0 G0 SLOK/GPIO H QRT_STTE0/GPIO QRT_STTE/GPIO G STLKREQ#/GPIO F SLO/GPIO J STOUT0/GPIO 0 STOUT/GPIO SPKR J MH_SYN# J TP IHM REV.0 SM SYS GPIO ST locks GPIO Power MGT MIS GPIO ontroller Link ST0GP/GPIO STGP/GPIO STGP/GPIO STGP/GPIO LK LK SUSLK SLP_S# SLP_S# SLP_S# S_STTE#/GPIO PWROK PRSLPVR/GPIO TLOW# PWRTN# LN_RST# RSMRST# K_PWRG LPWROK SLP_M# L_LK0 L_LK L_T0 L_T L_VREF0 L_VREF L_RST# MEM_LE/GPIO ME_E_LERT/GPIO0 E_ME_LERT/GPIO WOL_EN/GPIO J J0 F G G G G F H E J E H0 G E E J F E F F H J J J F G OR_I OR_I GPIO GPIO M_IH LKUS_ SLP_S# SLP_S# SLP_S# IH_PWROK PM_PRSLPVR_R PM_TLOW#_R NSWON# PM_LN_ENLE_R RSMRST#_R EPWROK L_VREF0_S L_VREF_S IH_GPIO HPT IH_GPIO HPINT R 00_ R 00_ R 00_ R T PM_PRSLPVR *0_ T T PLTRST# R 0_ T LKUS_ M_IH R R0 *0_ *_ M_IH () LKUS_ () SUS# () *0P_ *0p/0V_ SUS# () PM_PRSLPVR (,) NSWON# () PM_LN_ENLE_R R *0K_ +V PLTRST# (,,,,,,) R 0K_ Internal LN disable. 0K P K_PWRG () EPWROK () MPWROK () +V_S +V L_LK0 () R R L_LK ().K/F_.K/F_ L_T0 () L_T () L_RST#0 () R R 0 HPT () /F_ 0.u/0V_ /F_ 0.u/0V_ HPINT () +V_S 0.u/0V_ () VR_PWRG_K0# U +V 0.u/0V_ VR_PWRG_LKEN (,,) ELY_VR_PWRGOO ELY_VR_PWRGOO EPWROK R 00K_ IH_PWROK U TSH0FU NSZ0 +V +V +V +V +V +V +V_S R 00K_ R IEHM@0K_ R MIN@0K_ R *GS@0K_ R L@0K_ R NEW@0K_ R R lways mount 0K_ R0 R0 lways mount 0K_ No Reboot strap OR_I OR_I OR_I OR_I OR_I0 LOW_ET FM_ET LOW_ET () FM_ET () SPKR Low = efault High = No Reboot +V R R R R R R R *WOHM@0K_ *LOW@0K_ WOGS@0K_ *LE@0K_ *@0K_ *0K_ *0K_ R *0_ SPKR R *0K_ GPIO THERM_LERT# SERIRQ R R R0 0K_.K_ 0K_ +V_S With GS need stuff R and N R W/O HMI stuff R and N R RSMRST#_R Q MMT0 RSMRST# () LKRUN# MH_IH_SYN#_R L_RST# KSMI#_IH SI# IH_GPIO RST_H# GPIO GPIO PM_PRSLPVR R R R0 R0 R0 R R R0 R0 R.K_ *0K_ 0K_ 0K_ 0K_ 0K_ 0K_.K_.K_ 00K_ SMLINK0 SMLINK SYS_RST# NSWON# IH_GPIO HPT RI# SLK ST R R0 R R Internal Pull up R R R R0 R 0K_ 0K_ 0K_ *0K_ *0K_ *0K_ 0K_.K_.K_ hange oard I to I detect and modify Low ost board detect oard I NEW R R US FL Panel LE Panel W/ G-SENSOR W/O G-SENSOR Main stream I Low ost I W/ HMI W/O HMI I H L I H L I H L I H L I0 H L M/L FM R0 0K_ R.K_ V V R.K_ +V_S IH_PWROK IH_GPIO HPINT IH_GPIO R R R0 R 0K_ 0K_ *0K_ 0K_ SM_LERT# R PIE_WKE# R PM_TLOW#_R R0 0K_ K_.K_ W/O Low ost board W Low ost W/O FM W FM H L H L Quanta omputer Inc. PROJET : TE Size ocument Number Rev IHM GPIO( of ) Wednesday, January, 00 ate: Sheet of

17 +V.S_VPORE_IH +.0V_S VMIPLL_IH VMIPLL_+.V +.V_MI +V._ST_IH +V.S_IE_IH +V_.V_H_IO_IH TP_VSUS_0_IH_ TP_VSUS_0_IH_ TP_VSUS IH_ TP_VSUS IH_ TP_VL_0_IH +V._IH +V._US_IH +V.S_PI_IH +V.M_IH VL INT_IH +VREF_S +VREF_SUS_S +.V_US +.V_PLL +.V_ST +.V_ST TP_VLN_0_IH_ TP_VLN_0_IH_ +V_VLN +.V_VGLNPLL +.V_VGL +V_GLN +V._MI_IH +VSUSH TP_VLN_0_IH_ TP_VLN_0_IH_ TP_VL_0_IH TP_VSUS_0_IH_ TP_VSUS IH_ TP_VSUS IH_ TP_VSUS_0_IH_ +.V_PLL_RR +.0V +.V +.V +.0V +V +V +V_S VRT +V +V_S +V_S +.V +.V +V +.V +.V_PIE +V +.V_PIE +V +.0V_V_PU_IO +V_S +V Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : IHM Power( of ) Wednesday, January, 00 TE Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : IHM Power( of ) Wednesday, January, 00 TE Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : IHM Power( of ) Wednesday, January, 00 TE 0 Hsin modify hange P value from 0.u to u follow L REV_0 u m m m m 0m V :0m m 0m m m m VSUS_:m m m V_:m m 0m m 0m 0 0.u/0V_ 0 0.u/0V_ T T PZ. PZ..u/.V_.u/.V_ R 0_ R 0_ R 0_ R 0_ u/0v_ u/0v_ *u/.vv_ *u/.vv_ 0.u/0V_ 0.u/0V_ 0 PZ. 0 PZ. u/0v_ u/0v_ R 0_ R 0_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ L 0uh_ V000MN0 L 0uh_ V000MN0 + *0u/.V_ + *0u/.V_ R 0_ R 0_ 0.u/0V_ 0.u/0V_ R 0_ R 0_ 0.u/0V_ 0.u/0V_ u/0v_ u/0v_ 0 0.u/V_ 0 0.u/V_ R _ R _ R 0_ R 0_ 0.u/V_ 0.u/V_ R 0_ R 0_ R 0_ R 0_ R 0_0 R 0_0 0 0.u/0V_ 0 0.u/0V_ u/.vv_ u/.vv_ R 0_ R 0_ R 0_ R 0_ u/.vv_ u/.vv_ u/0v_ u/0v_ 00.u/.V_ 00.u/.V_ 0.u/0V_ 0.u/0V_ R 0_ R 0_ 0 0.u/0V_ 0 0.u/0V_ 0.u/V_ 0.u/V_ 0 0.u/0V_ 0 0.u/0V_ 0 0.u/0V_ 0 0.u/0V_ 0.u/0V_ 0.u/0V_ T T.u/.V_.u/.V_ T T R 0_ R 0_ L0 PY00T-0Y-N_ L0 PY00T-0Y-N_ R 0_ R 0_ 0.u/V_ 0.u/V_ R 0_ R 0_ 0.u/0V_ 0.u/0V_ R 0_ R 0_ 0 n/v_ 0 n/v_ R 0_ R 0_ 0 0u/0V_ 0 0u/0V_ 0.u/0V_ 0.u/0V_.u/.V_.u/.V_ 0.u/0V_ 0.u/0V_ 0 0.u/0V_ 0 0.u/0V_.u/.V_.u/.V_ 0.u/0V_ 0.u/0V_ u/0v_ u/0v_ 0.0u/V_ 0.0u/V_ R 0_ R 0_ 0 u/.v_ 0 u/.v_ 0 0u/0V_ 0 0u/0V_ VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] 0 VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] E VSS[0] E VSS[0] E VSS[0] E VSS[0] VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[0] F VSS[00] F VSS[0] F VSS[0] F VSS[0] F VSS[0] G VSS[0] G VSS[0] H0 VSS[0] H VSS[0] H VSS[0] H VSS[00] H VSS[0] F VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[0] J VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] 0 VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[0] F VSS[00] E VSS[0] F VSS[0] F VSS[0] F VSS[0] G VSS[0] E VSS[0] G0 VSS[0] G VSS[0] G VSS[0] G VSS[00] G VSS[0] G VSS[0] G VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[0] J VSS[0] J VSS[00] J VSS[0] J VSS[0] J VSS[0] J VSS[0] K VSS[0] K VSS[0] K VSS[0] K VSS[0] K VSS[00] L VSS[0] L VSS[0] L VSS[0] L VSS[0] L VSS[0] L VSS[0] L VSS[0] M VSS[0] M VSS[0] M VSS[0] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] N VSS[] N VSS[] N VSS[0] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[0] N VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[0] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[0] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] U VSS[] U VSS[] U VSS[0] U VSS[] U VSS[] U VSS[] U VSS[] U VSS[] U VSS[] U VSS[] U VSS[] V VSS[] V VSS[0] V VSS[] V VSS[] W VSS[] W VSS[] W VSS[] Y VSS[] Y VSS[] Y VSS[] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] H VSS_NTF[0] H VSS_NTF[0] J VSS_NTF[0] J VSS_NTF[0] J VSS_NTF[0] J VSS_NTF[] VSS_NTF[] VSS[] VSS[0] VSS[] VSS[] VSS[] U VSS[0] K VSS[] W UE IHM REV.0 UE IHM REV.0 L PY00T-0Y-N_ L PY00T-0Y-N_ 0u/0V_ 0u/0V_ R 00/F_ R 00/F_ VREF[] VREF[] T VREF_SUS G V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] E V [0] E V [] E V [] F V [] F V [] G V [] H V [] H V [] J V [] J V [] K V [0] K V [] L V [] L V [] L V [] M V [] M V [] N V [] N V [] N V [] P V [0] P V [] R V [] R V [] R V [] R V [] T V [] T V [] T V [] T V [] T V [0] U V_[0] F VMIPLL R V [0] E V [0] F V [0] G V [0] H V [0] J VSTPLL J V_[0] V [0] V [0] V [0] V [0] V [0] VUSPLL VLN_0[] F VLN_0[] G V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] E V_0[0] F V_0[0] G V_0[0] L V_0[0] L V_0[] L V_0[] L V_0[] L V_0[] L V_0[] M V_0[] M V_0[] P V_0[] P V_0[] T V_0[0] T VLN_[] F VLN_[] G0 VH VSUSH V_PU_IO[] V_PU_IO[] V_[0] V_[0] U V_[0] V V_[0] W V_[] W V_[] W V_[] Y V_[] V_[] V_[] V_[] V_[] V_[0] V_[] V_[] E0 V_[] E V_[] F VRT VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[0] G0 VSUS_[0] H VSUS_[0] P VSUS_[0] P VSUS_[0] VSUS_[0] N VSUS_[] P VSUS_[] P VSUS_[] P VSUS_[] P VSUS_[] P VSUS_[] R VSUS_[] R VSUS_[] R V [] 0 V [] V [] V [] V [] G V [] G VSUS_0[] J VSUS_0[] F0 V [0] F V [] L V [] L V [] M V [] M VSUS_[0] V_[] V [] W V_0[] U V_0[] V V_0[] V V_0[] V V_0[] U V_0[] V V_0[] V V_0[] V VGLN_[] VGLN_[] VGLN_[] VGLN_[] VGLN_[] VGLN_ VGLNPLL V_[0] F V_[0] V_[0] E V_[0] VSUS_[] R V [] H VSUS_[] V [] V [] VSUS_[] J V_MI[] E V_MI[] E VL_0 G VL_[] G VL_[] F0 VL_ V [] W V [] V V [] U V [] Y V [] V V [] V ORE VGP TX RX IE US ORE PI GLN POWER VP_ORE VPSUS VPUS UF IHM REV.0 ORE VGP TX RX IE US ORE PI GLN POWER VP_ORE VPSUS VPUS UF IHM REV.0 L FMJHS0-T_ L FMJHS0-T_ 0u/0V_ 0u/0V_ 0.u/0V_ 0.u/0V_ R _ R _ 0 0.u/V_ 0 0.u/V_ R0 0_ R0 0_