Penryn 479 ufcpga. NB Cantiga

Transcription

1 OM MRK INT VG STUFF FOR EXT VG STUFF FOR UM or VG X'TL.MHz LOK GENERTOR IS: SELGO: SLGSPTTR RII SO-IMM SO-IMM P P ual hannel R / MHz Penryn ufpg N antiga FS / MHz P, P, P, P, P, P, P P, P (GM/ PM/ GL) Thermal Sensor (G-PU) PIE X LVS RG P NVII NM-GE VRM RII G P-P Fan river (G) P EXT_LVS EXT_RT INT_LVS INT_RT R PWR TPS THERML PROTETION SWITH IRUIT P P ISHRGER P VG ORE OZ P P RT LVS HRGER ISL P /V SYS PWR P ISL PU ORE PWR OZLN.V UPQ P P P P H (ST) * X MI interface Ext US Port x US, P Int US Port x US P luetooth US US P P udio mplifier GL P O (ST) udio OE (X) P MI Jack P P P Int. MI P ST ST US. zalia S IHM P,P,P,P LP E (WPLG) SPI ROM P Touch Pad P P X'TL.KHz X'TL.KHz PI-Express US K/ OON. P Media ardreader (RTS) US ard Reader onnector P P PIE- theros Giga-LN (R) Transformer RJ PIE- P X'TL MHz P P Mini ard WLN P Int. Speaker P Quanta omputer Inc. PROJET : ZRE Size ocument Number Rev lock iagram ate: Tuesday, May, Sheet of

2 lock Generator (LK) V PI/M RS= ohm when one loading = ohm when two loading [] PLK_EUG [] PLK_ [] PLK_IH L KPHST. *p/v_ PLK_EUG_R *p/v_ PLK R.u/V_ R _ R _ R _ *p/v_ PLK_IH_R *.u/v_ PLK_EUG_R PLK R PLK_IH_R.u/V_ V_LK.u/V_ u/.v_ *.u/v_.u/v_ p/v_ p/v_ G_XIN Y The trace within mil.mhz G_XOUT [] STLKREQ# R /F_ STLKREQ#_R [] LN_LKREQ# R /F_ LN_LKREQ#_R PLK_EUG_R PLK R PLK_PM_R PLK_IH_R PU_SEL R.K_ R _ [] LKUS_ R _ FS [] LK_ard PU_SEL PU_SEL R K_ [] M_IH R _ FS *p/v_ U V_PI V_ V_PLL V_SR V_PU V_REF XTL_IN XTL_OUT V_I/O V_PLL_I/O V_SR_I/O_ V_SR_I/O_ V_SR_I/O_ V_PU_I/O PU_STOP# PI_STOP# KPWRG/P# PU_ PU_# PI_/LKREQ_# PU MH PI_/LKREQ_# PU MH# PI_ SR_/PU_ITP PI_ SR_#/PU_ITP# ^PI_/LLK_SEL PIF_/ITP_EN N US_MHz/FS_ FS_/TEST_MOE LLK/M LLK#/M_SS REF/FS_/TEST_SEL LK_REFSSLK_R LK_REFSSLK#_R V_LK u/.v_.u/v_.u/v_ PM_STPPU# [] PM_STPPI# [] K_PWRG [] LK_PU_LK [] LK_PU_LK# [] LK_MH_LK [] LK_MH_LK# [] LK V power range.v~.v *.u/v_.u/v_.u/v_ L KPHST..u/V_.V Pin : It acts as a level sensitive strobe to latch the FS pins and other multiplexed inputs. [,,,] [,,,] *p/v_ FS PT_SM PLK_SM Q MNK- V V Q MNK- R K_ R K_ GT_SM GLK_SM LK_REFLK_R LK_REFLK#_R GLK_SM GT_SM SR_/OT_ SR_ SR_#/OT_# SR_# SR_/LKREQ_# SL SR_#/LKREQ_# S SR_ SR_# SR_ SR_# SR_/LKREQ_F# VSS_PI SR_#/LKREQ_E# VSS_ SR_ VSS_I/O SR_# VSS_PLL SR_ VSS_SR_ SR_# VSS_SR_ SR_/LKREQ_H# VSS_SR_ SR_#/LKREQ_G# VSS_PU VSS_REF LK-GEN_SLGSPTTR LK_PIE_SR LK_PIE_SR# LK_PIE_SR LK_PIE_SR# LK_MH_OE#_ LK_PIE_SR# LK_PIE_ST [] LK_PIE_ST# [] T T LK_PIE_LN [] LK_PIE_LN# [] LK_PIE_IH [] LK_PIE_IH# [] T T LK_PIE_MINI [] LK_PIE_MINI# [] LK_PIE_GPLL [] LK_PIE_GPLL# [] From GMH From eisceret R R RN LK_REFLK_R LK_REFLK#_R RN LK_REFSSLK_R LK_REFSSLK#_R /F_ /F_ RN LK_REFLK_R LK_REFLK#_R RN LK_REFSSLK_R LK_REFSSLK#_R IV@_PR IV@_PR EV@_PR EV@_PR LK_MH_OE# [] MINI_LKREQ# [] LK_REFLK [] LK_REFLK# [] LK_REFSSLK [] LK_REFSSLK# [] LK_PIE_VG [] LK_PIE_VG# [] M_NONSS [] M_SS [] PU lock select Pin // : For Pin PU frequency selection SEL Frequency Select Table FS FS FS Frequency Mhz V R R R R K_ K_ *K_ K_ STLKREQ#_R LN_LKREQ#_R PLK_EUG_R R LK_PIE_SR# Strap table LKREQ_# ontrol SR_ & SR_ LKREQ_# ontrol LLK & SR_ *K_ Reserve overclocking [] PU_SEL [] PU_SEL PU_SEL R PU_SEL R *short *short MH_SEL [] MH_SEL [] Mhz Mhz Mhz Mhz R EV@K_ PLK_PM_R R IV@K_ Pin : For Pin / and / selection = LLK & OT for internal graphic controller support = M & M_SS &SR_ for external graphic controller support PU_SEL R *short [] PU_SEL MH_SEL [] Mhz Mhz Pin : For Pin / selection = PU_ITP = SR_ PLK_IH_R R K_ Quanta omputer Inc. PROJET : ZRE Size ocument Number Rev LOK GENERTOR ate: Tuesday, May, Sheet of

3 [] H_#[..] [] H_ST# [] H_REQ#[..] [] H_#[..] [] H_ST# [] H_M# [] H_FERR# [] H_IGNNE# [] H_STPLK# [] H_INTR [] H_NMI [] H_SMI# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_REQ# H_REQ# H_REQ# H_REQ# H_REQ# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# U J []# L []# L []# K []# M []# N []# J []# N []# P []# P []# L []# P []# P []# R []# M ST[]# R GROUP_ R GROUP_ K REQ[]# H REQ[]# K REQ[]# J REQ[]# L REQ[]# Y []# U []# R []# W []# U []# Y []# U []# R []# T []# T []# W []# W []# Y []# U []# V []# W []# []# []# []# V ST[]# M# FERR# IGNNE# IH STPLK# LINT LINT SMI# M RSV[] N RSV[] T RSV[] V RSV[] RSV[] RSV[] RSV[] RSV[] F RSV[] RESERVE XP/ITP SIGNLS ONTROL S# NR# PRI# EFER# RY# SY# R# IERR# INIT# LOK# RESET# RS[]# RS[]# RS[]# TRY# HIT# HITM# PM[]# PM[]# PM[]# PM[]# PRY# PREQ# TK TI TO TMS TRST# R# THERML PROHOT# THERM THERM THERMTRIP# H LK LK[] LK[] H E G H F E F H F F G G G E H_IERR# XP_PM# XP_PM# XP_PM# XP_PM# XP_PM# XP_PM# XP_TK XP_TI XP_TO XP_TMS XP_TRST# SYS_RST# H_PROHOT#_ H_THERM H_THERM PM_THRMTRIP# R _ T T T T T H_S# [] H_NR# [] H_PRI# [] H_EFER# [] H_RY# [] H_SY# [] H_REQ# [].V H_INIT# [] H_LOK# [] H_PURST# [] H_RS# [] H_RS# [] H_RS# [] H_TRY# [] H_HIT# [] H_HITM# [] onnect it to PU R# is for ITP debug port or PU interposer (like IE) to reset the system SYS_RST# [] LK_PU_LK [] LK_PU_LK# [].V R K/F_ R K/F_ Layout note: H_GTLREF: Zo= ohm L<.", /*VP-% [] H_#[..] [] H_STN# [] H_STP# [] H_INV# [] H_#[..] [] H_STN# [] H_STP# [] H_INV# [] PU_SEL [] PU_SEL [] PU_SEL H_#[..] H_#[..] R R T T T T T H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# U E []# F []# E []# G []# F []# G []# E []# E []# K []# G []# J []# J []# H []# F []# K []# H []# J STN[]# H STP[]# H INV[]# N []# K []# P []# R []# L []# M []# L []# M []# P []# P []# P []# T []# R []# L []# T []# N []# L STN[]# M STP[]# N INV[]# H_GTLREF *K_ PU_TEST GTLREF *K_ PU_TEST TEST PU_TEST TEST PU_TEST TEST F PU_TEST TEST F PU_TEST TEST PU_TEST TEST TEST SEL[] SEL[] SEL[] Penryn T GRP T GRP MIS T GRP T GRP []# []# []# []# []# []# []# []# []# []# []# []# []# []# []# []# STN[]# STP[]# INV[]# []# []# []# []# []# []# []# []# []# []# []# []# []# []# []# []# STN[]# STP[]# INV[]# OMP[] OMP[] OMP[] OMP[] PRSTP# PSLP# PWR# PWRGOO SLP# PSI# Y V V V T U U Y W Y W W Y U E E F E F E F R U Y E E H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# OMP OMP OMP OMP R R R R H_#[..] H_#[..]./F_./F_./F_./F_ H_#[..] [] H_STN# [] H_STP# [] H_INV# [] H_#[..] [] Layout note: comp,: Zo=.ohm, L<." comp,: Zo=ohm, L<." Layout note: PRSTP#, aisy hain (S>Power>N>PU) H_STN# [] H_STP# [] H_INV# [] For ual ore IH_PRSTP# [,,] H_PSLP# [] H_PWR# [] H_PWRG [] H_PUSLP# [] PSI# [] Penryn Thermal Trip.V PU Thermal monitor (THM) V XP PU/P V [,,,] ELY_VR_PWRGOO.V Q MNK- R _ V_TH SYS_RST# R *K_.V [,] PM_THRMTRIP# Processor hot PM_THRMTRIP# R _ Q MMT SYS_SHN# [,] No use Thermal trip PU side still PU ohm. Use Thermal trip can share PU at S side [] N_MLK [] N_MT V R *K_ U SLK S LERT# OVERT# V XP XN GN.u/V_ H_THERM p_ H_THERM XP_TO XP_TI XP_TMS XP_PM# XP_TK XP_TRST# R R R R R R *./F_./F_./F_./F_./F_./F_ H_PROHOT#_.V R _ R No use PROHOT PU side still PU ohm. Use PROHOT to optional receiver PU side PU ohm and through isolat.k ohm to receiver side *_ H_PROHOT# [] [] THERM_LERT# R *_ G-PU V R K_ [] THER_OVERT# GMT L Use p WINON LL heck XP_RESET# and XP_TO reserve for XP Quanta omputer Inc. PROJET : ZRE Size ocument Number Rev PU Host us ate: Tuesday, May, Sheet of

4 U V_ORE V_ORE V: (Low power type) VSS[] VSS[] P V: (Standard type) VSS[] VSS[] P U VSS[] VSS[] P V[] V[] VSS[] VSS[] R V[] V[] VSS[] VSS[] R VSS[] VSS[] R V[] V[] V[] V[] VSS[] VSS[] R Layout Note: *u/v_ F u/.v_ u/.v_ VSS[] VSS[] T *u/v_ u/.v_ *u/v_ V[] V[] *u/v_ *u/v_ V[] V[] Inside PU center cavity in rows VSS[] VSS[] T V[] V[] VSS[] VSS[] T V[] V[] VSS[] VSS[] T V[] V[] VSS[] VSS[] U V[] V[] VSS[] VSS[] U V[] V[] VP :.(Supply after V Stable) VSS[] VSS[] U V[] V[].(Supply before V Stable) VSS[] VSS[] U V[] V[] VSS[] VSS[] V VSS[] VSS[] V V[] V[] V[] V[].V VSS[] VSS[] V u/.v_ *u/v_ *u/v_ u/.v_ VSS[] VSS[] V u/.v_ *u/v_ V[] V[] *u/v_ *u/v_ V[] V[] VSS[] VSS[] W V[] V[] E VSS[] VSS[] W V[] V[] E VSS[] VSS[] W V[] V[] E VSS[] VSS[] W V[] V[] E.u/V_ VSS[] VSS[] Y.u/V_.u/V_ V[] V[] E VSS[] VSS[] Y u/v_ V[] V[] E VSS[] VSS[] Y V[] V[] E VSS[] VSS[] Y V[] V[] E VSS[] VSS[] VSS[] VSS[] V[] V[] F V[] V[] F VSS[] VSS[] u/.v_ VSS[] VSS[] *u/v_ V[] V[] F *u/v_ *u/v_ u/.v_ V[] V[] F VSS[] VSS[] V[] V[] F VSS[] VSS[] V[] V[] F VSS[] VSS[] V[] V[] F E *.u/v_ VSS[] VSS[] E.u/V_.u/V_ V[] V[] F E VSS[] VSS[] Layout Note: E V[] E VSS[] VSS[] E E Place these parts V[] VP[] G VSS[] VSS[] E V[] VP[] V E VSS[] VSS[] reference to Intel demo E E VSS[] VSS[] V[] VP[] J E E board. V[] VP[] K VSS[] VSS[] E E VSS[] VSS[] *u/v_ u/.v_ V[] VP[] M *u/v_ E V[] VP[] J E VSS[] VSS[] E V[] VP[] K F VSS[] VSS[] F V[] VP[] M F VSS[] VSS[] F V[] VP[] N F VSS[] VSS[] F V[] VP[] N F VSS[] VSS[] F V[] VP[] R F VSS[] VSS[] F V[] VP[] R F VSS[] VSS[] F V[] VP[] T F VSS[] VSS[] F F VSS[] VSS[] V[] VP[] T F V[] VP[] V F.V VSS[] VSS[] F V:m G *u/v_ u/.v_ *u/v_ *u/v_ VSS[] VSS[] *u/v_ u/.v_ V[] VP[] W V[] G VSS[] VSS[] V[] V[] G VSS[] VSS[] V[] V[] G VSS[] VSS[] V[] H VSS[] VSS[] V[] VI[] H_VI [] H VSS[] VSS[] V[] VI[] F H_VI [] H VSS[] VSS[] V[] VI[] E.u/V_ u/.v_ H_VI [] H VSS[] VSS[] V[] VI[] F H_VI [] J VSS[] VSS[] H_VI [] J VSS[] VSS[] V[] VI[] E V[] VI[] F H_VI [] J VSS[] VSS[] H_VI [] J u/.v_ *u/v_ VSS[] VSS[] E *u/v_ V[] VI[] E u/.v_ u/.v_ u/.v_ R /F_ V[] V_ORE K VSS[] VSS[] E V[] K VSS[] VSS[] E V[] VSENSE F VSENSE [] K VSS[] VSS[] E V[] K VSS[] VSS[] E V[] L VSS[] VSS[] E V[] VSSSENSE E VSSSENSE [] L VSS[] VSS[] E L R VSS[] VSS[] E Penryn L VSS[] VSS[] E. M /F_ VSS[] VSS[] M VSS[] VSS[] F M *u/v_ *u/v_ VSS[] VSS[] F *u/v_ *u/v_ M VSS[] VSS[] F Layout Note: N VSS[] VSS[] F N Z=.,PU/P L<" VSS[] VSS[] F N VSS[] VSS[] F N VSS[] VSS[] F P VSS[] VSS[] VSS[] F Penryn. Montevina platform : Early Reference oard Schematics Feb. Rev. stuff U*, N U* stuff U*, NU* Quanta omputer Inc. PROJET : Size ocument Number Rev PU Power ZRE ate: Tuesday, May, Sheet of

5 H_#[..] [] U [] H_#[..] H_# H_# H_#_ F H_# H_# H_#_ H_#_ G H_# H_# H_#_ H_#_ F F H_# H_# H_#_ H_#_ H QI P/N E H_# H_# H_#_ H_#_ G H_# H_# H_#_ H_#_ M H H_# H_# H_#_ H_#_ J Intel antiga (G)M JSLT H H_# H_# H_#_ H_#_ P F H_# H_# H_#_ H_#_ R H_# H_# H_#_ H_#_ N Intel antiga (P)M JSLT H H_# H_# H_#_ H_#_ M M H_# H_# H_#_ H_#_ E M H_# H_# H_#_ H_#_ P Intel antiga (G)L JSLGGMT J H_# H_# H_#_ H_#_ F J H_# H_# H_#_ H_#_ G N H_# H_# H_#_ H_#_ J H_# H_# H_#_ H_#_ J P H_# H_# H_#_ H_#_ E L H_# H_# H_#_ H_#_ H R H_# H_# H_#_ H_#_ J N H_# H_# H_#_ H_#_ L L H_# H_# H_#_ H_#_ M H_# H_# H_#_ H_#_ J H_# H_# H_#_ H_#_ L N H_# H_# H_#_ H_#_ R H_# H_# H_#_ H_#_ J N H_# H_# H_#_ H_#_ H N H_# H_# H_#_ H_#_ P H_# H_# H_#_ H_#_ K N H_# H_# H_#_ H_#_ L H_# H_# H_#_ H_#_ F N H_#.V H_# H_#_ H_#_ K M H_# H_# H_#_ H_#_ L Y.*VP H_# H_#_ H_S# [] H_# H_#_ H_S# H Y WIE():SPING(), H_ST# [] H_# H_#_ H_ST#_ Y H_ST# [] L<." H_# H_ST#_ G R H_#_ Y H_NR# [] H_# H_#_ H_NR# Y H_PRI# [] H_# H_PRI# F /F_ H_#_ Y H_REQ# [] H_# H_#_ H_REQ# G W H_EFER# [] H_SWING H_# H_#_ H_EFER# E H_SY# [] H_# H_#_ H_SY# Y LK_MH_LK [] H_# H_#_ HPLL_LK H LK_MH_LK# [] H_# HPLL_LK# H R H_#_ H_PWR# [] H_# H_#_ H_PWR# J H_RY# [] H_# H_#_ H_RY# F /F_.u/V_ H_HIT# [] H_# H_#_ H_HIT# H H_HITM# [] H_# H_#_ H_HITM# E H_LOK# [] H_# H_#_ H_LOK# H E H_TRY# [] H_# H_#_ H_TRY# E H_# H_#_ H_# H_#_ H_# H_#_ H_INV#[..] [] H_# H_#_ H_INV# H_# H_#_ H_INV#_ J H_INV# H_ROMP H_# H_#_ H_INV#_ L E H_INV# H_# H_#_ H_INV#_ Y F H_INV# H_# H_#_ H_INV#_ Y H_STN#[..] [] H_# H_#_ E H_STN# H_# H_#_ H_STN#_ L R H_STN# Layout Note: H_# H_#_ H_STN#_ M E H_STN# H_# H_#_ H_STN#_./F_ E H_STN# WIE():SPING(), H_# H_#_ H_STN#_ E G H_STP#[..] [] L<." H_# H_#_ H_STP# H_#_ H_STP#_ L H_STP# H_STP#_ M H_STP# H_SWING H_STP#_ H_STP# H_ROMP H_SWING H_STP#_ E E.V H_ROMP H_REQ#[..] [] H_REQ# H_REQ#_ H_REQ# H_REQ#_ K H_REQ# H_REQ#_ F H_REQ# H_REQ#_ H_REQ# [] H_PURST# H_PURST# H_REQ#_ R [] H_PUSLP# E H_PUSLP# H_RS#[..] [] /*VP H_RS# H_RS#_ K/F_ H_RS# WIE():SPING(), H_RS#_ F H_RS# L<." H_VREF H_RS#_ H_VREF H_VREF R NTIG_PM K/F_ *.u/v_ HOST Quanta omputer Inc. PROJET : Size ocument Number Rev GMH HOST ZRE ate: Tuesday, May, Sheet of

6 Strap table U Pin Name FG[:] FG[:] FG FG FG FG FG FG FG FG FG FG[:] FG FG[:] FG FG SVO_TRLT P_TRLT PIE Graphics Lane Reversal PIE Loopback enable XOR Strap description FS Frequency Select MI X Select itpm Host Interface ME TLS onfidentiality LLZ FS ynamic OT MI Lane Reversal igital isplay Port (SVO/P/iHMI) oncurrent with PIE SVO Present igital isplay Present Strap pin V V VSUS R R R R R R R R R R R R R R R R R *.K/F_ *.K/F_ *.K/F_ *.K/F_ *.K/F_ *.K/F_ *.K/F_ *.K/F_ *.K/F_ *.K/F_ IV@.K_ IV@.K_ *.K/F_ *.K/F_ K_ K_ K_ onfiguration = FS MHz = FS MHz = FS MHz = MI X = MI X(efault) = itpm Host Interface is enabled = itpm Host Interface is disabled(efault) = MT Firmware will use TLS cipher suite with no confidentiality = MT Firmware will use TLS cipher suite with confidentiality(efault) = Reverse Lanes = Normal operation(efault) = Enabled = isabled (efault) = LLZ mode enable = disable(efault) = XOR mode enable = disable(efault) = ynamic OT disable = ynamic OT Enable(efault) = Normal (efault) = Lanes Reversed = Only igital isplay port (SVO/P/iHMI) or PIE is operational (efault) = igital isplay port (SVO/P/iHMI) and PIE are operating simultaneously via PEG port = No SVO/HMI evice Present(efault) = SVO/HMI evice present = igital display(hmi/p) device absent(efault) = igital display(hmi/p) device present MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ SVO_TRLT SVO_TRLLK P_T P_TRLLK LK_MH_OE# PM_EXTTS# PM_EXTTS# TPM isable [,,,] [] PM_SYN# [,,] IH_PRSTP# [] PM_EXTTS# [] PM_EXTTS# ELY_VR_PWRGOO [] PLT_RST# [,] PM_THRMTRIP# [,] PM_PRSLPVR [] [] [] MH_SEL MH_SEL MH_SEL T T R R T T T T T T T T /F_ *_ N Thermal trip pin No use Thermal trip N side can N.(N has OT) PM_PRSTP# The aisy chain topology should be routed from IHM to IMVP, then to (G)MH and PU, in that order. JTG_TO_GMHN JTG_TMS_GMHM MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ RST_IN#_MH THRMTRIP#_R M N R T H H H H K T M Y G F H F L K T R P P P N M E N P T R M L H P R T R N P T T T R G F H G E H F G H H H H G H F H G E G F F RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV ME_JTG_TK ME_JTG_TI ME_JTG_TO ME_JTG_TMS FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ PM_SYN# PM_PRSTP# PM_EXT_TS#_ PM_EXT_TS#_ PWROK RSTIN# THERMTRIP# PRSLPVR N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ NTIG_PM FG PM RSV ME JTG N R LK/ ONTROL/OMPENSTION LK MI GRPHIS VI ME MIS H S_K_ S_K_ S_K_ S_K_ S_K#_ S_K#_ S_K#_ S_K#_ S_KE_ S_KE_ S_KE_ S_KE_ S_S#_ S_S#_ S_S#_ S_S#_ S_OT_ S_OT_ S_OT_ S_OT_ SM_ROMP SM_ROMP# SM_ROMP_VOH SM_ROMP_VOL SM_VREF SM_PWROK SM_REXT SM_RMRST# PLL_REF_LK PLL_REF_LK# PLL_REF_SSLK PLL_REF_SSLK# PEG_LK PEG_LK# MI_RXN_ MI_RXN_ MI_RXN_ MI_RXN_ MI_RXP_ MI_RXP_ MI_RXP_ MI_RXP_ MI_TXN_ MI_TXN_ MI_TXN_ MI_TXN_ MI_TXP_ MI_TXP_ MI_TXP_ MI_TXP_ GFX_VI_ GFX_VI_ GFX_VI_ GFX_VI_ GFX_VI_ GFX_VR_EN L_LK L_T L_PWROK L_RST# L_VREF P_TRLLK P_TRLT SVO_TRLLK SVO_TRLT LKREQ# IH_SYN# TSTN# H_LK H_RST# H_SI H_SO H_SYN P T V U R R U V Y Y Y V R Y F Y G H F H V R F E F F E E E E H E E E H E E E H E F H G F E H H N J H N M G E K H M_ROMP M_ROMP# SM_ROMP_VOH SM_ROMP_VOL SM_VREF SM_PWROK R SM_REXT R LK_REFLK LK_REFLK# LK_REFSSLK LK_REFSSLK# LK_PIE_GPLL LK_PIE_GPLL# MI_TXN MI_TXN MI_TXN MI_TXN MI_TXP MI_TXP MI_TXP MI_TXP MI_RXN MI_RXN MI_RXN MI_RXN MI_RXP MI_RXP MI_RXP MI_RXP MH_LVREF_R P_TRLLK P_T LK_MH_OE# TSTN# H_IT_LK_HMI H_RST#_HMI H_SIN_HMI H_SOUT_HMI H_SYN_HMI K/F_ /F_ M_LK [] M_LK [] M_LK [] M_LK [] M_LK# [] M_LK# [] M_LK# [] M_LK# [] M_KE [] M_KE [] M_KE [] M_KE [] M_S# [] M_S# [] M_S# [] M_S# [] M_OT [] M_OT [] M_OT [] M_OT [] LK_REFLK [] LK_REFLK# [] LK_REFSSLK [] LK_REFSSLK# [] LK_PIE_GPLL [] LK_PIE_GPLL# [] MI_TXN[:] [] MI_TXP[:] [] MI_RXN[:] [] MI_RXP[:] [] *p/v_ L_LK [] L_T [] MPWROK [,] L_RST# [] SVO_TRLLK [] SVO_TRLT [] LK_MH_OE# [] MH_IH_SYN# [].V H_IT_LK_HMI [] H_RST#_HMI [] H_SIN_HMI [] H_SOUT_HMI [] H_SYN_HMI [] R *_ H_IT_LK_HMI heck list note : L_VREF=.V R _ SM_VREF=.*V_SM SM_PWROK only for R.(R P only) SM_RMRST# only for R.(R:N) For EMI.u/V_.V If HMI not support H --> N V_H-->GN ifferential signal-->n Impact IHM VH and VSUSH supply.v/.v NOTE: If (G)MH's H udio signals are connected to IHM for ihmi, VH and VSUSH on IHM should be only on.v. These power pins on IHM can be supplied with.v if and only if (G)MH's H is not connected to IHM. onsequently, only.v audio/modem codecs can be used on the platform. R K/F_ R /F_ M_ROMP M_ROMP# SM_VREF TSTN# LK_REFLK# LK_REFLK LK_REFSSLK# LK_REFSSLK SM_ROMP_VOH.u/.V_ SM_ROMP_VOL.V P_TRL for HMI port SVO_TRL for HMI port.vsus./f_./f_ SM_VREF.efault use voltage divider for poor layout cause SMR_VREF not meet spec.nd Intel circuit PU/P is K,ut heck list PU/P is K. INTEL FE Suggest P for Ext graphics N Thermaltrip elete SM_VREF related circuit.u/.v_ R R R R R *K_ R R R R.VSUS->.VSUS.u/V_.u/V_ Q *MMT.VSUS K/F_ K/F_ K/F_ R.K/F_ R K/F_ EV@_ EV@_ EV@_ EV@_.VSUS R TSTN_E# [] <hecklist ver.> If TSTN# is not used, then it must be terminated with a - pull-up resistor to VP. <Pin out check issue> antiga ES. change all to TSTN# from TSTN Quanta omputer Inc. PROJET : ZRE Size ocument Number Rev GMH MI.VSUS->.VSUS.VSUS->.VSUS Tuesday, May, ate: Sheet of

7 If LVS no use,all signal can N [] L_KLT_TRL [] INT_LVS_LON [] INT_LVS_EILK [] INT_LVS_EIT [] INT_LVS_IGON [] INT_TXLOUT- [] INT_TXLOUT- [] INT_TXLOUT- [] INT_TXLLKOUT- [] INT_TXLLKOUT [] INT_TXLOUT [] INT_TXLOUT [] INT_TXLOUT [] INT_RT_LK [] INT_RT_T [] INT_HSYN [] INT_VSYN HSYN_G VSYN_G V iscrete Stuffed. (RT) SP@ [] INT_RT_LU [] INT_RT_GRN [] INT_RT_RE LVS_IG INT_TXLLKOUT- INT_TXLLKOUT INT_TXLOUT- INT_TXLOUT- INT_TXLOUT- INT_TXLOUT INT_TXLOUT INT_TXLOUT TV_// For IV: ohm For EV:ohm L_TRL_LK L_TRL_T INT_TV_OMP INT_TV_Y/G INT_TV_/R INT_RT_LU INT_RT_GRN INT_RT_RE HSYN_G RTIREF VSYN_G HSYN/VSYN serial R place close to N RTIREF pull down for IV cantiga.k ohm/f U R R R IV@.K/F_ R R R R R IV@K_ IV@K_ SP@_ SP@_ SP@_ IV@._ IV@._ L G M M K J M E E H E G H F H G J G F K F H K H E E G J G H J J E L L_KLT_TRL L_KLT_EN L_TRL_LK L_TRL_T L LK L T L_V_EN LVS_IG LVS_VG LVS_VREFH LVS_VREFL LVS_LK# LVS_LK LVS_LK# LVS_LK LVS_T#_ LVS_T#_ LVS_T#_ LVS_T#_ LVS_T_ LVS_T_ LVS_T_ LVS_T_ LVS_T#_ LVS_T#_ LVS_T#_ LVS_T#_ LVS_T_ LVS_T_ LVS_T_ LVS_T_ TV_ TV_ TV_ TV_RTN TV_ONSEL_ TV_ONSEL_ RT_LUE RT_GREEN RT_RE RT_IRTN RT LK RT T RT_HSYN RT_TVO_IREF RT_VSYN NTIG_PM LVS PI-EXPRESS GRPHIS TV VG PEG_OMPI PEG_OMPO PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ T T L<.", If PIE not support still connect to V_PEG EXP OMPX H PEG_RXN J PEG_RXN L PEG_RXN L PEG_RXN N PEG_RXN P PEG_RXN N PEG_RXN T PEG_RXN U PEG_RXN Y PEG_RXN Y PEG_RXN Y PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN H PEG_RXP J PEG_RXP L PEG_RXP L PEG_RXP N PEG_RXP P PEG_RXP N PEG_RXP T PEG_RXP U PEG_RXP Y PEG_RXP W PEG_RXP Y PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP J M M M M R N T U U Y J L M M M R N T U U Y Y _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN R _PEG_TXP _PEG_TXP _PEG_TXP _PEG_TXP _PEG_TXP _PEG_TXP _PEG_TXP _PEG_TXP _PEG_TXP _PEG_TXP _PEG_TXP _PEG_TXP _PEG_TXP _PEG_TXP _PEG_TXP _PEG_TXP.V./F_ PEG_RXN[:] [] PEG_RXP[:] [,] an support reversal routing.if FG=, PI Express is normal operation. If FG=, then PEG_TXP becomes PEG_TXP, PEG_TXP becomes PEG_TXP, PEG_TXP becomes PEG_TXP, etc. similarly for PEG_RXP[:] and PEG_RXN[:].u/V_.u/V_.u/V_.u/V_ EV@.U/V_ EV@.U/V_ EV@.U/V_ EV@.U/V_ EV@.U/V_ EV@.U/V_ EV@.U/V_ EV@.U/V_ EV@.U/V_ EV@.U/V_ EV@.U/V_ EV@.U/V_ PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN.u/V_ PEG_TXP.u/V_ PEG_TXP.u/V_ PEG_TXP.u/V_ PEG_TXP EV@.U/V_ PEG_TXP EV@.U/V_ PEG_TXP EV@.U/V_ PEG_TXP EV@.U/V_ PEG_TXP EV@.U/V_ PEG_TXP EV@.U/V_ PEG_TXP EV@.U/V_ PEG_TXP EV@.U/V_ PEG_TXP EV@.U/V_ PEG_TXP EV@.U/V_ PEG_TXP EV@.U/V_ PEG_TXP EV@.U/V_ PEG_TXP PEG_TXN[:] [,] PEG_TXP[:] [,] </>Montevina_Schematics_hecklist_Rev_ a)for TVOUT isabled, TV_ONSEL[:] onnect to GN. ut design guide Rev. show N.What is correct. b)for RT isable, RT LK, RT T. RT_HSYN, RT_VSYNThese signals should be connected to GN. ut design guide Rev. show N, Intel suggest follow esign guide. <check list> <check list> For EV@ For IV@ RT R/G/ ohm to GN RT R/G/ ohm to GN RTIREF ohm to GN RTIREF Kohm to GN For topology without the analog switch - if the total motherboard route length is less than ", the recommended reference resistor value is k ±% RTIREF For IV: Kohm For EV:ohm SP@ R R R R RT_R/G/ For IV: ohm For EV:ohm SP@K/F_ SP@/F_ SP@/F_ SP@/F_ RTIREF INT_RT_LU INT_RT_GRN INT_RT_RE R EV@_ R EV@_ Quanta omputer Inc. PROJET : ZRE Size ocument Number Rev GMH VG ate: Tuesday, May, Sheet of

8 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M M M M M M M M M M M M M M M M M QS M QS M QS M QS M QS M QS M QS M QS M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS# M M M M M M M M M M M M M M M M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M M QS# M M QS# M M M QS# M M QS# M M M M QS# M M QS M QS# M M M M M M QS M M M M M QS M M QS M QS M M QS M M M M QS M QS M M M M M QS# M QS# M M M M M Q[:] [] M S [] M M[:] [] M QS[:] [] M QS#[:] [] M [:] [] M RS# [] M S# [] M WE# [] M Q[:] [] M S [] M M[:] [] M QS[:] [] M QS#[:] [] M [:] [] M RS# [] M S# [] M WE# [] M S [] M S [] M S [] M S [] Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMH RII Tuesday, May, ZRE Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMH RII Tuesday, May, ZRE Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMH RII Tuesday, May, ZRE R SYSTEM MEMORY U NTIG_PM R SYSTEM MEMORY U NTIG_PM S_Q_ J S_Q_ J S_Q_ U S_Q_ T S_Q_ N S_Q_ N S_Q_ U S_Q_ U S_Q_ V S_Q_ Y S_Q_ S_Q_ S_Q_ N S_Q_ V S_Q_ Y S_Q_ S_Q_ S_Q_ Y S_Q_ S_Q_ V S_Q_ T S_Q_ Y S_Q_ S_Q_ M S_Q_ V S_Q_ W S_Q_ S_Q_ U S_Q_ S_Q_ S_Q_ U S_Q_ V S_Q_ S_Q_ S_Q_ J S_Q_ S_Q_ S_Q_ U S_Q_ V S_Q_ S_Q_ S_Q_ Y S_Q_ S_Q_ V S_Q_ V S_Q_ J S_Q_ T S_Q_ N S_Q_ U S_Q_ U S_Q_ T S_Q_ N S_Q_ M S_Q_ M S_Q_ J S_Q_ J S_Q_ M S_Q_ N S_Q_ M S_Q_ J S_Q_ J S_Q_ M S_Q_ N S_Q_ N S_S_ S_S_ G S_S_ T S_S# S_M_ M S_M_ T S_M_ Y S_M_ U S_M_ S_M_ Y S_M_ T S_QS_ J S_QS_ T S_QS_ S_QS_ S_QS_ W S_QS_ S_QS_ U S_QS_ M S_M_ J S_QS#_ J S_QS#_ T S_QS#_ S_QS#_ S_QS#_ Y S_QS#_ S_QS#_ U S_QS#_ M S_M_ S_M_ S_M_ S_M_ G S_M_ H S_M_ H S_M_ G S_M_ H S_M_ G S_M_ S_M_ S_M_ G S_M_ F S_M_ W S_RS# S_WE# Y S_M_ Y R SYSTEM MEMORY UE NTIG_PM R SYSTEM MEMORY UE NTIG_PM S_Q_ K S_Q_ H S_Q_ S_Q_ Y S_Q_ T S_Q_ R S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ G S_Q_ F S_Q_ P S_Q_ E S_Q_ S_Q_ F S_Q_ F S_Q_ G S_Q_ F S_Q_ H S_Q_ G S_Q_ H S_Q_ G S_Q_ P S_Q_ G S_Q_ H S_Q_ H S_Q_ G S_Q_ H S_Q_ G S_Q_ H S_Q_ F S_Q_ F S_Q_ G S_Q_ J S_Q_ S_Q_ S_Q_ Y S_Q_ Y S_Q_ F S_Q_ F S_Q_ S_Q_ S_Q_ V S_Q_ U S_Q_ J S_Q_ R S_Q_ N S_Q_ Y S_Q_ V S_Q_ P S_Q_ R S_Q_ L S_Q_ L S_Q_ J S_Q_ H S_Q_ M S_Q_ M S_Q_ M S_Q_ H S_Q_ J S_Q_ P S_Q_ U S_Q_ U S_S_ S_S_ S_S_ S_S# G S_M_ M S_M_ Y S_M_ S_M_ F S_M_ G S_M_ S_M_ P S_M_ K S_QS_ L S_QS_ V S_QS_ G S_QS_ G S_QS_ H S_QS_ S_QS_ U S_QS_ N S_QS#_ L S_QS#_ V S_QS#_ H S_QS#_ H S_QS#_ G S_QS#_ S_QS#_ T S_QS#_ N S_M_ V S_M_ S_M_ S_M_ W S_M_ Y S_M_ H S_M_ S_M_ U S_M_ W S_M_ S_M_ U S_M_ W S_M_ T S_M_ S_M_ U S_RS# U S_WE# F

9 Power consumption reference to Intel antiga chipset ES Volume. Section.VSUS to.vsus UG.V_XG Intel check list(rev.) No description for V_SM bulk P Intel R(Rev.) U* Reserve near to power U* near to N Intel check list(rev.) U* near to power(v.m). U* near to N Intel R(Rev.) U* near to power(v.m). U* near to N ESR=m ohm u/.v_ *u/.v_.u/v_.v_xg.v_xg Voltage regulator is shared between the Graphics ore Rail, V_HPLL,V_MPLL,V_PEG_PLLV_PEG_PLL, V_SM_K, V_PLL, V_PLL, V_HPLL, V_SM, V_XF IV@ u/v_ R R IV@/F_ IV@/F_ P N H G F Y W V U T R P N H G F G H G F Y W V U T R P W W T Y E E Y E J G E Y H F E T T M L E J H G F Y V U N M U T J H V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_/N V_SM_/N V_SM_/N V_SM_/N V_SM_/N V_SM_/N V_SM_/N V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_SENSE VSS_XG_SENSE POWER V SM V GFX V GFX NTF V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V SM LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF W V W V W V W V W V M L K W V U M K W U M L K J H G F E Y W V U M K H G F E Y W V M L K J H G F E Y W V U V M V Y M V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF.V_XG IV@.V Internal connect to power.u/v_.v IV@u/V_.V_XG Place close to the GMH Intel check list(rev.) U* near to N(ESR=m ohm) Intel R(Rev.) U* near to power(v.s). U* near to N.u/V_ R R R.u/.V_ IV@_ IV@_ IV@_ IV@u/V_.u/.V_ IV@.u/.V_.u/.V_.V Place close to the GMH esign guide(table ) For INT VG diasble.v_xg power can connect to GN SP@ SP@u/V_ u/v_.u/v_ u/v_ IV@u/.V_ *.u/.v_ IV@u/.V_.u/.V_ IV@.u/V_ u/.v_ u/v_ IV@.u/V_ avity apacitors IV@.u/V_ UF G V_ V_ V_ V_ Y V_ V V_ U V_ M V_ K V_ J V_ G V_ F V_ E V_ V_ V_ Y V_ W V_ V V_ U V_ H V_ F V_ V_ V_ J V_ G V_ E V_ V_ H V_ G V_ F V_ G V_ J V_ H V_ F V_ T V_ NTIG_PM V ORE POWER V NTF V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_.V M L K J H G E Y W U M L K H G F E Y W V U L K J H G E Y W V L K L K K K K. Route V_XG_SENSE and VSS_XG_SENSE differentially. V_XG_SENSE PU to VGFX_ORE_INT with ohm and VSS_XG_SENSE P with ohm for Intel suggest NTIG_PM POWER PLNE S S S/S Voltage I(max) V(EXT_VG) O X X.V m V(INT_VG) O X X.V m Note V_XG O X X.V m Graphics ore V_SM() O O X.VSUS (RII-). V_SM(Standby) O O X.VSUS m Self Refresh during S (See N ES Rev:. Section. for max current) (See N ES Rev:. Section. for voltage) Quanta omputer Inc. PROJET : ZRE Size ocument Number Rev GMH V,NTF Tuesday, May, ate: Sheet of

10 If RT have Flicker issue STUFF. ohm V_RT_TV_ R V_V_RT_ Power consumption reference to Intel IV@_ antiga chipset ES Volume. Section IV@.u/V_ SP@.u/V_ *IV@u/.V_ IV@ EV@ VSYN_RT GN UH, % R V G. R_max =. V_RT_ GN SP@ IV@_.V V_LVS GN FS-.V L IV@uH m IV@.u/V_ SP@.u/V_ IV@u/.V_ UH m V_TX_LVS GN U.V_VP_GMH R *short.v V_LVS GN VTT_ T IV@u/.V_ SP@.u/V_ VTT_ U V_TV GN V_RT VTT_ T ESR= m V_RT VTT_ U V_Q GN VTT_ T.u/.V_.u/.V_.u/.V_.u/.V_ u/v_ VTT_ U V G GN V G VTT_ T VSS G VTT_ ESR= m ohm V_PLL/ always keep to.v USE same GN plane U V_XG GN VTT_ UH, % (If no use IV dynamic core power) T VTT_. R_max =. U V_XG_NTF GN.VM_PLL VTT_ F T V_PLL VTT_ U.V L IV@uH m.vm_pll VTT_ L T V_PLL VTT_ U.VM_HPLL VTT_ T V_HPLL VTT_ U IV@u/.V_ SP@.u/V_.VM_MPLL VTT_ E T V_MPLL VTT_ ESR= m V.V_TXLVS VTT_ U VTT_.V J V V_LVS VTT_ m U VTT_.V J T.V R *short VSS_LVS VTT_ SP@p/V_ V u VTT_.V U VTT_.m.V R *short V_PEG_G.VM_XF L.uH m.v.u/.v_.u/v_ V_PEG_G.V.V.V. nh,. nh,.u/v_ m u/v_ *u_.m R-.V, R_max= m.vm_pegpll V_PEG_PLL UH, Rdc =. -.. L KPHST. m V_PEG_PLL ESR = m R- Max rated current = m.v for Teenah use(m) m.uh, %,,.V R _.VM SM R V_SM_ R_max=. P.VSUS_V_SM_K L uh..vsus ->.VSUS V_SM_.VSUS N.VM_MPLL_R R./F_ V_SM_ R V_SM_ POWER u/.v_.u/.v_ u/v_ P /F_ R.VSUS_SMK_R u/.v_ V_SM_ N.u/V_ V_SM_ T V_SM_ R u/.v_.u/v_ V_SM_ P V_SM_.V.m for V_TV_.m for V_TV_.m for V_TV_ Total.m.V.V.m for RT m for TV MHz, %..V R_max= m m V L IV@KPHST. R no U heck list need min U~U for V_TV_ R IV@u/.V_ IV@_.V m V_TV always keep.u/.u/u to.v.v m.v R *short MHz, %. R_max= m L KPHST..V IV@.u/V_.u/V_.V.m R SP@.u/V_ *short SP@.u/V_.u/V_.V R- m R : ohm heck list :.nh.v.vm SM_K *.u/v_ u/.v_ V_Q share to TV and RT R *short.v.m.u/v_.u/v_ V_RT_TV_ V_H.V_TV.V_Q.VM_MH_PLL.VM_PEGPLL P N P N N M M M L M L M L M L F M L V_SM_K_ V_SM_K_ V_SM_K_ V_SM_K_ V_SM_K_ V_SM_K_NTF_ V_SM_K_NTF_ V_SM_K_NTF_ V_SM_K_NTF_ V_SM_K_NTF_ V_SM_K_NTF_ V_SM_K_NTF_ V_SM_K_NTF_ V_TV V_TV V_H V_TV V_Q V_HPLL V_PEG_PLL V_LVS_ V_LVS_ NTIG_PM RT PLL LVS PEG SM TV H LVS K TV/RT XF SM K MI HV PEG VTT V_SM_K_ V_SM_K_ V_SM_K_ V_SM_K_ VTTLF V_XF_ V_XF_ V_XF_ V_TX_LVS V_HV_ V_HV_ V_HV_ V_PEG_ V_PEG_ V_PEG_ V_PEG_ V_PEG_ V_MI_ V_MI_ V_MI_ V_MI_ VTTLF VTTLF VTTLF F H G F K V U V U U H F H G L VTTLF VTTLF VTTLF.V_TXLVS.V.m.V m.v_v_peg.u/.v_.v m.u/.v_.u/v_ SP@p/V_.V.m L *IV@u/.V_ V R _.u/v_.u/.v_ u/.v_ IV@.uH m.v_s R u/.v_.v Internal connect to power.u/.v_.vsus.v *short H.V.V u/.v_ R no U heck list need min U~U for V_Q.u/V_ MHz, %,.V m L KPHST..u/V_ Power Net Name V_XG_# V_XG_NTF_# V_PEG_G V_PLL V_PLL antiga(v).v.v.v.v V_SM_#.V.VM_PEGPLL_R R u/.v_ ESR=m ohm /F_.u/V_.u/V_.VSUS R IV@_.V.m.V_LVS SP@u/V_ V_HPLL V_MPLL V_SM_K_# V_PEG_PLL V_XF_# V_HPLL V_PEG_PLL.V.V.V.V.V.V.V Quanta omputer Inc. PROJET : ZRE Size ocument Number Rev GMH POWER Tuesday, May, ate: Sheet of

11 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMH VSS Tuesday, May, ZRE Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMH VSS Tuesday, May, ZRE Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMH VSS Tuesday, May, ZRE VSS VSS NTF VSS S N UJ NTIG_PM VSS VSS NTF VSS S N UJ NTIG_PM VSS_ G VSS_ W VSS_ U VSS_ P VSS_ N VSS_ H VSS_ F VSS_ VSS_ R VSS_ M VSS_ J VSS_ G VSS_ VSS_ VSS_ W VSS_ T VSS_ J VSS_ G VSS_ Y VSS_ N VSS_ K VSS_ F VSS_ VSS_ VSS_ G VSS_ VSS_ G VSS_ VSS_ W VSS_ T VSS_ R VSS_ M VSS_ H VSS_ VSS_ VSS_ U VSS_ N VSS_ N VSS_ K VSS_ G VSS_ E VSS_ G VSS_ W VSS_ VSS_ G VSS_ VSS_ VSS_ G VSS_ VSS_ VSS_ N VSS_ J VSS_ E VSS_ N VSS_ L VSS_ G VSS_ E VSS_ F VSS_ V VSS_ T VSS_ M VSS_ VSS_ J VSS_ VSS_ VSS_ VSS_ Y VSS_ N VSS_ H VSS_ Y VSS_ N VSS_ G VSS_ VSS_ G VSS_ V VSS_ T VSS_ J VSS_ E VSS_ VSS_ H VSS_ VSS_ G VSS_ VSS_ M VSS_ N VSS_ VSS_ M VSS_ F VSS_ H VSS_ Y VSS_ L VSS_ E VSS_ VSS_ Y VSS_ U VSS_ N VSS_ J VSS_ E VSS_ VSS_ N VSS_ J VSS_ G VSS_ VSS_ V VSS_ T VSS_ VSS_ M VSS_ M VSS_ VSS_ VSS_ H VSS_ VSS_ Y VSS_ L VSS_ J VSS_ H VSS_ F VSS_ E VSS_ VSS_ V VSS_ L VSS_NTF_ F VSS_NTF_ VSS_NTF_ V VSS_NTF_ J VSS_NTF_ M VSS_NTF_ F VSS_NTF_ VSS_NTF_ U VSS_NTF_ U VSS_NTF_ L VSS_NTF_ V VSS_NTF_ VSS_NTF_ L VSS_NTF_ J VSS_NTF_ VSS_NTF_ U VSS_S_ H VSS_S_ H VSS_S_ VSS_S_ VSS_S_ N_ E N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ F N_ E N_ N_ VSS_ R VSS_ P VSS_ VSS_ R VSS_ U VSS_ P VSS_ F VSS_ W VSS_ E VSS_ F VSS_ H VSS_ J VSS_ VSS_ VSS_ Y VSS_ M VSS_ K VSS_ M VSS_ VSS_ P VSS_ H VSS_ VSS_ V VSS_ T VSS_ U VSS_ U VSS_ U VSS_ U VSS_ L VSS_ J N_ VSS UI NTIG_PM VSS UI NTIG_PM VSS_ U VSS_ VSS_ R VSS_ L VSS_ VSS_ W VSS_ N VSS_ J VSS_ F VSS_ VSS_ VSS_ Y VSS_ T VSS_ N VSS_ L VSS_ G VSS_ VSS_ VSS_ V VSS_ R VSS_ M VSS_ V VSS_ R VSS_ P VSS_ H VSS_ F VSS_ F VSS_ H VSS_ VSS_ VSS_ Y VSS_ U VSS_ T VSS_ M VSS_ F VSS_ VSS_ V VSS_ U VSS_ M VSS_ J VSS_ VSS_ G VSS_ Y VSS_ T VSS_ N VSS_ J VSS_ E VSS_ N VSS_ L VSS_ VSS_ U VSS_ M VSS_ H VSS_ VSS_ VSS_ Y VSS_ U VSS_ T VSS_ M VSS_ G VSS_ VSS_ G VSS_ VSS_ V VSS_ N VSS_ H VSS_ E VSS_ T VSS_ M VSS_ J VSS_ E VSS_ N VSS_ L VSS_ VSS_ H VSS_ VSS_ VSS_ U VSS_ H VSS_ VSS_ VSS_ Y VSS_ U VSS_ T VSS_ J VSS_ F VSS_ VSS_ VSS_ M VSS_ E VSS_ P VSS_ L VSS_ J VSS_ F VSS_ VSS_ H VSS_ VSS_ Y VSS_ U VSS_ T VSS_ F VSS_ M VSS_ J VSS_ F VSS_ E VSS_ W VSS_ VSS_ VSS_ G VSS_ VSS_ VSS_ V VSS_ R VSS_ L VSS_ H VSS_ VSS_ P VSS_ L VSS_ H VSS_ N VSS_ K VSS_ F VSS_ VSS_ VSS_ N VSS_ T VSS_ N VSS_ K VSS_ H VSS_ F VSS_ VSS_ G VSS_ VSS_ VSS_ V VSS_ T VSS_ R VSS_ J VSS_ G VSS_ E VSS_ VSS_ Y VSS_ P VSS_ K VSS_ H VSS_ F VSS_ VSS_ F VSS_ H VSS_ F VSS_ VSS_ VSS_ VSS_ VSS_ H VSS_ VSS_ VSS_ V VSS_ R VSS_ J VSS_ VSS_ Y VSS_ N VSS_ L VSS_ J VSS_ G VSS_ E VSS_ F VSS_ F VSS_ VSS_ W VSS_ T VSS_ N VSS_ J VSS_ H VSS_ VSS_ G VSS_ U VSS_ T VSS_ H VSS_ VSS_ L VSS_ Y VSS_ G VSS_ E VSS_ G VSS_ VSS_ Y VSS_ J VSS_ F VSS_ R VSS_ K VSS_ J VSS_ F VSS_ H VSS_ Y VSS_ K VSS_

12 ST H O (ST) VRT IHM(LG). Ohm pull up to.v for GLN_OMPI/O is required, no matter intel LN is used or not. [] Z_SIN [] ST_LE# [] ST_RXN [] ST_RXP [] ST_TXN [] ST_TXP [] ST_RXN [] ST_RXP [] ST_TXN [] ST_TXP p/v_ p/v_ Internal pull-down resistors that are always enabled R R V_S R.V R Y.KHZ R T T.u/V_.u/V_.u/V_.u/V_ R M_ M/F_ K/F_ K/F_ LK_KX LK_KX RT_RST# SRT_RST# SM_INTRUER# IH_INTVRMEN LN_SLP K_ IH_GPIO./F_ H_IT_LK_R H_SYN_R H_RST#_R H_SIN H_SIN H_SOUT_R ST_TXN_ ST_TXP_ ST_TXN_ ST_TXP_ U RTX RTX RTRST# F SRTRST# INTRUER# INTVRMEN LN_SLP E GLN_LK LN_RSTSYN F LN_RX G LN_RX LN_RX LN_TX LN_TX E LN_TX F H_IT_LK H H_SYN E H_RST# F H_SIN G H_SIN H H_SIN E H_SIN G G GLN_OK#/GPIO GLN_OMPI GLN_OMPO H_SOUT STLE# J STRXN H STRXP F STTXN G STTXP H STRXN J STRXP G STTXN F STTXP IHM REV. RT LP LN / GLN PU IH G H_OK_EN#/GPIO E H_OK_RST#/GPIO ST FWH/L FWH/L FWH/L FWH/L FWH/LFRME# LRQ# LRQ#/GPIO GTE M# PRSTP# PSLP# FERR# PUPWRG IGNNE# INIT# INTR RIN# NMI SMI# STPLK# THRMTRIP# TP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP ST_LKN ST_LKP STRIS# STRIS K K L K K J J N J J E J F E G L F F H G G H J G F H J E F H J H_FERR#_R T T H_THERMTRIP_R J ST_RIS_PN H STIS L<." T LRQ/# : Internal PU R.K_ V R _ R R R./F_ K_./F_ V LK_PIE_ST# [] LK_PIE_ST [] L [,] L [,] L [,] L [,] LFRME# [,] GTE [] H_M# [] H_PWRG [] H_IGNNE# [] H_INIT# [] H_INTR [] RIN# [] H_NMI [] H_SMI# [] H_STPLK# [] H_THERMTRIP_RR.V R *_ R R *_ R _ *_ Layout note: PRSTP#, aisy hain (S>Power>N>PU) IH_PRSTP# [,,] H_PSLP# [].V PM_THRMTRIP# [,].V Intel IHM R _ H_FERR# [] No use Thermal trip S side still PU ohm.(serial R use ohm) Use Thermal trip can share PU for PU and S side(nd Serial R use. ohm) PU L<" JSLQT H udio R *EV@_ MXM_SOUT_HMI [] R *IV@_ H_SOUT_HMI [] H_SOUT_R R _ Z_SOUT_UIO [] Weak integrated P on the H_SOUT pin. *p/v_ R *EV@_ R *IV@_ H_IT_LK_R R _. MHz is output from the IHM. *p/v_ R For EMI H_IT_LK_R *p/v_ MXM_IT_LK_HMI [] H_IT_LK_HMI [] IT_LK_UIO [] *p/v_ RT VPU VRT_ MIL Pjt: TZ Ons: TZ T MIL VRT R K_ u/v_ SRT_RST# G *SHORT_ P R *EV@_ R *EV@_ MXM_SYN_HMI [] MXM_RST#_HMI [] R *IV@_ *p/v_ *_ R *IV@_ H_SYN_HMI [] H_RST#_HMI [] H_SYN_R R _ H_RST#_R R _ Z_SYN_UIO [] Z_RST#_UIO [] Weak integrated P on the H_SYN pins *p/v_ H_SIN R *EV@_ MXM_SIN_HMI [] H_SIN R *IV@_ H_SIN_HMI [] South ridge Strap Pin (/) Pin Name Strap description Sampled onfiguration PU/P R K_ VRT_ MIL RT_N Q *MMT RT_N R u/v_ R *K_ VPU R *.K/F_ u/v_ K_ RT_RST# G *SHORT_ P H_OK_EN/ GPIO Flash escriptor Security Override Strap PWROK = The Flash escriptor Security will be overridden. = The security measures defined in the Flash escriptor will be in effect This strap should only be enabled in manufacturing environments using an external pull-up resistor. N T_ONN R *K/F_ STLE# PI Express Lane Reversal (Lanes -) PWROK Internal PU hange type TP H_SOUT XOR hain Entrance XOR hain Entrance /PI Express* Port onfig bit (Port -) PWROK PWROK IH_TP H_SOUT escription RSV [] IH_TP IH_TP R *K_ Enter XOR hain Normal opration(efault) H_SOUT_R R *K_ V Set PIE port config bit Quanta omputer Inc. PROJET : ZRE Size ocument Number Rev IHM HOST ate: Tuesday, May, Sheet of

13 IHM(LG) INT# INT# INT# INT# U E E E G F F E F F F F G H G H G H J E J PI REQ# GNT# REQ#/GPIO GNT#/GPIO REQ#/GPIO GNT#/GPIO REQ#/GPIO GNT#/GPIO /E# /E# /E# /E# IRY# PR PIRST# EVSEL# PERR# PLOK# SERR# STOP# TRY# FRME# PLTRST# PILK PME# Interrupt I/F PIRQ# PIRQE#/GPIO PIRQ# PIRQF#/GPIO PIRQ# PIRQG#/GPIO PIRQ# PIRQH#/GPIO IHM REV. F G F F E F E R E J F R H K F G REQ# GNT# REQ# GNT# REQ# GNT# REQ# GNT# IRY# PIRST# EVSEL# PERR# LOK# SERR# STOP# TRY# FRME# PLT_RST# INTE# INTF# INTG# INTH# T T T PME# internal PU K~K PIRST# [] PLT_RST# [] PLK_IH [] WLN GLN [] [] [] [] [] [] [] [] PIE_RXN PIE_RXP PIE_TXN PIE_TXP GLN_RXN GLN_RXP GLN_TXN GLN_TXP PLE NER IH WITHIN MIL T T T.u/V_.u/V_.u/V_.u/V_ PIE_TXN_ PIE_TXP_ GLN_TXN_S GLN_TXP_S SPI_LK_S SPI_S# SPI_S# SPI_MOSI SPI_MISO USO# USO# USO# USO# USO# USO# USO# USO# USO# USO# USO# USO# S_USIS N N P P L L M M J J K K G G H H E E F F F E N N N P M N M M N N P P G G U PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PI-Express SPI irect Media Interface MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP PERN MIRXN PERP MIRXP PETN MITXN PETP MITXP PERN MI_LKN PERP MI_LKP PETN PETP MI_ZOMP MI_IROMP PERN/GLN_RXN PERP/GLN_RXP USPN PETN/GLN_TXN USPP PETP/GLN_TXP USPN USPP SPI_LK USPN SPI_S# USPP SPI_S#/GPIO/LGPIO USPN USPP SPI_MOSI USPN SPI_MISO USPP USPN O#/GPIO USPP O#/GPIO USPN O#/GPIO US USPP O#/GPIO USPN O#/GPIO USPP O#/GPIO USPN O#/GPIO USPP O#/GPIO USPN O#/GPIO USPP O#/GPIO USPN O#/GPIO USPP O#/GPIO USPN USPP USRIS USRIS# V V U U Y Y W W T T F F W W Y Y W W V V U U U U MI_IROMP_R R MI_RXN [] MI_RXP [] MI_TXN [] MI_TXP [] MI_RXN [] MI_RXP [] MI_TXN [] MI_TXP [] MI_RXN [] MI_RXP [] MI_TXN [] MI_TXP [] MI_RXN [] MI_RXP [] MI_TXN [] MI_TXP [] LK_PIE_IH# [] LK_PIE_IH []./F_ USP- [] USP [] USP- [] USP [] USP- [] USP [] USP- [] USP [] USP- [] USP [] USP- [] USP [] USP- [] USP [].V EXT-US ardreader EXT-US LUETOOTH Wireless M/ US Port MER R./F_ IHM REV. L<.",void routing next to clock/high speed signals. V South ridge Strap Pin (/).u/v_ Pin Name Strap description Sampled onfiguration PU/P REQ# TRY# STOP# EVSEL# V INT# INT# SERR# INTE# V RN.K_PR RN.K_PR V V REQ# FRME# REQ# INT# INTF# INTG# PLT_RST# USO# USO# USO# USO# V_S RN K_PR U TSHFU R K_ USO# USO# USO# USO# PLTRST# [,,,,] V_S H_SYN GNT# / GPIO GNT# / GPIO GNT# / GPIO SPI_MOSI PI Express Port onfig bit (Port -) PI Express Port onfig bit (Port -) ESI Strap(Server Only) Top-lock Swap Override Integrated TPM Enable PWROK PWROK PWROK PWROK LPWROK = efault = Setting bit = Setting bit = efault = MI for ESI-compatible = efault = "top-block swap" mode = efault = INT TPM disable(efault) = INT TPM enable GNT# SPI_MOSI R R *K_ *K_ V_S LOK# REQ# V RN.K_PR V IRY# PERR# INT# INTH# USO# USO# USO# USO# RN K_PR V_S GNT# SPI_S# / GPIO / LGPIO oot IOS Selection oot IOS Selection PWROK LPWROK PI_GNT# SPI_S# oot Location SPI PI LP(efault) GNT# SPI_S# R R *K_ *K_ Quanta omputer Inc. PROJET : ZRE Size ocument Number Rev IHM PIE / PI / US Tuesday, May, ate: Sheet of

14 V_S R R R R R R R R R R R R R V R R R R R R R R R R R V_S R R R R K_ K_.K_.K_ K_ K_ K_ K_ K_.K_ *K_ K_ K_.K_.K_.K_ K_ *K_ *K_ *K_ K_ K_ K_ K_ K_ */F_ K_ K_ SM_LK_ME SM_T_ME PLK_SM PT_SM RI# IH_GPIO SYS_RST# SM_LERT# PIE_WKE# PM_TLOW# NSWON# IH_GPIO IH_GPIO LKRUN# SERIRQ THERM_LERT# E_SI# HMI_SET STLKREQ# MH_IH_SYN# KSMI#_IH LI#_IH PM_STPPI# PM_STPPU# IH_GPIO R_WKE# IH_PWROK IHM(LG) PWRTN : ms of internal debounce logic on this pin and internal PU K TPM Physical Presence for itpm. Stuff R HMI SET HMI [,,,] [,,,] [] [] [] [] PLK_SM PT_SM SYS_RST# PM_SYN# PM_STPPI# PM_STPPU# [] LKRUN# [,,] PIE_WKE# [] SERIRQ [] THERM_LERT# [] [] [,] [] [] KSMI# LI# E_SI# STLKREQ# [] PSPK MH_IH_SYN# [] IH_TP T T T T T T T S S PLK_SM PT_SM IH_GPIO SM_LK_ME SM_T_ME RI# SYS_RST# SM_LERT# PM_STPPI# PM_STPPU# LKRUN# PIE_WKE# THERM_LERT# VR_PWRG_LKEN KSMI#_IH LI#_IH HMI_SET IH_GPIO IH_GPIO OR_I OR_I PNEL_I OR_I STLKREQ# R_WKE# IH_GPIO IH_GPIO MI_TERM_SEL IH_GPIO MH_IH_SYN# IH_TP G E F R G M E L E M J G H G E K F J L E G F H M J H J J U SMLK SMT LINKLERT#/GPIO/LGPIO SMLINK SMLINK RI# SUS_STT#/LPP# SYS_RESET# PMSYN#/GPIO SMLERT#/GPIO STP_PI# STP_PU# LKRUN# WKE# SERIRQ THRM# VRMPWRG TP IHM REV. SM GPIO GPIO GPIO GPIO LN_PHY_PWR_TRL/GPIO ENERGY_ETET/GPIO GPIO GPIO GPIO SLOK/GPIO GPIO GPIO STLKREQ#/GPIO SLO/GPIO STOUT/GPIO STOUT/GPIO GPIO GPIO/LGPIO SPKR MH_SYN# TP TP TP TP ST GPIO locks SYS GPIO Power MGT MIS GPIO ontroller Link STGP/GPIO STGP/GPIO STGP/GPIO STGP/GPIO LK LK SUSLK SLP_S# SLP_S# SLP_S# S_STTE#/GPIO PWROK PRSLPVR/GPIO TLOW# PWRTN# LN_RST# RSMRST# K_PWRG LPWROK SLP_M# L_LK L_LK L_T L_T L_VREF L_VREF L_RST# L_RST# MEM_LE/GPIO GPIO/SUS_PWR_K GPIO/_PRESENT WOL_EN/GPIO H F E H F P E G G M R R R F F F OR_I PNEL_I IH_GPIO IH_GPIO IH_PWROK PM_TLOW# PM_LN_ENLE_R PM_RSMRST#_R L_VREF_S L_VREF_S IH_GPIO IH_GPIO IH_GPIO R R R T T T T T T T T R R R R R K_ K_ K_ K_ K_ K_ V M_IH [] LKUS_ [] SUS# [] SUS# [] PM_PRSLPVR [,] NSWON# [] *short *_ PM_RSMRST#_R K_PWRG [] MPWROK [,] L_LK [] L_T [] L_RST# [] V_S For EMI(EMI) L_VREF_S V M_IH LKUS_ <hecklist ver.> If integrated LN is not used LN_RST# tie it to GN.N serial R from RSMRST#. If Intel LN is used with Wake On LN, tie LN_RST# to RSMRST# and N ohm. L_PWROK must not assert after PWROK asserts for IMT. L_PWROK to the N and S should be connected to existing PWROK inputs on the N and S on a platform with no IMT L VREF *p/v_ *p/v_ R */F_ R *_ R *_ VREF R connect to V_S hecklist connect to V(iMT reserve) R *.K/F_ *.u/v_ L_VREF_S <hecklist ver.> The IHM ontroller Link VREF circuit is required only if Intel MT is to be supported. V R.K/F_ R /F_.u/V_ R K_ HMI_SET R No HMI V_S IH PWROK Resume RST M/ I I= -->ZK,I= -->ZR I= -->UM,I= -->iscrete R *K_ E_SI# PM_RSMRST#_R Q RSMRST# [] V V V V V R K_ PNEL_I R K_ IH_GPIO R K_ IH_GPIO Follow HEK LIST V. V_S *.u/v_ IH_PWROK U TSHFU R PWROK_E K_ ELY_VR_PWRGOO [,,,] PWROK_E [] R K_ R.K_ MMT R V V.K_ V_S Z INTEL FE (/) "dd RSMRST# isolation (important!!! See ww Santa Rosa MoW)" efault stuff for Teenah(Interposer) chipset ZS Intel FE suggestion to add for to protect RT/MOS data from corruption when system encounters an abnormal power down sequence R R *K_ K_ OR_I OR_I R R K_ *K_ oard I R EV@K_ OR_I R IV@K_ I R K_ OR_I R *K_ I I I -SMT,I= -->UM,I= -->iscrete / South ridge Strap Pin (/) Pin Name Strap description Sampled onfiguration PU/P GPIO PWROK LK Enable U V *.u/v_ / / / / SPKR GPIO No Reboot MI Termination Voltage PWROK PWROK = efault = No Reboot mode = for desktop applications = for mobile applications Internal PU PSPK MI_TERM_SEL R R *K_ *K_ [] VR_PWRG_K# V NSZ VR_PWRG_LKEN R K_ Quanta omputer Inc. PROJET : ZRE Size ocument Number Rev IHM GPIO Tuesday, May, ate: Sheet of

15 IHM(LG) PER INTEL SUGGESTION: HNGE TO OHM & UF V V V_S V_S.V.V.V S:m V S//:m R R.V VRT V.V m V m V S:m S//:m Ohms@ MHz, L LMPGSN. ~.v.u_g.v, Powered by V_ in S R H /F_ H /F_ u/.v_ *short L.V m MOIFY L u/.v_ Power consumption reference to Intel IH Family ES Rev. VPU_IH_VREF_SUS.u/V_.V m.v_ u/.v_ uh m.v_pll_ih u/.v_ u/v_ VLN_ If use S M for LN function. nd support wake up need connect to relation power. uh m.u/v_ S_VREF u/v_.u/v_.u/v_.v m.v m.u/.v_ u/v_ u/v_.u/v_.u/v_ VLN INT_IH.u/V_.V_IH_GLNPLL_R u/.v_.u/.v_ E E E E E E F G H H J J K K L L L M M N N N P P R R R R T T T T U U V V U W W K Y Y J E F G H J E F G G H J G G J E E UF VRT VREF VREF_SUS V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] VSTPLL V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] VUSPLL V [] V [] V [] V [] V [] VLN_[] VLN_[] VLN_[] VLN_[] VGLNPLL VGLN_[] VGLN_[] VGLN_[] VGLN_[] VGLN_ IHM REV. VGP RX TX US ORE GLN POWER ORE VPSUS VPUS VP_ORE PI V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] VMIPLL V_MI[] V_MI[] V_PU_IO[] V_PU_IO[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] VH VSUSH VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VL_ VL_ VL_[] VL_[] E F L L L L L L M M P P T T U U V V V V V V R W Y G J F G F G G J J K J J F F E F T T T T T T U U V V W W Y Y T G G.V_IH_VMIPLL.u/V_ V_H_IO_IH V_VSUSH TP_VSUS IH_ TP_VSUS IH_ TP_VSUS IH_ VSUS INT_IH VL INT_IH VL INT_IH VL_.V_IH_MI.u/.V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_ *u/v_ R.u/V_ If use S M for LN function. nd support wake up need connect to relation power..v m.v.u/v_.v m L uh m.v m, % u/.v_.v m L NQT-Y-N m MHz,. u/.v_ T T T.u/V_.u/V_.u/V_.u/V_.u/V_ *.u/v_.v.v S:m S//:m *short.u/.v_.v m.v m V V_S.V S:m S//:m V.V EV@_ V.V /.V m IV@_.V V_S IV@_.VSUS.V /.V S:m S//:m VSUS_ power by V_ in S / VSUS_ in S/S/S VSUS_ power by V in S / VSUS_ in S/S/S.u/V_.u/V_.u/V_ R R.u/V_ R R EV@_ VL_ power by V in S VL_ power by V in S NOTE: If (G)MH's H udio signals are connected to IHM for ihmi, VH and VSUSH on IHM should be only on.v. These power pins on IHM can be supplied with.v if and only if (G)MH's H is not connected to IHM. onsequently, only.v audio/modem codecs can be used on the platform. E E E E E E E E E E E E F F F F H F F F F F G G G G G G G G H H H H H H H H H H J J J J E E E E E E E E F F F G G G G G G G G H H H H UE VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] IHM REV. VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS_NTF[] VSS_NTF[] VSS_NTF[] VSS_NTF[] VSS_NTF[] VSS_NTF[] VSS_NTF[] VSS_NTF[] VSS_NTF[] VSS_NTF[] VSS_NTF[] VSS_NTF[] H J J J K K L L L L L L L M M M M M M M M M N N N N N N N N N N P P P P P P P P P P P P R R R R R R R R R T T T T T T T U U U U U U U U U V V V V V V V V W W W Y Y Y Y Y G H F H H J J J J.V m.v_ MOIFY.u/.V_.V m V R *short VGLN_ Quanta omputer Inc. PROJET : ZRE Size ocument Number Rev IH POWER Tuesday, May, ate: Sheet of

16 M Q M Q M_LK M M Q PM_EXTTS# M Q M_S# M M M M M_OT M Q M M QS M_LK# M M QS# M QS# M M Q M M M M QS M RS# M_KE M S M M M M_LK M M M QS# M Q M QS M Q M Q M Q M M M Q M Q M Q M Q M Q M Q M_LK# M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q _S _S SL_R S_R M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M QS M M QS# M Q M Q M Q M QS# M QS M QS# M Q M Q M WE# M QS M S M M M M QS M_S# M Q M M QS# M_OT M M M M M QS# M_KE M M M Q M Q M S# M S M Q M Q M M M QS M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q PM_EXTTS# M WE# M S# M M[:] M QS[:] M QS#[:] M RS# M QS[:] M M[:] M QS#[:] M RS# M S# M_S#[:] M_LK#[:] M S[:] M [:] M Q[:] M WE# M [:] M_KE[:] M_OT[:] PM_EXTTS# M Q[:] M_LK[:] M S[:] S_R M M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M QS M M M QS# M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M_LK M Q M Q M_LK# M Q M QS M QS# M_KE M Q M M M Q M M M M_S# M M RS# M S PM_EXTTS# M M_LK M M M M_OT M Q M_LK# M QS# M QS M M M M M Q M M M M_KE M S M M_OT M_OT M_KE M M_KE M M WE# M S# M M M M_KE M M S M M M S M M RS# M M M SL_R _S _S M M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M M Q M Q M Q M M M QS M S M WE# M M Q M QS# M QS M_OT M M S# M QS# M QS# M QS M_KE M M M_S# M M M M M M S M Q M Q M Q M QS M QS# M Q M Q M Q M M M QS# M Q M Q M Q M QS M Q M Q M Q M Q M Q M Q M M_S# M M M RS# M M M M_S# M M S M M M S M M WE# M S# M M M_S# M_S# M M_OT M_OT M S S_R SL_R M [:] [] M QS[:] [] M WE# [] M RS# [] M M[:] [] M Q[:] [] M S[:] [] M QS#[:] [] M QS#[:] [] M S[:] [] M [:] [] M_OT[:] [] M_LK#[:] [] M S# [] M S# [] M QS[:] [] M_LK[:] [] M WE# [] PM_EXTTS# [] M_S#[:] [] M Q[:] [] M RS# [] PT_SM [,,,] PM_EXTTS# [] M_KE[:] [] M M[:] [] PLK_SM [,,,].VSUS.VSUS V.VSUS V.VSUS V SMR_VREF SMR_VTERM SMR_VTERM SMR_VREF.VSUS V.VSUS V Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RII SO-IMM Tuesday, May, ZRE Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RII SO-IMM Tuesday, May, ZRE Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RII SO-IMM Tuesday, May, ZRE R SO-IMM SOKET SMbus address LOK,, KE, TERMINTOR EOUPLING PITOR LOK,, LOSE SO-IMM SOKET PITORS KE, SMbus address LOSE SO-IMM SOKET PITORS R TERMINTOR RN _PR RN _PR R K_ R K_.u/.V_.u/.V_.u/V_.u/V_ R _ R _.u/.v_.u/.v_.u/.v_.u/.v_ R K_ R K_ RN _PR RN _PR Q RHUN Q RHUN R _ R _ RN _PR RN _PR.u/V_.u/V_ RN _PR RN _PR R _ R _ R _ R _ Q RHUN Q RHUN.u/V_.u/V_ R _ R _.u/v_.u/v_.u/v_.u/v_ R _ R _ R _ R _ R _ R _ R _ R _.u/.v_.u/.v_ R _ R _.u/v_.u/v_.u/v_.u/v_ R _ R _ P R SRM SO-IMM (P) N R_H. P R SRM SO-IMM (P) N R_H. VREF VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS M N VSS Q Q VSS KE V N _ V V V /P WE# V S# S# V OT VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS Q Q VSS M VSS Q Q VSS Q Q VSS M VSS K K# VSS Q Q VSS VSS Q Q VSS N M VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS KE V V V V RS# S# V OT V N VSS Q Q VSS M VSS Q Q VSS Q Q VSS VSS M VSS Q Q VSS Q Q VSS NTEST VSS QS# QS VSS Q Q Q Q VSS M VSS Q Q VSS S SL V(SP) QS# QS VSS Q Q VSS Q Q VSS K K# VSS M VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS S S VSS.u/V_.u/V_ R _ R _.u/v_.u/v_ RN _PR RN _PR.u/V_.u/V_.u/V_.u/V_ RN _PR RN _PR RN _PR RN _PR RN _PR RN _PR.u/.V_.u/.V_.u/.V_.u/.V_ RN _PR RN _PR RN _PR RN _PR R K_ R K_ R _ R _.u/v_.u/v_ R _ R _ R K_ R K_.u/V_.u/V_.u/V_.u/V_ R K_ R K_ RN _PR RN _PR R _ R _ R _ R _ RN _PR RN _PR R _ R _.u/.v_.u/.v_ R _ R _.u/.v_.u/.v_.u/v_.u/v_ R _ R _ R K_ R K_.u/V_.u/V_.u/.V_.u/.V_.u/V_.u/V_ R _ R _.u/v_.u/v_.u/.v_.u/.v_ R _ R _ RN _PR RN _PR.u/.V_.u/.V_.u/V_.u/V_.u/.V_.u/.V_ R _ R _ R _ R _ R _ R _ RN _PR RN _PR.u/.V_.u/.V_.u/.V_.u/.V_ R _ R _.u/v_.u/v_ R _ R _.u/v_.u/v_ P R SRM SO-IMM (P) N R_H. P R SRM SO-IMM (P) N R_H. VREF VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS M N VSS Q Q VSS KE V N _ V V V /P WE# V S# S# V OT VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS Q Q VSS M VSS Q Q VSS Q Q VSS M VSS K K# VSS Q Q VSS VSS Q Q VSS N M VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS KE V V V V RS# S# V OT V N VSS Q Q VSS M VSS Q Q VSS Q Q VSS VSS M VSS Q Q VSS Q Q VSS NTEST VSS QS# QS VSS Q Q Q Q VSS M VSS Q Q VSS S SL V(SP) QS# QS VSS Q Q VSS Q Q VSS K K# VSS M VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS S S VSS