VM9M Block Diagram Intel UMA

Transcription

1 GRTIS - FOR FREE lock iagram Intel UM VER : F POWER /TT ONNETOR PG TT HRGER RUN POWER SW +.V_SUS/+V_SUS +V/+.V/+.V PG PG Penryn ( Micro-FPG) PG, 00/0 MHz antiga FN & THERML EM--IZL-TR PG LOK SLGSPV (QFN-) PG LVS POWER REGULTOR +.V_RUN/+.0V_VP PG REGULTOR +.V_SUS /+0.V_R_VTT PG PU VR REGULTOR +.V_LW/+V_SUS/+V_LW PG 0 Panel onnector (WXG) PG PG R-SOIMM* /00 MHZ R II ufg VG RT ONN. PG PG, PG,,,,,0 RTLL RJ/Magnetics MI interface GLN PG PG ST-O PG ST-H PG ST ST IH-M PIE PIE PIE MINI-R WLN PG luetooth PG US.0 IH G PG,,, PIE US.0 US.0 EXPRESS-R US conn x PG PG udio SPK conn Wx UIO/MP X0-0z PG PG udio Jacks x PG MOEM (MOM) X0-Z oard to board RJ-conn PG SPI LP K ITE0 FLSH M bytes PG X PS/ Touchpad PG PG Keyboard PG USER INTERFE PG 0 US.0 PIE -in- ard Reader RU0(a+Media) oard to board PG US conn x oard to board Panel onnector (To ) PG ard Reader ONN. a ONN QUNT OMPUTER Schematic lock iagram PG Size ocument Number Rev ate: Monday, June 0, 00 Sheet of

2 PGE ESRIPTION Schematic lock iagram IHM Table of ontents Front Page Penryn antiga - RII SO-IMM(00P) 0 lock Generator L onn. RT onn Express card SIO (ITE) FLSH/RT LNK PGE Mini ard / T US ST onn TP / KEYOR SWITH /LE FN & Thermal udio OE/Phone Jack oard To oard LN / TRNSFORM LNK PGE attery Selector & harger.0vp /.VRUJN R_.VSUS, 0.V PU_MX0(phase) MX00 (+.V,+,V) RUN Power Switch IN,att & SREW EMI P SMUS LOK Power lock ianram Power States POWER PLNE +PWR_SR +RT_ELL +.V_LW +V_LW +V_LW +.V_LN +V_SUS +.V_SUS +.V_SUS +0.V_R_VTT +V_RUN +.V_RUN +.V_RUN +.0V_VP +V_ORE +LV +V_MO +V_H +PTT VOLTGE 0V~+V +.0V~+.V +.V +V +V +.V +V +.V +.V +0.V +V +.V +.V +.0V +0.V~+.V +.V +V +V +0V~+V PGE,,,,,,,,0,,,,,,,0,,,,0,,,,,0,,,,0,,,0,,0,,,,,,,,,0,,,,,,,,,,,,,,,,,,,0,,,,,,,,,,,,,,0,,,,,, 0,,,,,,,,,,,,,,,,,,,,,,, ESRIPTION MIN POWER RT 0 POWER L/HRGE POWER LRGE POWER LN POWER SLP_S# TRL POWER SLP_S# TRL POWER SOIMM POWER SOIMM POWER SLP_S# TRL POWER SLP_S# TRL POWER LISTOG/IH POWER PU/LISTOG/IH POWER PU ORE POWER L Power Module Power H Power MIN TTERY ONTROL SIGNL LWON LWON +V_LW SUS_ON.V_SUS_ON R_ON 0.V_R_VTT_ON RUN_ON.V_RUN_ON.V_RUN_ON.0V_RUN_ON IMVP_VR_ON LV_TST_EN & ENV HG_PTT TIVE IN S0~S S0~S S0~S S0~S S0~S GN PLNE PGE ESRIPTION GN LL QUNT OMPUTER Index & Power Status Size ocument Number Rev ate: Wednesday, June 0, 00 Sheet of

3 GRTIS - FOR FREE [] H_#[..] [] H_ST#0 [] H_REQ#[0..] [] [] H_#[..] H_ST# [] H_0M# [] H_FERR# [] H_IGNNE# [] H_STPLK# [] H_INTR [] H_NMI [] H_SMI# ITP_TO ITP_TMS ITP_TI ITP_PM# H_#[..] H_REQ#[0..] H_#[..] R ITP_TK R ITP_TRST# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_REQ#0 H_REQ# H_REQ# H_REQ# H_REQ# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# Populate ITP00Flex for bringup R R R R *_N U J H L []# S# E []# NR# L G []# PRI# K []# M H []# EFER# N F []# RY# J E N []# SY# [0]# P F []# R0# P []# L 0 []# IERR# P []# INIT# P []# R H []# LOK# M ST[0]# RESET# K F REQ[0]# RS[0]# H F REQ[]# RS[]# K G REQ[]# RS[]# J G REQ[]# TRY# L REQ[]# G HIT# Y E []# HITM# U []# R []# PM[0]# W [0]# PM[]# U Y []# PM[]# []# PM[]# U []# PRY# R []# PREQ# T []# TK T []# TI W W []# TO []# TMS Y []# TRST# U 0 [0]# R# V []# W []# THERML []# []# []# PROHOT# V ST[]# THERM THERM 0M# FERR# THERMTRIP# IGNNE# STPLK# H LK LINT0 LINT LK[0] SMI# LK[] Quard ore Only F TI_/RSV RSV[0] TO_/RSV R GROUP 0 R GROUP +.0V_VP Layout Note: Place R~R close to PU IH ONTROL XP/ITP SIGNLS N M MP_#[0]/RSV MP_#[]/RSV MP_#[]/RSV E MP_#[]/VSS LKPH_/VSS F LKPH_/VSS T GTLREF_/RSV THRM_/RSV V THRM_/RSV HFPLL_/VSS SPRE_[]/VSS R#/V Penryn all-out Rev a H_#[0..] U [] H_#[0..] H_#0 H_# H_S# [] E Y H_# H_# H_NR# [] F [0]# []# H_# []# []# H_# H_PRI# [] E V H_# []# []# G V H_# H_# []# []# H_# H_EFER# [] F V H_# []# []# H_# H_RY# [] G T H_# []# []# H_# H_SY# [] E U H_# H_# H_R0# [] E []# []# U H_# []# []# K Y H_#0 R H_# []# [0]# G W H_# H_IERR# H_#0 []# []# +.0V_VP J Y H_# H_# [0]# []# H_# H_INIT# [] J W H_# []# []# H W H_# H_# []# []# H_# H_LOK# [] F H_# []# []# K H_# Reserve from EMI R0 0 0 H_# H_# H_RESET# [] H []# []# []# []# H_RS#0 [] [] H_STN#0 J Y STN[0]# STN[]# H_RS# [] [] H_STP#0 H STP[0]# STP[]# H_RS# [] [] H_INV#0 H U INV[0]# INV[]# H_TRY# [] H_#[0..] [] H_#[0..] H_# H_# H_HIT# [] N E H_# []# []# H_# H_HITM# [] K H_# []# []# P H_#0 ITP_PM#0 H_# []# [0]# H_# T0 R ITP_PM# Layout Note: H_#0 []# []# H_# T L ITP_PM# H_# [0]# []# H_# T Place voltage M ITP_PM# H_# H_# T L []# []# 0 ITP_PM# divider within H_# []# []# M H_# T E ITP_PM# 0." of GTLREF H_# []# []# P F H_# ITP_TK pin H_# []# []# P H_# ITP_TI H_# []# []# P E H_# ITP_TO H_# []# []# T H_# ITP_TMS +.0V_VP H_# R []# []# H_#0 ITP_TRST# H_# []# [0]# L H_# ITP_RESET# H_#0 []# []# T H_# T F H_# [0]# []# N H_# R0 []# []# [] H_STN# L E R +.0V_VP K/F STN[]# STN[]# [] H_STP# M F [] H_INV# N STP[]# STP[]# 0 H_PROHOT# INV[]# INV[]# T H_THERM V_PU_GTLREF R OMP0 H_THERM R PU_TEST GTLREF OMP[0] *K/F_N MIS U OMP R *K/F_N PU_TEST TEST OMP[] OMP H_THERMTRIP# R T PU_TEST TEST OMP[] OMP H_THERMTRIP# [,] Y K/F T PU_TEST F TEST OMP[] T0 PU_TEST TEST F E T PU_TEST TEST PRSTP# T PU_TEST TEST PSLP# TEST PWR# LK_PU_LK [] [,] PU_MH_SEL0 SEL[0] PWRGOO LK_PU_LK# [] [,] PU_MH_SEL SEL[] SLP# [,] PU_MH_SEL E SEL[] PSI# Penryn all-out Rev a T Place under PU Q MMST0--F REM_IOE_P REM_IOE_N H_THERM H_THERM 0/0mils 00P 0 ap should close to thermal I 0 00P 0 +.V_RUN 0.U 0 U V P N P OMP0 OMP OMP OMP R./F omp0, connect with Zo=.ohm,omp, connect with Zo=ohm, make those traces length shorter than 0.".Trace should be at least mils away from any other toggling signal. SL 0 S LERT# SYS_SHN# N GN EM--IZL-TR OTP 00 degree SMLK SMT THERM_LERT# SYS_SHN# R./F R./F R./F +.V_RUN +.V_RUN SMLK [,,] SMT [,,] 0 THERM_LERT# [] R.K/F Stephen / Q N00W--F T GRP 0 T GRP T GRP T GRP THERM_STP# [0] H_#[0..] H_#[0..] FS LK SEL SEL SEL to E QUNT OMPUTER Penryn Processor (HOST US) H_STN# [] H_STP# [] H_INV# [] H_#[0..] [] H_STN# [] H_STP# [] H_INV# [] H_#[0..] [] Note: H_PRTSTP need to daisy chain from IH to IMVP to PU. H_PRSTP# [,,] H_PSLP# [] H_PWR# [] H_PWRGOO [] H_PUSLP# [] H_PSI# [] Size ocument Number Rev ate: Saturday, June 0, 00 Sheet of

4 +V_ORE ll use 0U V(+-0%,XS,00)Pb-Free. +V_ORE 0U 0 inside cavity, north side, secondary layer. +V_ORE +V_ORE inside cavity, south side, secondary layer. +V_ORE 0U 0 0U 0 *0U_N 0 *0U_N 0 *0U_N 0 *0U_N 0 0U 0 inside cavity, north side, primary layer. +V_ORE 0U 0 0U 0 0U 0 *0U_N 0 inside cavity, south side, primary layer. +.0V_VP 0U 0 0U 0 *0U_N 0 0U 0 0U 0 0U 0 0 0U 0 0U 0 0U 0 0U 0 0U 0 *0U_N 0 0 0U 0 0 0U 0 0U 0 0U 0 0U 0 0U 0 *0U_N 0 0 0U 0 +V_ORE U V[00] V[00] 0 V[00] V[00] V[00] V[00] V[00] V[00] 0 V[00] V[00] V[0] 0 V[0] V[0] V[0] V[0] V[0] 0 V[0] V[0] 0 V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] 0 V[0] V[0] V[0] V[00] V[0] V[0] E E V[0] V[0] E0 E V[0] V[0] E E V[0] V[0] E V[0] E V[00] E0 V[0] F V[0] F V[0] F0 V[0] F F V[0] V[0] F F V[0] V[0] F V[0] F0 V[00] 0 V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] 0 V[0] V[00] V[0] V[0] V[0] V[0] E V[0] E0 V[0] E V[0] E V[0] E V[0] E V[00] E V[0] E0 V[0] F V[0] F0 V[0] F V[0] F V[0] F V[0] F V[0] F V[0] F0 V[00] G VP[0] V VP[0] J VP[0] K VP[0] M VP[0] J VP[0] K VP[0] M VP[0] N VP[0] N VP[0] R VP[] R VP[] T VP[] T VP[] V VP[] W VP[] V[0] V[0] 0 V[0] V[0] V[0] V[0] VI[0] F V[0] VI[] E V[0] VI[] F V[0] VI[] 0 E V[0] VI[] F V[00] VI[] 0 E 0 V[0] VI[] V[0] V[0] V[0] VSENSE F V[0] V[0] V[0] VSSSENSE E Penryn all-out Rev a. +V_ORE VSENSE VSSSENSE +.0V_VP + 0U VI0 [] VI [] VI [] VI [] VI [] VI [] VI [] VSENSE [] VSSSENSE [] 0.0U VSENSE VSSSENSE +.V_RUN Layout Note: Place near PIN. +V_ORE 0 0U 0 R 00/F R 00/F U VSS[00] VSS[0] VSS[00] VSS[0] VSS[00] VSS[0] VSS[00] VSS[0] VSS[00] VSS[0] VSS[00] VSS[0] VSS[00] VSS[0] F VSS[00] VSS[0] VSS[00] VSS[00] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[] VSS[0] VSS[] VSS[0] VSS[] E VSS[0] VSS[] VSS[0] VSS[] E E VSS[0] VSS[] VSS[0] VSS[] E E VSS[0] VSS[] VSS[0] VSS[0] E VSS[00] VSS[] E VSS[0] VSS[] E VSS[0] VSS[] E VSS[0] VSS[] F VSS[0] VSS[] VSS[] F F VSS[0] VSS[] VSS[0] VSS[] F F VSS[0] VSS[0] VSS[0] F VSS[00] VSS[] F VSS[0] VSS[] F G VSS[0] VSS[] VSS[0] VSS[] G VSS[0] VSS[] G VSS[0] VSS[] G H VSS[0] VSS[] VSS[0] VSS[] H VSS[0] VSS[] H VSS[0] VSS[0] H VSS[00] VSS[] J VSS[0] VSS[] J J VSS[0] VSS[] VSS[0] VSS[] J VSS[0] VSS[] K VSS[0] VSS[] K K VSS[0] VSS[0] VSS[] K VSS[0] VSS[] L VSS[0] VSS[0] L VSS[00] VSS[] L VSS[0] VSS[] L VSS[0] VSS[] M VSS[0] VSS[] M M VSS[0] VSS[] VSS[0] VSS[] M N VSS[0] VSS[] VSS[0] VSS[] N VSS[0] VSS[] N VSS[0] VSS[0] N VSS[00] VSS[] P VSS[0] VSS[] VSS[] Penryn all-out Rev a P P P R R R R T T T T U U U U V V V V W W W W Y Y Y Y E E E E E E. E E F F F F F F F F 0.U 0 0.U 0 0.U 0 0.U 0 Layout out: Place these inside socket cavity on North side secondary. 0.U U 0 Layout Note: Route VSENSE and VSSSENSE traces at.ohms and length matched to within mil. Place PU and P within inch of PU. QUNT OMPUTER Penryn Processor (POWER) Size ocument Number Rev ate: Wednesday, June 0, 00 Sheet of

5 GRTIS - FOR FREE +.0V_VP R /F R 00/F R./F H_SWING H_ROMP 0.U 0 [] Layout Note: H_ROMP trace should be 0-mil wide with 0-mil spacing. +.0V_VP H_#[0..] R K/F R K/F [] [] H_RESET# H_PUSLP# 0.U 0 H_#[0..] H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_SWING H_ROMP H_REF U F H_#_0 G H_#_ F H_#_ E H_#_ G H_#_ H H H_#_ H_#_ F H_#_ H_#_ H H_#_ M H_#_0 M J H_#_ H_#_ J H_#_ N H_#_ J H_#_ P H_#_ L R H_#_ H_#_ N H_#_ L H_#_0 M H_#_ J H_#_ N R H_#_ H_#_ N H_#_ N H_#_ P H_#_ N H_#_ L N0 H_#_ H_#_0 M H_#_ Y H_#_ H_#_ Y H_#_ Y0 Y H_#_ H_#_ Y H_#_ Y H_#_ W H_#_ H_#_0 Y H_#_ H_#_ H_#_ H_#_ H_#_ 0 H_#_ E H_#_ H_#_ E H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ E H_#_ F H_#_ H_#_ E H_#_ E H_#_ H_#_0 E H_#_ G H_#_ H_#_ H_SWING E H_ROMP H_PURST# E H_PUSLP# H_VREF H_VREF NTIG_p0 HOST H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_S# H_ST#_0 H_ST#_ H_NR# H_PRI# H_REQ# H_EFER# H_SY# HPLL_LK HPLL_LK# H_PWR# H_RY# H_HIT# H_HITM# H_LOK# H_TRY# H_INV#_0 H_INV#_ H_INV#_ H_INV#_ H_STN#_0 H_STN#_ H_STN#_ H_STN#_ H_STP#_0 H_STP#_ H_STP#_ H_STP#_ H_REQ#_0 H_REQ#_ H_REQ#_ H_REQ#_ H_REQ#_ H_RS#_0 H_RS#_ H_RS#_ For E test use F H M J P R N M E P F G0 J E0 H J0 L L J H0 K 0 F K L0 H G F G E 0 H H J F H E H J L Y Y L0 M E L M E K F F H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_#[..] H_#[..] [] H_S# [] H_ST#0 [] H_ST# [] H_NR# [] H_PRI# [] H_R0# [] H_EFER# [] H_SY# [] LK_MH_LK [] LK_MH_LK# [] H_PWR# [] H_RY# [] H_HIT# [] H_HITM# [] H_LOK# [] H_TRY# [] H_INV#0 [] H_INV# [] H_INV# [] H_INV# [] H_STN#0 [] H_STN# [] H_STN# [] H_STN# [] H_STP#0 [] H_STP# [] H_STP# [] H_STP# [] H_REQ#0 [] H_REQ# [] H_REQ# [] H_REQ# [] H_REQ# [] H_RS#0 [] H_RS# [] H_RS# [] Layout Note: Place the 0. uf decoupling capacitor within 00 mils from GMH pins. ET0 ET ET ET ET ET ET ET H_STP#0 H_# H_# H_STN# H_STP# H_# H_# H_# antiga (HOST) QUNT OMPUTER Size ocument Number Rev ate: Wednesday, June 0, 00 Sheet of

6 [,] [,] [,] [,,,,,] [] [,,] [] [] [,] SM_ROMP_VOH 0 0.0U SM_ROMP_VOL 0.0U +.V_RUN R R PU_MH_SEL0 PU_MH_SEL PU_MH_SEL T T T T T T T T T T T0 T T T T T T PM_MUSY# H_PRSTP# PM_EXTTS#0 PM_EXTTS# PWROK [,] H_THERMTRIP# [,] PRSLPVR PLTRST#.U 0 0.U 0 0 0K 0K +.V_SUS R K/F R.0K/F R K/F PM_EXTTS#0 PM_EXTTS# Layout Note: Location of all MH_FG strap resistors needs to be close to minmize stub. R PM_EXTTS#0 PM_EXTTS# PLTRST#_R H_THERMTRIP# 00 PLTRST#_R FG FG FG FG FG FG FG FG0 FG FG FG FG FG FG FG FG FG FG0 M N R T H H0 H H K L K N M T J M Y G F H F T R P P0 P N M E N P T R0 M0 L H P R T R N P T0 T T0 R G F H G E H F G H H H H G H F H G E G F F U RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV FG_0 FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_0 FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_0 PM_SYN# PM_PRSTP# PM_EXT_TS#_0 PM_EXT_TS#_ PWROK RSTIN# THERMTRIP# PRSLPVR N_ N_ N_ N_ N_ N_ N_ N_ N_ N_0 N_ N_ N_ N_ N_ N_ N_ N_ N_ N_0 N_ N_ N_ N_ N_ RSV N PM MIS U R ONTROL/OMPENSTION LK MI FG GRPHIS VI ME H S_K_0 S_K_ S_K_0 S_K_ S_K#_0 S_K#_ S_K#_0 S_K#_ S_KE_0 S_KE_ S_KE_0 S_KE_ S_S#_0 S_S#_ S_S#_0 S_S#_ S_OT_0 S_OT_ S_OT_0 S_OT_ SM_ROMP SM_ROMP# SM_ROMP_VOH SM_ROMP_VOL SM_VREF SM_PWROK SM_REXT SM_RMRST# PLL_REF_LK PLL_REF_LK# PLL_REF_SSLK PLL_REF_SSLK# PEG_LK PEG_LK# MI_RXN_0 MI_RXN_ MI_RXN_ MI_RXN_ MI_RXP_0 MI_RXP_ MI_RXP_ MI_RXP_ MI_TXN_0 MI_TXN_ MI_TXN_ MI_TXN_ MI_TXP_0 MI_TXP_ MI_TXP_ MI_TXP_ GFX_VI_0 GFX_VI_ GFX_VI_ GFX_VI_ GFX_VI_ GFX_VR_EN L_LK L_T L_PWROK L_RST# L_VREF P_TRLLK P_TRLT SVO_TRLLK SVO_TRLT LKREQ# IH_SYN# TSTN H_LK H_RST# H_SI H_SO H_SYN P T V U0 R R U V0 Y Y Y V R Y F Y G H F H V R F E F F E E E E H E0 E E H0 E E E H E F H G F E H H N J H N M G E K H 0 SMROMPP SMROMPN SM_ROMP_VOH SM_ROMP_VOL V_R_MH_REF_L MH_LVREF M_LK_R0 [] M_LK_R [] M_LK_R [] M_LK_R [] M_LK_R#0 [] M_LK_R# [] M_LK_R# [] M_LK_R# [] R_KE0_IMM [,] R_KE_IMM [,] R_KE_IMM [,] R_KE_IMM [,] R_S0_IMM# [,] R_S_IMM# [,] R_S_IMM# [,] R_S_IMM# [,] M_OT0 [,] M_OT [,] M_OT [,] M_OT [,] R /F T T0 T00 T T T0 T0 T T T T MH_REFLK [] MH_REFLK# [] REF_SSLK [] REF_SSLK# [] LK_MH_GPLL [] LK_MH_GPLL# [] MI_MRX_ITX_N0 [] MI_MRX_ITX_N [] MI_MRX_ITX_N [] MI_MRX_ITX_N [] MI_MRX_ITX_P0 [] MI_MRX_ITX_P [] MI_MRX_ITX_P [] MI_MRX_ITX_P [] MI_MTX_IRX_N0 [] MI_MTX_IRX_N [] MI_MTX_IRX_N [] MI_MTX_IRX_N [] MI_MTX_IRX_P0 [] MI_MTX_IRX_P [] MI_MTX_IRX_P [] MI_MTX_IRX_P [] L_LK0 [] L_T0 [] IH_L_PWROK [,] IH_L_RST0# [] LK_GPLLREQ# [] MH_IH_SYN# [] T T0 T0 T0 T R +.V_SUS +.0V_VP R *K/F_N R *K/F_N R 0/F +.V_RUN R0.K R.K R 0/F V_R_MH_REF VG_LU VG_GRN VG_RE Non-iMT MH_LVREF 0.U 0 +.0V_VP L_LK L_T SMROMPP SMROMPN L_IG +.V_SUS R Layout Note: 0/F Place 0 ohm termination resistors close to GMH. R K/F R /F R 0./F R 0./F +.V_RUN R.K/F FG FG FG FG FG0 R R0 [] [] [] [] [] 0K/F [] G_LK_ [] G_T_ [] VGHSYN [] 0K/F [] [] [] [] [] [] [] [] [] [] [] VGVSYN I_PWM PNEL_KEN L_LK L_T ENV L_0- L_- L_- L_LK- L_LK+ T0 T0 L_0+ L_+ L_+ VG_LU VG_GRN VG_RE VG_LU VG_GRN VG_RE L_TRL_LK L_TRL_T L_LK L_T L_IG Low=MIx MI X Select High=MIx(efault) PI Express Graphic Lane FS ynamic OT MI Lane Reversal SVO/PIE oncurrent Operation T Low= Reveise Lane High=Normal operation Low=ynamic OT isable High=ynamic OT Enable(default). Low=Normal(default). High=Lane Reversed Low=Only SVO or PIEx is operational (defaults) High=SVO and PIEx are operating simultaneously via PEG port Low=No SVO evice Present (default) SVO_RTL_T SVO Present. High=SVO evice Present R R R T0 T T T0 T T /F_ /F_ /F_ R 0/F R.K/F R 0/F L G M M K J M E E 0 H E G0 0 H F0 0 H G J G F K F H K H E E G J G H J J E L L_KLT_TRL L_KLT_EN L_TRL_LK L_TRL_T L LK L T L_V_EN LVS_IG LVS_VG LVS_VREFH LVS_VREFL LVS_LK# LVS_LK LVS_LK# LVS_LK LVS_T#_0 LVS_T#_ LVS_T#_ LVS_T#_ LVS_T_0 LVS_T_ LVS_T_ LVS_T_ LVS_T#_0 LVS_T#_ LVS_T#_ LVS_T#_ LVS_T_0 LVS_T_ LVS_T_ LVS_T_ TV_ TV_ TV_ TV_RTN TV_ONSEL_0 TV_ONSEL_ RT_LUE RT_GREEN RT_RE RT_IRTN RT LK RT T RT_HSYN RT_TVO_IREF RT_VSYN NTIG_p0 LVS TV PI-EXPRESS GRPHIS VG PEG_OMPI PEG_OMPO PEG_RX#_0 PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_0 PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX_0 PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_0 PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_TX#_0 PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_0 PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX_0 PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_0 PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ R T VG_PIE_R T H J L L0 N P N T U Y Y Y H J L L N0 P N T U Y W Y 0 J M M M0 M R N T0 U U0 Y0 0 J L M M M R N T U U Y Y +V_PEG./F NTIG_p0 QUNT OMPUTER antiga (VG,MI) Size ocument Number Rev Saturday, June 0, 00 ate: Sheet of

7 R R R R R R R R R R R R R R R 0 R R R R R 0 R R R R 0 R R R R R R R R 0 R R R R R R 0 R R R R 0 R R R R R R R R R R R R R R R R R R R R R R 0 R S R S0 R S R 0 R R R R R R R 0 R R R R R R R R R R R R R 0 R R R R R R 0 R R R R R R R R R R R R R R R 0 R R R R R R R 0 R R R R R R R R R R R R R 0 R R R S R S0 R S R S# R M R RS# R WE# R M0 R M R M R M R M R M R M R M R M R M0 R M R M R M R M R QS0 R QS R QS R QS R QS R QS R QS R QS R QS#0 R QS# R QS# R QS# R QS# R QS# R QS# R QS# R M0 R M R M R M R M R M R M R M R S# R WE# R RS# R M0 R QS#0 R QS# R QS# R QS# R QS# R QS# R QS# R QS# R M R M R M R M R M R M0 R M R M R M R M R M R M R M R M R M R QS0 R QS R QS R QS R QS R QS R QS R QS R M R M0 R M R M R M R M R M R [0..] [] R S [,] R S0 [,] R S [,] R [0..] [] R S# [,] R S [,] R S0 [,] R S [,] R RS# [,] R WE# [,] R M[0..] [,] R QS#[0..] [] R QS[0..] [] R M[0..] [] R S# [,] R WE# [,] R RS# [,] R QS#[0..] [] R M[0..] [,] R QS[0..] [] R M[0..] [] Size ocument Number Rev ate: Sheet of QUNT OMPUTER antiga (R) Saturday, June 0, 00 Size ocument Number Rev ate: Sheet of QUNT OMPUTER antiga (R) Saturday, June 0, 00 Size ocument Number Rev ate: Sheet of QUNT OMPUTER antiga (R) Saturday, June 0, 00 R SYSTEM MEMORY U NTIG_p0 R SYSTEM MEMORY U NTIG_p0 S_Q_0 J S_Q_ J S_Q_0 U0 S_Q_ T S_Q_ N S_Q_ N S_Q_ U S_Q_ U S_Q_ V S_Q_ Y S_Q_ 0 S_Q_ S_Q_ N S_Q_0 V S_Q_ Y S_Q_ S_Q_ 0 S_Q_ Y S_Q_ S_Q_ V S_Q_ T S_Q_ Y S_Q_ S_Q_ M S_Q_0 V S_Q_ W S_Q_ S_Q_ U S_Q_ S_Q_ S_Q_ U S_Q_ V S_Q_ S_Q_ S_Q_ J S_Q_0 S_Q_ S_Q_ U0 S_Q_ V S_Q_ S_Q_ S_Q_ Y S_Q_ S_Q_ V S_Q_ V S_Q_ J0 S_Q_0 T S_Q_ N S_Q_ U S_Q_ U S_Q_ T S_Q_ N0 S_Q_ M S_Q_ M S_Q_ J S_Q_ J S_Q_ M S_Q_0 N S_Q_ M S_Q_ J S_Q_ J S_Q_ M S_Q_ N S_Q_ N S_S_0 S_S_ G S_S_ T S_S# 0 S_M_0 M S_M_ T S_M_ Y S_M_ U S_M_ S_M_ Y S_M_ T S_QS_0 J S_QS_ T S_QS_ S_QS_ S_QS_ W S_QS_ S_QS_ U S_QS_ M S_M_ J S_QS#_0 J S_QS#_ T S_QS#_ S_QS#_ S_QS#_ Y S_QS#_ S_QS#_ U S_QS#_ M S_M_0 S_M_ S_M_0 S_M_ G S_M_ H S_M_ H S_M_ G S_M_ H S_M_ G S_M_ S_M_ S_M_ G S_M_ F S_M_ W S_RS# 0 S_WE# Y0 S_M_ Y R SYSTEM MEMORY UE NTIG_p0 R SYSTEM MEMORY UE NTIG_p0 S_Q_0 K S_Q_ H S_Q_0 S_Q_ Y S_Q_ T S_Q_ R S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ G S_Q_ F S_Q_ P S_Q_0 E S_Q_ S_Q_ F0 S_Q_ F S_Q_ G S_Q_ F S_Q_ H S_Q_ G S_Q_ H0 S_Q_ G S_Q_ P S_Q_0 G S_Q_ H S_Q_ H S_Q_ G S_Q_ H S_Q_ G S_Q_ H S_Q_ F S_Q_ F S_Q_ G S_Q_ J S_Q_0 S_Q_ S_Q_ Y S_Q_ Y S_Q_ F S_Q_ F S_Q_ S_Q_ S_Q_ V S_Q_ U S_Q_ J S_Q_0 R S_Q_ N S_Q_ Y S_Q_ V S_Q_ P S_Q_ R S_Q_ L S_Q_ L S_Q_ J S_Q_ H S_Q_ M S_Q_0 M S_Q_ M S_Q_ H S_Q_ J S_Q_ P S_Q_ U S_Q_ U S_S_0 S_S_ S_S_ S_S# G S_M_0 M S_M_ Y S_M_ 0 S_M_ F S_M_ G S_M_ S_M_ P S_M_ K S_QS_0 L S_QS_ V S_QS_ G S_QS_ G S_QS_ H S_QS_ S_QS_ U S_QS_ N S_QS#_0 L S_QS#_ V S_QS#_ H S_QS#_ H S_QS#_ G S_QS#_ S_QS#_ T S_QS#_ N S_M_0 V S_M_ S_M_0 S_M_ W S_M_ Y S_M_ H S_M_ S_M_ U S_M_ W S_M_ S_M_ U S_M_ W S_M_ T S_M_ S_M_ U S_RS# U S_WE# F hexainf@hotmail.com GRTIS - FOR FREE

8 +.V_SUS UG UF +.V_RUN +.0V_VP +.0V_VP R0 *0_N R *0_N P V_SM_ N V_SM_ H V_SM_ G V_SM_ F V_SM_ V_SM_ V_SM_ V_SM_ Y V_SM_ V_SM_0 W V_SM_ V V_SM_ U T V_SM_ V_SM_ R P V_SM_ V_SM_ N H V_SM_ V_SM_ G F V_SM_ V_SM_0 G0 V_SM_ H V_SM_ G V_SM_ F V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ Y W V_SM_ V_SM_0 V U V_SM_ V_SM_ T R V_SM_ V_SM_ P V_SM_ V_SM_/N V_SM_/N V_SM_/N V_SM_/N W V_SM_0/N W V_SM_/N T V_SM_/N Y E V_XG_ V_XG_ V_XG_ V_XG_ E V_XG_ V_XG_ V_XG_ Y V_XG_ E V_XG_ V_XG_0 V_XG_ V_XG_ J V_XG_ G V_XG_ E V_XG_ V_XG_ V_XG_ Y V_XG_ H0 F0 V_XG_ V_XG_0 E0 V_XG_ 0 V_XG_ 0 V_XG_ 0 V_XG_ T V_XG_ T V_XG_ M L V_XG_ V_XG_ E J V_XG_ V_XG_0 H V_XG_ G V_XG_ F V_XG_ V_XG_ Y V_XG_ V_XG_ V U V_XG_ V_XG_ N V_XG_ M V_XG_0 U T V_XG_ V_XG_ J V_XG_SENSE H VSS_XG_SENSE NTIG_p0 POWER V SM V GFX V GFX NTF V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V SM LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF W V W V W V W V W V M L K W V U M0 K0 W0 U0 M L K J H G F E Y W V U M K H G F E Y W V M L K J H G F E Y W V U V M0 V Y M0 VSM_LF VSM_LF VSM_LF VSM_LF VSM_LF VSM_LF VSM_LF 0.U 0 0.U 0 0.U 0 +.0V_VP Layout Note: 0 mils from edge. 0.U 0 + 0U Layout Note: Inside GMH cavity for V_XG. 0 U 0 +.V_SUS 0 U 0.U Layout Note: Inside GMH cavity. 0.U 0 Layout Note: Place where LVS and R taps. +.0V_VP +.0V_VP +.0V_VP +.0V_VP *0.U_N 0 U 0 0 *0.U_N 0 0.U V_VP +.0V_VP +.0V_VP 0.U 0 0 0U 0. *0.U_N 0 0.U *0.U_N 0 0.U 0 0 U 0 0 R0 0 *0.U_N 0 *0.U_N *0U_N *0U_N U 0 0 +V_GMH_L 0.U V_VP Layout Note: 0 mils from edge. + 0U/.V_ Leon / 0 *0.U_N 0 RV-0 0.U 0 U 0 V_SM U 0 Layout Note: Place on the edge. G V_ V_ V_ Y V_ V_ V U V_ V_ M K V_ V_ J V_0 G V_ F V_ E V_ V_ Y V_ V_ W V V_ V_ U V_ H V_0 F V_ V_ V_ J V_ G V_ E V_ H V_ V_ G F V_ V_0 G J V_ V_ H F V_ V_ T V_ V ORE POWER NTIG_p0 antiga (V,NTF) V NTF QUNT OMPUTER V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ M L K J H G E Y W U M0 L0 K0 H0 G0 F0 E Y0 W0 V0 U0 L K J H G E Y W V L K L K K K K +.0V_VP Size ocument Number Rev ate: Wednesday, June 0, 00 Sheet of

9 GRTIS - FOR FREE +.V_RUN 0 R0 0./F 0 +V_MPLL_L +.0V_VP +.V_RUN +.V_RUN F_0ohm+-%_00mHz_00m_0.0ohm Remove R00 0ohm resistor Ray / L LMPGSN +V_RT 0 +V_HPLL +V_MPLL F_0ohm+-%_00MHz 0.ohm +V G Non-iMT m Mx. +.0V_VP F_0ohm+-%_00mHz _00m_0.ohm L L U 0 0 LM0S 0 LM0S L.U 0. 0.U 0 0.0U LMPSGPT +V_PEG_PLL 0 0 0U 0. +V_TV +V_TV +V_Q +.0V_VP 0.aps should be placed 00 mils with in its pins. +.0V_VP +.0V_VP F_0ohm+-%_00mHz_00m_0.0ohm L LMPGSN 0 Remove R0 0ohm resistor Ray / L LMPGSN U 0 0.U 0 0.U 0 0.U 0 R0 /F 0 0.0U 0 0.0U 0.0U 0.U 0 0.0U Remove R 0ohm Ray / 0.U 0 L 0uH 0 +.0V_VP 0m Mx. 0uH+-0%_00m +V_PLL L 0uH *0U_N +V_PLL + 0 *0U_N L uh/00m UH 0U 0..U 0. U 0 0U 0. +.V_SUS 0.U 0 0 U 0 0 Remove R 0ohm resistor Ray / L 0 0.U 0 0 U 0 F_0ohm+-%_00MHz 0.ohm +.V_RUN 0.U 0 U 0 0.U 0 0.U 0 LMPSGPT +V_PEG_PLL 0 R0 /F 0 0 0U P 0 U 0 0 U 0 0 +V_RT +V G +V_PLL +V_PLL +V_HPLL +V_MPLL +V_TX_LVS +V_PEG_PLL +V_SM_K 0 0.U 0 +V_TV +V_H +V_TV +V_Q +V_MPLL +V_PEG_PLL U 0 0 *0U_N 0. +VTTLF +VTTLF +VTTLF V_RT V_RT V G VSS G F L E J J V_PLL V_PLL V_HPLL V_MPLL V_LVS V_PEG_G V_PEG_PLL R0 V_SM_ P0 V_SM_ N0 V_SM_ R P V_SM_ V_SM_ N V_SM_ T V_SM_ R V_SM_ P V_SM_ V_TV V_TV F V_HPLL V_PEG_PLL NTIG_p0 RT PLL LVS PEG SM P N V_SM_K_ V_SM_K_ P V_SM_K_ N V_SM_K_ N V_SM_K_ M V_SM_K_NTF_ M M V_SM_K_NTF_ V_SM_K_NTF_ L V_SM_K_NTF_ M V_SM_K_NTF_ L V_SM_K_NTF_ M V_SM_K_NTF_ L V_SM_K_NTF_ M L VSS_LVS V_H V_TV V_Q M V_LVS_ L V_LVS_ 0.U U 0 0 TV H LVS POWER K TV/RT 0.U 0 0 XF SM K MI HV PEG VTT VTTLF U VTT_ T VTT_ U VTT_ T VTT_ U VTT_ T VTT_ U0 VTT_ T0 VTT_ U VTT_ T VTT_0 U VTT_ T VTT_ U VTT_ T VTT_ U VTT_ T VTT_ U VTT_ T VTT_ V VTT_ U VTT_0 V VTT_ U VTT_ T VTT_ V VTT_ U VTT_ V_XF_ V_XF_ V_XF_ F V_SM_K_ H0 V_SM_K_ G0 V_SM_K_ F0 V_SM_K_ V_TX_LVS K V_HV_ V_HV_ V_HV_ V V_PEG_ U V_PEG_ V V_PEG_ U V_PEG_ U V_PEG_ H V_MI_ F V_MI_ H V_MI_ G V_MI_ VTTLF L VTTLF VTTLF +V_SM_K +V_TX_LVS +V_RXR_MI +VTTLF +VTTLF +VTTLF.U 0 0.U 0. lose to VTT U U P U 00 0.U 0 0.U. +V_PEG R /F 0 0U 0. U 0 0 antiga (POWER) +.0V_VP +.V_RUN QUNT OMPUTER Place on the edge. Remove L 0ohm resistor Ray / 0U 0. L.U 0. nh/. L uh/00m 0 0.U 0 0.U U L 0 uh/00m +.0V_VP +.V_SUS +.0V_VP +.V_SUS Remove R 0ohm Ray / +.0V_VP Size ocument Number Rev ate: Saturday, June 0, 00 Sheet of

10 Size ocument Number Rev ate: Sheet of QUNT OMPUTER antiga (VSS) 0 Wednesday, June 0, 00 Size ocument Number Rev ate: Sheet of QUNT OMPUTER antiga (VSS) 0 Wednesday, June 0, 00 Size ocument Number Rev ate: Sheet of QUNT OMPUTER antiga (VSS) 0 Wednesday, June 0, 00 VSS VSS NTF VSS S N UJ NTIG_p0 VSS VSS NTF VSS S N UJ NTIG_p0 VSS_ G VSS_0 W VSS_0 U VSS_0 P VSS_0 N VSS_0 H VSS_0 F VSS_0 VSS_0 R VSS_0 M VSS_0 J VSS_ G VSS_ 0 VSS_ 0 VSS_ W0 VSS_ T0 VSS_ J0 VSS_ G0 VSS_ Y0 VSS_ N0 VSS_0 K0 VSS_ F0 VSS_ 0 VSS_ 0 VSS_ G VSS_ VSS_ G VSS_ VSS_ W VSS_ T VSS_0 R VSS_ M VSS_ H VSS_ VSS_ VSS_ U VSS_ N VSS_ N VSS_0 K VSS_ G VSS_ E VSS_ G VSS_ W VSS_ VSS_ G VSS_ VSS_ VSS_0 G VSS_ VSS_ VSS_ N VSS_ J VSS_ E VSS_ N VSS_ L VSS_0 G VSS_ E VSS_ F VSS_ V VSS_ T VSS_ M VSS_ VSS_ J VSS_ VSS_ VSS_0 VSS_ Y VSS_ N VSS_ H VSS_ Y VSS_ N VSS_ G VSS_ VSS_ G0 VSS_0 V0 VSS_ T0 VSS_ J0 VSS_ E0 VSS_ 0 VSS_ H VSS_ VSS_ G VSS_0 VSS_ M VSS_ N VSS_ VSS_ M0 VSS_ F VSS_ H VSS_ Y VSS_ L VSS_00 E VSS_0 VSS_0 Y VSS_0 U VSS_0 N VSS_0 J VSS_0 E VSS_0 VSS_0 N VSS_0 J VSS_0 G VSS_ VSS_ V VSS_ T VSS_ VSS_ M VSS_ M VSS_ VSS_ VSS_ H VSS_ VSS_0 Y VSS_ L VSS_ J VSS_ H VSS_ F VSS_ E VSS_ VSS_ V VSS_ L VSS_NTF_ F VSS_NTF_ VSS_NTF_ V VSS_NTF_ J0 VSS_NTF_ M VSS_NTF_ F VSS_NTF_ VSS_NTF_ U VSS_NTF_ U VSS_NTF_0 L0 VSS_NTF_ V0 VSS_NTF_ VSS_NTF_ L VSS_NTF_ J VSS_NTF_ VSS_NTF_ U VSS_S_ H VSS_S_ H VSS_S_ VSS_S_ VSS_S_ VSS_S_ N_ E N_ N_ N_ N_0 N_ N_ N_ N_ N_ N_ N_ N_ N_ F N_0 E N_ N_ VSS_0 R VSS_ P VSS_ VSS_ R VSS_ U VSS_ P VSS_ F VSS_ W VSS_ E VSS_0 F VSS_ H VSS_ J VSS_ VSS_ VSS_ Y VSS_ M VSS_ K VSS_ M VSS_ VSS_ P VSS_0 H VSS_ VSS_ V VSS_ T VSS_ U VSS_ U VSS_ U VSS_ U VSS_00 L VSS UI NTIG_p0 VSS UI NTIG_p0 VSS_ U VSS_ VSS_ R VSS_ L VSS_ VSS_ W VSS_ N VSS_ J VSS_ F VSS_ VSS_0 VSS_ Y VSS_ T VSS_ N VSS_ L VSS_ G VSS_ VSS_ VSS_ V VSS_0 R VSS_ M VSS_ V VSS_ R VSS_ P VSS_ H VSS_ F VSS_ F VSS_ H VSS_ VSS_0 VSS_ Y VSS_ U VSS_ T VSS_ M VSS_ F VSS_ VSS_ V VSS_ U VSS_ M VSS_0 J VSS_ VSS_ G VSS_ Y VSS_ T VSS_ N VSS_ J VSS_ E VSS_ N VSS_ L VSS_0 VSS_ U VSS_ M VSS_ H VSS_ VSS_ VSS_ Y VSS_ U VSS_ T VSS_ M VSS_0 G VSS_ VSS_ G0 VSS_ 0 VSS_ V0 VSS_ N0 VSS_ H0 VSS_ E0 VSS_ T VSS_ M VSS_0 J VSS_ E VSS_ N VSS_ L VSS_ VSS_ H VSS_ VSS_ VSS_ U VSS_ H VSS_0 VSS_ VSS_ Y VSS_ U VSS_ T VSS_ J VSS_ F VSS_ VSS_ VSS_00 M VSS_0 E VSS_0 P VSS_0 L VSS_0 J VSS_0 F VSS_0 VSS_0 H VSS_0 VSS_0 Y VSS_0 U VSS_ T VSS_ F VSS_ M VSS_ J VSS_ F VSS_ E VSS_ W VSS_ VSS_ VSS_0 G VSS_ VSS_ VSS_ V VSS_ R VSS_ L VSS_ H VSS_ VSS_ P VSS_ L VSS_0 H VSS_ N VSS_ K VSS_ F VSS_ VSS_ VSS_ N VSS_ T VSS_ N VSS_ K VSS_0 H VSS_ F VSS_ VSS_ G VSS_ VSS_ VSS_ V VSS_ T VSS_ R VSS_ J VSS_0 G VSS_ E VSS_ VSS_ Y VSS_ P VSS_ K VSS_ H VSS_ F VSS_ VSS_ F VSS_0 H VSS_ F VSS_ VSS_ VSS_ VSS_ VSS_ H VSS_ VSS_ VSS_ V VSS_0 R VSS_ J VSS_ VSS_ Y VSS_ N VSS_ L VSS_ J VSS_ G VSS_ E VSS_ F VSS_ F VSS_ VSS_0 W VSS_ T VSS_ N VSS_ J VSS_ H VSS_ VSS_ G VSS_ U VSS_ T VSS_ H VSS_ VSS_ L VSS_ Y VSS_ G VSS_ E VSS_ G VSS_ VSS_ Y VSS_ J VSS_ F VSS_ R VSS_ K VSS_0 J VSS_ F VSS_ H VSS_ Y VSS_ K VSS_0

11 GRTIS - FOR FREE.KHZ R0 0M IH_RTX W IH_RTX +RT_ELL P/0V.KHZ P/0V R K/F IH_INTVRMEN +RT_ELL [] [] [] [] [] IH_Z_OE_ITLK [] IH_Z_OE_SYN [,] IH_Z_OE_RST# [] IH_Z_OE_SOUT [] ST_RX0- Master H [] ST_RX0+ ST_TX0- ST_TX0+ ST_TX- ST_TX+ R M IH_RTRST# IH_SRTRST# IH_INTRUER# Place all series terms close to IH except for SIN input lines,which should be close to source. R 0K U/0V R 0K 0 U/0V 0.0U/V 0.0U/V 0.0U/V 0.0U/V R L *uh_n 0 *P/0V_N R R R ST_TX0-_ ST_TX0+_ ST_TX-_ ST_TX+_ Z_IT_LK Z_SYN Z_RST# Z_SOUT IHM Internal VR Enable Strap (Internal VR for VccSus.0, VccSus., VccL.) IH_INTVRMEN Reserved for Intel Nineveh T design. T0 T T T T +.V_SUS +.V_PIE_IH [] IH_Z_OE_SIN0 T T T Low = Internal VR isabled High = Internal VR Enabled(efault) [0] ST_T# [] ST_RX- [] ST_RX+ ST O T R0 *0K_N IH_RTX IH_RTX IH_RTRST# IH_SRTRST# IH_INTRUER# IH_INTVRMEN GLN_LK LN_RX0 LN_RX LN_RX LN_TX0 LN_TX LN_TX R./F GLN_OMP Z_IT_LK Z_SYN Z_RST# Z_SOUT ST_TX0-_ ST_TX0+_ ST_TX-_ ST_TX+_ IHM LN00 SLP Strap (Internal VR for VccLN.0 and VccL.0) IH_LN00_SLP U RTX RTX RTRST# F0 SRTRST# INTRUER# INTVRMEN LN00_SLP E GLN_LK LN_RSTSYN F LN_RX0 G LN_RX LN_RX LN_TX0 LN_TX E LN_TX 0 F H_IT_LK H H_SYN E H_RST# F H_SIN0 G H_SIN H H_SIN E H_SIN G G GLN_OK#/GPIO GLN_OMPI GLN_OMPO H_SOUT STLE# J ST0RXN H ST0RXP F ST0TXN G ST0TXP H STRXN J STRXP G STTXN F STTXP IHM REV.0 Low = Internal VR isabled High = Internal VR Enabled(efault) RT LP LN / GLN PU IH G H_OK_EN#/GPIO E H_OK_RST#/GPIO ST K FWH0/L0 K FWH/L L FWH/L K FWH/L FWH/LFRME# K J LRQ0# J LRQ#/GPIO 0GTE N J 0M# J PRSTP# E PSLP# FERR# PUPWRG IGNNE# J F E INIT# INTR G L RIN# F NMI F SMI# STPLK# THRMTRIP# TP H G G STRXN H STRXP J STTXN G STTXP F STRXN H STRXP J STTXN E0 STTXP F0 ST_LKN H ST_LKP J J STRIS# STRIS H SIO_0GTE H_PRSTP# H_PSLP# H_FERR#_L R SIO_RIN# R STIS H_THERMTRIP#./F R LP_L0 [,] LP_L [,] LP_L [,] LP_L [,] LP_LFRME# [,] SIO_0GTE [] H_0M# [] H_PRSTP# [,,] H_PSLP# [] H_FERR# H_PWRGOO [] H_IGNNE# [] H_INIT# [] H_INTR [] SIO_RIN# [] H_NMI [] H_SMI# [] H_STPLK# [] T T T T T T T0 LK_PIE_ST# [] LK_PIE_ST [] H_FERR# [] H_THERMTRIP# [,] Place within 00mils of IH ball H_PRSTP# H_PSLP# H_FERR# SIO_0GTE SIO_RIN# H_THERMTRIP# R *_N R0.K +.0V_VP R *_N +.V_RUN +.0V_VP R R 0K R +.V_RUN IH RSV 0 0 XOR hain Entrance Strap H SOUT escription 0 RSV Enter XOR hain 0 Normal Operation (efault) Set PIE port config bit R *K_N Z_SOUT R *K_N IH_RSV [] QUNT OMPUTER IH-M (PU,ST,LP,LN,OE) Size ocument Number Rev ate: Saturday, June 0, 00 Sheet of

12 Place TX blocking caps close IH. [] PIE_RX- [] PIE_RX+ [] PIE_TX- [] PIE_TX+ +.V_SUS O# O# O# O# O0# O# 0.U 0.U 0 0.U 0.U 0.U 0.U 0.U 0 0.U LP PI SPI RP 0KX R0 R oot IOS Strap 0 0 0K 0K GNT0# No stuff No stuff Stuff +.V_SUS O# US_O_# US_O0_# O# PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ GLN_TXN_ GLN_TXP_ SPI_S# No stuff Stuff No stuff +.V_SUS U N PERN MI0RXN V MI_MTX_IRX_N0 [] N PERP MI0RXP V MI_MTX_IRX_P0 [] P PETN MI0TXN U MI_MRX_ITX_N0 [] P PETP MI0TXP U MI_MRX_ITX_P0 [] MiniWWN MiniWLN MiniWPN Express ard [] PIE_RX-/GLN_RX- [] PIE_RX+/GLN_RX+ [] PIE_RX- [] PIE_RX+ [] PIE_TX- [] PIE_TX+ +ardreader [] PIE_TX- [] PIE_TX+ [] PIE_TX-/GLN_TX- [] PIE_TX+/GLN_TX+ [] PIE_RX- [] PIE_RX+ Giga it LOM T T T T0 T [] US_O0_# [] US_O_# R./F PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ GLN_TXN_ GLN_TXP_ SPI_LK_R SPI_S#0_R IH_SPI_S#_R SPI_MOSI SPI_MISO US_O0_# US_O_# O# O# O# O# O# O# O0# O# USRIS Places within 00 mils of the IH L PERN L PERP M M PETN PETP J PERN J K PERP PETN K PETP G G PERN PERP H H PETN PETP G USRIS G USRIS# IHM REV.0 PI-Express SPI irect Media Interface MIRXN Y MIRXP Y MITXN W MITXP W MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP E PERN MI_LKN T E F PERP MI_LKP T PETN F PETP MI_ZOMP F MI_IROMP F PERN/GLN_RXN PERP/GLN_RXP USP0N PETN/GLN_TXN USP0P PETP/GLN_TXP USPN USPP SPI_LK USPN USPP F SPI_S0# SPI_S#/GPIO/LGPIO USPN USPP SPI_MOSI USPN E SPI_MISO USPP USPN N N O0#/GPIO USPP O#/GPIO0 USPN N O#/GPIO US W P USPP W O#/GPIO USPN Y M O#/GPIO USPP Y N O#/GPIO USPN W M O#/GPIO0 USPP W M O#/GPIO USPN V N O#/GPIO USPP V N O#/GPIIO USP0N U P P O0#/GPIO USP0P U O#/GPIO USPN U USPP U MI_MTX_IRX_N [] MI_MTX_IRX_P [] MI_MRX_ITX_N [] MI_MRX_ITX_P [] MI_MTX_IRX_N [] MI_MTX_IRX_P [] MI_MRX_ITX_N [] MI_MRX_ITX_P [] MI_MTX_IRX_N [] MI_MTX_IRX_P [] MI_MRX_ITX_N [] MI_MRX_ITX_P [] LK_PIE_IH# [] LK_PIE_IH [] MI_OMP R./F +.V_PIE_IH Place within 00mils of IH IH_USP0- [] IH_USP0+ [] Side Pair Left IH_USP- [] IH_USP+ [] Side Pair Left IH_USP- [] IH_USP+ [] Side Pair Right IH_USP- [] IH_USP+ [] Side Pair Right IH_USP- [] IH_USP+ [] amera T Mini ard (WWN) PI Pullups T IH_USP- [] IH_USP+ [] luetooth IH_USP- [] IH_USP+ [] Express ard PI_FRME# IH_USP- [] PI_TRY# Mini ard (WLN) IH_USP+ [] PI_EVSEL# T0 PI_REQ# T +.V_RUN 0 T T T T PI_IRY# PI_PIRQ# PI_PIRQE# PI_PIRQ# 0 +.V_RUN PI_REQ# RP RP R0.K +.V_RUN PI_PLOK# PI_STOP# PI_PIRQ# PI_PERR# +.V_RUN PI_PIRQ# PI_REQ0# IH_IRQH_GPIO PI_SERR# +.V_RUN +.V_RUN GPIO R.K GPIO R.K PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# U 0 E E E0 G 0 F F E F0 0 F 0 F F G H G H G 0 H PI Interrupt I/F J PIRQ# E PIRQ# J PIRQ# PIRQ# IHM REV.0 REQ0# GNT0# REQ#/GPIO0 GNT#/GPIO REQ#/GPIO GNT#/GPIO REQ#/GPIO GNT#/GPIO /E0# /E# /E# /E# IRY# PR PIRST# EVSEL# PERR# PLOK# SERR# STOP# TRY# FRME# PLTRST# PILK PME# PIRQE#/GPIO PIRQF#/GPIO PIRQG#/GPIO PIRQH#/GPIO F PI_REQ0# G PI_GNT0# PI_REQ# PI_GNT# F PI_REQ# F PI_GNT# E GPIO F PI_GNT# PI_IRY# E R PI_EVSEL# E PI_PERR# PI_PLOK# J PI_SERR# PI_STOP# F PI_TRY# PI_FRME# PLTRST# LK_PI_IH R H PI_PIRQE# K GPIO F GPIO G IH_IRQH_GPIO T00 T T T T PLTRST# [,,,,,] LK_PI_IH [] T LK_PI_IH 0 *.P_N Reserved for EMI.Place resister and cap close to IH. R *0_N GPIO IOS should not enable the internal GPIO pull up resistor. QUNT OMPUTER IH-M (US,MI,PIE,PI) R.K Size ocument Number Rev ate: Saturday, June 0, 00 Sheet of

13 GRTIS - FOR FREE +.V_SUS RP Non-iMT IH_SMT IH_SMLK.KX Place these close to IH. Non-iMT +.V_SUS IH_SMLK IH_SMT +.V_RUN RP *0KX_N R.K LKRUN# R *0_N [] PIE_MR_ET# IH_SMLINK0 IH_SMLINK R 0 R 0 Option to " isable " clkrun. Pulling it down will keep the clks running. SF.0 IH_SMLINK0 IH_SMLINK PIE_MR_ET# [] IH_SMLK [] IH_SMT T0 T T [] PM_MUSY# [] US_MR_ET# [] H_STP_PI# [] H_STP_PU# [] LKRUN# [,,] PIE_WKE# [] IRQ_SERIRQ [] THERM_LERT# [,] +.V_SUS R R R0 R IMVP_PWRG T +.V_SUS T T T [] SIO_EXT_WKE# [] SIO_EXT_SMI# [] SIO_EXT_SI# T R T.K T T T T0 [] ST_LKREQ# T T T T T0 [] SPKR [] MH_IH_SYN# [] IH_RSV T T T0 0K 0K 0K K RSV_IH_L_RST# IH_RI# SIO_EXT_SI# PIE_WKE# IH_SMLK IH_SMT RSV_IH_L_RST# IH_SMLINK0 IH_SMLINK IH_RI# RSV_LPP# R K US_MR_ET# LKRUN# PIE_WKE# IRQ_SERIRQ THERM_LERT# IMVP_PWRG SIO_EXT_SMI# SIO_EXT_SI# SPKR MH_IH_SYN#_R TP TP0 TP Non-iMT U G SMLK SMT E LINKLERT#/GPIO0/LGPIO SMLINK0 SMLINK F R SUS_STT#/LPP# G SYS_RESET# M PMSYN#/GPIO0 SMLERT#/GPIO STP_PI#/GPIO E STP_PU#/GPIO L LKRUN#/GPIO E0 WKE# M SERIRQ J THRM# 0 RI# VRMPWRG TP G H TH/GPIO TH/GPIO G TH/GPIO GPIO LNPHYP/GPIO ENGET/GPIO E K TH0/GPIO GPIO F GPIO0 J SLOK/GPIO QRT_STTE0/GPIO QRT_STTE/GPIO L E STLKREQ#/GPIO SLO/GPIO G STOUT0/GPIO F STOUT/GPIO H GPIO GPIO/LGPIO M SPKR J MH_SYN# TP H0 TP J0 TP0 J TP IHM REV.0 SM ST GPIO locks SYS GPIO Power MGT MIS GPIO ontroller Link ST0GP/GPIO STGP/GPIO STGP/GPIO STGP/GPIO LK LK SUSLK SLP_S# SLP_S# SLP_S# S_STTE#/GPIO PWROK PRSLPVR/GPIO TLOW# PWRTN# LN_RST# RSMRST# K_PWRG LPWROK SLP_M# L_LK0 L_LK L_T0 L_T L_VREF0 L_VREF L_RST0# L_RST# MEM_LE/GPIO LERT#/GPIO0 NETETET/GPIO WOL_EN/GPIO H F E 0 H F P E G 0 G0 M R 0 R R F F F 0 +.V_RUN LK_IH_M LK_IH_M IH_SUSLK PWROK PRSLPVR IH_TLOW# RSV_IH_LN_RST# IH_RSMRST# IH_L_PWROK RSV_IH_L_LK RSV_IH_L_T L_VREF0 L_RST# R.K RSV_GPIO RSV_GPIO0 RSV_GPIO RSV_WOL_EN LK_IH_M [] LK_IH_M [] T SIO_SLP_S# [] T SIO_SLP_S# [] R.K PWROK [,] PRSLPVR [,] +.V_SUS SIO_PWRTN# [] IH_RSMRST# [] LK_PWRG [] IH_L_PWROK [,] L_LK0 [] T L_T0 [] T IH_L_RST0# [] T R0.K T T T T T +.V_SUS Non-iMT Non-iMT +.V_RUN LK_IH_M R *0_N 0 PWROK PRSLPVR R R 0K 00K IH_RSMRST# R 0K RSV_IH_LN_RST# R 0K IH_L_PWROK R0 M +.V_SUS RSV_GPIO0 R0 0K 0 *.P_N 0 LK_IH_M R *0_N *.P_N +.V_RUN +.V_RUN R0 *K_N SMbus address +.V_RUN Non-iMT L_VREF0 R.K/F R 00K PIE_MR_ET# SPKR SPKR No Reboot strap. Low = efault. High = No Reboot. These are for backdrive issue. RP.KX Q [] IH_SMT ST [,] T 0 0.U 0 R /F +.V_RUN +.V_SUS R R0 R R 0K R 0K R 00K *0K_N MH_IH_SYN#_R 0K IRQ_SERIRQ 0K THERM_LERT# RSV_WOL_EN SIO_EXT_SMI# US_MR_ET# [] IH_SMLK N00W--F +.V_RUN Q N00W--F SLK [,] L_VREF0/ ~=0.0V QUNT OMPUTER IH-M (PM,GPIO,SM,L) Size ocument Number Rev ate: Saturday, June 0, 00 Sheet of

14 +IH_VREF_SUS +.V_MIPLL +VL_0 +VL_ +VSTPLL +.V_MIPLL_R +IH_VREF_RUN +VSTPLL IH_GLNPLL TP_VSUSLN TP_VSUSLN +V_MI_IH +VSUSH TP_VSUS.0_ TP_VSUS.0_ TP_VSUS.0_ TP_VSUS._ TP_VSUS._ IH_GLNPLL IH_GLNPLL +V_H_IH +VSUSH +.V_RUN +V_RUN +V_SUS +.V_SUS +.V_RUN +.V_RUN +.V_RUN +.V_RUN +.V_RUN +.V_RUN +.V_RUN +.V_PIE_IH +.V_PIE_IH +.0V_VP +.V_RUN +.V_RUN +.V_RUN +.V_RUN +.0V_VP +.0V_VP +.0V_VP +.V_RUN +.V_RUN +.V_SUS +.V_SUS +RT_ELL +.V_RUN Size ocument Number Rev ate: Sheet of QUNT OMPUTER IH-M (POWER,GN) Wednesday, June 0, 00 Size ocument Number Rev ate: Sheet of QUNT OMPUTER IH-M (POWER,GN) Wednesday, June 0, 00 Size ocument Number Rev ate: Sheet of QUNT OMPUTER IH-M (POWER,GN) Wednesday, June 0, 00 0uH+-0%_00m F_0ohm+-%_00mHz_._0.0 ohm uh+-0%_00m Non-iMT Non-iMT Non-iMT WWN Noise - IH improvements m m m m V TOTL. m m m 0m m V_ 0m m m m VSUS _ m m m m Remove R 0ohm resistor Ray / Remove R 0ohm resistor Ray / Remove R 0ohm resistor Ray / 00 0.U U 0 *.U_N. 0 *.U_N. 0 *0.U_N *0.U_N + 0U + 0U L uh/00m_ L uh/00m_ *0.U_N 0 *0.U_N 0 T T 0U. 0 0U U U 0 T T 0 0.U/0V 0 0.U/0V L LMPGSN 0 L LMPGSN 0 0 U U 0 0 L0 0uH 0 L0 0uH 0 R 0 R 0 0.U/0V 0.U/0V RV-0 RV-0 *0.U_N 0 *0.U_N 0 T T 0.U 0 0.U 0.U 0 0.U 0 0.U. 0.U. 0 0.U 0 0.U 0 U 0 0 U 0 0 RV-0 RV-0 T T 0.U 0 0.U 0.U 0 0.U 0 0 0U. 0 0U. 0 L uh L uh *0.U_N 0 *0.U_N 0 U 0 0 U U 0 0.U 0 0.U 0 0.U 0 0.U 0 0.U 0 ORE VGP TX RX US ORE PI GLN POWER VP_ORE VPSUS VPUS UF IHM REV.0 ORE VGP TX RX US ORE PI GLN POWER VP_ORE VPSUS VPUS UF IHM REV.0 VREF VREF_SUS E V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] E V [0] E V [] E V [] E V [] E V [] F V [] G V [] H V [] H V [] J V [] J V [0] K V [] K V [] L V [] L V [] L V [] M V [] M V [] N V [] N V [] N V [0] P V [] P V [] R V [] R V [] R V [] R V [] T V [] T V [] T V [] T V [0] U V_[0] G VMIPLL R V [0] V [0] V [0] V [0] E V [0] F VSTPLL J V_[0] J V [0] G V [0] H V [0] J V [0] V [0] VUSPLL J VLN_0[] 0 VLN_0[] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] E V_0[0] F V_0[0] L V_0[0] L V_0[0] L V_0[0] L V_0[] L V_0[] L V_0[] M V_0[] M V_0[] P V_0[] P V_0[] T V_0[] T V_0[] U V_0[0] U VLN_[] VLN_[] VH J VSUSH J V_PU_IO[] V_PU_IO[] V_[0] 0 V_[0] V_[0] F V_[0] G V_[] G V_[] J V_[] J VRT VSUS_[0] VSUS_[0] VSUS_[0] E VSUS_[0] F VSUS_[0] T VSUS_[0] T VSUS_[0] T VSUS_[0] T VSUS_[0] T VSUS_[] T VSUS_[] U VSUS_[] U VSUS_[] V VSUS_[] V VSUS_[] W VSUS_[] W VSUS_[] Y V [] E V [] F V [] G0 V [] G V [] H0 V [] J0 VSUS_0[] VSUS_0[] F V [0] V [] G0 V [] G V [] V [] VSUS_[0] V_[] K V [] V_0[] V V_0[] V V_0[] V V_0[] V V_0[] V V_0[] V VGLN_[] E VGLN_[] VGLN_[] E VGLN_[] VGLN_ VGLNPLL V_[0] 0 V_[0] V_[0] G V_[0] F0 VSUS_[] Y V [] VSUS_[] V [] V [] VSUS_[] F V_MI[] Y V_MI[] W VL_0 G VL_[] VL_[] VL_ G V [] W V [] V V [] U V [] W V [] U V [] V V [] K V [] Y V [] Y V [] V [] V [] V [] V [0] VSUS_[0] T 0 0.U U 0 0.U 0.U R 0 0 R 0 0 R 0 R 0 0.0U 0.0U 0.U 0 0.U 0 0U. 0 0U. 0 R0 R0 0.U 0 0.U 0 0U. 0 0U. 0 *0.U_N *0.U_N 0.U 0 0.U 0 *0.U_N *0.U_N.U. 0.U. 0 0.U 0 0.U 0 0.U 0 0.U 0 *0.U_N *0.U_N *0.U_N 0 *0.U_N 0 0 *U_N *U_N 0 0 UE IHM REV.0 UE IHM REV.0 VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] 0 VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E0 VSS[0] E VSS[0] E VSS[0] E VSS[00] E VSS[0] E VSS[0] F VSS[0] F VSS[0] F VSS[0] F VSS[0] H VSS[0] F VSS[0] F VSS[0] F VSS[00] F VSS[0] F VSS[0] G VSS[0] G VSS[0] G VSS[0] G0 VSS[0] G VSS[0] G VSS[0] G VSS[0] G VSS[00] H VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[00] J VSS[0] J VSS[0] J VSS[0] J VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] 0 VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[00] E VSS[0] E VSS[0] F VSS[0] F VSS[0] F VSS[0] G VSS[0] G VSS[0] G VSS[0] G VSS[00] G VSS[0] G VSS[0] G VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[0] J VSS[0] J VSS[0] J VSS[] VSS[] K VSS[] K VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[0] L VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[0] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[0] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[0] P VSS[] P VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[0] R VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] VSS[] U VSS[0] U VSS[] U VSS[] U VSS[] U VSS[] U VSS[] VSS[] U VSS[] U VSS[] U VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] H VSS_NTF[0] H VSS_NTF[0] J VSS_NTF[0] J VSS_NTF[0] J VSS_NTF[0] J VSS_NTF[] VSS_NTF[] VSS[] V VSS[0] V VSS[] V VSS[] V VSS[] V VSS[0] G VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] W VSS[0] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] G VSS[] H VSS[] F VSS[] L LMPGSN 0 L LMPGSN 0 T0 T0 0.U 0 0.U 0 *0.U_N 0 *0.U_N 0 0.U 0 0.U 0 0U 0 0 0U U 0 0.U 0 T T/R T T/R 0.U 0 0.U 0

15 R QS R M R M R M R QS R QS R M R QS# M_OT0 R M R QS# R M R M R M_OT R QS# R QS#0 R R M0 R S0 R QS# R R M R QS R WE# R M R M0 R M R M R QS R RS# R M R QS# R R M R S R M R S R QS0 R R R QS# R R 0 R QS R QS R M R R R S# R M0 R 0 R QS# R M R M R R M R M ST SLK PM_EXTTS#0 R R R R R R R R R R R R R R R R R R R 0 R R R 0 R R R R R R R R R R R R 0 R R R 0 R R R R R R R R R R R R R R 0 R R R R 0 SLK ST R R PM_EXTTS# R R R R 0 R R R R R R R R R R R R R R R R R R R R 0 R R R R R M R QS R M R QS# R M R QS R R M R M0 R M R M R M R R QS R M0 R QS# R M R S0 R M R WE# R M0 R S# R M R R QS# R R M R M R M R QS# R M R R R R QS0 R R QS R R R R R QS R QS#0 R R R R R QS# M_OT M_OT R QS# R S R R QS# R QS R RS# R R R R M R R 0 R QS R R M R R R R 0 R R M R M R M R S R 0 R R 0 R_S_IMM# [,] R_S0_IMM# [,] R QS#[0..] [] R [0..] [] R M[0..] [,] R S [,] R M[0..] [] M_OT [,] M_LK_R0 [] R RS# [,] R QS[0..] [] R_KE_IMM [,] R S [,] M_LK_R# [] M_LK_R [] PM_EXTTS#0 [] R S# [,] R S0 [,] R WE# [,] R_KE0_IMM [,] M_OT0 [,] M_LK_R#0 [] R M [,] R QS#[0..] [] R QS[0..] [] R M[0..] [] R M[0..] [,] R [0..] [] R_S_IMM# [,] R_KE_IMM [,] R RS# [,] R S [,] R_S_IMM# [,] R S [,] R S0 [,] R WE# [,] R S# [,] M_OT [,] M_OT [,] R_KE_IMM [,] M_LK_R [] M_LK_R# [] M_LK_R# [] M_LK_R [] R M [,] PM_EXTTS# [] ST [,] SLK [,] V_R_MH_REF +.V_RUN +.V_SUS V_R_MH_REF +.V_SUS +.V_RUN +.V_SUS +.V_SUS +.V_RUN V_R_MH_REF V_R_MH_REF +.V_SUS +.V_SUS +.V_RUN +.V_SUS +.V_SUS +.V_RUN Size ocument Number Rev ate: Sheet of QUNT OMPUTER R SO-IMM (00P) X Saturday, June 0, 00 Size ocument Number Rev ate: Sheet of QUNT OMPUTER R SO-IMM (00P) X Saturday, June 0, 00 Size ocument Number Rev ate: Sheet of QUNT OMPUTER R SO-IMM (00P) X Saturday, June 0, 00 LOK 0, SMbus address 0 KE 0, is required to route to Top SoIMM for MTto function. h. SOIMM needs to be populated for Intel MT support. Non-iMT Non-iMT Non-iMT Non-iMT Place these aps near So-imm. Place these aps near So-imm. Non-iMT LOK, SMbus address KE, Place these aps near So-imm. Place these aps near So-imm. R 0K R 0K 0 0.U U U U 0 R 0K R 0K *0.U_N *0.U_N 0.U 0 0.U 0 0.U 0 0.U 0 P00 R SRM SO-IMM (00P) N R_SOIMM P00 R SRM SO-IMM (00P) N R_SOIMM VREF VSS Q0 Q VSS QS#0 QS0 VSS Q Q VSS Q Q VSS QS# QS VSS Q0 Q VSS0 VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS M N VSS Q Q VSS KE0 V N _ V V 0 V0 0 0/P WE# 0 V S# S# V OT VSS Q Q VSS QS# QS VSS Q Q VSS Q0 Q VSS Q Q VSS M0 0 VSS Q Q VSS Q 0 Q VSS M VSS K0 0 K0# VSS Q Q VSS 0 VSS0 Q0 Q VSS N 0 M VSS Q Q VSS 0 Q Q VSS QS# QS 0 VSS0 Q0 Q VSS KE 0 V V 0 V V 0 0 RS# 0 S0# 0 V OT0 V N 0 VSS Q Q VSS M 0 VSS Q Q VSS Q 0 Q VSS VSS M VSS Q Q VSS0 Q Q VSS NTEST VSS0 QS# QS VSS Q0 Q Q Q VSS M VSS Q Q VSS S SL V(SP) QS# QS VSS 0 Q Q VSS Q Q 0 VSS K K# VSS M 0 VSS Q Q VSS Q0 0 Q VSS QS# QS VSS 0 Q Q VSS S0 S 00 VSS 0.U 0 0.U 0 0 *0.U_N 0 *0.U_N.U 0 0.U 0 0.U 0 0.U 0 0 R 0K R 0K 0.U U 0 0.U 0 0.U U 0 0.U 0 P00 R SRM SO-IMM (00P) N -0- P00 R SRM SO-IMM (00P) N -0- VREF VSS Q0 Q VSS QS#0 QS0 VSS Q Q VSS Q Q VSS QS# QS VSS Q0 Q VSS0 VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS M N VSS Q Q VSS KE0 V N _ V V 0 V0 0 0/P WE# 0 V S# S# V OT VSS Q Q VSS QS# QS VSS Q Q VSS Q0 Q VSS Q Q VSS M0 0 VSS Q Q VSS Q 0 Q VSS M VSS K0 0 K0# VSS Q Q VSS 0 VSS0 Q0 Q VSS N 0 M VSS Q Q VSS 0 Q Q VSS QS# QS 0 VSS0 Q0 Q VSS KE 0 V V 0 V V 0 0 RS# 0 S0# 0 V OT0 V N 0 VSS Q Q VSS M 0 VSS Q Q VSS Q 0 Q VSS VSS M VSS Q Q VSS0 Q Q VSS NTEST VSS0 QS# QS VSS Q0 Q Q Q VSS M VSS Q Q VSS S SL V(SP) QS# QS VSS 0 Q Q VSS Q Q 0 VSS K K# VSS M 0 VSS Q Q VSS Q0 0 Q VSS QS# QS VSS 0 Q Q VSS S0 S 00 VSS 0.U U 0 0.U 0 0.U 0 0.U 0 0.U *0U_N + *0U_N 0.U U 0 0.U 0 0.U 0 0 *0.U_N *0.U_N R0 0K R0 0K.U 0 0.U 0 0.U 0 0.U 0 0.U 0 0.U U 0 0.U 0 *0.U_N *0.U_N.U 0 0.U 0 0.U 0 0.U 0 0 *0.U_N *0.U_N hexainf@hotmail.com GRTIS - FOR FREE

16 +0.V_R_VTT Layout note: Place cap close to every R-pack terminated to SMR_VTERM. 0.U 0 0.U 0 0.U 0 +0.V_R_VTT 0.U 0 0.U U 0 0.U U 0 0.U 0 0.U 0 0.U 0 0.U U 0 0.U 0 0.U 0 0.U 0 0.U 0 0.U 0 0.U 0 0.U 0 0.U 0 0.U 0 0.U U 0 0.U 0 0.U 0 0.U 0 0.U 0 [,] R M[0..] +0.V_R_VTT R M[0..] [,] R M R M RP RP R M R M R M R M x RP x RP R M R M [,] R RS# [,] R S [,] M_OT0 R RS# R S R M M_OT0 x RP x RP x RP x RP R RS# R S M_OT R M R RS# [,] R S [,] M_OT [,] [,] R S R S R M x RP x RP R M R M Please these resistor closely IMM,all trace length<0 mil. R M R M R M R M x RP x RP x RP0 x RP R M R M R M R M Please these resistor closely IMM,all trace length<0 mil. [,] R S0 R S0 R M0 x RP x RP R WE# R S0 R WE# [,] R S0 [,] [,] [,] R S# R WE# R S# R WE# x RP x RP R S# R M0 R S# [,] R M0 R M x RP0 x RP R M0 R M [,] M_OT [,] R_S0_IMM# [,] R_S_IMM# [,] R_KE0_IMM [,] R_KE_IMM [,] R M R M x R R R R R R R x R R R0 R R R R M_OT [,] R S [,] R_S_IMM# [,] R_S_IMM# [,] R_KE_IMM [,] R_KE_IMM [,] R M [,] R RES RRY QUNT OMPUTER Size ocument Number Rev ate: Wednesday, June 0, 00 Sheet of

17 GRTIS - FOR FREE dd capacitor pads for improving WWN. 0P 0 LK_XTL_IN P 0 [] ST_LKREQ# [] LK_GPLLREQ# [] LK_LP_EUG [] LK_PI_ [] LK_PI_IH [] LK_IH_M [,] PU_MH_SEL0 [,] PU_MH_SEL [,] PU_MH_SEL [] LK_IH_M [] LK_PWRG.MHz LK_LP_EUG EMI / FS *P_N 0 FS 0 *P_N 0 PI_SIO *P_N 0 0 P 0.MHZ PI_IH Y LK_XTL_OUT ST_LKREQ# LK_GPLLREQ# LK_LP_EUG LK_PI_ LK_PI_IH LK_IH_M LK_IH_M P 0 R /F R /F R R R R R.K R 0K R [,,] SMT [,,] SMLK +K_V_PI +K_V_PLL +K_V_ +K_V_SR +K_V_MIN FS FS FS LK_XTL_OUT LK_XTL_IN U V_PI V_REF V_PLL V_ V_SR V_PU V_IO V_IO V_IO V_IO V_IO V_IO GN GN GN GN 0 GN GN GN GN GN R#_/PI-0 0 R_/PI- PI_SIO TME/PI- M_SEL SR_EN/PI- PI_IH M_SEL/PI- ITP_EN/PIF-# Remove R0 0ohm Ray / FS/US FS/TEST_MOE FS/TEST_SEL/REF RESET# K_PWRG/P# XOUT XIN ST SLK SLGSPV K0 QFN PU-0 0 PU-0# PU- PU-# SR-/PU_ITP SR-#/PU_ITP# 0 SR-0/OT SR-0#/OT# SR-/SE SR-#/SE SR-/ST SR-#/ST# R#_/SR- R#_/SR-# SR- SR-# PI_STOP#/SR- PU_STOP#/SR-# SR- SR-# R#_F/SR- 0 R#_E/SR-# SR- SR-# SR-0 SR-0# 0 R#_H/SR- R#_G/SR-# GN RP 0x RP 0x RP 0x R0 /F R /F RP 0x RP 0x RP 0x RP0 0x RP0 0x RP 0x RP 0x RP 0x MINILK_REQ# LK_PU_LK [] LK_PU_LK# [] LK_MH_LK [] LK_MH_LK# [] LK_PIE_MINI [] LK_PIE_MINI# [] MH_REFLK [] MH_REFLK# [] REF_SSLK [] REF_SSLK# [] LK_PIE_ST [] LK_PIE_ST# [] LK_PIE_R [] LK_PIE_R# [] LK_MH_GPLL [] LK_MH_GPLL# [] H_STP_PI# [] H_STP_PU# [] LK_PIE_EXPR [] LK_PIE_EXPR# [] MINILK_REQ# [] R_LK_REQ# [] LK_PIE_IH [] LK_PIE_IH# [] LK_PIE_LOM [] LK_PIE_LOM# [] LK_GPLLREQ# ST_LKREQ# R R +.V_RUN 0K 0K +.V_RUN MINILK_REQ# R0 0K +.V_RUN +.V_RUN L LMPG00SN 0 0 ohms@00mhz L LMPG00SN 0 0 ohms@00mhz 0.U 0 0.U 0 R. R. +K_V_MIN 0 0.U 0 +K_V_PI +K_V_PLL 0.U 0 0.U 0 UM without imt 0.U 0 0.U 0 *0U_N 0. H_STP_PI# H_STP_PU# R R 0K 0K PI_IH R *0K_N R 0K PI_SIO FS FS FS PU SR PI R0 *0K_N RSV R0. +K_V_ 0.U 0 M_SEL M_SEL (PIN) 0=UM PIN0 PIN PIN PIN OTT OT / 00M_T / 00M_ 0 0.U 0.U 0. M_SEL = isc. GRFX down SRT0 SR0 Mout MSSout R. +K_V_SR 0 0.U 0 R 0K QUNT OMPUTER LOK GENERTOR Size ocument Number Rev ate: Saturday, June 0, 00 Sheet of

18 Support the new imbeded diagnostics. [] ENV [] LV_TST_EN EN_LV T T/R R 0K +.V_SUS +V_LW +.V_RUN Q FN R 0K R K Q N00W--F LV_ON R *00K_N Q N00W--F 0 0.0U R 0 amera Q N00W--F U 0 0 +LV 0.0U J L_0- L_0+ L_LK- L_LK+ L_- L_+ L_- L_+ USP_+ USP_- KLITEON P 0 L_LK- [] L_LK+ [] L_- [] L_+ [] L_- [] L_+ [] L_0- [] L_0+ [] L_LK [] L_T [] For amera +V_RUN MI_LK [] MI_T [] +.V_RUN +LV L_TST [] P 0 SMLK [,,] SMT [,,] L_K# [] PWM_VJ [] L_L_ET# [] +PWR_SR +LV +PWR_SR Stephen / 0.U 0 0.U 0 0.0U 0 0.U 0 +.V_RUN +V_RUN 0.U 0 0.U 0 dress : H --ontrast H --acklight [] IH_USP+ [] IH_USP- R 0 R 0 stephen /0 USP_+ USP_- +PWR_SR 0mil 0mil +PWR_SR +.V_RUN Remove R 0ohm Ray / [] I_PWM R *0K_N KLITEON For PST support *P_N *P_N 0 *P_N *P_N *P_N 0 *P_N *P_N *P_N L_LK- L_LK+ L_- L_+ L_- L_+ L_0- L_0+ close to J for EMI solution QUNT OMPUTER L ONN & K-SS Size ocument Number Rev ate: Saturday, June 0, 00 Sheet of

19 GRTIS - FOR FREE E +.V_RUN +V_RUN SM0K--F [] VG_RE Layout Note: Setting R,G, treac impedance to 0 ohm. *0U_N *0U_N RE +V_RT_REF [] VG_GRN L LM0SN GREEN JVG 0 00FR0SJZR M_SEN#_R T [] VG_LU L LM0SN LUE 0 R R R0 0 0/F 0/F 0/F *P_N *P_N *P_N *0P_N *0P_N *0P_N Stephen /0 T M_I# V_RUN RT_V [] [] G_T_ [] G_LK_ +.V_RUN Q SS_NL G_T G_LK HTGGW Q SS_NL 0.U Place near *0P_N *0P_N U0,U < mil L LM0S HSYN JVG_HS 0 0 U R 0 L LM0S VGVSYN_R VSYN JVG_VS [] VGVSYN 0 HTGGW *0P_N 0P 0 L0 0 LM0SN *0U_N U 0.0U RP.KX +V_RUN RT_V SM0K--F VGHSYN R K VGHSYN_R R 0 RP.KX *0P_N 0 0 0P 0 Place near JVG connector < 00 mil RT&TV ONN QUNT OMPUTER Size ocument Number Rev ate: Wednesday, June 0, 00 Sheet of E

20 E QUNT OMPUTER ard Reader-RTSE Size ocument Number Rev Wednesday, June 0, 00 ate: Sheet of 0 E

21 GRTIS - FOR FREE E +.V_R Max. 0m, verage 00m. +V_R Max. 00m, verage 000m. +.V_R 0 *0.U_N Place the cap near connector. stephen / 0 0.U 0 Place the cap near connector. 0 *0.U_N [] [,,,,,] EXP_SW_SHN# PLTRST# Remove R 0ohm Ray / T R_RESET# EXPRR_PWREN# PUS# RLKEN R R +.V_RUN *00K_N *00K_N +.V_SUS +.V_RUN R_LK_REQ# [] R_LK_REQ#_R +.V_R +.V_RUN +.V_RUN +.V_SUS +.V_RUX +.V_R +.V_R [] IH_SMT RP0.KX Q0 R_ST 0 0.U 0 Please the cap near pin & (.VIN). 0 Please the cap near pin & (.VIN). 0 Please the cap near pin (UXIN). 0 0.U 0 Please the cap near pin (UXOUT). 0.U 0 Please the cap near pin & (.VOUT). Please the cap near pin & (.VOUT). 0 *0.U_N R 0 0 0U/.V/00 0 UXIN.VIN_0.VIN_.VIN_0.VIN_ UXOUT.VOUT_0.VOUT_.VOUT_0.VOUT_ ExpressSwitch SHN# STY# SYSRST# N GN0 PERST# PPE# PUS# O# OZ0LN 0 RLKEN R0 00K R 00K N00W--F Q0 N00W--F +.V_RUN 0 0.U 0 0.U 0.U 0 R 0 +.V_R [] IH_USP- USP_- [] IH_USP+ USP_+ +.V_RUN +.V_RUN +.V_SUS +.V_RUX +.V_R +.V_R U Q0 N R_SLK [] IH_SMLK USP_- GN_ USP_+ US- Express ard N00W--F PUS# US+ PUS# RSV_0 R_SLK RSV_ R_ST SMLK SMT +.V_0 +.V_R 0 +.V_ [,,] PIE_WKE# WKE# +.V_RUX R_RESET# +.VUX PERST# +.V_R +.V_ 0.U R_LK_REQ#_R +.V_ EXPRR_PWREN# LKREQ# 0 0.U PPE# 0.U [] LK_PIE_EXPR# REFLK- 0 [] LK_PIE_EXPR REFLK+ 0 0 GN_ [] PIE_RX- PERn0 [] PIE_RX+ PERp0 GN_ [] PIE_TX- PETn0 [] PIE_TX+ PETp0 GN_ Express ard cage -00 N N JE PX0FSPH-P Express ard QUNT OMPUTER Size ocument Number Rev Saturday, June 0, 00 ate: Sheet of E