Intel PENRYN ufcpga SB ICH9M

Transcription

1 V_RE P/ lock iagram +.V +.V +.V +.VSUS +.V +VPU +V_S +VSUS +V +VPU +V_S +V +SMR_VTERM +SMR_VREF INT MI Page RT Page L PNEL Page ST - H Page ST - Page est Page ST ST ST RT LVS Intel PENRYN ufpg N NTIG MI(x/x) Page, FS(/MHZ) Page,,,,, PI-E Lan / MHZ R II PI-Express LK GENERTR K ISLPR Page VG NNETR RII-SIMM RII-SIMM Page, Page MINI R- RSN (FT) Page PIE- RT HMI L/LE PIE- PIE- PIE- PIE- WLN Page US- US. S IHM MINI R- WLN Page MINI R- UM TV/RSN Page NEW R Page LN RTL Page amera Page luetooth Page New ard Page M/ US Page M/ US Page TV/RSN Page US- US- US- US- US- US- zalia Page,,, LP ITE PI us.khz Page Z Page IN Page Page VG oard US oard HP Page MI JK Page Port- Port- UI E L/L Page FN Page T/P oard Page Key FLSH IR oard RM Page Page Page Touch Pad oard Function oard aughter oard INT SPK Page SPK MP Page PRJET : P/ Quanta omputer Inc. Size ocument Number Rev lock iagram Friday, March, ate: Sheet of

2 lock Generator VP_V PYT-Y-N_ L VP V L PYT-Y-N_.u/V_ u/v_.u/v_ u/v_ *u/v_ u/v_.u/v_.u/v_.u/v_.u/v_.u/v_.u/v_.u/v_.u/v_.u/v_.u/v_ V_K_V_PI V_K_V_ V_K_V_PI V_K_V_REF V_K_V_PI V_K_V_PU VP_V U V_PI V_ V_PLL V_REF V_SR V_PU V I V_PLL_I V_SR_I_ V_SR_I_ V_SR_I_ V_PU_I K I_VUT SLK S SR/PI_STP# SR#/PU_STP# PU PU# PU PU# SR/ITP SR#/ITP# GLK_SM GT_SM PM_STPPI# PM_STPPU# LK_PU_LK_R LK_PU_LK#_R LK_MH_LK_R LK_MH_LK#_R LK_PIE_MINI_R LK_PIE_MINI#_R RP RP RP IV@ PM_STPPI# PM_STPPU# LK_PU_LK LK_PU_LK# LK_MH_LK LK_MH_LK# LK_PIE_MINI LK_PIE_MINI# To S To PU To N To RSN M ption Table Reference IV@ EV@ escription INT VG ET VG PLK_EUG T PLK_Z PLK_EUG PLK_Z R R _ R _ PLK_EUG_R PLK_PM_R PLK_Z_R PI/R#_ PI/R#_ PI/TME SR# SR SR/R#_H SR#/R#_G LK_PIE_GPLL#_R LK_PIE_GPLL_R LK_MH_E#_R NEW_LKREQ#_R RP R R /F_ /F_ LK_PIE_GPLL# LK_PIE_GPLL LK_MH_E# NEW_LKREQ# To N p/v_ L=p p/v_ G_IN Y.MHZ G_UT PLK_E PLK_IH LKUS_ M_IH LK_SEL LK_SEL PLK_E PLK_IH R _ LK_SEL R.K_ R K_ R _ R K_ R _ R _ PI_LK_SI_R PLK_E_R PLK_IH_R G_IN G_UT FS FS FS PI PI/SR_EN PIF/ITP_EN TL_IN TL_UT US_/FS FS/TEST/ME REF/FS/TESTSEL VSS_PI VSS_ VSS_I VSS_PLL VSS_PU VSS_SR VSS_SR VSS_SR VSS_REF SR SR# SR/R#_F SR#/R#_E SR SR# SR SR# SR/R#_ SR#/R#_ SR/ST SR#/ST# SR/SE SR#/SE SR/T SR#/T# KPWRG/PWRWN# LK_PIE_NEW_R LK_PIE_NEW_R# LK_PIE_MINI_R LK_PIE_MINI#_R LK_PIE_MINI_R LK_PIE_MINI#_R LK_PIE_LN_R LK_PIE_LN#_R LK_PIE_IH_R LK_PIE_IH#_R LK_PIE_ST_R LK_PIE_ST#_R REFSSLK_R REFSSLK#_R REFLK_R REFLK#_R RP RP RP RP RP RP RP LK_PIE_NEW LK_PIE_NEW# LK_PIE_MINI LK_PIE_MINI# LK_PIE_MINI LK_PIE_MINI# LK_PIE_LN LK_PIE_LN# LK_PIE_IH LK_PIE_IH# LK_PIE_ST LK_PIE_ST# REFLK REFLK# K_PWRG To New ard To TV To WLN To LN To S To S To N PM_STPPI# R PM_STPPU# R NEW_LKREQ#_R R.K_.K_ K_ V ISLPRSGLFT Pin ISLPRS RTMT- (LPRSK) (LK) PI/TME PI/TME internal P PULL HIGH N VERLKING (default) PULL WN NRML RUN V R R K_ *K_ PLK_Z <MIN>:ISLPRSGLFT QI:LPRSK <SEN>:SLGSPTTR: QI:LSPK Pin Pin Pin PI-/SR_EN PI- internal P PI-/M_SEL PI-/M_SEL internal P PIF-/ITP_EN PIF-/ITP_EN internal P PIN/ IS SR PIN / IS MHz PIN / IS PUITP PIN/ IS PI_STP/PU_STP PIN / IS SR/T PIN / IS SR (default) (default) (default) V V R R R *K_ K_ *K_ PLK_E HIGH MHz LW SR PLK_IH REFSSLK_R REFSSLK#_R RP RP IV@ EV@ REFSSLK REFSSLK# LK_MM LK_MM# To N To VG ard R K_ FREQ. SEL TLE lock Gen I V Q R PU_SEL R _ LK_SEL MH_SEL RHUN K_ SEL Frequency Select Table VP R R *_ K_, ST V GT_SM GT_SM PLK_Z PLK_E p p FS FS FS Frequency LKUS_ p Mhz Mhz Mhz Mhz VP PU_SEL R _ R R *_ K_ LK_SEL MH_SEL, SLK Q RHUN R K_ GLK_SM GLK_SM M_IH PLK_IH PLK_EUG p p p Mhz Mhz VP PU_SEL R _ R R *_ K_ LK_SEL MH_SEL PRJET : P/ Quanta omputer Inc. Mhz Size ocument Number Rev LK GEN Friday, May, ate: Sheet of

3 H_#[..] H_ST# H_REQ#[..] H_#[..] H_ST# H_M# H_FERR# H_IGNNE# H_STPLK# H_INTR H_NMI H_SMI# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_ST# H_REQ# H_REQ# H_REQ# H_REQ# H_REQ# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_ST# H_M# H_FERR# H_IGNNE# R _ H_INTR H_NMI H_SMI# T T T T T T T T T J L L K M N J N P P L P P R M K H K J L Y U R W U Y U R T T W W Y U V W V M N T V F U []# []# []# []# []# []# []# []# []# []# []# []# []# []# ST[]# REQ[]# REQ[]# REQ[]# REQ[]# REQ[]# []# []# []# []# []# []# []# []# []# []# []# []# []# []# []# []# []# []# []# ST[]# M# FERR# IGNNE# STPLK# LINT LINT SMI# RSV[] RSV[] RSV[] RSV[] RSV[] RSV[] RSV[] RSV[] RSV[] R GRUP_ R GRUP_ IH RESERVE P/ITP SIGNLS NTRL S# NR# PRI# EFER# RY# SY# R# IERR# INIT# LK# RESET# RS[]# RS[]# RS[]# TRY# HIT# HITM# PM[]# PM[]# PM[]# PM[]# PRY# PREQ# TK TI T TMS TRST# R# THERML PRHT# THERM THERM THERMTRIP# H LK LK[] LK[] H E G H F E F H F F G G G E H_S# H_NR# H_PRI# H_EFER# H_RY# H_SY# H_REQ# H_IERR# H_INIT# H_LK# H_PURST# H_RS# H_RS# H_RS# H_TRY# H_HIT# H_HITM# P_PM# P_PM# P_PM# P_PM# P_PM# P_PM# P_TK P_TI P_T P_TMS P_TRST# P_RESET# H_PRHT#_ H_THERM H_THERM PU_PM_THRMTRIP# LK_PU_LK LK_PU_LK# H_S# H_NR# H_PRI# H_EFER# H_RY# H_SY# ZS efault no use this function H_REQ# R _ VP H_INIT# H_LK# H_PURST# H_RS# H_RS# H_RS# H_TRY# H_HIT# H_HITM# T T T T onnect it to PU R# is for ITP debug port T or PU interposer (like IE) to reset the system T R _ SYS_RST# LK_PU_LK LK_PU_LK# SYS_RST# VP Layout note: H_GTLREF: Zo= ohm,l<." /*VP+-% R K/F_ R K/F_ H_#[..] H_STN# H_STP# H_INV# H_#[..] H_STN# H_STP# H_INV# PU_SEL PU_SEL PU_SEL T T T T T T T H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_STN# H_STP# H_INV# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_STN# H_STP# H_INV# H_GTLREF PU_TEST PU_TEST PU_TEST PU_TEST PU_TEST PU_TEST PU_TEST PU_SEL PU_SEL PU_SEL E F E G F G E E K G J J H F K H J H H N K P R L M L M P P P T R L T N L M N F F U []# []# []# []# []# []# []# []# []# []# []# []# []# []# []# []# STN[]# STP[]# INV[]# []# []# []# []# []# []# []# []# []# []# []# []# []# []# []# []# STN[]# STP[]# INV[]# GTLREF TEST TEST TEST TEST TEST TEST TEST SEL[] SEL[] SEL[] Penryn_p T GRP T GRP MIS T GRP T GRP []# []# []# []# []# []# []# []# []# []# []# []# []# []# []# []# STN[]# STP[]# INV[]# []# []# []# []# []# []# []# []# []# []# []# []# []# []# []# []# STN[]# STP[]# INV[]# MP[] MP[] MP[] MP[] PRSTP# PSLP# PWR# PWRG SLP# PSI# Y V V V T U U Y W Y W W Y U E E F E F E F R U Y E E H_#[..] H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_STN# H_STN# H_STP# H_STP# H_INV# H_INV# H_#[..] H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_STN# H_STN# H_STP# H_STP# H_INV# H_INV# MP R./F_ MP R./F_ MP R./F_ MP R./F_ IH_PRSTP# IH_PRSTP#,, H_PSLP# H_PSLP# H_PWR# H_PWR# H_PWRG H_PUSLP# H_PUSLP# PSI# PSI# Layout note: IH_PRSTP#, aisy hain (S>PowerI>N>PU) M ption Table Reference escription N/ N/ Layout note: comp,: Zo=.ohm, L<." comp,: Zo=ohm, L<." H_PWRG Penryn_p Thermal Trip VP VP P PU Thermal monitor VP V V V,, ELY_VR_PWRG VP PU_PM_THRMTRIP# R./F_ Q R FVN *K_ *S *u/v_ Q MMT SYS_SHN# SYS_SHN# R *_ PM_THRMTRIP# PM_THRMTRIP#, R */F_ H_PURST# Reserve K for P function VP P_T R */F_ P_TI R _ P_TMS R./F_ P_TK R _ P_TRST# R _,, MLK,, MT Q RHUN Q NS LM PU this pin V R *K_ R K_ N_MLK# N_MT# RHUN R K_ R _ LMV U ST VT SLK LERT V P N G RESS: H.u/V_ H_THERM p/v_ H_THERM No use Thermal trip PU side still PU ohm. Use Thermal trip can share PU at S side, THERM_LERT# V R _ R K_ THERM_LERT#_R Processor hot V R _ SYS_SHN# THER_SH# VP Q MMT R _ No use PRHT PU side still PU ohm. Use PRHT to optional receiver PU side PU ohm and through isolat.k ohm to receiver side H_PRHT#_ R *_ H_PRHT# PRJET : P/ Quanta omputer Inc. Size ocument Number Rev PU(/) HST US Friday, May, ate: Sheet of

4 M ption Table Reference N/ escription N/ Need N PS u before M released( all stuff) U VSS[] VSS[] P VSS[] VSS[] P VSS[] VSS[] P VSS[] VSS[] R VSS[] VSS[] R VSS[] VSS[] R VSS[] VSS[] R F VSS[] VSS[] T VSS[] VSS[] T VSS[] VSS[] T VSS[] VSS[] T VSS[] VSS[] U VSS[] VSS[] U VSS[] VSS[] U VSS[] VSS[] U VSS[] VSS[] V VSS[] VSS[] V VSS[] VSS[] V VSS[] VSS[] V VSS[] VSS[] W VSS[] VSS[] W VSS[] VSS[] W VSS[] VSS[] W VSS[] VSS[] Y VSS[] VSS[] Y VSS[] VSS[] Y VSS[] VSS[] Y VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] E VSS[] VSS[] E VSS[] VSS[] E VSS[] VSS[] E VSS[] VSS[] E VSS[] VSS[] E VSS[] VSS[] E VSS[] VSS[] E VSS[] VSS[] E VSS[] VSS[] F VSS[] VSS[] F VSS[] VSS[] F VSS[] VSS[] F VSS[] VSS[] F VSS[] VSS[] F VSS[] VSS[] F VSS[] VSS[] F VSS[] VSS[] F VSS[] VSS[] G VSS[] VSS[] G VSS[] VSS[] G VSS[] VSS[] G VSS[] VSS[] H VSS[] VSS[] H VSS[] VSS[] H VSS[] VSS[] H VSS[] VSS[] J VSS[] VSS[] J VSS[] VSS[] J VSS[] VSS[] J VSS[] VSS[] E K VSS[] VSS[] E K VSS[] VSS[] E K VSS[] VSS[] E K VSS[] VSS[] E L VSS[] VSS[] E L VSS[] VSS[] E L VSS[] VSS[] E L VSS[] VSS[] E M VSS[] VSS[] M VSS[] VSS[] F M VSS[] VSS[] F M VSS[] VSS[] F N VSS[] VSS[] F N VSS[] VSS[] F N VSS[] VSS[] F N VSS[] VSS[] F P VSS[] VSS[] VSS[] F Penryn_p..u.u + u/v_ u/v_ u/v_ u/v_ Place these parts reference to Intel demo board. u/.v_ u/v_ u/v_ u/v_ u/v_ u/v_ V_RE + u/v_ u/v_ u/v_ u/.v_ u/v_ u/v_ u/v_ u/v_ u/v_ u/v_ u/v_ u/v_ u/v_ u/v_ u/v_ u/v_ u/v_ u/v_ u/v_ u/v_ V_RE ulk Ps place to T of PU centeral u/v_ u/v_ u/v_ u/v_ Penryn PU Power Status and max current table PWER PLNE V_RE V_RE S S S/S Voltage VI VI I(max) Note Standard Voltage PU SV esign Target V_RE V_RE VI VI T Extreme Edition PU EE esign Target V +.V m V_RE u/v_ V_RE u/v_ V_RE u/v_ V_RE u/v_ V_RE U V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[] E V[] V[] E V[] V[] E V[] V[] E V[] V[] E V[] V[] E V[] V[] E V[] V[] E V[] V[] F V[] V[] F V[] V[] F V[] V[] F V[] V[] F V[] V[] F V[] V[] F E V[] V[] F E V[] E V[] VP[] G E V[] VP[] V E V[] VP[] J E V[] VP[] K E V[] VP[] M E V[] VP[] J E V[] VP[] K F V[] VP[] M F V[] VP[] N F V[] VP[] N F V[] VP[] R F V[] VP[] R F V[] VP[] T F V[] VP[] T F V[] VP[] V F V[] VP[] W V[] V[] V[] V[] V[] V[] V[] VI[] V[] VI[] F V[] VI[] E V[] VI[] F V[] VI[] E V[] VI[] F V[] VI[] E V[] V[] V[] VSENSE F V[] V[] V[] VSSSENSE E Penryn_p. V_RE PU_G +V_PR R _ H_VI H_VI H_VI H_VI H_VI H_VI H_VI V_RE R /F_ R /F_.u/V_ VP_PU VSENSE VSSSENSE Layout Note: Inside PU center cavity in rows.u/v_.u/v_ + u/v_ Layout Note: Route VSENSE and VSSSENSE traces at. hms with mil spacing. Place PU and P within inch of PU..u/V_ R _ R _ u/v_.u/v_ VP_PU VP_PU VP VP ulk P close to Pin V..u/V_.u/V_ Place.u near pin- VP VP +.V +.V.. efore V Stable fter V Stable (See Penryn EMTS Rev:. Table, for voltage and current) (See Penryn EMTS Rev:. Table- for VI table) PRJET : P/ Quanta omputer Inc. Size ocument Number Rev PU(/) PWER Friday, May, ate: Sheet of

5 VP R /F_ R /F_ R./F_ VP R K/F_ R K/F_ H_SWING.u/V_ H_RMP R _.*VP W:,S:, L<." W:,S:, L<." /*VP W:,S:, L<." H_VREF H_VREF H_#[..] H_#[..] H_#[..] H_#[..] H_PURST# H_PUSLP# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_SWING H_RMP H_PURST# H_PUSLP# H_VREF H_VREF U F H_#_ G H_#_ F H_#_ E H_#_ G H_#_ H H_#_ H H_#_ F H_#_ H_#_ H H_#_ M H_#_ M H_#_ J H_#_ J H_#_ N H_#_ J H_#_ P H_#_ L H_#_ R H_#_ N H_#_ L H_#_ M H_#_ J H_#_ N H_#_ R H_#_ N H_#_ N H_#_ P H_#_ N H_#_ L H_#_ N H_#_ M H_#_ Y H_#_ H_#_ Y H_#_ Y H_#_ Y H_#_ Y H_#_ Y H_#_ W H_#_ H_#_ Y H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ E H_#_ E H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ E H_#_ F H_#_ H_#_ E H_#_ H_#_ E H_#_ E H_#_ G H_#_ H_#_ H_SWING E H_RMP H_PURST# E H_PUSLP# H_VREF H_VREF NTIG_p HST H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_S# H_ST#_ H_ST#_ H_NR# H_PRI# H_REQ# H_EFER# H_SY# HPLL_LK HPLL_LK# H_PWR# H_RY# H_HIT# H_HITM# H_LK# H_TRY# H_INV#_ H_INV#_ H_INV#_ H_INV#_ H_STN#_ H_STN#_ H_STN#_ H_STN#_ H_STP#_ H_STP#_ H_STP#_ H_STP#_ H_REQ#_ H_REQ#_ H_REQ#_ H_REQ#_ H_REQ#_ H_RS#_ H_RS#_ H_RS#_ F H M J P R N M E P F G J E H J L L J H K F K L H G F G E H H J F H E H J L Y Y L M E L M E K F F H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_S# H_ST# H_ST# H_NR# H_PRI# H_REQ# H_EFER# H_SY# LK_MH_LK LK_MH_LK# H_PWR# H_RY# H_HIT# H_HITM# H_LK# H_TRY# H_INV# H_INV# H_INV# H_INV# H_STN# H_STN# H_STN# H_STN# H_STP# H_STP# H_STP# H_STP# H_REQ# H_REQ# H_REQ# H_REQ# H_REQ# H_RS# H_RS# H_RS# H_#[..] H_#[..] H_S# H_ST# H_ST# H_NR# H_PRI# H_REQ# H_EFER# H_SY# LK_MH_LK LK_MH_LK# H_PWR# H_RY# H_HIT# H_HITM# H_LK# H_TRY# H_INV#[..] H_STN#[..] H_STP#[..] H_REQ#[..] H_RS#[..] M ption Table Reference N/ escription N/ PRJET : P/ Quanta omputer Inc. Size ocument Number Rev N (/) HST ate: Friday, May, Sheet of

6 PM_SYN#,, IH_PRSTP# PM_ETTS# PM_ETTS#,, ELY_VR_PWRG PLT_RST#_N, PM_THRMTRIP#, PM_PRSLPVR N Thermal trip pin No use Thermal trip N side can N.(N has T) PM_PRSTP# The aisy chain topology should be routed from IHM to IMVP, then to (G)MH and PU, in that order. MH_SEL MH_SEL MH_SEL MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ PM_ETTS# PM_ETTS# T T T T T T T T T T T T T T T T T T T T T T T T T T T T R _ R _ R _ R _ R _ R _ R *_ R _ T T T T T T T T T T T T T T T T T T T T T T T T T U MH_RSV M MH_RSV RSV N MH_RSV RSV R MH_RSV RSV T MH_RSV RSV H MH_RSV RSV H MH_RSV RSV H MH_RSV RSV H MH_RSV RSV K RSV MH_RSV T RSV MH_RSV RSV MH_RSV M RSV MH_RSV Y RSV MH_RSV MH_RSV RSV G MH_RSV RSV F MH_RSV RSV H MH_RSV RSV F RSV L ME_JTG_TK JTG_TI K ME_JTG_TI N ME_JTG_T JTG_TMS M ME_JTG_TMS MH_SEL T MH_SEL FG_ R MH_SEL FG_ P MH_FG_ FG_ P MH_FG_ FG_ P MH_FG_ FG_ MH_FG_ FG_ N MH_FG_ FG_ M MH_FG_ FG_ E MH_FG_ FG_ MH_FG_ FG_ MH_FG_ FG_ N MH_FG_ FG_ P MH_FG_ FG_ T MH_FG_ FG_ R MH_FG_ FG_ M MH_FG_ FG_ L MH_FG_ FG_ H MH_FG_ FG_ P MH_FG_ FG_ R MH_FG_ FG_ T FG_ PM_SYN#_R R IH_PRSTP#_R PM_SYN# PM_ETTS# E_R PM_PRSTP# N TS#IMM R PM_ET_TS#_ P PM_ET_TS#_ T RST_IN#_MH PWRK T THRMTRIP#_R RSTIN# T PRSLPVR_R THERMTRIP# R PRSLPVR TP_MH_N G TP_MH_N N_ F TP_MH_N N_ TP_MH_N N_ TP_MH_N N_ H TP_MH_N N_ G TP_MH_N N_ E TP_MH_N N_ H TP_MH_N N_ F TP_MH_N N_ G TP_MH_N N_ H TP_MH_N N_ H TP_MH_N N_ H TP_MH_N N_ H TP_MH_N N_ G TP_MH_N N_ H TP_MH_N N_ F TP_MH_N N_ H TP_MH_N N_ G TP_MH_N N_ E TP_MH_N N_ G TP_MH_N N_ F TP_MH_N N_ TP_MH_N N_ TP_MH_N N_ F N_ FG PM RSV ME JTG N R LK/ NTRL/MPENSTIN LK MI GRPHIS VI ME MIS H S_K_ P S_K_ T S_K_ V S_K_ U S_K#_ R S_K#_ R S_K#_ U S_K#_ V S_KE_ S_KE_ Y S_KE_ Y S_KE_ S_S#_ S_S#_ Y S_S#_ V S_S#_ R S_T_ S_T_ Y S_T_ F S_T_ Y SM_RMP G SM_RMP# H SM_RMP_VH F SM_RMP_VL H SM_VREF V SM_PWRK R SM_RET F SM_RMRST# PLL_REF_LK PLL_REF_LK# PLL_REF_SSLK E PLL_REF_SSLK# F PEG_LK F PEG_LK# E MI_RN_ E MI_RN_ E MI_RN_ E MI_RN_ H MI_RP_ E MI_RP_ E MI_RP_ E MI_RP_ H MI_TN_ E MI_TN_ E MI_TN_ E MI_TN_ H MI_TP_ MI_TP_ E MI_TP_ F MI_TP_ H GF_VI_ GF_VI_ GF_VI_ G GF_VI_ F GF_VI_ E GF_VR_EN L_LK H L_T H L_PWRK N L_RST# J L_VREF H P_TRLLK N P_TRLT M SV_TRLLK G SV_TRLT E LKREQ# K IH_SYN# H TSTN# H_LK H_RST# H_SI H_S H_SYN M_LK_R M_LK_R M_LK_R M_LK_R M_LK_R# M_LK_R# M_LK_R# M_LK_R# M_KE M_KE M_KE M_KE M_S# M_S# M_S# M_S# M_T M_T M_T M_T M_RMP M_RMP# SM_RMP_VH SM_RMP_VL SM_VREF SM_PWRK SM_RET MH_SM_RMRST# REFLK REFLK# REFSSLK REFSSLK# LK_PIE_GPLL LK_PIE_GPLL# MI_TN MI_TN MI_TN MI_TN MI_TP MI_TP MI_TP MI_TP MI_RN MI_RN MI_RN MI_RN MI_RP MI_RP MI_RP MI_RP L_LK L_T MPWRK L_RST# MH_LVREF_R P_TRLLK P_TRLT SV_TRLLK SV_TRLT LK_MH_E# MH_IH_SYN# TSTN# T T T T T T T T T T T T T M_LK_R M_LK_R M_LK_R M_LK_R M_LK_R# M_LK_R# M_LK_R# M_LK_R# M_KE, M_KE, M_KE, M_KE, M_S#, M_S#, M_S#, M_S#, M_T, M_T, M_T, M_T, REFLK REFLK# REFSSLK REFSSLK# LK_PIE_GPLL LK_PIE_GPLL# MI_TN[:] MI_TP[:] MI_RN[:] MI_RP[:] L_LK L_T MPWRK L_RST# SM_RMRST# only for R.(R N). P_TRL for HMI port SV_TRL for HMI port P_TRLT SV_TRLT LK_MH_E# MH_IH_SYN# RT I/F INT_RT_LK INT_RT_T INT_HSYN INT_VSYN, NTE: If (G)MH's H udio signals are connected to IHM for ihmi, VH and VSUSH on IHM should be only on.v. These power pins on IHM can be supplied with.v if and only if (G)MH's H is not connected to IHM. onsequently, only.v audio/modem codecs can be used on the platform. LVS I/F INT_LVS_PWM INT_LVS_LN INT_LVS_EILK INT_LVS_EIT INT_LVS_IGN TV IF (isable) INT_TLLKUT- INT_TLLKUT+ INT_TULKUT- INT_TULKUT+ INT_TLUT- INT_TLUT- INT_TLUT- INT_TLUT+ INT_TLUT+ INT_TLUT+ INT_TUUT- INT_TUUT- INT_TUUT- INT_TUUT+ INT_TUUT+ INT_TUUT+ INT_HSYN R INT_VSYN R HSYN/VSYN serial R place close to N M ption Table Reference escription IV@ INT VG EV@ ET VG IHM@ EV_IV@ T T T T T INT HMI EV&IV diff. value INT_LVS_PWM INT_LVS_LN L_TRL_LK L_TRL_T INT_LVS_EILK INT_LVS_EIT INT_TUUT- INT_TUUT- INT_TUUT- INT_TUUT- INT_LVS_IGN LVS_IG LVS_VG LVS_VREFH LVS_VREFL INT_TLLKUT- INT_TLLKUT+ INT_TULKUT- INT_TULKUT+ INT_TLUT- INT_TLUT- INT_TLUT- INT_TLUT- INT_TLUT+ INT_TLUT+ INT_TLUT+ INT_TLUT+ INT_TUUT+ INT_TUUT+ INT_TUUT+ INT_TUUT+ INT_TV_MP INT_TV_Y/G INT_TV_/R INT_TV_RNT TV_NSEL_ TV_NSEL_ INT INTG INTR RT_IRTN INT_RT_LK INT_RT_T IV@./F_HSYN_G RTIREF IV@./F_VSYN_G For onnect to.ohm For EV@ N L G M M K J M E E H E G H F H G J G F K F H K H E E G J G H J J E L U L_KLT_TRL L_KLT_EN L_TRL_LK L_TRL_T L LK L T L_V_EN LVS_IG LVS_VG LVS_VREFH LVS_VREFL LVS_LK# LVS_LK LVS_LK# LVS_LK LVS_T#_ LVS_T#_ LVS_T#_ LVS_T#_ LVS_T_ LVS_T_ LVS_T_ LVS_T_ LVS_T#_ LVS_T#_ LVS_T#_ LVS_T#_ LVS_T_ LVS_T_ LVS_T_ LVS_T_ TV_ TV_ TV_ TV_RTN TV_NSEL_ TV_NSEL_ RT_LUE RT_GREEN RT_RE RT_IRTN RT LK RT T RT_HSYN RT_TV_IREF RT_VSYN NTIG_p LVS PI-EPRESS GRPHIS TV VG L<.", If PIE not support still connect to +V_PEG EP MP PEG_MPI T R PEG_MP T PEG_RN PEG_R#_ H PEG_RN PEG_R#_ J PEG_RN PEG_R#_ L PEG_RN PEG_R#_ L PEG_RN PEG_R#_ N PEG_RN PEG_R#_ P PEG_RN PEG_R#_ N PEG_RN PEG_R#_ T PEG_RN PEG_R#_ U PEG_RN PEG_R#_ Y PEG_RN PEG_R#_ Y PEG_RN PEG_R#_ Y PEG_RN PEG_R#_ PEG_RN PEG_R#_ PEG_RN PEG_R#_ PEG_RN PEG_R#_ PEG_RP PEG_R_ H PEG_RP PEG_R_ J PEG_RP PEG_R_ L PEG_RP PEG_R_ L PEG_RP PEG_R_ N PEG_RP PEG_R_ P PEG_RP PEG_R_ N PEG_RP PEG_R_ T PEG_RP PEG_R_ U PEG_RP PEG_R_ Y PEG_RP PEG_R_ W PEG_RP PEG_R_ Y PEG_RP PEG_R_ PEG_RP PEG_R_ PEG_RP PEG_R_ PEG_RP PEG_R PEG_TN PEG_T#_ J _PEG_TN PEG_T#_ M _PEG_TN PEG_T#_ M _PEG_TN PEG_T#_ M _PEG_TN PEG_T#_ M _PEG_TN PEG_T#_ R _PEG_TN PEG_T#_ N _PEG_TN PEG_T#_ T _PEG_TN PEG_T#_ U _PEG_TN PEG_T#_ U _PEG_TN PEG_T#_ Y _PEG_TN PEG_T# PEG_TN PEG_T# PEG_TN PEG_T# PEG_TN PEG_T# PEG_TN PEG_T# PEG_TP PEG_T_ J _PEG_TP PEG_T_ L _PEG_TP PEG_T_ M _PEG_TP PEG_T_ M _PEG_TP PEG_T_ M _PEG_TP PEG_T_ R _PEG_TP PEG_T_ N _PEG_TP PEG_T_ T _PEG_TP PEG_T_ U _PEG_TP PEG_T_ U _PEG_TP PEG_T_ Y _PEG_TP PEG_T_ Y _PEG_TP PEG_T PEG_TP PEG_T PEG_TP PEG_T PEG_TP PEG_T_ lose U INTR INTG INT +.V_V_PEG./F_ PEG_RN[:] PEG_RP[:] EV@.u/V_ PEG_TN EV@.u/V_ PEG_TN EV@.u/V_ PEG_TN EV@.u/V_ PEG_TN EV@.u/V_ PEG_TN EV@.u/V_ PEG_TN EV@.u/V_ PEG_TN EV@.u/V_ PEG_TN EV@.u/V_ PEG_TN EV@.u/V_ PEG_TN EV@.u/V_ PEG_TN EV@.u/V_ PEG_TN EV@.u/V_ PEG_TN EV@.u/V_ PEG_TN EV@.u/V_ PEG_TN EV@.u/V_ PEG_TN EV@.u/V_ PEG_TP EV@.u/V_ PEG_TP EV@.u/V_ PEG_TP EV@.u/V_ PEG_TP EV@.u/V_ PEG_TP EV@.u/V_ PEG_TP EV@.u/V_ PEG_TP EV@.u/V_ PEG_TP EV@.u/V_ PEG_TP EV@.u/V_ PEG_TP EV@.u/V_ PEG_TP EV@.u/V_ PEG_TP EV@.u/V_ PEG_TP EV@.u/V_ PEG_TP EV@.u/V_ PEG_TP EV@.u/V_ PEG_TP INT_RT_RE INT_RT_GRN INT_RT_LU PEG_TN[:] PEG_TP[:] NTIG_p *.P *.P *.P *.P *.P *.P heck list note : L_REF=.V VP R K/F_ SM_VREF.efault use voltage divider for poor layout cause +SMR_VREF not meet spec.nd Intel circuit PU/P is K,ut heck list PU/P is K. R _ SMR_VREF <hecklist ver.> If TSTN# is not used, then it must be terminated with a - pull-up resistor to VP. TSTN# _ R VP V IV&EV is/enable LVS setting(see G. P Table ) R IV@_ LVS_VREFH For ohm LVS_VREFL For EV@ N For R IV@.K/F_ LVS_IG For EV@ N MH_LVREF_R.u/V_ R /F_ SM_VREF R R *K/F_ *K/F_ +.VSUS_GMH LK_MH_E# PM_ETTS# PM_ETTS# K_ K_ K_ R R R V R IV@K_ L_TRL_LK For K For EV@ N R IV@K_ L_TRL_T IV&EV is/enable RT setting(see G. P Table ) is TV/En RT( See G. P Table ) SM_RET R /F_ SM_PWRK only for R.(R P only) R R *EV@_ *EV@_ INT_RT_LK INT_RT_T For N For EV@ ohm to or N R R R EV_IV@_ INT_TV_MP EV_IV@_ INT_TV_Y/G EV_IV@_ INT_TV_/R For ohm to For EV@ ohm to +.VSUS_GMH R./F_ M_RMP R */F_ +.VSUS_GMH R */F_ M_RMP# R./F_ +.VSUS_GMH R K/F_ R.K/F_ R K/F_ SM_RMP_VH.u/V_.u/.V_ SM_RMP_VL.u/V_.u/.V_ SM_PWRK R *K/F_ R K/F_ HWPG_.V, R R R R R R *EV@_ HSYN_G *EV@_ VSYN_G EV_IV@/F_ INT EV_IV@/F_ INTG EV_IV@/F_ INTR EV_IV@K/F_ RTIREF Layout Note :See G. P For N For EV@ ohm to or N For onnect to ohm/f For EV@ onnect to ohm For onnect to.k/f For EV@ onnect to ohm For ohm to R _ TV_NSEL_ For EV@ ohm to R _ TV_NSEL_ IV&EV is/enable PLL setting(see G. P Table ) REFLK R EV@_ REFLK# R EV@_ For N REFSSLK R EV@_ For EV@ ohm to REFSSLK# R EV@_ PRJET : P/ Quanta omputer Inc. Size ocument Number Rev N(/) Wednesday, June, ate: Sheet of

7 M M M M M M M M M M M M M M M M M QS M QS M QS M QS M QS M QS M QS M QS M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS# M M M M M M M M M M M M M M M M RS# M S# M WE# M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M S# M S# M S# M RS# M S# M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M M S# M S# M S# M M QS# M M QS# M M M QS# M M QS# M M M M QS# M M QS M QS# M M M M M M QS M M M M M QS M M QS M QS M M QS M M M M QS M QS M M M M M QS# M QS# M M M M WE# M Q[..] M S#, M M[..] M QS[..] M QS#[..] M [..], M RS#, M S#, M WE#, M S#, M S#, M S#, M M[..] M QS[..] M QS#[..] M [..], M RS#, M S#, M WE#, M S#, M S#, M Q[..] M Q[..] M Q[..] M Q[..] M Q[..] M Q[..] M Q[..] M Q[..] M Q[..] M Q[..] M Q[..] M Q[..] M Q[..] M Q[..] M Q[..] Size ocument Number Rev ate: Sheet of RII Friday, May, Size ocument Number Rev ate: Sheet of RII Friday, May, Size ocument Number Rev ate: Sheet of RII Friday, May, N/ Reference escription M ption Table N/ S_Q_ J S_Q_ J S_Q_ U S_Q_ T S_Q_ N S_Q_ N S_Q_ U S_Q_ U S_Q_ V S_Q_ Y S_Q_ S_Q_ S_Q_ N S_Q_ V S_Q_ Y S_Q_ S_Q_ S_Q_ Y S_Q_ S_Q_ V S_Q_ T S_Q_ Y S_Q_ S_Q_ M S_Q_ V S_Q_ W S_Q_ S_Q_ U S_Q_ S_Q_ S_Q_ U S_Q_ V S_Q_ S_Q_ S_Q_ J S_Q_ S_Q_ S_Q_ U S_Q_ V S_Q_ S_Q_ S_Q_ Y S_Q_ S_Q_ V S_Q_ V S_Q_ J S_Q_ T S_Q_ N S_Q_ U S_Q_ U S_Q_ T S_Q_ N S_Q_ M S_Q_ M S_Q_ J S_Q_ J S_Q_ M S_Q_ N S_Q_ M S_Q_ J S_Q_ J S_Q_ M S_Q_ N S_Q_ N S_S_ S_S_ G S_S_ T S_S# S_M_ M S_M_ T S_M_ Y S_M_ U S_M_ S_M_ Y S_M_ T S_QS_ J S_QS_ T S_QS_ S_QS_ S_QS_ W S_QS_ S_QS_ U S_QS_ M S_M_ J S_QS#_ J S_QS#_ T S_QS#_ S_QS#_ S_QS#_ Y S_QS#_ S_QS#_ U S_QS#_ M S_M_ S_M_ S_M_ S_M_ G S_M_ H S_M_ H S_M_ G S_M_ H S_M_ G S_M_ S_M_ S_M_ G S_M_ F S_M_ W S_RS# S_WE# Y S_M_ Y R SYSTEM MEMRY U NTIG_p R SYSTEM MEMRY U NTIG_p S_Q_ K S_Q_ H S_Q_ S_Q_ Y S_Q_ T S_Q_ R S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ G S_Q_ F S_Q_ P S_Q_ E S_Q_ S_Q_ F S_Q_ F S_Q_ G S_Q_ F S_Q_ H S_Q_ G S_Q_ H S_Q_ G S_Q_ P S_Q_ G S_Q_ H S_Q_ H S_Q_ G S_Q_ H S_Q_ G S_Q_ H S_Q_ F S_Q_ F S_Q_ G S_Q_ J S_Q_ S_Q_ S_Q_ Y S_Q_ Y S_Q_ F S_Q_ F S_Q_ S_Q_ S_Q_ V S_Q_ U S_Q_ J S_Q_ R S_Q_ N S_Q_ Y S_Q_ V S_Q_ P S_Q_ R S_Q_ L S_Q_ L S_Q_ J S_Q_ H S_Q_ M S_Q_ M S_Q_ M S_Q_ H S_Q_ J S_Q_ P S_Q_ U S_Q_ U S_S_ S_S_ S_S_ S_S# G S_M_ M S_M_ Y S_M_ S_M_ F S_M_ G S_M_ S_M_ P S_M_ K S_QS_ L S_QS_ V S_QS_ G S_QS_ G S_QS_ H S_QS_ S_QS_ U S_QS_ N S_QS#_ L S_QS#_ V S_QS#_ H S_QS#_ H S_QS#_ G S_QS#_ S_QS#_ T S_QS#_ N S_M_ V S_M_ S_M_ S_M_ W S_M_ Y S_M_ H S_M_ S_M_ U S_M_ W S_M_ S_M_ U S_M_ W S_M_ T S_M_ S_M_ U S_RS# U S_WE# F R SYSTEM MEMRY UE NTIG_p R SYSTEM MEMRY UE NTIG_p Quanta omputer Inc. PRJET : P/ Quanta omputer Inc. PRJET : P/

8 M ption Table Reference escription INT VG ET VG VP UF +.VSUS_GMH UG +VGF_RE_INT +.VSUS_GMH.VSUS R _ R _ G V_ V_ V_ V_ Y V_ V V_ U V_ M V_ K V_ J V_ G V_ F V_ E V_ V_ V_ Y V_ W V_ V V_ U V_ H V_ F V_ V_ V_ J V_ G V_ E V_ V_ H V_ G V_ F V_ G V_ J V_ H V_ F V_ T V_ NTIG_p V RE PWER V NTF V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ VP M L K J H G E Y W U M L K H G F E Y W V U L K J H G E Y W V L K L K K K K +VGF_RE_INT R R P N H G F Y W V U T R P N H G F G H G F Y W V U T R P W W T +VGF_RE_INT Y E E Y E J G E Y H F E T T M L E J H G F Y V U N M U T IV@/F_ J IV@/F_ H V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_/N V_SM_/N V_SM_/N V_SM_/N V_SM_/N V_SM_/N V_SM_/N V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_ V_G_SENSE VSS_G_SENSE PWER V SM V GF V GF NTF V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V_G_NTF_ V SM LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF W V W V W V W V W V M L K W V U M K W U M L K J H G F E Y W V U M K H G F E Y W V M L K J H G F E Y W V U V M V Y M + lose to GMH u/.v_ u/.v_.u/v_ u/.v_ VP +.u/v_.u/.v_.u/.v_ u/.v_ u/v_ lose to GMH +VGF_RE_INT IV@.u/.V_ IV@u/V_ IV@u/V_ IV@u/.V_ IV@.u/V_ IV@.u/V_ +VGF_RE_INT + + IV@u/.V_ IV@u/.V_ lose to GMH N Power Status and max current table(/) PWER PLNE S S S/S Voltage I(max) Note V(ET_VG) +.V m V(INT_VG) +.V m V_G +.V m Graphics ore V_SM() +.VSUS (RII-). V_SM(Standby) +.VSUS m Self Refresh during S (See N ES Rev:. Section. for max current) (See N ES Rev:. Section. for voltage) lose to each pins.v Internal connect to power.u/v_.u/v_.u/.v_.u/.v_.u/v_ u/v_ u/v_ See Page EV&IV table R EV@_ R EV@_ Place close to the GMH and different location R EV@_ R R R R R R R R VP IV@_ IV@_ IV@_ IV@_ IV@_ IV@_. Route V_G_SENSE and VSS_G_SENSE differentially. V_G_SENSE PU to +VGF_RE_INT with ohm and VSS_G_SENSE P with ohm for Intel suggest NTIG_p PRJET : P/ Quanta omputer Inc. Size ocument Number Rev N(/) V,NTF Friday, March, ate: Sheet of

9 V L IV@u/V_ +V TV_RT IV@LMPGSN_ IV@.u/V_ IV@.u/V_ R EV@_ R R +V G +V TV_RT IV@.u/V_ +V RT_ IV@.u/V_ M ption Table Reference escription IV@ INT VG EV@ ET VG IHM@ INT HMI VP L IV@_ VP L IV@_ +.VM_PLL + IV@u/.V_ IV@.u/V_ R EV@_ R IV@u/.V_ + IV@.u/V_ R EV@_ R VP VP VP VP R _ R _ R _ +.VM_MH_PLL + u/v_ *.u/.v_ R _.u/v_ L _ *u/.v_ u/.v_ R.u/V_ u/.v_.u/v_.u/v_.u/v_ *./F_ *u/.v_ u/.v_ +.VM_PLL +.VM_HPLL +.VM_MPLL +.VM_MPLL_R IV@p/V_ +.VM SM +.VM SM_K V. R _ UH +V RT_ V_RT V_RT +V G V G VSS G +.VM_PLL F V_PLL +.VM_PLL L V_PLL +.VM_HPLL V_HPLL +.VM_MPLL E V_MPLL +.VSUS_TLVS J V_LVS J VSS_LVS +.V_V_PEG_G V_PEG_G.u/V_ +.VM_PEGPLL V_PEG_PLL +.VM SM R V_SM_ P V_SM_ N V_SM_ R V_SM_ P V_SM_ N V_SM_ T V_SM_ R V_SM_ P V_SM_ RT PLL LVS PEG SM VTT PWER VTT_ U VTT_ T VTT_ U VTT_ T VTT_ U VTT_ T VTT_ U VTT_ T VTT_ U VTT_ T VTT_ U VTT_ T VTT_ U VTT_ T VTT_ U VTT_ T VTT_ U VTT_ T VTT_ V VTT_ U VTT_ V VTT_ U VTT_ T VTT_ V VTT_ U.u/.V_.u/.V_ +.VM_F.u/V_ +.VSUS_V_SM_K +.VSUS_TLVS.u/V_ R EV@_ R R +.u/v_ u/v_ L.uh_ VP u/.v_ *u/v_ L uh_ +.VSUS_GMH /F_ R +.VSUS_SMK_R u/v_ L IV@.uh_.VSUS IV@p/V_ IV@u/.V_ VP V V. V. V. R R R _ L IV@_ IHM@_ IV@u/.V_ IV@.u/V_ IHM@.u/V_.u/V_ IV@LMPGSN_ IV@.u/V_ FR ihmi H I/F only.u/v_ IV@.u/V_ IV@.u/V_ R EV@_ R R EV@_ R R EV@_ +V_TV_ +.V_V_H IF ihmi not used,h connect ot (G. P) +.V_TV +.V_Q.u/V_ +.VM SM_K P N P N N M M M L M L M L +V_TV_ +.V_V_H +.V_TV M +.V_Q L +.VM_MH_PLL F +.VM_PEGPLL +.VSUS_LVS M L V_SM_K_ V_SM_K_ V_SM_K_ V_SM_K_ V_SM_K_ V_SM_K_NTF_ V_SM_K_NTF_ V_SM_K_NTF_ V_SM_K_NTF_ V_SM_K_NTF_ V_SM_K_NTF_ V_SM_K_NTF_ V_SM_K_NTF_ V_TV V_TV V_H V_TV V_Q V_HPLL V_PEG_PLL V_LVS_ V_LVS_ NTIG_p TV H LVS K TV/RT F SM K MI HV PEG V_F_ V_F_ V_F_ V_SM_K_ V_SM_K_ V_SM_K_ V_SM_K_ V_T_LVS V_HV_ V_HV_ V_HV_ VTTLF V_PEG_ V_PEG_ V_PEG_ V_PEG_ V_PEG_ F H G F K V U V U U V_MI_ H V_MI_ F V_MI_ H V_MI_ G VTTLF VTTLF L VTTLF +.VM_F +.VSUS_V_SM_K +.VSUS_TLVS +V_V_HV +.V_V_PEG +.V_V_MI.u/.V_.u/.V_ +V_V_HV.u/V_ +.V_V_PEG.u/V_.u/.V_ +.V_V_MI _ R u/.v_ *u/v_ R _ +.V_V_PEG + u/.v_ + L *u/.v_ +.V_S R _ R _.u/v_ T V VP *nh_ +.V_V_PEG VP el it to save space? R VP L LMPGSN_ +.VM_PEGPLL N Power Status and max current table(/)(n left side) PWER PLNE S S S/S Voltage I(max) Note V_RT_ +.V m ET&INT VG Power Plane ption table PWER PLNE ET VG INT VG MRK V_RT_ +V R N Power Status and max current table(/)(n Right side) PWER PLNE S S S/S Voltage I(max) Note VTT +.V m FS at MHz V G +.V m V_LVS +.VSUS R V_F +.V m.u/v_.u/v_ V_PLL +.V.m V_T_LVS +.VSUS R V_SM_K() +.VSUS m (RII-) m V_PLL +.V.m V_LVS +.VSUS R V_T_LVS +.VSUS m R /F_ +.VM_PEGPLL_R V_HPLL V_MPLL +.V +.V m.m V_TV V_TV_ +.V +.V +V R V_HV V_PEG +V +.V m m V_LVS +.VSUS.m V_Q +.V R V_MI +.V m.vsus R IV@_ u/v_ +.VSUS_LVS V_PEG_G V_PEG_PLL V_SM(RII-) V_SM_K() +.V +.V +.V +.V u m m m (RII-) m (RII-) m V G V_G V_G_NTF V_PLL +V +.V +.V +.V R R Page R Page R (See N ES Rev:. Section. for max current) (See N ES Rev:. Section. for voltage) IV@u/.V_ R EV@_ R V_TV_ V_H V_TV V_Q V_HPLL V_PEG_PLL V_LVS +.V +.V +.V +.V +.V +.V +.VSUS m m m u m m m V_PLL +.V R V_H +.V R For ihmi ET VG->isable TV/RT/LVS/HMI(See G. P Table ) INT VG->isable TV/Enable RT( See G. P Table ) INT VG->isable HMI(See G. P section..) PRJET : P/ Quanta omputer Inc. Size ocument Number Rev N(/) PWER Thursday, pril, ate: Sheet of

10 MH_VSS_ MH_VSS_ MH_VSS_ MH_VSS_ MH_VSS_ Size ocument Number Rev ate: Sheet of N(/) VSS Friday, March, Size ocument Number Rev ate: Sheet of N(/) VSS Friday, March, Size ocument Number Rev ate: Sheet of N(/) VSS Friday, March, N/ Reference escription M ption Table N/ Quanta omputer Inc. PRJET : P/ Quanta omputer Inc. PRJET : P/ R _ R _ VSS_ G VSS_ W VSS_ U VSS_ P VSS_ N VSS_ H VSS_ F VSS_ VSS_ R VSS_ M VSS_ J VSS_ G VSS_ VSS_ VSS_ W VSS_ T VSS_ J VSS_ G VSS_ Y VSS_ N VSS_ K VSS_ F VSS_ VSS_ VSS_ G VSS_ VSS_ G VSS_ VSS_ W VSS_ T VSS_ R VSS_ M VSS_ H VSS_ VSS_ VSS_ U VSS_ N VSS_ N VSS_ K VSS_ G VSS_ E VSS_ G VSS_ W VSS_ VSS_ G VSS_ VSS_ VSS_ G VSS_ VSS_ VSS_ N VSS_ J VSS_ E VSS_ N VSS_ L VSS_ G VSS_ E VSS_ F VSS_ V VSS_ T VSS_ M VSS_ VSS_ J VSS_ VSS_ VSS_ VSS_ Y VSS_ N VSS_ H VSS_ Y VSS_ N VSS_ G VSS_ VSS_ G VSS_ V VSS_ T VSS_ J VSS_ E VSS_ VSS_ H VSS_ VSS_ G VSS_ VSS_ M VSS_ N VSS_ VSS_ M VSS_ F VSS_ H VSS_ Y VSS_ L VSS_ E VSS_ VSS_ Y VSS_ U VSS_ N VSS_ J VSS_ E VSS_ VSS_ N VSS_ J VSS_ G VSS_ VSS_ V VSS_ T VSS_ VSS_ M VSS_ M VSS_ VSS_ VSS_ H VSS_ VSS_ Y VSS_ L VSS_ J VSS_ H VSS_ F VSS_ E VSS_ VSS_ V VSS_ L VSS_NTF_ F VSS_NTF_ VSS_NTF_ V VSS_NTF_ J VSS_NTF_ M VSS_NTF_ F VSS_NTF_ VSS_NTF_ U VSS_NTF_ U VSS_NTF_ L VSS_NTF_ V VSS_NTF_ VSS_NTF_ L VSS_NTF_ J VSS_NTF_ VSS_NTF_ U VSS_S_ H VSS_S_ H VSS_S_ VSS_S_ VSS_S_ N_ E N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ N_ F N_ E N_ N_ VSS_ R VSS_ P VSS_ VSS_ R VSS_ U VSS_ P VSS_ F VSS_ W VSS_ E VSS_ F VSS_ H VSS_ J VSS_ VSS_ VSS_ Y VSS_ M VSS_ K VSS_ M VSS_ VSS_ P VSS_ H VSS_ VSS_ V VSS_ T VSS_ U VSS_ U VSS_ U VSS_ U VSS_ L VSS_ J N_ VSS VSS NTF VSS S N UJ NTIG_p VSS VSS NTF VSS S N UJ NTIG_p R _ R _ R _ R _ VSS_ U VSS_ VSS_ R VSS_ L VSS_ VSS_ W VSS_ N VSS_ J VSS_ F VSS_ VSS_ VSS_ Y VSS_ T VSS_ N VSS_ L VSS_ G VSS_ VSS_ VSS_ V VSS_ R VSS_ M VSS_ V VSS_ R VSS_ P VSS_ H VSS_ F VSS_ F VSS_ H VSS_ VSS_ VSS_ Y VSS_ U VSS_ T VSS_ M VSS_ F VSS_ VSS_ V VSS_ U VSS_ M VSS_ J VSS_ VSS_ G VSS_ Y VSS_ T VSS_ N VSS_ J VSS_ E VSS_ N VSS_ L VSS_ VSS_ U VSS_ M VSS_ H VSS_ VSS_ VSS_ Y VSS_ U VSS_ T VSS_ M VSS_ G VSS_ VSS_ G VSS_ VSS_ V VSS_ N VSS_ H VSS_ E VSS_ T VSS_ M VSS_ J VSS_ E VSS_ N VSS_ L VSS_ VSS_ H VSS_ VSS_ VSS_ U VSS_ H VSS_ VSS_ VSS_ Y VSS_ U VSS_ T VSS_ J VSS_ F VSS_ VSS_ VSS_ M VSS_ E VSS_ P VSS_ L VSS_ J VSS_ F VSS_ VSS_ H VSS_ VSS_ Y VSS_ U VSS_ T VSS_ F VSS_ M VSS_ J VSS_ F VSS_ E VSS_ W VSS_ VSS_ VSS_ G VSS_ VSS_ VSS_ V VSS_ R VSS_ L VSS_ H VSS_ VSS_ P VSS_ L VSS_ H VSS_ N VSS_ K VSS_ F VSS_ VSS_ VSS_ N VSS_ T VSS_ N VSS_ K VSS_ H VSS_ F VSS_ VSS_ G VSS_ VSS_ VSS_ V VSS_ T VSS_ R VSS_ J VSS_ G VSS_ E VSS_ VSS_ Y VSS_ P VSS_ K VSS_ H VSS_ F VSS_ VSS_ F VSS_ H VSS_ F VSS_ VSS_ VSS_ VSS_ VSS_ H VSS_ VSS_ VSS_ V VSS_ R VSS_ J VSS_ VSS_ Y VSS_ N VSS_ L VSS_ J VSS_ G VSS_ E VSS_ F VSS_ F VSS_ VSS_ W VSS_ T VSS_ N VSS_ J VSS_ H VSS_ VSS_ G VSS_ U VSS_ T VSS_ H VSS_ VSS_ L VSS_ Y VSS_ G VSS_ E VSS_ G VSS_ VSS_ Y VSS_ J VSS_ F VSS_ R VSS_ K VSS_ J VSS_ F VSS_ H VSS_ Y VSS_ K VSS_ VSS UI NTIG_p VSS UI NTIG_p R _ R _ R _ R _

11 North ridge Strap Pin onfiguration Table (See G. P Table ) (See N ES. P Table ) Pin Name Strap description onfiguration PU<.K> P <.K> Note FG[:] FS Frequency Select []= FS MHz [] = FS MHz [] = FS MHz See Page FS selection table FG[:] FG MI Select = MI = MI (efault) MH_FG_ R *.K/F_ FG itpm Host Interface = itpm Host Interface is enabled = itpm Host Interface is disabled(efault) MH_FG_ R *K/F_ Enable itpm FG ME TLS onfidentiality = MT Firmware will use TLS cipher suite with no confidentiality = MT Firmware will use TLS cipher suite with confidentiality(efault) MH_FG_ R *.K/F_ M ption Table FG Reference N/ escription N/ FG PI Express Graphics Lane Reversal = Reverse Lanes = Normal operation(efault) MH_FG_ R *.K/F_ FG PIE Loopback enable = Enabled = isabled (efault) MH_FG_ R *.K/F_ FG FG LLZ = LLZ mode enable = disable(efault) MH_FG_ R *.K/F_ FG R = R mode enable = disable(efault) MH_FG_ R *.K/F_ FG[:] FG FS ynamic T = ynamic T disable = ynamic T Enable(efault) MH_FG_ R *.K/F_ FG[:] FG MI Lane Reversal = Normal (efault) = Lanes Reversed MH_FG_ R *.K/F_ V FG igital isplay Port (SV/P/iHMI) oncurrent with PIE = nly igital isplay port (SV/P/iHMI) or PIE is operational (efault) = igital isplay port (SV/P/iHMI) and PIE are operating simultaneously via PEG port MH_FG_ R *.K/F_ V SV_TRLT SV Present = No SV/HMI/P evice Present(efault) = SV/HMI/P evice present SV_TRLT R *.K/F_ V L T Local Flat Panel(LFP) Present = LFP isable(efault) = LFP ard Present;PIE disable, INT_LVS_EIT R *.K/F_ V P_TRLT igital isplay Present = igital display(hmi/p) device absent(efault) = igital display(hmi/p) device present P_TRLT R *.K/F_ V Enable itpm Table PGE Net Name PU & P NTE MH_FG_ P K to SPI_MSI PU K to +V_S LGPI PU K to +V_S N Strap pin S Strap pin S Strap pin PRJET : P/ Quanta omputer Inc. Size ocument Number Rev N(/) STRP ate: Friday, May, Sheet of

12 RT RYSTL RESET JUMP VRT n R delay circuit with a time delay in the range of ms to ms should be provided R K_ VRT VRT RV p/v_ p/v_ R K_ R M_ R K/F_ u/.v_ u/.v_ LK_K R.KHZ Y M_ LK_K LER_MS LER_MS G *SHRT_ P SRT_RST# G *SHRT_ P (G. Table-) SM_INTRUER# Internal VRM enabled for IH_INTVRMEN VccSus_, VccSus_, VccL_, VccLN_ and VccL_. Z_SIN T T T T T T LK_K LK_K LER_MS SRT_RST# SM_INTRUER# IH_INTVRMEN IH_GPI GLN_MP H_IT_LK_R H_SYN_R H_RST#_R Z_SIN H_SIN H_SIN H_SIN H_SUT_R IH_GPI IH_GPI ST_LE# ST_RN_ ST_RP_ ST_TN_ ST_TP_ ST_RN_ ST_RP_ ST_TN_ ST_TP_ IT_LK_UI F E F G E F H E F G H E G G E G J H F G H J G F U RT RT RTRST# SRTRST# INTRUER# INTVRMEN LN_SLP GLN_LK LN_RSTSYN LN_R LN_R LN_R LN_T LN_T LN_T GPI GLN_MPI GLN_MP H_IT_LK H_SYN H_RST# H_SIN H_SIN H_SIN H_SIN H_SUT H_K_EN#/GPI H_K_RST#/GPI STLE# STRN STRP STTN STTP STRN STRP STTN STTP IHM REV. RT LP LN / GLN PU IH ST FWH/L FWH/L FWH/L FWH/L FWH/LFRME# LRQ# LRQ#/GPI GTE M# PRSTP# PSLP# FERR# PUPWRG IGNNE# INIT# INTR RIN# NMI SMI# STPLK# THRMTRIP# TP STRN STRP STTN STTP STRN STRP STTN STTP ST_LKN ST_LKP STRIS# STRIS K K L K K J J N J J E J F E G L F F H G G H J G F H J E F H J J H L L L L LFRME# LRQ# LRQ# GTE H_M# H_PRSTP#_R H_PSLP#_R H_FERR#_R H_PWRG H_IGNNE# H_INIT# H_INTR RIN# LRQ/# : Internal PU H_NMI H_SMI#_R H_STPLK# H_THERMTRIP_R IH_TP ST_RN_ ST_RP_ ST_TN_ ST_TP_ ST_RN_ ST_RP_ ST_TN_ ST_TP_ LK_PIE_ST# LK_PIE_ST ST_RIS_PN ST_RIS_PN<.".void routing next to clock/high speed signals T T T R./F_ L, L, L, L, LFRME#, GTE H_M# H_PWRG H_IGNNE# H_INIT# H_INTR RIN# H_NMI H_STPLK# LK_PIE_ST# LK_PIE_ST R *_ R _ R _ R _ R _ R _ Layout note: PRSTP#, aisy hain (S>Power>N>PU) H_SMI# ST I/F +.V_IH_I R *_ H_THERMTRIP_RR To ST H To ST H IH_PRSTP#,, H_PSLP# H_SMI# +.V_IH_I ST_RN ST_RP ST_TN ST_TP R _ ST_RN ST_RP ST_TN ST_TP R M ption Table +.V_IH_I *_ ST_RN ST_RP ST_TN ST_TP ST_RN ST_RP ST_TN ST_TP Reference R _ IHM@ H_FERR# PM_THRMTRIP# Layout note: PU R needs to placed within " of IH-M, series R must be placed within "of PU R w/o stub. escription INT HMI GTE RIN# R R H_FERR# PM_THRMTRIP#, p/v_ p/v_ p/v_ p/v_ p/v_ p/v_ p/v_ p/v_.k_ K_ ST_RN_ ST_RP_ ST_TN_ ST_TP_ ST_RN_ ST_RP_ ST_TN_ ST_TP_ V R V. K_ IH_GPI R To ST ST_RN ST_RP ST_TN ST_TP ST_RN ST_RP ST_TN ST_TP p/v_ p/v_ p/v_ p/v_ ST_RN_ ST_RP_ ST_TN_ ST_TP_ R./F_ GLN_MP. hm pull up to.v for GLN_MPI/ is required, no matter intel LN is used or not. p To est ST_RN ST_RP ST_TN ST_TP ST_RN ST_RP ST_TN ST_TP p/v_ p/v_ p/v_ p/v_ ST_RN_ ST_RP_ ST_TN_ ST_TP_ H udio I/F(E& ihmi) RT TTERY H_SUT_R R _ Z_SUT_UI VPU R K_ RV VRT R LER_MS H_RST#_R R _ Z_RST#_UI H_SYN_R R _ Z_SYN_UI R R_VRT RV u/v_ South ridge Strap Pin (/) Pin Name H_K_EN/ GPI STLE# H_IT_LK_R Strap description Sampled onfiguration PU/P Flash escriptor Security verride Strap PI Express Lane Reversal (Lanes -) PWRK PWRK = The Flash escriptor Security will be overridden. = The security measures defined in the Flash escriptor will be in effect Internal PU R _ IT_LK_UI This strap should only be enabled in manufacturing environments using an external pull-up resistor. N - --P-L K_ RT_N R Q MMT.K/F_ R RT_N.K/F_ R.K_ R VPU K_ TP H_SUT R hain Entrance R hain Entrance /PI Express* Port onfig bit (Port -) PWRK PWRK IH_TP H_SUT escription RSV Enter R hain Normal opration(efault) Set PIE port config bit IH_TP IH_TP H_SUT_R R R *K_ *K_ +V_H_I_IH PU V. PRJET : P/ Quanta omputer Inc. Size ocument Number Rev S(/) HST ate: Friday, May, Sheet of

13 PI/PI-E/US/MI/SPI M ption Table Reference IV@ escription INT VG [..] EV@ ET VG INT# PLT_RST-R# R _ R *_ T T R _ R _ V INT#_R INT#_R INT#_R INT#_R U E E E G F F E F F F F G H G H G H J PIRQ# E PIRQ# J PIRQ# PIRQ# GFRST# PLT_RST#_N PI REQ# F GNT# G REQ#/GPI GNT#/GPI REQ#/GPI F GNT#/GPI F REQ#/GPI E GNT#/GPI F /E# /E# /E# /E# IRY# PR E PIRST# R EVSEL# PERR# E PLK# SERR# J STP# TRY# F FRME# PLTRST# PILK PME# R Interrupt I/F IHM REV. PIRQE#/GPI H PIRQF#/GPI K PIRQG#/GPI F PIRQH#/GPI G GFRST# PLT_RST#_N REQ# GNT# REQ# GNT# REQ# GNT# REQ# GNT# E# E# E# E# IRY# PR PIRST# EVSEL# PERR# LK# SERR# STP# TRY# FRME# PLT_RST-R# PLK_IH PI_PME# INTE# INTF# INTG# INTH# REQ# GNT# T T T T T T E# E# E# E# IRY# PR PIRST#,, EVSEL# STP# TRY# FRME# PLK_IH PI_PME# T PI RUTING TLE ISEL REQ# / GNT# REQ# / GNT# PIE_RN PIE_RP PIE_TN PIE_TP PIE_RN PIE_RP PIE_TN PIE_TP PIE_RN PIE_RP PIE_TN PIE_TP PIE_RN PIE_RP PIE_TN PIE_TP PIE_RN PIE_RP PIE_TN PIE_TP INTERUPT EVIE INT#/INT# ZT INT#/INT#.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_ T T T T T R./F_ PIE_TN_ PIE_TP_ PIE_TN_ PIE_TP_ PIE_TN_ PIE_TP_ PIE_TN_ PIE_TP_ PIE_TN_ PIE_TP_ SPI_LK SPI_S# SPI_S# SPI_MSI SPI_MIS US# US# US# US# US# US# US# US# US# US# US# US# USRIS_PN U N PERN MIRN N PERP MIRP P PETN MITN P PETP MITP L PERN MIRN L PERP MIRP M PETN MITN M PETP MITP J PERN MIRN J PERP MIRP K PETN MITN K PETP MITP G PERN MIRN G PERP MIRP H PETN MITN H PETP MITP E PERN MI_LKN E PERP MI_LKP F PETN F PETP MI_ZMP MI_IRMP PERN/GLN_RN PERP/GLN_RP USPN PETN/GLN_TN USPP PETP/GLN_TP USPN USPP SPI_LK USPN SPI_S# USPP F SPI_S#/GPI/LGPI USPN USPP SPI_MSI USPN E SPI_MIS USPP USPN N #/GPI USPP N #/GPI USPN N #/GPI US USPP P #/GPI USPN M #/GPI USPP N #/GPI USPN M #/GPI USPP M #/GPI USPN N #/GPI USPP N #/GPI USPN P #/GPI USPP P #/GPI USPN USPP G USRIS G USRIS# IHM REV. PI-Express SPI irect Media Interface V V U U Y Y W W T T F F W W Y Y W W V V U U U U MI_RN MI_RP MI_TN MI_TP MI_RN MI_RP MI_TN MI_TP MI_RN MI_RP MI_TN MI_TP MI_RN MI_RP MI_TN MI_TP LK_PIE_IH# LK_PIE_IH MI_IRMP_R USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ MI_RN MI_RP MI_TN MI_TP MI_RN MI_RP MI_TN MI_TP MI_RN MI_RP MI_TN MI_TP MI_RN MI_RP MI_TN MI_TP LK_PIE_IH# LK_PIE_IH USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ T T T T +.V_PIE_IH R./F_ R U TSHFU.u/V_ PLTRST# R PLTRST#, K_ *K_ South ridge Strap Pin (/) PI PULL-UP US# PULL-UP Pin Name Strap description Sampled onfiguration PU/P H_SYN GNT# / GPI PI Express Port onfig bit (Port -) PI Express Port onfig bit (Port -) PWRK PWRK = efault = Setting bit = Setting bit = efault FRME# IRY# LK# REQ# V RP.K_PR V INT#_R STP# REQ# EVSEL# US# US# US# US# VSUS RP K_PR US# US# US# US# VSUS GNT# / GPI GNT# / GPI SPI_MSI GNT# SPI_S# / GPI / LGPI ESI Strap(Server nly) Top-lock Swap verride Integrated TPM Enable oot IS Selection oot IS Selection PWRK PWRK LPWRK PWRK LPWRK = MI for ESI-compatible = efault = "top-block swap" mode = efault = INT TPM disable(efault) = INT TPM enable PI_GNT# SPI_S# oot Location SPI(efault) PI LP GNT# isable itpm SPI_MSI GNT# SPI_S# INTH# REQ# R *K_ V R R R *K_ *K_ *K_ VSUS INT#_R INTF# V RP.K_PR RP.K_PR V V INTG# REQ# PERR# INT#_R INT#_R SERR# INTE# TRY# US# US# US# US# RP K_PR VSUS PRJET : P/ Quanta omputer Inc. Size ocument Number Rev S (/) PIE/PI/US ate: Friday, May, Sheet of

14 RV V RV V R R RV RV R R R R R R R R R R R R R R R R R R.K_.K_ K_ K_ K_ K_ K_ K_ *K_ K_ K_.K_ K_ K_.K_ K_ *K_ K_ K_ K_ SLK ST IH_GPI SM_LK_ME SM_T_ME RI# SYS_RST# SM_LERT# STPPI# STPPU# LKRUN# PIE_WKE# SERIRQ THERM_LERT# KSMI# SI# WP# IH_GPI IH_GPI IH_GPI SI#(PU to MIN or S) leakage issue R K_ SI# Enable itpm(pu to PU or S?) MH_IH_SYN#,, SLK ST SYS_RST# PM_SYN# PM_STPPI# PM_STPPU# LKRUN#, PIE_WKE# SERIRQ, THERM_LERT# R _ KSMI# SI# LN WP# SPKR IH_TP T T T T T T T T T T T SLK ST IH_GPI SM_LK_ME SM_T_ME RI# SUS_STT# SYS_RST# PM_SYN# SM_LERT# R R LKRUN# PIE_WKE# SERIRQ THERM_LERT# VR_PWRG_LKEN IH_TP KSMI# Port_# SI# IH_GPI R_I R_I R_I WP# IH_GPI IH_GPI IH_GPI IH_GPI MI_TERM_SEL LGPI STPPI# STPPU# SPKR MH_IH_SYN#_R IH_TP IH_TP IH_TP IH_TP U G SMLK SMT E LINKLERT#/GPI/LGPI SMLINK SMLINK F R G M E L E M J G H G E K F J L E G F H M J H J J RI# SUS_STT#/LPP# SYS_RESET# PMSYN#/GPI SMLERT#/GPI STP_PI# STP_PU# LKRUN# WKE# SERIRQ THRM# VRMPWRG TP GPI GPI GPI GPI GPI GPI GPI GPI GPI SLK/GPI GPI GPI STLKREQ#/GPI SL/GPI STUT/GPI STUT/GPI GPI GPI/LGPI SPKR MH_SYN# TP TP TP TP IHM REV. SM ST GPI locks SYS GPI Power MGT MIS GPI ontroller Link STGP/GPI STGP/GPI STGP/GPI STGP/GPI LK LK SUSLK SLP_S# SLP_S# SLP_S# S_STTE#/GPI PWRK PRSLPVR/GPI TLW# PWRTN# LN_RST# RSMRST# K_PWRG LPWRK SLP_M# L_LK L_LK L_T L_T L_VREF L_VREF L_RST# L_RST# MEM_LE/GPI GPI/SUS_PWR_K GPI/_PRESENT WL_EN/GPI H F E H F P E G G M R R R F F F R_I R_I IH_GPI IH_GPI M_IH LKUS_ SUSLK SUSR# SUSR# SLP_S# IH_GPI IH_PWRK PM_PRSLPVR_R PM_TLW# NSWN# PM_LN_ENLE_R PM_RSMRST#_R K_PWRG EPWRK SLP_M# L_LK L_LK L_T L_T L_VREF_S L_VREF_S L_RST# L_RST# IH_GPI HPT IH_GPI SWI# M_IH LKUS_ T R _ R _ T T PM_TLW# K_PWRG R _ L_LK L_T L_RST# SUS# SUS# PM_PRSLPVR NSWN# R *_ PM_RSMRST#_R T T T R _ T HPT M ption Table Reference N/ SUS# SUS# PM_PRSLPVR, MPWRK escription N/ L_VREF_S IH_GPI IH_GPI PM_TLW# NSWN# PM_LN_ENLE_R.u/V_ V R R R R R.K/F_ R /F_ K_ K_.K_ K_ R _ L_VREF_S *.u/v_ V RV V R *.K/F_ R */F_ RV R *K_ LGPI R /F_ IH_GPI R *K_ HPT R *K_ V R *K_ MH_IH_SYN#_R SWI# IH_GPI SWI# R R R K_ K_ *K_ V RV ELY_VR_PWRG need PU K to +V. ZS PU at power side(nee HEK PWR KT).u/V_ VR_PWRG_K# VR_PWRG_K#.u/V_ U NSZ VR_PWRG_LKEN R K_,, ELY_VR_PWRG, EPWRK P ELY_VR_PWRG EPWRK R K_ U TSHFU IH_PWRK R K_ PM_RSMRST#_R R *_ Q MMT RSMRST# R K_ RV V R.K_ South ridge Strap Pin (/) oard I Table R_I of TEM always keep low, TE hasn't support TV V V V V V V Pin Name Strap description Sampled onfiguration PU/P GPI SPKR GPI No Reboot MI Termination Voltage PWRK PWRK PWRK = efault = No Reboot mode = for desktop applications = for mobile applications Internal PU SPKR MI_TERM_SEL R R *K_ *K_ V oard I NEW R R US FL Panel LE Panel W/ G-SENSR W/ G-SENSR W/ TV W/ TV W/ HMI W/ HMI I I I I I H L H L H L H L H L R *K_ R_I R *K_ R *K_ R_I R *K_ R *K_ R_I R *K_ R *K_ R_I R *K_ R *K_ R_I R *K_ R.K_ PRJET : P/ Quanta omputer Inc. Size ocument Number Rev S(/) GPI ate: Friday, May, Sheet of

15 M ption Table Reference escription N/ N/ VRT V V VPU VPU V. V. V. V L R R R _ + u/.v_ +.V_ST_IH L u/.v_ +.V_PIE_IH VRT +S_VREF.u/.V_ +VPU_IH_VREF_SUS +.V_PIE_IH +.V_PLL_IH +TP_VSUS IH_ V [] VSUS_[] T +TP_VSUS IH_ V [] VSUS_[] F T u/v_ u/.v_ V [] E +TP_VSUS IH_ T V [] VSUS_[] F V [] G +VSUS INT_IH +.V_ST_IH V [] VSUS_[] F H V [] J V [] +VPU_IH VSUS_[] u/.v_ V [] VSUS_[].u/V_ V [] VSUS_[] E V [] VSUS_[] E F V [] G +.V_ST_IH V [] G V [] VSUS_[] F H V [] J V [] VSUS_[] T u/.v_ VSUS_[] T V [] VSUS_[] T VSUS_[] T +.V_ST_IH V [] VSUS_[] T V [] VSUS_[] T VSUS_[] U V [] VSUS_[] U +VPU_US_IH VSUS_[] V G R _ +.V_US_IH V [] VSUS_[] V G V [] VSUS_[] W VSUS_[] W.u/V_.u/V_ V [] VSUS_[] Y.u/V_ V [] VSUS_[] Y V [] VSUS_[] T R _ /F_ /F_ T T LMPGSN_.u/V_.u/V_.u/V_.u/V_.u/V_ uh_.u/v_ u/.v_.u/v_ +.V_US_IH +VLN INT_IH +VM_VPU +.V_IH_GLNPLL_R +.V_PIE_IH +S_VGLN_ UF VRT VREF E E E E E E F G H H J J K K L L L M M N N N P P R R R R T T T T U U V V U W W K Y Y J J E E VREF_SUS V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] VSTPLL VUSPLL V [] V [] V [] V [] V [] VLN_[] VLN_[] VLN_[] VLN_[] VGLNPLL VGLN_[] VGLN_[] VGLN_[] VGLN_[] VGLN_ VGP R T US RE GLN PWER RE VPSUS VPUS VP_RE PI V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] VMIPLL V_MI[] V_MI[] V_PU_I[] V_PU_I[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] VH VSUSH VL_ VL_ VL_[] VL_[] E F L L L L L L M M P P T T U U V V V V V V R W Y G J F G F G G J J K J J G G +.V_IH +.V_IH_MI +V_MI_IH +V_ST_IH +V_VPRE_IH +V_PI_IH +V_H_I_IH +V_VSUSH +VL INT_IH +VL INT_IH +VM_VL_IH +.V_IH_VMIPLL +.V_IH_I +.V_IH_I +V_H_I_IH *.u/v_.u/v_ *.u/v_.u/v_.u/v_.u/v_.u/v_.u/v_.u/v_.u/v_.u/v_.u/v_.u/v_ u/v_ u/.v_.u/v_.u/v_.u/v_.u/v_.u/v_ heck list:.u for Pin F R _ L uh_ R _ R _ R _ R _ R _ R _.u/v_ R _ R _ R _ R _ R _ VP V. +.V_IH VP V V V V V. RV. RV V UE VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] E VSS[] VSS[] E VSS[] VSS[] E VSS[] VSS[] E VSS[] VSS[] E VSS[] VSS[] E VSS[] VSS[] E VSS[] VSS[] E VSS[] VSS[] E VSS[] VSS[] E VSS[] VSS[] E VSS[] VSS[] E VSS[] VSS[] F VSS[] VSS[] F VSS[] VSS[] F VSS[] VSS[] F VSS[] VSS[] H VSS[] VSS[] F VSS[] VSS[] F VSS[] VSS[] F VSS[] VSS[] F VSS[] VSS[] F VSS[] VSS[] G VSS[] VSS[] G VSS[] VSS[] G VSS[] VSS[] G VSS[] VSS[] G VSS[] VSS[] G VSS[] VSS[] G VSS[] VSS[] G VSS[] VSS[] H VSS[] VSS[] H VSS[] VSS[] H VSS[] VSS[] H VSS[] VSS[] H VSS[] VSS[] H VSS[] VSS[] H VSS[] VSS[] H VSS[] VSS[] H VSS[] VSS[] H VSS[] VSS[] J VSS[] VSS[] J VSS[] VSS[] J VSS[] VSS[] J VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] E VSS[] VSS[] E VSS[] VSS[] E VSS[] VSS[] E VSS[] VSS[] E VSS[] VSS[] E VSS[] VSS[] E VSS[] VSS[] E VSS[] VSS[] F VSS[] VSS[] F VSS[] F VSS[] VSS_NTF[] G VSS[] VSS_NTF[] G VSS[] VSS_NTF[] G VSS[] VSS_NTF[] G VSS[] VSS_NTF[] G VSS[] VSS_NTF[] G VSS[] VSS_NTF[] G VSS[] VSS_NTF[] G VSS[] VSS_NTF[] H VSS[] VSS_NTF[] H VSS[] VSS_NTF[] H VSS[] VSS_NTF[] H VSS[] IHM REV. H J J J K K L L L L L L L M M M M M M M M M N N N N N N N N N N P P P P P P P P P P P P R R R R R R R R R T T T T T T T U U U U U U U U U V V V V V V V V W W W Y Y Y Y Y G H F H H J J J J V. L uh_ IHM REV. u/v_.u/.v_ S Power Status and max current table(/)(s left side) PWER PLNE S S S/S Voltage I(max) Note S Power Status and max current table(/)(s right side) PWER PLNE S S S/S Voltage I(max) Note +.V_PIE_IH VRT +VRT u u@g V_ +.V. VREF +V m VMIPLL +.V m.u/v_ VREF_SUS +V_S m m@s/s/s V_MI +.V m V +.V m V_PU_I +.V m V R _ VSTPLL V +.V +.V m. V_ VH +V +.V m m VUSPLL +.V m VSUSH +.V_S m m@s/s/s VLN_ +.V Powered by Vcc_ in S VSUS_ +.V Powered by Vcc_ in S VLN_ +V m Tied to +V,not +VSUS VSUS_ +.V Powered by Vcc in S VGLNPLL +.V m VGLN_ +.V m VGLN_ +V m VSUS_ +VSUS m VL_ +.V VL_ +.V VL_ +V m Note:VSUS_, VSUS_ are powered by VccSus_ in S/S/S m@s/s/s Powered by Vcc_ in S Powered by Vcc in S Tied to +V,not +VSUS PRJET : P/ Quanta omputer Inc. Size ocument Number Rev S(/) PWER Friday, March, ate: Sheet of

16 R ual channel / PULL UP M ption Table Reference escription N/ N/ RII HNNEL M [..] M [..] M [..], M [..], RII HNNEL SMR_VTERM SMR_VTERM.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_ Place one cap close to every pull-up resistor terminated to SMR_VTERM M M RP SMR_VTERM M M RP M M RP SMR_VTERM M M RP,, M_KE M S# RP, M_KE M RP,, M_T M_S# RP,,, M_KE M S# M S# M M M RP RP RP,,,,, M_T M S# M S# M S# M WE# M RP RP RP,, M_S# M RS# RP M RP SMR_VTERM, M WE#, M S#, M_S# M RP M, M_KE M RP RP, M S# M RP,, M_T M RS# RP M M RP, M_T M RP M M M M RP RP, M_S# M RP M M RP M R _ SMR_VTERM M R _ SMR_VTERM PRJET : P/ Quanta omputer Inc. Size ocument Number Rev R RES. RRV ate: Friday, May, Sheet of

17 M_LK_R# M_LK_R M M_KE RLK_SM RT_SM M Q M Q M Q PM_ETTS# M Q M M M M QS M QS# M M Q M QS# M Q M_T M M M Q M Q M QS M Q M M Q M M M M QS# M M QS M Q M S# M Q M Q M_KE M Q M Q M Q M WE# M Q M M M_S# M M M M M Q M S# M QS# M Q M M M_S# M Q M Q M Q M M Q M Q M QS# M M Q M M Q M Q M Q M QS M Q M Q M QS M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M QS# M QS V M Q M Q M Q M Q M Q M_T M Q M_LK_R M_LK_R# M S# M QS# M QS M QS# M Q M Q M RS# M Q M Q M Q M Q M M M Q M QS M Q M M M Q M M M M M S# RT_SM M Q M Q M Q M Q M M M M Q M WE# M M M Q M S# M M M Q M Q M QS# M QS M QS# M Q M Q M Q M M Q M Q M_KE M S# V M RLK_SM M Q M Q M Q M QS M QS M Q M Q M Q M Q M Q M QS# M QS M Q M Q M Q M QS# M_T M Q M M M QS M QS# M Q M_S# M Q M Q M Q M Q M Q M Q M M M S# M_LK_R# M_LK_R M Q M Q M Q M Q M M Q M M Q M M M Q M QS M Q M M QS# M QS M M M M M QS# M_S# M Q M Q M M QS# M M Q M_T M Q M_LK_R M_LK_R# M S# M Q M RS# M Q M M M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M M QS M M M Q M Q M Q M_KE M M PM_ETTS# M Q M Q M Q M Q M Q M Q M Q M Q M S#, M WE#, M_S#, M S#, M_S#, M S#, M_T, M_T, M_LK_R M_LK_R# M RS#, M_KE, M_KE, M S#, M_LK_R# M_LK_R PM_ETTS# M S#, M WE#, M_S#, M S#, M_T, M_KE, M S#, M M[..] M [..], M QS#[..] M QS[..] M M[..] M [..], M QS#[..] M QS[..] M_S#, M S#, M_T, M_LK_R M_LK_R# M RS#, M_KE, M_LK_R# M_LK_R PM_ETTS# GT_SM GLK_SM M Q[..] M Q[..] M Q[..] M Q[..] M Q[..] M Q[..] M Q[..] M Q[..] M Q[..] M Q[..] M Q[..] M Q[..] M Q[..] M Q[..] M Q[..] M Q[..] SMR_VREF_IMM V.VSUS.VSUS.VSUS SMR_VREF_IMM SMR_VREF SMR_VREF_IMM V.VSUS.VSUS SMR_VREF_IMM V.VSUS V.VSUS.VSUS.VSUS V SMR_VREF_IMM Size ocument Number Rev ate: Sheet of R S-IMM Friday, May, Size ocument Number Rev ate: Sheet of R S-IMM Friday, May, Size ocument Number Rev ate: Sheet of R S-IMM Friday, May, R II IMM Socket N/ Reference escription M ption Table N/ H- SP RESS:?????? H- SP RESS:??????.u/.V_.u/.V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_ R _ R _.u/.v_.u/.v_.u/v_.u/v_.u/v_.u/v_ R K_ R K_ R K_ R K_.u/V_.u/V_ R K_ R K_ VREF VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS M N VSS Q Q VSS KE V N _ V V V /P WE# V S# S# V T VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS Q Q VSS M VSS Q Q VSS Q Q VSS M VSS K K# VSS Q Q VSS VSS Q Q VSS N M VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS KE V V V V RS# S# V T V N VSS Q Q VSS M VSS Q Q VSS Q Q VSS VSS M VSS Q Q VSS Q Q VSS NTEST VSS QS# QS VSS Q Q Q Q VSS M VSS Q Q VSS S SL V(SP) QS# QS VSS Q Q VSS Q Q VSS K K# VSS M VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS S S VSS P R SRM S-IMM (P) N R_.H P R SRM S-IMM (P) N R_.H.u/V_.u/V_ Quanta omputer Inc. PRJET : P/ Quanta omputer Inc. PRJET : P/.u/V_.u/V_.u/.V_.u/.V_.u/.V_.u/.V_ R *K_ R *K_ + u/.v_ + u/.v_.u/.v_.u/.v_ VREF VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS M N VSS Q Q VSS KE V N _ V V V /P WE# V S# S# V T VSS Q Q VSS QS# QS VSS Q Q VSS Q Q VSS Q Q VSS M VSS Q Q VSS Q Q VSS M VSS K K# VSS Q Q VSS VSS Q Q VSS N M VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS KE V V V V RS# S# V T V N VSS Q Q VSS M VSS Q Q VSS Q Q VSS VSS M VSS Q Q VSS Q Q VSS NTEST VSS QS# QS VSS Q Q Q Q VSS M VSS Q Q VSS S SL V(SP) QS# QS VSS Q Q VSS Q Q VSS K K# VSS M VSS Q Q VSS Q Q VSS QS# QS VSS Q Q VSS S S VSS P R SRM S-IMM (P) N R_.H P R SRM S-IMM (P) N R_.H.u/.V_.u/.V_.u/.V_.u/.V_.u/.V_.u/.V_.u/V_.u/V_.u/.V_.u/.V_.u/.V_.u/.V_.u/.V_.u/.V_.u/V_.u/V_.u/.V_.u/.V_.u/V_.u/V_.u/V_.u/V_ R *K_ R *K_ + u/.v_ + u/.v_ R K_ R K_.u/.V_.u/.V_.u/.V_.u/.V_