ZC1 SYSTEM BLOCK DIAGRAM. Yonah/Merom 479 ufcpga

Transcription

1 TVOUT TFT L Panel." WSXG+ X'TL M VI RT luetooth US US P P P P P amera Module(.M) P in ardreader (SMS ) P US US Port x US0~ P VI TVout LVS VG Media-ay O/nd H/nd attery P X'TL.MHZ lock Generator H IS0GLF P VRM X (GR) M/00MHZ P VG TI MP P,P,P0,P, P,P X'TL M P Int MI P ST US.0 Z SYSTEM LOK IGRM PI-Express X Lan Yonah/Merom ufpg G P,P,P,P / MHZ FS LISTOG-PM FG P,P,P,P,P0,P MI X interface IH-M igital Home SMUS G-SENSOR P X'TL.KHZ P,P ual hannel R / Mhz PI-Express PI us interface PU Thermal Sensor P R II SOIMM0 R II SOIMM P,P X'TL.MHZ PMI+ +ardreader ontroller EZ ocking onnector PIE~, Lan Ser & Par Port PS, VG, VI SPIF,SM US P Miniard / WLN EV@: Stuff when external VG used SH@: Stuff when ST H used PH@: Stuff when PT H used P Intel Tekoa GigaLN E P PI-Express X TV out / RT udio VI 0/00/G New ard X'TL M US Switch P Switch P, Switch P MX P,P udio mplifier Maxim Max 0 P zalia udio ontroller Realtek L P zalia X'TL.K LP K P OS MHZ O MP P0,P SPI FLSH P Transformer P RJ P Speaker P MI Jack P Phone Jack P Line in P zalia M RJ P P IOS P Touch Pad (ual-point) P0 P G sensor P Super I/O NS P IEEE Port P P FIR P Smart card P0 TPM. P (Option) PMI Slot P0 Size ocument Number Rev LOK IGRM Fan Header ate: Monday, November 0, 00 Sheet of P Primary attery Secod attery P,P PROJET : Z Quanta omputer Inc. hexainf@hotmail.com

2 E FS FS FS PU SR PI V_ P-0V_ G_XIN efault -change X,X capacitor from pf to pf(l=0pf) U L mils +-0PPM,0PF 0 Y 0 M_REF R _ KHS-T_ P-0V_ X REF0.MHZ M_IH +V V_SR_PU G_XOUT RHLK_PU X PULKT0 LK_PU_LK RHLK_PU# LK_PU_LK# 0 ohms@00mhz 0 +V R *0K_ PULK0 K-0M RP _PR_S *0P_.U-0V_ 0U-0V_, VR_PWRG_K0# 0 RHLK_MH LK_MH_LK.U-0V_.U-0V_.U-0V_ PM_STPPU# Vtt_PwrGd#/P PULKT PM_STPPU# RHLK_MH# LK_MH_LK# PM_STPPI# PU_STOP# PULK PM_STPPI# RP0 _PR_S R0._ V_ PI/PIE_STOP# GLK_SM PULKT/PIET GLK_SM :Remove PIE clock GT_SM SLK PULK/PIE GT_SM.U-0V_ 0U-0V_ R00 _ ST LK_PIE_EZ_L LKUS_ LK_PIE_EZ LK_SEL0 R0.K_ REQ#/PIET 0 LK_PIE_EZ#_L LK_PU_LK LK_PIE_EZ# LK_SEL FS/US_MHz REQ#/PIE RP _PR_S LK_PU_LK# LK_SEL R.K_ FS/TEST_MOE RSR_MH RP._PR_S LK_PIE_GPLL R _ REF/FSL/TEST_SEL PIET RSR_MH# LK_MH_LK SIO_M LK_PIE_GPLL# V_REF PIE RP _PR_S LK_MH_LK# V_SR_PU V_REF 0 LK_PIE_EZ_L RP._PR_S LK_PIE_EZ VPU PIET LK_PIE_EZ#_L LK_PIE_EZ# *0P_ V_PI PIE RP _PR_S V_PI_ 0 LK_PIE_NEW V_PI_ PIET LK_PIE_NEW_ mils LK_PIE_NEW# LK_PIE_LN LK_PIE_NEW_# V_SR_PU PIE RP _PR_S LK_PIE_LN# L V_PI V_PIE RSR_ST +V RP._PR_S LK_PIE_ST KHS-T_ VPIE ST_KT RSR_ST# LK_PIE_GPLL LK_PIE_ST# 0 V_PIE ST_K RP _PR_S LK_PIE_GPLL#.U-0V_.U-0V_ 0U-0V_ V_ RSR_IH RP._PR_S V_ PIET LK_PIE_IH RSR_IH# LK_PIE_ST LK_PIE_IH# LKGN_REQ_PIE PIE RP _PR_S LK_PIE_ST# R0._ V_ LKGN_REQ_PIE REQ(PIE) LK_PIE_LN_L RP._PR_S REQ(PIE) PIET LK_PIE_LN LK_PIE_LN#_L LK_PIE_MINI Iref=m, LK_PIE_LN# R /F_ IREF PIE RP _PR_S LK_PIE_MINI#.U-0V_ 0U-0V_ Ioh=*Iref IREF LK_PIE_MINI_ RP._PR_S PIET LK_PIE_MINI 0 LK_PIE_MINI_# LK_PIE_IH PIE LK_PIE_MINI# RP RP _PR_S LK_PIE_IH# R _ V_REF REFLK R_OT R_REFSSLK REFLK RP._PR_S REFLK# R_OT# OTMHz Mfix/L_SSGT/PIE0T R_REFSSLK# LK_PIE_NEW_ REFLK# OTMHz# SS/L_SSG/PIE0 LK_PIE_NEW_# 00 0 _PR_S R_PLK_SIO R _ RP._PR_S selpiex0_l#/pi PI_LK_SIO.U-0V_ 0U-0V_ R_PLK_ R _ REFLK T PI_LK_ 0 PWRSVE# PI R_PLK_TPM R _ REFLK# INTERNL PULL HIGH PLK_TPM PI PLK_MINI_LP R _ RP0._PR_S PILK/REQ_SEL PLK_MINI R_PLK_IH R _ LK_PIE_EZ PIF/selL_# PLK_IH R_PLK_ R0 _ LK_PIE_EZ# PIF0/ITP_EN PLK_ RP._PR_S IS0GLF LK_PIE_EZ +V R 0K_ LK_PIE_EZ# RP._PR_S ITP/SR SELET *0P_ *0P_ *0P_ LK_PIE_M# LKGN_REQ_PIE R0 0K_ 0 LK_PIE_M NEW_LKREQ# 0: SR : ITP LKGN_REQ_PIE R 0K_ RP._PR_S EZ_LKREQ# *0P_ *0P_ *0P_ :hange pin PLK_LN to PLK_TPM -FS Frequency Select:by PU driven PREQ(PIE) Latched Select "0" : LK Enable "" : LK isable ontrol : PIE,,, PREQ(PIE) Latched Select "0" : LK Enable "" : LK isable ontrol : PIE,,, +.0V R lose to I <00mils R 0_ LK_SEL0 R K_ PU_SEL0 MH_SEL0 R *./F_ *K_ GN GN_ GN GN_PI_ GN_PI_ GN_SR GN V GN Place these termination to close K0M. swap R_REFSSLK# R_REFSSLK RP EV@_PR_S LK_PIE_M# LK_PIE_M GT_SM,,,,, PT_SM R_PLK_IH R0 0K_ +V SELL_# Select. (Pin,) Stuff 0 ohm for MHz, N for MHz "0" : MHzSS/MHzSS# pair R *0K_ "" : L LK pair,,,,, PLK_SM Q RHU00N0 Q RHU00N0 +V +V R 0K_ R 0K_ GLK_SM PU_SEL +.0V +.0V R 0_ LK_SEL R0 K_ PU_SEL MH_SEL R R R R *K_ R 0_ *0_ *K_ *0_ LK_SEL R K_ MH_SEL R_PLK_SIO PLK_MINI_LP R R R R 0K_ *0K_ *0K_ 0K_ +V +V Latched Select. (Pin,) "0" : L LK(UM) "" : PIEX LK(M) Latched Select. (Pin 0,) "0" : PIEX LK "" : PEREQ# Size ocument Number Rev LOK GENERTOR PROJET : Z Quanta omputer Inc. ate: Friday, ecember 0, 00 Sheet of E

3 H_STPLK# XP_RESET# R XP_TMS H_#[:] H_ST0# H_REQ#[:0] H_#[:] H_ST# H_0M# H_FERR# H_IGNNE# R0 0_ H_INTR H_NMI H_SMI# T T T T T0 T0 T T T T T R U H_# J H_# []# L H_# []# M H_# []# K H_# []# M H_# []# N H_# []# J H_#0 []# N H_# [0]# P H_# []# P H_# []# L H_# []# P H_# []# P H_# []# R []# L ST[0]# H_REQ#0 H_REQ# H_REQ# H_REQ# H_REQ# TP_# TP_# TP_# TP_# TP_# TP_# TP_# TP_# TP_PM0# TP_PM# TP_HFPLL +.0V K H K J L H_# Y H_# U H_# R H_#0 W H_# U H_# Y H_# U H_# R H_# T H_# T H_# W H_# W H_# Y H_#0 W H_# Y V REQ[0]# REQ[]# REQ[]# REQ[]# REQ[]# []# []# []# [0]# []# []# []# []# []# []# []# []# []# [0]# []# ST[]# 0M# FERR# IGNNE# H_STPLK_R# STPLK# LINT0 LINT SMI# *./F_./F_ RSV[0]# RSV[0]# RSV[0]# RSV[0]# M RSV[0]# N RSV[0]# T RSV[0]# V RSV[0]# RSV[0]# RSV[0]# RSV[]# R GROUP 0 XP/ITP SIGNLS THERM H LK RESERVE ONTROL PZ-- S# NR# PRI# EFER# RY# SY# R0# H E G H F E F,, ELY_VR_PWRGOO T H_S# H_NR# H_PRI# H_EFER# H_RY# H_SY# H_REQ#0 E:dd Q,remove,R, to resolve System can't boot when battery under 0% issue +.0V +.0V +.0V R./F_ +.0V,,,,,0,,, Near to MH <00mils 0 IERR# H_#[:0] INIT# H_INIT# T U H H_#0 H_LOK# E LOK# H_# [0]# H_PURST# F H_# []# E RESET# H_RS#0 H_# []# F H RS[0]# H_RS# H_# []# F F RS[]# H_RS# H_# []# G H_RS#[:0] G RS[]# H_# []# G H_TRY# E TRY# T H_# []# E H_# []# G H_HIT# K HIT# H_# []# E H_HITM# G HITM# H_#0 []# J T H_# [0 J PM[0]# T0 H_# []# XP PU_R < 0." H PM[]# T H_# []# F PM[]# T H_# []# K PM[]# T H_# []# H PRY# XP_PM# +.0V []# H_STN#0 H PREQ# XP_TK STN[0]# H_STP#0 G TK XP_TI T STP[0]# H_INV#0 J TI XP_TO TO INV[0]# H_#[:0] XP_TMS TMS XP_TRST# R H_#N TRST# 0 XP_RESET# _ H_# []# K R# H_# []# P H_PROHOT_R# R 0_ H_# []# PROHOT H_PROHOT# R H_#0 THERM []# H_THERM L H_# THERM [0]# H_THERM L H_# []# L THERMTRIP#_PWR R 0_ H_# []# THERMTRIP# PM_THRMTRIP#, M :Stuff R0 H_# []# P H_# []# P T H_# []# P +.0V H_# []# LK[0] LK_PU_LK T H_# []# LK[] LK_PU_LK# R H_# []# L T H_#0 []# T T TP_EXTREF T H_# [0]# N RSV[]# R []# H_STN# M K/F_ STN[]# H_STP# N TP_SPRE0 T STP[]# RSV[]# H_INV# M F TP_SPRE T INV[]# RSV[]# TP_SPRE T H_GTLREF RSV[]# TP_SPRE T :Intel WW,suggest Stuff R(S00F) GTLREF MIS RSV[]# F TP_SPRE T0 RSV[]# TP_SPRE T R K/F_ RSV[]# TP_SPRE T 0/mils TEST RSV[]# TP_SPRE T R _ RSV[0]# R TEST K/F_ PU_SEL0 SEL[0] PU_SEL SEL[] PU_SEL SEL[] :Intel 00 WW update T GRP 0 T GRP PZ-- +.0V T GRP T GRP []# []# []# []# []# []# []# []# [0]# []# []# []# []# []# []# []# STN[]# STP[]# INV[]# []# []# [0]# []# []# []# []# []# []# []# []# []# [0]# []# []# []# STN[]# STP[]# INV[]# OMP[0] OMP[] OMP[] OMP[] PRSTP# PSLP# PWR# PWRGOO SLP# PSI# H_# H_# V H_# V H_# W H_# U H_# U H_# U H_# H_#0 W H_# Y H_# H_# Y H_# Y H_# H_# H_# W Y V H_# H_# H_#0 H_# H_# H_# 0 H_# E H_# F H_# H_# E H_# H_# E H_#0 F H_# F H_# F H_# E 0 R OMP0./F_ U OMP./F_ U OMP./F_ V OMP./F_ T E E IH_PRSTP# H_PSLP# H_#[:0] H_STN# H_STP# H_INV# H_#[:0] H_STN# H_STP# H_INV# H_PUSLP#, PSI# TO VR R R R0 R0 /mils T0 +.0V R *00/F_ H_PWR# H_PWRG H_PWRG is MOS driving by IH XP_TI R0./F_ +.0V R *0_ XP_PM# XP_TK XP_TRST# R0 R R./F_./F_./F_ XP_TK P./%? XP_TRST P 0ohm /%? XP_TI PU 0ohm /.0V XP_TMS PU./%? XP_TO PU.ohm? For ITP00 THERMTRIP#_PWR R _ R 0_ Q SS0 Q MMT0 *S R *0K_ XP_RESET# *U-V SHT# Q0 *MMT0 R 0_ SYS_RST# Size ocument Number Rev PU( OF ) PROJET : Z Quanta omputer Inc. ate: Sunday, ecember 0, 00 Sheet of hexainf@hotmail.com

4 +.0V V_ORE +.V H_VI0 H_VI H_VI H_VI H_VI H_VI H_VI VSENSE SENSE +.0V,,,,,0,,, V_ORE +.V,0,,,,,, V_ORE V_ORE +.0V V_ORE +.V +.V +.0V V_ORE V_ORE Size ocument Number Rev ate: Sheet of PU( OF ) Monday, November, 00 Size ocument Number Rev ate: Sheet of PU( OF ) Monday, November, 00 Size ocument Number Rev ate: Sheet of PU( OF ) Monday, November, 00 change to 00 :Reversed VSENSE/SENSE on Vcore side V (.v) is a power source required by the PLL clock near PU U-.V_ U-.V_ U-.V_ U-.V_ U-.V_ U-.V_.U-0V_.U-0V_ 0.U-0V_ 0.U-0V_ [00] [00] [00] [00] [00] [00] [00] [00] [00] [00] [0] [0] [0] [0] [0] [0] [0] [0] [0] [00] [0] [0] [0] [0] [0] [0] [0] [0] [0] [00] [0] [0] [0] [0] [0] E [0] E [0] E [0] E [0] E [00] E [0] E [0] E [0] E [0] F [0] F [0] F [0] F [0] F [0] F [00] F [0] F [0] F [0] G [0] G [0] G [0] G [0] H [0] H [0] H [00] H [0] J [0] J [0] J [0] J [0] K [0] K [0] K [0] K [0] L [00] L [0] L [0] L [0] M [0] M [0] M [0] M [0] N [0] N [0] N [00] N [0] P [0] P [0] P [0] P [0] R [0] R [0] R [0] R [0] T [00] T [0] T [0] T [0] U [0] U [0] U [0] U [0] V [0] V [0] V [00] V [0] W [0] W [0] W [0] W [0] Y [0] Y [0] Y [0] Y [0] [0] [] [] [] [] [] [] [] [] [] [0] [] [] [] [] [] [] [] [] [] [0] [] [] [] [] [] [] [] [] [] [0] [] [] [] [] [] E [] E [] E [] E [] E [0] E [] E [] E [] E [] F [] F [] F [] F [] F [] F [0] F [] F [] F U PZ-- U PZ-- U-.V_ U-.V_ U-.V_ U-.V_ U-.V_ U-.V_ 0 U-.V_ 0 U-.V_.0U-V_.0U-V_ 0 U-.V_ 0 U-.V_ U-.V_ U-.V_ 0 U-.V_ 0 U-.V_.U-0V_.U-0V_ 0 U-.V_ 0 U-.V_ 0 U-.V_ 0 U-.V_ U-.V_ U-.V_ 0 U-.V_ 0 U-.V_ U-.V_ U-.V_ R0 *00/F_ R0 *00/F_ U-.V_ U-.V_ V[00] V[00] V[00] 0 V[00] V[00] V[00] V[00] V[00] V[00] 0 V[00] V[0] V[0] 0 V[0] V[0] V[0] V[0] V[0] V[0] 0 V[0] V[00] 0 V[0] V[0] V[0] V[0] V[0] V[0] V[0] 0 V[0] V[0] V[00] V[0] V[0] V[0] E V[0] E V[0] E0 V[0] E V[0] E V[0] E V[0] E V[00] E V[0] E0 V[0] F V[0] F V[0] F0 V[0] F V[0] F V[0] F V[0] F V[0] F V[00] F0 V[0] V[0] V[0] 0 V[0] V[0] V[0] V[0] V[0] V[0] 0 V[00] V[0] 0 V[0] 0 V[0] V[0] V[0] V[0] V[0] V[] 0 V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] 0 V[0] V[] V[] V[] V[] V[] E V[] E0 V[] E V[] E V[] E V[0] E V[] E V[] E0 V[] F V[] F0 V[] F V[] F V[] F V[] F V[] F V[00] F0 VP[0] V VP[0] G VP[0] J VP[0] K VP[0] M VP[0] J VP[0] K VP[0] M VP[0] N VP[0] N VP[] R VP[] R VP[] T VP[] T VP[] V VP[] W V VI[0] VI[] F VI[] E VI[] F VI[] E VI[] F VI[] E VSENSE F SENSE E U PZ-- U PZ-- U-.V_ U-.V_ U-.V_ U-.V_ 0 U-.V_ 0 U-.V_ U-.V_ U-.V_ U-.V_ U-.V_ 00 U-.V_ 00 U-.V_ U-.V_ U-.V_ U-.V_ U-.V_ U-.V_ U-.V_ U-.V_ U-.V_ + 0U-.V_ + 0U-.V_ U-.V_ U-.V_ U-.V_ U-.V_ 0 U-.V_ 0 U-.V_ U-.V_ U-.V_ U-.V_ U-.V_ U-.V_ U-.V_ Quanta omputer Inc. PROJET : Z Quanta omputer Inc. PROJET : Z.U-0V_.U-0V_ 0.U-0V_ 0.U-0V_.U-0V_.U-0V_ U-.V_ U-.V_ U-.V_ U-.V_ 0U/XR-.V_ 0U/XR-.V_ U-.V_ U-.V_ R *00/F_ R *00/F_ 0 U-.V_ 0 U-.V_

5 +V +V,, MLK Q RHU00N0 R 00_ LMV mils +V R 0K_ R 0K_ U.U-0V_,, MT Q RHU00N0 LM SM LM_SM THERM_LERT# R0 *0_ THERM_OVER# +V R 0K_ :dd R for PU thermal sensor SLK V S XP LERT# XN OVERT# GN MX/GMT- RESS: H H_THERM 0 00P-0V_ H_THERM 0/0mils H_THERM H_THERM :dd R for VG thermal sensor +V PU FN VG_THERM# THERM_OVER# +V PUFN# R 0_ R 0_ R0 G_VEN *0_ G_VEN U VIN VO GN FON# GN GN VSET GN GPU Q *O0 THERM_OVER# FNSIG TH_FN_POWER 0 MIL R 0K_.0U-V_ *.0U-V_ +V R 0K_ N FN_ON :hange FN ONN footprint :hange FN driver to G :Remove FNSIG capacitor F:dd R, to prevent FN noise Size ocument Number Rev Thermal Sensor,FN PROJET : Z Quanta omputer Inc. ate: Friday, ecember 0, 00 Sheet of hexainf@hotmail.com

6 +.0V +.0V +.0V +.0V H_XROMP R0./F_ R./F_ H_XSOMP R /F_ R 00/F_ R./F_ H_XSWING H_YSOMP R /F_ R 00/F_ H_YSWING 0 mils/0mils.u-0v_ 0 mils/0mils 0 mils/0mils 0 mils/0mils H_YROMP R./F_.U-0V_ H_#[:0] H_XROMP H_XSOMP H_XSWING H_YROMP H_YSOMP H_YSWING LK_MH_LK LK_MH_LK# T T H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# Short Stub < 00mils extract from same point U F H_#_0 J H_#_ H H_#_ J H_#_ H H_#_ K H_#_ G H_#_ G H_#_ K H_#_ K H_#_ K H_#_0 J H_#_ H H_#_ J H_#_ K H_#_ G H_#_ T0 H_#_ W H_#_ T H_#_ U H_#_ U H_#_0 U H_#_ T H_#_ W H_#_ T H_#_ T H_#_ T H_#_ W H_#_ U H_#_ T H_#_ W H_#_0 T H_#_ H_#_ H_#_ W H_#_ W H_#_ Y H_#_ Y H_#_ W H_#_ Y0 H_#_ H_#_0 W H_#_ H_#_ H_#_ H_#_ H_#_ 0 H_#_ Y H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 0 H_#_ H_#_ H_#_ E E E Y U W G G H_XROMP H_XSOMP H_XSWING H_YROMP H_YSOMP H_YSWING H_LKIN H_LKIN# alistoga(pm) HOST H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_S# H_ST#_0 H_ST#_ H_VREF_0 H_NR# H_PRI# H_REQ#0 H_PURST# H_SY# H_EFER# H_PWR# H_RY# H_VREF_ H_INV#_0 H_INV#_ H_INV#_ H_INV#_ H_STN#_0 H_STN#_ H_STN#_ H_STN#_ H_STP#_0 H_STP#_ H_STP#_ H_STP#_ H_HIT# H_HITM# H_LOK# H_REQ#_0 H_REQ#_ H_REQ#_ H_REQ#_ H_REQ#_ H_RS#_0 H_RS#_ H_RS#_ H_SLPPU# H_TRY# H E G F G F H J G J H J F E G F E J F J H K J W U 0 K T Y K T G F E E E H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# R 0_ H_INV#0 H_INV# H_INV# H_INV# H_STN#0 H_STN# H_STN# H_STN# H_STP#0 H_STP# H_STP# H_STP# H_REQ#0 H_REQ# H_REQ# H_REQ# H_REQ# H_RS#0 H_RS# H_RS# H_#[:] H_S# H_ST0# H_ST# H_NR# H_PRI# H_REQ#0 H_PURST# H_SY# H_EFER# H_PWR# H_RY# H_INV#[:0] H_STN#[:0] H_STP#[:0] H_HIT# H_HITM# H_LOK# H_REQ#[:0] H_RS#[:0] H_PUSLP#, H_TRY# +.0V.U-0V_.U-0V_ +.0V R 00/F_ R 00/F_ +.0V,,,,,0,,, H_VREF H_VREF H_VREF :0 mils/0 mils space Place within 00 mils PROJET : Z Quanta omputer Inc. Size ocument Number Rev GMH HOST( OF ) ate: Friday, ecember 0, 00 Sheet of

7 M Q[:0] M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q U J S_Q0 J S_Q M S_Q M S_Q J S_Q K S_Q J S_Q H S_Q N S_Q P S_Q R S_Q0 P S_Q N S_Q M S_Q M S_Q N S_Q K S_Q L S_Q M S_Q N S_Q K S_Q0 L S_Q M S_Q P S_Q P S_Q L S_Q P S_Q N0 S_Q L S_Q P S_Q P0 S_Q0 T S_Q R S_Q R S_Q P S_Q P S_Q T S_Q T S_Q L S_Q L S_Q K S_Q0 N S_Q K S_Q K S_Q P S_Q N S_Q T S_Q L S_Q Y S_Q W S_Q P S_Q0 N S_Q V S_Q T S_Q N S_Q L S_Q G S_Q F S_Q G S_Q F S_Q G S_Q0 H S_Q F S_Q F S_Q alistoga(pm) R SYSTEM MEMORY S_S_0 S_S_ S_S_ S_S# S_M_0 S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_QS_0 S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS#_0 S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_M_0 S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_0 S_M_ S_M_ S_M_ S_RS# S_RVENIN# S_RVENOUT# S_WE# U V 0 Y J M L N M L R H K T N M N N P G K U N M M L N H Y U W U V U W T U T V0 V W K K Y M S#0 M S# M S# M S# M M0 M M M M M M M M M M M M M M M QS0 M QS M QS M QS M QS M QS M QS M QS M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M 0 M M M M M M M M M M 0 M M M TP_M_RVENIN# TP_M_RVENOUT# T T M Q[:0] M S#0, M S#, M S#, M S#, M M[:0] M QS[:0] M QS#[:0] M [:0], M RS#, M WE#, M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q UE K S_Q0 J S_Q P S_Q R S_Q J S_Q K S_Q N S_Q P S_Q T0 S_Q V S_Q U S_Q0 V S_Q P S_Q R0 S_Q W S_Q Y S_Q S_Q V S_Q R S_Q P S_Q S_Q0 U S_Q P S_Q P S_Q Y S_Q S_Q T S_Q U S_Q U S_Q W S_Q V S_Q0 W S_Q M S_Q L S_Q P S_Q N S_Q N S_Q M S_Q P S_Q L S_Q J S_Q0 H0 S_Q J S_Q N0 S_Q K S_Q H S_Q K0 S_Q J S_Q 0 S_Q W0 S_Q S_Q0 W S_Q Y0 S_Q Y S_Q W S_Q Y S_Q V S_Q R S_Q K S_Q K S_Q T S_Q0 K S_Q J S_Q J S_Q alistoga(pm) R SYSTEM MEMORY S_S_0 S_S_ S_S_ S_S# S_M_0 S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_QS_0 S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS#_0 S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_M_0 S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_0 S_M_ S_M_ S_M_ S_RS# S_RVENIN# S_RVENOUT# S_WE# T V Y R K R T L H N M T U R R R0 R N M0 U T P P T0 T P Y W Y R T T U V V W V Y R U K K R M M0 M M M M M M M M M M M M M M M QS0 M QS M QS M QS M QS M QS M QS M QS M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M 0 M M M M M M M M M M 0 M M M TP_M_RVENIN# TP_M_RVENOUT# M S#0, M S#, M S#, M S#, M M[:0] M QS[:0] M QS#[:0] M [:0], M RS#, T T M WE#, Size ocument Number Rev GMH R( OF ) PROJET : Z Quanta omputer Inc. ate: Friday, ecember 0, 00 Sheet of hexainf@hotmail.com

8 MH_SEL0 MH_SEL MH_SEL T :hange PM_EXTTS# to PRSLPVR PM_MUSY# PM_EXTTS#0 PRSLPVR, PM_THRMTRIP#,, ELY_VR_PWRGOO PLT_RST-R# R +V +.V +.V T T T T T T T T T T0 T T T T T T T T MH_IH_SYN R R T T T0 T T T T T T T0 T T T T T T0 T T T T T LK_MH_OE# MH_RSV_ MH_RSV_ MH_RSV_ MH_RSV_ MH_RSV_ MH_RSV_ MH_RSV_ MH_RSV_ TV_ONSEL0 TV_ONSEL MH_RSV_ MH_RSV_ MH_RSV_ MH_RSV_ MH_RSV_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_0 MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_0 SVO_TRLLK SVO_TRLT :Reversed for SVO LK/T R R T T T0 TP_MH_N0 TP_MH_N TP_MH_N TP_MH_N TP_MH_N 0 TP_MH_N TP_MH_N TP_MH_N TP_MH_N TP_MH_N TP_MH_N0 TP_MH_N Y TP_MH_N Y TP_MH_N W TP_MH_N W TP_MH_N 0 TP_MH_N TP_MH_N TP_MH_N 0K/F_ PM_EXTTS#0 alistoga(pm) *0K/F_ PRSLPVR :don't stuff PM_EXTTS# pull high resistor *.K_SVO_TRLLK *.K_SVO_TRLT U H RSV_0 T RSV_ R RSV_ F RSV_ F RSV_ G RSV_ F RSV_ H RSV_ J RSV_ K0 RSV_ J RSV_0 RSV_ RSV_ RSV_ RSV_ RSV_ K FG_0 K FG_ J FG_ F FG_ E FG_ F FG_ E FG_ FG_ FG_ G FG_ E FG_0 FG_ G FG_ K FG_ FG_ H FG_ G FG_ H FG_ J FG_ K FG_ J FG_0 G PM_MUSY# F R 0_ PM_EXTTS#_0 H PM_EXTTS#_ G PM_THRMTRIP# H RST IN# MH PWROK H 00/F_ RSTIN# H SVO_TRLLK H SVO_TRLT K LT_RESET# N0 N N N N N N N N N N0 N N N N N N N N RSV FG PM MIS N PULL LOW FOR VO NOT PRESENT(INTERNL PULLLOW IN GM).MH_FG_ Low = MI X, High=MIX.MH_FG_ R : Low =Moby ick, High= alistoga (efault).mh_fg_ PU Strap Low=RSV, High=Mobile PU.MH_FG_ PI Exp Graphics Lane: Low =Reserved,High=Mobility.MH_FG_0 Host PLL V Select: Low=Reserved, High=Mobility.MH_FG_: PS x LK ENLE Low=Reserved, High=alistoga.MH_FG_ FS ynmic OT: Low=ynamic OT isabled, High=ynamic OT Enabled. R MUXING LK MI.MH_FG_ V Select: LOW=.0V, High=.V.MH_FG_ MI LNE Reversal: Low=Normal,High=LNES Reversed. 0.MH_FG_0 PIE ackward interpoerability mode: Low= only SVO or PIE x is operational (defaults),high=svo and PIE x are operation simultaneously via the PEG port. Y SM_K_0 R SM_K_ W SM_K_ W0 SM_K_ W SM_K#_0 T SM_K#_ Y SM_K#_ Y0 SM_K#_ U0 SM_KE_0 T0 SM_KE_ SM_KE_ Y SM_KE_ W SM_S#_0 W SM_S#_ Y SM_S#_ W SM_S#_ L0 SM_OOMP_0 F0 SM_OOMP_ SM_OT_0 SM_OT_ Y0 SM_OT_ U SM_OT_ SM_ROMP# V SM_ROMP T MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_0 MH_FG_ MH_FG_ MH_FG_ MH_FG_0 M_OOMP_0 M_OOMP_ M_ROMP# M_ROMP F G_LKIN# G_LKIN G _REFLKIN# _REFLKIN 0 REFSSLK# _REFSSLKIN# REFSSLK _REFSSLKIN E MI_TXN0 MI_RXN_0 F MI_TXN MI_RXN_ G MI_TXN MI_RXN_ H MI_TXN MI_RXN_ MI_TXP0 MI_RXP_0 E MI_TXP MI_RXP_ F MI_TXP MI_RXP_ G MI_TXP MI_RXP_ E MI_RXN0 MI_TXN_0 F MI_RXN MI_TXN_ G MI_RXN MI_TXN_ H MI_RXN MI_TXN_ MI_RXP0 MI_TXP_0 E MI_RXP MI_TXP_ F MI_RXP MI_TXP_ G MI_RXP MI_TXP_ +V._PIE +V SMR_VREF +.VSUS :MH_FG_->intel WW recommand remove MH_FG_ R *.K_ :intel WW recommand remove MH_FG_ MH_FG_ M_LK_R0 M_LK_R M_LK_R M_LK_R M_LK_R#0 M_LK_R# M_LK_R# M_LK_R# M_KE0, M_KE, M_KE, M_KE, M_S#0, M_S#, M_S#, M_S#, M_OT0, M_OT, M_OT, *0./F_ M_OT, LK_PIE_GPLL# LK_PIE_GPLL REFLK# REFLK T T MI_TXN[:0] MI_TXP[:0] MI_RXN[:0] MI_RXP[:0] < 0.". mils/mils space use % R GMH Strap pin R R R R R0 R *.K_ *.K_ *.K_ *.K_ mils/mils Layout as short as passable N from WW K/F_ FG_RSV_0_R *K/F_ +V +V R +V +V._PIE 0 +V,,0,,,,,,,,0,,,,,,0,,,,,,,,,,0,,, SMR_VREF, +.VSUS,,0,, If the LVS interface is not implemented, all signals associated with the interface can be left as No onnects R *0./F_ K SMR_VREF_MH R 0_ SM_VREF_0 SMR_VREF K SM_VREF_ mils/0mils R R0 R R R *.K_ *.K_ *.K_ *.K_ *K/F_ M_ROMP# M_ROMP +.VSUS +.V :TV disable connect to +.V :RT disable connect to GMH V ore R *0_ R 0./F_ R 0./F_ +.0V R 0_ R 0_ U L_KLTTL J0 L_KLTEN H0 L_LKTL H L_LKTL G L LK G L T L_IG L_VG F L_VEN L_VREFH L_VREFL L_LK# L_LK E L_LK# E L_LK L_T#_0 L_T#_ L_T#_ L_T_0 L_T_ L_T_ G0 L_T#_0 0 L_T#_ F L_T#_ F0 L_T_0 L_T_ F L_T_ TV OUT TV OUT TV OUT J0 TV_IREF TV_IRTN TV_IRTN TV_IRTN E RT_LUE RT_LUE# RT_GREEN RT_GREEN# RT_RE RT_RE# RT LK RT T G RT_HSYN J RT_IREF H RT_VSYN alistoga(pm) LVS TV VG PI-EXPRESS GRPHIS PEG_TXP0 PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP0 PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP 0mils/0mils space EXP OMPI 0 EXP OMPX EXP OMPO PEG_RXN0 EXP RXN_0 F PEG_RXN EXP RXN_ G PEG_RXN EXP RXN_ H PEG_RXN EXP RXN_ J PEG_RXN EXP RXN_ L PEG_RXN EXP RXN_ M PEG_RXN EXP RXN_ N PEG_RXN EXP RXN_ P PEG_RXN EXP RXN_ R PEG_RXN EXP RXN_ T PEG_RXN0 EXP RXN_0 V PEG_RXN EXP RXN_ W PEG_RXN EXP RXN_ Y PEG_RXN EXP RXN_ PEG_RXN EXP RXN_ PEG_RXN EXP RXN_ PEG_RXP0 EXP RXP_0 PEG_RXP EXP RXP_ F PEG_RXP EXP RXP_ G PEG_RXP EXP RXP_ H PEG_RXP EXP RXP_ J PEG_RXP EXP RXP_ L PEG_RXP EXP RXP_ M PEG_RXP EXP RXP_ N PEG_RXP EXP RXP_ P PEG_RXP EXP RXP_ R PEG_RXP0 EXP RXP_0 T PEG_RXP EXP RXP_ V PEG_RXP EXP RXP_ W PEG_RXP EXP RXP_ Y PEG_RXP EXP RXP_ PEG_RXP EXP RXP_ F _PEG_TXN0 EXP TXN_0 G0 _PEG_TXN EXP TXN_ H _PEG_TXN EXP TXN_ J0 _PEG_TXN EXP TXN_ L _PEG_TXN EXP TXN_ M0 _PEG_TXN EXP TXN_ N _PEG_TXN EXP TXN_ P0 _PEG_TXN EXP TXN_ R _PEG_TXN EXP TXN_ T0 _PEG_TXN EXP TXN_ V _PEG_TXN0 EXP TXN_0 W0 _PEG_TXN EXP TXN_ Y _PEG_TXN EXP TXN_ 0 _PEG_TXN EXP TXN PEG_TXN EXP TXN_ 0 _PEG_TXN EXP TXN PEG_TXP0 EXP TXP_0 F0 _PEG_TXP EXP TXP_ G _PEG_TXP EXP TXP_ H0 _PEG_TXP EXP TXP_ J _PEG_TXP EXP TXP_ L0 _PEG_TXP EXP TXP_ M _PEG_TXP EXP TXP_ N0 _PEG_TXP EXP TXP_ P _PEG_TXP 0 EXP TXP_ R0 _PEG_TXP EXP TXP_ T _PEG_TXP0 EXP TXP_0 V0 _PEG_TXP EXP TXP_ W _PEG_TXP EXP TXP_ Y0 _PEG_TXP 0 EXP TXP PEG_TXP EXP TXP_ 0 _PEG_TXP EXP TXP_ PEG_TXP[:0] PEG_TXN0 PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN0 PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN R PEG_RXN[:0] PEG_RXP[:0] EV@.U-0V_PEG_TXN0 EV@.U-0V_PEG_TXN EV@.U-0V_PEG_TXN EV@.U-0V_PEG_TXN EV@.U-0V_PEG_TXN EV@.U-0V_PEG_TXN EV@.U-0V_PEG_TXN EV@.U-0V_PEG_TXN EV@.U-0V_PEG_TXN EV@.U-0V_PEG_TXN EV@.U-0V_PEG_TXN0 EV@.U-0V_PEG_TXN EV@.U-0V_PEG_TXN EV@.U-0V_PEG_TXN EV@.U-0V_PEG_TXN EV@.U-0V_PEG_TXN EV@.U-0V_PEG_TXP0 EV@.U-0V_PEG_TXP EV@.U-0V_PEG_TXP EV@.U-0V_PEG_TXP EV@.U-0V_PEG_TXP EV@.U-0V_PEG_TXP EV@.U-0V_PEG_TXP EV@.U-0V_PEG_TXP EV@.U-0V_PEG_TXP EV@.U-0V_PEG_TXP EV@.U-0V_PEG_TXP0 EV@.U-0V_PEG_TXP EV@.U-0V_PEG_TXP EV@.U-0V_PEG_TXP EV@.U-0V_PEG_TXP EV@.U-0V_PEG_TXP PEG_TXN[:0] +V._PIE If not implemented, the SVO interface signals can be left as No onnect. PROJET : Z./F_ Quanta omputer Inc. Size ocument Number Rev GMH MI/VEIO( OF ) ate: Tuesday, ecember 0, 00 Sheet of

9 +.0V +.VSUS +.V_UX V_SM0 V_SM0 V_SM V_SM +.0V,,,,,0,,, +.VSUS,,0,, +.V_UX 0 +.V_UX +.VSUS +.0V +.0V Size ocument Number Rev ate: Sheet of GMH PW & STRP( OF ) Friday, ecember 0, 00 Size ocument Number Rev ate: Sheet of GMH PW & STRP( OF ) Friday, ecember 0, 00 Size ocument Number Rev ate: Sheet of GMH PW & STRP( OF ) Friday, ecember 0, 00 mils mils mils 0mils 00mils 00m R. V, MTs( hannel) 00m.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_ Quanta omputer Inc. PROJET : Z Quanta omputer Inc. PROJET : Z.U-0V_.U-0V_ 0 U-V_ 0 U-V_ + 0U-.V_ + 0U-.V_.U-0V_.U-0V_ 0U/XR-.V_ 0U/XR-.V_ + 0U-.V_ + 0U-.V_.U-0V_.U-0V_ + 0U-.V_ + 0U-.V_.U-0V_.U-0V_ 0U/XR-.V_ 0U/XR-.V_.U-0V_.U-0V_ V_0 V_ W V_ P V_ N V_ L V_ J V_ V_ Y V_ W V_ V V_0 P V_ N V_ M V_ L V_ J V_ V_ W V_ V V_ T V_ R V_0 P V_ N V_ M V_ 0 V_ Y0 V_ W0 V_ V0 V_ U0 V_ T0 V_ R0 V_0 P0 V_ N0 V_ M0 V_ L0 V_ V_ Y V_ W V_ V V_ U V_ R V_0 P V_ M V_ L V_ V_ V_ Y V_ V V_ U V_ T V_ R V_0 P V_ N V_ M V_ L V_ P V_ N V_ M V_ L V_ P V_ N V_0 L V_ N V_ M V_ L V_ P V_ N V_ M V_ V_ V_ Y V_0 P V_ N V_ M V_ L V_ V_ V_ Y V_ W V_ P V_ N V_0 M V_ L V_ V_ V_ W V_ N V_ M V_ L V_ 0 V_ 0 V_0 Y0 V_ W0 V_ P0 V_ N0 V_ M0 V_ L0 V_ V_ V_ Y V_ N V_00 M V_0 L V_0 N V_0 M V_SM_0 U V_SM_ T V_SM_ M V_SM_ U0 V_SM_ V_SM_ Y V_SM_ W V_SM_ V V_SM_ U V_SM_ T V_SM_0 R V_SM_ 0 V_SM_ Y0 V_SM_ W0 V_SM_ V0 V_SM_ U0 V_SM_ T0 V_SM_ R0 V_SM_ P0 V_SM_ N0 V_SM_0 M0 V_SM_ M V_SM_ L V_SM_ K V_SM_ J V_SM_ H V_SM_ J V_SM_ H V_SM_ J V_SM_ H V_SM_0 V_SM_ Y V_SM_ W V_SM_ V V_SM_ U V_SM_ T V_SM_ R V_SM_ J V_SM_ H V_SM_ J V_SM_0 H V_SM_ J V_SM_ H V_SM_ V_SM_ J V_SM_ V_SM_ Y V_SM_ W V_SM_ V V_SM_ U V_SM_0 T V_SM_ R V_SM_ P V_SM_ K V_SM_ J V_SM_ K V_SM_ K0 V_SM_ V_SM_ Y V_SM_ W V_SM_0 V V_SM_ U V_SM_ T V_SM_ R V_SM_ P V_SM_ K V_SM_ J V_SM_ J V_SM_ J V_SM_ H V_SM_0 J V_SM_ H V_SM_ V_SM_ Y V_SM_ W V_SM_ V V_SM_ U V_SM_ T V_SM_ R V_SM_ J V_SM_0 J V_SM_ J V_SM_ H V_SM_ K V_SM_ J V_SM_ H V_SM_ G V_SM_ K V_SM_ V_SM_ Y V_SM_0 W V_SM_ V V_SM_ T V_SM_ R V_SM_ P V_SM_ V_SM_ Y V_SM_ W V_SM_ V V_SM_ T V_SM_00 R V_SM_0 P V_SM_0 N V_SM_0 L V_SM_0 K V_SM_0 J V_SM_0 V V_SM_0 J V_0 L V_0 P V_0 N V_0 M V_0 N V_0 M V_0 L V UG alistoga(pm) V UG alistoga(pm).u-0v_.u-0v_.u-0v_.u-0v_ 0U/XR-.V_ 0U/XR-.V_ 0U/XR-.V_ 0U/XR-.V_ 0.U-0V_ 0.U-0V_.U-0V_.U-0V_ V_NTF0 V_NTF V_NTF V_NTF V_NTF Y V_NTF W V_NTF V V_NTF U V_NTF T V_NTF R V_NTF0 V_NTF V_NTF V_NTF V_NTF Y V_NTF W V_NTF V V_NTF U V_NTF T V_NTF R V_NTF0 V_NTF V_NTF V_NTF V_NTF Y V_NTF W V_NTF V V_NTF U V_NTF T V_NTF R V_NTF0 V_NTF V_NTF V_NTF V_NTF Y V_NTF W V_NTF V V_NTF U V_NTF T V_NTF R V_NTF0 V_NTF V V_NTF U V_NTF T V_NTF R V_NTF V_NTF V V_NTF U V_NTF T V_NTF R V_NTF0 V_NTF V V_NTF U V_NTF T V_NTF R V_NTF 0 V_NTF V0 V_NTF U0 V_NTF T0 V_NTF R0 V_NTF0 V_NTF V V_NTF U V_NTF T V_NTF V_NTF V_NTF V_NTF V_NTF Y V_NTF W V_NTF0 V V_NTF U V_NTF T _NTF0 E _NTF E _NTF E _NTF E _NTF E _NTF E _NTF E _NTF E0 _NTF E _NTF E _NTF0 _NTF Y _NTF U VUX_NTF R VUX_NTF G VUX_NTF0 F VUX_NTF R VUX_NTF G VUX_NTF F VUX_NTF E VUX_NTF VUX_NTF VUX_NTF VUX_NTF W VUX_NTF V VUX_NTF0 T VUX_NTF R VUX_NTF G VUX_NTF F VUX_NTF E VUX_NTF VUX_NTF VUX_NTF VUX_NTF VUX_NTF Y VUX_NTF0 W VUX_NTF V VUX_NTF U VUX_NTF T VUX_NTF R VUX_NTF G VUX_NTF F VUX_NTF E VUX_NTF VUX_NTF VUX_NTF0 VUX_NTF0 G VUX_NTF F VUX_NTF G VUX_NTF F VUX_NTF G VUX_NTF F VUX_NTF G VUX_NTF F VUX_NTF G VUX_NTF F VUX_NTF0 G VUX_NTF F VUX_NTF G VUX_NTF F VUX_NTF G0 VUX_NTF F0 VUX_NTF G VUX_NTF F VUX_NTF VUX_NTF Y VUX_NTF W VUX_NTF V VUX_NTF U VUX_NTF T VUX_NTF R NTF UF alistoga(pm) NTF UF alistoga(pm).u-0v_.u-0v_ 0.U-0V_ 0.U-0V_ hexainf@hotmail.com

10 +.V L L L0 L +V._PIE +V._GPLL +.0V +.V +V._PIE +.V +V 0uH_ 0uH_ +.V_UX +V._TV nh_0%_. 0mils GPLL_F_R +V._PLL + 0.U-0V_ 0U-.V_ +V._PLL +.U-0V_ 0U-.V_ K0LL_ +V._HPLL 0.U-0V_ U-.V_ K0LL_ +V._MPLL 0mils V_SFOLLOW :hange to 0UF :hange to 0UF :hange to UF :hange to UF :hange L0 to VMN0(NH+-0%.),footprint Lx U-.V_ 0U/XR-.V_ 0U/XR-.V_ R 0./F_ U-.V_.U-0V_ R 0_.U-0V_ 0mils L0 nh_lx- PIE_L +.V 0mils GPLL_F_L :Remove R for +.V_UX R *0_ R L uh_ :Remove +V._TV *PZ. *0_ +.V R00 0_ R 0_ +.V +.V +.0V,,,,,,,, +.V,,,,,,, +V._PIE +.V,,0,, +V,,,,,,,,,,0,,,,,,0,,,,,,,,,,0,,, +V When the LVS interface is not implemented, the VTX_LVS, V_LVS, and V_LVS signals of the interface can be connected to ground +.0V :RT disable +.V +V._TV +V._QTV R 0_ 0mils R 0_ :TV disable +V._GPLL +V._TVG +V +.V :TV disable :hange to ground(lvs disable).u-0v_ 0U/XR-.V_ 0.U-0V_.0U-V_ 0mils +.V +.V +V._PIE +V._PLL +V._HPLL :hange to ground(lvs disable) +.V +.V :hange to ground(lvs disable) :TV disable +V._TV R0 0_ +V.U-0V_ 0U/XR-.V_.U-0V_ +V._QTV 0U/XR-.V_ +.V_UX 00m.0U-V_ 0.U-0V_.0U-V_.U-0V_ 0.U-0V_.0U-V_ R.U-0V_ 0U/XR-.V_.U-0V_ 0_ +V._PLL +V._MPLL +.V 00m UH H VSYN 0 V_TXLVS0 0 V_TXLVS 0 V_TXLVS J VG0 VG Y VG V R VG VG N VG L VG V_GPLL G V_GG H _GG F V_RT0 E V_RT G _RT V_PLL V_PLL F V_HPLL V_LVS _LVS F V_MPLL H0 V_TVG G0 _TVG E V_TV0 F V_TV 0 V_TV0 0 V_TV E0 F0 V_TV0 V_TV POWER H V_HMPLL0 H V_HMPLL V_LVS0 V_LVS V_LVS V_TV V_HV0 V_HV V_HV H V_QTV K VUX0 F VUX E VUX VUX L0 VUX K0 VUX J0 VUX H0 VUX G0 VUX F0 VUX E0 VUX0 0 VUX 0 G VUX VUX F VUX E VUX VUX VUX G VUX F VUX E VUX0 H VUX J H VUX VUX J0 VUX H0 VUX H VUX P VUX P VUX H VUX P VUX0 H VUX G F VUX VUX E VUX Y VUX F VUX E VUX F VUX E VUX VUX0 alistoga(pm) VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ W V T R P N M L Y W V U T R N M L Y W V U T R P N M L R P N M R0 P0 N0 M0 P N M R P N M P N M R P M R P N M P N M R P N M R P M R P N M +.0V 00m +.0V + 0 0U-.V_.U-.V_.U-0V_.U-0V_ 0U/XR-.V_ +.0V 0.U-.V_.U-.V_.U-0V_.U-0V_ +.V.U-0V_.U-0V_ Size ocument Number Rev GMH POWER ( OF ) PROJET : Z Quanta omputer Inc. ate: Friday, ecember 0, 00 Sheet 0 of

11 Size ocument Number Rev ate: Sheet of GMH GN( OF ) Friday, ecember 0, 00 Size ocument Number Rev ate: Sheet of GMH GN( OF ) Friday, ecember 0, 00 Size ocument Number Rev ate: Sheet of GMH GN( OF ) Friday, ecember 0, 00 _0 W _ T _ P _ M _ J _ F _ V0 _ P0 _0 N0 _ K0 _ J0 _ H0 _ G0 _ F0 _ E0 _ 0 _ Y _ W _0 V _ R _ N _ J Y _ W _ V _0 T _ R _ P _ N _ M _ L _ J _ H _ G _ F _0 _ T _ M _ H _ G _ F _ E K _ H _0 Y _ W _ V _ T _ R _ P _ N _ M _0 L _ J _ H _ G _ F Y _ W _ N _ H _0 G _ F _ E _ V _ R _ H _0 Y _ W _ V _ T _ R _ P _ F _00 E _0 _0 _0 W _0 V _0 R _0 E _0 _0 Y _0 V _0 T _ R _ M _ H _ G _ F _ H _ G _0 F _ E _ G Y _ V _ N _ J _0 G Y _ 0 _ E0 _ T _ N T _ N _0 K _ G _ E _ W _ U _ P _0 M _ W _ J _ E _ P _ M _ K _ J _0 G _ F _ N _ M _ K _ F K _0 P _ K _ H _ E U _ L _ W _ N _ M _0 L _ J _ H _ G _ F N _ K _ G UI alistoga(pm) UI alistoga(pm) _0 T _ N _ M _ H W _ K _ J _ F 0 _ K _ G _ F _ E V _ R _00 N _0 L _0 _0 Y _0 P _0 K _0 J _0 H _0 _0 W0 _0 R0 _ M0 _ 0 _ K0 _ 0 _ 0 _ N W _ K _0 G H _ P _ H _ Y _ R _ P _0 M _ K _ V _ N _ L _ J _ F N _ M _0 K _ N _ M _ L T _ K 0 _ U _ K _ H _ E _ V _ R _ N _ M _ L _0 G _ P _ F _ Y K _ H _ E _0 Y _ J _ V0 _ W _ R _ H Y _0 R _ G _ E G _ U _ K 00 _0 V _0 P _0 L _0 J _0 H _0 F _0 _0 R _0 G _0 _ G _ Y _ U _ N _ K _ H 0 V _ F Y _ R _ P _ L _ J _ Y _ U _0 R _ J _ F Y _ W _ V _ L _ H _ G _0 F G _ T _ R _ P _ K _ J _0 Y _ U _ T _ N _ J _0 G0 _ 0 _ W0 _ U0 L0 _ J0 _ P0 _ H _ F 0 L UJ alistoga(pm) UJ alistoga(pm) Quanta omputer Inc. PROJET : Z Quanta omputer Inc. PROJET : Z hexainf@hotmail.com

12 RII UL HNNEL,. RII HNNEL RII HNNEL M [..0] SMR_VTERM M [..0], SMR_VTERM, SMR_VTERM SMR_VTERM SMR_VTERM 0.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_ Layout note: Place one cap close to every pullup resistors terminated to SMR_VTERM :Swap net :Swap net, M_OT0, M_KE, M S#0, M S#, M WE#, M S# M M_OT0 M M M M M_KE M M 0 M S#0 M M M M 0 M S# M M M M WE# M S# RP RP RP RP RP RP RP RP RP RP _PR_S _PR_S _PR_S _PR_S _PR_S _PR_S _PR_S _PR_S _PR_S _PR_S SMR_VTERM SMR_VTERM SMR_VTERM, M S#, M_KE, M S#, M_S#, M RS#, M WE#, M S#, M S#0 M S# M M M M M M 0 M M M M M M_KE M S# M_S# M RS# M WE# M S# M 0 M S#0 RP RP RP RP0 RP RP RP RP RP RP _PR_S _PR_S _PR_S _PR_S _PR_S _PR_S _PR_S _PR_S _PR_S _PR_S SMR_VTERM SMR_VTERM SMR_VTERM :Swap net M [..0] +.VSUS +V M [..0], +.VSUS,,,0,, +V,,,0,,,,,,,,0,,,,,,0,,,,,,,,,,0,,,, M_S#0, M RS#, M_OT, M_OT, M_S#, M_S#, M_OT, M_KE, M_KE0, M S# M_S#0 M RS# M M_OT M_OT M_S# M_S# M_OT M_KE M M_KE0 M S# RP0 RP RP RP RP0 RP _PR_S _PR_S _PR_S _PR_S _PR_S _PR_S SMR_VTERM PROJET : Z Quanta omputer Inc. Size ocument Number Rev R RES. RRY ate: Monday, November, 00 Sheet of

13 M M[0..] +V SMR_VREF_IMM +V,,,0,,,,,,,0,,,,,,0,,,,,,,,,,0,,, M Q[0..] M M[0..] +.VSUS SMR_VREF_IMM +.VSUS +.VSUS,,0,, M QS[0..] M Q[0..] SMR_VREF_IMM :Swap net M QS#[0..] M QS[0..] Place these aps near So-imm. +.VSUS :Swap net +.VSUS +.VSUS +.VSUS M [0..], M QS#[0..] N0 M [0..], N :hange RII footprint to same as T VREF M Q 0 VREF M Q M Q Q M Q0 M Q Q M Q0 M Q Q0 Q.U-.V_.U-.V_ M Q Q0 Q Q 0 M M0 Q M M0 M QS#0 M0 0 M QS#0 M0 M QS0 QS#0 M Q M QS0 QS#0 M Q QS0 Q M Q +.VSUS QS0 Q M Q M Q Q Place these aps near So-imm. M Q Q M Q Q 0 M Q M Q Q M Q Q Q 0 M Q Q Q M Q M Q Q M Q Q M Q Q M M M Q Q M M Q M.U-0V_.U-0V_.U-0V_.U-0V_ Q M M QS# 0 M_LK_R M QS# M_LK_R0 M QS QS# K0 M_LK_R 0 M_LK_R# M_LK_R0 M QS QS# K0 M_LK_R#0 QS K0# M_LK_R# M_LK_R#0 QS K0# M Q M Q M Q M Q M Q0 Q0 Q M Q M Q Q0 Q M Q0 Q Q 0 :hange SOIMM pin 0 from PM_EXTTS# SMR_VREF_IMM +V Q Q to PM_EXTTS#0(Intel recommend) M Q 0 M Q M Q 0 M Q0 M Q0 Q Q0 M Q M Q Q Q0 M Q Q Q 0 Q Q M QS# 0 PM_EXTTS#0 PM_EXTTS#0.U-0V_.U-.V_.U-.V_.U-0V_ M QS# PM_EXTTS#0 PM_EXTTS#0 M QS QS# N 0 M M M QS QS# N M M QS M QS M M Q M Q M Q M Q M Q Q Q M Q M Q Q Q M Q Q Q 0 Q Q M Q 0 M Q Place these aps near So-imm. M Q M Q M Q Q Q M Q M Q Q Q M Q Q Q No Vias etween the Trace of PIN to Q Q M M M QS# M M M QS# M QS# 0 M QS P. M QS# M QS N QS 0 N QS M Q0 0 M Q M Q0 0 M Q M Q Q Q0 M Q M Q Q Q0 M Q Q Q +.VSUS Q Q M_KE M_KE, M_KE 0 M_KE, Place these aps near So-imm. M_KE0 M_KE KE0 KE, M_KE0 0 M_KE, KE0 KE V V V V M S# N, M S# M S# N _, M S# _ M V V 0 M M V V M M 0 M.U-.V_.U-.V_ M M M M M M M V V M M V V M M 00 M M M M M 0 +.VSUSPlace these aps near So-imm. M M M 0 V0 V M S# M S#, M 0 V0 V M S# M S#0 0/P 0 0 M RS# M S#,, M S# /P M RS#,, M S#0 M RS# M WE# 0 RS# 0 0 M_S# M RS#,, M WE# 0 0 M_S#, M WE# 0 RS# M_S#0 WE# S0#, M WE# 0 0 M_S#0, 0 WE# S0# M S# V V M_OT.U-0V_, M S#.U-0V_.U-0V_.U-0V_ M_OT, M S# V V M_OT0 M_S# S# OT0 M, M S# M_OT0, M_S# S# OT0 M, M_S# S#, M_S# S# M_OT V V, M_OT 0 M_OT V V OT N, M_OT 0 OT N M Q M Q M Q M Q M Q Q Q M Q SMR_VREF_IMM +V M Q Q Q M Q Q Q Q Q M QS# 0 M M M QS# M M M QS QS# M 0 M QS QS# M QS M Q QS M Q M Q Q M Q M Q Q M Q M Q Q Q.U-0V_.U-.V_.U-.V_.U-0V_ M Q Q Q Q 0 M Q Q M Q M Q Q 0 M Q M Q Q M Q M Q0 Q0 Q M Q0 Q0 Q Q M QS# Q M QS# M M QS# M QS M M QS# M QS M QS 0 Place these aps near So-imm. M QS M Q 0 M Q M Q M Q M Q Q Q M Q No Vias etween the Trace of PIN to M Q Q Q M Q Q Q Q Q M Q 0 M Q P. M Q 0 M Q M Q Q Q 0 M Q M Q Q Q M Q Q Q 0 Q Q M_LK_R M_LK_R M_LK_R NTEST K M_LK_R# M_LK_R NTEST K M_LK_R# M_LK_R# M QS# 0 K# SMR_VREF M_LK_R# M QS# 0 K# M QS QS# 0 M M M QS QS# M M QS M 0 QS M M Q0 M Q M Q M Q M Q Q0 Q M Q M Q0 Q0 Q M Q Q Q SMR_VREF_IMM R0 0_ Q Q SMR_VREF, M Q 0 M Q0 R M Q M Q M Q Q Q0 0 M Q M Q Q Q0 M Q0 Q Q R0 *0K/F_ Q Q +.VSUS M M M QS# *0K/F_ M M M QS# M QS# M QS M QS# M QS M Q QS 0 M Q QS M Q Q 0 M Q M Q Q M Q Q Q M Q Q Q M Q GT_SM Q GT_SM GT_SM Q GLK_SM S R 0K_ PROJET : Z GLK_SM GLK_SM S R 0K_ SL S0 +V 00 R 0K_ SL S0 V(SP) S +V 00 R 0K_ V(SP) S R_SOIMM(-0-) Quanta omputer Inc. +V R_SOIMM(-0-) Size ocument Number Rev SMbus address 0 SMbus address RII SO-IMM(00P) LOK 0, KE 0, H. LOK, KE, H. nd source:gmk nd source:gmk0000 ate: Wednesday, November 0, 00 Sheet of P00 R SRM SO-IMM (00P) P00 R SRM SO-IMM (00P).U-.V_.U-.V_.U-.V_.U-.V_.U-.V_.U-.V_ hexainf@hotmail.com

14 RT VRT +VPU H00H-0 VRT U-V_ KL:/: pf -> L:.pF /: 0pF -> L Value =.pf :hange RTX/RTX from 0pf to pf +VPU VRT_ R0 K_ :hange RT onnector footprint R R.K_ R K_ N 0MIL KL:n ~ 0nF +V 0 H00H-0 R RT ONN VRT_ R.K_ R0.K_ M/F_ R0 0K_ VRT_ 0MIL VRT_ K_ ST_RXN0 ST_RXP0 ST_TXN0 ST_TXP0 ST_RXN ST_RXP ST_TXN ST_TXP R.K_ U-V_ Q 0 ST_LE# LK_PIE_ST# LK_PIE_ST MMT0 mils/mils Internal PU 00P_ 00P_ 00P_ 00P_ 00P_ 00P_ 00P_ 00P_ LK_KX 0 LK_KX P-0V_ RTRST# Z_SIN0 Z_SIN SM_INTRUER# IH_INTVRMEN ST_LE# Z_LK Z_SYN Z_RST# Z_SIN0 Z_SIN Z_SIN Z_SOUT ST_RXN0_ ST_RXP0_ ST_TXN0_ ST_TXP0_ ST_RXN_ ST_RXP_ ST_TXN_ ST_TXP_ R0./F_ ST_IS Place within 00 mils of IH PIOR# PIOW# PK# IRQ PIORY PREQ P-0V_ Y.KHZ Internal PU T IRQ PIORY R 0M_ RTX RTX Y INTRUER# W INTVRMEN W EE_S Y EE_SHLK Y EE_OUT W EE_IN V U LN_LK LN_RSTSYN U LN_RX0 V LN_RX T LN_RX U LN_TX0 V LN_TX V LN_TX U Z_IT_LK R Z_SYN R Z_RST# T Z_SIN0 T Z_SIN T Z_SIN T F U RTRST# Z_SOUT STLE# F ST0RXN E ST0RXP G ST0TXN H ST0TXP F STRXN E STRXP G STTXN H STTXP F ST_LKN E ST_LKP H0 STRISN G0 STRISP F IOR# H IOW# F K# H IEIRQ G IORY E REQ IH-M H RT LP LN PU -/ZLI ST IE L0 L L L LRQ0# LRQ#/GPIO LFRME# 0GTE 0M# PUSLP# TP/PRSTP# TP/PSLP# FERR# GPIO/PUPWRG IGNNE# INIT_V# INIT# INTR RIN# NMI SMI# STPLK# THERMTRIP# S# S# Y E H G F H G G G G F F G H F H F E G F E F F H H H E F E LRQ#0 LRQ# GTE0 TP_H_PUSLP# H_PRSTP#_R H_PSLP#_R RIN# H_SMI#_R P0 P P P P P P P P P P0 P P P P P P0 P P H_THERMTRIP_R L0, L, L, L, LRQ#0 T LFRME#, GTE0 H_0M# P[:0] P[:0] PS# PS# H_PWRG H_IGNNE# H_INIT# H_INTR RIN# H_NMI H_SMI# H_STPLK# +.0V Z_SOUT Z_SYN RIN# GTE0 R0 *0_ H_PUSLP#, :Per Intel comment,don't stuff R0 for PUSLP# R0 0_ IH_PRSTP# R 0_ H_PSLP# R 0_ T R0 0_ R R *./F_ *./F_ +V +.0V R0./F_ Should be " close IH series termination resistor is required for the PRIMRY OE R _ R0 _ R00 0K_ +V +.0V R 0K_ R./F_ R./F_ *0P_ *0P_ H_FERR# PM_THRMTRIP#, Z_SOUT_UIO Z_SYN_UIO PIORY IRQ Z_LK R0 _ IT_LK_UIO IH internal VR enable strap INTVRMEN Enable (default) VRT R K/F_ IH_INTVRMEN Z_LK R _ :dd R for IT_LK_MOEM *0P_ IT_LK_MOEM *0P_ isable 0 R *0_ Z_RST# R _ Z_RST#_UIO PROJET : Z Quanta omputer Inc. Size ocument Number Rev IH-M HOST ( OF ) ate: Friday, ecember 0, 00 Sheet of

15 :hange PIE pin define to meet cer spec New card GLN MINI R(WLN) EZ_ EZ_ T T T0 T T +V R *0K_ PIE_RXN0 PIE_RXP0 PIE_TXN0 PIE_TXP0 PIE_RXN PIE_RXP PIE_TXN PIE_TXP T T T T PIE_RXN PIE_RXP PIE_TXN PIE_TXP PIE_RXN PIE_RXP PIE_TXN PIE_TXP PIE_RXN PIE_RXP PIE_TXN PIE_TXP R R *0K_ *0K_ 0 SPI_SLK SPI_E# NVM_R SPI_SI SPI_SO.U-0V_PIE_TXN0_.U-0V_ PIE_TXP0_.U-0V_PIE_TXN_.U-0V_ PIE_TXP_ PIE_RXN PIE_RXP.U-0V_PIE_TXN_.U-0V_ PIE_TXP_.U-0V_PIE_TXN_.U-0V_ PIE_TXP_.U-0V_PIE_TXN_.U-0V_ PIE_TXP_.U-0V_PIE_TXN_.U-0V_ PIE_TXP_ SPI_SLK SPI_E# NVM_R SPI_SI SPI_SO USO#0 USO# USO# USO# USO# USO# USO# USO# U F PERn F PERp E PETn E PETp H PERn H PERp G PETn G PETp K PERn K PERp J PETn J PETp M PERn M PERp L PETn L PETp P PERn P PERp N PETn N PETp T PERn T PERp R PETn R PETp R SPI_LK P SPI_S# P SPI_R P SPI_MOSI P SPI_MISO O0# O# O# O# E O# O#/GPIO O#/GPIO0 O#/GPIO IH-M H PI-Express SPI irect Media Interface US MI0RXN MI0RXP MI0TXN MI0TXP MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MI_LKN MI_LKP MI_ZOMP MI_IROMP USP0N USP0P USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USRIS# USRIS V V U U Y Y W W E E F F G G H H J J K K L L M M N N US_RIS_PN Place within 00 mils of IH MI_RXN0 MI_RXP0 MI_TXN0 MI_TXP0 MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP LK_PIE_IH# LK_PIE_IH /mils RI_IROMP_R USP0- USP0+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ mils/mils R./F_ +.V R./F_ Place within 00 mils of IH M US PORT(RIGHT) M US PORT(RIGHT) M US PORT(RER) M US PORT(RER) in card reader NEW R luetooth Module amera module +V +V_S +V +V REQ# FRME# STOP# REQ# LOK# SERR# PERR# EVSEL# INTF# REQ# REQ0# IRY# INT# USO# USO# INT# :hange to +V_S RP.K_0PR RP.K_0PR RP0.K_0PR RP.K_0PR KL use 0Kohm +V INTG# REQ# REQ# TRY# +V INTH# INTE# +V USO# INT# INT# USO# +V_S USO#0 USO# USO# USO# IH oot IOS select,0 [0..] T T T T T INT# INT# INT# INT# TP_IH_RSV TP_IH_RSV TP_IH_RSV TP_IH_RSV TP_IH_RSV U E 0 F E E E 0 G G E 0 0 F F0 E E 0 PIRQ# PIRQ# PIRQ# PIRQ# E RSV[] RSV[] G RSV[] H RSV[] RSV[] PI REQ0# GNT0# REQ# GNT# REQ# GNT# REQ# GNT# REQ#/GPIO GNT#/GPIO GPIO/REQ# GPIO/GNT# /E0# /E# /E# /E# IRY# PR PIRST# EVSEL# PERR# PLOK# SERR# STOP# TRY# FRME# PLTRST# PILK PME# Interrupt I/F IH-M H MIS GPIO/PIRQE# GPIO/PIRQF# GPIO/PIRQG# GPIO/PIRQH# RSV[] RSV[] RSV[] RSV[] MH_SYN# E E F E0 E 0 F F F G F F G REQ0# GNT0# REQ# GNT# REQ# REQ# REQ# REQ# IRY# EVSEL# PERR# LOK# SERR# STOP# TRY# FRME# PLT_RST-R# PLK_IH INTE# INTF# INTG# INTH# E TP_IH_RSV G TP_IH_RSV H TP_IH_RSV F RSV H0 E0#,0 E#,0 E#,0 E#,0 INTE# 0 T T T T R *K/F_ GNT# IRY#,0 PR 0 PIRST#,0 EVSEL#,0 PERR# 0 SERR# 0 STOP# 0 TRY#,0 FRME#,0 PLK_IH PI_PME# 0 REQ0# 0 GNT0# 0 T U R *0P_ *_ +V PLK_IH PLT_RST-R# PLT_RST-R# MH_IH_SYN PLTRST#,,,,,,, TSH0FU on't connect to PI device / Express card.u-0v_ R 00K_ :Reserve 00k pull low to GN LP (default) PI SPI PI EVIE OZMP STRP ISEL# GNT# R Size ocument Number Rev IH-M PI E ( OF ) ate: Friday, ecember 0, 00 Sheet of GNT# R UNSTUFF UNSTUFF 0 UNSTUFF STUFF 0 STUFF REQ# / GNT# UNSTUFF Interrupts REQ0# / GNT0# INTE# PROJET : Z Quanta omputer Inc. hexainf@hotmail.com

16 Z_SPKR PM_STPPI# PM_STPPU# THERM_LERT# +V +V R *0K/F_ +V R0 *K/F_ Note: onnect to E; Reserve PH/V PLK_SM PT_SM PIE_WKE# VR_PWRG_K0 U PLK_SM PT_SM SMLK SM_LINK_LERT# SMT SMLINK0 LINKLERT# SMLINK SMLINK0 SMLINK LP_P# LP_P# SYS_RST# SYS_RST# +V R0 *0K_ R 0_ PM_MUSY# R0 :dd for SM_LERT# *0K/F_ SM_LERT# No SF support SM_LERT# R0 R 0_ 0_ PM_STPPI_IH# PM_STPPU_IH# 0 F 0,, LKRUN# R 0K/F_,, PIE_WKE# 0,, SERIRQ,,,,, PLK_SM,,,,, PT_SM SI# KSMI# +V 0 RI# T to lock Gen & IMM RST_RY# R 0_ R0 0_ R0 *0K_ OR_I0 T T T R R00 R OR_I0 OR_I RI# LKRUN# PIE_WKE# SERIRQ RUNTIME_SI#_R EXTSMI#_R +V R0 *0K_.K_.K_ K_ OR_I +V_S E G U F0 H F0 E RI# SPKR SUS_STT# SYS_RST# GPIO0/M_USY# GPIO/SMLERT# GPIO/STPPI# GPIO0/STPPU# GPIO GPIO GPIO GPIO/LKRUN# GPIO GPIO GPIO :hange SM_LERT# to MIN power RI# SM_LINK_LERT# SMLINK0 SMLINK EXTSMI#_R SM_LERT# RYI RYI0 GPIO/Z_OK_EN# GPIO/Z_OK_RST# WKE# SERIRQ THRM# VRMPWRG IH-M H SM ST GPIO SYS GPIO Power MGT GPIO locks R R R R R R R0 R GPIO/ST0GP GPIO/STGP GPIO/STGP GPIO/STGP LK LK SUSLK SLP_S# SLP_S# SLP_S# PWROK GPIO/PRSLPVR TP0/TLOW# PWRTN# LN_RST# RSMRST# GPIO GPIO0 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO 0K_ 0K_ 0K_ 0K_ *0K_ 0K_ 0K_ 0K_ F H H E 0 F Y E0 0 F E R E R 0 0 E0 +V_S ST0GP STGP RST_H# RYON# M_IH LKUS_ R R0 IH_PWROK PRSLPVR PM_TLOW#_R NSWON# R0 *00K_ R0 0_ PM_RSMRST#_R LOW_G_INT HIGHT_G_INT EMIL_LE# LN_ISLE# RYI RYI0 VR_PWRG_K0 NSWON# SYS_RST# R0 R 0K_ 0K_ PM_TLOW#_R R0.K_ :hange to.k 00/F_ 00/F_ +V R R 00K_ +V T0 RYON# M_IH LKUS_ T SUS# SUS# R _ NSWON# RSMRST# +V_S PRSLPVR LKRUN# SERIRQ RUNTIME_SI#_R ST0GP STGP RSMRST# PM_PRSLPVR :R place near PR and change to 00 ohm series resistor 00/F_ :hange to PLTRST# PLTRST#,,,,,,, RSMRST#, LOW_G_INT, HIGHT_G_INT, :dd for H protect(g-sensor) EMIL_LE# 0 RST_KXP :dd for G sensor reset LI#,,0 OKIN#,, GPIO has an internal pull-up(main) LN_ISLE# :dd for isable LN circuit EXPRR_STY# GPIO(Not cleared by Fh reset event RYI RYI0 :hange to inverter for VR_PWRG_K0 U GPIO /Suspend rail is a HW strap, don't pull down. VR_PWRG_K0#, R0 R R0 R R0 R LKUS_ R *0_.K_.K_ 0K_ 0K_ 0K_ 0K_ *_ +V M_IH R R0 0K_ R0 0K_ +VSUS SNLVG0KR Note: External pull-up V *0P_ *0P_ OM oard I omo-p Reserve Reserve Reserve I (R0/R0) I0 (R0/R0),, ELY_VR_PWRGOO PWROK_E +V R R.K/F_ 00K_.0U-V_ U TSH0FU IH_PWROK R 0K_ To Lan pwr ok IH_PWROK Size ocument Number Rev IH-M GPIO ( OF ) PROJET : Z Quanta omputer Inc. ate: Tuesday, ecember 0, 00 Sheet of

17 VREF_SUS VREF() GPLL_R_L GPLL_R VS_IH_SUS TPVSUSLN TPVSUSLN TP_IHVSUS TP_IHVSUS TP_IHVSUS +V +V +.V +.V_PIE_IH +V_S +V_S +V +.V +.V_GPLL_IH +.V +.V +.V +V_S +.V +.V +.V +.V +.V +V_S VRT +V +.0V +V +V +V +.0V +V_S +V +V +V_S Size ocument Number Rev ate: Sheet of IH-M POWER ( OF ) Friday, ecember 0, 00 Size ocument Number Rev ate: Sheet of IH-M POWER ( OF ) Friday, ecember 0, 00 Size ocument Number Rev ate: Sheet of IH-M POWER ( OF ) Friday, ecember 0, 00 /mils /mils 0mils 0mils :hange +VSUS to +V_S to prevent leakage :hange to HKMJ(ME height limit H=.) :hange +V_S to +V 0m VREF[] G0 VREF[] VREF_Sus F Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [0] Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] E Vcc [] E Vcc [] E Vcc [] F Vcc [] F Vcc [0] G Vcc [] G Vcc [] H Vcc [] H Vcc [] J Vcc [] J Vcc [] K Vcc [] K Vcc [] L Vcc [] L Vcc [0] M Vcc [] M Vcc [] N Vcc [] N Vcc [] P Vcc [] P Vcc [] R Vcc [] R Vcc [] R Vcc [] R Vcc [0] R Vcc [] T Vcc [] T Vcc [] T Vcc [] T Vcc [] T Vcc [] U Vcc [] U Vcc [] V Vcc [] V Vcc [0] W Vcc [] W Vcc [] Y Vcc [] Y Vcc_[] VccMIPLL G Vcc [] Vcc [] Vcc [] Vcc [] Vcc [] E Vcc [] F Vcc [] F Vcc [] G Vcc [] H VccSTPLL Vcc_[] H Vcc [0] 0 Vcc [] Vcc [] 0 Vcc [] 0 Vcc [] E0 Vcc [] F0 Vcc [] F Vcc [] G Vcc [] H VccUSPLL VccSus_0/VccLN_0[] VccSus_0/VccLN_0[] Y Vcc_0[] L Vcc_0[] L Vcc_0[] L Vcc_0[] L Vcc_0[] L Vcc_0[] L Vcc_0[] M Vcc_0[] M Vcc_0[] P Vcc_0[0] P Vcc_0[] T Vcc_0[] T Vcc_0[] U Vcc_0[] U Vcc_0[] V Vcc_0[] V Vcc_0[] V Vcc_0[] V Vcc_0[] V Vcc_0[0] V VccSus_/VccLN_[] V VccSus_/VccLN_[] V VccSus_/VccLN_[] W VccSus_/VccLN_[] W Vcc_/VccH U VccSus_/VccSusH R V_PU_IO[] E V_PU_IO[] E V_PU_IO[] H Vcc_[] Vcc_[] Vcc_[] 0 Vcc_[] Vcc_[] Vcc_[] Vcc_[] G Vcc_[0] G Vcc_[] G Vcc_[] Vcc_[] Vcc_[] Vcc_[] Vcc_[] 0 Vcc_[] Vcc_[] F Vcc_[] G Vcc_[0] G Vcc_[] G VccRT W VccSus_[] P VccSus_[] VccSus_[] VccSus_[] VccSus_[] VccSus_[] G VccSus_[] K VccSus_[] K VccSus_[] K VccSus_[0] K VccSus_[] L VccSus_[] L VccSus_[] L VccSus_[] L VccSus_[] L VccSus_[] M VccSus_[] M VccSus_[] N Vcc [] Vcc [0] Vcc [] T Vcc [] F Vcc [] G Vcc [] Vcc [] VccSus_0[] K VccSus_0[] VccSus_0[] G0 Vcc [] Vcc [] H Vcc [] H Vcc [] J Vcc [0] J VccSus_[] E ORE VGP V PUX US TX RX IE US ORE PI UF IH-M H ORE VGP V PUX US TX RX IE US ORE PI UF IH-M H.U-0V_.U-0V_.U-0V_.U-0V_ T0 T0.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_0.U-0V_0 0.U-0V_ 0.U-0V_.U-0V_.U-0V_.0U-V_.0U-V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_ R0 *0_ R0 *0_ Quanta omputer Inc. PROJET : Z Quanta omputer Inc. PROJET : Z.U-0V_.U-0V_ 0.U-0V_ 0.U-0V_.U-0V_.U-0V_ PZ. PZ. T T.U-0V_.U-0V_ PZ. PZ. U-V_ U-V_ U-V_ U-V_ + 0U-V_ + 0U-V_ 0 U-V_ 0 U-V_.U-0V_.U-0V_.U-0V_.U-0V_ + 0U-.V_ + 0U-.V_.U-0V_.U-0V_.U-0V_.U-0V_ L uh_ L uh_ R 00/F_ R 00/F_.U-0V_.U-0V_ 0 0U/XR-.V_ 0 0U/XR-.V_ U-V_ U-V_.U-0V_.U-0V_ R 0_ R 0_.U-0V_.U-0V_ R _ R _.U-0V_.U-0V_ [] [] [] [] [] [] [] [] 0 [] [0] [] [] [] [] 0 [] [] [] [] [] E [0] E [] E [] E [] E [] F [] F [] F [] F [] F [] F [0] G [] G [] G [] G [] G [] G [] G [] G [] G [] G [0] G [] H [] H [] H [] H [] H [] H [] J [] J [] J [0] J [] J [] J [] K [] K [] K [] L [] L [] L [] L [0] L [] M [] M [] M [] M [] M [] M [] M [] M [] M [0] M [] M [] M [] N [] N [] N [] N [] N [] N [] N [0] N [] N [] N [] N [] N [] N [] N [] N [] P [] P [0] P [] P [] P [] P [] P [] P [] P [] P [] P [] R [00] R [0] R [0] R [0] R [0] R [0] R [0] R [0] R [0] T [0] T [0] T [] T [] T [] T [] T [] U [] U [] U [] U [] U [0] U [] U [] U [] U [] U [] V [] V [] V [] V [] V [0] V [] W [] W [] W [] W [] Y [] Y [] Y [] Y [] [0] [] [] [] [] [] [] [] [] [] [0] [] [] [] [] [] [] [] [] [] [0] [] [] [] [] [] [] E [] E [] E [] E [0] E [] E [] E [] E [] E [] F [] F [] F [] F [] F [0] F [] G [] G [] G [] G [] G [] G [] G0 [] G [] H [0] H [] H [] H [] H [] H UE IH-M H UE IH-M H.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_ 0.U-0V_ 0.U-0V_ R 0_ R 0_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_ T T T *P T *P.U-0V_.U-0V_ 0.U-0V_ 0.U-0V_.U-0V_.U-0V_ R 0_ R 0_.U-0V_.U-0V_.U-0V_.U-0V_ T *P T *P 0.U-0V_ 0.U-0V_ L K0HS00_ L K0HS00_.U-0V_.U-0V_ 0.U-0V_ 0.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_.U-0V_ hexainf@hotmail.com

18 PIE TEST PS PIE TEST POINTS MUST E WITHIN 0 MILS OF THE SI LL WITH POSITIVE N NEGTIVE SIGNLS THE SME ISTNE PEG_RXP[:0] PEG_RXN[:0] PEG_TXP[:0] PEG_TXN[:0] U PEG_TXP0 PEG_TXN0 J H PIE_RX0P PIE_RX0N PRT OF PIE_TX0P PIE_TX0N K V_GMHEXP_RXP0 J V_GMHEXP_RXN0 0 0 EV@.U-0V_ PEG_RXP0 EV@.U-0V_ PEG_RXN0 TI FETURE NOT ENLE (MP,MP,MP) :on't stuff R,R for PIE_TEST +V R *.K_ PIE_TEST R *.K_ PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN H0 G0 G F F E E Y PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN P I - E X P R E S S I N T E R F E PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN J V_GMHEXP_RXP H V_GMHEXP_RXN H V_GMHEXP_RXP G V_GMHEXP_RXN G V_GMHEXP_RXP F V_GMHEXP_RXN F V_GMHEXP_RXP E V_GMHEXP_RXN E V_GMHEXP_RXP V_GMHEXP_RXN V_GMHEXP_RXP V_GMHEXP_RXN V_GMHEXP_RXP V_GMHEXP_RXN V_GMHEXP_RXP V_GMHEXP_RXN EV@.U-0V_ EV@.U-0V_ EV@.U-0V_ EV@.U-0V_ EV@.U-0V_ EV@.U-0V_ EV@.U-0V_ EV@.U-0V_ EV@.U-0V_ EV@.U-0V_ EV@.U-0V_ EV@.U-0V_ EV@.U-0V_ EV@.U-0V_ EV@.U-0V_ EV@.U-0V_ PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_TXP PEG_TXN Y W PIE_RXP PIE_RXN PIE_TXP PIE_TXN V_GMHEXP_RXP Y V_GMHEXP_RXN EV@.U-0V_ EV@.U-0V_ PEG_RXP PEG_RXN PEG_TXP0 PEG_TXN0 W0 V0 PIE_RX0P PIE_RX0N PIE_TX0P PIE_TX0N Y V_GMHEXP_RXP0 W V_GMHEXP_RXN0 EV@.U-0V_ EV@.U-0V_ PEG_RXP0 PEG_RXN0 PEG_TXP PEG_TXN V U PIE_RXP PIE_RXN PIE_TXP PIE_TXN W V_GMHEXP_RXP V V_GMHEXP_RXN EV@.U-0V_ EV@.U-0V_ PEG_RXP PEG_RXN PEG_TXP PEG_TXN U T PIE_RXP PIE_RXN PIE_TXP PIE_TXN V U V_GMHEXP_RXP V_GMHEXP_RXN EV@.U-0V_ EV@.U-0V_ PEG_RXP PEG_RXN PEG_TXP PEG_TXN T0 R0 PIE_RXP PIE_RXN PIE_TXP PIE_TXN U T V_GMHEXP_RXP V_GMHEXP_RXN 0 EV@.U-0V_ EV@.U-0V_ PEG_RXP PEG_RXN PEG_TXP PEG_TXN R P PIE_RXP PIE_RXN PIE_TXP PIE_TXN T R V_GMHEXP_RXP V_GMHEXP_RXN 0 EV@.U-0V_ EV@.U-0V_ PEG_RXP PEG_RXN PEG_TXP PEG_TXN P N PIE_RXP PIE_RXN PIE_TXP PIE_TXN R P V_GMHEXP_RXP V_GMHEXP_RXN EV@.U-0V_ EV@.U-0V_ PEG_RXP PEG_RXN,,,,,,, PLTRST# PLTRST# +V LK_PIE_M LK_PIE_M# U EV@TSH0FU R *0_ E:dd U for M PLTRST# PLTRST#_M PIE_TEST L K G F lock PIE_REFLKP PIE_REFLKN PERST PIE_TEST PERST_MSK EV@M-P Tie To alibration PIE_LRN PIE_LRP PIE_LI E R R R EV@K/F_ EV@/F_ EV@.K/F_ FOR MP,MP,MP PIE_LRN = K PIE LRP = R PIE LI =.K :PIE_LRN(ball E) need change to +.V_VPIE +.V_VPIE Size ocument Number Rev MP OF PROJET : Z Quanta omputer Inc. ate: Friday, ecember 0, 00 Sheet of

19 OS_SPRE MEMORY LOK SPRE SPETRUM R :dd pull low 0k GPIO HI =.0V V GPIO LO =.V V V_PWRNTL R 0K_ EV@_ +V XT_IN _S0 _KO R *0K S0 R *0K_ FOR MP,MP,MP ONNET TO +.V.V 0M SI MPV ONNET TO V U XIN SRS SSLK EV@Y MK- M_IN M_O +.V_VG XT_OUT MK_V MK_P MK_M R0 VGM Voltage divider resistor values R and R to ensure XTLIN/XTLOUT voltage level matches vddc :Reversed LVSLK,LVST pull high to LVS side EV@.U-0V_ MOUT EV@0_ XT_IN XT_OUT MEMTYP_ MEMTYP_0 MK_P LVS_T LVS_LK :hange LVS_T/LVS_LK to VPT/VPT Y +-0PPM NY UNUSE GPIO N OPTIONLLY E MEMORY TYPE ONFIG STRPS :hange GPIO instead of GPIO for MEMTYPE_ E:dd R for MEMTYPE_ XOUT V P REF EV@0_ *0_ :hange R,R to 0 ohm for VG MHZ R EV@./F_ R :on't stuff _Strap _Strap _Strap EMUX_SEL GPIO[..0] MEMTYP_ GPIO V_PWRNTL RIVEN HI SELET.0V V V_PWRNTL RIVEN LO SELET.V V V_PWRNTL For mx,mp,mp,mp thermal interrupt is low edge and connects to gpio +V EV@/F_ R T T T T T0 T T T T T +V FOR MP,MP,MP NOT ONNETE R MP VI/VO_R VI/VO_R VI/VO_R EV@0_ V_PWRNTL OS_SPRE VG_OVT# EV@0_ *.U-0V_ :Reserved for VREFG +PV VGTHRM+ +.V L0 VGTHRM- EV@LMPGSN_ PV EV@U-V_ EV@.U-0V_ EV@U-.V_ 0 m +MPV P L0 EV@LMPGSN_ R EV@.U-0V_ EV@U-.V_ EV@U-V_ EV@U-.V_ EV@U-.V_ EV@P-0V_ EV@TX=MHz EV@P-0V_ EV@0_ R *0P-0V_ R EV@M_ R R R *0K_ EV@/F_ T0 *_ *_ L EV@U-V_ R T T R T R R EV@LMPGSN_ EV@0_ *0_ VI/VO_R VI/VO_R GPIO0 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO0 GPIO GPIO GPIO M_IN M_O R0 TESTEN EV@K_ G H G H J H G0 F0 H F F E E0 G F F E K L F F F G G G H H J J K K K L L M E F F G J H J G H F E G G H J H L M G G K J F H G G H U GPIO_ GPIO_ GPIO_ GPIO_ GPIO_0 GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_0 GPIO_ GPIO_ N_VOVMOE_0 N_VOVMOE_ VPNTL_0 VPNTL_ VPNTL_ VPLK VPT_0 VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_0 VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_0 VPT_ VPT_ VPT_ GPIO_0 General GPIO_ Purpose GPIO_ I/O GPIO_ GPIO_ GPIO_ GPIO_ GPIO LON GPIO_ GPIO_ GPIO_0 GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ N_ VREFG PLUS MINUS PV P MPV MP XTLIN XTLOUT PLLTEST TESTEN ROMSb LR_ LR_ LR_ LR_ LR_ LR_ LR_ Thermal iode PLL & XTL Test ROM LVS PLL and I/O GN PRT OF Expand GPIO VIP Host/External TMS V I E O & M U L T I M E I External SS LVS PLL and I/O GN Integrated TMS / RT TXM TXP TX0M TX0P TXM TXP TXM TXP TXM TXP TXM TXP TXM TXP TPV TP TXVR_ TXVR_ TXVR_ TXVR_ TXR_ TXR_ TXR_ TXR_ TXR_ R G HSYN VSYN GENERI GENERI RSET V_ V_ Q N_ N_ VI I (TV/RT) R G Monitor Interface HSYN VSYN Y OMP RSET V_ V_ N_ N_ N_VQ Q VI I HP T LK T LK T LK GENERI LP LR_0 LR_ LR_ L M K0 L0 L M L M K J K J K J M L J K L M J K L M K K M L J J K F L L M K K J M L K M L F G J J H K M L M L L K J J F H H H G E F E E F F F R R :The TMS termination resistor values (0 ohm) are pcb layout dependent and may require final tuning R R R0 R V VG_OVT# +TPV EXT_TV_Y/G EXT_TV_/R EXT_TV_OMP +VI TXM_EX TXP_EX TX0M_EX TX0P_EX TXM_EX TXP_EX TXM_EX TXP_EX :hange R,R0,R,R from 0 to 0 for TMS R EV@0_ EV@0_ EV@0_ EV@0_ EV@0_ EV@/F_ EV@U-.V_ EV@U-V_ EV@/F_ EV@U-.V_ EV@U-.V_ R_ G HSYN_, VSYN_, +.V L V_PNL_PLL 0m SI LPV,TPV) EV@LMPGSN_ EV@U-V_ FOR MP,MP,MP ONNET TO +.V For mx,mp,mp,mp thermal interrupt is low edge and connects to gpio 0 EV@.U-0V_ EV@U-.V_ +V EV@.U-0V_ EV@U-.V_ EV@U-.V_ EV@.U-0V_ TXVR +.V L EV@LMPGSN_ EV@.U-0V_ Y OMP_ +.V TMS_HP, RTT RTLK TMS_T TMS_LK L +.V V_. m SI V) EV@LMPGSN_ FOR MP,MP,MP ONNET TO +.V EV@U-V_ +VI FOR MP,MP,MP VQ IT IS NO ONNET EV@U-V_ +VQ L +.V EV@U-.V_ L EV@LMPGSN_ FOR MP,MP,MP ONNET TO +.V EV@U-V_ R *0_ VTHM_T_E :Reserve for thermal R *0_ VTHM_LK_E sensor LK/T :Stuff R,R for VG thermal sensor SMus :Remove R,R for VG thermal sensor SMus GENERI FOR MP,MP,MP GENERI IT IS GPIO L EV@.U-0V_ EV@U-V_ +.V VI_. 0m SI VI,VI) EV@LMPGSN_ EV@.U-0V_ PLE LOSE TO SI E:dd R,R,R,R,R,R (0 ohm) for RT/TV can't detect issue R_ G EXT_TV_Y/G EXT_TV_/R EXT_TV_OMP R R R R R R +.V EV@LMPGSN_ 0 EV@U-V_ 0/F_ 0/F_ 0/F_ 0/F_ 0/F_ 0/F_ The is for VI (TMS) reading EI data, which cannot be shared with other I devices. EV@M-P +V MIL L V_THM EV@LMPGSN_ EV@.U-0V_ R 0K_ +V :on't stuff R,R for thermal sensor :stuff R for thermal sensor +V +V :Stuff Q,Q for VG thermal sensor Q N00E VGTHRM- 0 mil trace / 0 mil space VGTHRM+ EV@00P-0V_ lose to pin SI U V XN XP GN EV@G- LERT# S SLK OVERT# SLVE RESS: VG_OVT# VTHM_T_E VTHM_LK_E VG_THERM# :onnect U OVERT to fan driver VTHM_T_E R 0K_ R 0K_ VTHM_LK_E :Reserve for VG thermal sensor :hange R,R to 0K to resolve attery can't learning issue VTHM_T_E MT VTHM_LK_E MLK N00E Q +V :Remove Q,Q for VG thermal sensor MT,, MLK,, PROJET : Z Quanta omputer Inc. Size ocument Number Rev MP OF Saturday, ecember 0, 00 ate: Sheet of hexainf@hotmail.com