ZYA SYSTEM BLOCK DIAGRAM

Transcription

1 ZY SYSTEM LOK IGRM GPU ORE PWR ISL P HRGER ISL P GPU IO PWR ISL P /V SYS PWR P RT X'TL.MHz LOK GENERTOR SELGO: SLGSPV P LK: MHz PEG_LK: MHz PLL_REF_SSLK: MHz intel <MH Processor> Fan river (PWM Type) P ISHRGER V, V,.V,.V,.V_VTT.V/.V P RT TPS P PU ORE PWR ISL P PU VTT UPQ R:.V F:.V P Note: HM does not support US & HM does not support ST & est onn. US US Port x US,,, (ebug) US (ebug) luetooth P P P R III P,,, est uffer P SO-IMM SO-IMM SO-IMM SO-IMM H (ST) * P O (ST) P ual hannel / MHz MT/s MT/s ST ST ST ST US. zalia R SYSTEM MEMORY ST. GT/s US H rrandale (SG) larksfield (iscrete) FI FI rpg (.mm X.mm) P... MI intel <PH> MI Ibex Peak_M mg (mm X mm) * PI-E X PIE X MI interface PI-Express.GT/s X'TL.KHz M GPU.GT/s roadway-pro / Madison-Pro [rrandale Only] G (Mb x IO x pcs) * P... Graphics Interfaces PI-E RT P INT_RT INT_LVS P,,,,,,, * [rrandale Only] *[rrandale Only] PIE- HMI RT LVS X'TL.MHz LKOUT_PIE PU VGFX_XG ISL P THERML PROTETION LVS_RT Switch Grapgics P P PIE- & PIE- R PWR RT HMI RT LVS LKOUT_PEG_& LKOUT_PEG_ VTT.V UPQ P P P P P Mini ard WLN / TV US & P US FingerPrint US P P udio OE LX P SPI SPI ROM M x (asic MEraidwood) P LP E (WP) P X'TL.KHz IEEE & Media ardreader OZ P X'TL.MHz theros Giga-LN R P & aughter oard X'TL MHz SPI ROM P IEEEa connector P ard Reader onnector P Transformer aughter oard Front Stereo mp (GL/ WW) P Front Speaker P enter Mono mp (G/ W) P enter Speaker P Rear udio mp & Head phone N P Speaker S/PIF P P Sub-mplifier (TP) SUWOOFER P P Line in P MI Jack P Int. -MI P Touch Pad K/ OON. P P IR P SSI: ISRETE: SSI: SWITH GFX: SVI: RJ onnector aughter oard Quanta omputer Inc. PROJET : ZY Size ocument Number Rev ZY lock iagram ate: Wednesday, January, Sheet of

2 GPU PWR TRL Option (efault/ VR before V).V.V.V_SUS.V V dgpu_vron VR MOS (O) P V_ V ISL P PG_GPUIO_EN VI ISL P PG_V_EN V (P PLL PWR) PG_.V_EN VR GJ & MOS P MOS (O) P PG_.V_EN VR MOS (O) P PG_.V_EN JT P dgpu_pwrok dgpu_pwr_en# MOS O P _ (.) VGPU_ORE () VGPU_IO (.) V ().V_GPU ().V_GPU () _GPU GPU PWR TRL Option (VR after VR).V.V_SUS.V.V V dgpu_vron V ISL P PG_GPUIO_EN VI ISL P PG_V_EN V (P PLL PWR) PG_.V_EN VR GJ & MOS P MOS (O) P.V_GPU VR MOS (O) P V_ VR MOS (O) P PG_.V_EN JT P dgpu_pwrok dgpu_pwr_en# MOS O P VGPU_ORE () VGPU_IO (.) V ().V_GPU () _ (.).V_GPU () _GPU Power States Thermal Follow hart POWER PLNE VOLTGE ESRIPTION ONTROL SIGNL TIVE IN VRT VPU VPU V~V V~.V.V V MIN POWER RT POWER E POWER HRGE POWER LWYS LWYS LWYS LWYS LWYS LWYS LWYS LWYS NT Thermal Protection V V HRGE PUMP POWER LWYS LWYS V_S V_S.V V LN/T/IR POWER US POWER S_ON S_ON S-S S-S PU ORE PWR H_ORIHOT# H/W Throttling PU PM_THRMTRIP# WIRE-N SYS_SHN# V/ V SYS PWR V V H/O/odec/TP/RT/HMI POWER MINON S V.VSUS.V_R_VTT.V.V.V PH/GPU/Peripheral component POWER PU/SOIMM ORE POWER SOIMM Termination POWER MINON SUSON MINON S S-S S PH SMLLERT# FN river FN VGFX_XG.V variation.v Internal GPU POWER PU/PH/raidwood POWER GFX_ON MINON S S SM-us.V.V_VTT.V.V or.v MINI R/NEW R POWER PU VTT POWER MINON MINON S S E PUFN#.V.V PH ORE POWER MINON S V_ORE variation PU ORE POWER VRON S LV.V L POWER LVS_VEN S V_GPU V SWITHLE PWM I POWER dgpu_pwr_en# iscrete enable GPU_ORE.V~.V GPU ORE POWER V_ iscrete enable GPU_IO.V~.V GPU I/O POWER PG_GPUIO_EN iscrete enable.v_gpu.v VRM ORE POWER PG_.V_EN iscrete enable.v_gpu.v GPU_RE/LVS/PLL POWER.V_GPU iscrete enable V V P/PEG POWER PG_V_EN iscrete enable Quanta omputer Inc. PROJET : ZY Size ocument Number Rev PWR Status & GPU PWR RL & THRM Wednesday, January, ate: Sheet of

3 .V L m(mil) close L LMG/._.V_LK ohm/. R *_ *u/.v_ V L LMG/._.u/V_.u/V_ V_LK [] LK_IH_M close L u/.v_.u/v_.u/v_ SLGSPV SLGSPV STUFF L (default) STUFF R.u/V_ p_ p_ R _ REV : chenge pin define for -test LK_ST LK_SLK PU_SEL XTL_IN Y XTL_OUT.MHZ U V_OT V_SR V_PU V_ V_REF S SL REF_/PU_SEL XTL_IN XTL_OUT VSS_OT VSS_ VSS_ST VSS_SR VSS_PU VSS_REF GN SLGLVV V_SR_I/O V_PU_I/O OT_ OT_# M M_SS SR_/ST SR_#/ST# SR_ SR_# *PU_STOP# PU_ PU_# PU_ PU_# KPWRG/P# VIO_LK R R LK_UF_REFLK [] LK_UF_REFLK# [] TP TP V LK_UF_LK [] LK_UF_LK# [] *_ For TI suggest m(mil) M_LK [] LK_UF_REFSSLK [] LK_UF_REFSSLK# [] LK_UF_PIE_GPLL [] LK_UF_PIE_GPLL# [] KPHST..u/V_.u/V_ For EMI LK_IH_M M_LK close L u/yv_.v Switch LK_UF_REFSSLK and LK_UF_PIE_GPLL on ver (ST) R K_ L *p/v_ *p/v_ PU_LK select SMus V LK Enable V.V R *.K_ PU_SEL R.K_ R.K_ LK_ST [] IH_SMT LK_ST [,,,,] Q NK V [] VR_PWRG_K# R K/F_ K_PWRG_R Q NK R K/F_ PU_SEL PU/=MHz (default) PU/=MHz [] IH_SMLK Q NK R.K_ LK_SLK LK_SLK [,,,,] Quanta omputer Inc. Size ocument Number Rev lock Generator PROJET : ZY ate: Wednesday, January, Sheet of

4 UURNLE/LRKSFIEL PROESSOR (MI,PEG,FI) UURNLE/LRKSFIEL PROESSOR (LK,MIS,JTG) U PEG_OMP R./F_ PEG_IOMPI PEG_IOMPO [] MI_TXN MI_RX#[] PEG_ROMPO PEG_RIS [] MI_TXN R /F_ MI_RX#[] PEG_RIS [] MI_TXN MI_RX#[] PEG_RXN[..] [] PEG_RXN [] MI_TXN MI_RX#[] PEG_RX#[] K PEG_RXN PEG_RX#[] J PEG_RXN [] MI_TXP MI_RX[] PEG_RX#[] J PEG_RXN [] MI_TXP MI_RX[] PEG_RX#[] G PEG_RXN [] MI_TXP MI_RX[] PEG_RX#[] G PEG_RXN [] MI_TXP MI_RX[] PEG_RX#[] F PEG_RXN PEG_RX#[] F PEG_RXN [] MI_RXN MI_TX#[] PEG_RX#[] PEG_RXN [] MI_RXN G Use reverse type MI_TX#[] PEG_RX#[] E PEG_RXN [] MI_RXN F MI_TX#[] PEG_RX#[] PEG_RXN [] MI_RXN H MI_TX#[] PEG_RX#[] (at GPU side) PEG_RXN PEG_RX#[] [] H_PEI PEG_RXN [] MI_RXP MI_TX[] PEG_RX#[] PEG_RXN [] MI_RXP F MI_TX[] PEG_RX#[] PEG_RXN [] MI_RXP E MI_TX[] PEG_RX#[] PEG_RXN [] MI_RXP G MI_TX[] PEG_RX#[] [] H_PROHOT# PEG_RXP[..] [] PEG_RXP PEG_RX[] J PEG_RXP PEG_RX[] H PEG_RXP PEG_RX[] H PEG_RXP [] FI_TXN E FI_TX#[] PEG_RX[] F PEG_RXP [] FI_TXN FI_TX#[] PEG_RX[] G PEG_RXP [] FI_TXN FI_TX#[] PEG_RX[] E PEG_RXP [] FI_TXN FI_TX#[] PEG_RX[] F PEG_RXP [] FI_TXN G FI_TX#[] PEG_RX[] PEG_RXP [] FI_TXN E FI_TX#[] PEG_RX[] F PEG_RXP [] FI_TXN F FI_TX#[] PEG_RX[] PEG_RXP [] FI_TXN G FI_TX#[] PEG_RX[] PEG_RXP PEG_RX[] PEG_RXP PEG_RX[] [] PM_SYN PEG_RXP [] FI_TXP FI_TX[] PEG_RX[] PEG_RXP [] FI_TXP FI_TX[] PEG_RX[] PEG_TXN[..] [] PEG_RXP [] FI_TXP FI_TX[] PEG_RX[] [] FI_TXP FI_TX[] PEG_TXN.u/XR_ PEG_TXN [] FI_TXP G FI_TX[] PEG_TX#[] L PEG_TXN PEG_TXN [] FI_TXP E FI_TX[] PEG_TX#[] M.u/XR_ [] H_PWRGOO PEG_TXN PEG_TXN [] FI_TXP F FI_TX[] PEG_TX#[] M.u/XR_ PEG_TXN.u/XR_ PEG_TXN [] FI_TXP G FI_TX[] PEG_TX#[] M PEG_TXN PEG_TXN [,] PM_RM_PWRG FI_FSYN_R PEG_TX#[] L.u/XR_ F PEG_TXN PEG_TXN FI_FSYN_R FI_FSYN[] PEG_TX#[] K.u/XR_ E PEG_TXN PEG_TXN FI_FSYN[] PEG_TX#[] M.u/XR_ PEG_TXN PEG_TXN FI_INT_R PEG_TX#[] J.u/XR_ PEG_TXN PEG_TXN FI_INT PEG_TX#[] K.u/XR_ PEG_TXN.u/XR_ PEG_TXN FI_LSYN_R PEG_TX#[] H F PEG_TXN PEG_TXN FI_LSYN_R FI_LSYN[] PEG_TX#[] H.u/XR_ PEG_TXN PEG_TXN FI_LSYN[] PEG_TX#[] F.u/XR_ PEG_TXN PEG_TXN PEG_TX#[] E.u/XR_ PEG_TXN PEG_TXN PEG_TX#[].u/XR_ PEG_TXN.u/XR_ PEG_TXN [,,,,,] PLTRST# PEG_TX#[] PEG_TXP[..] [] PEG_TXN PEG_TXN PEG_TX#[].u/XR_ MI Intel(R) FI PI EXPRESS -- GRPHIS PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] L M M L M K M H K G G F E PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP.u/XR_.u/XR_.u/XR_.u/XR_.u/XR_.u/XR_.u/XR_.u/XR_.u/XR_.u/XR_.u/XR_.u/XR_.u/XR_.u/XR_.u/XR_.u/XR_ PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP Processor ompensation Signals R R R R R PM_THRMTRIP# H_PURST#_R R T /F_ /F_.K/F_./F_./F_ *K_ H_OMP H_OMP H_OMP H_OMP TP_SKT# H_TERR# H_VTTPWRG H_PWRG_XP PU_PLTRST# R /F_ T T G T H K T N K P L N N K M M L U OMP OMP OMP OMP SKTO# TERR# PEI PROHOT# THERMTRIP# RESET_OS# PM_SYN VPWRGOO_ VPWRGOO_ SM_RMPWROK VTTPWRGOO TPPWRGOO RSTIN# larksfield/uburndale MIS THERML PWR MNGEMENT LOKS R MIS JTG & PM LK LK# LK_ITP LK_ITP# PEG_LK PEG_LK# PLL_REF_SSLK PLL_REF_SSLK# SM_RMRST# SM_ROMP[] SM_ROMP[] SM_ROMP[] PM_EXT_TS#[] PM_EXT_TS#[] PRY# PREQ# TK TMS TRST# TI TO TI_M TO_M R# PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] R T E F L M N N P T P N P T T R R P N J K K J J H K H LK_ITP_P LK_ITP_N SM_ROMP_ SM_ROMP_ SM_ROMP_ XP_PRY# XP_PREQ# XP_TLK XP_TMS XP_TRST# XP_TI XP_TO XP_TI_M XP_TO_M H_R#_R XP_OS XP_OS XP_OS XP_OS XP_OS XP_OS XP_OS XP_OS R R R R R R LK_PU_LK [] LK_PU_LK# [] LK_PIE_GPLL [] LK_PIE_GPLL# [] R R R R T T PU_R_RMRST# [] T T T T T T T T T E@_ E@_ /F_./F_ /F_ K_ K_ *Short_ REV : no stuff for -test PM_EXTTS# [,].V_VTT PM_EXTTS# [,] PU_R_RMRST# PLL_REF_SSLK [] PLL_REF_SSLK# [] REV : Modify for -test REV : Short XP_RST# [] R *K_ larksfield/uburndale Thermaltrip protect VTT PWR_Good Processor pull-up.v_vtt [,] ELY_VR_PWRGOO PM_THRMTRIP# [] PM_THRMTRIP# pull-up ohm close to PH.V_VTT Q FVN R K_ Q MMT SYS_SHN# [,] [] MPWROK V.u/V_ R K/F_ U TSHFU H_VTTPWRG R K_ XP_TO H_TERR# H_PROHOT# H_PURST#_R XP_TMS XP_TI XP_PREQ# XP_TO_M XP_TLK XP_TRST# / REV: MOIFY Y G. R.K/F_ R K/F_.V_PUVQ If S leakage circuit is realized, the PU and P resistors must be un-staff. PM_RM_PWRG R /F_ R./F_ R _ R *_ R *_ R *_ R *_ R */F_ R R Use a voltage divider with VQ (.V) rail (ON in S) and resistor combination of.k (to VQ)/K(to GN) to generate the required voltage. Note: R uses a.v (always ON) rail with K and K combination. *_ /F_ FI_FSYN_R [] FI_FSYN FI_FSYN_R [] FI_FSYN FI_INT_R [] FI_INT FI_LSYN_R [] FI_LSYN FI_LSYN_R [] FI_LSYN R E@K_ R E@K_ R E@K_ R E@K_ R E@K_ Quanta omputer Inc. PROJET : ZY Size ocument Number Rev UURN / Wednesday, January, ate: Sheet of

5 UURNLE/LRKSFIEL PROESSOR (R) U U [,] M Q[:] [,] M S# [,] M S# [,] M S# [,] M S# [,] M RS# [,] M WE# M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q E F E F E E H G K J G G J J L M M L L K N P H F K K F G J J J J L K K L K L N M R L M N T P M N M T T L R P U E E S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_S[] S_S[] S_S[] S_S# S_RS# S_WE# R SYSTEM MEMORY S_K[] S_K#[] S_KE[] S_K[] S_K#[] S_KE[] S_S#[] S_S#[] S_OT[] S_OT[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] P Y Y P E E F H M G M N N F J N H K P T F H M H K N R Y W V V T Y U T U G T V M M M M M M M M M M M M M M M M M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS M QS M QS M QS M QS M QS M QS M QS M M M M M M M M M M M M M M M M M LK [] M LK# [] M KE [] M LK [] M LK# [] M KE [] M S# [] M S# [] M OT [] M OT [] M M[:] [,] M QS#[:] [,] M QS[:] [,] M [:] [,] [,] M Q[:] [,] M S# [,] M S# [,] M S# [,] M S# [,] M RS# [,] M WE# M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q E F F F F G H G J J G G J J J K L M K K M N F G J K G G J H K K M N K K M M P N T N N N T T N P P T T P R T W R Y S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_S[] S_S[] S_S[] S_S# S_RS# S_WE# R SYSTEM MEMORY - S_K[] S_K#[] S_KE[] S_K[] S_K#[] S_KE[] S_S#[] S_S#[] S_OT[] S_OT[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] W W M V V M E H K H L R T F J L H L R R E H M G L P R U V T V R T R R R R P R F P N M M M M M M M M M M M M M M M M M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS M QS M QS M QS M QS M QS M QS M QS M M M M M M M M M M M M M M M M M LK [] M LK# [] M KE [] M LK [] M LK# [] M KE [] M S# [] M S# [] M OT [] M OT [] M M[:] [,] M QS#[:] [,] M QS[:] [,] M [:] [,] larksfield/uburndale hannel Q[,,,], M[] Requires minimum mils spacing with all other signals, including data signals. larksfield/uburndale hannel Q[,,,,,,,,] Requires minimum mils spacing with all other signals, including data signals. Size ocument Number Rev UURN / Quanta omputer Inc. PROJET : ZY ate: Wednesday, January, Sheet of

6 u/.v_ u/.v_ u_ u/.v_ u/.v_ *u/v_ u_ u_ u_ u/.v_ u/.v_ u/v_ u_ u_ u/.v_ u/.v_ u_ u_ u/.v_ u/.v_ *u/v_ u_ u_ u/.v_ PU ore Power R: F: u_ u_ u/.v_ u_ u/.v_ u/v_ u_ u/.v_ V_ORE u_ u_ u/.v_ u/.v_ UF G V G V G V G V G V G V G V G V G V G V F V F V F V F V F V F V F V F V F V F V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V Y V Y V Y V Y V Y V Y V Y V Y V Y V Y V V V V V V V V V V V V V V V V V V V V V U V U V U V U V U V U V U V U V U V U V R V R V R V R V R V R V R V R V R V R V P V P V P V P V P V P V P V P V P V P V PU ORE SUPPLY POWER SENSE LINES PU VIS.V RIL POWER VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ PSI# VI[] VI[] VI[] VI[] VI[] VI[] VI[] PRO_PRSLPVR VTT_SELET ISENSE V_SENSE VSS_SENSE VTT_SENSE VSS_SENSE_VTT H H H H J J H H G G G G F F F F E E F E Y W U T J J J J N K K K L L M M M G N J J H_PSI# H_VI H_VI H_VI H_VI H_VI H_VI H_VI H_PRSLPVR u_ u/v_ VTT_SENSE VSS_SENSE_VTT VTT Rail Values are uburndal VTT=.V larksfield VTT=.V.V_VTT u_ u_ u_ u_.v_vtt (mils) H_PSI# [] H_VI [] H_VI [] H_VI [] H_VI [] H_VI [] H_VI [] H_VI [] H_PRSLPVR [] H_VTTVI TP H_VTTVI=Low,.V H_VTTVI=High,.V R R u_ u_ u_ /F_ /F_ u_ u_ REV : short R & R for -test I_MON [] V_ORE VSENSE [] VSSSENSE [] TP TP u_ u/v_ u_ VGFX_XG REV : dd,, & for EMI.V_VTT UURNLE/LRKSFIEL PROESSOR and may be @u_ u_ H_VI H_VI H_VI H_VI H_VI H_VI H_VI H_PRSLPVR H_PSI# u_ u_ u_ u_ R K_ R K_ T T T T R R R R P P P P N N N N M M M M L L L L K K K K J J J J H H H H J J H K J J J H G G G F E E R *K_ UG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ larksfield/uburndale.v_vtt R *K_ R K_ GRPHIS FI PEG & MI POWER R *K_ SENSE LINES R K_ GRPHIS VIs R -.V RILS.V.V R *K_ VXG_SENSE VSSXG_SENSE GFX_VI[] GFX_VI[] GFX_VI[] GFX_VI[] GFX_VI[] GFX_VI[] GFX_VI[] GFX_VR_EN GFX_PRSLPVR GFX_IMON VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VPLL VPLL VPLL R T M P N P M P N R T M J F E E Y W W U T T P N N L H P N L K J J J H H H L L M R V_XG_SENSE [] VSS_XG_SENSE [] GFX_VI [] GFX_VI [] GFX_VI [] GFX_VI [] GFX_VI [] GFX_VI [] GFX_VI [] GFX_ON [] GFX_PRSLPVR [] GFX_IMON [] u/v_ u_ u/.v_ u_ u/v_ E@K_ u/v_ u_ u/.v_ u_ u/v_ u/v_ u/v_.v_vpll.u_ S : hecklist request.-k pull-down to GN GFX_ON.V_VTT. R: F: u/v_.u_.v u/v_.v_puvq R *Short_ u_ R *.K_ R *K_ R *K_ R *K_ R K_ R K_ R *K_ R K_ R *K_ R K_ larksfield/uburndale UURNLE/LRKSFIEL PROESSOR (POWER) Note: For Validating IMVP VR R should be STUFF and RN NO_STUFF HFM_VI : Max.V LFM_VI : Min.V Quanta omputer Inc. PROJET : ZY Size ocument Number Rev UURN / (PWR) Wednesday, January, ate: Sheet of

7 UURNLE/LRKSFIEL PROESSOR (GN) UH UI UURNLE/LRKSFIEL PROESSOR( RESERVE, FG) UE T T R R R R R R R R R R R R P P P P P P P N N N N N M M M M M M M M M M L L L L L L L L L K K K K K J J J J J J J J J H H H H H H H H H H H H H H H H G F F F E VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS E E E E E E E E E E Y Y Y W W W W W W W W W W W V U U U T T T T T T T T T T T R P P P N N N N N N N N N N N M L L L L L L K K K K K K K J J J J H H H H H H H H H H H H H G G G G G G F F F F F F E E E E E E E E E E E VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF T T R TP TP TP [] VREF_Q_IMM [] VREF_Q_IMM FG FG FG FG TP TP P RSV L RSV L RSV L RSV J RSV G RSV M RSV L RSV J S_IMM_VREF H S_IMM_VREF G RSV G RSV E RSV E RSV M FG[] M FG[] P FG[] L FG[] L FG[] M FG[] N FG[] M FG[] K FG[] K FG[] K FG[] J FG[] N FG[] N FG[] J FG[] J FG[] J FG[] K FG[] H RSV_TP_ RSV RSV RSV RSV U RSV T RSV RSV RSV RSV_NTF_ RSV_NTF_ J RSV J RSV RSV_NTF_ RSV_NTF_ RSV_NTF_ RSV_NTF_ larksfield/uburndale RESERVE RSV RSV RSV RSV RSV RSV_NTF_ RSV RSV RSV_NTF_ RSV_NTF_ RSV_NTF_ RSV_NTF_ RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV_NTF_ RSV_NTF_ RSV_NTF_ RSV_NTF_ RSV RSV_TP_ RSV_TP_ KEY RSV RSV RSV RSV RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ VSS J J H K L R J J P T T R L L P P L T T P R T T P R R E F J H R R G E V V N W W N E P TP TP TP M LK [] M LK# [] M KE [] M S# [] M OT [] M LK [] M LK# [] M KE [] M S# [] M OT [] M LK [] M LK# [] M KE [] M S# [] M OT [] M LK [] M LK# [] M KE [] M S# [] M OT [] P can be N on R; ES/G suggestion to GN larksfield/uburndale larksfield/uburndale Processor Strapping FG (isplay Port Presence) FG (PI-Epress onfiguration Select) FG (PI-Epress Static Lane Reversal) isabled; No Physical isplay Port attached to Embedded iplay Port Single PEG Normal Operation Enabled; n external isplay port device is connected to the Embedded isplay port ifurcation enabled Lane Numbers Reversed Use reverse type.v_vtt FG[ : ] - PI_Epress onfiguration Select * = x PEG * = x PEG R R R.K/F_.K/F_ *.K/F_ FG FG FG FG R R R R *.K/F_ *.K/F_.K/F_ *.K/F_ S: The FG signals have a default value of '' if not terminated on the board. The larkfield processor's PI Express interface may not meet PI Express. jitter specifications. Intel recommends placing a.k /- % pull down resistor to VSS on FG[] pin for both rpg and G components. This pull down resistor should be removed when this issue is fixed.(es only) Quanta omputer Inc. Size ocument Number Rev UURN / PROJET : ZY ate: Wednesday, January, Sheet of

8 IEX PEK-M (MI,FI,GPIO) [,] SYS_PWROK PM_RM_PWRG [].V [] IH_RSMRST# [] rrandale only U FI_TXN_R FI_RXN FI_TXN_R [] MI_RXN MIRXN FI_RXN H FI_TXN_R [] MI_RXN J MIRXN FI_RXN FI_TXN_R [] MI_RXN W MIRXN FI_RXN J FI_TXN_R [] MI_RXN J MIRXN FI_RXN FI_TXN_R FI_RXN E FI_TXN_R [] MI_RXP MIRXP FI_RXN FI_TXN_R [] MI_RXP G MIRXP FI_RXN [] MI_RXP MIRXP FI_TXP_R [] MI_RXP G MIRXP FI_RXP FI_TXP_R FI_RXP F FI_TXP_R [] MI_TXN E MITXN FI_RXP FI_TXP_R [] MI_TXN F MITXN FI_RXP G FI_TXP_R [] MI_TXN MITXN FI_RXP W FI_TXP_R [] MI_TXN E MITXN FI_RXP FI_TXP_R FI_RXP FI_TXP_R [] MI_TXP MITXP FI_RXP [] MI_TXP H MITXP [] MI_TXP MITXP [] MI_TXP MITXP FI_INT J R E@K_ FI_FSYN F H R E@K_ MI_ZOMP R./F_ MI_OMP FI_FSYN H F R E@K_ MI_IROMP FI_LSYN J R E@K_ FI_LSYN G R E@K_ REV : Modify for -test [] NSWON# PH_IN XP_RST# R XP_RST# RSV_IH_LN_RST# SUS_PWR_K_R *_ IN_R PM_TLOW# T M K M P P SYS_RESET# SYS_PWROK PWROK MEPWROK LN_RST# RMPWROK RSMRST# PWRTN# PRESENT / GPIO TLOW# / GPIO MI System Power Management SUS_PWR_N_K / GPIO FI WKE# LKRUN# / GPIO SUS_STT# / GPIO SUSLK / GPIO SLP_S# / GPIO SLP_S# SLP_S# SLP_M# TP PMSYNH J Y P F E H P K N J SUS_STT# SLP_S#_R SLP_M# R TP TP *_ TP FI_INT [] PIE_WKE# [] LKRUN# [] IH_SUSLK [] SUS# [] SUS# [] PM_SYN [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXP [] FI_TXP [] FI_TXP [] FI_TXP [] FI_TXP [] FI_TXP [] FI_TXP [] FI_TXP [] FI_FSYN [] FI_FSYN [] FI_LSYN [] FI_LSYN [] [] [] [] [] [] [] [] [] [] [] INT_LVS_LON [] INT_LVS_IGON [] [] [] [] [] INT_LVS_EILK INT_LVS_EIT [] [] [] INT_RT_LU INT_RT_GRN INT_RT_RE INT_RT_LK INT_RT_T INT_HSYN INT_VSYN [] [] [] [] [] [] [] [] [] INT_LVS_RIGHT V R R R INT_TXLOUT- INT_TXLOUT- INT_TXLOUT- INT_TXLLKOUT- INT_TXLLKOUT INT_TXLOUT INT_TXLOUT INT_TXLOUT INT_TXULKOUT- INT_TXULKOUT INT_TXUOUT- INT_TXUOUT- INT_TXUOUT- INT_TXUOUT INT_TXUOUT INT_TXUOUT R R @_ INT_RT_LU LV_IG LV_VREFH LV_VREFL INT_TXLLKOUT- INT_TXLLKOUT INT_TXLOUT- INT_TXLOUT- INT_TXLOUT- INT_TXLOUT INT_TXLOUT INT_TXLOUT INT_TXULKOUT- P INT_TXULKOUT P INT_TXUOUT- INT_TXUOUT- INT_TXUOUT- INT_TXUOUT INT_TXUOUT INT_TXUOUT HSYN_G VSYN_G _IREF R K/F_ IEX PEK-M (LVS,I) T T Y Y V P P T T V V Y V Y V Y T U T Y T U T V V Y Y U L_KLTEN L_V_EN L_KLTTL L LK L T L_TRL_LK L_TRL_T LV_IG LV_VG LV_VREFH LV_VREFL LVS_LK# LVS_LK LVS_T# LVS_T# LVS_T# LVS_T# LVS_T LVS_T LVS_T LVS_T LVS_LK# LVS_LK LVS_T# LVS_T# LVS_T# LVS_T# LVS_T LVS_T LVS_T LVS_T RT_LUE RT_GREEN RT_RE RT LK RT T RT_HSYN RT_VSYN _IREF RT_IRTN IbexPeak-M_RP LVS RT igital isplay Interface SVO_TVLKINN SVO_TVLKINP SVO_STLLN SVO_STLLP SVO_INTN SVO_INTP SVO_TRLLK SVO_TRLT P_UXN P_UXP P_HP P_N P_P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT P_UXN P_UXP P_HP P_N P_P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT P_UXN P_UXP P_HP P_N P_P P_N P_P P_N P_P P_N P_P J G J G F H T T G J U J G W Y E V E F H U U T J G J G F H E SVO_TRL_LK SVO_TRL_T P_HP_INT#_R P_LNE_N P_LNE_P P_LNE_N P_LNE_P P_LNE_N P_LNE_P P_LNE_N P_LNE_P R R R TP TP TP TP TP TP TP TP TP TP TP R place close @/F_ INT_RT_LU INT_RT_GRN INT_RT_RE PM_RI# F RI# SLP_LN# / GPIO F PM_SLP_LN# IbexPeak-M_RP PH Pull-high/low V REV : change to K for -test LKRUN# R.K_ XP_RST# R K_ PM_RI# PM_TLOW# PIE_WKE# R R R V_S K_.K_ K_ System PWR_OK *.u_ V_S ELY_VR_PWRGOO need PU K to V. PU at power side IH_RSMRST# R RSV_IH_LN_RST# R SYS_PWROK R K_ K_ K_ PM_SLP_LN# R SUS_PWR_K_R R IN_R R *K_ K_ K_ SYS_PWROK U TSHFU R K_ ELY_VR_PWRGOO [,] PWROK_E [] Size ocument Number Rev IEX PEK-M / Quanta omputer Inc. PROJET : ZY Wednesday, January, ate: Sheet of

9 RT ircuitry VPU VRT_ MIL R K_ mils T VRT R mils R u/v_ K/F_ K/F_ u/v_ u/v_ RT_RST# J *SHORT_ P SRT_RST# J *SHORT_ P VRT P/V_ P/V_ R Y.KHZ R M_ M_ RT_X RT_X RT_RST# SRT_RST# SM_INTRUER# PH_INVRMEN IEX PEK-M (H,JTG,ST) U RTX RTX RTRST# SRTRST# INTRUER# INTVRMEN RT LP FWH / L FWH / L FWH / L FWH / L FWH / LFRME# LRQ# LRQ# / GPIO SERIRQ F PH_RQ# PH_RQ# TP TP R K_ V LP_L [,] LP_L [,] LP_L [,] LP_L [,] LP_LFRME# [,] IRQ_SERIRQ [] VRT_ MIL H us N RT_ML [] [] [] [] PH_Z_OE_SYN PH_Z_OE_RST# PH_Z_OE_SOUT PH_Z_OE_ITLK MIL RT_N Q MMT RT_N R.K/F_ V_S Z_SYN Z_RST# Z_SOUT Z_IT_LK Place all series terms close to PH except for SIN input lines,which should be close to source.placement of R, R, R & R should equal distance to the T split trace point. asically, keep the same distance from T for all series termination resistors. R K/F_ R _ R _ R _ R _ *p_ R K/F_ H_SYN (PH strap pin) Internal weak pull-down VVRM=>.V (default) external pull-up VVRM=>.V PH Strap Table SPKR [] [] SPKR PH_Z_OE_SIN V_S REV : no stuff R for -test No reboot mode setting R V Z_IT_LK Z_SYN Z_RST# Z_SOUT PWROK H_OK_EN# PH_GPIO SPI_LK_R SPI_S#_R SPI_S# SPI_SI_R SPI_SO_R Pin Name Strap description Sampled onfiguration R *K_ R */F_ *K_ TP TP TP TP TP TP TP P G F E F H J M K K J J V Y Y V H_LK H_SYN SPKR H_RST# H_SIN H_SIN H_SIN H_SIN H_SO H_OK_EN# / GPIO H_OK_RST# / GPIO JTG_TK JTG_TMS JTG_TI JTG_TO TRST# SPI_LK SPI_S# SPI_S# SPI_MOSI SPI_MISO IbexPeak-M_RP IH SPI JTG = efault (weak pull-down K) = Setting to No-Reboot mode ST STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STIOMPO STIOMPI STLE# STGP / GPIO STGP / GPIO V K K K K H H H H F F F F H H F F F F T Y V ST_TXN_ ST_TXP_ ST_TXN_ ST_TXP_ ST_RXN_ ST_RXP_ ST_TXN_ ST_TXP_ ST_TXN_ ST_TXP_ ZY note R STOMP SPKR V.V ST_T# [] ST_RX- [] ST_RX [] ST_TX- [] ST_TX [] ST_RX- [] ST_RX [] ST_TX- [] ST_TX [] Note: ST port/ may not be available on all PH sku (HM support port only) R R *K_ R K/F_ K/F_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_./F_ ST_RX- [] ST_RX [] ST_TX- [] ST_TX [] ST_RX- [] ST_RX [] ST_TX- [] ST_TX [] ST H ST O E-ST N ST H PH SPI SPI_S#_R SPI_LK_R SPI_SI_R SPI_SO_R V R *p_.k/f_ U E# SK SI SO WP# V HOL# VSS WXVSSIG t / add Winbond WXVSSIG KEZPN EON ENF-HIP KEZQ MI L KEZN R.K/F_ V.u/XR_ INIT_V GNT# / GPIO INTVRMEN GNT# / GPIO GNT# GNT# / GPIO NV_LE Reserved Top-lock Swap Override Integrated.V VRM enable oot IOS Selection [bit-] oot IOS Selection [bit-] ESI strap (Server only) PWROK PWROK LWYS PWROK PWROK PWROK = efault (weak pull-up K) Should not be pull-down = "top-block swap" mode = efault (weak pull-up K) Should be always pull-up GNT# GNT# Should not be pull-down (weak pull-up K) oot Location Intel nti-theft H protection PWROK = isable (Internal pull-down ohm) SPI PI LP VRT NV_LE PI_GNT# [] PH_INVRMEN efault weak pull-up on GNT/# [Need external pull-down for LP IOS] V R *K_ R *K_.V R R R R R *K_ K_ K_ USE GPIO PIN *K_ K_ PI_GNT# [] PI_GNT# [] NV_LE [] swap override Strap/Top-lock Swap Override jumper PI_GNT# oot IOS Strap GNT# anbury Technology Enabled NV_LE Low = swap override/top-lock Swap Override enabled High = efault GNT# oot IOS Location LP Reserved (NN) PI SPI High = Enable Low = isable NV_LE H_OK_EN#/GPIO MI Termination voltage Flash escriptor Security PWROK PWROK weak pull-down ohm = Override = efault (weak pull-up K).V R R V R *K_ NV_LE *K_ *K_ NV_LE [] H_OK_EN# MI Termination Voltage Set to Vcc when LOW NV_LE Set to Vcc/ when HIGH SPI_MOSI H_SO GPIO itpm function isable MEPWROK = efault (weak pull-down K) Reserved Reserved RSMRST# RSMRST# = Enable Should not be pull-up (weak pull-down K) Should not be pull-down (weak pull-up K) V_S V R *K_ R K_ SPI_SI_R RSV_GPIO [] GPIO H_SYN GPIO On-die PLL Voltage Regulator On-die PLL PWR supply select Reserved RSMRST# RSMRST# RSMRST# = isable = Enable (weak pull-up K) =.V supply (weak pull-down K) =.V supply = TLS no onfidentiality (weak pull-down K) = TLS onfidentiality use defaul ( =.V supply) V_S R K_ R_WKE# [] Quanta omputer Inc. PROJET : ZY Size ocument Number Rev IEX PEK-M / Wednesday, January, ate: Sheet of

10 IEX PEK-M (PI,US,NVRM) IEX PEK-M (PI-E,SMUS,LK) [] [] LK_LP_EUG LK_PI_ [] [] [] [] [] For EMI [] LK_PI_F LK_LP_EUG LK_PI_ LK_PI_F dgpu_selet# PI_GNT# PI_GNT# PWM_SELET# PI_GNT# PI_RST# TP TP R _ T R _ R _ PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_REQ# PI_REQ# dgpu_selet# PI_REQ# PI_GNT# PI_GNT# PI_GNT# PI_PIRQE# PI_PIRQF# PI_PIRQG# PI_PIRQH# PI_RST# PI_SERR# PI_PERR# PI_IRY# PI_PR PI_EVSEL# PI_FRME# PI_PLOK# PI_STOP# PI_TRY# IH_PME# PI_PLTRST# LK_LP_EUG_ LK_PI_PR LK_PI LK_PI_F_ H N J E H E M M F M M J K F K M J K L F J G F M H J G H G G H F M F K F H K K E E H F M N P P P P UE /E# /E# /E# /E# PIRQ# PIRQ# PIRQ# PIRQ# REQ# REQ# / GPIO REQ# / GPIO REQ# / GPIO GNT# GNT# / GPIO GNT# / GPIO GNT# / GPIO PIRQE# / GPIO PIRQF# / GPIO PIRQG# / GPIO PIRQH# / GPIO PIRST# SERR# PERR# IRY# PR EVSEL# FRME# PLOK# STOP# TRY# PME# PLTRST# LKOUT_PI LKOUT_PI LKOUT_PI LKOUT_PI LKOUT_PI PI NVRM US NV_E# NV_E# NV_E# NV_E# NV_QS NV_QS NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_LE NV_LE NV_ROMP NV_R# NV_WR#_RE# NV_WR#_RE# NV_WE#_K NV_WE#_K USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USRIS# USRIS O# / GPIO O# / GPIO O# / GPIO O# / GPIO O# / GPIO O# / GPIO O# / GPIO O# / GPIO Y P V G P P T T V E J J G Y U V Y Y V F H J N P J L F G M N H J E F G H L M N J F L E G F T NV_LE NV_LE NV_ROMP US_IS US_O# US_O# US_O# US_O# US_O# US_O# US_O# US_O# raidwood : ZY no use. R USP- [] USP [] USP- [] USP [] USP- [] USP [] USP- [] USP [] USP- [] USP [] USP- [] USP [] USP- [] USP [] USP- [] USP [] USP- [] USP [] USP- [] USP [] R NV_LE [] NV_LE [] *./F_ Port and port can be used on debug mode M/ US Finger Printer EXT-US LUETOOTH US port/ may not be available on all PH sku (HM support port only)./f_ amera EST US Mini ard (WWN) EXT-US- EXT-US- Mini ard (WLN) EHI EHI LN Mini TV OZ MiniWLN Mini TV MiniWLN OZ LN [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] LK_PH_SR# LK_PH_SR [] [] [] PIE_RX- PIE_RX PIE_TX- PIE_TX PIE_RX- PIE_RX PIE_TX- PIE_TX PIE_RX- PIE_RX PIE_TX- PIE_TX PIE_RX- PIE_RX PIE_TX- PIE_TX [] LKREQ_TV# LK_PH_SR# LK_PH_SR LKREQ_WLN# LK_PH_SR# LK_PH_SR LK_PIE_REQ# LK_PIE_LOM# LK_PIE_LOM LK_PIE_LN_REQ# IbexPeak-M_RP *p/v_ *p/v_ *p/v_ LK_IH_M R *_ *p/v_ LK_PI_F R *_ *p/v_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ Note: PIE port/ may not be available on all PH sku (HM support port only) REV :, dd for -test R R R.u_.u_.u_.u_.u_.u_.u_.u_ *_ *Short_ *Short_ T T T T LK_PIE_REQ# LK_PIE_REQ#_R LK_PIE_REQ# LK_PIE_REQ#_R LK_PIE_REQ#_R LK_PIE_REQ# G J F H W U T U V E F H G J W T U U V G J G J K K P M M U M M N H H M M M J J H K K P U PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP LKOUT_PIEN LKOUT_PIEP PIELKRQ# / GPIO LKOUT_PIEN LKOUT_PIEP PIELKRQ# / GPIO LKOUT_PIEN LKOUT_PIEP PIELKRQ# / GPIO LKOUT_PIEN LKOUT_PIEP PIELKRQ# / GPIO LKOUT_PIEN LKOUT_PIEP PIELKRQ# / GPIO LKOUT_PIEN LKOUT_PIEP PIELKRQ# / GPIO LKOUT_PEG N LKOUT_PEG P PI-E* PEG LKRQ# / GPIO IbexPeak-M_RP SMus From LK UFFER lock Flex ontroller PEG Link SMLERT# / GPIO SMLK SMT SMLLERT# / GPIO SMLLK SMLT SMLLERT# / GPIO SMLLK / GPIO SMLT / GPIO L_LK L_T L_RST# PEG LKRQ# / GPIO LKOUT_PEG N LKOUT_PEG P LKOUT_MI_N LKOUT_MI_P LKOUT_P_N / LKOUT_LK_N LKOUT_P_P / LKOUT_LK_P LKIN_MI_N LKIN_MI_P LKIN_LK_N LKIN_LK_P LKIN_OT_N LKIN_OT_P LKIN_ST_N / KSS_N LKIN_ST_P / KSS_P REFLKIN LKIN_PILOOPK XTL_IN XTL_OUT XLK_ROMP LKOUTFLEX / GPIO LKOUTFLEX / GPIO LKOUTFLEX / GPIO LKOUTFLEX / GPIO H J G M E G T T T H N N T T W P P F E H H P J H H F T P T N RSV_SMLERT# IH_SMLK IH_SMT RSV_SMLLERT# SM_LK_ME SM_T_ME RSV_SMLLERT# SM_LK_ME SM_T_ME L_LK L_T L_RST# PEG_LKREQ#_R LK_PI_F XTL_IN XTL_OUT XLK_ROMP LK_FLEX LK_FLEX LK_FLEX R R IH_SMLK [] IH_SMT [] For LN For E L_LK [] L_T [] L_RST# [] LK_PIE_VG# [] LK_PIE_VG [] LK_PIE_GPLL# [] LK_PIE_GPLL [] PLL_REF_SSLK# [] PLL_REF_SSLK [] LK_UF_PIE_GPLL# [] LK_UF_PIE_GPLL [] LK_UF_LK# [] LK_UF_LK [] LK_UF_REFLK# [] LK_UF_REFLK [] LK_UF_REFSSLK# [] LK_UF_REFSSLK [] LK_IH_M [] dgpu_eisel# [] SMLLERT# [,,] PEG_LKREQ# [] T T T R K_ V *_ *_ PEG LKRQ# P for FreeRun, due GPU not support. No stuff XTL_IN and XTL_OUT circuitry until integrated G becomes PH POR. For EMI REV :, igpu stuff for -test, hage PLTRST# PI_PLTRST# V_S dd uffers as needed for Loading and fanout concerns. U TSHFU.u_ R K_ PLTRST# [,,,,,] PI/USO# Pull-up US_O# US_O# US_O# US_O# V_S PI_REQ# PI_PIRQ# PI_REQ# PI_PIRQ# V PI_PLOK# PI_SERR# PI_EVSEL# PI_STOP# V RP.K_PR RP.K_PR RP.K_PR V_S US_O# US_O# US_O# US_O# V PI_PIRQH# PI_TRY# PI_FRME# PI_REQ# V PI_PERR# PI_PIRQ# PI_IRY# PI_PIRQ# LK_REQ/Strap Pin V_S R K_ LK_PIE_REQ# R K_ LK_PIE_REQ#_R R K_ LK_PIE_REQ#_R R K_ LK_PIE_REQ# R K_ LK_PIE_LN_REQ# V R K_ LK_PIE_REQ#_R R K_ LK_PIE_REQ# V R K_ dgpu_selet# R.K_ PI_PIRQE# R.K_ PI_PIRQF# R.K_ PI_PIRQG# SMus/Pull-up PEG LKRQ# P for FreeRun, due GPU not support. V_S R *K_ V_S R K_ PEG_LKREQ#_R R K_ R K_ R.K_ R R.K_ K_ R.K_ R.K_ RSV_SMLERT# RSV_SMLLERT# RSV_SMLLERT# IH_SMLK IH_SMT SM_LK_ME SM_T_ME V_S R Q NK.K_ SM_LK_ME [] N_MLK V_S R Q NK.K_ SM_T_ME [] N_MT Quanta omputer Inc. PROJET : ZY Size ocument Number Rev IEX PEK-M / Wednesday, January, ate: Sheet of

11 IEX PEK-M (GPIO,VSS_NTF,RSV) GPU RST# UF [] SIO_EXT_SMI# [] SIO_EXT_SI# [] RSV_GPIO TP [] R_WKE# MUSY# SIO_EXT_SMI# SIO_EXT_SI# OR_I RSV_GPIO LN_ISLE# R_WKE# dgpu_hol_rst# Y J F K T MUSY# / GPIO TH / GPIO TH / GPIO TH / GPIO GPIO LN_PHY_PWR_TRL / GPIO GPIO STGP / GPIO MIS LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP GTE LKOUT_LK_N / LKOUT_PIEN H H F F U M TP_PH_PIEN TP_PH_PIEP TP_PH_PIEN TP_PH_PIEP TP TP TP TP SIO_GTE [] LK_PU_LK# [] [] GPU_RST_OP# V *.u_ PLTRST# [,,,,,] dgpu_hol_rst# U TSHFU R K_ [] dgpu_pwrok TP TP GPIO TP_PH_GPIO STP_PI# F Y H V M TH / GPIO SLOK / GPIO GPIO GPIO GPIO STP_PI# / GPIO GPIO PU LKOUT_LK_P / LKOUT_PIEP PEI RIN# PROPWRG THRMTRIP# M G T E PH_THRMTRIP#_R R /F_ R LK_PU_LK [] H_PEI [] SIO_RIN# [] H_PWRGOO [] /F_ PM_THRMTRIP# [].V_VTT dgpu_pwr_en# should be stable before dgpu_vron enable [,,] SMLLERT# [,,] dgpu_vron [] dgpu_pwr_en# [] RST_GTE# R E suggestion use GPIO for FN control *Short_ dgpu_pwr_en# dgpu_prsnt# GPIO SVE_LE# GPIO SV_SET_UP STGP GPIO STGP / GPIO / TEMP_LERT# is used to alert for E when PU or Graph/Memory controllers' temperature go out of limit. So connecting GPIO to E and avoid this pin to be used for other purpose V V P H F F STLKREQ# / GPIO STGP / GPIO STGP / GPIO SLO / GPIO STOUT / GPIO PIELKRQ# / GPIO PIELKRQ# / GPIO STOUT / GPIO STGP / GPIO GPIO VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ E VSS_NTF_ E VSS_NTF_ F VSS_NTF_ F VSS_NTF_ H VSS_NTF_ H VSS_NTF_ H VSS_NTF_ H VSS_NTF_ J VSS_NTF_ J VSS_NTF_ J VSS_NTF_ J VSS_NTF_ J VSS_NTF_ J VSS_NTF_ J VSS_NTF_ J VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ E VSS_NTF_ E VSS_NTF_ IbexPeak-M_RP NTF RSV TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP N_ N_ N_ N_ N_ INIT_V# TP W Y Y V V F M N J K K M N M N H T P TP_PH TP_PH TP_INT_V TP TP TP GPIO Pull-up/Pull-down TP_PH_GPIO GPIO RST_GTE# GPIO LN_ISLE# SIO_EXT_SMI# SIO_EXT_SI# dgpu_pwr_en# SIO_RIN# SIO_GTE dgpu_hol_rst# STGP GPIO dgpu_prsnt# SVE_LE# STP_PI# GPIO MUSY# SV_SET_UP V_S R K_ R K_ R K_ R *K_ R K_ V R K_ R K_ R K_ V R K_ R K_ R *K_ R K_ R K_ R *K_ R K_ R K_ R K_ R.K_ R K_ SV_SET_UP -X High = Strong (efault) GPIO R K_ REV :, hange V_S to V V R *K_ OR_I R K_ dgpu_prsnt# R K_ dgpu always exist Integrated lock hip Enable OR_I High = iscrete Low = SW RSV_GPIO High = isable Low = Enable Size ocument Number Rev IEX PEK-M / Quanta omputer Inc. PROJET : ZY ate: Wednesday, January, Sheet of

12 IEX PEK-M (POWER) m(mils).v.v.v VORE(.V) =.(mils).v.v m(mils) VIO =.(mils).v VRM enable by strap pin GPIO which supply clean.v for [VLK,VPLLEXP,VFIPLL,VSTPLL] L L L R R R L.V uh_ uh_ *uh_ *Short_.V_PH_VPLL_EXP V.LN_VPLL_EXP V.LN_VPLL_FI VVRM=m(mils) R V.LN_V PL u_ V.LN_V PL u_ *Short_ *Short_ *uh_ *u/.v_ *u/.v_.v_vore_ih *Short_ u/v_ u/v_ u/v_ u/v_ u/v_ u/v_ u/.v_ V V.S_.S.V u/v_.u/v_ u/.v_.u/v_ F F F F H H H H J J K J N N N N N N J J T T U U V V W W E E G G H N N N T J M UG V.S_.S VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VIO[] VPLLEXP VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] V_[] VVRM[] VFIPLL VIO[] IbexPeak-M_RP POWER V ORE PI E* FI RT LVS HVMOS MI NN / SPI V[] V[] VSS_[] VSS_[] VLVS VSS_LVS VTX_LVS[] VTX_LVS[] VTX_LVS[] VTX_LVS[] V_[] V_[] V_[] VVRM[] VMI[] VMI[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VME_[] VME_[] VME_[] VME_[] H_SYN (PH strap pin) Internal weak pull-down VVRM=>.V (default) external pull-up VVRM=>.V E E F F H H P P T T T T U M K K K K K M M M M M P P V= m(mils) V L V KPHST..u/V_ u/.v_.u/v_ VLVS= m R VTX_LVS UJ VLK= m(mils).v L *uh_ V.LN_V_LK P V *u/.v_ VLK[] *u/.v_ P VLK[] VLN = m(mils).v R *Short_.V_VUX F VLN[] F.V VLN[] u/v_ TP_PH_VSW Y PSUSYP VTX_LVS= m(mils) VME[] E@_ VME[] VME[] Rev : hange to PYT-Y_ F VME[] V_V_GIO R PYT-Y_ V VME(.V) =.(mils) F VME[] V_ = m(mils).v R *Short_.V_VEPW F VME[].u/V_ R *Short_ u_ V VME[] u_ V VME[] u/v_ V VME[] VVRM= m(mils) u/v_ Y VVRM R *Short_ VME[] V.S_.S Y VME[] VM R *Short_.V_VTTVMI= m(mils) Y VME[] R *_.V VRTEXT V.u/V_ PRT u/v_ V.S_.S U VVRM[] VPNN= m(mils) VPNN R *Short_.V m(mils) V.LN_V PL VPLL[] VPLL[].u/V_ m(mils) V.LN_V PL VPLL[] VPLL[].V H VIO[] J VIO[] VIO =.(mils) H u/v_ VIO[] VME_= m(mils) u/v_ F u/v_ VIO[] V_VME_SPI R *Short_ V H VIO[] F VIO[].u/V_.u/V_ VSST V PSST V.LN_INT_VSUS Y.u/V_ PSUS P VSUS_[] VSUS_ = m(mils) V_S R *Short_ V_S_VPSUS U VSUS_[].u/V_ U VSUS_[] U VSUS_[] V_ =.(mils) V R *Short_ V_VPORE V V_[] V V_[].u/V_ Y V_[] V_PU_IO >m(mils).v_vtt R *Short_ VTT_VPPU T V_PU_IO[].u/V_.u/V_ U.u/V_ V_PU_IO[] VRT= m(mils) VRT VRT IbexPeak-M_RP.u/V_.u/V_ POWER lock and Miscellaneous RT PU PI/GPIO/LP ST PI/GPIO/LP US H VIO[] VIO[] VIO[] VIO[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VIO[] VREF_SUS VREF V_[] V_[] V_[] V_[] V_[] V_[] V_[] VSTPLL[] VSTPLL[] VIO[] VVRM[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VME[] VME[] VME[] VME[] VSUSH VIO =.(mils) V.V V Y u/v_ Y VSUS_ =.(mils) V V_S_VPUS R *Short_ V_S U U U P.u_.u/V_.u/V_ P N N M M L L J J H H G G F F E E U V.V VREF_SUS< m F R /F_ V_S RV- V_S u/v_ VREF< m K R /F_ V RV- V J u/v_ L M V_VPPI R *Short_ V N V_ =.(mils) P.u/V_ U V.u/V_ m(mils) K K V.LN_VPLL L *uh_.v *u/.v_ *u/.v_ VIO =.(mils) H.V T V.S_.S u/v_ H F F F H VME =.(mils).v_vepw Y Y L V._._H_IO R *Short_ V_S VSUSH= m(mils) u/v_ Quanta omputer Inc. PROJET : ZY Size ocument Number Rev IEX PEK-M / Wednesday, January, ate: Sheet of

13 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : IEX PEK-M / Wednesday, January, ZY Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : IEX PEK-M / Wednesday, January, ZY Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : IEX PEK-M / Wednesday, January, ZY IEX PEK-M (GN) VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] E VSS[] E VSS[] F VSS[] F VSS[] P VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] J VSS[] J VSS[] J VSS[] J VSS[] J VSS[] J VSS[] J VSS[] J VSS[] J VSS[] T VSS[] J VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] L VSS[] L VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] U VSS[] M VSS[] V VSS[] M VSS[] M VSS[] VSS[] N VSS[] N VSS[] N VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] R VSS[] R VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] W VSS[] F VSS[] W VSS[] W VSS[] W VSS[] W VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] U VSS[] N VSS[] VSS[] VSS[] V VSS[] U VSS[] M VSS[] M VSS[] N VSS[] H VSS[] VSS[] H VSS[] VSS[] VSS[] UH IbexPeak-M_RP UH IbexPeak-M_RP VSS[] Y VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] G VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] H VSS[] VSS[] VSS[] VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] F VSS[] F VSS[] F VSS[] G VSS[] G VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] VSS[] VSS[] VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] K VSS[] K VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] M VSS[] M VSS[] M VSS[] N VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] N VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] R VSS[] R VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] U VSS[] U VSS[] U VSS[] U VSS[] P VSS[] V VSS[] P VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] E VSS[] E VSS[] F VSS[] F VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] P VSS[] P VSS[] VSS[] F VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] T VSS[] VSS[] T VSS[] VSS[] Y VSS[] T VSS[] M VSS[] T VSS[] M VSS[] K VSS[] K VSS[] V VSS[] K VSS[] K VSS[] H VSS[] H VSS[] J UI IbexPeak-M_RP UI IbexPeak-M_RP

14 M M M M M M M M M M M M M M M M LK_SLK LK_ST M M M M M M M M M M M M M M M M M QS M QS M QS M QS M QS M QS M QS M QS M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS# M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q IMM_S IMM_S V_JM.V_VTT_ SMR_VREF_IMM_ SMR_VREF_Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q SMR_VREF_IMM_ M Q M Q M Q M Q M Q M Q M [:] [,] M S# [,] M S# [,] M S# [,] M S# [,] M RS# [,] M WE# [,] M QS[:] [,] M QS#[:] [,] M M[:] [,] M Q[:] [,] LK_SLK [,,,,] LK_ST [,,,,] R_RMRST# [,,,] PM_EXTTS# [,] SMR_VREF_Q [,] M S# [] M S# [] M LK [] M LK# [] M LK [] M LK# [] M KE [] M KE [] M OT [] M OT [].V_SUS SMR_VREF_IMM_ V_JM.V_SUS.V_VTT_ SMR_VREF_Q V V.V_R_VTT SMR_VREF_IMM_.V_SUS Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM- Wednesday, January, ZY Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM- Wednesday, January, ZY Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM- Wednesday, January, ZY Place these aps near So-imm.. H H S S H H.u/V_.u/V_.u/V_.u/V_.u/V_.u/V_ U/.V_ U/.V_ R K_ R K_ R K_ R K_ u/.v_ u/.v_ /P /# S# S# K K# K K# KE KE S# RS# WE# S S SL S OT OT M M M M M M M M QS QS QS QS QS QS QS QS QS# QS# QS# QS# QS# QS# QS# QS# Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q P R SRM SO-IMM (P) JIM R-IMM_H=._RVS P R SRM SO-IMM (P) JIM R-IMM_H=._RVS u/.v_ u/.v_ U/.V_ U/.V_ u/.v_ u/.v_ R K_ R K_ R *K_ R *K_ u/.v_ u/.v_.u/v_.u/v_ u/v_ u/v_ U/.V_ U/.V_ p/xr_ p/xr_ U/.V_ U/.V_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_.u/v_.u/v_.u/v_.u/v_ R *Short_ R *Short_ R *Short_ R *Short_.u/V_.u/V_.u/.V_.u/.V_.u/.V_.u/.V_ V V V V V V V V V V V V V V V V V V VSP N N NTEST EVENT# RESET# VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VTT VTT GN GN P R SRM SO-IMM (P) JIM R-IMM_H=._RVS P R SRM SO-IMM (P) JIM R-IMM_H=._RVS.u/.V_.u/.V_.u/V_.u/V_ R K_ R K_

15 M M M M M M M M M M M M M M M M LK_SLK LK_ST M M M M M M M M M M M M M M M M M QS M QS M QS M QS M QS M QS M QS M QS M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS# M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q IMM_S IMM_S V_JM.V_VTT_ SMR_VREF_IMM_ M M M M M M M M M M M M M M M M SMR_VREF_Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M [:] [,] M S# [,] M S# [,] M S# [,] M S# [,] M RS# [,] M WE# [,] M QS[:] [,] M QS#[:] [,] M M[:] [,] M Q[:] [,] LK_SLK [,,,,] LK_ST [,,,,] R_RMRST# [,,,] PM_EXTTS# [,] SMR_VREF_Q [,] M S# [] M S# [] M LK [] M LK# [] M LK [] M LK# [] M KE [] M KE [] M OT [] M OT [].V_SUS SMR_VREF_IMM_ V_JM.V_SUS.V_VTT_ SMR_VREF_Q V V.V_R_VTT V SMR_VREF_IMM_ Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM- Wednesday, January, ZY Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM- Wednesday, January, ZY Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM- Wednesday, January, ZY Place these aps near So-imm.. lose to SO-IMM H H S S H H R E@K_ R E@K_ E@u/.V_ E@u/.V_ R E@_ R E@_ E@U/.V_ E@U/.V_ E@.u/V_ E@.u/V_ E@u/.V_ E@u/.V_ E@.u/V_ E@.u/V_ V V V V V V V V V V V V V V V V V V VSP N N NTEST EVENT# RESET# VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VTT VTT GN GN P R SRM SO-IMM (P) JIM E@R-IMM_H=._RVS P R SRM SO-IMM (P) JIM E@R-IMM_H=._RVS E@u/.V_ E@u/.V_ R E@_ R E@_ E@.u/V_ E@.u/V_ R E@_ R E@_ E@U/.V_ E@U/.V_ E@u/.V_ E@u/.V_ R E@_ R E@_ E@U/.V_ E@U/.V_ E@.u/.V_ E@.u/.V_ R E@_ R E@_ E@.u/V_ E@.u/V_ R E@_ R E@_ R *K_ R *K_ /P /# S# S# K K# K K# KE KE S# RS# WE# S S SL S OT OT M M M M M M M M QS QS QS QS QS QS QS QS QS# QS# QS# QS# QS# QS# QS# QS# Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q P R SRM SO-IMM (P) JIM E@R-IMM_H=._RVS P R SRM SO-IMM (P) JIM E@R-IMM_H=._RVS E@.u/.V_ E@.u/.V_ R E@_ R E@_ R E@_ R E@_ E@.u/V_ E@.u/V_ E@.u/V_ E@.u/V_ E@u/V_ E@u/V_ E@u/.V_ E@u/.V_ R E@_ R E@_ E@.u/.V_ E@.u/.V_ E@.u/V_ E@.u/V_ R E@_ R E@_ E@u/.V_ E@u/.V_ E@u/.V_ E@u/.V_ E@U/.V_ E@U/.V_ R E@K_ R E@K_ E@.u/V_ E@.u/V_

16 M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M QS M QS M QS M QS M QS M QS M QS M QS M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS# M Q M Q M Q M Q M Q M Q M Q M Q M Q IMM_S IMM_S V_JM.V_VTT_ SMR_VREF_IMM_ M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q SMR_VREF_IMM_ M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M [:] [,] M S# [,] M S# [,] M S# [,] M S# [,] M RS# [,] M WE# [,] M QS[:] [,] M QS#[:] [,] M M[:] [,] M Q[:] [,] R_RMRST# [,,,] PM_EXTTS# [,] LK_SLK [,,,,] LK_ST [,,,,] SMR_VREF_Q [,] M S# [] M S# [] M LK [] M LK# [] M LK [] M LK# [] M KE [] M KE [] M OT [] M OT [].V_SUS V SMR_VREF_IMM_ V_JM.V_SUS.V_VTT_ SMR_VREF_Q V.V_R_VTT V SMR_VREF_IMM_.V_SUS Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM- Wednesday, January, ZY Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM- Wednesday, January, ZY Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM- Wednesday, January, ZY Place these aps near So-imm.. H H S S H H R K_ R K_ u/.v_ u/.v_ u/.v_ u/.v_ u/v_ u/v_ R K_ R K_ /P /# S# S# K K# K K# KE KE S# RS# WE# S S SL S OT OT M M M M M M M M QS QS QS QS QS QS QS QS QS# QS# QS# QS# QS# QS# QS# QS# Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q P R SRM SO-IMM (P) JIM R-IMM_H=._RVS P R SRM SO-IMM (P) JIM R-IMM_H=._RVS R K_ R K_ p/xr_ p/xr_ U/.V_ U/.V_ u/.v_ u/.v_ R K_ R K_.u/V_.u/V_ U/.V_ U/.V_.u/.V_.u/.V_ u/.v_ u/.v_.u/v_.u/v_ U/.V_ U/.V_.u/V_.u/V_.u/.V_.u/.V_ R *K_ R *K_.u/V_.u/V_ U/.V_ U/.V_.u/V_.u/V_ u/.v_ u/.v_.u/v_.u/v_ V V V V V V V V V V V V V V V V V V VSP N N NTEST EVENT# RESET# VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VTT VTT GN GN P R SRM SO-IMM (P) JIM R-IMM_H=._RVS P R SRM SO-IMM (P) JIM R-IMM_H=._RVS u/.v_ u/.v_ R *Short_ R *Short_ R *Short_ R *Short_.u/V_.u/V_.u/.V_.u/.V_ u/.v_ u/.v_.u/v_.u/v_

17 M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M QS M QS M QS M QS M QS M QS M QS M QS M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS# M Q M Q M Q M Q M Q M Q M Q M Q M Q IMM_S IMM_S V_JM.V_VTT_ M M M M M M M M M M M M M M M M SMR_VREF_IMM_ SMR_VREF_Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M [:] [,] M S# [,] M S# [,] M S# [,] M S# [,] M RS# [,] M WE# [,] M QS[:] [,] M QS#[:] [,] M M[:] [,] M Q[:] [,] R_RMRST# [,,,] PM_EXTTS# [,] LK_SLK [,,,,] LK_ST [,,,,] SMR_VREF_Q [,] M S# [] M S# [] M LK [] M LK# [] M LK [] M LK# [] M KE [] M KE [] M OT [] M OT [].V_SUS V SMR_VREF_IMM_ V_JM.V_SUS.V_VTT_ SMR_VREF_Q V.V_R_VTT V SMR_VREF_IMM_ Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM- Wednesday, January, ZY Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM- Wednesday, January, ZY Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM- Wednesday, January, ZY Place these aps near So-imm.. lose to SO-IMM H H S S H H R E@K_ R E@K_ E@.u/V_ E@.u/V_ E@.u/.V_ E@.u/.V_ E@U/.V_ E@U/.V_ R E@_ R E@_ E@u/.V_ E@u/.V_ E@.u/V_ E@.u/V_ R E@_ R E@_ E@.u/V_ E@.u/V_ E@.u/V_ E@.u/V_ R E@_ R E@_ E@.u/V_ E@.u/V_ E@U/.V_ E@U/.V_ R E@_ R E@_ E@u/V_ E@u/V_ E@.u/.V_ E@.u/.V_ E@u/.V_ E@u/.V_ E@u/.V_ E@u/.V_ R E@_ R E@_ R E@_ R E@_ E@u/.V_ E@u/.V_ V V V V V V V V V V V V V V V V V V VSP N N NTEST EVENT# RESET# VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VTT VTT GN GN P R SRM SO-IMM (P) JIM E@R-IMM_H=._RVS P R SRM SO-IMM (P) JIM E@R-IMM_H=._RVS E@U/.V_ E@U/.V_ E@u/.V_ E@u/.V_ E@U/.V_ E@U/.V_ E@.u/V_ E@.u/V_ R E@_ R E@_ E@.u/V_ E@.u/V_ E@.u/.V_ E@.u/.V_ R E@_ R E@_ E@u/.V_ E@u/.V_ R *K_ R *K_ /P /# S# S# K K# K K# KE KE S# RS# WE# S S SL S OT OT M M M M M M M M QS QS QS QS QS QS QS QS QS# QS# QS# QS# QS# QS# QS# QS# Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q P R SRM SO-IMM (P) JIM E@R-IMM_H=._RVS P R SRM SO-IMM (P) JIM E@R-IMM_H=._RVS E@.u/V_ E@.u/V_ R E@_ R E@_ R E@K_ R E@K_ E@u/.V_ E@u/.V_ R E@_ R E@_