BD6 Shark Bay Block Diagram

Transcription

1 Shark ay lock iagram 0 RL-SOIMM RL-SOIMM P, ual hannel RL RL SYSTEM MEMORY Haswell W/W rpg PEGX Gen P,,,, P_ ep FI MI PEG x HMI ep dgpu nvii NP-GV nvii NM-GL P,,,, 0,, HMI Level Shift P VRM R-M* VRM R-M* EXT_LVS EXT_RT EXT_HMI HMI Level Shift P HMI on. P US- L/ on. P RT on. P HMI on. P ST - H P ST ST0 FI FI(x) MI MI(x) ep to LVS P L US- L/ on. P ST - O P ST ST Touch Panel ard Reader P P US- US- Lynx Point FG 0 US.0 PIe.0 RT PIE- US-0 WLN P0 RT on. P aughter oard US.0 L on. US.0 L on. P US- US- TTERY P zalia RT IH P,, 0,,, LP US.0 SPI PIE- SPI Flash P Giga/0/00 Lan P US-0 US- US.0 R Port US.0 R Port P P LP udio odec E P P MI JK HP SPK on. P P P FN P K/ on. P HLL Sensor P Touch Pad / on. P Power / on. P POWER SYSTEM ISLHRTZ-T RTP TPSRUKR TPSSR ISLHRZ-T RT (harge) (System V/V) (R.V) (+.0V) (+_ORE) (NV_VGPU_ORE) (other GPU) P0 P P P P P P Quanta omputer Inc. PROJET : Size ocument Number Rev lock iagram Thursday, January 0, 0 ate: Sheet of

2 0 Table of ontents PGE - - ESRIPTION Schematic lock iagram Front Page Processor PH OI-FUNTIONS PU LG - RIII SO-IMM R - NP-GV/NM-GL - VRM - R VG VG LE LE 0 H O udio odec theros LN harger System V/V R.V +.0V +VORE H O O LN ard reader MM E HMI comm part Keyoard TP&FP board Power SW HM VG onnector VG PH XP L Panel RT & RT US SWITH HLL SENSOR&K LIGHT SWITH 0 MINI ard (Wi-Fi & WIMX) US onnector US Sleep harger LG EP to LVS LS ischarge GPU_ORE other GPU LS RT HSR MNW US SL K K TP,FP PSW PWM PWM PWM PWM PWM PWM PWM PWM POWER PLNE +VIN +V_RT +V +V_S +VPU +V +V_S +VPU +.VSUS +.V VOLTGE 0V~+V +.0V~+.V +.V +.V +.V +V +V +V +.V +.V ONTROL SIGNL MIN_ON S_ON / Insert enable MIN_ON S_ON / Insert enable S_ON MIN_ON +.0V +.0V MIN_ON +VORE ~ MPWROK S0 +V_GPU +.V GPU_PWR_EN_R +VGPU_ORE ~ GPU_PWR_EN_R +.V_GPU +.V GPU_PWR_G +.0V_GPU +.0V GPU_PWR_G S0 Power States TIVE IN S0~S S0~S S0 S0~S S0~S S0 S0~S S0~S S0~S S0 S0 S0 S0 S0 GN PLNE GN_SIGNL GN GN OGN PGE LL Quanta omputer Inc. PROJET : hief River Size ocument Number Rev POWER STGE & OI-FUNTION Tuesday, ecember, 0 ate: Sheet of

3 Haswell Processor (MI,PEG,FI) <PU/VG> +IO_OUT Haswell Processor (LK,MIS,JTG) <PU> 0 {} MI_TXN0 {} MI_TXN {} MI_TXN {} MI_TXN {} MI_TXP0 {} MI_TXP {} MI_TXP {} MI_TXP {} MI_RXN0 {} MI_RXN {} MI_RXN {} MI_RXN {} MI_RXP0 {} MI_RXP {} MI_RXP {} MI_RXP {} FI_SYN {} FI_INT R 0_ R 0_ Haswell rpg ES MI_RXN_0 MI_RXN_ MI_RXN_ MI_RXN_ 0 0 MI_RXP_0 0 MI_RXP_ 0 MI_RXP_ MI_RXP_ MI_TXN_0 MI_TXN_ MI_TXN_ MI_TXN_ MI_TXP_0 MI_TXP_ MI_TXP_ MI_TXP_ FI_SYN_R H FI_INT_R J FI_SYN ISP_INT HSW_RPG_ES_PG MI FI PEG U PEG_ROMP PEG_ROMP E M PEG_RXN0 PEG_RXN_0 K PEG_RXN PEG_RXN_ M PEG_RXN PEG_RXN_ L0 PEG_RXN PEG_RXN_ M PEG_RXN PEG_RXN_ L PEG_RXN PEG_RXN_ M PEG_RXN PEG_RXN_ L PEG_RXN PEG_RXN_ E PEG_RXN_ PEG_RXN_ E PEG_RXN_0 0 PEG_RXN_ E PEG_RXN_ PEG_RXN_ E PEG_RXN_ E PEG_RXN_ L PEG_RXP0 PEG_RXP_0 L PEG_RXP PEG_RXP_ L PEG_RXP PEG_RXP_ K0 PEG_RXP PEG_RXP_ L PEG_RXP PEG_RXP_ K PEG_RXP PEG_RXP_ L PEG_RXP PEG_RXP_ K PEG_RXP PEG_RXP_ F PEG_RXP_ E PEG_RXP_ F PEG_RXP_0 E0 PEG_RXP_ F PEG_RXP_ E PEG_RXP_ F PEG_RXP_ PEG_RXP_ H PEG_TXN0_ PEG_TXN_0 H PEG_TXN_ PEG_TXN_ J PEG_TXN_ PEG_TXN_ H PEG_TXN_ PEG_TXN_ J PEG_TXN_ PEG_TXN_ G0 PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN_ 0 PEG_TXN_ PEG_TXN_0 PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN_ J PEG_TXP0_ PEG_TXP_0 G PEG_TXP_ PEG_TXP_ H PEG_TXP_ PEG_TXP_ G PEG_TXP_ PEG_TXP_ H PEG_TXP_ PEG_TXP_ H0 PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP_ 0 PEG_TXP_ PEG_TXP_0 PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP_ OF R./F_ +.0V PEG_RXN[0..] {} R0 PEG_RXP[0..] {} PEG_TXN[0..] {} EV@0.U/0V_X PEG_TXN0 EV@0.U/0V_X PEG_TXN EV@0.U/0V_X PEG_TXN EV@0.U/0V_X PEG_TXN EV@0.U/0V_X PEG_TXN EV@0.U/0V_X PEG_TXN EV@0.U/0V_X PEG_TXN EV@0.U/0V_X PEG_TXN PEG_TXP[0..] {} EV@0.U/0V_X PEG_TXP0 EV@0.U/0V_X PEG_TXP EV@0.U/0V_X PEG_TXP EV@0.U/0V_X PEG_TXP EV@0.U/0V_X PEG_TXP EV@0.U/0V_X PEG_TXP 0 EV@0.U/0V_X PEG_TXP EV@0.U/0V_X PEG_TXP FI isable(iscrete Only) <OEV> FI_SYN_R FI_INT_R R R OEV@K_ OEV@K_ *0_ 0 *.U/.V_X Thermal Trip & Process HOT<PU> Intel Turbo mode only<pu> {,} ELY_VR_PWRGOO PM_THRMTRIP#_R PU/P of PU <PU> H_PROHOT# H_PWRGOO_R +ST XP PU/P <PU> {} E_PEI {0,} H_PROHOT# 0 {,} PM_THRMTRIP# *0.U/0V_X {} PM_SYN {} H_PWRGOO {} PM_RM_PWRG_R {} PU_PLTRST# {0} LK_PLL_NSLKN {0} LK_PLL_NSLKP {0} LK_PLL_SSLKN {0} LK_PLL_SSLKP {0} LK_PU_LKN {0} LK_PU_LKP R0 _ R0 +.0V EP isable(iscrete Only) <OEV> Reserved For buffer reset of PLTRSRIN# <PU> Q H_PROHOT# +V +.0V N00KW_M 0 R0 00K_ *P/0V_N U R N *0.U/0V_X *K_ R H_PROHOT_E {} H_PROHOT_E {,0,,,,} PLTRST# IN PM_THRMTRIP# {,} +IO_OUT +IO_OUT LK_PLL_SSLKN R0 OEV@0K_ 0K_ +.0V XP_TO R _ XP_TLK R _ XP_TRST# R00 _ K_ SKTO# P TP TERR# N TP E_PEI R K H_PROHOT# R0 _ H_PROHOT#_R M0 M R 0_ PM_SYN_R T R0 0_ H_PWRGOO_R L PM_RM_PWRG_R 0 R 0_ PU_RST#_R T G H F E E Q R0 00K_ METR0-G_00M S_ON +IO_OUT LK_PLL_NSLKN R *OEV@0K_ +IO_OUT LK_PLL_NSLKP R *OEV@0K_ R OEV@0K_ LK_PLL_SSLKP Haswell rpg ES U MIS SKTO SM_ROMP_0 SM_ROMP_ TERR SM_ROMP_ PEI SM_RMRST F_K PROHOT PRY THERMTRIP PREQ TK TMS TRST PM_SYN TI PWRGOO TO SM_RMPWROK R PLTRSTIN PM_N_0 PM_N_ PLL_REF_LKN PM_N_ PLL_REF_LKP PM_N_ SS_PLL_REF_LKN PM_N_ SS_PLL_REF_LKP PM_N_ LKN PM_N_ LKP OF PM_N_ HSW_RPG_ES_PG R LOK THERML PWR JTG P SM_ROMP_0 R 00/F_ R SM_ROMP_ R /F_ P SM_ROMP_ R 00/F_ N PU_RMRST# PU_RMRST# {} R XP_PRY# T TP XP_PREQ# M TP XP_TLK N TP XP_TMS TP0 M XP_TRST# TP M XP_TI L TP XP_TO P TP XP_RST# XP_RST# {,} R0 XP_PM#0 TP N XP_PM# TP N XP_PM# TP P XP_PM# TP P0 XP_PM# TP N XP_PM# TP P XP_PM# TP P XP_PM# TP Q GN OUT N00KW_M *LVG0GW R *.K/F_ PU_PLTRST#_Q R R *0K_ R *0/F_ *_ PU_RST#_R PU_RST#_R R *OEV@0K_ <TH> FN ontrol-->for one FN solution <TH> PU Thermal sensor / M Local TEMP <THP/UG/VG> Rset(Kohm)=0.00T*T-0.0T+. +V VIN +VPU R0 U *IV@NT_0K_ OUT Q *MMT_00M IN- OUT VFN IN+ IN- TH_FN_POWER R0 *00K_ GN IN+ R0 *EV@NT_0K_ R0 *K/F_ S_ON Q0 *N00KW_M R0 R00 *IV@M_ *EV@M_ +V 0 {} VFN.U/.V_X U0 VIN VO GN /FON GN GN VSET GN {} FNSIG TH_FN_POWER 0 FNSIG +V R *0K_ N +VPU R 0_ HYST= for 0 degree Hys. HYST=GN for 0 degree Hys. +VPU_HW_S 0.U/V_Y U HYST G0TU SET GN OT# R R SYS_SHN# R EV@.K/F_ IV@.K/F_ R 0_ S_ON S_ON {0,,} *0K_ *SS_00M +VPU R *00K_ R *K/F_ *LM R *.K/F_ R0 *K/F_ Q0 *N00KW_M PEM.U/.V_X 0-000L Quanta omputer Inc. PROJET : Size ocument Number Rev Haswell / (PEG/MI/FI) ate: Thursday, ecember 0, 0 Sheet of

4 0 PU SM_VREF M PU VREFQ M Haswell Processor (R) Haswell Processor (R) <PU> <PU> <PU> <PU> M Q0 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M 0 M M M M M M M M M 0 M M M M M M M QSN M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSP M QSP M QSP M QSP0 M QSP M QSP M QSP M QSP +VREFQ_S_PU +VREFQ_S_PU +SM_VREF +SM_VREF RMRST_NTRL +VREFQ_S_PU +VREFQ_S_PU RMRST_NTRL M M M 0 M M M M M M M M M 0 M M M M M QSN M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSP M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M Q[:0] {} M Q[:0] {} M LKP0 {} M LKN0 {} M KE0 {} M LKN {} M LKP {} M KE {} M S#0 {} M S# {} M OT0 {} M OT {} M S#0 {} M S# {} M S# {} M RS# {} M WE# {} M S# {} M [:0] {} M QSN[:0] {} M QSP[:0] {} M LKN0 {} M LKP0 {} M KE0 {} M KE {} M LKN {} M LKP {} M S#0 {} M S# {} M OT {} M OT0 {} M S# {} M S# {} M S#0 {} M RS# {} M WE# {} M S# {} M [:0] {} M QSN[:0] {} M QSP[:0] {} RMRST_NTRL {} +VREF PU +VREFQ_S_M +VREFQ_S_M +SM_VREF +VREFQ_S_PU +VREFQ_S_PU +SM_VREF +VREFQ_S_PU +VREFQ_S_PU Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : Haswell / (R I/F) Thursday, ecember 0, 0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : Haswell / (R I/F) Thursday, ecember 0, 0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : Haswell / (R I/F) Thursday, ecember 0, 0 Q *P0GN R 0_ Q *P0GN 0 *0.U/0V_X R *K_ R0 *K_ R *K_ R 0_ Haswell rpg ES OF U HSW_RPG_ES_PG RSV G S_KN0 Y S_K0 S_KE_0 F0 S_KN Y S_K S_KE_ G0 S_KN Y S_K S_KE_ G S_KN Y S_K S_KE_ F S_S_N_0 P S_S_N_ R S_S_N_ P S_S_N_ P S_OT_0 R S_OT_ R S_OT_ R S_OT_ P S_S_0 R S_S_ P S_S_ R0 S_RS R S_WE P S_S P S_M_0 R S_M_ Y S_M_ Y0 S_M_ S_M_ Y S_M_ S_M_ Y S_M_ S_M_ Y S_M_ 0 S_M_0 R S_M_ Y S_M_ F S_M_ P S_M_ S_M_ G S_QS_N_0 P S_QS_N_ P S_QS_N_ P S_QS_N_ J S_QS_N_ L S_QS_N_ H S_QS_N_ S_QS_N_ S_QS_P_0 P S_QS_P_ P S_QS_P_ P S_QS_P_ K S_QS_P_ M S_QS_P_ H S_QS_P_ S_QS_P_ S_Q_0 R S_Q_ T S_Q_ M S_Q_ M S_Q_ R S_Q_ T S_Q_ N S_Q_ N S_Q_ T S_Q_ R S_Q_0 N S_Q_ M S_Q_ T S_Q_ R S_Q_ M S_Q_ N S_Q_ R S_Q_ R S_Q_ M S_Q_ M S_Q_0 T S_Q_ T S_Q_ N S_Q_ N S_Q_ J S_Q_ K S_Q_ J S_Q_ J S_Q_ M S_Q_ N S_Q_0 K S_Q_ K S_Q_ L S_Q_ M S_Q_ L S_Q_ M S_Q_ L S_Q_ M S_Q_ L S_Q_ M S_Q_0 G S_Q_ J S_Q_ G S_Q_ G S_Q_ J S_Q_ J S_Q_ G0 S_Q_ J0 S_Q_ S_Q_ S_Q_0 S_Q_ S_Q_ S_Q_ E S_Q_ S_Q_ E S_Q_ E S_Q_ S_Q_ S_Q_ S_Q_0 E S_Q_ S_Q_ S_Q_ Haswell rpg ES OF U HSW_RPG_ES_PG RSV_ S_K_N_0 U S_K_P_0 V S_KE_0 S_K_N_ U S_K_P_ V S_KE_ S_K_N_ U S_K_P_ V S_KE_ S_K_N_ U S_K_P_ V S_KE_ S_S_N_0 M S_S_N_ L S_S_N_ M S_S_N_ M0 S_OT_0 M S_OT_ L S_OT_ L S_OT_ L0 S_S_0 V S_S_ U S_S_ V0 S_RS U S_WE U S_S U S_M_0 V S_M_ S_M_0 V S_M_ S_M_ S_M_ V S_M_ S_M_ S_M_ V S_M_ U S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_QS_N_0 P S_QS_N_ P S_QS_N_ J S_QS_N_ F S_QS_N_ J S_QS_N_ E S_QS_N_ S_QS_N_ S_QS_P_0 P S_QS_P_ P S_QS_P_ K S_QS_P_ G S_QS_P_ H S_QS_P_ E S_QS_P_ S_QS_P_ S_Q_0 R S_Q_ T S_Q_ M S_Q_ N S_Q_ T S_Q_ R S_Q_ N S_Q_ M S_Q_ M S_Q_ N S_Q_0 M S_Q_ N S_Q_ R S_Q_ T S_Q_ R S_Q_ T S_Q_ J S_Q_ K S_Q_ J S_Q_ K S_Q_0 J0 S_Q_ K0 S_Q_ J S_Q_ K S_Q_ F S_Q_ F S_Q_ F S_Q_ F S_Q_ G S_Q_ G S_Q_0 G S_Q_ G S_Q_ J S_Q_ J S_Q_ J S_Q_ H S_Q_ H S_Q_ H S_Q_ J S_Q_ H S_Q_0 F S_Q_ F S_Q_ S_Q_ S_Q_ S_Q_ F S_Q_ S_Q_ S_Q_ S_Q_ E S_Q_0 S_Q_ S_Q_ S_Q_ E S_Q_ S_Q_ S_Q_ E S_Q_ S_Q_ S_Q_ S_Q_0 E S_Q_ S_Q_ S_Q_ SM_VREF M S_IMM_VREFQ F S_IMM_VREFQ F Q0 *P0GN R 0_ TP R 0_ R 0_ TP

5 0 Haswell Processor (I,eP,FI) <PU> Haswell rpg ES UH {} IV_HMITX# {} IV_HMITX {} IV_HMITX# {} IV_HMITX {} IV_HMITX0# {} IV_HMITX0 {} IV_HMILK# {} IV_HMILK T U I_TXN_0 T0 I_TXP_0 U0 I_TXN_ U I_TXP_ V I_TXN_ U I_TXP_ V I_TXN_ I_TXP_ T U I_TXN_0 U I_TXP_0 V I_TXN_ U I_TXP_ T I_TXN_ U I_TXP_ V I_TXN_ I_TXP_ ep INT_EP_UXN EP_UXN M N INT_EP_UXP EP_UXP EP_HP P E EP_ROMP EP_ROMP R EP_ISP_UTIL P INT_EP_TXN0 EP_TXN_0 R INT_EP_TXP0 EP_TXP_0 N INT_EP_TXN EP_TXN_ P INT_EP_TXP EP_TXP_ P FI_TXN0 FI_TXN_0 R FI_TXP0 FI_TXP_0 N FI_TXN FI_TXN_ P FI_TXP FI_TXP_ TP0 INT_EP_UXN {} INT_EP_UXP {} INT_EP_HP {} R INT_EP_TXN0 {} INT_EP_TXP0 {} INT_EP_TXN {} INT_EP_TXP {} FI_TXN0 {} FI_TXP0 {} FI_TXN {} FI_TXP {}./F_ +IO_OUT P R I_TXN_0 N I_TXP_0 P I_TXN_ P I_TXP_ R I_TXN_ N0 I_TXP_ P0 I_TXN_ I_TXP_ I OF HSW_RPG_ES_PG Quanta omputer Inc. PROJET : Size ocument Number Rev Haswell / (I/eP) Thursday, ecember 0, 0 ate: Sheet of

6 +.V_PU +.V_PU. VQ Output ecoupling Recommendations 0uFx ufx 0uFx0 0U/.V_X IO_OUT_R 0U/.V_X 0U/.V_X 0U/.V_X 0 0U/.V_X OT socket side ontop, on OT inside socket cavity ontop, on OT inside socket cavity {} 00m 00m +_ORE _SENSE 0.U/0V_X 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X +IO_OUT +IO_PH +IO_OUT 0U/.V_X 0U/.V_X 0U/.V_X 00 0U/.V_X R 00_ R 0_ R 0_0 R *0_0 R 0_0 R 0_ 0 0U/.V_X 0U/.V_X 0 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0 0U/.V_X +_ORE _SENSE_R +IO_OUT_R +IO_PH_R +IO_OUT_R H_PU_SVIRT# H_PU_SVILK H_PU_SVIT PWR_EUG_R TP TP TP TP +_ORE TP0 TP TP0 TP TP TP TP Haswell Processor (POWER) TP TP TP TP K L T V E E E E H K N N T T T T W W W W N K L K L E N F W L J L M M L P H P T R R L T L T M M M M0 M L M T Y Y Y Y Y Y0 Y Y Y Y Y RSV RSV RSV RSV VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ RSV RSV RSV Haswell rpg ES _SENSE RSV IO_OUT F_ VOMP_OUT RSV RSV RSV RSV VILERT VISLK VISOUT PWR_EUG RSV_TP RSV_TP RSV_TP RSV_TP OF UE E E E E0 G G E F F F F F F0 F F F F F G H H G0 G H H H H H H0 H H H J J J J J J0 J J J J J G H J K L M N P R T U U V V W W <PU> P P U/.V_X U/.V_X P P0 U/.V_X U/.V_X P P U/.V_X U/.V_X P U/.V_X P U/.V_X P U/.V_X +_ORE P P U/.V_X U/.V_X P P U/.V_X U/.V_X P U/.V_X P U/.V_X +_ORE Power Test Propose <PU> SVI +.0V <PU> Place PU resistor close to PU H_PU_SVIT Place PU resistor close to PU H_PU_SVIRT# H_PU_SVILK R 0_ PWR_EUG_R R *0K_ +IO_OUT R 0/F_ +.0V +.0V R 0_ R0 _ R0 0_ R R 0_ +IO_OUT *0_ 0.U/0V_X +IO_OUT +IO_OUT +IO_PH R0 /F_ *.U/.V_X *.U/.V_X 0 Near R VR_SVIT {} VR_SVIRT# {} VR_SVILK {} HSW_RPG_ES_PG Quanta omputer Inc. PROJET : Size ocument Number Rev Haswell / (POWER) Thursday, ecember 0, 0 ate: Sheet of

7 Haswell rpg ES 0 0 E E0 E E E E E E E E E F F F G G E G E G H H0 H G G H G G H H H H H H J J K K K K K K0 K E Haswell Processor (GN) <PU> Haswell Processor (FG,RSV) <PU> UF Haswell rpg ES UG Haswell rpg ES UI K K0 K K L K T L0 K T RSV_TP L 0 K 0 RSV_TP RSV_TP L K RSV RSV_TP L K RSV_TP L K RSV_TP RSV_TP L K RSV_TP L K W L K W RSV_TP T FG_ROMP R./F_ L0 K R./F_ RSV0 G RSV_TP FG_ROMP R TP L L W TESTLO_G FG_ R 0 L L0 RSV FG_ TP L P TP E L L RSV FG_ P M +_ORE F RSV FG_ TP L L M L M 0 M0 RSV_TP RSV R L M RSV_TP RSV G R L M L RSV M L M RSV_TP RSV M L N RSV W0 RSV F R M0 TP N0 RSV W RSV_TP RSV M N R0./F_ TESTLO W RSV_TP RSV K *K_ M TP M M N TESTLO N T0 RSV E E TP0 M N TP R0 FG_0 N FG P0 FG_ RSV U0 M N TP P FG_ RSV P0 M N0 N FG T FG_ E N FG N FG_ N N E0 N FG T FG_ RSV N R N E N FG N FG_ RSV_TP N E N TP R FG_ E N E P TP T FG_ RSV_TP E0 N E P TP N0 FG_ RSV_TP N F0 P TP P FG_0 F R P FG_ RSV P N0 TP F R N FG_ RSV R N TP N F R TP N FG_ F R0 TP P FG_ RSV L R 0_ N F R FG_ RSV L R0 0_ P P0 F R P F0 R OF P F T P F T0 HSW_RPG_ES_PG P F T P F T W F T R0 F0 T onfiguration Signals: The FG signals have a default value of '' if not terminated on the board. R F T R F T x = Normal operation R F T FG[] PI Express Static Lane Reversal FG R *EV@K_ R F T x0 = Lane numbers reversed R F T R F U x = isabled R F U FG[] ep enable FG R PIV@K_ R G V x0 = Enabled R G V R G V0 x00 = x & x PI Express R G V T0 G V x0 = reserved FG R *EV@K_ T G W FG[:] PI Express ifurcation T G W0 x0 = x PI Express FG R EV@K_ T G W T G W x = x PI Express T G W T G W x = PEG train follow RESET de-asseted T H0 W FG[] PEG defer training FG R *K_ T0 H W x0 = PEG wait for IOS fro training T H Y T H H 0 J L J F J T J0 K _SENSE_R R 0 SENSE {} J _SENSE J RSV K R 00_ J K *.K_ SYS_PWROK_R SYS_PWROK_R {,} 0 OF HSW_RPG_ES_PG OF HSW_RPG_ES_PG Quanta omputer Inc. PROJET : Size ocument Number Rev Haswell / (FG/GN) Thursday, ecember 0, 0 ate: Sheet of

8 Lynx Point (MI,FI,PM) <LG> 0 {} MI_RXN0 {} MI_RXN {} MI_RXN {} MI_RXN U W R0 MI_RXN_0 MI_RXN_ P V0 MI_RXN_ MI_RXN_ LPT_PH_M_ES REV = J FI_RXN_0 L FI_RXN_ FI_TXN0 {} FI_TXN {} Lynx Point (RT,PI,I NTL) <LG> UE LPT_PH_M_EV {} MI_RXP0 {} MI_RXP {} MI_RXP {} MI_RXP Y P0 MI_RXP_0 MI_RXP_ R W0 MI_RXP_ MI_RXP_ MI FI J FI_RXP_0 L FI_RXP_ V TP FI_TXP0 {} FI_TXP {} {} INT_RT_LU {} INT_RT_GRN {} INT_RT_RE T VG_LUE U VG_GREEN V VG_RE REV = P_TRLLK P_TRLT P_TRLLK R0 R R HMI_LK {} HMI_T {} {} MI_TXN0 {} MI_TXN {} MI_TXN {} MI_TXN E0 MI_TXN_0 MI_TXN_ E MI_TXN_ MI_TXN_ Y TP V TP W TP0 {} INT_RT_LK {} INT_RT_T {} INT_HSYN R PIRT@_ M VG LK M VG T RT_HSYN_R N VG_HSYN RT P_TRLT P_TRLLK P_TRLT R N0 N {} MI_TXP0 {} MI_TXP 0 MI_TXP_0 MI_TXP_ {} MI_TXP {} MI_TXP MI_TXP_ MI_TXP_ +.V R 0_ MI_IREF E MI_IREF W TP V TP R.K/F_ MI_ROMP Y MI_ROMP SUSK#_R R SUSK# {,} XP_RST# R 0_ SYS_RESET# M SYS_RESET# System Power Management FI_SYN L L0 FI_INT T FI_IREF U TP U TP R FI_ROMP SWVRMEN L PWROK FI_SYN {} FI_INT {} FI_IREF R 0_ +.V FI_ROMP R.K/F_ SWVREN SWVREN {} PWROK {} INT_VSYN {} PH_RIGHT {,} LVS_KLT_PH {} INT_LVS_IGON R R0 R PIRT@_ RT_VSYN_R N VG_VSYN PIRT@/F IREF U0 OEV@0 IREF U VG_IRTN N EP_KLTTL LVS_KLT_PH K EP_KLTEN G EP_VEN PI_PIRQ# H0 PIRQ# PI_PIRQ# L0 PIRQ# PI_PIRQ# K PIRQ# LVS ISPLY P_UXN H P_UXN K P_UXN J H P_UXP K P_UXP J P_UXP P_HP K0 P_HP K P_HP H HMI_ON_HP_PH {} {} PM_RM_PWRG {,} RSMRST# {} NSWON# {} PH_SLP_WLN# SYS_PWROK_R SYS_PWROK PH_PWROK F0 PWROK PH_PWROK PWROK H RMPWROK J RSMRST# PH_SUSPWRK J SUSWRN#/SUSPWRNK/GPIO0 R 0_ PH_PWRTN# K PWRTN# PH_PRESENT E PRESENT/GPIO (SW) PH_TLOW# K TLOW#/GPIO (SUS) PH_RI# N RI# 0 TP TP PH_SLP_WLN# SLP_WLN#/GPIO (SW) LPT_PH_M_ES/G WKE# LKRUN# (SUS) SUS_STT#/GPIO (SUS) SUSLK/GPIO (SUS) SLP_S#/GPIO (SUS) SLP_S# SLP_S# SLP_# SLP_SUS# PMSYNH SLP_LN# OF K N U Y Y H F F Y G PIE_WKE# LKRUN# SUS_STT# PH_SUSLK PH_SLP_S# PH_SLP_# PH_SLP_SUS# PH_SLP_LN# PIE_WKE# {0,} LKRUN# {} TP R 0_ SUSLK {,} TP SUS# {} *E@0P/0V_ SUS# {,0} TP0 PM_SYN {} PI_PIRQ# M0 PIRQ# {} GPU_HOL_RST# GPU_HOL_RST# GPIO0 (ORE) {,} GPIO GPIO GPIO (ORE) GPU_PWR_EN GPIO (ORE) {} S_IT S_IT 0 GPIO (ORE) GPIO 0 TP0 GPIO (ORE) {} STP_OVR STP_OVR L GPIO (ORE) LPT_PH_M_ES/G GPIO can not P PI (ORE) G PIRQE#/GPIO (ORE) F OR_I PIRQF#/GPIO (ORE) L OR_I PIRQG#/GPIO (ORE) M OR_I0 PIRQH#/GPIO 0 PI_PME# PME# Y PI_PLTRST# PLTRST# OF <LG> O_M# {} OR_I {} OR_I {} OR_I0 {} TP +V R PX@K_ GPU_PWR_EN_R GPU_PWR_EN_R {} {0} GPU_PWR_EN GPU_PWR_EN Q0 PX@MEN00E_00M PH PWROK&PWROK <LG> PLTRST# uffer <LG> +V_S *0.U/0V_X PI PU <LG> PH WKE EVENT<LG> RT IMPENE MTHING <LG> +V PH_TLOW# R.K_ +PSW {,,} ELY_VR_PWRGOO MPWROK R 0_ R *0_ R00 *0_ R 0_ PH_PWROK PH_PWROK PI_PLTRST# U *TSH0FU R *SHORT_ PLTRST# {,0,,,,} R 00K_ R EV@0_ VG_PLTRST# {} GPU_HOL_RST# GPU_PWR_EN O_M# PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# R R R R R R0 R 0K_ 0K_ 0K_.K_.K_.K_.K_ {,} GPIO PH_PWRTN# PIE_WKE# GPIO R R R R0 R0 *S@0K_ S@0K_ NS@0K_ S@0K_ NS@0K_ +PSW +PSW +V_S +PSW +V_S R0 R R PIRT@0/F_ INT_RT_LU PIRT@0/F_ INT_RT_GRN PIRT@0/F_ INT_RT_RE PH PM PU/P <LG> +V SYSPWOK <LG> SW ircuit <LG> Net Name eep Sx Support eep Sx No Support SYS_RESET# LKRUN# R R0 K_.K_ R0 0 PRESENT V N PM_RM_PWRG PH_RI# PH_SUSPWRK R R R +V_S *S@00/F_ 0K_ 0K_ +V_S *0.U/0V_X PH_PRESENT SUSK#_R R 0K_ +PSW R S@0_ Reserve for S R S@0 PRESENT {} SUSK# {} SUS_PWR_K SUSK#_R PWROK V V V N V N SYS_PWROK_R PH_PWROK RSMRST# PH_SLP_LN# PH_SLP_WLN# R R R R R0 0K_ 0K_ 0K_ +PSW *0K_ 0K_ {,} SYS_PWROK_R SYS_PWROK_R U MPWROK *TSH0FU(F) ELY_VR_PWRGOO {,,} MPWROK {,,} *E@0P/0V_ PH_SUSPWRK PWROK PH_SLP_SUS# R 0_ R NS@0_ R S@0_ R S@00K_ R S@0_ SUS_PWR_K {} RSMRST# SYS_HWPG {,} SLP_SUS# {,} SLP_SUS V N Quanta omputer Inc. PROJET : Size ocument Number Rev LPT / (MI/FI/VG) Thursday, ecember 0, 0 ate: Sheet of

9 RT lock.khz (RT) <LG> P/0V_ P/0V_ RT ircuitry (RT) <RT> PU & Password lear <LG> N -T-0-K0 +V Y.KHZ_0 0 *R00V-0_00M R +VPU T--F_00M +R_VRT_R +R_VRT *R00V-0_00M R R K_ R 0K_ R 0K_ R 0K_ R 0K_ RT_X R 0M_ RT_X Trace = 0mils for power +V_RT 0K_ 0 U/.V_X 0K_ 0 RT_RST# G *SHORT P SRT_RST# G U/.V_X U/.V_X *SHORT P SERIRQ G ST_LE# GPIO S_IT0 *SHORT P +V_RT R {} PEEP TP0 {} OR_I RT_X RT_X SRT_RST# M_ SM_INTRUER# PH_INVRMEN RT_RST# H_LK_R H_SYN_Q PEEP H_RST#_R Z_SIN0_UIO H_SO_R GPIO OR_I PH_JTG_TK_R PH_JTG_TMS_R PH_JTG_TI_R PH_JTG_TO_R Lynx Point (RT,IH,ST,JTG) <LG> Lynx Point (LP,SPI,SMUS,-LINK,THERML) <LG> U LPT_PH_M_ES REV = RTX G0 L0 L K G F RTX SRTRST# INTRUER# INTVRMEN RTRST# H_LK H_SYN SPKR H_RST# H_SI0 H_SI H_SI H_SI ST_TXN/PETN ST_TXP/PETP H_SO ST_RXN/PERN OKEN#/GPIO (ORE) ST_RXP/PERP H_OK_RST#/GPIO (SUS) ST_TXN/PETN ST_TXP/PETP ST_ROMP STLE# JTG_TK (ORE) ST0GP/GPIO JTG_TMS (ORE) STGP/GPIO E JTG_TI JTG_TO RT ZLI JTG ST ST_RXN_0 ST_RXP_0 ST_TXN_0 ST_TXP_0 ST_RXN_ ST_RXP_ ST_TXN_ ST_TXP_ ST_RXN_ ST_RXP_ ST_TXN_ ST_TXP_ ST_RXN_ ST_RXP_ ST_TXN_ ST_TXP_ ST_RXN/PERN ST_RXP/PERP R *0_ F TP TP TP {} PM_TEST_RST# R *0_ TP0 ST0RXN E ST0RXP W ST0TXN Y ST0TXP 0 E0 V0 W0 Y W E R T V W E P R Y P T U ST_IREF TP ST_ROMP ST_LE# GPIO S_IT0 ST_IREF TP TP U LPT_PH_M_ES REV = TP TP (SUS) N SMLERT# {0,} L0 L0 0 SMLERT#/GPIO L_0 SMus SLK {0,} L L 0 SMLK R0 L_ ST {0,} L L SMT U L_ (SUS) N RMRST_NTRL_PH {0,} L L SML0LERT#/GPIO0 L_ SM_ME0_LK LFRME# SML0LK U {0,} LFRME# LFRME# SM_ME0_T PH_RQ#0 SML0T R TP0 LRQ0# (SUS) H PH_TEMP_LERT# {} OR_I OR_I G0 SMLLERT#/PHHOT#/GPIO LRQ#/GPIO (ORE) (SUS) K SM_ME_LK {} SERIRQ SERIRQ L SMLLK/GPIO SERIRQ (SUS) N SM_ME_T SMLT/GPIO L_LK PH_SPI_LK_R J L_LK F ST_RXN_O# {} SPI_LK L_T ST_RXP_O {} -Link PH_SPI_S0#_R J L_T F0 SPI_S0# F L_RST# ST_TXN_O# {} PH_SPI_S#_R L L_RST# ST_TXP_O {} SPI_S# J0 ST_RXN_ST_H# {} SPI_S# ST_RXP_ST_H {} PH_SPI_SI_R H TP SPI_MOSI ST_TXN_ST_H# {} Thermal PH_SPI_SO_R H TP ST_TXP_ST_H {} SPI_MISO E PH_SPI_IO J TP R.K/F_ SPI_IO +.V E PH_SPI_IO J TP SPI_IO Y T_IREF R.K_ T_IREF R 0_ XP_FN {} R 0_ OF XP_FN {} LPT_PH_M_ES/G R 0_ +.V LP SPI 0 SLK {,0} ST {,0} RMRST_NTRL_PH {0,} TP TP TP0 PH JTG <LG> JTG_TK,JTG_TMS Trace Length < 000mils +V_S LPT_PH_M_ES/G OF {} PH_JTG_TO {} PH_JTG_TI {} PH_JTG_TMS {} PH_JTG_TK R R R R XP@0_ XP@0_ XP@0_ XP@0_ R XP@0/F_ R XP@00/F_ R XP@0/F_ PH_JTG_TO_R PH_JTG_TI_R PH_JTG_TMS_R PH_JTG_TK_R R0 R XP@00/F_ XP@_ SMus <LG> +V_S R R R R 0K_ 0K_.K_.K_ SMLERT# PH_TEMP_LERT# SLK ST E nd_sm read SML us of PH temps +V_S SM_ME_LK {,} N_MLK R R R0 R.K_.K_.K_.K_ SM_ME0_LK SM_ME0_T SM_ME_LK SM_ME_T Q0 *N00KW_M +V_S H <LG> {} Z_RST#_UIO R _ H_RST#_R +V R *K/F_ {,,0,} SM_RUN_LK R.K_ Q SLK N00KW_M {,} N_MT SM_ME_T Q0 *N00KW_M {} Z_SOUT_UIO {} IT_LK_UIO {} Z_SYN_UIO {} Z_SIN0_UIO R _ R _ R _ H_SO_R H_LK_R *0.U/V_Y H_SYN_R Z_SIN0_UIO H_SYN_R R *M_ R Q *N00K_00M *SHORT_ 0 *P/0V_N H_SYN_Q +V R {,,0,} SM_RUN_T PH STRPING.K_ Q ST N00KW_M PH ual SPI <LG> ME@M PH_SPI_S0#_R PH_SPI_LK_R PH_SPI_SI_R PH_SPI_SO_R +V_S {} PH_SPI_S0# {} PH_SPI_LK {} PH_SPI_SI {} PH_SPI_SO _ R _ R _ R0 _ R0 R.K/F_ PH_SPI_IO R *_ R _ PH_SPI_S0#_RR R _ PH_SPI_LK_RR R0 _ PH_SPI_SO_RR R _ PH_SPI_SI_RR U PH_SPI_S0#_RR PH_SPI_LK_RR E# V PH_SPI_SI_RR SK PH_SPI_SO_RR SI SPI_HOL# R0 SO HOL# SPI_WP# R WP# WQFIQ *P/0V_N +V_S.K/F_ *_ PH_SPI_IO 0 0.U/V_Y Pin Name SPKR GPIO / SUSLK GPIO INTVRMEN GPIO STGP/GPIO H_SO Usage No Reboot PLL On-ie Voltage Regulator Enable Top-lock Swap Override Integrated VRM Enable oot IOS Strap bit oot IOS Strap bit 0 Flash escriptor Security Override / Intel ME ebug Mode Sampled PWROK RSMRST# PWROK lways PWROK PWROK PWROK onfiguration 0 = isable (Int P) = Enable 0 = isable = Enable (Int PU) 0 = Top-lock Swap mode = efault (Int PU) 0 = isable = Enable it it0 0 Resvered SPI 0 0 LP 0 = Security Effect (Int P) = an be Override PEEP {,} SUSLK {} STP_OVR PH_INVRMEN +V R {} S_IT S_IT0 {} Z_SOUT_R 0K_ ircuitry R *K_ R *K_ R0 *K_ R0 0K_ R0 *K_ R *K_ H_SO_R R *K_ +V +V_RT +_H_IO PH_SPI_S#_R PH_SPI_LK_R PH_SPI_SI_R PH_SPI_SO_R R R R R00 *_ PH_SPI_S#_RRR *_ PH_SPI_LK_RR_R *_ PH_SPI_SI_RR_R *_ PH_SPI_SO_R_R 0 *P/0V_N SPI_WP# U E# V SK SI SPI_HOL# SO HOL# WP# *WQIG +V_S *0.U/V_Y GPIO RSV PWROK STGP/GPIO TLS onfidentiality PWROK GPIO RSV RSMRST# GPIO PLL on die VR enable RSMRST# SWVREN On ie SW VR Enable lways Internal P 0 = TLS no confidentiality (Int P) = TLS with confidentiality Internal PU 0 = isable = Enable (Int PU) = Enable 0 = isable Must be PU to RT {} GPIO {} FI_OVRVLTG {} GPIO {} PLL_OVR_EN {} SWVREN R R0 R R R R *K_ K_ 0K_ *K_ 0K_ *0K_ +V +V +V_RT Quanta omputer Inc. PROJET : Size ocument Number Rev LPT / (ST/H/SPI) ate: Thursday, ecember 0, 0 Sheet of

10 0 PIE_IREF PIE_ROMP Lynx Point (PIE,US.0,US.0) <LG,U,MNW> W US0#_R {} Y PERN/USRN USN0 PERP/USRP USP0 US0_R {} US.0(R) US0#_R {} E USN US0_R {} US.0(R) PETN/USTN USP PETP/USTP USN US0#_L {} US0_L {} US.0(L) T USP USPN USPN {} R PERN/USRN USN USPP PERP/USRP USP USPP {} US Touch USN PETN/USTN USP F PETP/USTP USN G USP K {0} PIE_RXN_WLN# W USN L {0} PIE_RXP_WLN Y PERN_ USP G PERP_ USN WLN H {0} PIE_TXN_WLN# 0.U/0V_X PIE_TXN_WLN#_ E USP US_R# {} {0} PIE_TXP_WLN 0.U/0V_X PIE_TXP_WLN_ PETN_ USN PETP_ USP US_R {} (R REER) 0 US0#_L {} {} PIE_RXN_LN# T USN 0 US0_L {} (US.0 L) LN {} PIE_RXP_LN R PERN_ USP US_WLN# PERP_ USN0 US_WLN# {0} US_WLN US_WLN {0} (WLN) {} PIE_TXN_LN# LN@0.U/0V_X PIE_TXN_LN#_ E USP0 US_# US_# {} {} PIE_TXP_LN LN@0.U/0V_X PIE_TXP_LN_ PETN_ USN US_ PETP_ USP US_ {} () G W USN F V PERN_ USP F PERP_ USN G USP PETN_ PETP_ R US0_RXN_R {} Y USRN P US0_RXP_R {} W PERN_ USRP E PERP_ USTN US0_TXN_R {} US.0(R) US0_TXP_R {} USTP W PETN_ US0_RXN_R {} E USRN V PETP_ USRP US0_RXP_R {} US0_TXN_R {} US.0(R) T0 USTN PERN_ USTP US0_TXP_R {} T W PERP_ USRN V E0 USRP E 0 PETN_ USTN PETP_ USTP R N USRN P N PERN_ USRP PERP_ USTN E USTP PETN_ K USOMP R./F_ PETP_ USRIS# K USRIS +.V R0 0_ R.K/F_ E0 0 UI PIE_IREF TP TP PIE_ROMP LPT_PH_M_ES/G LPT_PH_M_ES PIe US TP TP (SUS) O0#/GPIO (SUS) O#/GPIO0 (SUS) O#/GPIO (SUS) O#/GPIO (SUS) O#/GPIO (SUS) O#/GPIO (SUS) O#/GPIO0 (SUS) O#/GPIO OF M L P V U P M T N M US_S_O#_R US_O# GPIO R 0_ GPIO US_O# R 0_ US0_SMI# GPIO0 SI#_R US_Normal_O#_L_Q US_Normal_O#_L_Q US.0 ombo Port EHI EHI xhi LN WLN {0} {0} US.0_S&_O0#(R) US.0_Normal_O#(R) US.0_Normal_O#(L&L) LK_PI_F LK_PIE_REQ# LK_PIE_REQ# 0X LK_PIE_WLN#_R LK_PIE_WLN_R PIE_LK_WLN_REQ# LK_PIE_REQ# LK_PIE_REQ# LK_PIE_REQ# GPIO LK_PIE_XPN LK_PIE_XPP LK_PH_PI0 LK_PH_PI LK_PH_PI LK_PH_PI LK_PH_PI Lynx Point (LOK) <LG> R LN@0X R {} LK_PIE_LN# LK_PIE_LN#_R Y LK_PIE_VGN_R EV@0X {} LK_PIE_LN LKOUT_PIE_N_0 LKOUT_PEG_ LK_PIE_LN_R Y LK_PIE_VGP_R LKOUT_PIE_P_0 LKOUT_PEG P {} PIE_LK_LN_REQ# PIE_LK_LN_REQ# (SUS) (SUS) F LK_PEG_REQ# PIELKRQ0#/GPIO PEG_LKRQ#/GPIO LK_PEG_REQ# {} {0} LK_PIE_WLN# {0} LK_PIE_WLN PIE_LK_WLN_REQ# PLK_EUG {} PLK_ E@.P/0V_ TP00 TP0 R0 TP TP0 R _ R R _ E@.P/0V_ NMP@_ F F T F F V E E 0 E J J Y H H E F 0 U LKOUT_PIE_N_ LKOUT_PIE_P_ PIELKRQ#/GPIO LKOUT_PIE_N_ LPT_PH_M_ES (ORE) LKOUT_PIE_P_ PIELKRQ#/GPIO0/SMI# (ORE) LKOUT_PIE_N_ LKOUT_PIE_P_ PIELKRQ#/GPIO LKOUT_PIE_N_ LKOUT_PIE_P_ PIELKRQ#/GPIO LKOUT_PIE_N LKOUT_PIE_P_ PIELKRQ#/GPIO LKOUT_PIE_N_ LKOUT_PIE_P_ PIELKRQ#/GPIO LKOUT_PIE_N_ LKOUT_PIE_P_ PIELKRQ#/GPIO LKOUT_ITPXP LKOUT_ITPXP_P LKOUT_MHZ0 LKOUT_MHZ LKOUT_MHZ LKOUT_MHZ LKOUT_MHZ LOK SIGNL LPT_PH_M_ES/G (SUS) (SUS) (SUS) (SUS) (SUS) LKOUT_PEG P (SUS) PEG_LKRQ#/GPIO XTL_IN XTL_OUT (ORE) LKOUTFLEX0/GPIO (ORE) LKOUTFLEX/GPIO (ORE) LKOUTFLEX/GPIO (ORE) LKOUTFLEX/GPIO OF LKOUT_PEG_ LKOUT_MI LKOUT_MI_P LKOUT_P LKOUT_P_P LKOUT_PNS LKOUT_PNS_P LKIN_MI LKIN_MI_P LKIN_GN LKIN_GN_P LKIN_OTN LKIN_OTP LKIN_ST LKIN_ST_P REFLKIN LKIN_MHZLOOPK ILK_IREF TP TP IFFLK_ISREF Y Y U F F0 J0 J F F S_STRP LK_PU_LKN_R LK_PU_LKP_R LK_PLL_SSLKN_R LK_PLL_SSLKP_R LK_PLL_NSLKN_R LK_PLL_NSLKP_R Y LK_UF_EXPN WLK_UF_EXPP R T H G E F M L 0 F F F M N LK_UF_PYKN LK_UF_PYKP LK_UF_OTN LK_UF_OTP LK_UF_KSSN LK_UF_KSSP LK_UF_REF LK_PI_F XTL_IN XTL_OUT LK_FLEX0 LK_FLEX LK_FLEX LK_FLEX ILK_IREF ILK_IS TP0 TP TP0 R R R R R *0K_ R 0_ R *.K/F_.K/F_ 0X PIV@0X PIV@0X +V +.V +XK_VRM LK_PIE_VGN {} LK_PIE_VGP {} LK_PU_LKN {} LK_PU_LKP {} LK_PLL_SSLKN {} LK_PLL_SSLKP {} LK_PLL_NSLKN {} LK_PLL_NSLKP {} US_S_O#_R US_O# Q0 R R0 o-lay +V_S S@N00KW_M NS@0_ NS@0_ +V_S Q0 S@N00KW_M R NS@0_ R0 NS@0_ US_S_O# {,} US_Normal_O#_R {,} US Overcurrent PH Intenal lock PH XP Signal Routed by 0 ohm <LG> <LG> +V_S LK_UF_EXPN R 0K_ <LG> +V_S RP 0 US_O# US_O# GPIO GPIO 0KX PIE_LK_WLN_REQ# PIE_LK_LN_REQ# LK_PIE_REQ# LK_PIE_REQ# LK_PIE_REQ# GPIO0 GPIO US_S_O#_R SI#_R US0_SMI# LK_PIE_REQ# LK_PIE_REQ# LK_PEG_REQ# R R R 0K_ LK_UF_EXPP R 0K_ R 0K_ LK_UF_PYKN R 0K_ R 0K_ LK_UF_PYKP R 0K_ XTL_IN P/0V_ R 0K_ LK_UF_OTN R 0K_ US_S_O# R XP@0_ R 0K_ LK_UF_OTP R 0K_ US_O# R XP@0_ R 0K_ LK_UF_KSSN R 0K_ R GPIO R XP@0_ LK_UF_KSSP R 0K_ M_ Y GPIO R XP@0_ +V LK_UF_REF R 0K_ MHZ_0 US_O# R XP@0_ US0_SMI# R XP@0_ R0 0K_ XTL_OUT P/0V_ GPIO0 R XP@0_ R0 0K_ +V_S SI# R XP@0_ LK_PIE_REQ# R0 XP@0_ S_STRP R NS@0K_ LK_PIE_REQ# R0 XP@0_ +V_S R S@0K_ +V_S 0K_ *0K_ {,} RMRST_NTRL_PH RMRST_NTRL_PH R R K_ *0K_ XP_FN0 {} XP_FN {} XP_FN {} XP_FN {} XP_FN {} XP_FN {} XP_FN {} XP_FN {} XP_FN {} XP_FN {} o-lay +V_S Q S@N00KW_M US_Normal_O#_L_Q US_Normal_O#_L {,} o-lay R0 R0 NS@0_ NS@0_ +V_S SI#_R Q S@N00KW_M SI# {} R R0 o-lay NS@0_ NS@0_ Quanta omputer Inc. PROJET : Size ocument Number Rev LPT / (PIE/US/LK) Tuesday, ecember, 0 ate: Sheet of 0

11 {} GPIO TP {} O_PRSNT# {,,} GPU_PWROK {,} GPIO {} PLL_OVR_EN {} GPIO {} FI_OVRVLTG {} TEMP_LERT# {} PH_O_EN GPIO OR_I R0 0_ ox_vendor OR_I0 GPIO GPIO OR_I OR_I OR_I OR_I GPIO OR_I OR_I FI_OVRVLTG OR_I OR_I TEMP_LERT# I_etect PH_O_EN OR_I OR_I OR_I TP NTF Lynx Point (GPIO,PU/MIS,NTF) <LG> UF LPT_PH_M_ES T MUSY#/GPIO0 (ORE) F TH/GPIO (ORE) TH/GPIO (ORE) G TH/GPIO (ORE) Y GPIO (SUS) K LN_PHY_PWR_TRL/GPIO (SUS) GPIO (SUS) N STGP/GPIO (ORE) GPIO TH0/GPIO (ORE) SLOK/GPIO (ORE) Y0 GPIO (SUS) R GPIO (SW) GPIO (SUS) N GPIO (ORE) P GPIO/NMI# (ORE) T STGP/GPIO (ORE) K STGP/GPIO (ORE) T SLO/GPIO (ORE) M STOUT0/GPIO (ORE) N STOUT/GPIO (ORE) K STGP/GPIO (ORE) U GPIO (SUS) TH/GPIO (ORE) TH/GPIO (ORE) G TH/GPIO0 (ORE) H TH/GPIO (ORE) E E LPT_PH_M_ES/G NTF PU/Misc OF TP PEI RIN# PROPWRG THRMTRIP# PLTRST_PRO# N0 Y T V V U N0 E E E E PH_PEI RIN# PH_THRMTRIP# TP R 0_ GTE0 {} RIN# {} H_PWRGOO {} PU_PLTRST# {} XP Signal PM_THRMTRIP# {} +V_S W/ HMI W/O HMI OR I SETTING <LG> oard I I0 I I I I I I I I I I I HM H HM L UM SKU VG SKU VRM-000MHz VRM-00MHz Standard ULV " " GV GL W/ KK W/O KK W/ RT W/O RT Only VG Optimus WIN WIN Reserve EP LVS eleron I/I/I W W +V R0 0K_ GPIO R *0K_ R R0 R R0 IV@0K_ 000M@0K_ OR_I OR_I OR_I OR_I0 OR_I0 {} H L H L L H H L H L H L H L L H H L +V +V +V R EV@0K_ R 00M@0K_ R0 *0K_ H L H L I I I H L H L OR_I {} H L {} XP_FN_LK {} XP_FN_LK {} XP_FN0 {} XP_FN {} XP_FN {} XP_FN PH MIS PU/P R R R R0 R0 R0 XP@0_ XP@0_ XP@0_ XP@0_ XP@0_ XP@0_ GPIO OR_I GPIO FI_OVRVLTG GPIO TEMP_LERT# +V +V +V R R R 0K_ GV@0K_ *0K_ OR_I OR_I OR_I +V R HM@0K_ OR_I +V R0 RT@0K_ OR_I +V R R0 R R GTE0 RIN# R R.K_ 0K_ +.0V GL@0K_ 0K_ NHM@0K_ NRT@0K_ PH_THRMTRIP# R0 *K_ +V +V +V PH GPIO PU/P GPIO TEMP_LERT# O_PRSNT# PH_O_EN R0 R0 R00 R +V *0K_ 0K_ 0K_ 0K_ GPIO FI_OVRVLTG R R0 *0K_ *0K_ R U_@0K_ OR_I R U_@0K_ R S&@0K_ OR_I0 R NS&@0K_ R 0K_ OR_I escription US.0* US.0*&US.0* S& Non S& Reserve I H L I0 L H I H L +V +V_S +V +V +V_S R0 R 0K_ Metal_IMR@0K_ +V R 0K_ R0 EP@0K_ OR_I R LS@0K_ R 0@0K_ OR_I R0 W@0K_ OR_I {} OR_I OR_I {} R0 W@0K_ I_etect R TEXTURE@0K_ ox_vendor R *0K_ ox_vendor {} GPIO W/O K acklight GPIO {,} GPIO H +V +V +V W K acklight L R R R H L GPIO I_etect Speaker Metal/IMR ox TEXTURE oxless GPIO ox Vendor other ONKYO Touch Pad.V(ITP) V(NMTP) GPIO K acklight X Metal(Y) IMR(X) OEV@0K_ W@0K_ 0K_ OR_I OR_I OR_I R0 R R PX@0K_ W@0K_ *0K_ OR_I {} Quanta omputer Inc. PROJET : Size ocument Number Rev LPT / (GPIO/MIS) Wednesday, January 0, 0 ate: Sheet of

12 Lynx Point (Power) <LG> 0m (0mils) + L +V_S +.V PIRT@H0KF-T_. +.0V R 0_ R 0_ m (0mils) +V._PUS 0.U/0V_X +V.0S_US Lynx Point (Power) <LG> UH LPT_PH_M_ES +PSW R 0_ 0.U/0V_X +.0V +.0V. (0mils) R 0_0 +V.0S_PH_ 0 0U/.V_X U/.V_X U/.V_X U/.V_X R./F_ +PH_SW U/.V_X 0m (0mils) R 0_0 +V.0M_SW 0U/.V_X U/.V_X U/.V_X UG 0 E E0 E E E G G0 G G Y U PSUSYP U SW U0 SW U SW U SW V SW V0 SW V SW V SW Y SW Y0 SW Y SW SW LPT_PH_M_ES/G LPT_PH_M_ES RT FI HVMOS ore US PIe/MI ST MPHY P _ P M G_ VRM IO N IO N R0 R0 R R Y PSUS J0 SUS_ J SUS_ J PSUS J PSUS IO K0 VRM K VRM K VRM E IO K VRM N IO K IO M IO M0 IO M IO P IO R OF IO T R OEV@0_ PIRT@0.0U/V_X PIRT@0.U/0V_X PIRT@0U/.V_X R OEV@0_ +V.S_G R PIRT@0_.m (0mils) R *PIRT@0_ +V.0S_PLL_FI m (0mils) +V.0S EXP +V.S GIO R 0_ +V. (0mils) 0.U/0V_X 0m (0mils) +V.0M_SUS +V_S m (0mils) *U/.V_X +V.0S EXP +_USSUS +PLL_US +V.0S_PLL_EXP *U/.V_X *0U/.V_X +V.0S EXP +V.0S_PLL_ST m (0mils) +V.0S EXP +V +V_G +V R 0_ +.0V R0 0_ +V R 0_ +V R 0_ +V R0 0_ +V R 0_ 0 m (0mils) 0.U/0V_X R R0 +V_S m (0mils) R SUS_ SUS_ R +V.S_UG R SUS_ SUS_ U SUS_ GPIO/LP SUS_ +PSW_PH M SW_ 0.U/0V_X +SST U PSST USPLL E +V.S_PORE +V.0S_USORE L _ F m (0mils) G U0 _ V IO. (0mils) 0.U/0V_X V0 IO +V.0S_UX IO IO U Y0 IO m (mils) +V.0M_USSUS Y zalia PSUS 0m (0mils) +_H_IO m (0mils) +XK_VRM F SUSH VRM *U/.V_X +V.0S XK_ P K +PRTSUS_P SUS_. (0mils) m (0mils) +V.0S SSFF Y +V.S FLEX0 LK RT M RT +RTEXT LK_ PRT P m (0mils) L PRT P U/.V_X LK_ m (0mils) L +V.0S_PPU M LK_ V_PRO_IO J 0.U/0V_X PU +V.S FLEX LK_ V_PRO_IO J U LK_ m (0mils) V +V.M_PSPI LK_ SPI SPI U/.V_X 0m (0mils) LK +V.S_PFUSE +V.0S SSFF 0 P +V.S FLEX LK P0 LK Fuse +V.0S_LKF00 SW L LK +V.0S_SSF00 G0 SW R U/.V_X G LK LK +V.S SEPI +V.0S_LKF00 VRM W0 LK K0 +V.0S_SSF00 E0 _ Thermal. (0mils) E LK K U/.V_X LK _ OF US I 0.U/0V_X R 0_ +V 0.0U/V_X R 0_ +.0V R 0_ +V_S U/.V_X 0.U/0V_X 0.U/0V_X 0.U/0V_X 0.U/0V_X +V_RT 0 U/.V_X R 0_ +IO_PH U/.V_X R 0_ +V_S U/.V_X R 0_ +V R *0_ +.0V +.0V R0 0_ +LKF 0 U/.V_X LPT_PH_M_ES/G 0m (0mils) +PH 0 U/.V_X R 0_ +.0V 0m (0mils) +PH R 0_ +.0V m (0mils) +V.S_TS R 0_ +.V m (0mils) +V.S_PTS R 0_ +V 0.U/0V_X PH VRM Power 0. (0mils) PH IO Power PH S SUS PH SW +.0V +.V L R 0_ *uh M +V.0S_PLL_FI *0U/.V_X +.0V R 0_0 +V.0S EXP 0U/.V_X U/.V_X. (0mils) U/.V_X U/.V_X 0 U/.V_X U/.V_X *S@0.U/.V_X +V_S R S@00K_ R +V_S NS@0_ +VPU +PSW +.0V +.V +.0V L R 0_ *0uh 00M +PLL_US *0U/.V_X +V.0S_PLL_EXP PH band gap Power +V_S +V_G Q *PIRT@N00K_00M {,} SLP_SUS# Q S@ME0T R S@0_ Q S@TEU 0.U/0V_X +V_S R S@R00V-0_00M NS@0_ +.V +.0V L R 0_ L *uh M *0uh 00M *0U/.V_X +V.0S_PLL_ST +.0V R {,,} MIN +XK_VRM_R */F_ L0 +XK_VRM *0uh 00M +.0V +_XK_ +V.0S XK_ R 0_ L 0_ PH H Power 0.0 (0mils) +V_S +_H_IO +.0V +V.0S_LKF00 R 0_ R 0_ +.0V +V.0S SSFF +.0V +V.0S_SSF00 R0 0_ R 0_ +.V R 0_ *0U/.V_X +.V R 0_ 0 0U/.V_X *0U/.V_X U/.V_X 0 0.U/0V_X U/.V_X U/.V_X U/.V_X Quanta omputer Inc. PROJET : Size ocument Number Rev LPT / (POWER) Thursday, ecember 0, 0 ate: Sheet of

13 Lynx Point (GN) <LG> Lynx Point (GN) <LG> UJ LPT_PH_M_ES UK LPT_PH_M_ES L L L M M M M M0 M M N N0 N N P P P P R K T0 T T T0 T T T T V V V V V V0 V W F Y0 Y Y0 Y Y Y 0 OF K L L M M N N N N P P P P P0 P R R R R R R R R T U0 U U U U U U V V V V W W Y Y Y Y Y Y Y0 Y E E F F G G G G G J J J0 J J J J J J K K K K L L LPT_PH_M_ES/G OF 0 Y T V F F0 F F G G G G H0 H H H H H H H H0 H K0 K K0 K K LPT_PH_M_ES/G Quanta omputer Inc. PROJET : Size ocument Number Rev LPT / (GN) Thursday, ecember 0, 0 ate: Sheet of

14 . VREF Q0 M Solution Place these aps near So-imm0. VREF M Solution <R> H= (Rev) M 0 M M M M M M 0 M M M M M M M M M SM_RUN_LK SM_RUN_T M M M M M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q IMM0_S0 IMM0_S +SMR_VREF_IMM +SMR_VREF_Q0 +SMR_VREF_IMM M Q M Q M Q M Q M Q M Q0 +SMR_VREF_Q0_M PM_EXTTS#0 +SMR_VREF_Q0 M Q[:0] {} M [:0] {} M S#0 {} M S# {} M S# {} M S#0 {} M S# {} M LKP0 {} M LKN0 {} M LKP {} M LKN {} M KE0 {} M KE {} M WE# {} M RS# {} M S# {} M OT0 {} M OT {} M QSP[:0] {} M QSN[:0] {} SM_RUN_LK {,,0,} SM_RUN_T {,,0,} R_RMRST# {,} +V +SMR_VTERM +V +.VSUS +SMR_VREF_IMM +V +.VSUS +SMR_VTERM +SMR_VREF_Q0 +.VSUS +VREFQ_S_M +.VSUS +VREF PU +SMR_VREF_IMM +SMR_VREF_Q0 +SMR_VREF_IMM +SMR_VREF_Q0 +SMR_VREF +SMR_VREF +SMR_VREF_Q0 +SMR_VREF_IMM Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : System Memory / (.H) Thursday, ecember 0, 0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : System Memory / (.H) Thursday, ecember 0, 0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : System Memory / (.H) Thursday, ecember 0, 0 *.U/0V_Y 0 *0U/.V_X R K/F_.U/.V_X R./F_ R *0K_ R 0_.U/.V_X 0P/0V_X R0 *0_ P00 R SRM SO-IMM (0P) JIM RSK-00-TP V V V V V V V V V V0 00 V 0 V 0 V V V V V V VSP N N NTEST EVENT# RESET# 0 VREF_Q VREF_ VTT 0 VTT 0 GN 0 GN 0 *.U/0V_Y 0.U/0V_X R K/F_ R *0_ 0 U/.V_X *.U/.V_X R K/F_ *.U/.V_X P00 R SRM SO-IMM (0P) JIM RSK-00-TP 0 0 0/P 0 /# S0# S# K0 0 K0# 0 K 0 K# 0 KE0 KE S# RS# 0 WE# S0 S 0 SL 0 S 00 OT0 OT 0 M0 M M M M M M 0 M QS0 QS QS QS QS QS QS QS QS#0 0 QS# QS# QS# QS# QS# QS# QS# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q0 Q Q Q Q Q Q Q 0 Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q 0 U/.V_X 0.U/0V_X 0 *0U/.V_X R K/F_ R0 0_ 0.U/0V_X R 0_ *.U/.V_X 0.0U/V_X *.U/.V_X + *0U/.V_P_Eb 0.U/0V_X U/.V_X 0 U/.V_X R 0K_ 0.U/0V_X.U/.V_X 0.U/.V_X 0.0U/V_X R 0K_ R./F_ 0.U/0V_X *.U/.V_X 0.U/0V_X *.U/.V_X

15 . VREF Q M Solution <R> H= (Rev) M 0 M M M M M M 0 M M M M M M M M M M M M M M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q IMM_S0 IMM_S M Q0 M Q M Q0 M Q +SMR_VREF_IMM +SMR_VREF_Q +SMR_VREF_Q +SMR_VREF_Q_M PM_EXTTS# M Q[:0] {} M [:0] {} M S#0 {} M S# {} M S# {} M S#0 {} M S# {} M LKP0 {} M LKN0 {} M LKP {} M LKN {} M KE0 {} M KE {} M WE# {} M RS# {} M S# {} M OT0 {} M OT {} M QSP[:0] {} M QSN[:0] {} SM_RUN_LK {,,0,} SM_RUN_T {,,0,} R_RMRST# {,} +V +SMR_VREF_IMM +V +.VSUS +SMR_VTERM +V +SMR_VTERM +V +SMR_VREF_IMM +.VSUS +SMR_VREF_Q +VREFQ_S_M +.VSUS +SMR_VREF_Q +SMR_VREF_Q +SMR_VREF +SMR_VREF_Q +SMR_VREF_IMM Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : System Memory / (.H) Thursday, ecember 0, 0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : System Memory / (.H) Thursday, ecember 0, 0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : System Memory / (.H) Thursday, ecember 0, 0 *.U/.V_X R K/F_ R *0_ 0.U/0V_X *0.U/0V_X *.U/.V_X *.U/.V_X.U/.V_X R *0K_ U/.V_X 0.U/0V_X 0 *.U/.V_X R 0_ U/.V_X R 0K_ 0.U/0V_X U/.V_X P00 R SRM SO-IMM (0P) JIM RSK-00-TP V V V V V V V V V V0 00 V 0 V 0 V V V V V V VSP N N NTEST EVENT# RESET# 0 VREF_Q VREF_ VTT 0 VTT 0 GN 0 GN 0 R 0K_ *.U/.V_X 0.U/0V_X.U/.V_X 0 *0U/.V_X *.U/.V_X R 0_ 0 *0U/.V_X 0.0U/V_X.U/.V_X *0.0U/V_X.U/.V_X + *0U/.V_P_Eb 0.U/0V_X 00 U/.V_X R./F_ R K/F_ *.U/0V_Y R *./F_ P00 R SRM SO-IMM (0P) JIM RSK-00-TP 0 0 0/P 0 /# S0# S# K0 0 K0# 0 K 0 K# 0 KE0 KE S# RS# 0 WE# S0 S 0 SL 0 S 00 OT0 OT 0 M0 M M M M M M 0 M QS0 QS QS QS QS QS QS QS QS#0 0 QS# QS# QS# QS# QS# QS# QS# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q0 Q Q Q Q Q Q Q 0 Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q 0.U/0V_X *.U/0V_Y

16 +.0V_GPU 0 EV@0U/.V_X EV@0U/.V_X EV@0U/.V_X U NP_GVGK0 N NM_GLGF PEX_WKE 00 *EV@0.U/0V_X EV@0U/.V_X EV@.U/.V_X EV@U/.V_X EV@U/.V_X E E PEX_IOV PEX_IOV PEX_IOV PEX_IOV PEX_IOV PEX_IOV PI_EXPRESS PEX_RST PEX_LKREQ PEX_REFLK PEX_REFLK E VG_RST# PEX_LKREQ# R R0 EV@00_ EV@0K_ PEGX_RST# +V_GPU LK_PIE_VGP {0} LK_PIE_VGN {0} PEX_IOV + PEX_IOVQ =. +.0V_GPU 0 EV@0U/.V_X EV@0U/.V_X EV@0U/.V_X EV@0U/.V_X EV@.U/.V_X EV@U/.V_X EV@U/.V_X 0 0 E F F PEX_IOVQ PEX_IOVQ PEX_IOVQ PEX_IOVQ PEX_IOVQ PEX_IOVQ PEX_IOVQ PEX_IOVQ PEX_IOVQ PEX_IOVQ PEX_IOVQ PEX_IOVQ PEX_IOVQ PEX_IOVQ PEX_TX0 PEX_TX0 PEX_RX0 PEX_RX0 PEX_TX PEX_TX PEX_RX PEX_RX PEX_TX PEX_TX PEX_RX PEX_RX PEX_TX PEX_TX G G 0 0 F E E F _PEG_RX0 _PEG_RX#0 _PEG_RX _PEG_RX# _PEG_RX _PEG_RX# _PEG_RX _PEG_RX# 0 EV@0.U/0V_X EV@0.U/0V_X EV@0.U/0V_X EV@0.U/0V_X EV@0.U/0V_X EV@0.U/0V_X EV@0.U/0V_X EV@0.U/0V_X PEG_RXP0 {} PEG_RXN0 {} PEG_TXP0 {} PEG_TXN0 {} PEG_RXP {} PEG_RXN {} PEG_TXP {} PEG_TXN {} PEG_RXP {} PEG_RXN {} PEG_TXP {} PEG_TXN {} PEG_RXP {} PEG_RXN {} PEX_RX PEX_RX G G0 PEG_TXP {} PEG_TXN {} PEX_PLL_HV + PEX_SV_V = 0m PEX_TX PEX_TX PEX_RX PEX_RX F0 E0 _PEG_RX _PEG_RX# EV@0.U/0V_X EV@0.U/0V_X PEG_RXP {} PEG_RXN {} PEG_TXP {} PEG_TXN {} +V_GPU EV@0.U/0V_X EV@.U/.V_X EV@.U/.V_X PEX_PLL_HV PEX_PLL_HV PEX_SV_V PEX_TX PEX_TX PEX_RX PEX_RX PEX_TX PEX_TX E F _PEG_RX _PEG_RX# _PEG_RX _PEG_RX# 0 EV@0.U/0V_X EV@0.U/0V_X EV@0.U/0V_X EV@0.U/0V_X PEG_RXP {} PEG_RXN {} PEG_TXP {} PEG_TXN {} PEG_RXP {} PEG_RXN {} PEX_RX PEX_RX G G PEG_TXP {} PEG_TXN {} PEX_TX PEX_TX _PEG_RX _PEG_RX# EV@0.U/0V_X EV@0.U/0V_X PEG_RXP {} PEG_RXN {} PEX_RX PEX_RX F E PEG_TXP {} PEG_TXN {} {} VG_SENSE F V_SENSE N N N N N N PEX_TX PEX_TX PEX_RX PEX_RX PEX_TX PEX_TX E F PIE (RESET) +V {} VG_SENSE R *EV@00/F_ PEX_TSTLK PEX_TSTLK# PEX_PLLV = 0m +.0V_GPU L EV@H0KF-T_. F F E GN_SENSE PEX_TSTLK_OUT PEX_TSTLK_OUT N N N N N N N N N N N N N N N N PEX_RX PEX_RX PEX_TX0 PEX_TX0 PEX_RX0 PEX_RX0 PEX_TX PEX_TX PEX_RX PEX_RX PEX_TX PEX_TX PEX_RX PEX_RX PEX_TX PEX_TX G G F E 0 0 E F G G E PIE (LK_REQ) {} VG_PLTRST# {} GPU_HOL_RST# R +V_GPU U0 PX@TSH0FU(F) OEV@0_ PX@0.U/0V_X PEGX_RST# R0 PX@00K_ PEGX_RST# {0} LK_PEG_REQ# {0} 0 R R EV@.U/.V_X EV@U/.V_X EV@0.U/0V_X EV@0K_ EV@.K/F_ PEX_PLLV TESTMOE PEX_TERMP F PEX_PLLV PEX_PLLV TESTMOE PEX_TERMP N N N N N N N N N N GK0 NP_GV PEX_RX PEX_RX PEX_TX PEX_TX PEX_RX PEX_RX PEX_TX PEX_TX PEX_RX PEX_RX GF NM_GL F E F E E F G G G G {,,} GPU_PWROK R *EV@0_ PEX_LKREQ# Q *EV@LT0EUFSTL_0M R0 *EV@.K_ LKREQ_ +V_GPU Q *EV@LT0EUFSTL_0M bga-nvidia-np-gv-s-a OMMON PEX_LKREQ# LK_PEG_REQ# Q EV@N00K_00M Quanta omputer Inc. PROJET : hief River Size ocument Number Rev Nx (PIE I/F) Thursday, ecember 0, 0 ate: Sheet of

17 {0,,} F_LMP TP R EV@0K_ F_LMP_R F R0 G@0_ {,} F_M0 {} F_M {} F_M E {,} F_M F {,} F_M {,} F_M {,} F_M F {,} F_M F {,} F_M F {,} F_M G {,} F_M0 G {,} F_M G {,} F_M F {,} F_M G {,} F_M G {,} F_M G {,} F_M M {} F_M M {} F_M K {,} F_M K {,} F_M0 M {,} F_M M {,} F_M M {,} F_M K {,} F_M K {,} F_M J {,} F_M J J {} F_M {,} F_M K {,} F_M K {} F_M0 J F_M J U F_LMP F UL RNK (Mode E) F_M0 Rank 0/ [:0] OT F_M Rank [:0] S# F_M Rank0 [:0] S0# F_M Rank 0/ [:0] KE F_M [Rank0:],[Rank:] F_M [Rank0:],[Rank:] F_M [Rank0:],[Rank:] F_M [Rank0:0],[Rank:] F_M [Rank0:],[Rank:] F_M [Rank0:],[Rank:0] F_M0 [Rank0:],[Rank:] F_M [Rank0:RS#],[Rank:RS#] F_M [Rank0:],[Rank:] F_M [Rank0:],[Rank:] F_M [Rank0:],[Rank:] F_M [Rank0:S#],[Rank:S#] F_M Rank 0/ [:] OT F_M Rank [:] S# F_M Rank0 [:] S0# F_M Rank 0/ [:] KE F_M0 [Rank0:RST],[Rank:RST] F_M [Rank0:],[Rank:] F_M [Rank0:],[Rank:] F_M [Rank0:],[Rank:] F_M [Rank0:],[Rank:] F_M [Rank0:0],[Rank:WE#] F_M [Rank0:],[Rank:] F_M Rank0 F_M [Rank0:WE#],[Rank:0] F_M [Rank0:0],[Rank:0] F_M0 Rank F_M N/ F_0 E VM_Q0 F_ F VM_Q F_ E VM_Q F_ F VM_Q F_ 0 VM_Q F_ VM_Q F_ F0 VM_Q F_ E VM_Q F_ E VM_Q F_ VM_Q F_0 F VM_Q0 F_ F VM_Q F_ VM_Q F_ VM_Q F_ E VM_Q F_ VM_Q F_ VM_Q F_ VM_Q F_ VM_Q F_ VM_Q F_0 VM_Q0 F_ VM_Q F_ VM_Q F_ VM_Q F_ VM_Q F_ VM_Q F_ VM_Q F_ VM_Q F_ VM_Q F_ VM_Q F_0 0 VM_Q0 F_ VM_Q F_ R VM_Q F_ R VM_Q F_ T VM_Q F_ R VM_Q F_ N VM_Q F_ N VM_Q F_ N VM_Q F_ N VM_Q F_0 V VM_Q0 F_ V VM_Q F_ T VM_Q F_ U VM_Q F_ Y VM_Q F_ VM_Q F_ Y VM_Q F_ VM_Q F_ VM_Q F_ VM_Q F_0 VM_Q0 F_ VM_Q F_ VM_Q F_ VM_Q F_ W VM_Q F_ Y VM_Q F_ R VM_Q F_ T VM_Q F_ N VM_Q F_ R VM_Q F_0 V VM_Q0 F_ V VM_Q F_ W VM_Q F_ W VM_Q VM_Q[:0] VM_Q[:0] {,} FVQ + FV =. +.V_GPU U EV@0.U/0V_X FVQ FVQ EV@0.U/0V_X E FVQ E FVQ EV@U/0V_X F FVQ F FVQ EV@U/0V_X G FVQ G FVQ EV@.U/.V_X G FVQ G FVQ EV@.U/.V_X G FVQ G FVQ EV@0U/.V_X G0 FVQ G FVQ EV@0U/.V_X H FVQ H FVQ J FVQ K FVQ L FVQ L FVQ L FVQ M FVQ N FVQ R FVQ T FVQ V FVQ W FVQ FVQ F_L_P_VQ F_L_P_VQ R F_L_PU_GN F_L_PU_GN R EV@0./F_ EV@./F_ +.V_GPU F_M F_M F_M F_M +.V_GPU R R EV@00_ EV@00_ F_M F_M0 R R EV@00_ EV@00_ EV@0.U/0V_X +.V_GPU R R EV@00_ EV@00_ F_M F_M R R EV@00_ EV@00_ EV@0.U/0V_X +.V_GPU R EV@00_ R EV@00_ R0 EV@00_ R EV@00_ +.V_GPU R EV@00_ R EV@00_ EV@0.U/0V_X +.V_GPU R EV@00_ R EV@00_ EV@0.U/0V_X +.V_GPU +.V_GPU R *EV@0./F_ R *EV@0./F_ {,} VM_LK0 {,} VM_LK0# {,} VM_LK {,} VM_LK# F_EUG F_EUG F J N M F_EUG0 F_EUG F_LK0 F_LK0 F_LK F_LK F_QM0 VM_M0 F_QM VM_M F_QM VM_M F_QM VM_M F_QM P VM_M F_QM W VM_M F_QM VM_M F_QM U VM_M F_QS_WP0 E VM_WQS0 F_QS_WP VM_WQS F_QS_WP VM_WQS F_QS_WP VM_WQS F_QS_WP R VM_WQS F_QS_WP W VM_WQS F_QS_WP VM_WQS F_QS_WP T VM_WQS VM_M[:0] {,} VM_WQS[:0] {,} F_LTERM_GN F_L_TERM_GN R bga-nvidia-np-gv-s-a OMMON EV@./F_ F_M F_M R EV@00_ R EV@00_ R EV@00_ R EV@00_ F_M F_M EV@0.U/0V_X R EV@00_ R EV@00_ R EV@00_ R EV@00_ 0 EV@0.U/0V_X F_PLLV = m * +.0V_GPU L EV@H0KF-T_. +F_PLLV EV@0U/.V_X 0 EV@0.U/0V_X EV@0.U/0V_X EV@0.U/0V_X F_LLV = m T U V V F P H F_WK0 F_WK0 F_WK F_WK F_WK F_WK F_WK F_WK F_PLLV F_PLLV F_LLV F_QS_RN0 F VM_RQS0 F_QS_RN VM_RQS F_QS_RN VM_RQS F_QS_RN VM_RQS F_QS_RN P VM_RQS F_QS_RN W VM_RQS F_QS_RN VM_RQS F_QS_RN T VM_RQS VM_RQS[:0] {,} OTx, KEx,RST (Termination) F_OT_L F_M0 R0 EV@0K_ F_OT_H F_M R EV@0K_ F_RST# F_M0 R EV@0K_ F_KE_L F_M R0 EV@0K_ F_KE_H F_M R EV@0K_ F_M F_M R EV@00_ R EV@00_ +.V_GPU R EV@00_ F_M0 F_M R 0 EV@00_ EV@0.U/0V_X R EV@00_ R EV@00_ +.V_GPU R EV@00_ R EV@0.U/0V_X EV@00_ F_VREF_PROE F_VREF_PROE TP bga-nvidia-np-gv-s-a OMMON +.V_GPU +.V_GPU +.V_GPU F_M F_M R EV@00_ R EV@00_ F_M F_M R EV@00_ R EV@00_ F_M F_M R EV@00_ R EV@00_ R EV@00_ R0 EV@00_ 0 EV@0.U/0V_X R EV@00_ R EV@00_ EV@0.U/0V_X R EV@00_ R EV@00_ EV@0.U/0V_X Quanta omputer Inc. PROJET : hief River Size ocument Number Rev Nx (Memory I/F) Thursday, ecember 0, 0 ate: Sheet of

18 UG R *EV@K/F_ IFP_RSET +V_GPU m V IFP_PLLV L0 OEVLS@H0KF-T_. W IFP_PLLV OEVLS@.U/.V_X OEVLS@U/.V_X 0 OEVLS@0.U/0V_X IFP_PLLV +.0V_GPU m * L OEVLS@H0KF-T_. W IFP_IOV OEVLS@.U/.V_X Y IFP_IOV OEVLS@U/.V_X OEVLS@0.U/0V_X IFP LVS LVS IFP_TX IFP_TX IFP_TX0 IFP_TX0 IFP_TX IFP_TX IFP_TX IFP_TX IFP_TX IFP_TX IFP_TX IFP_TX IFP_TX IFP_TX IFP_TX IFP_TX Y Y EV_TXLLKOUT- {} EV_TXLLKOUT+ {} EV_TXLOUT0- {} EV_TXLOUT0+ {} EV_TXLOUT- {} EV_TXLOUT+ {} EV_TXLOUT- {} EV_TXLOUT+ {} EV_TXULKOUT- {} EV_TXULKOUT+ {} EV_TXUOUT0- {} EV_TXUOUT0+ {} EV_TXUOUT- {} EV_TXUOUT+ {} R +V_GPU L V_GPU L OEVEP@K/F_ OEVEP@H0KF-T_. OEVEP@.U/.V_X OEVEP@U/.V_X OEVEP@0.U/0V_X OEVEP@0.U/0V_X OEVEP@0.U/0V_X OEVEP@H0KF-T_. OEVEP@.U/.V_X OEVEP@U/.V_X OEVEP@0.U/0V_X IFP_PLLV IFP_IOV UI U IFP_RSET T IFP_PLLV R IFP_PLLV R IFP_IOV bga-nvidia-np-gv-s-a IFP HP_ IFP_UX IFP_UX IFP_L IFP_L IFP_L IFP_L IFP_L IFP_L IFP_L0 IFP_L0 GPIO OMMON P P R R T T U U V V EV_EP_UXN EV_EP_UXN {,} EV_EP_UXP EV_EP_UXP {,} EV_EP_TXN {} EV_EP_TXP {} EV_EP_TXN {} EV_EP_TXP {} EV_EP_TXN {} EV_EP_TXP {} EV_EP_TXN0 {} EV_EP_TXP0 {} EV_EP_HP {} OEVLS@0.U/0V_X IFP_IOV IFP_TX IFP_TX E EV_TXUOUT- {} EV_TXUOUT+ {} OEVEP@0.U/0V_X IFP_TX IFP_TX EV_EP_UXN EV_EP_UXP EV_EP_UXN {,} EV_EP_UXP {,} R OEVEP@00K_ R OEVEP@00K_ HP_ GPIO bga-nvidia-np-gv-s-a OMMON UJ GK0(NP-GV) GF (NM-GL) TP0 GF (NM-GL) GK0(NP-GV) J IFPEF_PLLV N VI-L IY_S IY_SL VI-SL/HMI IY_S IY_SL P IFPE_UX IFPE_UX J J R OEHM@K/F_ +V_GPU 00m L OEHM@H0KF-T_. UH T IFP_RSET M IFP_PLLV N IFP_PLLV IFP HMI T LK IFP_UX IFP_UX N N EV_HMI_T {} EV_HMI_LK {} TP K IFPEF_PLLV N K IFPEF_RSET N IFPE N N N N N N N N TX TX TX0 TX0 TX TX TX TX TX TX TX0 TX0 TX TX TX TX IFPE_L IFPE_L IFPE_L IFPE_L IFPE_L IFPE_L IFPE_L0 IFPE_L0 J K K K M M M N OEHM@.U/.V_X OEHM@U/.V_X OEHM@0.U/0V_X OEHM@0.U/0V_X OEHM@0.U/0V_X IFP_PLLV TX LK- TX LK+ TX ata0 - TX ata0 + TX ata - TX ata + TX ata - TX ata + IFP_L IFP_L IFP_L IFP_L IFP_L IFP_L IFP_L0 IFP_L0 N N R R R T T T EXT_HMILK- {} EXT_HMILK+ {} EXT_HMITX0N {} EXT_HMITX0P {} EXT_HMITXN {} EXT_HMITXP {} EXT_HMITXN {} EXT_HMITXP {} TP GF GK0 (NM-GL) (NP-GV) H IFPE_IOV N J IFPF_IOV N N GK0(NP-GV) HP_E VI-L GF HP_E (NM-GL) VI-SL/HMI IZ_S IZ_SL GPIO P IFPF_UX IFPF_UX H H +.0V_GPU m L OEHM@H0KF-T_. OEHM@.U/.V_X P IFP_IOV bga-nvidia-np-gv-s-a HP_ GPIO OMMON EXT_HMI_HP {} IFPF N N N N N N TX TX TX TX TX TX TX0 TX0 TX TX IFPF_L IFPF_L IFPF_L IFPF_L IFPF_L IFPF_L J J K K L L OEHM@U/.V_X OEHM@0.U/0V_X N N TX TX TX TX IFPF_L0 IFPF_L0 M M OEHM@0.U/0V_X IFP_IOV N HP_F GPIO F bga-nvidia-np-gv-s-a OMMON Quanta omputer Inc. PROJET : hief River Size ocument Number Rev Nx (isplay I/F) Thursday, ecember 0, 0 ate: Sheet of

19 +.0V_GPU PLLV = m L EV@H0KF-T_. NV_PLLV EV@0.U/0V_X 0 EV@0U/.V_X SP_PLLV = m VI_PLLV = m +.0V_GPU L EV@H0KF-T_. UM 0 0 SP_PLLV EV@0.U/0V_X L M EV@0.U/0V_X N EV@.U/.V_X EV@0U/.V_X R EV@0K_ XTL_SSIN 0 LK_M_XTL_IN PLLV SP_PLLV VI_PLLV XTLSSIN XTLIN XTL_PLL XTLOUTUFF 0 XTLOUT XTLOUT 0 LK_M_XTL_OUT R R EV@0_ EV@0K_ LK_M_XTL_IN LK_M_XTL_OUT_R Y EV@MHZ_0 EV@P/0V_ EV@P/0V_ bga-nvidia-np-gv-s-a OMMON +V_GPU L 0m OERT@H0KF-T_. OERT@.U/.V_X OERT@U/.V_X OERT@0.U/0V_X OERT@0.U/0V_X OERT@0.U/0V_X OERT@0.U/0V_X _V _VREF UK W _V E _VREF RT I_SL I_S EV_RTLK {} EV_RTT {} EXT_RT_RE EXT_RT_GRN EXT_RT_LU R R R0 OERT@0/F_ OERT@0/F_ OERT@0/F_ +V_GPU R OERT@/F RESET F _RSET _HSYN E _VSYN E EXT_HSYN {} EXT_VSYN {} R0 OERT@.K_ R OERT@.K RE G _GREEN F _LUE F EXT_RT_RE {} EXT_RT_GRN {} EXT_RT_LU {} EV_RTLK EV_RTT bga-nvidia-np-gv-s-a OMMON R PIV@.K_ R PIV@.K_ Quanta omputer Inc. PROJET : hief River Size ocument Number Rev Nx (XTL/RT I/F) ate: Thursday, ecember 0, 0 Sheet of

20 TP TP THERM- E THERM+ F E E F JTG_TRST# G UN THERMN THERMP JTG_TK JTG_TMS JTG_TI JTG_TO JTG_TRST MIS GPIO F_LMP_MON MEM_V_LT L_L_PWM L_ L_LEN Reserved F_LMP_TGL_REQ Vision OVERT LERT MEM_VREF_TRL PWM_VI PWM_LEVEL PSI IS_SL IS_S I_SL I_S I_SL I_S GPIO0 GPIO GPIO GPIO GPIO F GPIO GPIO GPIO GPIO GPIO F GPIO0 GPIO E GPIO GPIO GFx_SL GFx_S EV_LVS_LK EV_LVS_T NE_SL NE_S R R0 F_LMP_RR R G@0_ TP0 EV_LVS_RIGHT EV_LVS_IGON GPU_LON R0 *EV@0_ F_LMP_TGL_REQ#_Q Vision VG_OVT# VG_LERT NV_MEM_VERF_TRL VG_PWR_LEVEL VG_PSI R0 EV@.K_ EV@.K_ EV@0K_ EV_LVS_LK {} EV_LVS_T {} F_LMP {,,} EV_LVS_RIGHT {} EV_LVS_IGON {} GPU_LON {} VG_STY {} GPU_VI0 {} VG_PWR_LEVEL {} +V_GPU GPU_PSI {} R0 OEVLS@.K_ EV_LVS_LK EV_LVS_T +V_GPU R PIV@.K_ +V_GPU R0 OEVLS@.K_ R PIV@.K_ 0 FRM_LK Reserved Reserved GPIO GPIO0 E GPIO GPU_GPIO TP TP TP GPIO PU/P bga-nvidia-np-gv-s-a VG_OVT# Q *EV@MEN00E_00M OMMON PEGX_RST# {} S_ON {,,} F_LMP_RR G@ME0T Q GPU_PWR_EN {} F_LMP VG_PWR_LEVEL R VG_OVT# VG_LERT R R F_LMP_TGL_REQ#_Q R +V_GPU EV@00K_ EV@00K_ EV@00K_ G@0K_ SMUS [Thermal] +V_GPU +V_GPU +V_GPU EV_LVS_RIGHT EV_LVS_IGON GPU_LON R R R OEV@0K_ *OEV@0K_ *OEV@0K_ R EV@0K_ R EV@0K_ JTG_TRST# F_LMP_RR R R EV@0K_ G@0K_ GFx_SL {,} N_MLK {,} N_MT Q EV@N00KW_M Q GFx_S EV@N00KW_M F_LMP_TGL_REQ#_Q Q G@MEN00E_00M F_LMP_TGL_REQ# {} Vision R NV_MEM_VERF_TRL R *EV@00K_ *EV@00K_ Quanta omputer Inc. PROJET : hief River Size ocument Number Rev Nx (GPIO) ate: Friday, ecember, 0 Sheet 0 of

21 E0 F0 UL GF (NM_GL) VMON_IN0 VMON_IN GK0(NP_GV) N N ROM_S ROM_S TP STRP0 STRP STRP STRP STRP STRP0 STRP E STRP E STRP STRP MIS GF(NM_GL) GK0(NP_GV) STRP N ROM_SI ROM_SO ROM_SLK UFRST ROM_SI ROM_SO ROM_SLK TP TP TP PI_EVI STRP RM_FG PI EVIE I RM_FG[:0] for memory configuration MULT STRIP [NP_GV] 0x -->QS 0x -->ES P_PLL_V PEX_PLL_EN_TERM [efault] PIE PLL termination 0:isable [efault] ; :Enable MSTRP_REF0_GN F MULTISTRP_REF0_GN N PGOO 0 NV_PWG SU_VENOR 0:No VIOS ROM ; IOS ROM [efault] GIO_PFG [0000] --> Gen support GF (NM_GL) GK0(NP_GV) GK0 GF (NP_GV)(NM_GL) F MULTISTRP_REF_GNN N E F MULTISTRP_REF_GNN GK0 GF (NP_GV)(NM_GL) bga-nvidia-np-gv-s-a OMMON E R EV@0K_ F[:0] VG_EVIE IS_Slave ddress [:0] --> M 0: evice ; :VG evice 0:E [efault] ; : PIE_MX_SPEE PIE_SPEE_HNG_ GEN SORx_EXPOSE [] -->llow boot to PIE Gen [] -->Enable Gen SOR0_EXP=0,SOR_EXP= [IFP/:LVS] ; [IFP:HMI] USER STRP Panel EI Support Vendor P/N STN /S P/N Size Strap Note Strap Pin name Strapping its Strapping its Strapping its Strapping its 0 SETTING NOTE M (G bit) Hynix S H H Samsung M S HTQGFR-N0 (M*) GL/GV HTQGFR- (M*) GL/GV KWGE- (M*) GL/GV KWGE- (M*) GL/GV MTJMJT-0G:K (M*) GL/GV x=g x=g x=g x=g x=g x=g x=g x=g x=g GL:0x0 00 GL:0x0 00 GL:0x0 00 GL:0x0 00 GL:0x0 000 GV:0x0 000MHz 00 GV:0x0 000MHz 00 GV:0x0 00MHz 00 GV:0x0 00MHz 00 GV:0x0 000MHz 0 GV:0x0 000MHz 0 GV:0x0 00MHz 0 GV:0x0 00MHz 0 GV:0x0 00MHz 00 ROM_SLK ROM_SI ROM_SO STRP0 STRP STRP STRP STRP.K PI_EVI[] SU_VENER PI_EVI[] PEX_PLL_EN_TERM RM_FG[] RM_FG[] RM_FG[] RM_FG[0] F[] F[0] SM_LT_R VG_EVIE USER[] USER[] USER[] USER[0] GIO_PFG[] GIO_PFG[] GIO_PFG[] GIO_PFG[0] PI_EVI[] PI_EVI[] PI_EVI[] PI_EVI[0] SOR_EXPOSE SOR_EXPOSE SOR_EXPOSE SOR0_EXPOSE RESERVE 000 PIE_SPEE_HN E_GEN 0000.K PIE_MX_SPEE P_PLL_VV V_GPU +V_GPU +V_GPU +V_GPU +V_GPU +V_GPU +V_GPU +V_GPU +V_GPU +V_GPU R R R R R R R R R R0 ROM_SLK ROM_SI ROM_SO PIV_GV@.K/F_ OEV_GV@0K/F_ STRP0 STRP STRP STRP STRP STRP GV@.K/F_ *K/F_ GV@.K/F_ *K/F_ *K/F_ *K/F_ *K/F_ *K/F_ R R o-lay R R R R0 R R R *K/F_ Strap_GV@K/F_ *K/F_ *K/F_ GV@.K/F_ GV@K/F_ OEV_GV@K/F_ PIV_GV@.K/F_ GV@.K/F_ NP_GV ROM_SI H/H.K S/S.K M/M 0.K SF SF S0F S00F S 0K M 0K S00F Micron M MTJMJT-0G:K (M*) GL/GV x=g x=g x=g GL:0x0 000 GV:0x0 00MHz 00 GV:0x0 000MHz 00 GV:0x0 000MHz 00 0K K 0K Resistor Value K.K.K V GN Resistor Value V GN Strap Pin name Strap Mapping Polarity inary Strap [NM_GL] SETTING MSTRP_REF0_GN R0 GV@0.K/F_ M (Gbit) Micron M Samsung H S Hynix H MTKMH-0G:E (M*) GL/GV KWG-H (M*) GL/GV HTQGMFR- (M*) GL HTQGFR- (M*) GL x=g x=g x=g x=g x=g N/ x=g GL:0x0 0 GL:0x0 0 GL:0x0 00 GL:0x0 000 GV:0x0 000 GV:0x0 000 GV:0x0 00 GV:0x MHz 00MHz 00MHz 00MHz 00MHz 00MHz ROM_SLK ROM_SI ROM_SO STRP0 STRP STRP STRP STRP SM_LT_R SU_VENER VG_EVIE RMFG[0] RMFG[] RMFG[] RMFG[] PIE_MX_SPEE Pull-down to GN Pull-UP to V if VIOS ROM Exists Pull-down to GN if no VIO ROM Pull-down to GN ( no dispaly ) USER defined USER defined USER defined USER defined Pull-down to GN +V_GPU +V_GPU +V_GPU +V_GPU +V_GPU +V_GPU +V_GPU R R R R0 R0 R R0 ROM_SLK ROM_SI ROM_SO STRP0 STRP STRP STRP *0K_ *0K_ *0K_ Strap_GL@0K_ Strap_GL@0K_ Strap_GL@0K_ Strap_GL@0K_ STRP R R R R R0 R R R GL@0K_ GL@0K_ GL@0K_ Strap_GL@0K_ Strap_GL@0K_ Strap_GL@0K_ Strap_GL@0K_ GL@0K_ NM_GL Strap Strap H 0 Strap H 0 0 H 0 0 H S 0 0 S 0 0 S 0 M M M Strap0 0 N/ Quanta omputer Inc. PROJET : hief River Size ocument Number Rev MSI & STRP Thursday, ecember 0, 0 ate: Sheet of