IDT 89EBPES48H12G2 Evaluation Board Manual

Transcription

1 IT 9EPESHG Evaluation oard Manual (Eval oard: --) May 9 Silver reek Valley Road, San Jose, alifornia 9 Telephone: () - () - FX: () - Printed in U.S.. 9 Integrated evice Technology, Inc.

2 ISLIMER Integrated evice Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IT product. The ompany makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Integrated evice Technology, Inc. oards that fail to function should be returned to IT for replacement. redit will not be given for the failed boards nor will a Failure nalysis be performed. LIFE SUPPORT POLIY Integrated evice Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of IT.. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.. critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. IT, the IT logo, and Integrated evice Technology are trademarks or registered trademarks of Integrated evice Technology, Inc.

3 Table of ontents Notes escription of the EHG Eval oard Introduction... - oard Features... - Hardware... - Software... - Other... - Revision History... - Installation of the EHG Eval oard EHG Installation... - Hardware escription... - Reference locks... - Power Sources... - External Power Source...- PI Express nalog High Power Voltage onverter... - PI Express nalog Power Voltage onverter... - PI Express Transmitter nalog Voltage onverter... - ore Logic Voltage onverter... -.V I/O Voltage Regulator... - Power-up Sequence for PESHG (PIe Gen device)... - Power-up Sequence for PESH (PIe Gen device)... - Reset... - Fundamental Reset... - ownstream Reset... - oot onfiguration Vector... - SMus Interfaces... - SMus Slave Interface...- SMus Master Interface... - JTG Header... - ttention uttons... - Miscellaneous Jumpers, Headers... - LEs... - PI Express onnectors EHG oard Figure... - Software for the EHG Eval oard Introduction... - evice Management Software... - Schematics Schematics... - EHG Eval oard Manual i May, 9

4 IT Table of ontents Notes EHG Eval oard Manual ii May, 9

5 List of Tables Notes Table. lock Source Selection... - Table. SM onnectors - Onboard Reference lock... - Table. External Power onnector - J... - Table. ownstream Reset Selection... - Table. oot onfiguration Vector Signals... - Table. oot onfiguration Vector Switches S & S (ON=, OFF=)... - Table. Slave SMus Interface onnector... - Table. JTG onnector Pin Out... - Table.9 ttention uttons... - Table. Miscellaneous Jumpers, Headers...- Table. LE Indicators... - Table. PI Express x onnector Pinout...-9 EHG Eval oard Manual iii May, 9

6 IT List of Tables Notes EHG Eval oard Manual iv May, 9

7 List of Figures Notes Figure. Function lock iagram of the EHG Eval oard...- EHG Eval oard Manual v May, 9

8 IT List of Figures Notes EHG Eval oard Manual vi May, 9

9 hapter escription of the EHG Eval oard Notes Introduction The 9HPESHG switch (also referred to as PESHG in this manual) is a member of IT s PI Express standard based line of products. It is a PIe ase Specification. compliant (Gen) - port switch. There are twelve x lanes ports. Two x ports can be merged to form one x port in PESHG. One upstream port is provided for connecting to the root complex (R), and up to eleven downstream ports are available for connecting to PIe endpoints or to another switch. More information on this device can be found in the 9HPESHG User Manual. The 9EPESHG Evaluation oard (also referred to as EHG in this manual) provides an evaluation platform for the PESHG switch. It is also a cost effective way to add PIe ports (slots) to an existing system with limited number of PIe ports/slots. The EHG board is designed to function as an add-on card to be plugged into a x PIe slot available on a motherboard hosting an appropriate root complex and microprocessor(s). The EHG is a vehicle to test and evaluate the functionality of the PESHG switch. It is also designed to work with the PESH (Gen ) switch. Refer to application note N- for detail information on esigning Gen-Ready boards for IT s -lane, -port PIe Switches. ustomers can use this board to get a headstart on software development prior to the arrival of their own hardware. The EHG is also used by IT to reproduce system-level hardware or software issues reported by customers. Figure. illustrates the functional block diagram representing the main parts of the EHG board. JTG Header lock Fanout lock Generator MHz rystal Main Reset I/O Expander MX EEPROM L SMUS HEER SMus PI Express Switch PESHG Port x Port Port Port Port x x x x PIe x ownstream Slot PIe x ownstream Slot PIe x ownstream Slot PIe x ownstream Slot Power Module PTHT External Power onnector PIe x Upstream Edge Voltages on board +V, +.V, +.V, +.V Figure. Function lock iagram of the EHG Eval oard EHG Eval oard Manual - May, 9

10 IT escription of the EHG Eval oard Notes oard Features Hardware PESHG PIe Gen switch Up to twelve x or six x ports - PIe lanes PIe ase Specification Revision. compliant (Gen Seres speeds of GT/S) Up to byte maximum Payload Size utomatic lane reversal and polarity inversion supported on all lanes utomatic per port link width negotiation to x, x, x, x Load configuration from an optional serial EEPROM via SMUS Upstream, ownstream Port One edge connector on the upstream port, to be plugged into a slot with at least x capable on a host motherboard Four slot connectors on the downstream ports, for PIe endpoint add-on cards to be plugged in. These slot connectors are x mechanically and electrically connected as three x and one x, but open-ended for card widths greater than x (e.g. x). Numerous user selectable configurations set using onboard jumpers and IP-switches Source of clock - host clock or onboard clock generator Two clock rates (/ MHz) from an onboard clock generator oot mode selection SMUS Slave Interface ( pin header) SMUS Master Interface connected to the Serial EEPROMs through I/O expander ttention button for each downstream port to initiate a hot swap event on each port Four pin connector for optional external power supply Push button for Warm Reset Several LEs to display status, reset, power, ttention, etc. One -pin JTG connector (pitch. mm x. mm) Software There is no software or firmware executed on the board. However, useful software is provided along with the Evaluation oard to facilitate configuration and evaluation of the PESHG within host systems running popular operating systems. Installation programs Operating Systems Supported: Windows Server, Windows Server, WindowsXP, Vista, Linux GUI based application for Windows and Linux llows users to view and modify registers in the PESHG inary file generator for programming the serial EEPROMs attached to the SMUS. Other metal bracket is provided to firmly hold in place three endpoints plugged into the EHG board. n external power supply may be required under some conditions. SMUS cable may be required for certain evaluation exercises. SM connectors are provided on the EHG board for clock outputs. Revision History January, 9: Initial publication of eval board manual. EHG Eval oard Manual - May, 9

11 IT escription of the EHG Eval oard Notes May, 9: On page -, changed reference to MHz oscillator (Y) to (X). In PI Express nalog Power Voltage onverter section, changed - onverter (U) to (U). In PI Express Transmitter nalog Power Voltage onverter section, changed - converter (U) to (U). In the SMus Slave Interface section of hapter, the slave interface default address was changed to b. In Table., signal S[] was changed from ON to OFF. In Table., locations were changed for the following signals: port : power-is-good; port power-is-good; port : power indicator; port : power indicator; port : attention indicator; port : attention indicator. EHG Eval oard Manual - a

12 IT escription of the EHG Eval oard Notes EHG Eval oard Manual - May, 9

13 hapter Installation of the EHG Eval oard Notes EHG Installation This chapter discusses the steps required to configure and install the EHG evaluation board. ll available IP switches and jumper configurations are explained in detail. The primary installation steps are:. onfigure jumper/switch options suitable for the evaluation or application requirements.. onnect PI Express endpoint cards to the downstream port PIe slots on the evaluation board.. Make sure that the host system (motherboard with root complex chipset) is powered off.. Insert the evaluation board into the host system.. pply power to the host system. The EHG board is typically shipped with all jumpers and switches configured to their default settings. In most cases, the board does not require further modification or setup. Hardware escription The PESHG is a -lane, -port PI Express switch. It is a peripheral chip that performs PI Express based switching with a feature set optimized for high performance applications such as servers and storage. It provides switching functions between a PI Express upstream port and downstream ports or peer-to-peer switching between downstream ports. The EHG has four PI Express downstream ports, accessible through four x connectors. Three ports are capable of negotiating a x, x, x and x link width and one port is capable of negotiating a x, x, or x link width. ll endpoint cards connected to the PESHG must support one of these link widths. asic requirements for the board to run are: Host system with a PI Express root complex supporting at least x configuration through a PI Express x or larger slot. x, x, x or x PI Express Endpoint ards. Reference locks The PESHG requires two differential reference clocks while the PESH requires four. lso, coupling is not required on the PESHG s reference input clocks, therefore capacitors,,, and need to be removed and capacitors, 9,, and should be replaced with ohm resistors when the Gen part is installed. The EHG derives these clocks from a common source which is user-selectable. The common source can be either the host system s reference clock or it can be the onboard clock generator. Selection is made by stuffing resistors as in Table.. lock onfiguration Stuffing Option W and W Pins and Pins and lock Source Onboard Reference lock Use onboard clock generator Upstream Reference lock Host system provides clock (efault) Table. lock Source Selection EHG Eval oard Manual - May, 9

14 IT Installation of the EHG Eval oard Notes The source for the onboard clock is the IS clock generator device (U) connected to a MHz oscillator (X). When using the onboard clock generator, the output frequency is fixed at MHz, therefore FSEL (S, pin ) should be in the ON position as the default setting. The outputs of the onboard clock generator and clock buffer (IS9) are accessible through two SM connectors located on the Evaluation oard. See Table.. This can be used to connect a scope for probing or capturing purposes and cannot be used to drive the clock from an external source. Onboard Reference lock Output (ifferential) J, J9, J-J J, J9, J, J Positive Reference lock J, J, J, J Negative Reference lock Power Sources Table. SM onnectors - Onboard Reference lock The EHG and all downstream ports are powered from the upstream port slot power. If add-in cards require more power than the upstream slot can support, an external source is required to supply this extra power via an auxiliary -pin power connector on the board. Header W, W, and W (see Table.) are used to select proper power source for the switch and all downstream ports. External Power Source If necessary, external power is supplied to the EHG board through a -pin auxiliary power connector attached to J. The external power supply provides +V to the EHG as described in Table.. The +V is unused. Pin Signal +V +V Table. External Power onnector - J PI Express nalog High Power Voltage onverter - converter (U) provides a.v PI Express analog high power voltage (shown as V PEH) to the PESHG. Install R ( ohm resistor) to provide a.v PI Express serial data transmit termination voltage (shown as VTTPE) when the PESH is installed. PI Express nalog Power Voltage onverter separate - converter (U) provides a.v PI Express analog power voltage (shown as V PE) to the PESHG. PI Express Transmitter nalog Voltage onverter separate - converter (U) provides a.v PI Express transmitter analog voltage (shown as V PET) to the PESHG. ore Logic Voltage onverter separate - converter (U) provides the.v core voltage (V ORE) to the PESHG. EHG Eval oard Manual - May, 9

15 IT Installation of the EHG Eval oard Notes.V I/O Voltage Regulator This evaluation board can be stuffed to host the PESHG (PIe Gen) device or the PESH (PIe Gen) device. epending on which device is populated on the board, appropriate settings can be made. V to.v voltage regulator (VR) provides the.v I/O voltage (V I/O) to the PESHG. Install R (.9 ohm) to provide the.v I/O voltage when the PESH is installed instead. Power-up Sequence for PESHG (PIe Gen device) uring power supply ramp-up, V ORE must remain at least.v below V I/O at all times. There are no other power-up sequence requirements for the various operating supply voltages. Power-up Sequence for PESH (PIe Gen device) The power -up sequence must be as following:. V I/O.V. V ORE, V PE, V PE.V. V TT PE.V When powering up, each voltage level must ramp up and stabilize prior to applying the next voltage in the sequence to ensure internal latch-up issues are avoided. There are no maximum time limitations between sequential valid power level requirements. Reset The PESHG supports two types of reset mechanisms as described in the PI Express specification: Fundamental Reset: This is a system-generated reset that propagates along the PI Express tree through a single side-band signal PERST# which is connected to the Root omplex, the PESHG, and the endpoints. Hot Reset: This is an In-band Reset, communicated downstream via a link from one device to another. Hot Reset may be initiated by software. This is further discussed in the PESHG User Manual. The EHG evaluation board provides seamless support for Hot Reset. Fundamental Reset There are two types of Fundamental Resets which may occur on the EHG evaluation board: old Reset: uring initial power-on, the onboard voltage monitor (TL) will assert the PI Express Reset (PERSTN) input pin of the PESHG. Warm Reset: This is triggered by hardware while the device is powered on. Warm Reset can be initiated by two methods: Pressing a push-button switch (S) located on EHG board The host system board IO ontroller Hub asserting PERST# signal, which propagates through the PIe upstream edge connector of the EHG. Note that one can bypass the onboard voltage monitor (TL) by moving the shunt from pin - to pin - (default) on W. oth events cause the onboard voltage monitor (TL) to assert the PI Express Reset (PERSTN) input of the PESHG while power is on. ownstream Reset The PESHG provides a a choice of either a software-controlled reset for each downstream port through GPIO pins or a fundamental reset through PERST#. Selection is made by jumpers described in Table.. EHG Eval oard Manual - May, 9

16 IT Installation of the EHG Eval oard Notes Port # Jumper Selection W9 [-] Software controlled reset through I/O Expander [-] Fundamental reset PERST# (default) W [-] Software controlled reset through I/O Expander [-] Fundamental reset PERST# (default) W9 [-] Software controlled reset through I/O Expander [-] Fundamental reset PERST# (default) W [-] Software controlled reset through I/O Expander [-] Fundamental reset PERST# (default) Table. ownstream Reset Selection oot onfiguration Vector boot configuration vector consisting of the signals listed in Table. is sampled by the PESHG during a fundamental reset (while PERSTN is active). The boot configuration vector defines the essential parameters for switch operation and is set using IP switches S and S as defined in Table.. Signal LKS LKUS LKMOE[:] SWMOE[:] escription ommon lock ownstream (for H). The assertion of this pin indicates that all downstream ports are using the same clock source as that provided to downstream devices. This pin is used as the initial value of the Slot lock onfiguration bit in all of the Link Status Registers for downstream ports. The value may be overridden by modifying the SLK bit in the downstream port s PIELSTS register. efault: x ommon lock Upstream (for PESH). The assertion of this pin indicates that the upstream port is using the same clock source as the upstream device. This pin is used as the initial value of the Slot lock onfiguration bit in the Link Status Register for the upstream port. The value may be overridden by modifying the SLK bit in the P_PIELSTS register. efault: x Initial Port locking mode (for PESHG). efault: x x - Global lock mode on all ports. Port/// SLK = x - Global lock mode on all ports. Port SLK =, Port SLK =, Port/ SLK = x - Global lock mode on all ports. Port SLK =, Port SLK =, Port/ SLK = x - Global lock mode on all ports. Port SLK =, Port SLK =, Port/ SLK = x - Local lock mode on Port/. Port SLK =, Port SLK =, Port/ SLK = x - Global lock mode on Port, Local lock mode on Port, Port SLK =, Port SLK =, Port/ SLK = x - Global lock mode on Port, Local lock mode on Port, Port SLK =, Port SLK =, Port/ SLK = x - Reserved Switch Mode. These configuration pins determine the PESHG switch operating mode. efault: x x - Normal switch mode x - Normal switch mode with Serial EEPROM-based initialization x through xf - Reserved Table. oot onfiguration Vector Signals EHG Eval oard Manual - May, 9

17 IT Installation of the EHG Eval oard Notes SMus Interfaces Signal escription efault S[] LKMOE OFF S[] LKMOE/LKS OFF S[] LKMOE/LKUS OFF S[] SWMOE[] OFF S[] SWMOE[] ON S[] SWMOE[] ON S[] SWMOE[] ON Table. oot onfiguration Vector Switches S & S (ON=, OFF=) The System Management us (SMus) is a two-wire interface through which various system component chips can communicate. It is based on the principles of operation of I. Implementation of the SMus signals in the PI Express connector is optional and may not be present on the host system. The SMus interface consists of an SMus clock pin and an SMus data pin. The PESHG contains two SMus interfaces: a slave SMus interface and a master SMus interface. The slave SMus interface allows a SMus Master device full access to all software-visible registers. The Master SMus interface provides connection to the external serial EEPROM used for initialization and the I/O expanders used for hot-plug signals. SMus Slave Interface On the PESHG board, the slave SMus interface is accessible through the PI Express edge connector as well as a -pin header as described in Table.. Note: The SMus signals to the PI Express edge connector is disabled by default. To enable them, place -ohm resistors at locations R and R.. Slave SMus Interface onnector J Pin Signal N/ SL S Table. Slave SMus Interface onnector fixed slave SMus address specified by the SSMR[,:] pins is used. For a fixed address, the SMus address of the PESHG slave interface is b by default. The slave SMus interface responds to the following SMus transactions initiated by an SMus master. Initiation of any SMus transaction other than those listed above produces undefined results. See the SMus. specification for a detailed description of the following transactions: yte and Word Write/Read lock Write/Read EHG Eval oard Manual - May, 9

18 IT Installation of the EHG Eval oard Notes SMus Master Interface onnected to the master SMus interface are seven -bit I/O Expanders (MX) and a serial EEPROM (L). Six I/O Expanders are used as the interface for the onboard hot-plug controllers (MI9). The SMbus address for the I/O Expander///// are fixed as x, x, x, x, x, x and x, respectively. Note: Hot-plug is not implemented when PESH is installed. The seven bits address for the selected EEPROM device is fixed at b_ by default. JTG Header The PESHG provides a JTG connector J for access to the PESHG JTG interface. The connector is a. x. mm pitch male -pin connector. Refer to Table. for the JTG onnector J pin out. ttention uttons JTG onnector J Pin Signal irection Pin Signal irection /TRST - Test reset Input TI - Test data Input TO - Test data Output TMS - Test mode select Input 9 TK - Test clock Input Table. JTG onnector Pin Out The PESHG features three attention buttons, shown in Table.9. Each button corresponds to a particular port and is used to initiate hot-swapping events. utton S S S S escription Port ttention utton Port ttention utton Port ttention utton Port ttention utton Table.9 ttention uttons EHG Eval oard Manual - May, 9

19 IT Installation of the EHG Eval oard Notes Miscellaneous Jumpers, Headers Miscellaneous Jumpers, Headers Ref. esignator Type efault escription W-W Header - Shunted -:.V source from Upstream Port (efault) -:.V source from external power connector W Header Shunted isable EEPROM Write protect feature (efault) S9[] Switch ON ON: Port, Force hot-plug controller on (efault) OFF: Port, Power Enable bit controls hot-plug controller S[] Switch ON ON: Port, Force hot-plug controller on (efault) OFF: Port, Power Enable bit controls hot-plug controller S[] Switch ON ON: Port, Force hot-plug controller on (efault) OFF: Port, Power Enable bit controls hot-plug controller S9[] Switch ON ON: Port, Force hot-plug controller on (efault) OFF: Port, Power Enable bit controls hot-plug controller W Header - Shunted -: Port, +V source from Upstream port (efault) -: Port, +V source from hot-plug controller W Header - Shunted -: Port, +V source from Upstream port (efault) -: Port, +V source from hot-plug controller W Header - Shunted -: Port, + source from Upstream port (efault) -: Port, + source from hot-plug controller W Header - Shunted -: Port, + source from Upstream port (efault) -: Port, + source from hot-plug controller W Header - Shunted -: Port, +.V source from Upstream port (efault) -: Port, +.V source from hot-plug controller W Header - Shunted -: Port, +.V source from Upstream port (efault) -: Port, +.V source from hot-plug controller W Header - Shunted -: Port, +.V source from Upstream port (efault) -: Port, +.V source from hot-plug controller W Header - Shunted -: Port, +.V source from Upstream port (efault) -: Port, +.V source from hot-plug controller W9 Header - Shunted -: Port, +.UX source from upstream port (efault) -: Port, +.V source from hot-plug controller W Header - Shunted -: Port, +.UX source from upstream port (efault) -: Port, +.V source from hot-plug controller W Header - Shunted -: Port, +.UX source from upstream port (efault) -: Port, +.V source from hot-plug controller W Header - Shunted -: Port, +.UX source from upstream port (efault) -: Port, +.V source from hot-plug controller Table. Miscellaneous Jumpers, Headers EHG Eval oard Manual - May, 9

20 IT Installation of the EHG Eval oard Notes LEs There are several LE indicators on the EHG which convey status feedback. description of each is provided in Table.. Location olor efinition S Green Port : Power-is-good Indicator S Green Port : Power-is-good Indicator S Green Port : Power-is-good Indicator S Green Port : Power-is-good Indicator S Green Port : Power Indicator S Green Port : Power Indicator S9 Green Port : Power Indicator S Green Port : Power Indicator S Yellow Port : ttention Indicator S Yellow Port : ttention Indicator S Yellow Port : ttention Indicator S Yellow Port : ttention Indicator S Green Port : ctivity Indicator S Green Port : ctivity Indicator S9 Green Port : ctivity Indicator S Green Port : ctivity Indicator S Green Port : ctivity Indicator S Green Port : Linkup Indicator S9 Green Port : Linkup Indicator S Green Port : Linkup Indicator S Green Port : Linkup Indicator S Green Port : Linkup Indicator S Red Port /: Power Fault Indicator S Red Port /: Power Fault Indicator S Green GPIO S Green GPIO S Green GPIO S Green GPIO S Green GPIO S Green GPIO S9 Green GPIO S Green GPIO Table. LE Indicators EHG Eval oard Manual - May, 9

21 IT Installation of the EHG Eval oard Notes PI Express onnectors Pin Side Side +V V power PRSNT# Hot-Plug presence detect +V V power +V V power RSV Reserved +V V power Ground Ground SMLK SMus clock JTG TK (Test lock) JTG i/f clk i/p SMT SMus ata JTG TI (Test ata Input) Ground JTG TO (Test ata Output) +.V.V power JTG TMS (Test Mode Select) 9 JTG TRST# (Test/Reset) resets JTG i/f +.V.V power.vaux.v auxiliary power +.V.V power WKE# Signal for Link reactivation PERST# Fundamental Reset Mechanical Key RSV Reserved Ground Ground REFLK+ REFLK Reference clock PETp Transmitter differential REFLK- (differential pair) PETn pair, Lane Ground Ground PERp Receiver differential PRSNT# Hot-Plug presence detect PERn pair, Lane Ground Ground 9 PETp Transmitter differential RSV Reserved PETn pair, Lane Ground Ground PERp Receiver differential Ground PERn pair, Lane PETp Transmitter differential Ground PETn pair, Lane Ground Ground PERp Receiver differential Ground PERn pair, Lane PETp Transmitter differential Ground PETn pair, Lane Ground 9 Ground PERp Receiver differential RSV Reserved PERn pair, Lane PRSNT# Hot-Plug presence detect Ground Ground RSV Reserved PETp Transmitter differential RSV Reserved Table. PI Express x onnector Pinout (Part of ) EHG Eval oard Manual - 9 May, 9

22 IT Installation of the EHG Eval oard Notes Pin Side Side PETn pair, Lane Ground Ground PERp Receiver differential Ground PERn pair, Lane PETp Transmitter differential Ground PETn pair, Lane Ground 9 Ground PERp Receiver differential Ground PERn pair, Lane PETp Transmitter differential Ground PETn pair, Lane Ground Ground PERp Receiver differential Ground PERn pair, Lane PETp Transmitter differential Ground PETn pair, Lane Ground Ground PERp Receiver differential PRSNT# Hot-Plug presence detect PERn pair, Lane 9 Ground Ground Table. PI Express x onnector Pinout (Part of ) Note: These x PI Express connectors comply with the PIe specification. ccording to the PI Express specification, the PRSNT# pin should be wired to the farthest available PRSNT# pin on the connector. In the EHG, all PRSNT# pins are tied together. This allows a board with a x or x width to be installed. EHG Eval oard Manual - May, 9

23 IT Installation of the EHG Eval oard Notes EHG oard Figure EHG Eval oard Manual - May, 9

24 IT Installation of the EHG Eval oard EHG Eval oard Manual - May, 9

25 hapter Software for the EHG Eval oard Notes Introduction This chapter discusses some of the main features of the available software to give users a better understanding of what can be achieved with the EHG evaluation board using the device management software. evice Management Software and related user documentation are available on a which is included in the Evaluation oard Kit. This information is also available on IT s FTP site. For more information, contact IT at ssdhelp@idt.com. evice Management Software The primary use of the evice Management Software package is to enable users of the evaluation board to access all the registers in the PESHG device. This access can be achieved using the PI Express in-band configuration cycles through the upstream port on the PESHG. This software also enables users to save a snapshot of the current register set into a dump file which can be used for debugging purposes. n export/import facility is also available to create and use onfiguration files which can be used to initialize the switch device with specific values in specific registers. conversion utility is also provided to translate a configuration file into an EEPROM programmable data structure. This enables the user to program an appropriate serial EEPROM with desirable register settings for the PESHG, and then to populate that EEPROM onto the Evaluation oard. It is also possible to program the EEPROM directly on the Evaluation oard using a feature provided by the software package. The front end of the evice Management Software is a user-friendly Graphical User Interface which allows the user to quickly read or write the registers of interest. The GUI also permits the user to run the software in simulation mode with no real hardware attached, allowing the creation of configuration files for the PESHG in the absence of the actual device. Much of the evice Management Software is written with device-independent and OS-independent code. The software will be guaranteed to work on Linux (/sys interface) and MS Windows XP. It may function flawlessly on various flavors of MS Windows, but may not be validated on all. The fact that the software is device-independent assures its scalability to future PIe parts from IT. Once users are familiar with the GUI, they will be able to use the same GUI on all PIe parts from IT. This software is customized for each device through an XML device description file which includes information on the number of ports, registers, types of registers, information on bit-fields within each register, etc. EHG Eval oard Manual - May, 9

26 IT Software for the EHG Eval oard Notes EHG Eval oard Manual - May, 9

27 hapter Schematics Notes Schematics EHG Eval oard Manual - May, 9

28 REVISIONS N REV ESRIPTION TE HNGE Y P-R. 9EPESHG EVL OR JULY JHU P_TOP_LEVEL_LOK_IGRM TITLE 9HPESHG Eval oard ONFIENTIL PROPERTY OF TEGRTE EVIE TEHNOLOGY,. SILVER REEK VLLEY R. SN JOSE, 9 OPYRIGHT () IT SIZE UTHOR RWG NO. SH- -- HEKE JHU.Le Tue Sep :: SHEET OF F P/N Y REV..

29 IOEXP_TTN PGE P_PN P_PN P_PN P_PN P_PFN P_PFN P_PFN P_PFN P_PEP P_PEP P_PEP P_PEP M_P_PERST_N M_P_PERST_N M_P_PERST_N M_P_PERST_N P_PN P_PN P_PN P_PN P_PFN P_PFN P_PFN P_PFN P_PEP P_PEP P_PEP P_PEP M_P_PERST_N M_P_PERST_N M_P_PERST_N M_P_PERST_N P_PN P_PN P_PN P_PN P_PFN P_PFN P_PFN P_PFN P_PEP P_PEP P_PEP P_PEP M_P_PERST_N M_P_PERST_N M_P_PERST_N M_P_PERST_N PERST_N RESET_POWER_ONN PGE PERST_N M_PERSTN PORT UPSTREM P_REFLKP PERST_N P_REFLKN PGE M_SSMLK M_SSMT P_WKE_N P_PETP<..> P_PETN<..> P_PERP<..> P_PERN<..> P_PETP<..> P_PETN<..> P_PERP<..> P_PERN<..> M_SSMLK M_SSMT P_PETP<:> P_PETN<:> P_PERP<:> P_PERN<:> P_PETP<:> P_PETN<:> P_PERP<:> P_PERN<:> M_PERSTN M_SL M_S M_IOTN M_SL M_S M_IOTN M_SSMLK M_SSMT M_PERSTN PLKP PLKN PLKP PLKN PEREFLKP PEREFLKN PEREFLKP PEREFLKN PEREFLKP PEREFLKN PEREFLKP PEREFLKN P_PETP<..> P_PETN<..> P_PERP<..> P_PERN<..> P_PETP<..> P_PETN<..> P_PERP<..> P_PERN<..> UT_TOP PGE P_WKE_N P_REFLKP P_REFLKN PLKP PLKN PLKP PLKN PEREFLKP PEREFLKN PEREFLKP PEREFLKN PEREFLKP PEREFLKN PEREFLKP PEREFLKN P_PETP<..> P_PETN<..> P_PERP<..> P_PERN<..> P_PETP<..> P_PETN<..> P_PERP<..> P_PERN<..> P_PETP<..> P_PETN<..> P_PERP<..> P_PERN<..> P_PETP<..> P_PETN<..> P_PERP<..> P_PERN<..> M_SL M_S M_IOTN P_REFLKP P_REFLKN PLKP PLKN PLKP PLKN PEREFLKP PEREFLKN PEREFLKP PEREFLKN PEREFLKP PEREFLKN PEREFLKP PEREFLKN LOK_TREE PGE M_SSMLK M_SSMT P_PWRGN P_PWRGN P_PWRGN P_PWRGN P_REFLKP P_REFLKN P_REFLKP P_REFLKN P_REFLKP P_REFLKN P_REFLKP P_REFLKN M_PERSTN M_SSMLK M_SSMT P_PETP<:> P_PETN<:> P_PERP<:> P_PERN<:> P_PETP<:> P_PETN<:> P_PERP<:> P_PERN<:> P_WKE_N PGE 9 P_PETP<:> P_PETN<:> P_PERP<:> P_PERN<:> P_PETP<:> P_PETN<:> P_PERP<:> P_PERN<:> PORT_WKE P_WKE_N P_WKE_N P_WKE_N P_WKE_N M_SL M_S M_IOTN P_PWRGN P_PWRGN P_PWRGN P_PWRGN P_REFLKP P_REFLKN P_REFLKP P_REFLKN P_REFLKP P_REFLKN P_REFLKP P_REFLKN P_PWRGN P_PWRGN P_PWRGN P_PWRGN P_WKE_N P_WKE_N P_WKE_N P_WKE_N S_PORTS PGE P_PWRGN P_PWRGN P_PWRGN P_PWRGN P_REFLKP P_REFLKN P_REFLKP P_REFLKN P_REFLKP P_REFLKN P_REFLKP P_REFLKN M_PERSTN M_SSMLK M_SSMT P_PETP<..> P_PETN<..> P_PERP<..> P_PERN<..> P_PETP<..> P_PETN<..> P_PERP<..> P_PERN<..> P_PETP<..> P_PETN<..> P_PERP<..> P_PERN<..> P_PETP<..> P_PETN<..> P_PERP<..> P_PERN<..> P_WKE_N P_WKE_N P_WKE_N P_WKE_N TITLE 9HPESHG Eval oard TOP LEVEL LOK IGRM ONFIENTIL PROPERTY OF TEGRTE EVIE TEHNOLOGY,. SILVER REEK VLLEY RO. SN JOSE, 9 OPYRIGHT () IT SIZE RWG NO. SH- -- UTHOR HEKE Y JHU.Le Mon ug :: SHEET OF F P/N REV..

30 LNE REVERSE FOR IMPROVE RG PGE PGE PGE OWNSTREM PORTS LNE REVERSE FOR IMPROVE RG LL PS RE TO E PLE T THE SSOITE ONNETORS PGE Wed Sep :: SHEET OF. --.Le JHU SH- 9HPESHG Eval oard 9 9 Y V U Y V U E E9 E E F F9 F F Y V U Y V U 9 9 E9 E E E 9 F G J K F G J K E E E9 E F F F9 F E E E E F F F F 9 9 F G J K F G J K P_PERN<:> PEREFLKP PEREFLKP PEREFLKN PEREFLKP PEREFLKN ^ _P_PETP _P_PETP _P_PETP _P_PETP _P_PETN _P_PETN _P_PETN _P_PETN _P_PETP _P_PETP _P_PETP _P_PETP _P_PETN _P_PETN _P_PETN _P_PETN _P_PETP _P_PETP _P_PETP _P_PETP _P_PETN _P_PETN _P_PETN _P_PETN P_PERP<> P_PERP<> P_PERP<> P_PERP<> P_PERN<> P_PERN<> P_PERN<> P_PERN<> P_PERP<> P_PERP<> P_PERP<> P_PERP<> P_PERN<> P_PERN<> P_PERN<> P_PERN<> P_PERP<> P_PERP<> P_PERP<> P_PERP<> P_PERN<> P_PERN<> P_PERN<> P_PERN<> 9 9 PEREFLKN v ^ PEREFLKP P_PETN<:> P_PERP<:> P_PETP<:> ^ P_PETN<> P_PETN<> P_PETP<> P_PETP<> P_PETN<> P_PETN<> P_PETP<> P_PETP<> P_PETP<> M_SSMT M_SL P_PETN<:> P_PETP<:> P_PETN<> P_PETP<> P_PETN<> P_PETP<> P_PETN<> P_PETP<> P_PETN<> P_PETP<> P_PETN<> P_PETP<> P_PETP<> P_PETN<> P_PETN<> P_PETP<> v P_PERP<:> P_PERP<:> P_PERN<:> P_PERP<:> P_PETP<:> P_PERN<:> P_PERP<:> P_PETN<:> P_PETP<:> M_IOTN M_SSMLK M_PERSTN M_S PEREFLKN PLKP PLKN PLKP PLKN ^ ^ ^ v ^ v v ^ ^ v P_PETP<:> P_PERN<:> P_PERN<:> P_PETP<:> P_PETN<:> ^ v ^ UT TOP P_PETN<> P_PETN<:> P_PETN<:> ^ v v ^ ^ v v ^ v ^ v ^ v ^ v ^ v ^ v ^ v v v ^ v ^ v ^ v ^ v ^ v ^ ^ v ^ v ^ v ^ ^ v v ^ ^ ^ ^ v ^ v ^ ^ ^ v ^ v P_PERP<:> P_PERN<:> ^ IT TITLE RWG NO. UTHOR HEKE Y OPYRIGHT () SIZE REV. F P/N SILVER REEK VLLEY RO. SN JOSE, 9 ONFIENTIL PROPERTY OF TEGRTE EVIE TEHNOLOGY,. UT_POWER PORT PORT PETP PETP PETP PETP PETN PETN PETN PETN PETP PETP PETP PETP PETN PETN PETN PETN PERN PERN PERN PERN PERP PERP PERP PERP PERN PERN PERN PERN PERP PERP PERP PERP PORT PORT PORT PORT 9 PE9TP PE9TP PE9TP PE9TP PE9TN PE9TN PE9TN PE9TN PETP PETP PETP PETP PETN PETN PETN PETN PETP PETP PETP PETP PETN PETN PETN PETN PETP PETP PETP PETP PETN PETN PETN PETN PE9RN PE9RN PE9RN PE9RN PE9RP PE9RP PE9RP PE9RP PERN PERN PERN PERN PERP PERP PERP PERP PERN PERN PERN PERN PERP PERP PERP PERP PERN PERN PERN PERN PERP PERP PERP PERP UT_ IO IO IO IO UT_SERIL_PORTS P_PETP<..> P_PETN<..> P_PERP<..> P_PERN<..> P_PERN<..> P_PERP<..> P_PETN<..> P_PETP<..> P_PERN<..> P_PERP<..> P_PETN<..> P_PETN<..> P_PETP<..> P_PERN<..> P_PERP<..> P_PETP<..> UT_ONTROL_MIS M_IOTN M_SSMLK M_SSMT M_PERSTN M_S M_SL PEREFLKP PEREFLKN PLKP PLKN PLKP PLKN PEREFLKP PEREFLKN PEREFLKP PEREFLKN PEREFLKP PEREFLKN

31 SWMOE_ SWMOE_ SWMOE_ SWMOE_ POS ESRIPTION SILKSREEN LEL: SILKSREEN LEL: SWITH S SPRE LKMOE_ LKMOE_ LKMOE_ POS ESRIPTION SWITH S HNGE RESISTORS THIS SETION TO K FOR G UT RSTHLT Wed Sep :: SHEET OF. --.Le JHU SH- 9HPESHG Eval oard PEREFLKP ^ ^ PLKN SSMR MSMR PEREFLKP PEREFLKN PEREFLKN PEREFLKP SWMOE_ SWMOE_ SWMOE_ SWMOE_ SSMR SSMR RSTHLT P9MERGE PMERGE PMERGE PMERGE PMERGE PLKP PMERGE PLKP PLKN M_IOTN GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO PEREFLKP PEREFLKN PEREFLKN REFLKM_GLKFSEL LKMOE_ LKMOE_ LKMOE_ ^ R9 ^ R R R9 R R R R W W W W9 TP TP TP TP TP TP9 TP TP TP TP TP TP TP TP R R R S W9 W9 W R S R R R R R R9 R R R R S9 S S S S S S R9 R9 R R R9 R9 R99 R R9 R9 R9 R9 R9 R R R R99 R R9 R9 W W W W R R R R S W W R R R R R 9 U 9 U 9 J R9 R U W R R W W W 9 R9 SM ^ M_PERSTN SSMT SSMT SSMLK SSMLK M_SSMT ^ M_SSMLK ^ R SM M_TK JTG_RST_N K _V K M_TI M_TO M_TMS UT_JTG_TK UT_JTG_TMS UT_JTG_TO UT_JTG_TO UT_JTG_TI UT_SMLK K K R K SM R R ^ ^ EPM_ EPM_ EPM_.K _V SM R K _V R R SM UT ONTROL N MIS ^ K K K _V ^ ^ ^ SM R SM UT_V_IO _V ^ ^ M_S M_SL ^ R SM ^ ^ K K K K K UT_V_IO R SM _V UT_V_IO GRN GRN GRN GRN GRN GRN YEL YEL YEL YEL YEL YEL YEL YEL YEL YEL YEL YEL YEL YEL SM GRN GRN R SM SM R SM R R SM SM R UT_SMT K UT_JTG_TRST UT_JTG_TI UT_JTG_TRST UT_JTG_TK UT_JTG_TMS NP NP UT_V_IO IT TITLE RWG NO. UTHOR HEKE Y OPYRIGHT () SIZE REV. F P/N SILVER REEK VLLEY RO. SN JOSE, 9 ONFIENTIL PROPERTY OF TEGRTE EVIE TEHNOLOGY,. IO SM_SW S S S S S S S S TMENP_VSS_ SSMR_VSS_ QTESTMOE_VSS_ MSMR_VSS_ GPIO_VSS_ GPIO_VSS_ GPIO_VSS_ GPIO9_VSS_9 VSS_REFRES VSS_REFRES VSS_REFRES VSS_REFRES VSS_REFRES VSS_REFRES VSS_REFRES VSS_REFRES VSS_REFRES VSS_REFRES9 VSS_REFRES VSS_REFRES PEREFLKP_N_ PEREFLKN_N_ PEREFLKN_N_ PEREFLKP_N_ SWMOE SWMOE SWMOE SWMOE SSMT SSMLK SSMR SSMR RSTHLT VSS_REFRESPLL PERSTN P9MERGEN PMERGEN PMERGEN PMERGEN PMERGEN VSS_PLKP VSS_PLKN PMERGEN VSS_PLKP VSS_PLKN MSMT MSMLK JTG_TRST_N JTG_TMS JTG_TO JTG_TI JTG_TK GPIO_VSS GPIO_VSS GPIO9_VSS GPIO_VSS GPIO_VSS GPIO_VSS GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO PEREFLKN_GLKP PEREFLKN_GLKP PEREFLKP_GLKN PEREFLKP_GLKN REFLKM_GLKFSEL VSS_LKMOE LKS_LKMOE LKUS_LKMOE N_ N_ SM_SW S S S S S S S S IO IO TXPWRG Vccb N OE N Vcca TXPWRG Vccb N OE N Vcca JTG HEER 9 L SL S WP V IO

32 LNE REVERSE FOR IMPROVE RG LL PS RE TO E PLE T THE SSOITE ONNETORS UPSTREM PORTS OWNSTREM PORTS LNE REVERSE FOR IMPROVE RG Wed Sep :: SHEET OF. --.Le JHU SH- 9HPESHG Eval oard M N R T M N R T V W V W E E E E E E E E M N R T M N R T V W V W E F H J L M P R E F H J L M P R L M P R L M P R E F H J E F H J P_PERN<> P_PERN<> P_PERN<> P_PERN<> P_PERP<> P_PERP<> P_PERP<> P_PERP<> P_PERN<> P_PERN<> P_PERN<> P_PERN<> P_PERP<> P_PERP<> P_PERP<> P_PERP<> _P_PETP _P_PETP _P_PETP _P_PETP _P_PETP _P_PETP _P_PETP _P_PETP _P_PETN _P_PETN _P_PETN _P_PETN _P_PETN _P_PETN _P_PETN _P_PETN P_PERP<> P_PERP<> P_PERP<> P_PERP<> P_PERN<> P_PERN<> P_PERN<> P_PERN<> P_PERP<> P_PERP<> P_PERP<> P_PERP<> P_PERN<> P_PERN<> P_PERN<> P_PERN<> P_PERP<> P_PERP<> P_PERP<> P_PERP<> P_PERN<> P_PERN<> P_PERN<> P_PERN<> P_PERP<> P_PERP<> P_PERP<> P_PERP<> P_PERN<> P_PERN<> P_PERN<> P_PERN<> _P_PETP _P_PETP _P_PETP _P_PETP _P_PETN _P_PETN _P_PETN _P_PETN _P_PETP _P_PETP _P_PETP _P_PETP _P_PETN _P_PETN _P_PETN _P_PETN _P_PETP _P_PETP _P_PETP _P_PETP _P_PETN _P_PETN _P_PETN _P_PETN _P_PETP _P_PETP _P_PETP _P_PETP _P_PETN _P_PETN _P_PETN _P_PETN P_PETN<> P_PETP<> P_PETN<> P_PETP<> P_PETN<> P_PETP<> P_PETN<> P_PETP<> P_PETN<> P_PETP<> P_PETN<> P_PETP<> P_PETN<> P_PETP<> P_PETN<> P_PETP<> P_PETN<> P_PETP<> P_PETN<> P_PETP<> P_PETN<> P_PETP<> P_PETN<> P_PETP<> P_PETN<:> P_PETN<> P_PETP<> P_PETN<> P_PETP<> P_PETN<> P_PETP<> P_PETN<> P_PETP<> P_PERN<:> P_PERP<:> ^ P_PERP<:> P_PERN<:> ^ ^ P_PETN<:> P_PETP<:> UT SERIL PORTS ^ ^ ^ ^ ^ ^ ^ ^ P_PETP<:> P_PETP<> P_PETP<> P_PETP<> P_PETP<> P_PETN<> P_PETN<> P_PETN<> P_PETN<> P_PETN<:> P_PETN<:> P_PETP<:> P_PETP<> P_PETP<> P_PETP<> P_PETP<> P_PETN<> P_PETN<> P_PETN<> P_PETN<> P_PERP<:> P_PERP<:> P_PERN<:> ^ ^ ^ ^ P_PETP<:> ^ P_PERN<:> IT TITLE RWG NO. UTHOR HEKE Y OPYRIGHT () SIZE REV. F P/N SILVER REEK VLLEY RO. SN JOSE, 9 ONFIENTIL PROPERTY OF TEGRTE EVIE TEHNOLOGY,. PORT PORT PORT PORT PERN PERN PERN PERN PERP PERP PERP PERP PERN PERN PERN PERN PERP PERP PERP PERP PERN PERN PERN PERN PERP PERP PERP PERP PERN PERN PERN PERN PERP PERP PERP PERP PETP PETP PETP PETP PETN PETN PETN PETN PETP PETP PETP PETP PETN PETN PETN PETN PETP PETP PETP PETP PETN PETN PETN PETN PETP PETP PETP PETP PETN PETN PETN PETN PORT PORT PERP PERP PERP PERP PERN PERN PERN PERN PERP PERP PERP PERP PERN PERN PERN PERN PETP PETP PETP PETP PETP PETP PETP PETP PETN PETN PETN PETN PETN PETN PETN PETN

33 Wed Sep :: SHEET OF. --.Le JHU SH- 9HPESHG Eval oard H H H H J J J J K K K K L L L L M M M M N N N N P P P P R R R R T T T T U U U U V V V V W W W W E F F G G H9 H H H H H J9 J J J J J N N N P9 P P P V9 V V V V V W9 W W W W W Y Y 9 F F9 F G G9 G L9 L L L M9 N9 T9 T T U U U Y Y Y9 9 F F G G K9 K K K K K L R9 R R R T T T Y9 Y E.UF UF UT_V_IO UT POWER SUPPLY UT_VPEH UT_VPE UT_VPET UT_VORE UT_VORE UF UF.UF UT_V_IO UT_VPEH UF UF UF.UF UT_VPET UT_VPE UF UF.UF.UF IT TITLE RWG NO. UTHOR HEKE Y OPYRIGHT () SIZE REV. F P/N SILVER REEK VLLEY RO. SN JOSE, 9 ONFIENTIL PROPERTY OF TEGRTE EVIE TEHNOLOGY,. power VIO_ VIO_ VPET_ VPET_ VPET_ VPET_ VPET_9 VPET_ VPET_ VPET_ VPET_ VPET_ VPET_ VPET_ VPET_ VPET_ VPET_9 VPET_ VPET_ VPET_ VPET_ VPET_ VPET_ VPET_ VPET_ VPET_ VPEH_ VPEH_ VPEH_ VPEH_ VPEH_9 VPEH_ VPEH_ VPEH_ VPEH_ VPEH_ VPEH_ VPEH_ VPEH_ VPEH_ VPEH_9 VPEH_ VPEH_ VPEH_ VPEH_ VPEH_ VPEH_ VPEH_ VPEH_ VPEH_ VPE_ VPE_ VPE_ VPE_ VPE_ VPE_ VPE_ VPE_ VPE_ VPE_9 VPE_ VPE_ VPE_ VPE_ VPE_ VPE_ VPE_ VPE_ VPE_ VPE_9 VPE_ VPE_ VPE_ VPE_ VPE_ VPE_ VPE_ VPE_ VPE_ VPE_9 VPE_ VPE_ VPE_ VPE_ VPE_ VPE_ VPE_ VPE_ VPE_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_9 VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VORE_ VORE_ VORE_ VORE_ VORE_ VORE_ VORE_ VORE_ VORE_9 VORE_ VORE_ VORE_ VORE_ VORE_ VORE_ VORE_ VORE_ VORE_ VORE_9 VORE_ VORE_ VORE_ VORE_ VORE_ VORE_ VORE_ VORE_ VORE_ VORE_9 VORE_ VORE_ VORE_ VORE_ VORE_ VORE_ VORE_ VORE_ VORE_ VORE_9 VORE_ VORE_ VORE_ VORE_ VORE_ VORE_ VORE_ VORE_ VORE_

34 Wed Sep :: SHEET OF. --.Le JHU SH- 9HPESHG Eval oard K E E E E E F F F F F F E E E E E9 E E E E E F F F F F F G G G G G G G G G G G H H H H H H H H H H H H9 J J J J J J J J9 K K K K K K K K K K K9 L L L L L L L L L L L L9 M M M M M M M M M M M9 N N N N N N N N N N9 P P P P P P P P P P P P9 R R R R R R R R9 T T T T T T T T T T T T9 U U U U U U U9 U U U U U U U U9 V V V V V V V V9 W W W W W W W W W W W W9 Y Y Y Y Y Y Y Y Y Y UT GROUN IT TITLE RWG NO. UTHOR HEKE Y OPYRIGHT () SIZE REV. F P/N SILVER REEK VLLEY RO. SN JOSE, 9 ONFIENTIL PROPERTY OF TEGRTE EVIE TEHNOLOGY,. VSS_ VSS_ VSS_9 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_9 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_9 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_9 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_9 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_9 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_99 VSS_9 VSS_9 VSS_9 VSS_9 VSS_9 VSS_9 VSS_9 VSS_9 VSS_9 VSS_9 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_9 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_9 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_9 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_9 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_9 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_9 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_9 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_9 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_99 VSS_9 VSS_9 VSS_9 VSS_9 VSS_9 VSS_9 VSS_9 VSS_9 VSS_9 VSS_9 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_9 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_9 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_9 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_9 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_9 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_9 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_9 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_

35 _V PF X MHZ PPM PF ^ P_REFLKP ^ P_REFLKN _V F OHM M R.UF.UF UF 9.UF R R PLE NER U SM SM W W v v 9v ^ 9v ^ 9v ^ 9v ^ 9v 9v ^ ^ REF_LKP REF_LKN P_PWRGN P_PWRGN P_PWRGN P_PWRGN M_SSMLK M_SSMT LOK_S_GREF P_REFLKP P_REFLKN PGE 9 REF_LKP REF_LKN P_PWRGN P_PWRGN P_PWRGN P_PWRGN M_SSMLK M_SSMT P_REFLKP P_REFLKN P_REFLKP P_REFLKN P_REFLKP P_REFLKN PEREFLKP PEREFLKN PEREFLKP PEREFLKN PEREFLKP PEREFLKN PEREFLKP PEREFLKN P_REFLKP P_REFLKN P_REFLKP P_REFLKN P_REFLKP P_REFLKN P_REFLKP P_REFLKN PEREFLKP PEREFLKN PEREFLKP PEREFLKN PEREFLKP PEREFLKN PEREFLKP PEREFLKN ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 9v 9v 9v 9v 9v 9v 9v 9v 9v 9v 9v 9v 9v 9v 9v 9v S SM_SW S S S S S S S S R R R R NP NP K NP R R K NP NP R TP YEL REF_SEL FSEL FSEL REF_EN MR_NOE SS_MOE PLL_YPSS R9 9 9 IS XTL_ V V XTL_ V V REF_ V REF_SEL FSEL FSEL OE_REF MR_nOE IREF SSM YPSS P REF_ U Q nq Q nq Q nq Q nq N N N N 9 TP YEL SR_R_T_LKP SR_R_T_LKN PLE R/R NER U ONR_REFLKP ONR_REFLKN R R R R R R R R R R PLE NER U G_REF_LKP G_REF_LKN LOK_UT_GREF M_SSMLK M_SSMT G_REF_LKP G_REF_LKN PGE PLKP PLKN PLKP PLKN PLKP PLKN PLKP PLKN ^ ^ ^ ^ v v v v J9 ONNSM R_T_LKN 9- NOTE: LOK GENERTOR EFULT WORKG MOE: RYSTL PUT NO SPRE MHZ PUT J ONNSM 9- R_T_LKP ONFIENTIL PROPERTY OF TEGRTE EVIE TEHNOLOGY,. SILVER REEK VLLEY RO. SN JOSE, 9 OPYRIGHT () IT TITLE 9HPESHG LOKS SIZE RWG NO. SH- Eval oard -- UTHOR HEKE Y JHU.Le Tue ug 9 :: SHEET OF F P/N REV..

36 _V OHM F. R. M 9 R R R R9 R.UF UF.UF SILKSREEN LEL: SWITH S POS ESRIPTION PLK_EN PLK_EN PLK_EN PLK_EN ^ ^ ^ ^ ^ ^ ^ ^ M_SSMLK M_SSMT S SM_SW S S S S S S S S REF_LKP REF_LKN P_PWRGN P_PWRGN P_PWRGN P_PWRGN NP NP R R PLK_EN PLK_EN PLK_EN PLK_EN K K K K 9 9 V V V SR_ SR_# OE# OE# OE# OE# OE# OE# OE# OE# U9 IS9 OE_V= IFF_STOP P HIGH_W# OE_V YPSS#/PLL SLK ST SR_IV# V V V IF_ IF_# IF_ IF_# IF_ IF_# IF_ IF_# IF_ IF_# IF_ IF_# IF_ IF_# IF_ IF_# LOK IREF 9 9 PE_REFLKP PE_REFLKN PE_REFLKP PE_REFLKN SR_P_LKP SR_P_LKN SR_P_LKP SR_P_LKN SR_P_LKP SR_P_LKN SR_P_LKP SR_P_LKN PE_REFLKP PE_REFLKN PE_REFLKP PE_REFLKN TP YEL R R R R R R R R R R R R R R9 R R R PEREF_LKP PEREF_LKN PEREF_LKP PEREF_LKN PEREF_LKP PEREF_LKN PEREF_LKP PEREF_LKN R R R R R R9 R R R R R R9 R R R R P_REFLKP P_REFLKN P_REFLKP P_REFLKN P_REFLKP P_REFLKN P_REFLKP P_REFLKN 9 PEREFLKP PEREFLKN PEREFLKP PEREFLKN PEREFLKP PEREFLKN PEREFLKP PEREFLKN ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ FOR GEN: - REPLE,,,N WITH R - REPLE R, R,R,N R9 WITH R - REMOVE R, R, R N R _V SILKSREEN LEL: W9 HIGHW W G_OE W YPSS W SR_IV R W9 W G_OE R R W G_HIGHW W G_SR_IV R SM SM SM SM G_YPSS ONFIENTIL PROPERTY OF TEGRTE EVIE TEHNOLOGY,. SILVER REEK VLLEY RO. SN JOSE, 9 OPYRIGHT () IT TITLE 9HPESHG SH- Eval oard LOK UFFER S, G SIZE RWG NO. -- UTHOR HEKE Y JHU.Le Tue ug 9 :: SHEET 9 OF F P/N REV..

37 J ONNSM R R9 R _V OHM F. M R9. R 9- J ONNSM K K K R R R R.UF UF.UF 9- J ONNSM SILKSREEN LEL: SWITH S POS ESRIPTION SPRELK_ SPRELK_ PLKEN PLKEN SPRE SPRE SPRE SPRE SILKSREEN LEL: W HIGHW W G_OE W YPSS W SR_IV ^ ^ ^ ^ M_SSMLK M_SSMT S SM_SW S S S S S S S S S S S S S S S S G_REF_LKP G_REF_LKN 9 _V R NP NP W W G_OE R R W R R SPRE_LK SPRE_LK PLK_EN PLK_EN SM W G_SR_IV R SM SM SM K K K K G_HIGHW G_YPSS 9 9 V V V SR_ SR_# OE# OE# OE# OE# OE# OE# OE# OE# U IS9 OE_V= IFF_STOP P HIGH_W# OE_V YPSS#/PLL SLK ST SR_IV# V V V IF_ IF_# IF_ IF_# IF_ IF_# IF_ IF_# IF_ IF_# IF_ IF_# IF_ IF_# IF_ IF_# LOK IREF 9 9 P_LKP P_LKN P_LKP P_LKN TP YEL R R R R R R R R R R9 R R9 R R R R R FOR G EVIE R-R HNGE TO OHM FOR G EVIE REMOVE R-R R R R R R9 R R R R R R R R R R R ONFIENTIL PROPERTY OF TEGRTE EVIE TEHNOLOGY,. SILVER REEK VLLEY RO. SN JOSE, 9 OPYRIGHT () IT TITLE PLKP PLKN PLKP PLKN 9HPESHG SH- Eval oard ^ ^ ^ ^ LOK UFFER G SIZE RWG NO. -- UTHOR HEKE Y 9- J ONNSM 9- J ONNSM 9- J ONNSM JHU.Le Tue ug 9 :: SHEET OF F P/N 9- REV..

38 SILKSREEN LEL: POS SWITH J ESRIPTION SMT SMLK N ^ ^ _V K K J IO ^ ^ ^ ^ R R9 M_SSMLK M_SSMT P_PERP<:> P_PERN<:> P_PERP<:> P_PERN<:> NP NP ^ _VUX R R UF P V P_PERP<> P_PERN<> NP P_PERP<> P_PERN<> NP P_PERP<> P_PERN<> P_WKE_N P_PERP<> P_PERN<> P_PERP<> P_PERN<> P_PERP<> P_PERN<> P_PERP<> P_PERN<> P_PERP<> P_PERN<> V UF R R _V PIE ON_PRESENT_N PIe x +V +V RSV SMLK SMT +.V JTG_TRSTN.VUX WKE# RSV PETP PETN PRSTN# PETP PETN PETP PETN PETP PETN RSV PRSTN# PETP PETN PETP PETN PETP PETN PETP PETN PRSTN# EGE PRSTN# +V +V JTG_TK JTG_TI JTG_TO JTG_TMS +.V +.V PERST# REFLK+ REFLK- PERP PERN RSV PERP PERN PERP PERN PERP PERN RSV RSV PERP PERN PERP PERN PERP PERN PERP PERN _V V UF P V UF PERST_N P_REFLKP P_REFLKN P_PETP<> P_PETN<> P_PETP<> P_PETN<> P_PETP<> P_PETN<> P_PETP<> P_PETN<> P_PETP<> P_PETN<> P_PETP<> P_PETN<> P_PETP<> P_PETN<> P_PETP<> P_PETN<> PORT N LNE SSIGNMENT SHOU E VERIFIE ^ ^ ^ P_PETP<:> P_PETN<:> P_PETP<:> P_PETN<:> ^ ^ ^ ^ P PORT N LNE SSIGNMENT SHOU E VERIFIE SILKSREEN LEL: ONETOR P PORT PIE X(,,,) ONFIENTIL PROPERTY OF TEGRTE EVIE TEHNOLOGY,. SILVER REEK VLLEY RO. SN JOSE, 9 OPYRIGHT () IT TITLE 9HPESHG SH- Eval oard ONNETOR EGE US PIE X SIZE RWG NO. -- UTHOR HEKE Y JHU.Le Tue ug 9 :: SHEET OF F P/N REV..

39 v v v v v v v v v v v ^ ^ IO v ^ v ^ v ^ v ^ v ^ v ^ v ^ v ^ M_SSMLK M_SSMT P_REFLKP P_REFLKN P_PN P_WKE_N M_PERSTN M_P_PERST_N P_PETP<:> P_PETN<:> v ^ P_PERP<:> v ^ P_PERN<:> M_SSMLK M_SSMT P_REFLKP P_REFLKN P_PN P_WKE_N M_PERSTN M_P_PERST_N P_PETP<..> P_PETN<..> P_PERP<..> P_PERN<..> PORT S_X_FEMLE PGE v ^ v ^ v ^ v ^ v ^ v v v v ^ ^ ^ ^ P_REFLKP P_REFLKN P_PN P_WKE_N M_PERSTN M_P_PERST_N P_PETP<:> P_PETN<:> P_PERP<:> P_PERN<:> M_SSMLK M_SSMT P_REFLKP P_REFLKN P_PN P_WKE_N M_PERSTN M_P_PERST_N P_PETP<..> P_PETN<..> P_PERP<..> P_PERN<..> PORT S_X_FEMLE PGE v v v v v v ^ ^ ^ ^ ^ ^ P_PFN P_PFN P_PWRGN P_PWRGN P_PEP P_PEP HOT_SWP_PORT P_PFN P_PFN P_PWRGN P_PWRGN P_PEP P_PEP PGE v ^ v ^ v ^ v ^ v ^ v ^ v ^ v v ^ ^ P_REFLKP P_REFLKN P_PN P_WKE_N M_PERSTN M_P_PERST_N P_PETP<:> P_PETN<:> P_PERP<:> P_PERN<:> M_SSMLK M_SSMT P_REFLKP P_REFLKN P_PN P_WKE_N M_PERSTN M_P_PERST_N P_PETP<..> P_PETN<..> P_PERP<..> P_PERN<..> PORT S_X_FEMLE PGE v v v v v v ^ ^ ^ ^ ^ ^ P_PFN P_PFN P_PWRGN P_PWRGN P_PEP P_PEP HOT_SWP_PORT P_PFN P_PFN P_PWRGN P_PWRGN P_PEP P_PEP PGE v ^ v ^ v ^ v ^ v v v v v ^ ^ ^ ^ ^ P_REFLKP P_REFLKN P_PN P_WKE_N M_PERSTN M_P_PERST_N P_PETP<:> P_PETN<:> P_PERP<:> P_PERN<:> M_SSMLK M_SSMT P_REFLKP P_REFLKN P_PN P_WKE_N M_PERSTN M_P_PERST_N P_PETP<..> P_PETN<..> P_PERP<..> P_PERN<..> PORT S_X_FEMLE PGE TITLE 9HPESHG Eval oard PIE OWNSTREM PORTS - ONFIENTIL PROPERTY OF TEGRTE EVIE TEHNOLOGY,. SILVER REEK VLLEY RO. SN JOSE, 9 OPYRIGHT () IT SIZE RWG NO. SH- -- UTHOR HEKE Y JHU.Le Wed ug :: SHEET OF F P/N REV..